; LLVM IR from sejja/3D-Software-Rasterizer :: Rasterizer/Engine/Math/Vector4.ll (ZNK7Vector45CrossERKS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Vector4 = type { %union.anon }
%union.anon = type { [4 x float] }
%struct.anon = type { float, float, float, float }

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK7Vector45CrossERKS_(ptr dead_on_unwind noalias writable sret(%class.Vector4) align 4 %0, ptr noundef nonnull align 4 dereferenceable(16) %1, ptr noundef nonnull align 4 dereferenceable(16) %2) #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %7 = load ptr, ptr %5, align 8
  %8 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %9 = getelementptr inbounds %struct.anon, ptr %8, i32 0, i32 1
  %10 = load float, ptr %9, align 4, !tbaa !9
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  %12 = getelementptr inbounds %class.Vector4, ptr %11, i32 0, i32 0
  %13 = getelementptr inbounds %struct.anon, ptr %12, i32 0, i32 2
  %14 = load float, ptr %13, align 4, !tbaa !9
  %15 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %16 = getelementptr inbounds %struct.anon, ptr %15, i32 0, i32 2
  %17 = load float, ptr %16, align 4, !tbaa !9
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = getelementptr inbounds %class.Vector4, ptr %18, i32 0, i32 0
  %20 = getelementptr inbounds %struct.anon, ptr %19, i32 0, i32 1
  %21 = load float, ptr %20, align 4, !tbaa !9
  %22 = fmul float %17, %21
  %23 = fneg float %22
  %24 = call float @llvm.fmuladd.f32(float %10, float %14, float %23)
  %25 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %26 = getelementptr inbounds %struct.anon, ptr %25, i32 0, i32 2
  %27 = load float, ptr %26, align 4, !tbaa !9
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = getelementptr inbounds %class.Vector4, ptr %28, i32 0, i32 0
  %30 = getelementptr inbounds %struct.anon, ptr %29, i32 0, i32 0
  %31 = load float, ptr %30, align 4, !tbaa !9
  %32 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %33 = getelementptr inbounds %struct.anon, ptr %32, i32 0, i32 0
  %34 = load float, ptr %33, align 4, !tbaa !9
  %35 = load ptr, ptr %6, align 8, !tbaa !5
  %36 = getelementptr inbounds %class.Vector4, ptr %35, i32 0, i32 0
  %37 = getelementptr inbounds %struct.anon, ptr %36, i32 0, i32 2
  %38 = load float, ptr %37, align 4, !tbaa !9
  %39 = fmul float %34, %38
  %40 = fneg float %39
  %41 = call float @llvm.fmuladd.f32(float %27, float %31, float %40)
  %42 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %43 = getelementptr inbounds %struct.anon, ptr %42, i32 0, i32 0
  %44 = load float, ptr %43, align 4, !tbaa !9
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %class.Vector4, ptr %45, i32 0, i32 0
  %47 = getelementptr inbounds %struct.anon, ptr %46, i32 0, i32 1
  %48 = load float, ptr %47, align 4, !tbaa !9
  %49 = getelementptr inbounds %class.Vector4, ptr %7, i32 0, i32 0
  %50 = getelementptr inbounds %struct.anon, ptr %49, i32 0, i32 1
  %51 = load float, ptr %50, align 4, !tbaa !9
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = getelementptr inbounds %class.Vector4, ptr %52, i32 0, i32 0
  %54 = getelementptr inbounds %struct.anon, ptr %53, i32 0, i32 0
  %55 = load float, ptr %54, align 4, !tbaa !9
  %56 = fmul float %51, %55
  %57 = fneg float %56
  %58 = call float @llvm.fmuladd.f32(float %44, float %48, float %57)
  call void @_ZN7Vector4C1Effff(ptr noundef nonnull align 4 dereferenceable(16) %0, float noundef %24, float noundef %41, float noundef %58, float noundef 0.000000e+00)
  ret void
}

declare void @_ZN7Vector4C1Effff(ptr, float, float, float, float)

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Vector4 = type { %union.anon }
%union.anon = type { [4 x float] }

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK7Vector45CrossERKS_(ptr dead_on_unwind noalias writable sret(%class.Vector4) align 4 %0, ptr nocapture noundef nonnull readonly align 4 dereferenceable(16) %1, ptr nocapture noundef nonnull readonly align 4 dereferenceable(16) %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %1, i64 4
  %5 = load float, ptr %4, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %2, i64 8
  %7 = load float, ptr %6, align 4, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %1, i64 8
  %9 = load float, ptr %8, align 4, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %2, i64 4
  %11 = load float, ptr %10, align 4, !tbaa !5
  %12 = fneg float %9
  %13 = fmul float %11, %12
  %14 = tail call float @llvm.fmuladd.f32(float %5, float %7, float %13)
  %15 = load float, ptr %2, align 4, !tbaa !5
  %16 = load float, ptr %1, align 4, !tbaa !5
  %17 = fneg float %16
  %18 = fmul float %7, %17
  %19 = tail call float @llvm.fmuladd.f32(float %9, float %15, float %18)
  %20 = fneg float %5
  %21 = fmul float %15, %20
  %22 = tail call float @llvm.fmuladd.f32(float %16, float %11, float %21)
  tail call void @_ZN7Vector4C1Effff(ptr noundef nonnull align 4 dereferenceable(16) %0, float noundef %14, float noundef %19, float noundef %22, float noundef 0.000000e+00)
  ret void
}

declare void @_ZN7Vector4C1Effff(ptr, float, float, float, float) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass