; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %11, i32 0, i32 13
  %13 = load i32, ptr %12, align 8, !tbaa !13
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %17, i32 0, i32 13
  store i32 1, ptr %18, align 8, !tbaa !13
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %22, i32 0, i32 14
  %24 = load volatile i32, ptr %23, align 4, !tbaa !16
  %25 = icmp ne i32 %24, 1
  br i1 %25, label %26, label %33

26:                                               ; preds = %21
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %27

27:                                               ; preds = %26
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %28, i32 0, i32 13
  store i32 0, ptr %29, align 8, !tbaa !13
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  %32 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %32, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

33:                                               ; preds = %21
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = icmp eq ptr %34, null
  br i1 %35, label %40, label %36

36:                                               ; preds = %33
  %37 = load i16, ptr %7, align 2, !tbaa !9
  %38 = zext i16 %37 to i64
  %39 = icmp eq i64 %38, 0
  br i1 %39, label %40, label %47

40:                                               ; preds = %36, %33
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %41

41:                                               ; preds = %40
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %42, i32 0, i32 13
  store i32 0, ptr %43, align 8, !tbaa !13
  br label %44

44:                                               ; preds = %41
  br label %45

45:                                               ; preds = %44
  %46 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %46, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

47:                                               ; preds = %36
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %48, i32 0, i32 14
  store volatile i32 3, ptr %49, align 4, !tbaa !16
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %50, i32 0, i32 15
  store volatile i32 0, ptr %51, align 8, !tbaa !17
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %53, i32 0, i32 2
  store ptr %52, ptr %54, align 8, !tbaa !18
  %55 = load i16, ptr %7, align 2, !tbaa !9
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %56, i32 0, i32 3
  store i16 %55, ptr %57, align 8, !tbaa !19
  %58 = load i16, ptr %7, align 2, !tbaa !9
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %59, i32 0, i32 4
  store volatile i16 %58, ptr %60, align 2, !tbaa !20
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %61, i32 0, i32 5
  store ptr null, ptr %62, align 8, !tbaa !21
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %63, i32 0, i32 10
  store ptr null, ptr %64, align 8, !tbaa !22
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %65, i32 0, i32 9
  store ptr null, ptr %66, align 8, !tbaa !23
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %67, i32 0, i32 6
  store i16 0, ptr %68, align 8, !tbaa !24
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %69, i32 0, i32 7
  store volatile i16 0, ptr %70, align 2, !tbaa !25
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %71, i32 0, i32 1
  %73 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %72, i32 0, i32 1
  %74 = load i32, ptr %73, align 4, !tbaa !26
  %75 = zext i32 %74 to i64
  %76 = icmp eq i64 %75, 393216
  br i1 %76, label %77, label %86

77:                                               ; preds = %47
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !27
  %81 = getelementptr inbounds %struct.SPI_TypeDef, ptr %80, i32 0, i32 0
  %82 = load volatile i32, ptr %81, align 4, !tbaa !28
  %83 = zext i32 %82 to i64
  %84 = or i64 %83, 2048
  %85 = trunc i64 %84 to i32
  store volatile i32 %85, ptr %81, align 4, !tbaa !28
  br label %100

86:                                               ; preds = %47
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !27
  %90 = getelementptr inbounds %struct.SPI_TypeDef, ptr %89, i32 0, i32 3
  %91 = load volatile i32, ptr %90, align 4, !tbaa !30
  %92 = zext i32 %91 to i64
  %93 = and i64 %92, -393217
  %94 = or i64 %93, 131072
  %95 = trunc i64 %94 to i32
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %96, i32 0, i32 0
  %98 = load ptr, ptr %97, align 8, !tbaa !27
  %99 = getelementptr inbounds %struct.SPI_TypeDef, ptr %98, i32 0, i32 3
  store volatile i32 %95, ptr %99, align 4, !tbaa !30
  br label %100

100:                                              ; preds = %86, %77
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %101, i32 0, i32 1
  %103 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %102, i32 0, i32 2
  %104 = load i32, ptr %103, align 8, !tbaa !31
  %105 = zext i32 %104 to i64
  %106 = icmp ugt i64 %105, 15
  br i1 %106, label %107, label %115

107:                                              ; preds = %100
  %108 = load ptr, ptr %5, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %108, i32 0, i32 11
  %110 = load ptr, ptr %109, align 8, !tbaa !32
  %111 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %110, i32 0, i32 1
  %112 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %111, i32 0, i32 5
  %113 = load i32, ptr %112, align 4, !tbaa !33
  %114 = icmp ne i32 %113, 16384
  br i1 %114, label %138, label %115

115:                                              ; preds = %107, %100
  %116 = load ptr, ptr %5, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %116, i32 0, i32 1
  %118 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %117, i32 0, i32 2
  %119 = load i32, ptr %118, align 8, !tbaa !31
  %120 = zext i32 %119 to i64
  %121 = icmp ugt i64 %120, 7
  br i1 %121, label %122, label %145

122:                                              ; preds = %115
  %123 = load ptr, ptr %5, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %123, i32 0, i32 11
  %125 = load ptr, ptr %124, align 8, !tbaa !32
  %126 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %125, i32 0, i32 1
  %127 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %126, i32 0, i32 5
  %128 = load i32, ptr %127, align 4, !tbaa !33
  %129 = icmp ne i32 %128, 8192
  br i1 %129, label %130, label %145

130:                                              ; preds = %122
  %131 = load ptr, ptr %5, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %131, i32 0, i32 11
  %133 = load ptr, ptr %132, align 8, !tbaa !32
  %134 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %133, i32 0, i32 1
  %135 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %134, i32 0, i32 5
  %136 = load i32, ptr %135, align 4, !tbaa !33
  %137 = icmp ne i32 %136, 16384
  br i1 %137, label %138, label %145

138:                                              ; preds = %130, %107
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %139

139:                                              ; preds = %138
  %140 = load ptr, ptr %5, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %140, i32 0, i32 13
  store i32 0, ptr %141, align 8, !tbaa !13
  br label %142

142:                                              ; preds = %139
  br label %143

143:                                              ; preds = %142
  %144 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %144, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

145:                                              ; preds = %130, %122, %115
  %146 = load ptr, ptr %5, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %146, i32 0, i32 1
  %148 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %147, i32 0, i32 2
  %149 = load i32, ptr %148, align 8, !tbaa !31
  %150 = zext i32 %149 to i64
  %151 = icmp ule i64 %150, 7
  br i1 %151, label %152, label %189

152:                                              ; preds = %145
  %153 = load ptr, ptr %5, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %153, i32 0, i32 11
  %155 = load ptr, ptr %154, align 8, !tbaa !32
  %156 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %155, i32 0, i32 1
  %157 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %156, i32 0, i32 5
  %158 = load i32, ptr %157, align 4, !tbaa !33
  %159 = icmp eq i32 %158, 8192
  br i1 %159, label %160, label %170

160:                                              ; preds = %152
  %161 = load ptr, ptr %5, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %161, i32 0, i32 4
  %163 = load volatile i16, ptr %162, align 2, !tbaa !20
  %164 = zext i16 %163 to i32
  %165 = add nsw i32 %164, 1
  %166 = ashr i32 %165, 1
  %167 = trunc i32 %166 to i16
  %168 = load ptr, ptr %5, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %168, i32 0, i32 4
  store volatile i16 %167, ptr %169, align 2, !tbaa !20
  br label %170

170:                                              ; preds = %160, %152
  %171 = load ptr, ptr %5, align 8, !tbaa !5
  %172 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %171, i32 0, i32 11
  %173 = load ptr, ptr %172, align 8, !tbaa !32
  %174 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %173, i32 0, i32 1
  %175 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %174, i32 0, i32 5
  %176 = load i32, ptr %175, align 4, !tbaa !33
  %177 = icmp eq i32 %176, 16384
  br i1 %177, label %178, label %188

178:                                              ; preds = %170
  %179 = load ptr, ptr %5, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %179, i32 0, i32 4
  %181 = load volatile i16, ptr %180, align 2, !tbaa !20
  %182 = zext i16 %181 to i32
  %183 = add nsw i32 %182, 3
  %184 = ashr i32 %183, 2
  %185 = trunc i32 %184 to i16
  %186 = load ptr, ptr %5, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %186, i32 0, i32 4
  store volatile i16 %185, ptr %187, align 2, !tbaa !20
  br label %188

188:                                              ; preds = %178, %170
  br label %217

189:                                              ; preds = %145
  %190 = load ptr, ptr %5, align 8, !tbaa !5
  %191 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %190, i32 0, i32 1
  %192 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %191, i32 0, i32 2
  %193 = load i32, ptr %192, align 8, !tbaa !31
  %194 = zext i32 %193 to i64
  %195 = icmp ule i64 %194, 15
  br i1 %195, label %196, label %215

196:                                              ; preds = %189
  %197 = load ptr, ptr %5, align 8, !tbaa !5
  %198 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %197, i32 0, i32 11
  %199 = load ptr, ptr %198, align 8, !tbaa !32
  %200 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %199, i32 0, i32 1
  %201 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %200, i32 0, i32 5
  %202 = load i32, ptr %201, align 4, !tbaa !33
  %203 = icmp eq i32 %202, 16384
  br i1 %203, label %204, label %214

204:                                              ; preds = %196
  %205 = load ptr, ptr %5, align 8, !tbaa !5
  %206 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %205, i32 0, i32 4
  %207 = load volatile i16, ptr %206, align 2, !tbaa !20
  %208 = zext i16 %207 to i32
  %209 = add nsw i32 %208, 1
  %210 = ashr i32 %209, 1
  %211 = trunc i32 %210 to i16
  %212 = load ptr, ptr %5, align 8, !tbaa !5
  %213 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %212, i32 0, i32 4
  store volatile i16 %211, ptr %213, align 2, !tbaa !20
  br label %214

214:                                              ; preds = %204, %196
  br label %216

215:                                              ; preds = %189
  br label %216

216:                                              ; preds = %215, %214
  br label %217

217:                                              ; preds = %216, %188
  %218 = load ptr, ptr %5, align 8, !tbaa !5
  %219 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %218, i32 0, i32 11
  %220 = load ptr, ptr %219, align 8, !tbaa !32
  %221 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %220, i32 0, i32 6
  store ptr @SPI_DMAHalfTransmitCplt, ptr %221, align 8, !tbaa !36
  %222 = load ptr, ptr %5, align 8, !tbaa !5
  %223 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %222, i32 0, i32 11
  %224 = load ptr, ptr %223, align 8, !tbaa !32
  %225 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %224, i32 0, i32 5
  store ptr @SPI_DMATransmitCplt, ptr %225, align 8, !tbaa !37
  %226 = load ptr, ptr %5, align 8, !tbaa !5
  %227 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %226, i32 0, i32 11
  %228 = load ptr, ptr %227, align 8, !tbaa !32
  %229 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %228, i32 0, i32 9
  store ptr @SPI_DMAError, ptr %229, align 8, !tbaa !38
  %230 = load ptr, ptr %5, align 8, !tbaa !5
  %231 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %230, i32 0, i32 11
  %232 = load ptr, ptr %231, align 8, !tbaa !32
  %233 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %232, i32 0, i32 10
  store ptr null, ptr %233, align 8, !tbaa !39
  %234 = load ptr, ptr %5, align 8, !tbaa !5
  %235 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %234, i32 0, i32 0
  %236 = load ptr, ptr %235, align 8, !tbaa !27
  %237 = getelementptr inbounds %struct.SPI_TypeDef, ptr %236, i32 0, i32 2
  %238 = load volatile i32, ptr %237, align 4, !tbaa !40
  %239 = zext i32 %238 to i64
  %240 = and i64 %239, -32769
  %241 = trunc i64 %240 to i32
  store volatile i32 %241, ptr %237, align 4, !tbaa !40
  %242 = load ptr, ptr %5, align 8, !tbaa !5
  %243 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %242, i32 0, i32 11
  %244 = load ptr, ptr %243, align 8, !tbaa !32
  %245 = load ptr, ptr %5, align 8, !tbaa !5
  %246 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %245, i32 0, i32 2
  %247 = load ptr, ptr %246, align 8, !tbaa !18
  %248 = ptrtoint ptr %247 to i32
  %249 = load ptr, ptr %5, align 8, !tbaa !5
  %250 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %249, i32 0, i32 0
  %251 = load ptr, ptr %250, align 8, !tbaa !27
  %252 = getelementptr inbounds %struct.SPI_TypeDef, ptr %251, i32 0, i32 8
  %253 = ptrtoint ptr %252 to i32
  %254 = load ptr, ptr %5, align 8, !tbaa !5
  %255 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %254, i32 0, i32 4
  %256 = load volatile i16, ptr %255, align 2, !tbaa !20
  %257 = zext i16 %256 to i32
  %258 = call i32 @HAL_DMA_Start_IT(ptr noundef %244, i32 noundef %248, i32 noundef %253, i32 noundef %257)
  %259 = icmp ne i32 0, %258
  br i1 %259, label %260, label %275

260:                                              ; preds = %217
  %261 = load ptr, ptr %5, align 8, !tbaa !5
  %262 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %261, i32 0, i32 15
  %263 = load volatile i32, ptr %262, align 8, !tbaa !17
  %264 = zext i32 %263 to i64
  %265 = or i64 %264, 16
  %266 = trunc i64 %265 to i32
  store volatile i32 %266, ptr %262, align 8, !tbaa !17
  br label %267

267:                                              ; preds = %260
  %268 = load ptr, ptr %5, align 8, !tbaa !5
  %269 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %268, i32 0, i32 13
  store i32 0, ptr %269, align 8, !tbaa !13
  br label %270

270:                                              ; preds = %267
  br label %271

271:                                              ; preds = %270
  %272 = load ptr, ptr %5, align 8, !tbaa !5
  %273 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %272, i32 0, i32 14
  store volatile i32 1, ptr %273, align 4, !tbaa !16
  store i32 1, ptr %8, align 4, !tbaa !11
  %274 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %274, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

275:                                              ; preds = %217
  %276 = load ptr, ptr %5, align 8, !tbaa !5
  %277 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %276, i32 0, i32 11
  %278 = load ptr, ptr %277, align 8, !tbaa !32
  %279 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %278, i32 0, i32 1
  %280 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %279, i32 0, i32 6
  %281 = load i32, ptr %280, align 8, !tbaa !41
  %282 = icmp eq i32 %281, 256
  br i1 %282, label %283, label %297

283:                                              ; preds = %275
  %284 = load ptr, ptr %5, align 8, !tbaa !5
  %285 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %284, i32 0, i32 0
  %286 = load ptr, ptr %285, align 8, !tbaa !27
  %287 = getelementptr inbounds %struct.SPI_TypeDef, ptr %286, i32 0, i32 1
  %288 = load volatile i32, ptr %287, align 4, !tbaa !42
  %289 = zext i32 %288 to i64
  %290 = and i64 %289, -65536
  %291 = or i64 %290, 0
  %292 = trunc i64 %291 to i32
  %293 = load ptr, ptr %5, align 8, !tbaa !5
  %294 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %293, i32 0, i32 0
  %295 = load ptr, ptr %294, align 8, !tbaa !27
  %296 = getelementptr inbounds %struct.SPI_TypeDef, ptr %295, i32 0, i32 1
  store volatile i32 %292, ptr %296, align 4, !tbaa !42
  br label %313

297:                                              ; preds = %275
  %298 = load ptr, ptr %5, align 8, !tbaa !5
  %299 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %298, i32 0, i32 0
  %300 = load ptr, ptr %299, align 8, !tbaa !27
  %301 = getelementptr inbounds %struct.SPI_TypeDef, ptr %300, i32 0, i32 1
  %302 = load volatile i32, ptr %301, align 4, !tbaa !42
  %303 = zext i32 %302 to i64
  %304 = and i64 %303, -65536
  %305 = load i16, ptr %7, align 2, !tbaa !9
  %306 = zext i16 %305 to i64
  %307 = or i64 %304, %306
  %308 = trunc i64 %307 to i32
  %309 = load ptr, ptr %5, align 8, !tbaa !5
  %310 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %309, i32 0, i32 0
  %311 = load ptr, ptr %310, align 8, !tbaa !27
  %312 = getelementptr inbounds %struct.SPI_TypeDef, ptr %311, i32 0, i32 1
  store volatile i32 %308, ptr %312, align 4, !tbaa !42
  br label %313

313:                                              ; preds = %297, %283
  %314 = load ptr, ptr %5, align 8, !tbaa !5
  %315 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %314, i32 0, i32 0
  %316 = load ptr, ptr %315, align 8, !tbaa !27
  %317 = getelementptr inbounds %struct.SPI_TypeDef, ptr %316, i32 0, i32 2
  %318 = load volatile i32, ptr %317, align 4, !tbaa !40
  %319 = zext i32 %318 to i64
  %320 = or i64 %319, 32768
  %321 = trunc i64 %320 to i32
  store volatile i32 %321, ptr %317, align 4, !tbaa !40
  %322 = load ptr, ptr %5, align 8, !tbaa !5
  %323 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %322, i32 0, i32 0
  %324 = load ptr, ptr %323, align 8, !tbaa !27
  %325 = getelementptr inbounds %struct.SPI_TypeDef, ptr %324, i32 0, i32 4
  %326 = load volatile i32, ptr %325, align 4, !tbaa !43
  %327 = zext i32 %326 to i64
  %328 = or i64 %327, 800
  %329 = trunc i64 %328 to i32
  store volatile i32 %329, ptr %325, align 4, !tbaa !43
  %330 = load ptr, ptr %5, align 8, !tbaa !5
  %331 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %330, i32 0, i32 0
  %332 = load ptr, ptr %331, align 8, !tbaa !27
  %333 = getelementptr inbounds %struct.SPI_TypeDef, ptr %332, i32 0, i32 0
  %334 = load volatile i32, ptr %333, align 4, !tbaa !28
  %335 = zext i32 %334 to i64
  %336 = or i64 %335, 1
  %337 = trunc i64 %336 to i32
  store volatile i32 %337, ptr %333, align 4, !tbaa !28
  %338 = load ptr, ptr %5, align 8, !tbaa !5
  %339 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %338, i32 0, i32 1
  %340 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %339, i32 0, i32 0
  %341 = load i32, ptr %340, align 8, !tbaa !44
  %342 = zext i32 %341 to i64
  %343 = icmp eq i64 %342, 4194304
  br i1 %343, label %344, label %353

344:                                              ; preds = %313
  %345 = load ptr, ptr %5, align 8, !tbaa !5
  %346 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %345, i32 0, i32 0
  %347 = load ptr, ptr %346, align 8, !tbaa !27
  %348 = getelementptr inbounds %struct.SPI_TypeDef, ptr %347, i32 0, i32 0
  %349 = load volatile i32, ptr %348, align 4, !tbaa !28
  %350 = zext i32 %349 to i64
  %351 = or i64 %350, 512
  %352 = trunc i64 %351 to i32
  store volatile i32 %352, ptr %348, align 4, !tbaa !28
  br label %353

353:                                              ; preds = %344, %313
  br label %354

354:                                              ; preds = %353
  %355 = load ptr, ptr %5, align 8, !tbaa !5
  %356 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %355, i32 0, i32 13
  store i32 0, ptr %356, align 8, !tbaa !13
  br label %357

357:                                              ; preds = %354
  br label %358

358:                                              ; preds = %357
  %359 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %359, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %360

360:                                              ; preds = %358, %271, %143, %45, %31, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %361 = load i32, ptr %4, align 4
  ret i32 %361
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfTransmitCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATransmitCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 160}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 164}
!17 = !{!14, !12, i64 168}
!18 = !{!14, !6, i64 96}
!19 = !{!14, !10, i64 104}
!20 = !{!14, !10, i64 106}
!21 = !{!14, !6, i64 112}
!22 = !{!14, !6, i64 136}
!23 = !{!14, !6, i64 128}
!24 = !{!14, !10, i64 120}
!25 = !{!14, !10, i64 122}
!26 = !{!14, !12, i64 12}
!27 = !{!14, !6, i64 0}
!28 = !{!29, !12, i64 0}
!29 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!30 = !{!29, !12, i64 12}
!31 = !{!14, !12, i64 16}
!32 = !{!14, !6, i64 144}
!33 = !{!34, !12, i64 28}
!34 = !{!"__DMA_HandleTypeDef", !6, i64 0, !35, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!35 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!36 = !{!34, !6, i64 80}
!37 = !{!34, !6, i64 72}
!38 = !{!34, !6, i64 104}
!39 = !{!34, !6, i64 112}
!40 = !{!29, !12, i64 8}
!41 = !{!34, !12, i64 32}
!42 = !{!29, !12, i64 4}
!43 = !{!29, !12, i64 16}
!44 = !{!14, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SPI_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 160
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %102, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 164
  %9 = load volatile i32, ptr %8, align 4, !tbaa !13
  %.not = icmp eq i32 %9, 1
  br i1 %.not, label %11, label %10

10:                                               ; preds = %7
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %102

11:                                               ; preds = %7
  %12 = icmp eq ptr %1, null
  %13 = icmp eq i16 %2, 0
  %or.cond = or i1 %12, %13
  br i1 %or.cond, label %14, label %15

14:                                               ; preds = %11
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %102

15:                                               ; preds = %11
  store volatile i32 3, ptr %8, align 4, !tbaa !13
  %16 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %16, align 8, !tbaa !14
  %17 = getelementptr inbounds i8, ptr %0, i64 96
  store ptr %1, ptr %17, align 8, !tbaa !15
  %18 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 %2, ptr %18, align 8, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %0, i64 106
  store volatile i16 %2, ptr %19, align 2, !tbaa !17
  %20 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr null, ptr %20, align 8, !tbaa !18
  %21 = getelementptr inbounds i8, ptr %0, i64 128
  %22 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 0, ptr %22, align 8, !tbaa !19
  %23 = getelementptr inbounds i8, ptr %0, i64 122
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %21, i8 0, i64 16, i1 false)
  store volatile i16 0, ptr %23, align 2, !tbaa !20
  %24 = getelementptr inbounds i8, ptr %0, i64 8
  %25 = getelementptr inbounds i8, ptr %0, i64 12
  %26 = load i32, ptr %25, align 4, !tbaa !21
  %27 = icmp eq i32 %26, 393216
  %28 = load ptr, ptr %0, align 8, !tbaa !22
  br i1 %27, label %29, label %32

29:                                               ; preds = %15
  %30 = load volatile i32, ptr %28, align 4, !tbaa !23
  %31 = or i32 %30, 2048
  store volatile i32 %31, ptr %28, align 4, !tbaa !23
  br label %37

32:                                               ; preds = %15
  %33 = getelementptr inbounds i8, ptr %28, i64 12
  %34 = load volatile i32, ptr %33, align 4, !tbaa !25
  %35 = and i32 %34, -393217
  %36 = or disjoint i32 %35, 131072
  store volatile i32 %36, ptr %33, align 4, !tbaa !25
  br label %37

37:                                               ; preds = %32, %29
  %38 = getelementptr inbounds i8, ptr %0, i64 16
  %39 = load i32, ptr %38, align 8, !tbaa !26
  %40 = icmp ugt i32 %39, 15
  br i1 %40, label %41, label %46

41:                                               ; preds = %37
  %42 = getelementptr inbounds i8, ptr %0, i64 144
  %43 = load ptr, ptr %42, align 8, !tbaa !27
  %44 = getelementptr inbounds i8, ptr %43, i64 28
  %45 = load i32, ptr %44, align 4, !tbaa !28
  %.not76 = icmp eq i32 %45, 16384
  br i1 %.not76, label %56, label %48

46:                                               ; preds = %37
  %47 = icmp ugt i32 %39, 7
  %.phi.trans.insert = getelementptr inbounds i8, ptr %0, i64 144
  %.pre = load ptr, ptr %.phi.trans.insert, align 8, !tbaa !27
  %.phi.trans.insert82 = getelementptr inbounds i8, ptr %.pre, i64 28
  %.pre83 = load i32, ptr %.phi.trans.insert82, align 4, !tbaa !28
  br i1 %47, label %.thread, label %49

.thread:                                          ; preds = %46
  switch i32 %.pre83, label %48 [
    i32 16384, label %.sink.split
    i32 8192, label %56
  ]

48:                                               ; preds = %.thread, %41
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %102

49:                                               ; preds = %46
  switch i32 %.pre83, label %56 [
    i32 8192, label %.sink.split
    i32 16384, label %50
  ]

50:                                               ; preds = %49
  br label %.sink.split

.sink.split:                                      ; preds = %.thread, %49, %50
  %.sink88 = phi i32 [ 3, %50 ], [ 1, %49 ], [ 1, %.thread ]
  %.sink86 = phi i32 [ 2, %50 ], [ 1, %49 ], [ 1, %.thread ]
  %51 = load volatile i16, ptr %19, align 2, !tbaa !17
  %52 = zext i16 %51 to i32
  %53 = add nuw nsw i32 %.sink88, %52
  %54 = lshr i32 %53, %.sink86
  %55 = trunc nuw i32 %54 to i16
  store volatile i16 %55, ptr %19, align 2, !tbaa !17
  br label %56

56:                                               ; preds = %.sink.split, %.thread, %41, %49
  %57 = phi ptr [ %.pre, %49 ], [ %43, %41 ], [ %.pre, %.thread ], [ %.pre, %.sink.split ]
  %58 = getelementptr inbounds i8, ptr %57, i64 80
  store ptr @SPI_DMAHalfTransmitCplt, ptr %58, align 8, !tbaa !31
  %59 = getelementptr inbounds i8, ptr %57, i64 72
  store ptr @SPI_DMATransmitCplt, ptr %59, align 8, !tbaa !32
  %60 = getelementptr inbounds i8, ptr %57, i64 104
  store ptr @SPI_DMAError, ptr %60, align 8, !tbaa !33
  %61 = getelementptr inbounds i8, ptr %57, i64 112
  store ptr null, ptr %61, align 8, !tbaa !34
  %62 = getelementptr inbounds i8, ptr %28, i64 8
  %63 = load volatile i32, ptr %62, align 4, !tbaa !35
  %64 = and i32 %63, -32769
  store volatile i32 %64, ptr %62, align 4, !tbaa !35
  %65 = ptrtoint ptr %1 to i64
  %66 = trunc i64 %65 to i32
  %67 = getelementptr inbounds i8, ptr %28, i64 32
  %68 = ptrtoint ptr %67 to i64
  %69 = trunc i64 %68 to i32
  %70 = load volatile i16, ptr %19, align 2, !tbaa !17
  %71 = zext i16 %70 to i32
  %72 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %57, i32 noundef %66, i32 noundef %69, i32 noundef %71) #3
  %.not79 = icmp eq i32 %72, 0
  br i1 %.not79, label %76, label %73

73:                                               ; preds = %56
  %74 = load volatile i32, ptr %16, align 8, !tbaa !14
  %75 = or i32 %74, 16
  store volatile i32 %75, ptr %16, align 8, !tbaa !14
  store i32 0, ptr %4, align 8, !tbaa !5
  store volatile i32 1, ptr %8, align 4, !tbaa !13
  br label %102

76:                                               ; preds = %56
  %77 = getelementptr inbounds i8, ptr %0, i64 144
  %78 = load ptr, ptr %77, align 8, !tbaa !27
  %79 = getelementptr inbounds i8, ptr %78, i64 32
  %80 = load i32, ptr %79, align 8, !tbaa !36
  %81 = icmp eq i32 %80, 256
  %82 = load ptr, ptr %0, align 8, !tbaa !22
  %83 = getelementptr inbounds i8, ptr %82, i64 4
  %84 = load volatile i32, ptr %83, align 4, !tbaa !37
  %85 = and i32 %84, -65536
  %86 = zext i16 %2 to i32
  %87 = select i1 %81, i32 0, i32 %86
  %.sink = or disjoint i32 %85, %87
  store volatile i32 %.sink, ptr %83, align 4, !tbaa !37
  %88 = getelementptr inbounds i8, ptr %82, i64 8
  %89 = load volatile i32, ptr %88, align 4, !tbaa !35
  %90 = or i32 %89, 32768
  store volatile i32 %90, ptr %88, align 4, !tbaa !35
  %91 = getelementptr inbounds i8, ptr %82, i64 16
  %92 = load volatile i32, ptr %91, align 4, !tbaa !38
  %93 = or i32 %92, 800
  store volatile i32 %93, ptr %91, align 4, !tbaa !38
  %94 = load volatile i32, ptr %82, align 4, !tbaa !23
  %95 = or i32 %94, 1
  store volatile i32 %95, ptr %82, align 4, !tbaa !23
  %96 = load i32, ptr %24, align 8, !tbaa !39
  %97 = icmp eq i32 %96, 4194304
  br i1 %97, label %98, label %101

98:                                               ; preds = %76
  %99 = load volatile i32, ptr %82, align 4, !tbaa !23
  %100 = or i32 %99, 512
  store volatile i32 %100, ptr %82, align 4, !tbaa !23
  br label %101

101:                                              ; preds = %76, %98
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %102

102:                                              ; preds = %3, %101, %73, %48, %14, %10
  %.0 = phi i32 [ 2, %10 ], [ 1, %14 ], [ 1, %48 ], [ 1, %73 ], [ 0, %101 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfTransmitCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATransmitCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 160}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 164}
!14 = !{!6, !11, i64 168}
!15 = !{!6, !7, i64 96}
!16 = !{!6, !12, i64 104}
!17 = !{!6, !12, i64 106}
!18 = !{!6, !7, i64 112}
!19 = !{!6, !12, i64 120}
!20 = !{!6, !12, i64 122}
!21 = !{!6, !11, i64 12}
!22 = !{!6, !7, i64 0}
!23 = !{!24, !11, i64 0}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!25 = !{!24, !11, i64 12}
!26 = !{!6, !11, i64 16}
!27 = !{!6, !7, i64 144}
!28 = !{!29, !11, i64 28}
!29 = !{!"__DMA_HandleTypeDef", !7, i64 0, !30, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!30 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!31 = !{!29, !7, i64 80}
!32 = !{!29, !7, i64 72}
!33 = !{!29, !7, i64 104}
!34 = !{!29, !7, i64 112}
!35 = !{!24, !11, i64 8}
!36 = !{!29, !11, i64 32}
!37 = !{!24, !11, i64 4}
!38 = !{!24, !11, i64 16}
!39 = !{!6, !11, i64 8}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass