; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (hsi2c)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @I2CWakeUpEnable(i32 noundef %0, i32 noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !5
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = icmp eq i32 1, %7
  br i1 %8, label %9, label %17

9:                                                ; preds = %3
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = add i32 %11, 52
  %13 = zext i32 %12 to i64
  %14 = inttoptr i64 %13 to ptr
  %15 = load volatile i32, ptr %14, align 4, !tbaa !5
  %16 = or i32 %15, %10
  store volatile i32 %16, ptr %14, align 4, !tbaa !5
  br label %41

17:                                               ; preds = %3
  %18 = load i32, ptr %6, align 4, !tbaa !5
  %19 = icmp eq i32 2, %18
  br i1 %19, label %20, label %28

20:                                               ; preds = %17
  %21 = load i32, ptr %5, align 4, !tbaa !5
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = add i32 %22, 72
  %24 = zext i32 %23 to i64
  %25 = inttoptr i64 %24 to ptr
  %26 = load volatile i32, ptr %25, align 4, !tbaa !5
  %27 = or i32 %26, %21
  store volatile i32 %27, ptr %25, align 4, !tbaa !5
  br label %40

28:                                               ; preds = %17
  %29 = load i32, ptr %6, align 4, !tbaa !5
  %30 = icmp eq i32 3, %29
  br i1 %30, label %31, label %39

31:                                               ; preds = %28
  %32 = load i32, ptr %5, align 4, !tbaa !5
  %33 = load i32, ptr %4, align 4, !tbaa !5
  %34 = add i32 %33, 76
  %35 = zext i32 %34 to i64
  %36 = inttoptr i64 %35 to ptr
  %37 = load volatile i32, ptr %36, align 4, !tbaa !5
  %38 = or i32 %37, %32
  store volatile i32 %38, ptr %36, align 4, !tbaa !5
  br label %39

39:                                               ; preds = %31, %28
  br label %40

40:                                               ; preds = %39, %20
  br label %41

41:                                               ; preds = %40, %9
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.I2CWakeUpEnable = private unnamed_addr constant [3 x i32] [i32 52, i32 72, i32 76], align 4

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local void @I2CWakeUpEnable(i32 noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %switch.tableidx = add i32 %2, -1
  %4 = icmp ult i32 %switch.tableidx, 3
  br i1 %4, label %switch.lookup, label %11

switch.lookup:                                    ; preds = %3
  %5 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [3 x i32], ptr @switch.table.I2CWakeUpEnable, i64 0, i64 %5
  %switch.load = load i32, ptr %switch.gep, align 4
  %6 = add i32 %switch.load, %0
  %7 = zext i32 %6 to i64
  %8 = inttoptr i64 %7 to ptr
  %9 = load volatile i32, ptr %8, align 4, !tbaa !5
  %10 = or i32 %9, %1
  store volatile i32 %10, ptr %8, align 4, !tbaa !5
  br label %11

11:                                               ; preds = %3, %switch.lookup
  ret void
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass