; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Core/Src (tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_MasterConfigTypeDef = type { i32, i32, i32 }
%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_BreakDeadTimeConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@htim1 = external dso_local global %struct.TIM_HandleTypeDef, align 8

; Function Attrs: nounwind uwtable
define dso_local void @MX_TIM1_Init() #0 {
  %1 = alloca %struct.TIM_MasterConfigTypeDef, align 4
  %2 = alloca %struct.TIM_OC_InitTypeDef, align 4
  %3 = alloca %struct.TIM_BreakDeadTimeConfigTypeDef, align 4
  call void @llvm.lifetime.start.p0(i64 12, ptr %1) #4
  call void @llvm.memset.p0.i64(ptr align 4 %1, i8 0, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 28, ptr %2) #4
  call void @llvm.memset.p0.i64(ptr align 4 %2, i8 0, i64 28, i1 false)
  call void @llvm.lifetime.start.p0(i64 52, ptr %3) #4
  call void @llvm.memset.p0.i64(ptr align 4 %3, i8 0, i64 52, i1 false)
  store ptr inttoptr (i64 1073807360 to ptr), ptr @htim1, align 8, !tbaa !5
  store i32 0, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), align 8, !tbaa !12
  store i32 0, ptr getelementptr inbounds (%struct.TIM_Base_InitTypeDef, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), i32 0, i32 1), align 4, !tbaa !13
  store i32 65535, ptr getelementptr inbounds (%struct.TIM_Base_InitTypeDef, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), i32 0, i32 2), align 8, !tbaa !14
  store i32 0, ptr getelementptr inbounds (%struct.TIM_Base_InitTypeDef, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), i32 0, i32 3), align 4, !tbaa !15
  store i32 0, ptr getelementptr inbounds (%struct.TIM_Base_InitTypeDef, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), i32 0, i32 4), align 8, !tbaa !16
  store i32 0, ptr getelementptr inbounds (%struct.TIM_Base_InitTypeDef, ptr getelementptr inbounds (%struct.TIM_HandleTypeDef, ptr @htim1, i32 0, i32 1), i32 0, i32 5), align 4, !tbaa !17
  %4 = call i32 @HAL_TIM_PWM_Init(ptr noundef @htim1)
  %5 = icmp ne i32 %4, 0
  br i1 %5, label %6, label %7

6:                                                ; preds = %0
  call void @Error_Handler()
  br label %7

7:                                                ; preds = %6, %0
  %8 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %1, i32 0, i32 0
  store i32 0, ptr %8, align 4, !tbaa !18
  %9 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %1, i32 0, i32 1
  store i32 0, ptr %9, align 4, !tbaa !20
  %10 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %1, i32 0, i32 2
  store i32 0, ptr %10, align 4, !tbaa !21
  %11 = call i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef @htim1, ptr noundef %1)
  %12 = icmp ne i32 %11, 0
  br i1 %12, label %13, label %14

13:                                               ; preds = %7
  call void @Error_Handler()
  br label %14

14:                                               ; preds = %13, %7
  %15 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 0
  store i32 96, ptr %15, align 4, !tbaa !22
  %16 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 1
  store i32 0, ptr %16, align 4, !tbaa !24
  %17 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 2
  store i32 0, ptr %17, align 4, !tbaa !25
  %18 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 3
  store i32 0, ptr %18, align 4, !tbaa !26
  %19 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 4
  store i32 0, ptr %19, align 4, !tbaa !27
  %20 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 5
  store i32 0, ptr %20, align 4, !tbaa !28
  %21 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %2, i32 0, i32 6
  store i32 0, ptr %21, align 4, !tbaa !29
  %22 = call i32 @HAL_TIM_PWM_ConfigChannel(ptr noundef @htim1, ptr noundef %2, i32 noundef 0)
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %24, label %25

24:                                               ; preds = %14
  call void @Error_Handler()
  br label %25

25:                                               ; preds = %24, %14
  %26 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 0
  store i32 0, ptr %26, align 4, !tbaa !30
  %27 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 1
  store i32 0, ptr %27, align 4, !tbaa !32
  %28 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 2
  store i32 0, ptr %28, align 4, !tbaa !33
  %29 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 3
  store i32 0, ptr %29, align 4, !tbaa !34
  %30 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 4
  store i32 0, ptr %30, align 4, !tbaa !35
  %31 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 5
  store i32 8192, ptr %31, align 4, !tbaa !36
  %32 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 6
  store i32 0, ptr %32, align 4, !tbaa !37
  %33 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 8
  store i32 0, ptr %33, align 4, !tbaa !38
  %34 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 9
  store i32 33554432, ptr %34, align 4, !tbaa !39
  %35 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 10
  store i32 0, ptr %35, align 4, !tbaa !40
  %36 = getelementptr inbounds %struct.TIM_BreakDeadTimeConfigTypeDef, ptr %3, i32 0, i32 12
  store i32 0, ptr %36, align 4, !tbaa !41
  %37 = call i32 @HAL_TIMEx_ConfigBreakDeadTime(ptr noundef @htim1, ptr noundef %3)
  %38 = icmp ne i32 %37, 0
  br i1 %38, label %39, label %40

39:                                               ; preds = %25
  call void @Error_Handler()
  br label %40

40:                                               ; preds = %39, %25
  call void @HAL_TIM_MspPostInit(ptr noundef @htim1)
  call void @llvm.lifetime.end.p0(i64 52, ptr %3) #4
  call void @llvm.lifetime.end.p0(i64 28, ptr %2) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr %1) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

declare i32 @HAL_TIM_PWM_Init(ptr noundef) #3

declare void @Error_Handler() #3

declare i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef, ptr noundef) #3

declare i32 @HAL_TIM_PWM_ConfigChannel(ptr noundef, ptr noundef, i32 noundef) #3

declare i32 @HAL_TIMEx_ConfigBreakDeadTime(ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_TIM_MspPostInit(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 8}
!13 = !{!6, !11, i64 12}
!14 = !{!6, !11, i64 16}
!15 = !{!6, !11, i64 20}
!16 = !{!6, !11, i64 24}
!17 = !{!6, !11, i64 28}
!18 = !{!19, !11, i64 0}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!20 = !{!19, !11, i64 4}
!21 = !{!19, !11, i64 8}
!22 = !{!23, !11, i64 0}
!23 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!24 = !{!23, !11, i64 4}
!25 = !{!23, !11, i64 8}
!26 = !{!23, !11, i64 12}
!27 = !{!23, !11, i64 16}
!28 = !{!23, !11, i64 20}
!29 = !{!23, !11, i64 24}
!30 = !{!31, !11, i64 0}
!31 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48}
!32 = !{!31, !11, i64 4}
!33 = !{!31, !11, i64 8}
!34 = !{!31, !11, i64 12}
!35 = !{!31, !11, i64 16}
!36 = !{!31, !11, i64 20}
!37 = !{!31, !11, i64 24}
!38 = !{!31, !11, i64 32}
!39 = !{!31, !11, i64 36}
!40 = !{!31, !11, i64 40}
!41 = !{!31, !11, i64 48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_MasterConfigTypeDef = type { i32, i32, i32 }
%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_BreakDeadTimeConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@htim1 = external dso_local global %struct.TIM_HandleTypeDef, align 8

; Function Attrs: nounwind uwtable
define dso_local void @MX_TIM1_Init() local_unnamed_addr #0 {
  %1 = alloca %struct.TIM_MasterConfigTypeDef, align 4
  %2 = alloca %struct.TIM_OC_InitTypeDef, align 4
  %3 = alloca %struct.TIM_BreakDeadTimeConfigTypeDef, align 4
  call void @llvm.lifetime.start.p0(i64 12, ptr nonnull %1) #4
  call void @llvm.lifetime.start.p0(i64 28, ptr nonnull %2) #4
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(28) %2, i8 0, i64 28, i1 false)
  call void @llvm.lifetime.start.p0(i64 52, ptr nonnull %3) #4
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(52) %3, i8 0, i64 52, i1 false)
  store ptr inttoptr (i64 1073807360 to ptr), ptr @htim1, align 8, !tbaa !5
  store <4 x i32> <i32 0, i32 0, i32 65535, i32 0>, ptr getelementptr inbounds (i8, ptr @htim1, i64 8), align 8, !tbaa !12
  store i32 0, ptr getelementptr inbounds (i8, ptr @htim1, i64 24), align 8, !tbaa !13
  store i32 0, ptr getelementptr inbounds (i8, ptr @htim1, i64 28), align 4, !tbaa !14
  %4 = tail call i32 @HAL_TIM_PWM_Init(ptr noundef nonnull @htim1) #4
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %6, label %5

5:                                                ; preds = %0
  tail call void @Error_Handler() #4
  br label %6

6:                                                ; preds = %5, %0
  store i32 0, ptr %1, align 4, !tbaa !15
  %7 = getelementptr inbounds i8, ptr %1, i64 4
  store i32 0, ptr %7, align 4, !tbaa !17
  %8 = getelementptr inbounds i8, ptr %1, i64 8
  store i32 0, ptr %8, align 4, !tbaa !18
  %9 = call i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef nonnull @htim1, ptr noundef nonnull %1) #4
  %.not1 = icmp eq i32 %9, 0
  br i1 %.not1, label %11, label %10

10:                                               ; preds = %6
  call void @Error_Handler() #4
  br label %11

11:                                               ; preds = %10, %6
  store i32 96, ptr %2, align 4, !tbaa !19
  %12 = getelementptr inbounds i8, ptr %2, i64 4
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(24) %12, i8 0, i64 24, i1 false)
  %13 = call i32 @HAL_TIM_PWM_ConfigChannel(ptr noundef nonnull @htim1, ptr noundef nonnull %2, i32 noundef 0) #4
  %.not2 = icmp eq i32 %13, 0
  br i1 %.not2, label %15, label %14

14:                                               ; preds = %11
  call void @Error_Handler() #4
  br label %15

15:                                               ; preds = %14, %11
  %16 = getelementptr inbounds i8, ptr %3, i64 20
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(20) %3, i8 0, i64 20, i1 false)
  store i32 8192, ptr %16, align 4, !tbaa !21
  %17 = getelementptr inbounds i8, ptr %3, i64 24
  store i32 0, ptr %17, align 4, !tbaa !23
  %18 = getelementptr inbounds i8, ptr %3, i64 32
  store i32 0, ptr %18, align 4, !tbaa !24
  %19 = getelementptr inbounds i8, ptr %3, i64 36
  store i32 33554432, ptr %19, align 4, !tbaa !25
  %20 = getelementptr inbounds i8, ptr %3, i64 40
  store i32 0, ptr %20, align 4, !tbaa !26
  %21 = getelementptr inbounds i8, ptr %3, i64 48
  store i32 0, ptr %21, align 4, !tbaa !27
  %22 = call i32 @HAL_TIMEx_ConfigBreakDeadTime(ptr noundef nonnull @htim1, ptr noundef nonnull %3) #4
  %.not3 = icmp eq i32 %22, 0
  br i1 %.not3, label %24, label %23

23:                                               ; preds = %15
  call void @Error_Handler() #4
  br label %24

24:                                               ; preds = %23, %15
  call void @HAL_TIM_MspPostInit(ptr noundef nonnull @htim1)
  call void @llvm.lifetime.end.p0(i64 52, ptr nonnull %3) #4
  call void @llvm.lifetime.end.p0(i64 28, ptr nonnull %2) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr nonnull %1) #4
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

declare i32 @HAL_TIM_PWM_Init(ptr noundef) local_unnamed_addr #3

declare void @Error_Handler() local_unnamed_addr #3

declare i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef, ptr noundef) local_unnamed_addr #3

declare i32 @HAL_TIM_PWM_ConfigChannel(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #3

declare i32 @HAL_TIMEx_ConfigBreakDeadTime(ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_TIM_MspPostInit(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!6, !11, i64 24}
!14 = !{!6, !11, i64 28}
!15 = !{!16, !11, i64 0}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!17 = !{!16, !11, i64 4}
!18 = !{!16, !11, i64 8}
!19 = !{!20, !11, i64 0}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!21 = !{!22, !11, i64 20}
!22 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48}
!23 = !{!22, !11, i64 24}
!24 = !{!22, !11, i64 32}
!25 = !{!22, !11, i64 36}
!26 = !{!22, !11, i64 40}
!27 = !{!22, !11, i64 48}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,SLPVectorizerPass,TailCallElimPass