; LLVM IR from Columbitech/rohc :: src/cudp_profile.ll (ZN4ROHC11CUDPProfileC2EPNS_10CompressorEtPKNS_5iphdrE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.ROHC::CUDPProfile" = type <{ %"class.ROHC::CProfile", i16, i16, i8, [3 x i8] }>
%"class.ROHC::CProfile" = type { ptr, ptr, i16, i64, i32, i32, i32, i32, i64, i64, i32, i32, i16, %"class.ROHC::WLSB", i32, i32, i8, i32, i32, i32, %"struct.ROHC::iphdr", i16, i16, %"class.ROHC::WLSB", [11 x i64] }
%"struct.ROHC::iphdr" = type { i8, i8, i16, i16, i16, i8, i8, i16, i32, i32 }
%"class.ROHC::WLSB" = type { %"class.std::vector", i64, i64, i64, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<ROHC::WLSB<int>::LSB, std::allocator<ROHC::WLSB<int>::LSB>>::_Vector_impl" }
%"struct.std::_Vector_base<ROHC::WLSB<int>::LSB, std::allocator<ROHC::WLSB<int>::LSB>>::_Vector_impl" = type { %"struct.std::_Vector_base<ROHC::WLSB<int>::LSB, std::allocator<ROHC::WLSB<int>::LSB>>::_Vector_impl_data" }
%"struct.std::_Vector_base<ROHC::WLSB<int>::LSB, std::allocator<ROHC::WLSB<int>::LSB>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.ROHC::udphdr" = type { i16, i16, i16, i16 }

@_ZTVN4ROHC11CUDPProfileE = external dso_local unnamed_addr constant { [10 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4ROHC11CUDPProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(333) %0, ptr noundef %1, i16 noundef zeroext %2, ptr noundef %3) unnamed_addr #0 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !5
  %10 = load ptr, ptr %5, align 8
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  %12 = load i16, ptr %7, align 2, !tbaa !9
  %13 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_ZN4ROHC8CProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(328) %10, ptr noundef %11, i16 noundef zeroext %12, ptr noundef %13)
  store ptr getelementptr inbounds inrange(-16, 64) ({ [10 x ptr] }, ptr @_ZTVN4ROHC11CUDPProfileE, i32 0, i32 0, i32 2), ptr %10, align 8, !tbaa !11
  %14 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 1
  store i16 0, ptr %14, align 8, !tbaa !13
  %15 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 2
  store i16 0, ptr %15, align 2, !tbaa !28
  %16 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 3
  store i8 1, ptr %16, align 4, !tbaa !29
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  %17 = load ptr, ptr %8, align 8, !tbaa !5
  %18 = getelementptr inbounds %"struct.ROHC::iphdr", ptr %17, i64 1
  store ptr %18, ptr %9, align 8, !tbaa !5
  %19 = load ptr, ptr %9, align 8, !tbaa !5
  %20 = getelementptr inbounds %"struct.ROHC::udphdr", ptr %19, i32 0, i32 0
  %21 = load i16, ptr %20, align 2, !tbaa !30
  %22 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 1
  store i16 %21, ptr %22, align 8, !tbaa !13
  %23 = load ptr, ptr %9, align 8, !tbaa !5
  %24 = getelementptr inbounds %"struct.ROHC::udphdr", ptr %23, i32 0, i32 1
  %25 = load i16, ptr %24, align 2, !tbaa !32
  %26 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 2
  store i16 %25, ptr %26, align 2, !tbaa !28
  %27 = load ptr, ptr %9, align 8, !tbaa !5
  %28 = getelementptr inbounds %"struct.ROHC::udphdr", ptr %27, i32 0, i32 3
  %29 = load i16, ptr %28, align 2, !tbaa !33
  %30 = zext i16 %29 to i32
  %31 = icmp ne i32 %30, 0
  %32 = getelementptr inbounds %"class.ROHC::CUDPProfile", ptr %10, i32 0, i32 3
  %33 = zext i1 %31 to i8
  store i8 %33, ptr %32, align 4, !tbaa !29
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret void
}

declare void @_ZN4ROHC8CProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef, i16 noundef zeroext, ptr noundef) unnamed_addr #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = !{!14, !10, i64 328}
!14 = !{!"_ZTSN4ROHC11CUDPProfileE", !15, i64 0, !10, i64 328, !10, i64 330, !25, i64 332}
!15 = !{!"_ZTSN4ROHC8CProfileE", !6, i64 8, !10, i64 16, !16, i64 24, !17, i64 32, !17, i64 36, !17, i64 40, !17, i64 44, !16, i64 48, !16, i64 56, !17, i64 64, !17, i64 68, !10, i64 72, !18, i64 80, !23, i64 136, !24, i64 140, !25, i64 144, !26, i64 148, !17, i64 152, !17, i64 156, !27, i64 160, !10, i64 180, !10, i64 182, !18, i64 184, !7, i64 240}
!16 = !{!"long", !7, i64 0}
!17 = !{!"int", !7, i64 0}
!18 = !{!"_ZTSN4ROHC4WLSBIiEE", !19, i64 0, !16, i64 24, !16, i64 32, !16, i64 40, !17, i64 48, !17, i64 52}
!19 = !{!"_ZTSSt6vectorIN4ROHC4WLSBIiE3LSBESaIS3_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSN4ROHC12Reordering_tE", !7, i64 0}
!24 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !7, i64 0}
!25 = !{!"bool", !7, i64 0}
!26 = !{!"_ZTSN4ROHC8CProfileUt_E", !7, i64 0}
!27 = !{!"_ZTSN4ROHC5iphdrE", !7, i64 0, !7, i64 0, !7, i64 1, !10, i64 2, !10, i64 4, !10, i64 6, !7, i64 8, !7, i64 9, !10, i64 10, !17, i64 12, !17, i64 16}
!28 = !{!14, !10, i64 330}
!29 = !{!14, !25, i64 332}
!30 = !{!31, !10, i64 0}
!31 = !{!"_ZTSN4ROHC6udphdrE", !10, i64 0, !10, i64 2, !10, i64 4, !10, i64 6}
!32 = !{!31, !10, i64 2}
!33 = !{!31, !10, i64 6}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN4ROHC11CUDPProfileE = external dso_local unnamed_addr constant { [10 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4ROHC11CUDPProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(333) %0, ptr noundef %1, i16 noundef zeroext %2, ptr noundef %3) unnamed_addr #0 align 2 {
  tail call void @_ZN4ROHC8CProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(328) %0, ptr noundef %1, i16 noundef zeroext %2, ptr noundef %3)
  store ptr getelementptr inbounds inrange(-16, 64) (i8, ptr @_ZTVN4ROHC11CUDPProfileE, i64 16), ptr %0, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 328
  %6 = getelementptr inbounds i8, ptr %0, i64 332
  %7 = getelementptr inbounds i8, ptr %3, i64 20
  %8 = load <2 x i16>, ptr %7, align 2, !tbaa !8
  store <2 x i16> %8, ptr %5, align 8, !tbaa !8
  %9 = getelementptr inbounds i8, ptr %3, i64 26
  %10 = load i16, ptr %9, align 2, !tbaa !11
  %11 = icmp ne i16 %10, 0
  %12 = zext i1 %11 to i8
  store i8 %12, ptr %6, align 4, !tbaa !13
  ret void
}

declare void @_ZN4ROHC8CProfileC2EPNS_10CompressorEtPKNS_5iphdrE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef, i16 noundef zeroext, ptr noundef) unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"short", !10, i64 0}
!10 = !{!"omnipotent char", !7, i64 0}
!11 = !{!12, !9, i64 6}
!12 = !{!"_ZTSN4ROHC6udphdrE", !9, i64 0, !9, i64 2, !9, i64 4, !9, i64 6}
!13 = !{!14, !26, i64 332}
!14 = !{!"_ZTSN4ROHC11CUDPProfileE", !15, i64 0, !9, i64 328, !9, i64 330, !26, i64 332}
!15 = !{!"_ZTSN4ROHC8CProfileE", !16, i64 8, !9, i64 16, !17, i64 24, !18, i64 32, !18, i64 36, !18, i64 40, !18, i64 44, !17, i64 48, !17, i64 56, !18, i64 64, !18, i64 68, !9, i64 72, !19, i64 80, !24, i64 136, !25, i64 140, !26, i64 144, !27, i64 148, !18, i64 152, !18, i64 156, !28, i64 160, !9, i64 180, !9, i64 182, !19, i64 184, !10, i64 240}
!16 = !{!"any pointer", !10, i64 0}
!17 = !{!"long", !10, i64 0}
!18 = !{!"int", !10, i64 0}
!19 = !{!"_ZTSN4ROHC4WLSBIiEE", !20, i64 0, !17, i64 24, !17, i64 32, !17, i64 40, !18, i64 48, !18, i64 52}
!20 = !{!"_ZTSSt6vectorIN4ROHC4WLSBIiE3LSBESaIS3_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4ROHC4WLSBIiE3LSBESaIS3_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!24 = !{!"_ZTSN4ROHC12Reordering_tE", !10, i64 0}
!25 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !10, i64 0}
!26 = !{!"bool", !10, i64 0}
!27 = !{!"_ZTSN4ROHC8CProfileUt_E", !10, i64 0}
!28 = !{!"_ZTSN4ROHC5iphdrE", !10, i64 0, !10, i64 0, !10, i64 1, !9, i64 2, !9, i64 4, !9, i64 6, !10, i64 8, !10, i64 9, !9, i64 10, !18, i64 12, !18, i64 16}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SLPVectorizerPass,SROAPass,TailCallElimPass