; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (uart_irda_cir)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTOperatingModeSelect(i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @UARTDivisorLatchWrite(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store volatile i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store volatile i32 0, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store volatile i32 0, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store volatile i32 0, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  store i32 0, ptr %9, align 4, !tbaa !5
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = call i32 @UARTRegConfigModeEnable(i32 noundef %10, i32 noundef 191)
  store volatile i32 %11, ptr %7, align 4, !tbaa !5
  %12 = load i32, ptr %3, align 4, !tbaa !5
  %13 = add i32 %12, 8
  %14 = zext i32 %13 to i64
  %15 = inttoptr i64 %14 to ptr
  %16 = load volatile i32, ptr %15, align 4, !tbaa !5
  %17 = and i32 %16, 16
  store volatile i32 %17, ptr %5, align 4, !tbaa !5
  %18 = load i32, ptr %3, align 4, !tbaa !5
  %19 = add i32 %18, 8
  %20 = zext i32 %19 to i64
  %21 = inttoptr i64 %20 to ptr
  %22 = load volatile i32, ptr %21, align 4, !tbaa !5
  %23 = or i32 %22, 16
  store volatile i32 %23, ptr %21, align 4, !tbaa !5
  %24 = load i32, ptr %3, align 4, !tbaa !5
  %25 = call i32 @UARTRegConfigModeEnable(i32 noundef %24, i32 noundef 127)
  %26 = load i32, ptr %3, align 4, !tbaa !5
  %27 = add i32 %26, 4
  %28 = zext i32 %27 to i64
  %29 = inttoptr i64 %28 to ptr
  %30 = load volatile i32, ptr %29, align 4, !tbaa !5
  %31 = and i32 %30, 16
  store volatile i32 %31, ptr %6, align 4, !tbaa !5
  %32 = load i32, ptr %3, align 4, !tbaa !5
  %33 = add i32 %32, 4
  %34 = zext i32 %33 to i64
  %35 = inttoptr i64 %34 to ptr
  %36 = load volatile i32, ptr %35, align 4, !tbaa !5
  %37 = and i32 %36, -17
  store volatile i32 %37, ptr %35, align 4, !tbaa !5
  %38 = load i32, ptr %3, align 4, !tbaa !5
  %39 = call i32 @UARTRegConfigModeEnable(i32 noundef %38, i32 noundef 191)
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = add i32 %40, 0
  %42 = zext i32 %41 to i64
  %43 = inttoptr i64 %42 to ptr
  %44 = load volatile i32, ptr %43, align 4, !tbaa !5
  %45 = and i32 %44, 255
  store i32 %45, ptr %9, align 4, !tbaa !5
  %46 = load i32, ptr %3, align 4, !tbaa !5
  %47 = add i32 %46, 4
  %48 = zext i32 %47 to i64
  %49 = inttoptr i64 %48 to ptr
  %50 = load volatile i32, ptr %49, align 4, !tbaa !5
  %51 = and i32 %50, 63
  %52 = shl i32 %51, 8
  %53 = load i32, ptr %9, align 4, !tbaa !5
  %54 = or i32 %53, %52
  store i32 %54, ptr %9, align 4, !tbaa !5
  %55 = load i32, ptr %3, align 4, !tbaa !5
  %56 = call i32 @UARTOperatingModeSelect(i32 noundef %55, i32 noundef 7)
  store volatile i32 %56, ptr %8, align 4, !tbaa !5
  %57 = load i32, ptr %4, align 4, !tbaa !5
  %58 = and i32 %57, 255
  %59 = load i32, ptr %3, align 4, !tbaa !5
  %60 = add i32 %59, 0
  %61 = zext i32 %60 to i64
  %62 = inttoptr i64 %61 to ptr
  store volatile i32 %58, ptr %62, align 4, !tbaa !5
  %63 = load i32, ptr %4, align 4, !tbaa !5
  %64 = and i32 %63, 16128
  %65 = lshr i32 %64, 8
  %66 = load i32, ptr %3, align 4, !tbaa !5
  %67 = add i32 %66, 4
  %68 = zext i32 %67 to i64
  %69 = inttoptr i64 %68 to ptr
  store volatile i32 %65, ptr %69, align 4, !tbaa !5
  %70 = load i32, ptr %3, align 4, !tbaa !5
  %71 = load volatile i32, ptr %8, align 4, !tbaa !5
  %72 = call i32 @UARTOperatingModeSelect(i32 noundef %70, i32 noundef %71)
  %73 = load i32, ptr %3, align 4, !tbaa !5
  %74 = call i32 @UARTRegConfigModeEnable(i32 noundef %73, i32 noundef 127)
  %75 = load volatile i32, ptr %6, align 4, !tbaa !5
  %76 = load i32, ptr %3, align 4, !tbaa !5
  %77 = add i32 %76, 4
  %78 = zext i32 %77 to i64
  %79 = inttoptr i64 %78 to ptr
  %80 = load volatile i32, ptr %79, align 4, !tbaa !5
  %81 = or i32 %80, %75
  store volatile i32 %81, ptr %79, align 4, !tbaa !5
  %82 = load i32, ptr %3, align 4, !tbaa !5
  %83 = call i32 @UARTRegConfigModeEnable(i32 noundef %82, i32 noundef 191)
  %84 = load i32, ptr %3, align 4, !tbaa !5
  %85 = add i32 %84, 8
  %86 = zext i32 %85 to i64
  %87 = inttoptr i64 %86 to ptr
  %88 = load volatile i32, ptr %87, align 4, !tbaa !5
  %89 = and i32 %88, -17
  store volatile i32 %89, ptr %87, align 4, !tbaa !5
  %90 = load volatile i32, ptr %5, align 4, !tbaa !5
  %91 = load i32, ptr %3, align 4, !tbaa !5
  %92 = add i32 %91, 8
  %93 = zext i32 %92 to i64
  %94 = inttoptr i64 %93 to ptr
  %95 = load volatile i32, ptr %94, align 4, !tbaa !5
  %96 = or i32 %95, %90
  store volatile i32 %96, ptr %94, align 4, !tbaa !5
  %97 = load volatile i32, ptr %7, align 4, !tbaa !5
  %98 = load i32, ptr %3, align 4, !tbaa !5
  %99 = add i32 %98, 12
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  store volatile i32 %97, ptr %101, align 4, !tbaa !5
  %102 = load i32, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 %102
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTRegConfigModeEnable(i32 noundef, i32 noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTOperatingModeSelect(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 16384) i32 @UARTDivisorLatchWrite(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3)
  store volatile i32 0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4)
  store volatile i32 0, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5)
  store volatile i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6)
  store volatile i32 0, ptr %6, align 4, !tbaa !5
  %7 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 191)
  store volatile i32 %7, ptr %5, align 4, !tbaa !5
  %8 = add i32 %0, 8
  %9 = zext i32 %8 to i64
  %10 = inttoptr i64 %9 to ptr
  %11 = load volatile i32, ptr %10, align 4, !tbaa !5
  %12 = and i32 %11, 16
  store volatile i32 %12, ptr %3, align 4, !tbaa !5
  %13 = load volatile i32, ptr %10, align 4, !tbaa !5
  %14 = or i32 %13, 16
  store volatile i32 %14, ptr %10, align 4, !tbaa !5
  %15 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 127)
  %16 = add i32 %0, 4
  %17 = zext i32 %16 to i64
  %18 = inttoptr i64 %17 to ptr
  %19 = load volatile i32, ptr %18, align 4, !tbaa !5
  %20 = and i32 %19, 16
  store volatile i32 %20, ptr %4, align 4, !tbaa !5
  %21 = load volatile i32, ptr %18, align 4, !tbaa !5
  %22 = and i32 %21, -17
  store volatile i32 %22, ptr %18, align 4, !tbaa !5
  %23 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 191)
  %24 = zext i32 %0 to i64
  %25 = inttoptr i64 %24 to ptr
  %26 = load volatile i32, ptr %25, align 4, !tbaa !5
  %27 = and i32 %26, 255
  %28 = load volatile i32, ptr %18, align 4, !tbaa !5
  %29 = shl i32 %28, 8
  %30 = and i32 %29, 16128
  %31 = or disjoint i32 %30, %27
  %32 = tail call i32 @UARTOperatingModeSelect(i32 noundef %0, i32 noundef 7)
  store volatile i32 %32, ptr %6, align 4, !tbaa !5
  %33 = and i32 %1, 255
  store volatile i32 %33, ptr %25, align 4, !tbaa !5
  %34 = lshr i32 %1, 8
  %35 = and i32 %34, 63
  store volatile i32 %35, ptr %18, align 4, !tbaa !5
  %.0..0..0..0. = load volatile i32, ptr %6, align 4, !tbaa !5
  %36 = tail call i32 @UARTOperatingModeSelect(i32 noundef %0, i32 noundef %.0..0..0..0.)
  %37 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 127)
  %.0..0..0..0.3 = load volatile i32, ptr %4, align 4, !tbaa !5
  %38 = load volatile i32, ptr %18, align 4, !tbaa !5
  %39 = or i32 %38, %.0..0..0..0.3
  store volatile i32 %39, ptr %18, align 4, !tbaa !5
  %40 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 191)
  %41 = load volatile i32, ptr %10, align 4, !tbaa !5
  %42 = and i32 %41, -17
  store volatile i32 %42, ptr %10, align 4, !tbaa !5
  %.0..0..0..0.4 = load volatile i32, ptr %3, align 4, !tbaa !5
  %43 = load volatile i32, ptr %10, align 4, !tbaa !5
  %44 = or i32 %43, %.0..0..0..0.4
  store volatile i32 %44, ptr %10, align 4, !tbaa !5
  %.0..0..0..0.2 = load volatile i32, ptr %5, align 4, !tbaa !5
  %45 = add i32 %0, 12
  %46 = zext i32 %45 to i64
  %47 = inttoptr i64 %46 to ptr
  store volatile i32 %.0..0..0..0.2, ptr %47, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3)
  ret i32 %31
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTRegConfigModeEnable(i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass