; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_pwr_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.PWREx_WakeupPinTypeDef = type { i32, i32, i32 }
%struct.PWR_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.EXTI_TypeDef = type { i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @HAL_PWREx_EnableWakeUpPin(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 196608, ptr %5, align 4, !tbaa !9
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %6, i32 0, i32 0
  %8 = load i32, ptr %7, align 4, !tbaa !11
  %9 = load ptr, ptr %2, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %9, i32 0, i32 1
  %11 = load i32, ptr %10, align 4, !tbaa !13
  %12 = load ptr, ptr %2, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %12, i32 0, i32 0
  %14 = load i32, ptr %13, align 4, !tbaa !11
  %15 = call i32 @__RBIT(i32 noundef %14)
  %16 = call zeroext i8 @__CLZ(i32 noundef %15)
  %17 = zext i8 %16 to i32
  %18 = add i32 %17, 8
  %19 = and i32 %18, 31
  %20 = shl i32 %11, %19
  %21 = or i32 %8, %20
  %22 = load ptr, ptr %2, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %22, i32 0, i32 2
  %24 = load i32, ptr %23, align 4, !tbaa !14
  %25 = load ptr, ptr %2, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %25, i32 0, i32 0
  %27 = load i32, ptr %26, align 4, !tbaa !11
  %28 = call i32 @__RBIT(i32 noundef %27)
  %29 = call zeroext i8 @__CLZ(i32 noundef %28)
  %30 = zext i8 %29 to i32
  %31 = mul i32 %30, 2
  %32 = add i32 %31, 16
  %33 = and i32 %32, 31
  %34 = shl i32 %24, %33
  %35 = or i32 %21, %34
  store i32 %35, ptr %3, align 4, !tbaa !9
  %36 = load ptr, ptr %2, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %36, i32 0, i32 0
  %38 = load i32, ptr %37, align 4, !tbaa !11
  %39 = zext i32 %38 to i64
  %40 = load ptr, ptr %2, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %40, i32 0, i32 0
  %42 = load i32, ptr %41, align 4, !tbaa !11
  %43 = call i32 @__RBIT(i32 noundef %42)
  %44 = call zeroext i8 @__CLZ(i32 noundef %43)
  %45 = zext i8 %44 to i32
  %46 = and i32 %45, 31
  %47 = zext i32 %46 to i64
  %48 = shl i64 256, %47
  %49 = or i64 %39, %48
  %50 = load ptr, ptr %2, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %50, i32 0, i32 0
  %52 = load i32, ptr %51, align 4, !tbaa !11
  %53 = call i32 @__RBIT(i32 noundef %52)
  %54 = call zeroext i8 @__CLZ(i32 noundef %53)
  %55 = zext i8 %54 to i32
  %56 = mul i32 %55, 2
  %57 = and i32 %56, 31
  %58 = shl i32 196608, %57
  %59 = zext i32 %58 to i64
  %60 = or i64 %49, %59
  %61 = trunc i64 %60 to i32
  store i32 %61, ptr %4, align 4, !tbaa !9
  %62 = load volatile i32, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 10), align 4, !tbaa !15
  %63 = load i32, ptr %4, align 4, !tbaa !9
  %64 = xor i32 %63, -1
  %65 = and i32 %62, %64
  %66 = load i32, ptr %3, align 4, !tbaa !9
  %67 = or i32 %65, %66
  store volatile i32 %67, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 10), align 4, !tbaa !15
  %68 = load volatile i32, ptr getelementptr inbounds (%struct.EXTI_TypeDef, ptr inttoptr (i64 1476395008 to ptr), i32 0, i32 25), align 4, !tbaa !17
  %69 = zext i32 %68 to i64
  %70 = and i64 %69, -360710145
  %71 = load ptr, ptr %2, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.PWREx_WakeupPinTypeDef, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 4, !tbaa !11
  %74 = shl i32 %73, 23
  %75 = zext i32 %74 to i64
  %76 = or i64 %70, %75
  %77 = trunc i64 %76 to i32
  store volatile i32 %77, ptr getelementptr inbounds (%struct.EXTI_TypeDef, ptr inttoptr (i64 1476395008 to ptr), i32 0, i32 25), align 4, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__RBIT(i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!13 = !{!12, !10, i64 4}
!14 = !{!12, !10, i64 8}
!15 = !{!16, !10, i64 40}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40}
!17 = !{!18, !10, i64 144}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !7, i64 24, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !7, i64 56, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !7, i64 88, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !10, i64 144, !10, i64 148, !10, i64 152, !10, i64 156, !10, i64 160, !10, i64 164, !10, i64 168}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @HAL_PWREx_EnableWakeUpPin(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  %2 = load i32, ptr %0, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 4
  %4 = load i32, ptr %3, align 4, !tbaa !10
  %5 = tail call i32 @__RBIT(i32 noundef %2)
  %6 = tail call zeroext i8 @__CLZ(i32 noundef %5)
  %7 = add i8 %6, 8
  %8 = and i8 %7, 31
  %9 = zext nneg i8 %8 to i32
  %10 = shl i32 %4, %9
  %11 = getelementptr inbounds i8, ptr %0, i64 8
  %12 = load i32, ptr %11, align 4, !tbaa !11
  %13 = load i32, ptr %0, align 4, !tbaa !5
  %14 = tail call i32 @__RBIT(i32 noundef %13)
  %15 = tail call zeroext i8 @__CLZ(i32 noundef %14)
  %16 = zext i8 %15 to i32
  %17 = shl nuw nsw i32 %16, 1
  %18 = and i32 %17, 30
  %19 = xor i32 %18, 16
  %20 = shl i32 %12, %19
  %21 = load i32, ptr %0, align 4, !tbaa !5
  %22 = tail call i32 @__RBIT(i32 noundef %21)
  %23 = tail call zeroext i8 @__CLZ(i32 noundef %22)
  %24 = and i8 %23, 31
  %25 = zext nneg i8 %24 to i32
  %26 = shl i32 256, %25
  %27 = load i32, ptr %0, align 4, !tbaa !5
  %28 = tail call i32 @__RBIT(i32 noundef %27)
  %29 = tail call zeroext i8 @__CLZ(i32 noundef %28)
  %30 = zext i8 %29 to i32
  %31 = shl nuw nsw i32 %30, 1
  %32 = and i32 %31, 30
  %33 = shl i32 196608, %32
  %34 = or i32 %26, %33
  %35 = or i32 %34, %21
  %36 = load volatile i32, ptr inttoptr (i64 1476544552 to ptr), align 8, !tbaa !12
  %37 = xor i32 %35, -1
  %38 = and i32 %36, %37
  %39 = or i32 %10, %20
  %40 = or i32 %39, %38
  %41 = or i32 %40, %2
  store volatile i32 %41, ptr inttoptr (i64 1476544552 to ptr), align 8, !tbaa !12
  %42 = load volatile i32, ptr inttoptr (i64 1476395152 to ptr), align 16, !tbaa !14
  %43 = and i32 %42, -360710145
  %44 = load i32, ptr %0, align 4, !tbaa !5
  %45 = shl i32 %44, 23
  %46 = or i32 %45, %43
  store volatile i32 %46, ptr inttoptr (i64 1476395152 to ptr), align 16, !tbaa !14
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden zeroext i8 @__CLZ(i32 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__RBIT(i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 4}
!11 = !{!6, !7, i64 8}
!12 = !{!13, !7, i64 40}
!13 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40}
!14 = !{!15, !7, i64 144}
!15 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !8, i64 24, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !8, i64 56, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !8, i64 88, !7, i64 128, !7, i64 132, !7, i64 136, !7, i64 140, !7, i64 144, !7, i64 148, !7, i64 152, !7, i64 156, !7, i64 160, !7, i64 164, !7, i64 168}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass