; LLVM IR from ShahjalalShohag/code-library :: Graph Theory/Dijkstra on Segment Tree.ll (Z3updiiiiiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@add = external dso_local global i32, align 4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z8add_edgeiii(i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3updiiiiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) #2 {
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  store i32 %0, ptr %9, align 4, !tbaa !5
  store i32 %1, ptr %10, align 4, !tbaa !5
  store i32 %2, ptr %11, align 4, !tbaa !5
  store i32 %3, ptr %12, align 4, !tbaa !5
  store i32 %4, ptr %13, align 4, !tbaa !5
  store i32 %5, ptr %14, align 4, !tbaa !5
  store i32 %6, ptr %15, align 4, !tbaa !5
  store i32 %7, ptr %16, align 4, !tbaa !5
  %18 = load i32, ptr %13, align 4, !tbaa !5
  %19 = load i32, ptr %10, align 4, !tbaa !5
  %20 = icmp slt i32 %18, %19
  br i1 %20, label %25, label %21

21:                                               ; preds = %8
  %22 = load i32, ptr %11, align 4, !tbaa !5
  %23 = load i32, ptr %12, align 4, !tbaa !5
  %24 = icmp slt i32 %22, %23
  br i1 %24, label %25, label %26

25:                                               ; preds = %21, %8
  br label %76

26:                                               ; preds = %21
  %27 = load i32, ptr %12, align 4, !tbaa !5
  %28 = load i32, ptr %10, align 4, !tbaa !5
  %29 = icmp sle i32 %27, %28
  br i1 %29, label %30, label %51

30:                                               ; preds = %26
  %31 = load i32, ptr %11, align 4, !tbaa !5
  %32 = load i32, ptr %13, align 4, !tbaa !5
  %33 = icmp sle i32 %31, %32
  br i1 %33, label %34, label %51

34:                                               ; preds = %30
  %35 = load i32, ptr %14, align 4, !tbaa !5
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %37, label %44

37:                                               ; preds = %34
  %38 = load i32, ptr %15, align 4, !tbaa !5
  %39 = load i32, ptr %9, align 4, !tbaa !5
  %40 = load i32, ptr @add, align 4, !tbaa !5
  %41 = mul nsw i32 5, %40
  %42 = add nsw i32 %39, %41
  %43 = load i32, ptr %16, align 4, !tbaa !5
  call void @_Z8add_edgeiii(i32 noundef %38, i32 noundef %42, i32 noundef %43)
  br label %50

44:                                               ; preds = %34
  %45 = load i32, ptr %9, align 4, !tbaa !5
  %46 = load i32, ptr @add, align 4, !tbaa !5
  %47 = add nsw i32 %45, %46
  %48 = load i32, ptr %15, align 4, !tbaa !5
  %49 = load i32, ptr %16, align 4, !tbaa !5
  call void @_Z8add_edgeiii(i32 noundef %47, i32 noundef %48, i32 noundef %49)
  br label %50

50:                                               ; preds = %44, %37
  br label %76

51:                                               ; preds = %30, %26
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #3
  %52 = load i32, ptr %10, align 4, !tbaa !5
  %53 = load i32, ptr %11, align 4, !tbaa !5
  %54 = add nsw i32 %52, %53
  %55 = ashr i32 %54, 1
  store i32 %55, ptr %17, align 4, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !5
  %57 = mul nsw i32 2, %56
  %58 = load i32, ptr %10, align 4, !tbaa !5
  %59 = load i32, ptr %17, align 4, !tbaa !5
  %60 = load i32, ptr %12, align 4, !tbaa !5
  %61 = load i32, ptr %13, align 4, !tbaa !5
  %62 = load i32, ptr %14, align 4, !tbaa !5
  %63 = load i32, ptr %15, align 4, !tbaa !5
  %64 = load i32, ptr %16, align 4, !tbaa !5
  call void @_Z3updiiiiiiii(i32 noundef %57, i32 noundef %58, i32 noundef %59, i32 noundef %60, i32 noundef %61, i32 noundef %62, i32 noundef %63, i32 noundef %64)
  %65 = load i32, ptr %9, align 4, !tbaa !5
  %66 = mul nsw i32 2, %65
  %67 = add nsw i32 %66, 1
  %68 = load i32, ptr %17, align 4, !tbaa !5
  %69 = add nsw i32 %68, 1
  %70 = load i32, ptr %11, align 4, !tbaa !5
  %71 = load i32, ptr %12, align 4, !tbaa !5
  %72 = load i32, ptr %13, align 4, !tbaa !5
  %73 = load i32, ptr %14, align 4, !tbaa !5
  %74 = load i32, ptr %15, align 4, !tbaa !5
  %75 = load i32, ptr %16, align 4, !tbaa !5
  call void @_Z3updiiiiiiii(i32 noundef %67, i32 noundef %69, i32 noundef %70, i32 noundef %71, i32 noundef %72, i32 noundef %73, i32 noundef %74, i32 noundef %75)
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #3
  br label %76

76:                                               ; preds = %51, %50, %25
  ret void
}

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@add = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z8add_edgeiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3updiiiiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #1 {
  %9 = icmp slt i32 %2, %3
  %10 = icmp slt i32 %4, %1
  %or.cond47 = or i1 %9, %10
  br i1 %or.cond47, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %8
  %.not36 = icmp sgt i32 %2, %4
  br i1 %.not36, label %tailrecurse.us, label %.lr.ph.split.split

tailrecurse.us:                                   ; preds = %.lr.ph, %tailrecurse.us
  %.tr3949.us = phi i32 [ %15, %tailrecurse.us ], [ %1, %.lr.ph ]
  %.tr48.us = phi i32 [ %14, %tailrecurse.us ], [ %0, %.lr.ph ]
  %11 = add nsw i32 %.tr3949.us, %2
  %12 = ashr i32 %11, 1
  %13 = shl nsw i32 %.tr48.us, 1
  tail call void @_Z3updiiiiiiii(i32 noundef %13, i32 noundef %.tr3949.us, i32 noundef %12, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7)
  %14 = or disjoint i32 %13, 1
  %15 = add nsw i32 %12, 1
  %.not55 = icmp slt i32 %12, %4
  br i1 %.not55, label %tailrecurse.us, label %.loopexit

.lr.ph.split.split:                               ; preds = %.lr.ph, %tailrecurse
  %.tr3949 = phi i32 [ %26, %tailrecurse ], [ %1, %.lr.ph ]
  %.tr48 = phi i32 [ %25, %tailrecurse ], [ %0, %.lr.ph ]
  %.not = icmp slt i32 %.tr3949, %3
  br i1 %.not, label %tailrecurse, label %.split.us

.split.us:                                        ; preds = %.lr.ph.split.split
  %.not37 = icmp eq i32 %5, 0
  %16 = load i32, ptr @add, align 4, !tbaa !5
  br i1 %.not37, label %20, label %17

17:                                               ; preds = %.split.us
  %18 = mul nsw i32 %16, 5
  %19 = add nsw i32 %18, %.tr48
  tail call void @_Z8add_edgeiii(i32 noundef %6, i32 noundef %19, i32 noundef %7)
  br label %.loopexit

20:                                               ; preds = %.split.us
  %21 = add nsw i32 %16, %.tr48
  tail call void @_Z8add_edgeiii(i32 noundef %21, i32 noundef %6, i32 noundef %7)
  br label %.loopexit

tailrecurse:                                      ; preds = %.lr.ph.split.split
  %22 = add nsw i32 %.tr3949, %2
  %23 = ashr i32 %22, 1
  %24 = shl nsw i32 %.tr48, 1
  tail call void @_Z3updiiiiiiii(i32 noundef %24, i32 noundef %.tr3949, i32 noundef %23, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7)
  %25 = or disjoint i32 %24, 1
  %26 = add nsw i32 %23, 1
  %.not54 = icmp slt i32 %23, %4
  br i1 %.not54, label %.lr.ph.split.split, label %.loopexit

.loopexit:                                        ; preds = %tailrecurse, %tailrecurse.us, %8, %17, %20
  ret void
}

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass