; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@SystemCoreClock = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_DMA_GetError(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_AbortTransfer(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Abort_IT(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 1, ptr %6, align 4, !tbaa !9
  %7 = load ptr, ptr %2, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %7, i32 0, i32 14
  store volatile i32 7, ptr %8, align 4, !tbaa !11
  store i32 0, ptr %3, align 4, !tbaa !9
  %9 = load i32, ptr @SystemCoreClock, align 4, !tbaa !9
  %10 = zext i32 %9 to i64
  %11 = udiv i64 %10, 24
  %12 = udiv i64 %11, 1000
  %13 = mul i64 100, %12
  %14 = trunc i64 %13 to i32
  store volatile i32 %14, ptr %4, align 4, !tbaa !9
  %15 = load ptr, ptr %2, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %15, i32 0, i32 0
  %17 = load ptr, ptr %16, align 8, !tbaa !15
  %18 = getelementptr inbounds %struct.SPI_TypeDef, ptr %17, i32 0, i32 0
  %19 = load volatile i32, ptr %18, align 4, !tbaa !16
  %20 = zext i32 %19 to i64
  %21 = and i64 %20, 512
  %22 = icmp eq i64 %21, 512
  br i1 %22, label %23, label %120

23:                                               ; preds = %1
  %24 = load ptr, ptr %2, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %25, align 8, !tbaa !15
  %27 = getelementptr inbounds %struct.SPI_TypeDef, ptr %26, i32 0, i32 4
  %28 = load volatile i32, ptr %27, align 4, !tbaa !18
  %29 = zext i32 %28 to i64
  %30 = and i64 %29, -9
  %31 = trunc i64 %30 to i32
  store volatile i32 %31, ptr %27, align 4, !tbaa !18
  br label %32

32:                                               ; preds = %46, %23
  %33 = load volatile i32, ptr %4, align 4, !tbaa !9
  %34 = add i32 %33, -1
  store volatile i32 %34, ptr %4, align 4, !tbaa !9
  %35 = load volatile i32, ptr %4, align 4, !tbaa !9
  %36 = zext i32 %35 to i64
  %37 = icmp eq i64 %36, 0
  br i1 %37, label %38, label %45

38:                                               ; preds = %32
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %39, i32 0, i32 15
  %41 = load volatile i32, ptr %40, align 8, !tbaa !19
  %42 = zext i32 %41 to i64
  %43 = or i64 %42, 64
  %44 = trunc i64 %43 to i32
  store volatile i32 %44, ptr %40, align 8, !tbaa !19
  br label %55

45:                                               ; preds = %32
  br label %46

46:                                               ; preds = %45
  %47 = load ptr, ptr %2, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %47, i32 0, i32 0
  %49 = load ptr, ptr %48, align 8, !tbaa !15
  %50 = getelementptr inbounds %struct.SPI_TypeDef, ptr %49, i32 0, i32 4
  %51 = load volatile i32, ptr %50, align 4, !tbaa !18
  %52 = zext i32 %51 to i64
  %53 = and i64 %52, 8
  %54 = icmp eq i64 %53, 8
  br i1 %54, label %32, label %55, !llvm.loop !20

55:                                               ; preds = %46, %38
  %56 = load ptr, ptr %2, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %56, i32 0, i32 0
  %58 = load ptr, ptr %57, align 8, !tbaa !15
  %59 = getelementptr inbounds %struct.SPI_TypeDef, ptr %58, i32 0, i32 0
  %60 = load volatile i32, ptr %59, align 4, !tbaa !16
  %61 = zext i32 %60 to i64
  %62 = or i64 %61, 1024
  %63 = trunc i64 %62 to i32
  store volatile i32 %63, ptr %59, align 4, !tbaa !16
  br label %64

64:                                               ; preds = %78, %55
  %65 = load volatile i32, ptr %4, align 4, !tbaa !9
  %66 = add i32 %65, -1
  store volatile i32 %66, ptr %4, align 4, !tbaa !9
  %67 = load volatile i32, ptr %4, align 4, !tbaa !9
  %68 = zext i32 %67 to i64
  %69 = icmp eq i64 %68, 0
  br i1 %69, label %70, label %77

70:                                               ; preds = %64
  %71 = load ptr, ptr %2, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %71, i32 0, i32 15
  %73 = load volatile i32, ptr %72, align 8, !tbaa !19
  %74 = zext i32 %73 to i64
  %75 = or i64 %74, 64
  %76 = trunc i64 %75 to i32
  store volatile i32 %76, ptr %72, align 8, !tbaa !19
  br label %87

77:                                               ; preds = %64
  br label %78

78:                                               ; preds = %77
  %79 = load ptr, ptr %2, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %79, i32 0, i32 0
  %81 = load ptr, ptr %80, align 8, !tbaa !15
  %82 = getelementptr inbounds %struct.SPI_TypeDef, ptr %81, i32 0, i32 0
  %83 = load volatile i32, ptr %82, align 4, !tbaa !16
  %84 = zext i32 %83 to i64
  %85 = and i64 %84, 512
  %86 = icmp eq i64 %85, 512
  br i1 %86, label %64, label %87, !llvm.loop !22

87:                                               ; preds = %78, %70
  %88 = load ptr, ptr %2, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %88, i32 0, i32 0
  %90 = load ptr, ptr %89, align 8, !tbaa !15
  %91 = getelementptr inbounds %struct.SPI_TypeDef, ptr %90, i32 0, i32 6
  %92 = load volatile i32, ptr %91, align 4, !tbaa !23
  %93 = zext i32 %92 to i64
  %94 = or i64 %93, 2048
  %95 = trunc i64 %94 to i32
  store volatile i32 %95, ptr %91, align 4, !tbaa !23
  br label %96

96:                                               ; preds = %110, %87
  %97 = load volatile i32, ptr %4, align 4, !tbaa !9
  %98 = add i32 %97, -1
  store volatile i32 %98, ptr %4, align 4, !tbaa !9
  %99 = load volatile i32, ptr %4, align 4, !tbaa !9
  %100 = zext i32 %99 to i64
  %101 = icmp eq i64 %100, 0
  br i1 %101, label %102, label %109

102:                                              ; preds = %96
  %103 = load ptr, ptr %2, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %103, i32 0, i32 15
  %105 = load volatile i32, ptr %104, align 8, !tbaa !19
  %106 = zext i32 %105 to i64
  %107 = or i64 %106, 64
  %108 = trunc i64 %107 to i32
  store volatile i32 %108, ptr %104, align 8, !tbaa !19
  br label %119

109:                                              ; preds = %96
  br label %110

110:                                              ; preds = %109
  %111 = load ptr, ptr %2, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %111, i32 0, i32 0
  %113 = load ptr, ptr %112, align 8, !tbaa !15
  %114 = getelementptr inbounds %struct.SPI_TypeDef, ptr %113, i32 0, i32 5
  %115 = load volatile i32, ptr %114, align 4, !tbaa !24
  %116 = zext i32 %115 to i64
  %117 = and i64 %116, 2048
  %118 = icmp eq i64 %117, 2048
  br i1 %118, label %96, label %119, !llvm.loop !25

119:                                              ; preds = %110, %102
  br label %120

120:                                              ; preds = %119, %1
  %121 = load ptr, ptr %2, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %121, i32 0, i32 11
  %123 = load ptr, ptr %122, align 8, !tbaa !26
  %124 = icmp ne ptr %123, null
  br i1 %124, label %125, label %163

125:                                              ; preds = %120
  %126 = load ptr, ptr %2, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %126, i32 0, i32 0
  %128 = load ptr, ptr %127, align 8, !tbaa !15
  %129 = getelementptr inbounds %struct.SPI_TypeDef, ptr %128, i32 0, i32 2
  %130 = load volatile i32, ptr %129, align 4, !tbaa !27
  %131 = zext i32 %130 to i64
  %132 = and i64 %131, 32768
  %133 = icmp eq i64 %132, 32768
  br i1 %133, label %134, label %157

134:                                              ; preds = %125
  %135 = load ptr, ptr %2, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %135, i32 0, i32 11
  %137 = load ptr, ptr %136, align 8, !tbaa !26
  %138 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %137, i32 0, i32 10
  store ptr @SPI_DMATxAbortCallback, ptr %138, align 8, !tbaa !28
  store i32 0, ptr %5, align 4, !tbaa !9
  %139 = load ptr, ptr %2, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %139, i32 0, i32 11
  %141 = load ptr, ptr %140, align 8, !tbaa !26
  %142 = call i32 @HAL_DMA_Abort_IT(ptr noundef %141)
  %143 = icmp ne i32 %142, 0
  br i1 %143, label %144, label %156

144:                                              ; preds = %134
  %145 = load ptr, ptr %2, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %145, i32 0, i32 11
  %147 = load ptr, ptr %146, align 8, !tbaa !26
  %148 = call i32 @HAL_DMA_GetError(ptr noundef %147)
  %149 = icmp eq i32 %148, 128
  br i1 %149, label %150, label %155

150:                                              ; preds = %144
  store i32 1, ptr %5, align 4, !tbaa !9
  %151 = load ptr, ptr %2, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %151, i32 0, i32 11
  %153 = load ptr, ptr %152, align 8, !tbaa !26
  %154 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %153, i32 0, i32 10
  store ptr null, ptr %154, align 8, !tbaa !28
  br label %155

155:                                              ; preds = %150, %144
  br label %156

156:                                              ; preds = %155, %134
  br label %162

157:                                              ; preds = %125
  %158 = load ptr, ptr %2, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %158, i32 0, i32 11
  %160 = load ptr, ptr %159, align 8, !tbaa !26
  %161 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %160, i32 0, i32 10
  store ptr null, ptr %161, align 8, !tbaa !28
  br label %162

162:                                              ; preds = %157, %156
  br label %163

163:                                              ; preds = %162, %120
  %164 = load ptr, ptr %2, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %164, i32 0, i32 12
  %166 = load ptr, ptr %165, align 8, !tbaa !31
  %167 = icmp ne ptr %166, null
  br i1 %167, label %168, label %206

168:                                              ; preds = %163
  %169 = load ptr, ptr %2, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %169, i32 0, i32 0
  %171 = load ptr, ptr %170, align 8, !tbaa !15
  %172 = getelementptr inbounds %struct.SPI_TypeDef, ptr %171, i32 0, i32 2
  %173 = load volatile i32, ptr %172, align 4, !tbaa !27
  %174 = zext i32 %173 to i64
  %175 = and i64 %174, 16384
  %176 = icmp eq i64 %175, 16384
  br i1 %176, label %177, label %200

177:                                              ; preds = %168
  %178 = load ptr, ptr %2, align 8, !tbaa !5
  %179 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %178, i32 0, i32 12
  %180 = load ptr, ptr %179, align 8, !tbaa !31
  %181 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %180, i32 0, i32 10
  store ptr @SPI_DMARxAbortCallback, ptr %181, align 8, !tbaa !28
  store i32 0, ptr %6, align 4, !tbaa !9
  %182 = load ptr, ptr %2, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %182, i32 0, i32 12
  %184 = load ptr, ptr %183, align 8, !tbaa !31
  %185 = call i32 @HAL_DMA_Abort_IT(ptr noundef %184)
  %186 = icmp ne i32 %185, 0
  br i1 %186, label %187, label %199

187:                                              ; preds = %177
  %188 = load ptr, ptr %2, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %188, i32 0, i32 12
  %190 = load ptr, ptr %189, align 8, !tbaa !31
  %191 = call i32 @HAL_DMA_GetError(ptr noundef %190)
  %192 = icmp eq i32 %191, 128
  br i1 %192, label %193, label %198

193:                                              ; preds = %187
  store i32 1, ptr %6, align 4, !tbaa !9
  %194 = load ptr, ptr %2, align 8, !tbaa !5
  %195 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %194, i32 0, i32 12
  %196 = load ptr, ptr %195, align 8, !tbaa !31
  %197 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %196, i32 0, i32 10
  store ptr null, ptr %197, align 8, !tbaa !28
  br label %198

198:                                              ; preds = %193, %187
  br label %199

199:                                              ; preds = %198, %177
  br label %205

200:                                              ; preds = %168
  %201 = load ptr, ptr %2, align 8, !tbaa !5
  %202 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %201, i32 0, i32 12
  %203 = load ptr, ptr %202, align 8, !tbaa !31
  %204 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %203, i32 0, i32 10
  store ptr null, ptr %204, align 8, !tbaa !28
  br label %205

205:                                              ; preds = %200, %199
  br label %206

206:                                              ; preds = %205, %163
  %207 = load i32, ptr %5, align 4, !tbaa !9
  %208 = zext i32 %207 to i64
  %209 = icmp eq i64 %208, 1
  br i1 %209, label %210, label %230

210:                                              ; preds = %206
  %211 = load i32, ptr %6, align 4, !tbaa !9
  %212 = zext i32 %211 to i64
  %213 = icmp eq i64 %212, 1
  br i1 %213, label %214, label %230

214:                                              ; preds = %210
  %215 = load ptr, ptr %2, align 8, !tbaa !5
  call void @SPI_AbortTransfer(ptr noundef %215)
  %216 = load ptr, ptr %2, align 8, !tbaa !5
  %217 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %216, i32 0, i32 15
  %218 = load volatile i32, ptr %217, align 8, !tbaa !19
  %219 = zext i32 %218 to i64
  %220 = and i64 %219, 64
  %221 = icmp eq i64 %220, 64
  br i1 %221, label %222, label %223

222:                                              ; preds = %214
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %226

223:                                              ; preds = %214
  %224 = load ptr, ptr %2, align 8, !tbaa !5
  %225 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %224, i32 0, i32 15
  store volatile i32 0, ptr %225, align 8, !tbaa !19
  br label %226

226:                                              ; preds = %223, %222
  %227 = load ptr, ptr %2, align 8, !tbaa !5
  %228 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %227, i32 0, i32 14
  store volatile i32 1, ptr %228, align 4, !tbaa !11
  %229 = load ptr, ptr %2, align 8, !tbaa !5
  call void @HAL_SPI_AbortCpltCallback(ptr noundef %229)
  br label %230

230:                                              ; preds = %226, %210, %206
  %231 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i32 %231
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATxAbortCallback(ptr noundef) #2

declare i32 @HAL_DMA_Abort_IT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMARxAbortCallback(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_SPI_AbortCpltCallback(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 164}
!12 = !{!"__SPI_HandleTypeDef", !6, i64 0, !13, i64 8, !6, i64 96, !14, i64 104, !14, i64 106, !6, i64 112, !14, i64 120, !14, i64 122, !10, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !10, i64 160, !10, i64 164, !10, i64 168}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !6, i64 0}
!16 = !{!17, !10, i64 0}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !7, i64 36, !10, i64 48, !7, i64 52, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80}
!18 = !{!17, !10, i64 16}
!19 = !{!12, !10, i64 168}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = distinct !{!22, !21}
!23 = !{!17, !10, i64 24}
!24 = !{!17, !10, i64 20}
!25 = distinct !{!25, !21}
!26 = !{!12, !6, i64 144}
!27 = !{!17, !10, i64 8}
!28 = !{!29, !6, i64 112}
!29 = !{!"__DMA_HandleTypeDef", !6, i64 0, !30, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!30 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!31 = !{!12, !6, i64 152}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_DMA_GetError(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_AbortTransfer(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_SPI_Abort_IT(ptr noundef %0) local_unnamed_addr #2 {
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
  %3 = getelementptr inbounds i8, ptr %0, i64 164
  store volatile i32 7, ptr %3, align 4, !tbaa !5
  %4 = load i32, ptr @SystemCoreClock, align 4, !tbaa !13
  %5 = udiv i32 %4, 24000
  %narrow = mul nuw nsw i32 %5, 100
  store volatile i32 %narrow, ptr %2, align 4, !tbaa !13
  %6 = load ptr, ptr %0, align 8, !tbaa !14
  %7 = load volatile i32, ptr %6, align 4, !tbaa !15
  %8 = and i32 %7, 512
  %.not = icmp eq i32 %8, 0
  br i1 %.not, label %.loopexit, label %9

9:                                                ; preds = %1
  %10 = getelementptr inbounds i8, ptr %6, i64 16
  %11 = load volatile i32, ptr %10, align 4, !tbaa !17
  %12 = and i32 %11, -9
  store volatile i32 %12, ptr %10, align 4, !tbaa !17
  br label %13

13:                                               ; preds = %20, %9
  %.0..0..0..0. = load volatile i32, ptr %2, align 4, !tbaa !13
  %14 = add i32 %.0..0..0..0., -1
  store volatile i32 %14, ptr %2, align 4, !tbaa !13
  %.0..0..0..0.4 = load volatile i32, ptr %2, align 4, !tbaa !13
  %15 = icmp eq i32 %.0..0..0..0.4, 0
  br i1 %15, label %16, label %20

16:                                               ; preds = %13
  %17 = getelementptr inbounds i8, ptr %0, i64 168
  %18 = load volatile i32, ptr %17, align 8, !tbaa !18
  %19 = or i32 %18, 64
  store volatile i32 %19, ptr %17, align 8, !tbaa !18
  br label %.loopexit54

20:                                               ; preds = %13
  %21 = load volatile i32, ptr %10, align 4, !tbaa !17
  %22 = and i32 %21, 8
  %.not42 = icmp eq i32 %22, 0
  br i1 %.not42, label %.loopexit54, label %13, !llvm.loop !19

.loopexit54:                                      ; preds = %20, %16
  %23 = load volatile i32, ptr %6, align 4, !tbaa !15
  %24 = or i32 %23, 1024
  store volatile i32 %24, ptr %6, align 4, !tbaa !15
  br label %25

25:                                               ; preds = %32, %.loopexit54
  %.0..0..0..0.5 = load volatile i32, ptr %2, align 4, !tbaa !13
  %26 = add i32 %.0..0..0..0.5, -1
  store volatile i32 %26, ptr %2, align 4, !tbaa !13
  %.0..0..0..0.6 = load volatile i32, ptr %2, align 4, !tbaa !13
  %27 = icmp eq i32 %.0..0..0..0.6, 0
  br i1 %27, label %28, label %32

28:                                               ; preds = %25
  %29 = getelementptr inbounds i8, ptr %0, i64 168
  %30 = load volatile i32, ptr %29, align 8, !tbaa !18
  %31 = or i32 %30, 64
  store volatile i32 %31, ptr %29, align 8, !tbaa !18
  br label %.loopexit53

32:                                               ; preds = %25
  %33 = load volatile i32, ptr %6, align 4, !tbaa !15
  %34 = and i32 %33, 512
  %.not43 = icmp eq i32 %34, 0
  br i1 %.not43, label %.loopexit53, label %25, !llvm.loop !21

.loopexit53:                                      ; preds = %32, %28
  %35 = getelementptr inbounds i8, ptr %6, i64 24
  %36 = load volatile i32, ptr %35, align 4, !tbaa !22
  %37 = or i32 %36, 2048
  store volatile i32 %37, ptr %35, align 4, !tbaa !22
  %38 = getelementptr inbounds i8, ptr %6, i64 20
  br label %39

39:                                               ; preds = %46, %.loopexit53
  %.0..0..0..0.7 = load volatile i32, ptr %2, align 4, !tbaa !13
  %40 = add i32 %.0..0..0..0.7, -1
  store volatile i32 %40, ptr %2, align 4, !tbaa !13
  %.0..0..0..0.8 = load volatile i32, ptr %2, align 4, !tbaa !13
  %41 = icmp eq i32 %.0..0..0..0.8, 0
  br i1 %41, label %42, label %46

42:                                               ; preds = %39
  %43 = getelementptr inbounds i8, ptr %0, i64 168
  %44 = load volatile i32, ptr %43, align 8, !tbaa !18
  %45 = or i32 %44, 64
  store volatile i32 %45, ptr %43, align 8, !tbaa !18
  br label %.loopexit

46:                                               ; preds = %39
  %47 = load volatile i32, ptr %38, align 4, !tbaa !23
  %48 = and i32 %47, 2048
  %.not44 = icmp eq i32 %48, 0
  br i1 %.not44, label %.loopexit, label %39, !llvm.loop !24

.loopexit:                                        ; preds = %46, %42, %1
  %49 = getelementptr inbounds i8, ptr %0, i64 144
  %50 = load ptr, ptr %49, align 8, !tbaa !25
  %.not45 = icmp eq ptr %50, null
  br i1 %.not45, label %65, label %51

51:                                               ; preds = %.loopexit
  %52 = getelementptr inbounds i8, ptr %6, i64 8
  %53 = load volatile i32, ptr %52, align 4, !tbaa !26
  %54 = and i32 %53, 32768
  %.not46 = icmp eq i32 %54, 0
  %55 = getelementptr inbounds i8, ptr %50, i64 112
  br i1 %.not46, label %.sink.split, label %56

56:                                               ; preds = %51
  store ptr @SPI_DMATxAbortCallback, ptr %55, align 8, !tbaa !27
  %57 = tail call i32 @HAL_DMA_Abort_IT(ptr noundef nonnull %50) #3
  %.not47 = icmp eq i32 %57, 0
  br i1 %.not47, label %65, label %58

58:                                               ; preds = %56
  %59 = load ptr, ptr %49, align 8, !tbaa !25
  %60 = tail call i32 @HAL_DMA_GetError(ptr noundef %59) #3
  %61 = icmp eq i32 %60, 128
  br i1 %61, label %62, label %65

62:                                               ; preds = %58
  %63 = load ptr, ptr %49, align 8, !tbaa !25
  %64 = getelementptr inbounds i8, ptr %63, i64 112
  br label %.sink.split

.sink.split:                                      ; preds = %51, %62
  %.sink = phi ptr [ %64, %62 ], [ %55, %51 ]
  store ptr null, ptr %.sink, align 8, !tbaa !27
  br label %65

65:                                               ; preds = %.sink.split, %58, %56, %.loopexit
  %66 = phi i1 [ false, %58 ], [ false, %56 ], [ true, %.loopexit ], [ true, %.sink.split ]
  %67 = getelementptr inbounds i8, ptr %0, i64 152
  %68 = load ptr, ptr %67, align 8, !tbaa !30
  %.not48 = icmp eq ptr %68, null
  br i1 %.not48, label %84, label %69

69:                                               ; preds = %65
  %70 = load ptr, ptr %0, align 8, !tbaa !14
  %71 = getelementptr inbounds i8, ptr %70, i64 8
  %72 = load volatile i32, ptr %71, align 4, !tbaa !26
  %73 = and i32 %72, 16384
  %.not49 = icmp eq i32 %73, 0
  %74 = getelementptr inbounds i8, ptr %68, i64 112
  br i1 %.not49, label %.sink.split55, label %75

75:                                               ; preds = %69
  store ptr @SPI_DMARxAbortCallback, ptr %74, align 8, !tbaa !27
  %76 = tail call i32 @HAL_DMA_Abort_IT(ptr noundef nonnull %68) #3
  %.not50 = icmp eq i32 %76, 0
  br i1 %.not50, label %.thread, label %77

77:                                               ; preds = %75
  %78 = load ptr, ptr %67, align 8, !tbaa !30
  %79 = tail call i32 @HAL_DMA_GetError(ptr noundef %78) #3
  %80 = icmp eq i32 %79, 128
  br i1 %80, label %81, label %.thread

81:                                               ; preds = %77
  %82 = load ptr, ptr %67, align 8, !tbaa !30
  %83 = getelementptr inbounds i8, ptr %82, i64 112
  br label %.sink.split55

.sink.split55:                                    ; preds = %69, %81
  %.sink56 = phi ptr [ %83, %81 ], [ %74, %69 ]
  store ptr null, ptr %.sink56, align 8, !tbaa !27
  br label %84

84:                                               ; preds = %.sink.split55, %65
  br i1 %66, label %85, label %.thread

85:                                               ; preds = %84
  tail call void @SPI_AbortTransfer(ptr noundef nonnull %0)
  %86 = getelementptr inbounds i8, ptr %0, i64 168
  %87 = load volatile i32, ptr %86, align 8, !tbaa !18
  %88 = and i32 %87, 64
  %.not51 = icmp eq i32 %88, 0
  br i1 %.not51, label %89, label %90

89:                                               ; preds = %85
  store volatile i32 0, ptr %86, align 8, !tbaa !18
  br label %90

90:                                               ; preds = %85, %89
  %.041 = phi i32 [ 0, %89 ], [ 1, %85 ]
  store volatile i32 1, ptr %3, align 4, !tbaa !5
  tail call void @HAL_SPI_AbortCpltCallback(ptr noundef nonnull %0)
  br label %.thread

.thread:                                          ; preds = %75, %77, %90, %84
  %.1 = phi i32 [ %.041, %90 ], [ 0, %84 ], [ 0, %77 ], [ 0, %75 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
  ret i32 %.1
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATxAbortCallback(ptr noundef) #2

declare i32 @HAL_DMA_Abort_IT(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMARxAbortCallback(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_SPI_AbortCpltCallback(ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 164}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!11, !11, i64 0}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !11, i64 0}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!17 = !{!16, !11, i64 16}
!18 = !{!6, !11, i64 168}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = distinct !{!21, !20}
!22 = !{!16, !11, i64 24}
!23 = !{!16, !11, i64 20}
!24 = distinct !{!24, !20}
!25 = !{!6, !7, i64 144}
!26 = !{!16, !11, i64 8}
!27 = !{!28, !7, i64 112}
!28 = !{!"__DMA_HandleTypeDef", !7, i64 0, !29, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!29 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!30 = !{!6, !7, i64 152}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass