; LLVM IR from fritzsedlazeck/SURVIVOR :: src/simulator/test_cov.ll (Z10get_SV_posii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl" }
%"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl" = type { %"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SV_sim = type { i32, i32 }

; Function Attrs: mustprogress uwtable
define dso_local void @_Z10get_SV_posii(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8 %0, i32 noundef %1, i32 noundef %2) #0 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i1, align 1
  %8 = alloca %struct.SV_sim, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  store ptr %0, ptr %4, align 8
  store i32 %1, ptr %5, align 4, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !5
  store i1 false, ptr %7, align 1
  call void @_ZNSt6vectorI6SV_simSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %12 = getelementptr inbounds %struct.SV_sim, ptr %8, i32 0, i32 1
  store i32 0, ptr %12, align 4, !tbaa !9
  %13 = load i32, ptr %5, align 4, !tbaa !5
  %14 = sext i32 %13 to i64
  invoke void @_ZNSt6vectorI6SV_simSaIS0_EE6resizeEmRKS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %14, ptr noundef nonnull align 4 dereferenceable(8) %8)
          to label %15 unwind label %21

15:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  store i64 0, ptr %11, align 8, !tbaa !11
  br label %16

16:                                               ; preds = %32, %15
  %17 = load i64, ptr %11, align 8, !tbaa !11
  %18 = call noundef i64 @_ZNKSt6vectorI6SV_simSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  %19 = icmp ult i64 %17, %18
  br i1 %19, label %25, label %20

20:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  br label %35

21:                                               ; preds = %3
  %22 = landingpad { ptr, i32 }
          cleanup
  %23 = extractvalue { ptr, i32 } %22, 0
  store ptr %23, ptr %9, align 8
  %24 = extractvalue { ptr, i32 } %22, 1
  store i32 %24, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @_ZNSt6vectorI6SV_simSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %39

25:                                               ; preds = %16
  %26 = call i32 @rand() #4
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = srem i32 %26, %27
  %29 = load i64, ptr %11, align 8, !tbaa !11
  %30 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI6SV_simSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %29) #4
  %31 = getelementptr inbounds %struct.SV_sim, ptr %30, i32 0, i32 0
  store i32 %28, ptr %31, align 4, !tbaa !13
  br label %32

32:                                               ; preds = %25
  %33 = load i64, ptr %11, align 8, !tbaa !11
  %34 = add i64 %33, 1
  store i64 %34, ptr %11, align 8, !tbaa !11
  br label %16, !llvm.loop !14

35:                                               ; preds = %20
  store i1 true, ptr %7, align 1
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %36 = load i1, ptr %7, align 1
  br i1 %36, label %38, label %37

37:                                               ; preds = %35
  call void @_ZNSt6vectorI6SV_simSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %38

38:                                               ; preds = %37, %35
  ret void

39:                                               ; preds = %21
  %40 = load ptr, ptr %9, align 8
  %41 = load i32, ptr %10, align 4
  %42 = insertvalue { ptr, i32 } poison, ptr %40, 0
  %43 = insertvalue { ptr, i32 } %42, i32 %41, 1
  resume { ptr, i32 } %43
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EE6resizeEmRKS0_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8)) #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI6SV_simSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: nounwind
declare i32 @rand() #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI6SV_simSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 4}
!10 = !{!"_ZTS6SV_sim", !6, i64 0, !6, i64 4}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!10, !6, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl" }
%"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl" = type { %"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SV_sim, std::allocator<SV_sim>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.SV_sim = type { i32, i32 }

; Function Attrs: mustprogress uwtable
define dso_local void @_Z10get_SV_posii(ptr dead_on_unwind noalias nonnull writable sret(%"class.std::vector") align 8 %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  %4 = alloca %struct.SV_sim, align 4
  tail call void @_ZNSt6vectorI6SV_simSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #4
  %5 = getelementptr inbounds i8, ptr %4, i64 4
  store i32 0, ptr %5, align 4, !tbaa !5
  %6 = sext i32 %1 to i64
  invoke void @_ZNSt6vectorI6SV_simSaIS0_EE6resizeEmRKS0_(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %6, ptr noundef nonnull align 4 dereferenceable(8) %4)
          to label %.preheader unwind label %8

.preheader:                                       ; preds = %3
  %7 = call noundef i64 @_ZNKSt6vectorI6SV_simSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  %.not = icmp eq i64 %7, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #4
  ret void

8:                                                ; preds = %3
  %9 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #4
  call void @_ZNSt6vectorI6SV_simSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  resume { ptr, i32 } %9

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %.07 = phi i64 [ %13, %.lr.ph ], [ 0, %.preheader ]
  %10 = call i32 @rand() #4
  %11 = srem i32 %10, %2
  %12 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI6SV_simSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.07) #4
  store i32 %11, ptr %12, align 4, !tbaa !10
  %13 = add nuw i64 %.07, 1
  %14 = call noundef i64 @_ZNKSt6vectorI6SV_simSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  %15 = icmp ult i64 %13, %14
  br i1 %15, label %.lr.ph, label %._crit_edge, !llvm.loop !11
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EE6resizeEmRKS0_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI6SV_simSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: nounwind
declare i32 @rand() local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI6SV_simSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI6SV_simSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTS6SV_sim", !7, i64 0, !7, i64 4}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass