; LLVM IR from balintbalazs/B3D :: source/src/B3D_cudaCompress/CPU (HuffmanCPU)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cudaCompress::HuffmanDecodeTableCPU" = type { %"class.std::vector.5", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.10" }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<cudaCompress::HuffmanEntry, std::allocator<cudaCompress::HuffmanEntry>>::_Vector_impl" }
%"struct.std::_Vector_base<cudaCompress::HuffmanEntry, std::allocator<cudaCompress::HuffmanEntry>>::_Vector_impl" = type { %"struct.std::_Vector_base<cudaCompress::HuffmanEntry, std::allocator<cudaCompress::HuffmanEntry>>::_Vector_impl_data" }
%"struct.std::_Vector_base<cudaCompress::HuffmanEntry, std::allocator<cudaCompress::HuffmanEntry>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.cudaCompress::HuffmanEntry" = type { i16, i32, i32 }

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [97 x i8], align 1
@__PRETTY_FUNCTION__._ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE = external hidden unnamed_addr constant [119 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN12cudaCompress12HuffmanEntryESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE(ptr noundef nonnull align 8 dereferenceable(28) %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(96) %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %14

14:                                               ; preds = %83, %4
  %15 = load i32, ptr %9, align 4, !tbaa !9
  %16 = load i32, ptr %6, align 4, !tbaa !9
  %17 = icmp ult i32 %15, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %86

19:                                               ; preds = %14
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  %21 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %20, i32 0, i32 3
  %22 = call noundef zeroext i1 @_ZNKSt6vectorIiSaIiEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #5
  br i1 %22, label %76, label %23

23:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 0, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %24

24:                                               ; preds = %41, %23
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  store i32 0, ptr %12, align 4, !tbaa !9
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = call noundef i32 @_ZN12cudaCompress17BitStreamReadOnly7readBitERj(ptr noundef nonnull align 8 dereferenceable(28) %25, ptr noundef nonnull align 4 dereferenceable(4) %12)
  %27 = load i32, ptr %10, align 4, !tbaa !9
  %28 = add i32 %27, 1
  store i32 %28, ptr %10, align 4, !tbaa !9
  %29 = load i32, ptr %11, align 4, !tbaa !9
  %30 = shl i32 %29, 1
  store i32 %30, ptr %11, align 4, !tbaa !9
  %31 = load i32, ptr %12, align 4, !tbaa !9
  %32 = load i32, ptr %11, align 4, !tbaa !9
  %33 = or i32 %32, %31
  store i32 %33, ptr %11, align 4, !tbaa !9
  %34 = load i32, ptr %10, align 4, !tbaa !9
  %35 = zext i32 %34 to i64
  %36 = icmp ult i64 %35, 32
  br i1 %36, label %37, label %38

37:                                               ; preds = %24
  br label %40

38:                                               ; preds = %24
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 38, ptr noundef @__PRETTY_FUNCTION__._ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE) #6
  unreachable

39:                                               ; No predecessors!
  br label %40

40:                                               ; preds = %39, %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  br label %41

41:                                               ; preds = %40
  %42 = load i32, ptr %11, align 4, !tbaa !9
  %43 = load ptr, ptr %8, align 8, !tbaa !5
  %44 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %43, i32 0, i32 3
  %45 = load i32, ptr %10, align 4, !tbaa !9
  %46 = sub i32 %45, 1
  %47 = zext i32 %46 to i64
  %48 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %44, i64 noundef %47) #5
  %49 = load i32, ptr %48, align 4, !tbaa !9
  %50 = icmp sgt i32 %42, %49
  br i1 %50, label %24, label %51, !llvm.loop !11

51:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  %52 = load ptr, ptr %8, align 8, !tbaa !5
  %53 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %52, i32 0, i32 1
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = sub i32 %54, 1
  %56 = zext i32 %55 to i64
  %57 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %56) #5
  %58 = load i32, ptr %57, align 4, !tbaa !9
  %59 = load i32, ptr %11, align 4, !tbaa !9
  %60 = add nsw i32 %58, %59
  %61 = load ptr, ptr %8, align 8, !tbaa !5
  %62 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %61, i32 0, i32 2
  %63 = load i32, ptr %10, align 4, !tbaa !9
  %64 = sub i32 %63, 1
  %65 = zext i32 %64 to i64
  %66 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %65) #5
  %67 = load i32, ptr %66, align 4, !tbaa !9
  %68 = sub nsw i32 %60, %67
  store i32 %68, ptr %13, align 4, !tbaa !9
  %69 = load ptr, ptr %7, align 8, !tbaa !5
  %70 = load ptr, ptr %8, align 8, !tbaa !5
  %71 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %70, i32 0, i32 0
  %72 = load i32, ptr %13, align 4, !tbaa !9
  %73 = zext i32 %72 to i64
  %74 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN12cudaCompress12HuffmanEntryESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %71, i64 noundef %73) #5
  %75 = getelementptr inbounds %"struct.cudaCompress::HuffmanEntry", ptr %74, i32 0, i32 0
  call void @_ZNSt6vectorItSaItEE9push_backERKt(ptr noundef nonnull align 8 dereferenceable(24) %69, ptr noundef nonnull align 2 dereferenceable(2) %75)
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  br label %82

76:                                               ; preds = %19
  %77 = load ptr, ptr %7, align 8, !tbaa !5
  %78 = load ptr, ptr %8, align 8, !tbaa !5
  %79 = getelementptr inbounds %"class.cudaCompress::HuffmanDecodeTableCPU", ptr %78, i32 0, i32 0
  %80 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN12cudaCompress12HuffmanEntryESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %79, i64 noundef 0) #5
  %81 = getelementptr inbounds %"struct.cudaCompress::HuffmanEntry", ptr %80, i32 0, i32 0
  call void @_ZNSt6vectorItSaItEE9push_backERKt(ptr noundef nonnull align 8 dereferenceable(24) %77, ptr noundef nonnull align 2 dereferenceable(2) %81)
  br label %82

82:                                               ; preds = %76, %51
  br label %83

83:                                               ; preds = %82
  %84 = load i32, ptr %9, align 4, !tbaa !9
  %85 = add i32 %84, 1
  store i32 %85, ptr %9, align 4, !tbaa !9
  br label %14, !llvm.loop !13

86:                                               ; preds = %18
  ret i1 true
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt6vectorIiSaIiEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN12cudaCompress17BitStreamReadOnly7readBitERj(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4)) #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorItSaItEE9push_backERKt(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 2 dereferenceable(2)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [97 x i8], align 1
@__PRETTY_FUNCTION__._ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE = external hidden unnamed_addr constant [119 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN12cudaCompress12HuffmanEntryESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE(ptr noundef nonnull align 8 dereferenceable(28) %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(96) %3) local_unnamed_addr #2 {
  %5 = alloca i32, align 4
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %4
  %6 = getelementptr inbounds i8, ptr %3, i64 72
  %7 = getelementptr inbounds i8, ptr %3, i64 24
  %8 = getelementptr inbounds i8, ptr %3, i64 48
  br label %9

._crit_edge:                                      ; preds = %28, %4
  ret i1 true

9:                                                ; preds = %.lr.ph, %28
  %.026 = phi i32 [ 0, %.lr.ph ], [ %30, %28 ]
  %10 = call noundef zeroext i1 @_ZNKSt6vectorIiSaIiEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #5
  br i1 %10, label %28, label %.preheader

.preheader:                                       ; preds = %9, %13
  %indvars.iv = phi i64 [ %indvars.iv.next, %13 ], [ 0, %9 ]
  %.021 = phi i32 [ %16, %13 ], [ 0, %9 ]
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #5
  store i32 0, ptr %5, align 4, !tbaa !5
  %11 = call noundef i32 @_ZN12cudaCompress17BitStreamReadOnly7readBitERj(ptr noundef nonnull align 8 dereferenceable(28) %0, ptr noundef nonnull align 4 dereferenceable(4) %5)
  %exitcond.not = icmp eq i64 %indvars.iv, 31
  br i1 %exitcond.not, label %12, label %13

12:                                               ; preds = %.preheader
  call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 38, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN12cudaCompress16huffmanDecodeCPUERNS_17BitStreamReadOnlyEjRSt6vectorItSaItEERKNS_21HuffmanDecodeTableCPUE) #6
  unreachable

13:                                               ; preds = %.preheader
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = shl i32 %.021, 1
  %16 = or i32 %14, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #5
  %17 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %indvars.iv) #5
  %18 = load i32, ptr %17, align 4, !tbaa !5
  %19 = icmp sgt i32 %16, %18
  br i1 %19, label %.preheader, label %20, !llvm.loop !9

20:                                               ; preds = %13
  %21 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %indvars.iv) #5
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = add nsw i32 %22, %16
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv) #5
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = sub i32 %23, %25
  %27 = zext i32 %26 to i64
  br label %28

28:                                               ; preds = %9, %20
  %.sink31 = phi i64 [ %27, %20 ], [ 0, %9 ]
  %29 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN12cudaCompress12HuffmanEntryESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %.sink31) #5
  call void @_ZNSt6vectorItSaItEE9push_backERKt(ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 2 dereferenceable(2) %29)
  %30 = add nuw i32 %.026, 1
  %exitcond29.not = icmp eq i32 %30, %1
  br i1 %exitcond29.not, label %._crit_edge, label %9, !llvm.loop !11
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt6vectorIiSaIiEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN12cudaCompress17BitStreamReadOnly7readBitERj(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorItSaItEE9push_backERKt(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 2 dereferenceable(2)) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass