; LLVM IR from VastoLorde95/Competitive-Programming :: Hackerrank/Week of Code/Week 20/Problem F/FFF.ll (Z3getii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FenwickRMQ = type <{ %"class.std::vector", %"class.std::vector", i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@segmentTree = external dso_local global [200200 x %struct.FenwickRMQ], align 16
@d = external dso_local global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z3getii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 1000000000, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = load i32, ptr @d, align 4, !tbaa !5
  %12 = add nsw i32 %10, %11
  store i32 %12, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = load i32, ptr @d, align 4, !tbaa !5
  %15 = add nsw i32 %13, %14
  store i32 %15, ptr %7, align 4, !tbaa !5
  br label %16

16:                                               ; preds = %48, %2
  %17 = load i32, ptr %6, align 4, !tbaa !5
  %18 = load i32, ptr %7, align 4, !tbaa !5
  %19 = icmp slt i32 %17, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %53

21:                                               ; preds = %16
  %22 = load i32, ptr %6, align 4, !tbaa !5
  %23 = and i32 %22, 1
  %24 = icmp ne i32 %23, 0
  br i1 %24, label %25, label %34

25:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %26 = load i32, ptr %6, align 4, !tbaa !5
  %27 = add nsw i32 %26, 1
  store i32 %27, ptr %6, align 4, !tbaa !5
  %28 = sext i32 %26 to i64
  %29 = getelementptr inbounds [200200 x %struct.FenwickRMQ], ptr @segmentTree, i64 0, i64 %28
  %30 = load i32, ptr %4, align 4, !tbaa !5
  %31 = call noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52) %29, i32 noundef %30)
  store i32 %31, ptr %8, align 4, !tbaa !5
  %32 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %33 = load i32, ptr %32, align 4, !tbaa !5
  store i32 %33, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %34

34:                                               ; preds = %25, %21
  %35 = load i32, ptr %7, align 4, !tbaa !5
  %36 = and i32 %35, 1
  %37 = icmp ne i32 %36, 0
  br i1 %37, label %38, label %47

38:                                               ; preds = %34
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %39 = load i32, ptr %7, align 4, !tbaa !5
  %40 = add nsw i32 %39, -1
  store i32 %40, ptr %7, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds [200200 x %struct.FenwickRMQ], ptr @segmentTree, i64 0, i64 %41
  %43 = load i32, ptr %4, align 4, !tbaa !5
  %44 = call noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52) %42, i32 noundef %43)
  store i32 %44, ptr %9, align 4, !tbaa !5
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %9)
  %46 = load i32, ptr %45, align 4, !tbaa !5
  store i32 %46, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %47

47:                                               ; preds = %38, %34
  br label %48

48:                                               ; preds = %47
  %49 = load i32, ptr %6, align 4, !tbaa !5
  %50 = ashr i32 %49, 1
  store i32 %50, ptr %6, align 4, !tbaa !5
  %51 = load i32, ptr %7, align 4, !tbaa !5
  %52 = ashr i32 %51, 1
  store i32 %52, ptr %7, align 4, !tbaa !5
  br label %16, !llvm.loop !9

53:                                               ; preds = %20
  %54 = load i32, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 %54
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FenwickRMQ = type <{ %"class.std::vector", %"class.std::vector", i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@segmentTree = external dso_local global [200200 x %struct.FenwickRMQ], align 16
@d = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z3getii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #3
  store i32 1000000000, ptr %3, align 4, !tbaa !5
  %6 = icmp slt i32 %0, %1
  br i1 %6, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %2
  %7 = load i32, ptr @d, align 4, !tbaa !5
  %8 = add nsw i32 %7, %1
  %9 = add nsw i32 %7, %0
  br label %.lr.ph

._crit_edge:                                      ; preds = %30, %2
  %10 = phi i32 [ 1000000000, %2 ], [ %31, %30 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #3
  ret i32 %10

.lr.ph:                                           ; preds = %.lr.ph.preheader, %30
  %11 = phi i32 [ %31, %30 ], [ 1000000000, %.lr.ph.preheader ]
  %.016 = phi i32 [ %33, %30 ], [ %8, %.lr.ph.preheader ]
  %.01215 = phi i32 [ %32, %30 ], [ %9, %.lr.ph.preheader ]
  %12 = and i32 %.01215, 1
  %.not = icmp eq i32 %12, 0
  br i1 %.not, label %20, label %13

13:                                               ; preds = %.lr.ph
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #3
  %14 = add nsw i32 %.01215, 1
  %15 = sext i32 %.01215 to i64
  %16 = getelementptr inbounds [200200 x %struct.FenwickRMQ], ptr @segmentTree, i64 0, i64 %15
  %17 = call noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52) %16, i32 noundef %1)
  store i32 %17, ptr %4, align 4, !tbaa !5
  %18 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4)
  %19 = load i32, ptr %18, align 4, !tbaa !5
  store i32 %19, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #3
  br label %20

20:                                               ; preds = %13, %.lr.ph
  %21 = phi i32 [ %19, %13 ], [ %11, %.lr.ph ]
  %.113 = phi i32 [ %14, %13 ], [ %.01215, %.lr.ph ]
  %22 = and i32 %.016, 1
  %.not14 = icmp eq i32 %22, 0
  br i1 %.not14, label %30, label %23

23:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #3
  %24 = add nsw i32 %.016, -1
  %25 = sext i32 %24 to i64
  %26 = getelementptr inbounds [200200 x %struct.FenwickRMQ], ptr @segmentTree, i64 0, i64 %25
  %27 = call noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52) %26, i32 noundef %1)
  store i32 %27, ptr %5, align 4, !tbaa !5
  %28 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %5)
  %29 = load i32, ptr %28, align 4, !tbaa !5
  store i32 %29, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #3
  br label %30

30:                                               ; preds = %20, %23
  %31 = phi i32 [ %29, %23 ], [ %21, %20 ]
  %.1 = phi i32 [ %24, %23 ], [ %.016, %20 ]
  %32 = ashr i32 %.113, 1
  %33 = ashr i32 %.1, 1
  %34 = icmp slt i32 %32, %33
  br i1 %34, label %.lr.ph, label %._crit_edge, !llvm.loop !9
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN10FenwickRMQ5queryEi(ptr noundef nonnull align 8 dereferenceable(52), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass