; LLVM IR from Simple-XX/SimpleKernel :: src/drv/tui/tui.ll (ZN3TUI10escapeconvEc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.pos_t = type { i8, i8 }
%class.col_t = type { i8 }
%class.char_t = type { i8, %class.col_t }

@_ZN3TUI3posE = external dso_local global %class.pos_t, align 1
@_ZN3TUI5colorE = external dso_local global %class.col_t, align 1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3TUI5writeEm6char_t(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef, ptr noundef) #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN3TUI10escapeconvEc(ptr noundef nonnull align 8 dereferenceable(8) %0, i8 noundef signext %1) #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca %class.char_t, align 1
  %7 = alloca %class.col_t, align 1
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  %10 = load ptr, ptr %4, align 8
  %11 = load i8, ptr %5, align 1, !tbaa !9
  %12 = sext i8 %11 to i32
  switch i32 %12, label %57 [
    i32 10, label %13
    i32 9, label %16
    i32 8, label %33
  ]

13:                                               ; preds = %2
  %14 = load i8, ptr getelementptr inbounds (%class.pos_t, ptr @_ZN3TUI3posE, i32 0, i32 1), align 1, !tbaa !10
  %15 = add i8 %14, 1
  store i8 %15, ptr getelementptr inbounds (%class.pos_t, ptr @_ZN3TUI3posE, i32 0, i32 1), align 1, !tbaa !10
  store i8 0, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  store i1 true, ptr %3, align 1
  br label %58

16:                                               ; preds = %2
  %17 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %18 = zext i8 %17 to i32
  %19 = srem i32 %18, 4
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  br label %27

22:                                               ; preds = %16
  %23 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %24 = zext i8 %23 to i32
  %25 = srem i32 %24, 4
  %26 = sub nsw i32 4, %25
  br label %27

27:                                               ; preds = %22, %21
  %28 = phi i32 [ 4, %21 ], [ %26, %22 ]
  %29 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %30 = zext i8 %29 to i32
  %31 = add nsw i32 %30, %28
  %32 = trunc i32 %31 to i8
  store i8 %32, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  store i1 true, ptr %3, align 1
  br label %58

33:                                               ; preds = %2
  %34 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %35 = zext i8 %34 to i32
  %36 = icmp sgt i32 %35, 0
  br i1 %36, label %37, label %56

37:                                               ; preds = %33
  %38 = load i8, ptr getelementptr inbounds (%class.pos_t, ptr @_ZN3TUI3posE, i32 0, i32 1), align 1, !tbaa !10
  %39 = zext i8 %38 to i64
  %40 = mul i64 %39, 80
  %41 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %42 = add i8 %41, -1
  store i8 %42, ptr @_ZN3TUI3posE, align 1, !tbaa !12
  %43 = zext i8 %42 to i64
  %44 = add i64 %40, %43
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %7, ptr align 1 @_ZN3TUI5colorE, i64 1, i1 false), !tbaa.struct !13
  invoke void @_ZN6char_tC1Eh5col_t(ptr noundef nonnull align 1 dereferenceable(2) %6, i8 noundef zeroext 32, ptr noundef %7)
          to label %45 unwind label %47

45:                                               ; preds = %37
  invoke void @_ZN3TUI5writeEm6char_t(ptr noundef nonnull align 8 dereferenceable(8) %10, i64 noundef %44, ptr noundef %6)
          to label %46 unwind label %51

46:                                               ; preds = %45
  call void @_ZN6char_tD1Ev(ptr noundef nonnull align 1 dereferenceable(2) %6) #3
  call void @_ZN5col_tD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %7) #3
  br label %56

47:                                               ; preds = %37
  %48 = landingpad { ptr, i32 }
          cleanup
  %49 = extractvalue { ptr, i32 } %48, 0
  store ptr %49, ptr %8, align 8
  %50 = extractvalue { ptr, i32 } %48, 1
  store i32 %50, ptr %9, align 4
  br label %55

51:                                               ; preds = %45
  %52 = landingpad { ptr, i32 }
          cleanup
  %53 = extractvalue { ptr, i32 } %52, 0
  store ptr %53, ptr %8, align 8
  %54 = extractvalue { ptr, i32 } %52, 1
  store i32 %54, ptr %9, align 4
  call void @_ZN6char_tD1Ev(ptr noundef nonnull align 1 dereferenceable(2) %6) #3
  br label %55

55:                                               ; preds = %51, %47
  call void @_ZN5col_tD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %7) #3
  br label %60

56:                                               ; preds = %46, %33
  store i1 true, ptr %3, align 1
  br label %58

57:                                               ; preds = %2
  store i1 false, ptr %3, align 1
  br label %58

58:                                               ; preds = %57, %56, %27, %13
  %59 = load i1, ptr %3, align 1
  ret i1 %59

60:                                               ; preds = %55
  %61 = load ptr, ptr %8, align 8
  %62 = load i32, ptr %9, align 4
  %63 = insertvalue { ptr, i32 } poison, ptr %61, 0
  %64 = insertvalue { ptr, i32 } %63, i32 %62, 1
  resume { ptr, i32 } %64
}

declare void @_ZN5col_tD1Ev(ptr)

declare void @_ZN6char_tC1Eh5col_t(ptr, i8, ptr)

declare void @_ZN6char_tD1Ev(ptr)

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !7, i64 1}
!11 = !{!"_ZTS5pos_t", !7, i64 0, !7, i64 1}
!12 = !{!11, !7, i64 0}
!13 = !{i64 0, i64 1, !9}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.pos_t = type { i8, i8 }
%class.col_t = type { i8 }
%class.char_t = type { i8, %class.col_t }

@_ZN3TUI3posE = external dso_local local_unnamed_addr global %class.pos_t, align 1
@_ZN3TUI5colorE = external dso_local local_unnamed_addr global %class.col_t, align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3TUI5writeEm6char_t(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef, ptr noundef) local_unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN3TUI10escapeconvEc(ptr noundef nonnull align 8 dereferenceable(8) %0, i8 noundef signext %1) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca %class.char_t, align 1
  %4 = alloca %class.col_t, align 1
  switch i8 %1, label %24 [
    i8 10, label %5
    i8 9, label %8
    i8 8, label %11
  ]

5:                                                ; preds = %2
  %6 = load i8, ptr getelementptr inbounds (i8, ptr @_ZN3TUI3posE, i64 1), align 1, !tbaa !5
  %7 = add i8 %6, 1
  store i8 %7, ptr getelementptr inbounds (i8, ptr @_ZN3TUI3posE, i64 1), align 1, !tbaa !5
  store i8 0, ptr @_ZN3TUI3posE, align 1, !tbaa !9
  br label %24

8:                                                ; preds = %2
  %9 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !9
  %reass.sub = and i8 %9, -4
  %10 = add i8 %reass.sub, 4
  store i8 %10, ptr @_ZN3TUI3posE, align 1, !tbaa !9
  br label %24

11:                                               ; preds = %2
  %12 = load i8, ptr @_ZN3TUI3posE, align 1, !tbaa !9
  %.not = icmp eq i8 %12, 0
  br i1 %.not, label %24, label %13

13:                                               ; preds = %11
  %14 = load i8, ptr getelementptr inbounds (i8, ptr @_ZN3TUI3posE, i64 1), align 1, !tbaa !5
  %15 = add i8 %12, -1
  store i8 %15, ptr @_ZN3TUI3posE, align 1, !tbaa !9
  %16 = load i8, ptr @_ZN3TUI5colorE, align 1, !tbaa !10
  store i8 %16, ptr %4, align 1, !tbaa !10
  invoke void @_ZN6char_tC1Eh5col_t(ptr noundef nonnull align 1 dereferenceable(2) %3, i8 noundef zeroext 32, ptr noundef nonnull %4)
          to label %17 unwind label %22

17:                                               ; preds = %13
  %18 = zext i8 %14 to i64
  %19 = mul nuw nsw i64 %18, 80
  %20 = zext i8 %15 to i64
  %21 = add nuw nsw i64 %19, %20
  call void @_ZN3TUI5writeEm6char_t(ptr noundef nonnull align 8 dereferenceable(8) %0, i64 noundef %21, ptr noundef nonnull %3)
  call void @_ZN6char_tD1Ev(ptr noundef nonnull align 1 dereferenceable(2) %3) #2
  call void @_ZN5col_tD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %4) #2
  br label %24

22:                                               ; preds = %13
  %23 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN5col_tD1Ev(ptr noundef nonnull align 1 dereferenceable(1) %4) #2
  resume { ptr, i32 } %23

24:                                               ; preds = %2, %11, %17, %8, %5
  %.0 = phi i1 [ true, %8 ], [ true, %5 ], [ true, %17 ], [ true, %11 ], [ false, %2 ]
  ret i1 %.0
}

declare void @_ZN5col_tD1Ev(ptr) local_unnamed_addr

declare void @_ZN6char_tC1Eh5col_t(ptr, i8, ptr) local_unnamed_addr

declare void @_ZN6char_tD1Ev(ptr) local_unnamed_addr

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 1}
!6 = !{!"_ZTS5pos_t", !7, i64 0, !7, i64 1}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!6, !7, i64 0}
!10 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass