; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %11, i32 0, i32 13
  %13 = load i32, ptr %12, align 8, !tbaa !13
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %17, i32 0, i32 13
  store i32 1, ptr %18, align 8, !tbaa !13
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %22, i32 0, i32 14
  %24 = load volatile i32, ptr %23, align 4, !tbaa !16
  %25 = icmp ne i32 %24, 1
  br i1 %25, label %26, label %33

26:                                               ; preds = %21
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %27

27:                                               ; preds = %26
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %28, i32 0, i32 13
  store i32 0, ptr %29, align 8, !tbaa !13
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  %32 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %32, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

33:                                               ; preds = %21
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = icmp eq ptr %34, null
  br i1 %35, label %40, label %36

36:                                               ; preds = %33
  %37 = load i16, ptr %7, align 2, !tbaa !9
  %38 = zext i16 %37 to i64
  %39 = icmp eq i64 %38, 0
  br i1 %39, label %40, label %47

40:                                               ; preds = %36, %33
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %41

41:                                               ; preds = %40
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %42, i32 0, i32 13
  store i32 0, ptr %43, align 8, !tbaa !13
  br label %44

44:                                               ; preds = %41
  br label %45

45:                                               ; preds = %44
  %46 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %46, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

47:                                               ; preds = %36
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %48, i32 0, i32 14
  store volatile i32 4, ptr %49, align 4, !tbaa !16
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %50, i32 0, i32 15
  store volatile i32 0, ptr %51, align 8, !tbaa !17
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %53, i32 0, i32 5
  store ptr %52, ptr %54, align 8, !tbaa !18
  %55 = load i16, ptr %7, align 2, !tbaa !9
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %56, i32 0, i32 6
  store i16 %55, ptr %57, align 8, !tbaa !19
  %58 = load i16, ptr %7, align 2, !tbaa !9
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %59, i32 0, i32 7
  store volatile i16 %58, ptr %60, align 2, !tbaa !20
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %61, i32 0, i32 9
  store ptr null, ptr %62, align 8, !tbaa !21
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %63, i32 0, i32 10
  store ptr null, ptr %64, align 8, !tbaa !22
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %65, i32 0, i32 3
  store i16 0, ptr %66, align 8, !tbaa !23
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %67, i32 0, i32 4
  store volatile i16 0, ptr %68, align 2, !tbaa !24
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %69, i32 0, i32 1
  %71 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %70, i32 0, i32 1
  %72 = load i32, ptr %71, align 4, !tbaa !25
  %73 = zext i32 %72 to i64
  %74 = icmp eq i64 %73, 393216
  br i1 %74, label %75, label %84

75:                                               ; preds = %47
  %76 = load ptr, ptr %5, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %76, i32 0, i32 0
  %78 = load ptr, ptr %77, align 8, !tbaa !26
  %79 = getelementptr inbounds %struct.SPI_TypeDef, ptr %78, i32 0, i32 0
  %80 = load volatile i32, ptr %79, align 4, !tbaa !27
  %81 = zext i32 %80 to i64
  %82 = and i64 %81, -2049
  %83 = trunc i64 %82 to i32
  store volatile i32 %83, ptr %79, align 4, !tbaa !27
  br label %98

84:                                               ; preds = %47
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %85, i32 0, i32 0
  %87 = load ptr, ptr %86, align 8, !tbaa !26
  %88 = getelementptr inbounds %struct.SPI_TypeDef, ptr %87, i32 0, i32 3
  %89 = load volatile i32, ptr %88, align 4, !tbaa !29
  %90 = zext i32 %89 to i64
  %91 = and i64 %90, -393217
  %92 = or i64 %91, 262144
  %93 = trunc i64 %92 to i32
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !26
  %97 = getelementptr inbounds %struct.SPI_TypeDef, ptr %96, i32 0, i32 3
  store volatile i32 %93, ptr %97, align 4, !tbaa !29
  br label %98

98:                                               ; preds = %84, %75
  %99 = load ptr, ptr %5, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %99, i32 0, i32 1
  %101 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %100, i32 0, i32 2
  %102 = load i32, ptr %101, align 8, !tbaa !30
  %103 = zext i32 %102 to i64
  %104 = icmp ugt i64 %103, 15
  br i1 %104, label %105, label %113

105:                                              ; preds = %98
  %106 = load ptr, ptr %5, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %106, i32 0, i32 12
  %108 = load ptr, ptr %107, align 8, !tbaa !31
  %109 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %108, i32 0, i32 1
  %110 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %109, i32 0, i32 5
  %111 = load i32, ptr %110, align 4, !tbaa !32
  %112 = icmp ne i32 %111, 16384
  br i1 %112, label %136, label %113

113:                                              ; preds = %105, %98
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %114, i32 0, i32 1
  %116 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %115, i32 0, i32 2
  %117 = load i32, ptr %116, align 8, !tbaa !30
  %118 = zext i32 %117 to i64
  %119 = icmp ugt i64 %118, 7
  br i1 %119, label %120, label %143

120:                                              ; preds = %113
  %121 = load ptr, ptr %5, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %121, i32 0, i32 12
  %123 = load ptr, ptr %122, align 8, !tbaa !31
  %124 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %123, i32 0, i32 1
  %125 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %124, i32 0, i32 5
  %126 = load i32, ptr %125, align 4, !tbaa !32
  %127 = icmp ne i32 %126, 8192
  br i1 %127, label %128, label %143

128:                                              ; preds = %120
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %129, i32 0, i32 12
  %131 = load ptr, ptr %130, align 8, !tbaa !31
  %132 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %131, i32 0, i32 1
  %133 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %132, i32 0, i32 5
  %134 = load i32, ptr %133, align 4, !tbaa !32
  %135 = icmp ne i32 %134, 16384
  br i1 %135, label %136, label %143

136:                                              ; preds = %128, %105
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %137

137:                                              ; preds = %136
  %138 = load ptr, ptr %5, align 8, !tbaa !5
  %139 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %138, i32 0, i32 13
  store i32 0, ptr %139, align 8, !tbaa !13
  br label %140

140:                                              ; preds = %137
  br label %141

141:                                              ; preds = %140
  %142 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %142, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

143:                                              ; preds = %128, %120, %113
  %144 = load ptr, ptr %5, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %144, i32 0, i32 0
  %146 = load ptr, ptr %145, align 8, !tbaa !26
  %147 = getelementptr inbounds %struct.SPI_TypeDef, ptr %146, i32 0, i32 2
  %148 = load volatile i32, ptr %147, align 4, !tbaa !35
  %149 = zext i32 %148 to i64
  %150 = and i64 %149, -16385
  %151 = trunc i64 %150 to i32
  store volatile i32 %151, ptr %147, align 4, !tbaa !35
  %152 = load ptr, ptr %5, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %152, i32 0, i32 1
  %154 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %153, i32 0, i32 2
  %155 = load i32, ptr %154, align 8, !tbaa !30
  %156 = zext i32 %155 to i64
  %157 = icmp ule i64 %156, 7
  br i1 %157, label %158, label %195

158:                                              ; preds = %143
  %159 = load ptr, ptr %5, align 8, !tbaa !5
  %160 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %159, i32 0, i32 12
  %161 = load ptr, ptr %160, align 8, !tbaa !31
  %162 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %161, i32 0, i32 1
  %163 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %162, i32 0, i32 5
  %164 = load i32, ptr %163, align 4, !tbaa !32
  %165 = icmp eq i32 %164, 8192
  br i1 %165, label %166, label %176

166:                                              ; preds = %158
  %167 = load ptr, ptr %5, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %167, i32 0, i32 7
  %169 = load volatile i16, ptr %168, align 2, !tbaa !20
  %170 = zext i16 %169 to i32
  %171 = add nsw i32 %170, 1
  %172 = ashr i32 %171, 1
  %173 = trunc i32 %172 to i16
  %174 = load ptr, ptr %5, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %174, i32 0, i32 7
  store volatile i16 %173, ptr %175, align 2, !tbaa !20
  br label %176

176:                                              ; preds = %166, %158
  %177 = load ptr, ptr %5, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %177, i32 0, i32 12
  %179 = load ptr, ptr %178, align 8, !tbaa !31
  %180 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %179, i32 0, i32 1
  %181 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %180, i32 0, i32 5
  %182 = load i32, ptr %181, align 4, !tbaa !32
  %183 = icmp eq i32 %182, 16384
  br i1 %183, label %184, label %194

184:                                              ; preds = %176
  %185 = load ptr, ptr %5, align 8, !tbaa !5
  %186 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %185, i32 0, i32 7
  %187 = load volatile i16, ptr %186, align 2, !tbaa !20
  %188 = zext i16 %187 to i32
  %189 = add nsw i32 %188, 3
  %190 = ashr i32 %189, 2
  %191 = trunc i32 %190 to i16
  %192 = load ptr, ptr %5, align 8, !tbaa !5
  %193 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %192, i32 0, i32 7
  store volatile i16 %191, ptr %193, align 2, !tbaa !20
  br label %194

194:                                              ; preds = %184, %176
  br label %223

195:                                              ; preds = %143
  %196 = load ptr, ptr %5, align 8, !tbaa !5
  %197 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %196, i32 0, i32 1
  %198 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %197, i32 0, i32 2
  %199 = load i32, ptr %198, align 8, !tbaa !30
  %200 = zext i32 %199 to i64
  %201 = icmp ule i64 %200, 15
  br i1 %201, label %202, label %221

202:                                              ; preds = %195
  %203 = load ptr, ptr %5, align 8, !tbaa !5
  %204 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %203, i32 0, i32 12
  %205 = load ptr, ptr %204, align 8, !tbaa !31
  %206 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %205, i32 0, i32 1
  %207 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %206, i32 0, i32 5
  %208 = load i32, ptr %207, align 4, !tbaa !32
  %209 = icmp eq i32 %208, 16384
  br i1 %209, label %210, label %220

210:                                              ; preds = %202
  %211 = load ptr, ptr %5, align 8, !tbaa !5
  %212 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %211, i32 0, i32 7
  %213 = load volatile i16, ptr %212, align 2, !tbaa !20
  %214 = zext i16 %213 to i32
  %215 = add nsw i32 %214, 1
  %216 = ashr i32 %215, 1
  %217 = trunc i32 %216 to i16
  %218 = load ptr, ptr %5, align 8, !tbaa !5
  %219 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %218, i32 0, i32 7
  store volatile i16 %217, ptr %219, align 2, !tbaa !20
  br label %220

220:                                              ; preds = %210, %202
  br label %222

221:                                              ; preds = %195
  br label %222

222:                                              ; preds = %221, %220
  br label %223

223:                                              ; preds = %222, %194
  %224 = load ptr, ptr %5, align 8, !tbaa !5
  %225 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %224, i32 0, i32 12
  %226 = load ptr, ptr %225, align 8, !tbaa !31
  %227 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %226, i32 0, i32 6
  store ptr @SPI_DMAHalfReceiveCplt, ptr %227, align 8, !tbaa !36
  %228 = load ptr, ptr %5, align 8, !tbaa !5
  %229 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %228, i32 0, i32 12
  %230 = load ptr, ptr %229, align 8, !tbaa !31
  %231 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %230, i32 0, i32 5
  store ptr @SPI_DMAReceiveCplt, ptr %231, align 8, !tbaa !37
  %232 = load ptr, ptr %5, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %232, i32 0, i32 12
  %234 = load ptr, ptr %233, align 8, !tbaa !31
  %235 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %234, i32 0, i32 9
  store ptr @SPI_DMAError, ptr %235, align 8, !tbaa !38
  %236 = load ptr, ptr %5, align 8, !tbaa !5
  %237 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %236, i32 0, i32 12
  %238 = load ptr, ptr %237, align 8, !tbaa !31
  %239 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %238, i32 0, i32 10
  store ptr null, ptr %239, align 8, !tbaa !39
  %240 = load ptr, ptr %5, align 8, !tbaa !5
  %241 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %240, i32 0, i32 12
  %242 = load ptr, ptr %241, align 8, !tbaa !31
  %243 = load ptr, ptr %5, align 8, !tbaa !5
  %244 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %243, i32 0, i32 0
  %245 = load ptr, ptr %244, align 8, !tbaa !26
  %246 = getelementptr inbounds %struct.SPI_TypeDef, ptr %245, i32 0, i32 10
  %247 = ptrtoint ptr %246 to i32
  %248 = load ptr, ptr %5, align 8, !tbaa !5
  %249 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %248, i32 0, i32 5
  %250 = load ptr, ptr %249, align 8, !tbaa !18
  %251 = ptrtoint ptr %250 to i32
  %252 = load ptr, ptr %5, align 8, !tbaa !5
  %253 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %252, i32 0, i32 7
  %254 = load volatile i16, ptr %253, align 2, !tbaa !20
  %255 = zext i16 %254 to i32
  %256 = call i32 @HAL_DMA_Start_IT(ptr noundef %242, i32 noundef %247, i32 noundef %251, i32 noundef %255)
  %257 = icmp ne i32 0, %256
  br i1 %257, label %258, label %273

258:                                              ; preds = %223
  %259 = load ptr, ptr %5, align 8, !tbaa !5
  %260 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %259, i32 0, i32 15
  %261 = load volatile i32, ptr %260, align 8, !tbaa !17
  %262 = zext i32 %261 to i64
  %263 = or i64 %262, 16
  %264 = trunc i64 %263 to i32
  store volatile i32 %264, ptr %260, align 8, !tbaa !17
  br label %265

265:                                              ; preds = %258
  %266 = load ptr, ptr %5, align 8, !tbaa !5
  %267 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %266, i32 0, i32 13
  store i32 0, ptr %267, align 8, !tbaa !13
  br label %268

268:                                              ; preds = %265
  br label %269

269:                                              ; preds = %268
  %270 = load ptr, ptr %5, align 8, !tbaa !5
  %271 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %270, i32 0, i32 14
  store volatile i32 1, ptr %271, align 4, !tbaa !16
  store i32 1, ptr %8, align 4, !tbaa !11
  %272 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %272, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

273:                                              ; preds = %223
  %274 = load ptr, ptr %5, align 8, !tbaa !5
  %275 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %274, i32 0, i32 12
  %276 = load ptr, ptr %275, align 8, !tbaa !31
  %277 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %276, i32 0, i32 1
  %278 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %277, i32 0, i32 6
  %279 = load i32, ptr %278, align 8, !tbaa !40
  %280 = icmp eq i32 %279, 256
  br i1 %280, label %281, label %295

281:                                              ; preds = %273
  %282 = load ptr, ptr %5, align 8, !tbaa !5
  %283 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %282, i32 0, i32 0
  %284 = load ptr, ptr %283, align 8, !tbaa !26
  %285 = getelementptr inbounds %struct.SPI_TypeDef, ptr %284, i32 0, i32 1
  %286 = load volatile i32, ptr %285, align 4, !tbaa !41
  %287 = zext i32 %286 to i64
  %288 = and i64 %287, -65536
  %289 = or i64 %288, 0
  %290 = trunc i64 %289 to i32
  %291 = load ptr, ptr %5, align 8, !tbaa !5
  %292 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %291, i32 0, i32 0
  %293 = load ptr, ptr %292, align 8, !tbaa !26
  %294 = getelementptr inbounds %struct.SPI_TypeDef, ptr %293, i32 0, i32 1
  store volatile i32 %290, ptr %294, align 4, !tbaa !41
  br label %311

295:                                              ; preds = %273
  %296 = load ptr, ptr %5, align 8, !tbaa !5
  %297 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %296, i32 0, i32 0
  %298 = load ptr, ptr %297, align 8, !tbaa !26
  %299 = getelementptr inbounds %struct.SPI_TypeDef, ptr %298, i32 0, i32 1
  %300 = load volatile i32, ptr %299, align 4, !tbaa !41
  %301 = zext i32 %300 to i64
  %302 = and i64 %301, -65536
  %303 = load i16, ptr %7, align 2, !tbaa !9
  %304 = zext i16 %303 to i64
  %305 = or i64 %302, %304
  %306 = trunc i64 %305 to i32
  %307 = load ptr, ptr %5, align 8, !tbaa !5
  %308 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %307, i32 0, i32 0
  %309 = load ptr, ptr %308, align 8, !tbaa !26
  %310 = getelementptr inbounds %struct.SPI_TypeDef, ptr %309, i32 0, i32 1
  store volatile i32 %306, ptr %310, align 4, !tbaa !41
  br label %311

311:                                              ; preds = %295, %281
  %312 = load ptr, ptr %5, align 8, !tbaa !5
  %313 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %312, i32 0, i32 0
  %314 = load ptr, ptr %313, align 8, !tbaa !26
  %315 = getelementptr inbounds %struct.SPI_TypeDef, ptr %314, i32 0, i32 2
  %316 = load volatile i32, ptr %315, align 4, !tbaa !35
  %317 = zext i32 %316 to i64
  %318 = or i64 %317, 16384
  %319 = trunc i64 %318 to i32
  store volatile i32 %319, ptr %315, align 4, !tbaa !35
  %320 = load ptr, ptr %5, align 8, !tbaa !5
  %321 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %320, i32 0, i32 0
  %322 = load ptr, ptr %321, align 8, !tbaa !26
  %323 = getelementptr inbounds %struct.SPI_TypeDef, ptr %322, i32 0, i32 4
  %324 = load volatile i32, ptr %323, align 4, !tbaa !42
  %325 = zext i32 %324 to i64
  %326 = or i64 %325, 832
  %327 = trunc i64 %326 to i32
  store volatile i32 %327, ptr %323, align 4, !tbaa !42
  %328 = load ptr, ptr %5, align 8, !tbaa !5
  %329 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %328, i32 0, i32 0
  %330 = load ptr, ptr %329, align 8, !tbaa !26
  %331 = getelementptr inbounds %struct.SPI_TypeDef, ptr %330, i32 0, i32 0
  %332 = load volatile i32, ptr %331, align 4, !tbaa !27
  %333 = zext i32 %332 to i64
  %334 = or i64 %333, 1
  %335 = trunc i64 %334 to i32
  store volatile i32 %335, ptr %331, align 4, !tbaa !27
  %336 = load ptr, ptr %5, align 8, !tbaa !5
  %337 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %336, i32 0, i32 1
  %338 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %337, i32 0, i32 0
  %339 = load i32, ptr %338, align 8, !tbaa !43
  %340 = zext i32 %339 to i64
  %341 = icmp eq i64 %340, 4194304
  br i1 %341, label %342, label %351

342:                                              ; preds = %311
  %343 = load ptr, ptr %5, align 8, !tbaa !5
  %344 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %343, i32 0, i32 0
  %345 = load ptr, ptr %344, align 8, !tbaa !26
  %346 = getelementptr inbounds %struct.SPI_TypeDef, ptr %345, i32 0, i32 0
  %347 = load volatile i32, ptr %346, align 4, !tbaa !27
  %348 = zext i32 %347 to i64
  %349 = or i64 %348, 512
  %350 = trunc i64 %349 to i32
  store volatile i32 %350, ptr %346, align 4, !tbaa !27
  br label %351

351:                                              ; preds = %342, %311
  br label %352

352:                                              ; preds = %351
  %353 = load ptr, ptr %5, align 8, !tbaa !5
  %354 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %353, i32 0, i32 13
  store i32 0, ptr %354, align 8, !tbaa !13
  br label %355

355:                                              ; preds = %352
  br label %356

356:                                              ; preds = %355
  %357 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %357, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %358

358:                                              ; preds = %356, %269, %141, %45, %31, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %359 = load i32, ptr %4, align 4
  ret i32 %359
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfReceiveCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAReceiveCplt(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 160}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 164}
!17 = !{!14, !12, i64 168}
!18 = !{!14, !6, i64 112}
!19 = !{!14, !10, i64 120}
!20 = !{!14, !10, i64 122}
!21 = !{!14, !6, i64 128}
!22 = !{!14, !6, i64 136}
!23 = !{!14, !10, i64 104}
!24 = !{!14, !10, i64 106}
!25 = !{!14, !12, i64 12}
!26 = !{!14, !6, i64 0}
!27 = !{!28, !12, i64 0}
!28 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!29 = !{!28, !12, i64 12}
!30 = !{!14, !12, i64 16}
!31 = !{!14, !6, i64 152}
!32 = !{!33, !12, i64 28}
!33 = !{!"__DMA_HandleTypeDef", !6, i64 0, !34, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!34 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!35 = !{!28, !12, i64 8}
!36 = !{!33, !6, i64 80}
!37 = !{!33, !6, i64 72}
!38 = !{!33, !6, i64 104}
!39 = !{!33, !6, i64 112}
!40 = !{!33, !12, i64 32}
!41 = !{!28, !12, i64 4}
!42 = !{!28, !12, i64 16}
!43 = !{!14, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SPI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 160
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %125, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 164
  %9 = load volatile i32, ptr %8, align 4, !tbaa !13
  %.not = icmp eq i32 %9, 1
  br i1 %.not, label %11, label %10

10:                                               ; preds = %7
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %125

11:                                               ; preds = %7
  %12 = icmp eq ptr %1, null
  %13 = icmp eq i16 %2, 0
  %or.cond = or i1 %12, %13
  br i1 %or.cond, label %14, label %15

14:                                               ; preds = %11
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %125

15:                                               ; preds = %11
  store volatile i32 4, ptr %8, align 4, !tbaa !13
  %16 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %16, align 8, !tbaa !14
  %17 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr %1, ptr %17, align 8, !tbaa !15
  %18 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 %2, ptr %18, align 8, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %0, i64 122
  store volatile i16 %2, ptr %19, align 2, !tbaa !17
  %20 = getelementptr inbounds i8, ptr %0, i64 128
  %21 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 0, ptr %21, align 8, !tbaa !18
  %22 = getelementptr inbounds i8, ptr %0, i64 106
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %20, i8 0, i64 16, i1 false)
  store volatile i16 0, ptr %22, align 2, !tbaa !19
  %23 = getelementptr inbounds i8, ptr %0, i64 8
  %24 = getelementptr inbounds i8, ptr %0, i64 12
  %25 = load i32, ptr %24, align 4, !tbaa !20
  %26 = icmp eq i32 %25, 393216
  %27 = load ptr, ptr %0, align 8, !tbaa !21
  br i1 %26, label %28, label %31

28:                                               ; preds = %15
  %29 = load volatile i32, ptr %27, align 4, !tbaa !22
  %30 = and i32 %29, -2049
  store volatile i32 %30, ptr %27, align 4, !tbaa !22
  br label %36

31:                                               ; preds = %15
  %32 = getelementptr inbounds i8, ptr %27, i64 12
  %33 = load volatile i32, ptr %32, align 4, !tbaa !24
  %34 = and i32 %33, -393217
  %35 = or disjoint i32 %34, 262144
  store volatile i32 %35, ptr %32, align 4, !tbaa !24
  br label %36

36:                                               ; preds = %31, %28
  %37 = getelementptr inbounds i8, ptr %0, i64 16
  %38 = load i32, ptr %37, align 8, !tbaa !25
  %39 = icmp ugt i32 %38, 15
  br i1 %39, label %40, label %45

40:                                               ; preds = %36
  %41 = getelementptr inbounds i8, ptr %0, i64 152
  %42 = load ptr, ptr %41, align 8, !tbaa !26
  %43 = getelementptr inbounds i8, ptr %42, i64 28
  %44 = load i32, ptr %43, align 4, !tbaa !27
  %.not75 = icmp eq i32 %44, 16384
  br i1 %.not75, label %67, label %47

45:                                               ; preds = %36
  %46 = icmp ugt i32 %38, 7
  br i1 %46, label %.thread, label %48

.thread:                                          ; preds = %45
  %.phi.trans.insert = getelementptr inbounds i8, ptr %0, i64 152
  %.pre = load ptr, ptr %.phi.trans.insert, align 8, !tbaa !26
  %.phi.trans.insert81 = getelementptr inbounds i8, ptr %.pre, i64 28
  %.pre82 = load i32, ptr %.phi.trans.insert81, align 4, !tbaa !27
  switch i32 %.pre82, label %47 [
    i32 8192, label %71
    i32 16384, label %71
  ]

47:                                               ; preds = %.thread, %40
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %125

48:                                               ; preds = %45
  %49 = getelementptr inbounds i8, ptr %27, i64 8
  %50 = load volatile i32, ptr %49, align 4, !tbaa !30
  %51 = and i32 %50, -16385
  store volatile i32 %51, ptr %49, align 4, !tbaa !30
  %52 = getelementptr inbounds i8, ptr %0, i64 152
  %53 = load ptr, ptr %52, align 8, !tbaa !26
  %54 = getelementptr inbounds i8, ptr %53, i64 28
  %55 = load i32, ptr %54, align 4, !tbaa !27
  switch i32 %55, label %82 [
    i32 8192, label %.thread80
    i32 16384, label %61
  ]

.thread80:                                        ; preds = %48
  %56 = load volatile i16, ptr %19, align 2, !tbaa !17
  %57 = zext i16 %56 to i32
  %58 = add nuw nsw i32 %57, 1
  %59 = lshr i32 %58, 1
  %60 = trunc nuw i32 %59 to i16
  store volatile i16 %60, ptr %19, align 2, !tbaa !17
  br label %82

61:                                               ; preds = %48
  %62 = load volatile i16, ptr %19, align 2, !tbaa !17
  %63 = zext i16 %62 to i32
  %64 = add nuw nsw i32 %63, 3
  %65 = lshr i32 %64, 2
  %66 = trunc nuw nsw i32 %65 to i16
  store volatile i16 %66, ptr %19, align 2, !tbaa !17
  br label %82

67:                                               ; preds = %40
  %68 = getelementptr inbounds i8, ptr %27, i64 8
  %69 = load volatile i32, ptr %68, align 4, !tbaa !30
  %70 = and i32 %69, -16385
  store volatile i32 %70, ptr %68, align 4, !tbaa !30
  br label %82

71:                                               ; preds = %.thread, %.thread
  %72 = getelementptr inbounds i8, ptr %27, i64 8
  %73 = load volatile i32, ptr %72, align 4, !tbaa !30
  %74 = and i32 %73, -16385
  store volatile i32 %74, ptr %72, align 4, !tbaa !30
  %75 = icmp eq i32 %.pre82, 16384
  br i1 %75, label %76, label %82

76:                                               ; preds = %71
  %77 = load volatile i16, ptr %19, align 2, !tbaa !17
  %78 = zext i16 %77 to i32
  %79 = add nuw nsw i32 %78, 1
  %80 = lshr i32 %79, 1
  %81 = trunc nuw i32 %80 to i16
  store volatile i16 %81, ptr %19, align 2, !tbaa !17
  br label %82

82:                                               ; preds = %67, %48, %.thread80, %76, %71, %61
  %83 = phi ptr [ %53, %48 ], [ %53, %.thread80 ], [ %.pre, %76 ], [ %.pre, %71 ], [ %42, %67 ], [ %53, %61 ]
  %84 = getelementptr inbounds i8, ptr %83, i64 80
  store ptr @SPI_DMAHalfReceiveCplt, ptr %84, align 8, !tbaa !31
  %85 = getelementptr inbounds i8, ptr %83, i64 72
  store ptr @SPI_DMAReceiveCplt, ptr %85, align 8, !tbaa !32
  %86 = getelementptr inbounds i8, ptr %83, i64 104
  store ptr @SPI_DMAError, ptr %86, align 8, !tbaa !33
  %87 = getelementptr inbounds i8, ptr %83, i64 112
  store ptr null, ptr %87, align 8, !tbaa !34
  %88 = getelementptr inbounds i8, ptr %27, i64 48
  %89 = ptrtoint ptr %88 to i64
  %90 = trunc i64 %89 to i32
  %91 = ptrtoint ptr %1 to i64
  %92 = trunc i64 %91 to i32
  %93 = load volatile i16, ptr %19, align 2, !tbaa !17
  %94 = zext i16 %93 to i32
  %95 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %83, i32 noundef %90, i32 noundef %92, i32 noundef %94) #3
  %.not78 = icmp eq i32 %95, 0
  br i1 %.not78, label %99, label %96

96:                                               ; preds = %82
  %97 = load volatile i32, ptr %16, align 8, !tbaa !14
  %98 = or i32 %97, 16
  store volatile i32 %98, ptr %16, align 8, !tbaa !14
  store i32 0, ptr %4, align 8, !tbaa !5
  store volatile i32 1, ptr %8, align 4, !tbaa !13
  br label %125

99:                                               ; preds = %82
  %100 = getelementptr inbounds i8, ptr %0, i64 152
  %101 = load ptr, ptr %100, align 8, !tbaa !26
  %102 = getelementptr inbounds i8, ptr %101, i64 32
  %103 = load i32, ptr %102, align 8, !tbaa !35
  %104 = icmp eq i32 %103, 256
  %105 = load ptr, ptr %0, align 8, !tbaa !21
  %106 = getelementptr inbounds i8, ptr %105, i64 4
  %107 = load volatile i32, ptr %106, align 4, !tbaa !36
  %108 = and i32 %107, -65536
  %109 = zext i16 %2 to i32
  %110 = select i1 %104, i32 0, i32 %109
  %.sink = or disjoint i32 %108, %110
  store volatile i32 %.sink, ptr %106, align 4, !tbaa !36
  %111 = getelementptr inbounds i8, ptr %105, i64 8
  %112 = load volatile i32, ptr %111, align 4, !tbaa !30
  %113 = or i32 %112, 16384
  store volatile i32 %113, ptr %111, align 4, !tbaa !30
  %114 = getelementptr inbounds i8, ptr %105, i64 16
  %115 = load volatile i32, ptr %114, align 4, !tbaa !37
  %116 = or i32 %115, 832
  store volatile i32 %116, ptr %114, align 4, !tbaa !37
  %117 = load volatile i32, ptr %105, align 4, !tbaa !22
  %118 = or i32 %117, 1
  store volatile i32 %118, ptr %105, align 4, !tbaa !22
  %119 = load i32, ptr %23, align 8, !tbaa !38
  %120 = icmp eq i32 %119, 4194304
  br i1 %120, label %121, label %124

121:                                              ; preds = %99
  %122 = load volatile i32, ptr %105, align 4, !tbaa !22
  %123 = or i32 %122, 512
  store volatile i32 %123, ptr %105, align 4, !tbaa !22
  br label %124

124:                                              ; preds = %99, %121
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %125

125:                                              ; preds = %3, %124, %96, %47, %14, %10
  %.0 = phi i32 [ 2, %10 ], [ 1, %14 ], [ 1, %47 ], [ 1, %96 ], [ 0, %124 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfReceiveCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAReceiveCplt(ptr noundef) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 160}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 164}
!14 = !{!6, !11, i64 168}
!15 = !{!6, !7, i64 112}
!16 = !{!6, !12, i64 120}
!17 = !{!6, !12, i64 122}
!18 = !{!6, !12, i64 104}
!19 = !{!6, !12, i64 106}
!20 = !{!6, !11, i64 12}
!21 = !{!6, !7, i64 0}
!22 = !{!23, !11, i64 0}
!23 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!24 = !{!23, !11, i64 12}
!25 = !{!6, !11, i64 16}
!26 = !{!6, !7, i64 152}
!27 = !{!28, !11, i64 28}
!28 = !{!"__DMA_HandleTypeDef", !7, i64 0, !29, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!29 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!30 = !{!23, !11, i64 8}
!31 = !{!28, !7, i64 80}
!32 = !{!28, !7, i64 72}
!33 = !{!28, !7, i64 104}
!34 = !{!28, !7, i64 112}
!35 = !{!28, !11, i64 32}
!36 = !{!23, !11, i64 4}
!37 = !{!23, !11, i64 16}
!38 = !{!6, !11, i64 8}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass