; LLVM IR from fdabrandao/vpsolver :: src/arcflow.ll (ZNK7Arcflow7is_fullERKSt6vectorIiSaIiEES4_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Arcflow = type <{ i8, [7 x i8], %"class.std::set", %class.NodeSet, %"class.std::vector.8", %"class.std::map", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", %"class.std::vector", i32, [4 x i8], i64, %class.Instance, i32, i32, i32, [4 x i8], %"class.std::vector.8", %"class.std::vector.23", i32, [4 x i8] }>
%"class.std::set" = type { %"class.std::_Rb_tree" }
%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<Arc, Arc, std::_Identity<Arc>, std::less<Arc>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<Arc, Arc, std::_Identity<Arc>, std::less<Arc>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"struct.std::_Rb_tree_header" = type { %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::_Rb_tree_node_base" = type { i32, ptr, ptr, ptr }
%class.NodeSet = type { %"class.std::map", %"class.std::vector" }
%"class.std::map" = type { %"class.std::_Rb_tree.0" }
%"class.std::_Rb_tree.0" = type { %"struct.std::_Rb_tree<std::vector<int>, std::pair<const std::vector<int>, int>, std::_Select1st<std::pair<const std::vector<int>, int>>, std::less<std::vector<int>>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<std::vector<int>, std::pair<const std::vector<int>, int>, std::_Select1st<std::pair<const std::vector<int>, int>>, std::less<std::vector<int>>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<Item, std::allocator<Item>>::_Vector_impl" }
%"struct.std::_Vector_base<Item, std::allocator<Item>>::_Vector_impl" = type { %"struct.std::_Vector_base<Item, std::allocator<Item>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Item, std::allocator<Item>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.Instance = type { i32, i32, i32, i32, i32, %"class.std::vector", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.13", i32, i8, i8, i8, %"class.std::vector.18", %"class.std::vector.8", %"class.std::vector.8" }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.23" = type { %"struct.std::_Vector_base.24" }
%"struct.std::_Vector_base.24" = type { %"struct.std::_Vector_base<Arc, std::allocator<Arc>>::_Vector_impl" }
%"struct.std::_Vector_base<Arc, std::allocator<Arc>>::_Vector_impl" = type { %"struct.std::_Vector_base<Arc, std::allocator<Arc>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Arc, std::allocator<Arc>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZNK7Arcflow7is_fullERKSt6vectorIiSaIiEES4_(ptr noundef nonnull align 8 dereferenceable(604) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #1 align 2 {
  %4 = alloca i1, align 1
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %32, %3
  %12 = load i32, ptr %8, align 4, !tbaa !9
  %13 = getelementptr inbounds %class.Arcflow, ptr %10, i32 0, i32 14
  %14 = getelementptr inbounds %class.Instance, ptr %13, i32 0, i32 0
  %15 = load i32, ptr %14, align 8, !tbaa !11
  %16 = icmp slt i32 %12, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %11
  store i32 2, ptr %9, align 4
  br label %35

18:                                               ; preds = %11
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #2
  %23 = load i32, ptr %22, align 4, !tbaa !9
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = load i32, ptr %8, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %26) #2
  %28 = load i32, ptr %27, align 4, !tbaa !9
  %29 = icmp ne i32 %23, %28
  br i1 %29, label %30, label %31

30:                                               ; preds = %18
  store i1 false, ptr %4, align 1
  store i32 1, ptr %9, align 4
  br label %35

31:                                               ; preds = %18
  br label %32

32:                                               ; preds = %31
  %33 = load i32, ptr %8, align 4, !tbaa !9
  %34 = add nsw i32 %33, 1
  store i32 %34, ptr %8, align 4, !tbaa !9
  br label %11, !llvm.loop !50

35:                                               ; preds = %30, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %36 = load i32, ptr %9, align 4
  switch i32 %36, label %40 [
    i32 2, label %37
    i32 1, label %38
  ]

37:                                               ; preds = %35
  store i1 true, ptr %4, align 1
  br label %38

38:                                               ; preds = %37, %35
  %39 = load i1, ptr %4, align 1
  ret i1 %39

40:                                               ; preds = %35
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 336}
!12 = !{!"_ZTS7Arcflow", !13, i64 0, !14, i64 8, !23, i64 56, !33, i64 128, !24, i64 152, !33, i64 200, !33, i64 224, !33, i64 248, !37, i64 272, !29, i64 296, !10, i64 320, !22, i64 328, !41, i64 336, !10, i64 536, !10, i64 540, !10, i64 544, !33, i64 552, !46, i64 576, !10, i64 600}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"_ZTSSt3setI3ArcSt4lessIS0_ESaIS0_EE", !15, i64 0}
!15 = !{!"_ZTSSt8_Rb_treeI3ArcS0_St9_IdentityIS0_ESt4lessIS0_ESaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSNSt8_Rb_treeI3ArcS0_St9_IdentityIS0_ESt4lessIS0_ESaIS0_EE13_Rb_tree_implIS4_Lb1EEE", !17, i64 0, !19, i64 8}
!17 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessI3ArcEE", !18, i64 0}
!18 = !{!"_ZTSSt4lessI3ArcE"}
!19 = !{!"_ZTSSt15_Rb_tree_header", !20, i64 0, !22, i64 32}
!20 = !{!"_ZTSSt18_Rb_tree_node_base", !21, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!21 = !{!"_ZTSSt14_Rb_tree_color", !7, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = !{!"_ZTS7NodeSet", !24, i64 0, !29, i64 48}
!24 = !{!"_ZTSSt3mapISt6vectorIiSaIiEEiSt4lessIS2_ESaISt4pairIKS2_iEEE", !25, i64 0}
!25 = !{!"_ZTSSt8_Rb_treeISt6vectorIiSaIiEESt4pairIKS2_iESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE", !26, i64 0}
!26 = !{!"_ZTSNSt8_Rb_treeISt6vectorIiSaIiEESt4pairIKS2_iESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !27, i64 0, !19, i64 8}
!27 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessISt6vectorIiSaIiEEEE", !28, i64 0}
!28 = !{!"_ZTSSt4lessISt6vectorIiSaIiEEE"}
!29 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIiSaIiEE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSSt6vectorI4ItemSaIS0_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseI4ItemSaIS0_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseI4ItemSaIS0_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseI4ItemSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!"_ZTS8Instance", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !29, i64 24, !33, i64 48, !33, i64 72, !37, i64 96, !10, i64 120, !13, i64 124, !13, i64 125, !7, i64 126, !42, i64 128, !33, i64 152, !33, i64 176}
!42 = !{!"_ZTSSt6vectorIcSaIcEE", !43, i64 0}
!43 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!46 = !{!"_ZTSSt6vectorI3ArcSaIS0_EE", !47, i64 0}
!47 = !{!"_ZTSSt12_Vector_baseI3ArcSaIS0_EE", !48, i64 0}
!48 = !{!"_ZTSNSt12_Vector_baseI3ArcSaIS0_EE12_Vector_implE", !49, i64 0}
!49 = !{!"_ZTSNSt12_Vector_baseI3ArcSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!50 = distinct !{!50, !51}
!51 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZNK7Arcflow7is_fullERKSt6vectorIiSaIiEES4_(ptr nocapture noundef nonnull readonly align 8 dereferenceable(604) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #0 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 336
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp slt i32 %5, 1
  br i1 %6, label %._crit_edge, label %.lr.ph

7:                                                ; preds = %.lr.ph
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %8 = load i32, ptr %4, align 8, !tbaa !5
  %9 = sext i32 %8 to i64
  %.not13 = icmp slt i64 %indvars.iv.next, %9
  br i1 %.not13, label %.lr.ph, label %._crit_edge, !llvm.loop !48

.lr.ph:                                           ; preds = %3, %7
  %indvars.iv = phi i64 [ %indvars.iv.next, %7 ], [ 0, %3 ]
  %10 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %11 = load i32, ptr %10, align 4, !tbaa !50
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #1
  %13 = load i32, ptr %12, align 4, !tbaa !50
  %.not = icmp eq i32 %11, %13
  br i1 %.not, label %7, label %._crit_edge

._crit_edge:                                      ; preds = %7, %.lr.ph, %3
  %.lcssa = phi i1 [ true, %3 ], [ %.not, %.lr.ph ], [ %.not, %7 ]
  ret i1 %.lcssa
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !38, i64 336}
!6 = !{!"_ZTS7Arcflow", !7, i64 0, !10, i64 8, !20, i64 56, !30, i64 128, !21, i64 152, !30, i64 200, !30, i64 224, !30, i64 248, !34, i64 272, !26, i64 296, !38, i64 320, !19, i64 328, !39, i64 336, !38, i64 536, !38, i64 540, !38, i64 544, !30, i64 552, !44, i64 576, !38, i64 600}
!7 = !{!"bool", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt3setI3ArcSt4lessIS0_ESaIS0_EE", !11, i64 0}
!11 = !{!"_ZTSSt8_Rb_treeI3ArcS0_St9_IdentityIS0_ESt4lessIS0_ESaIS0_EE", !12, i64 0}
!12 = !{!"_ZTSNSt8_Rb_treeI3ArcS0_St9_IdentityIS0_ESt4lessIS0_ESaIS0_EE13_Rb_tree_implIS4_Lb1EEE", !13, i64 0, !15, i64 8}
!13 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessI3ArcEE", !14, i64 0}
!14 = !{!"_ZTSSt4lessI3ArcE"}
!15 = !{!"_ZTSSt15_Rb_tree_header", !16, i64 0, !19, i64 32}
!16 = !{!"_ZTSSt18_Rb_tree_node_base", !17, i64 0, !18, i64 8, !18, i64 16, !18, i64 24}
!17 = !{!"_ZTSSt14_Rb_tree_color", !8, i64 0}
!18 = !{!"any pointer", !8, i64 0}
!19 = !{!"long", !8, i64 0}
!20 = !{!"_ZTS7NodeSet", !21, i64 0, !26, i64 48}
!21 = !{!"_ZTSSt3mapISt6vectorIiSaIiEEiSt4lessIS2_ESaISt4pairIKS2_iEEE", !22, i64 0}
!22 = !{!"_ZTSSt8_Rb_treeISt6vectorIiSaIiEESt4pairIKS2_iESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE", !23, i64 0}
!23 = !{!"_ZTSNSt8_Rb_treeISt6vectorIiSaIiEESt4pairIKS2_iESt10_Select1stIS5_ESt4lessIS2_ESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !24, i64 0, !15, i64 8}
!24 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessISt6vectorIiSaIiEEEE", !25, i64 0}
!25 = !{!"_ZTSSt4lessISt6vectorIiSaIiEEE"}
!26 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!30 = !{!"_ZTSSt6vectorIiSaIiEE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!34 = !{!"_ZTSSt6vectorI4ItemSaIS0_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseI4ItemSaIS0_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseI4ItemSaIS0_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseI4ItemSaIS0_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!38 = !{!"int", !8, i64 0}
!39 = !{!"_ZTS8Instance", !38, i64 0, !38, i64 4, !38, i64 8, !38, i64 12, !38, i64 16, !26, i64 24, !30, i64 48, !30, i64 72, !34, i64 96, !38, i64 120, !7, i64 124, !7, i64 125, !8, i64 126, !40, i64 128, !30, i64 152, !30, i64 176}
!40 = !{!"_ZTSSt6vectorIcSaIcEE", !41, i64 0}
!41 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!44 = !{!"_ZTSSt6vectorI3ArcSaIS0_EE", !45, i64 0}
!45 = !{!"_ZTSSt12_Vector_baseI3ArcSaIS0_EE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseI3ArcSaIS0_EE12_Vector_implE", !47, i64 0}
!47 = !{!"_ZTSNSt12_Vector_baseI3ArcSaIS0_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!48 = distinct !{!48, !49}
!49 = !{!"llvm.loop.mustprogress"}
!50 = !{!38, !38, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass