; LLVM IR from Columbitech/rohc :: src/dprofile.ll (ZN4ROHC8DProfile31parse_inferred_sequential_ip_idEt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.ROHC::DProfile" = type <{ ptr, ptr, i16, [2 x i8], i32, i16, i16, i32, i32, i32, i64, i64, i8, [3 x i8], %"struct.ROHC::iphdr", i64, i32, [4 x i8] }>
%"struct.ROHC::iphdr" = type { i8, i8, i16, i16, i16, i8, i8, i16, i32, i32 }

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4ROHC8DProfile31parse_inferred_sequential_ip_idEt(ptr noundef nonnull align 8 dereferenceable(92) %0, i16 noundef zeroext %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i16, align 2
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i16 %1, ptr %4, align 2, !tbaa !9
  %5 = load ptr, ptr %3, align 8
  %6 = getelementptr inbounds %"class.ROHC::DProfile", ptr %5, i32 0, i32 7
  %7 = load i32, ptr %6, align 4, !tbaa !11
  %8 = icmp eq i32 0, %7
  br i1 %8, label %9, label %22

9:                                                ; preds = %2
  %10 = getelementptr inbounds %"class.ROHC::DProfile", ptr %5, i32 0, i32 14
  %11 = getelementptr inbounds %"struct.ROHC::iphdr", ptr %10, i32 0, i32 3
  %12 = load i16, ptr %11, align 4, !tbaa !20
  %13 = call noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext %12)
  %14 = zext i16 %13 to i32
  %15 = load i16, ptr %4, align 2, !tbaa !9
  %16 = zext i16 %15 to i32
  %17 = add nsw i32 %14, %16
  %18 = trunc i32 %17 to i16
  %19 = call noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext %18)
  %20 = getelementptr inbounds %"class.ROHC::DProfile", ptr %5, i32 0, i32 14
  %21 = getelementptr inbounds %"struct.ROHC::iphdr", ptr %20, i32 0, i32 3
  store i16 %19, ptr %21, align 4, !tbaa !20
  br label %36

22:                                               ; preds = %2
  %23 = getelementptr inbounds %"class.ROHC::DProfile", ptr %5, i32 0, i32 7
  %24 = load i32, ptr %23, align 4, !tbaa !11
  %25 = icmp eq i32 1, %24
  br i1 %25, label %26, label %35

26:                                               ; preds = %22
  %27 = load i16, ptr %4, align 2, !tbaa !9
  %28 = zext i16 %27 to i32
  %29 = getelementptr inbounds %"class.ROHC::DProfile", ptr %5, i32 0, i32 14
  %30 = getelementptr inbounds %"struct.ROHC::iphdr", ptr %29, i32 0, i32 3
  %31 = load i16, ptr %30, align 4, !tbaa !20
  %32 = zext i16 %31 to i32
  %33 = add nsw i32 %32, %28
  %34 = trunc i32 %33 to i16
  store i16 %34, ptr %30, align 4, !tbaa !20
  br label %35

35:                                               ; preds = %26, %22
  br label %36

36:                                               ; preds = %35, %9
  ret void
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 28}
!12 = !{!"_ZTSN4ROHC8DProfileE", !6, i64 8, !10, i64 16, !13, i64 20, !10, i64 24, !10, i64 26, !14, i64 28, !15, i64 32, !15, i64 36, !16, i64 40, !16, i64 48, !17, i64 56, !18, i64 60, !16, i64 80, !19, i64 88}
!13 = !{!"_ZTSN4ROHC8DProfileUt_E", !7, i64 0}
!14 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !7, i64 0}
!15 = !{!"int", !7, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!"bool", !7, i64 0}
!18 = !{!"_ZTSN4ROHC5iphdrE", !7, i64 0, !7, i64 0, !7, i64 1, !10, i64 2, !10, i64 4, !10, i64 6, !7, i64 8, !7, i64 9, !10, i64 10, !15, i64 12, !15, i64 16}
!19 = !{!"_ZTSN4ROHC12Reordering_tE", !7, i64 0}
!20 = !{!12, !10, i64 64}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4ROHC8DProfile31parse_inferred_sequential_ip_idEt(ptr nocapture noundef nonnull align 8 dereferenceable(92) %0, i16 noundef zeroext %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 28
  %4 = load i32, ptr %3, align 4, !tbaa !5
  switch i32 %4, label %15 [
    i32 0, label %5
    i32 1, label %11
  ]

5:                                                ; preds = %2
  %6 = getelementptr inbounds i8, ptr %0, i64 64
  %7 = load i16, ptr %6, align 8, !tbaa !18
  %8 = tail call noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext %7)
  %9 = add i16 %8, %1
  %10 = tail call noundef zeroext i16 @_ZN4ROHC10rohc_htonsEt(i16 noundef zeroext %9)
  store i16 %10, ptr %6, align 8, !tbaa !18
  br label %15

11:                                               ; preds = %2
  %12 = getelementptr inbounds i8, ptr %0, i64 64
  %13 = load i16, ptr %12, align 8, !tbaa !18
  %14 = add i16 %13, %1
  store i16 %14, ptr %12, align 8, !tbaa !18
  br label %15

15:                                               ; preds = %2, %11, %5
  ret void
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 28}
!6 = !{!"_ZTSN4ROHC8DProfileE", !7, i64 8, !10, i64 16, !11, i64 20, !10, i64 24, !10, i64 26, !12, i64 28, !13, i64 32, !13, i64 36, !14, i64 40, !14, i64 48, !15, i64 56, !16, i64 60, !14, i64 80, !17, i64 88}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"short", !8, i64 0}
!11 = !{!"_ZTSN4ROHC8DProfileUt_E", !8, i64 0}
!12 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"long", !8, i64 0}
!15 = !{!"bool", !8, i64 0}
!16 = !{!"_ZTSN4ROHC5iphdrE", !8, i64 0, !8, i64 0, !8, i64 1, !10, i64 2, !10, i64 4, !10, i64 6, !8, i64 8, !8, i64 9, !10, i64 10, !13, i64 12, !13, i64 16}
!17 = !{!"_ZTSN4ROHC12Reordering_tE", !8, i64 0}
!18 = !{!6, !10, i64 64}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass