; LLVM IR from Eslam-Rizk/Elite-DriveGuard :: Application/Middlewares/Third_Party/FreeRTOS/Source (tasks)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [16 x i8], i64, i64, i64, i64, i32, i8, i8 }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@pxReadyTasksLists = external hidden global [56 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @uxListRemove(ptr noundef) #2

declare void @vListInsertEnd(ptr noundef, ptr noundef) #2

declare void @vPortValidateInterruptPriority() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i64 @xTaskGenericNotifyFromISR(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, ptr noundef %4) #3 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i8, align 1
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 1, ptr %13, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %19

17:                                               ; preds = %5
  call void @vPortRaiseBASEPRI()
  br label %18

18:                                               ; preds = %18, %17
  br label %18

19:                                               ; preds = %5
  call void @vPortValidateInterruptPriority()
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %20, ptr %11, align 8, !tbaa !5
  %21 = call i32 @ulPortRaiseBASEPRI()
  %22 = zext i32 %21 to i64
  store i64 %22, ptr %14, align 8, !tbaa !11
  %23 = load ptr, ptr %9, align 8, !tbaa !5
  %24 = icmp ne ptr %23, null
  br i1 %24, label %25, label %30

25:                                               ; preds = %19
  %26 = load ptr, ptr %11, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %26, i32 0, i32 10
  %28 = load volatile i32, ptr %27, align 8, !tbaa !13
  %29 = load ptr, ptr %9, align 8, !tbaa !5
  store i32 %28, ptr %29, align 4, !tbaa !9
  br label %30

30:                                               ; preds = %25, %19
  %31 = load ptr, ptr %11, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %31, i32 0, i32 11
  %33 = load volatile i8, ptr %32, align 4, !tbaa !16
  store i8 %33, ptr %12, align 1, !tbaa !17
  %34 = load ptr, ptr %11, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %34, i32 0, i32 11
  store volatile i8 2, ptr %35, align 4, !tbaa !16
  %36 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %36, label %62 [
    i32 1, label %37
    i32 2, label %43
    i32 3, label %48
    i32 4, label %52
    i32 0, label %73
  ]

37:                                               ; preds = %30
  %38 = load i32, ptr %7, align 4, !tbaa !9
  %39 = load ptr, ptr %11, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %39, i32 0, i32 10
  %41 = load volatile i32, ptr %40, align 8, !tbaa !13
  %42 = or i32 %41, %38
  store volatile i32 %42, ptr %40, align 8, !tbaa !13
  br label %73

43:                                               ; preds = %30
  %44 = load ptr, ptr %11, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %44, i32 0, i32 10
  %46 = load volatile i32, ptr %45, align 8, !tbaa !13
  %47 = add i32 %46, 1
  store volatile i32 %47, ptr %45, align 8, !tbaa !13
  br label %73

48:                                               ; preds = %30
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = load ptr, ptr %11, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %50, i32 0, i32 10
  store volatile i32 %49, ptr %51, align 8, !tbaa !13
  br label %73

52:                                               ; preds = %30
  %53 = load i8, ptr %12, align 1, !tbaa !17
  %54 = zext i8 %53 to i32
  %55 = icmp ne i32 %54, 2
  br i1 %55, label %56, label %60

56:                                               ; preds = %52
  %57 = load i32, ptr %7, align 4, !tbaa !9
  %58 = load ptr, ptr %11, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %58, i32 0, i32 10
  store volatile i32 %57, ptr %59, align 8, !tbaa !13
  br label %61

60:                                               ; preds = %52
  store i64 0, ptr %13, align 8, !tbaa !11
  br label %61

61:                                               ; preds = %60, %56
  br label %73

62:                                               ; preds = %30
  %63 = load ptr, ptr %11, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %63, i32 0, i32 10
  %65 = load volatile i32, ptr %64, align 8, !tbaa !13
  %66 = zext i32 %65 to i64
  %67 = icmp eq i64 %66, -1
  %68 = zext i1 %67 to i32
  %69 = icmp eq i32 %68, 0
  br i1 %69, label %70, label %72

70:                                               ; preds = %62
  call void @vPortRaiseBASEPRI()
  br label %71

71:                                               ; preds = %71, %70
  br label %71

72:                                               ; preds = %62
  br label %73

73:                                               ; preds = %72, %61, %48, %43, %37, %30
  %74 = load i8, ptr %12, align 1, !tbaa !17
  %75 = zext i8 %74 to i32
  %76 = icmp eq i32 %75, 1
  br i1 %76, label %77, label %129

77:                                               ; preds = %73
  %78 = load ptr, ptr %11, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %78, i32 0, i32 2
  %80 = getelementptr inbounds %struct.xLIST_ITEM, ptr %79, i32 0, i32 4
  %81 = load ptr, ptr %80, align 8, !tbaa !18
  %82 = icmp eq ptr %81, null
  %83 = zext i1 %82 to i32
  %84 = icmp eq i32 %83, 0
  br i1 %84, label %85, label %87

85:                                               ; preds = %77
  call void @vPortRaiseBASEPRI()
  br label %86

86:                                               ; preds = %86, %85
  br label %86

87:                                               ; preds = %77
  %88 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !11
  %89 = icmp eq i64 %88, 0
  br i1 %89, label %90, label %110

90:                                               ; preds = %87
  %91 = load ptr, ptr %11, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %91, i32 0, i32 1
  %93 = call i64 @uxListRemove(ptr noundef %92)
  %94 = load ptr, ptr %11, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %94, i32 0, i32 3
  %96 = load i64, ptr %95, align 8, !tbaa !19
  %97 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !11
  %98 = icmp ugt i64 %96, %97
  br i1 %98, label %99, label %103

99:                                               ; preds = %90
  %100 = load ptr, ptr %11, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %100, i32 0, i32 3
  %102 = load i64, ptr %101, align 8, !tbaa !19
  store volatile i64 %102, ptr @uxTopReadyPriority, align 8, !tbaa !11
  br label %103

103:                                              ; preds = %99, %90
  %104 = load ptr, ptr %11, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %104, i32 0, i32 3
  %106 = load i64, ptr %105, align 8, !tbaa !19
  %107 = getelementptr inbounds [56 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %106
  %108 = load ptr, ptr %11, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %108, i32 0, i32 1
  call void @vListInsertEnd(ptr noundef %107, ptr noundef %109)
  br label %113

110:                                              ; preds = %87
  %111 = load ptr, ptr %11, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %111, i32 0, i32 2
  call void @vListInsertEnd(ptr noundef @xPendingReadyList, ptr noundef %112)
  br label %113

113:                                              ; preds = %110, %103
  %114 = load ptr, ptr %11, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %114, i32 0, i32 3
  %116 = load i64, ptr %115, align 8, !tbaa !19
  %117 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %117, i32 0, i32 3
  %119 = load i64, ptr %118, align 8, !tbaa !19
  %120 = icmp ugt i64 %116, %119
  br i1 %120, label %121, label %127

121:                                              ; preds = %113
  %122 = load ptr, ptr %10, align 8, !tbaa !5
  %123 = icmp ne ptr %122, null
  br i1 %123, label %124, label %126

124:                                              ; preds = %121
  %125 = load ptr, ptr %10, align 8, !tbaa !5
  store i64 1, ptr %125, align 8, !tbaa !11
  br label %126

126:                                              ; preds = %124, %121
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !11
  br label %128

127:                                              ; preds = %113
  br label %128

128:                                              ; preds = %127, %126
  br label %129

129:                                              ; preds = %128, %73
  %130 = load i64, ptr %14, align 8, !tbaa !11
  %131 = trunc i64 %130 to i32
  call void @vPortSetBASEPRI(i32 noundef %131)
  %132 = load i64, ptr %13, align 8, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  ret i64 %132
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !10, i64 152}
!14 = !{!"tskTaskControlBlock", !6, i64 0, !15, i64 8, !15, i64 48, !12, i64 88, !6, i64 96, !7, i64 104, !12, i64 120, !12, i64 128, !12, i64 136, !12, i64 144, !10, i64 152, !7, i64 156, !7, i64 157}
!15 = !{!"xLIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!16 = !{!14, !7, i64 156}
!17 = !{!7, !7, i64 0}
!18 = !{!14, !6, i64 80}
!19 = !{!14, !12, i64 88}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@pxReadyTasksLists = external hidden global [56 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @uxListRemove(ptr noundef) local_unnamed_addr #1

declare void @vListInsertEnd(ptr noundef, ptr noundef) local_unnamed_addr #1

declare void @vPortValidateInterruptPriority() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xTaskGenericNotifyFromISR(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef writeonly %3, ptr noundef writeonly %4) local_unnamed_addr #2 {
  %6 = icmp eq ptr %0, null
  br i1 %6, label %7, label %9

7:                                                ; preds = %5
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %5
  tail call void @vPortValidateInterruptPriority() #3
  %10 = tail call i32 @ulPortRaiseBASEPRI()
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %14, label %11

11:                                               ; preds = %9
  %12 = getelementptr inbounds i8, ptr %0, i64 152
  %13 = load volatile i32, ptr %12, align 8, !tbaa !5
  store i32 %13, ptr %3, align 4, !tbaa !13
  br label %14

14:                                               ; preds = %11, %9
  %15 = getelementptr inbounds i8, ptr %0, i64 156
  %16 = load volatile i8, ptr %15, align 4, !tbaa !14
  store volatile i8 2, ptr %15, align 4, !tbaa !14
  switch i32 %2, label %30 [
    i32 1, label %17
    i32 2, label %21
    i32 3, label %25
    i32 4, label %27
    i32 0, label %34
  ]

17:                                               ; preds = %14
  %18 = getelementptr inbounds i8, ptr %0, i64 152
  %19 = load volatile i32, ptr %18, align 8, !tbaa !5
  %20 = or i32 %19, %1
  store volatile i32 %20, ptr %18, align 8, !tbaa !5
  br label %34

21:                                               ; preds = %14
  %22 = getelementptr inbounds i8, ptr %0, i64 152
  %23 = load volatile i32, ptr %22, align 8, !tbaa !5
  %24 = add i32 %23, 1
  store volatile i32 %24, ptr %22, align 8, !tbaa !5
  br label %34

25:                                               ; preds = %14
  %26 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %1, ptr %26, align 8, !tbaa !5
  br label %34

27:                                               ; preds = %14
  %.not32 = icmp eq i8 %16, 2
  br i1 %.not32, label %.thread, label %28

28:                                               ; preds = %27
  %29 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %1, ptr %29, align 8, !tbaa !5
  br label %34

30:                                               ; preds = %14
  %31 = getelementptr inbounds i8, ptr %0, i64 152
  %32 = load volatile i32, ptr %31, align 8, !tbaa !5
  tail call void @vPortRaiseBASEPRI()
  br label %33

33:                                               ; preds = %33, %30
  br label %33

34:                                               ; preds = %28, %25, %21, %17, %14
  %35 = icmp eq i8 %16, 1
  br i1 %35, label %36, label %.thread

36:                                               ; preds = %34
  %37 = getelementptr inbounds i8, ptr %0, i64 48
  %38 = getelementptr inbounds i8, ptr %0, i64 80
  %39 = load ptr, ptr %38, align 8, !tbaa !15
  %.not33 = icmp eq ptr %39, null
  br i1 %.not33, label %42, label %40

40:                                               ; preds = %36
  tail call void @vPortRaiseBASEPRI()
  br label %41

41:                                               ; preds = %41, %40
  br label %41

42:                                               ; preds = %36
  %43 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !16
  %44 = icmp eq i64 %43, 0
  br i1 %44, label %45, label %55

45:                                               ; preds = %42
  %46 = getelementptr inbounds i8, ptr %0, i64 8
  %47 = tail call i64 @uxListRemove(ptr noundef nonnull %46) #3
  %48 = getelementptr inbounds i8, ptr %0, i64 88
  %49 = load i64, ptr %48, align 8, !tbaa !17
  %50 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !16
  %51 = icmp ugt i64 %49, %50
  br i1 %51, label %52, label %53

52:                                               ; preds = %45
  store volatile i64 %49, ptr @uxTopReadyPriority, align 8, !tbaa !16
  br label %53

53:                                               ; preds = %52, %45
  %54 = getelementptr inbounds [56 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %49
  tail call void @vListInsertEnd(ptr noundef nonnull %54, ptr noundef nonnull %46) #3
  br label %56

55:                                               ; preds = %42
  tail call void @vListInsertEnd(ptr noundef nonnull @xPendingReadyList, ptr noundef nonnull %37) #3
  br label %56

56:                                               ; preds = %55, %53
  %57 = getelementptr inbounds i8, ptr %0, i64 88
  %58 = load i64, ptr %57, align 8, !tbaa !17
  %59 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !18
  %60 = getelementptr inbounds i8, ptr %59, i64 88
  %61 = load i64, ptr %60, align 8, !tbaa !17
  %62 = icmp ugt i64 %58, %61
  br i1 %62, label %63, label %.thread

63:                                               ; preds = %56
  %.not34 = icmp eq ptr %4, null
  br i1 %.not34, label %65, label %64

64:                                               ; preds = %63
  store i64 1, ptr %4, align 8, !tbaa !16
  br label %65

65:                                               ; preds = %64, %63
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !16
  br label %.thread

.thread:                                          ; preds = %27, %65, %56, %34
  %.036 = phi i64 [ 1, %65 ], [ 1, %56 ], [ 1, %34 ], [ 0, %27 ]
  tail call void @vPortSetBASEPRI(i32 noundef %10)
  ret i64 %.036
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 152}
!6 = !{!"tskTaskControlBlock", !7, i64 0, !10, i64 8, !10, i64 48, !12, i64 88, !7, i64 96, !8, i64 104, !12, i64 120, !12, i64 128, !12, i64 136, !12, i64 144, !11, i64 152, !8, i64 156, !8, i64 157}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST_ITEM", !11, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32}
!11 = !{!"int", !8, i64 0}
!12 = !{!"long", !8, i64 0}
!13 = !{!11, !11, i64 0}
!14 = !{!6, !8, i64 156}
!15 = !{!6, !7, i64 80}
!16 = !{!12, !12, i64 0}
!17 = !{!6, !12, i64 88}
!18 = !{!7, !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass