; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (hs_mmcsd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @HSMMCSDCommandSend(i32 noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, i32 noundef %4, i32 noundef %5) #0 {
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store i32 %0, ptr %7, align 4, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !9
  store i32 %4, ptr %11, align 4, !tbaa !5
  store i32 %5, ptr %12, align 4, !tbaa !5
  %13 = load ptr, ptr %10, align 8, !tbaa !9
  %14 = icmp ne ptr null, %13
  br i1 %14, label %15, label %18

15:                                               ; preds = %6
  %16 = load i32, ptr %8, align 4, !tbaa !5
  %17 = or i32 %16, 2097186
  store i32 %17, ptr %8, align 4, !tbaa !5
  br label %18

18:                                               ; preds = %15, %6
  %19 = load i32, ptr %12, align 4, !tbaa !5
  %20 = icmp eq i32 1, %19
  br i1 %20, label %21, label %24

21:                                               ; preds = %18
  %22 = load i32, ptr %8, align 4, !tbaa !5
  %23 = or i32 %22, 1
  store i32 %23, ptr %8, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %21, %18
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = add i32 %25, 516
  %27 = zext i32 %26 to i64
  %28 = inttoptr i64 %27 to ptr
  %29 = load volatile i32, ptr %28, align 4, !tbaa !5
  %30 = and i32 %29, 65535
  store volatile i32 %30, ptr %28, align 4, !tbaa !5
  %31 = load i32, ptr %11, align 4, !tbaa !5
  %32 = shl i32 %31, 16
  %33 = load i32, ptr %7, align 4, !tbaa !5
  %34 = add i32 %33, 516
  %35 = zext i32 %34 to i64
  %36 = inttoptr i64 %35 to ptr
  %37 = load volatile i32, ptr %36, align 4, !tbaa !5
  %38 = or i32 %37, %32
  store volatile i32 %38, ptr %36, align 4, !tbaa !5
  %39 = load i32, ptr %9, align 4, !tbaa !5
  %40 = load i32, ptr %7, align 4, !tbaa !5
  %41 = add i32 %40, 520
  %42 = zext i32 %41 to i64
  %43 = inttoptr i64 %42 to ptr
  store volatile i32 %39, ptr %43, align 4, !tbaa !5
  %44 = load i32, ptr %8, align 4, !tbaa !5
  %45 = load i32, ptr %7, align 4, !tbaa !5
  %46 = add i32 %45, 524
  %47 = zext i32 %46 to i64
  %48 = inttoptr i64 %47 to ptr
  store volatile i32 %44, ptr %48, align 4, !tbaa !5
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local void @HSMMCSDCommandSend(i32 noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef readnone %3, i32 noundef %4, i32 noundef %5) local_unnamed_addr #0 {
  %.not = icmp eq ptr %3, null
  %7 = or i32 %1, 2097186
  %spec.select = select i1 %.not, i32 %1, i32 %7
  %8 = icmp eq i32 %5, 1
  %9 = zext i1 %8 to i32
  %.1 = or i32 %spec.select, %9
  %10 = add i32 %0, 516
  %11 = zext i32 %10 to i64
  %12 = inttoptr i64 %11 to ptr
  %13 = load volatile i32, ptr %12, align 4, !tbaa !5
  %14 = and i32 %13, 65535
  store volatile i32 %14, ptr %12, align 4, !tbaa !5
  %15 = shl i32 %4, 16
  %16 = load volatile i32, ptr %12, align 4, !tbaa !5
  %17 = or i32 %16, %15
  store volatile i32 %17, ptr %12, align 4, !tbaa !5
  %18 = add i32 %0, 520
  %19 = zext i32 %18 to i64
  %20 = inttoptr i64 %19 to ptr
  store volatile i32 %2, ptr %20, align 4, !tbaa !5
  %21 = add i32 %0, 524
  %22 = zext i32 %21 to i64
  %23 = inttoptr i64 %22 to ptr
  store volatile i32 %.1, ptr %23, align 4, !tbaa !5
  ret void
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass