; LLVM IR from balintbalazs/B3D :: source/src/B3D_cudaCompress/B3D (B3DcompressFunctions)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cudaCompress::BitStream" = type <{ %"class.cudaCompress::BitStreamReadOnly.base", [4 x i8], ptr, i8, [7 x i8] }>
%"class.cudaCompress::BitStreamReadOnly.base" = type <{ ptr, ptr, i32, i32, i32 }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::allocator.2" = type { i8 }

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [107 x i8], align 1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN12cudaCompress9BitStreamC2EPSt6vectorIjSaIjEE(ptr noundef nonnull align 8 dereferenceable(41), ptr noundef) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

declare void @_ZN12cudaCompress4util19predictor7_tilesCPUEPKsPsiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

declare void @_ZN12cudaCompress4util12symbolizeCPUEPtPKsjjjjj(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaItEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorItSaItEEC2IPtvEET_S4_RKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef, ptr noundef, ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #5 align 2

declare noundef zeroext i1 @_ZN12cudaCompress15encodeRLHuffCPUEPPNS_9BitStreamEPPSt6vectorItSaItEEjjb(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i1 noundef zeroext) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12cudaCompress16compressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i64 noundef %8, float noundef %9, float noundef %10, i32 noundef %11, float noundef %12, float noundef %13) #5 personality ptr @__gxx_personality_v0 {
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i64, align 8
  %24 = alloca float, align 4
  %25 = alloca float, align 4
  %26 = alloca i32, align 4
  %27 = alloca float, align 4
  %28 = alloca float, align 4
  %29 = alloca [1 x ptr], align 8
  %30 = alloca %"class.cudaCompress::BitStream", align 8
  %31 = alloca ptr, align 8
  %32 = alloca %"class.std::vector.0", align 8
  %33 = alloca %"class.std::allocator.2", align 1
  %34 = alloca ptr, align 8
  %35 = alloca i32, align 4
  %36 = alloca ptr, align 8
  store ptr %0, ptr %15, align 8, !tbaa !5
  store ptr %1, ptr %16, align 8, !tbaa !5
  store ptr %2, ptr %17, align 8, !tbaa !5
  store ptr %3, ptr %18, align 8, !tbaa !5
  store ptr %4, ptr %19, align 8, !tbaa !5
  store i32 %5, ptr %20, align 4, !tbaa !9
  store i32 %6, ptr %21, align 4, !tbaa !9
  store i32 %7, ptr %22, align 4, !tbaa !9
  store i64 %8, ptr %23, align 8, !tbaa !11
  store float %9, ptr %24, align 4, !tbaa !13
  store float %10, ptr %25, align 4, !tbaa !13
  store i32 %11, ptr %26, align 4, !tbaa !9
  store float %12, ptr %27, align 4, !tbaa !13
  store float %13, ptr %28, align 4, !tbaa !13
  %37 = load i32, ptr %21, align 4, !tbaa !9
  %38 = load i32, ptr %22, align 4, !tbaa !9
  %39 = mul nsw i32 %37, %38
  store i32 %39, ptr %21, align 4, !tbaa !9
  store i32 1, ptr %22, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %29) #7
  %40 = load ptr, ptr %19, align 8, !tbaa !5
  store ptr %40, ptr %29, align 8, !tbaa !5
  %41 = load ptr, ptr %16, align 8, !tbaa !5
  %42 = load ptr, ptr %17, align 8, !tbaa !5
  %43 = load i32, ptr %20, align 4, !tbaa !9
  %44 = load i32, ptr %21, align 4, !tbaa !9
  %45 = mul nsw i32 %43, %44
  call void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef %41, ptr noundef %42, i32 noundef %45)
  %46 = load ptr, ptr %18, align 8, !tbaa !5
  %47 = load i32, ptr %20, align 4, !tbaa !9
  %48 = load i32, ptr %21, align 4, !tbaa !9
  %49 = mul nsw i32 %47, %48
  %50 = sext i32 %49 to i64
  %51 = mul i64 %50, 2
  call void @llvm.memset.p0.i64(ptr align 4 %46, i8 0, i64 %51, i1 false)
  %52 = load i64, ptr %23, align 8, !tbaa !11
  switch i64 %52, label %106 [
    i64 1, label %53
    i64 3, label %53
    i64 11, label %53
    i64 2, label %76
  ]

53:                                               ; preds = %14, %14, %14
  %54 = load ptr, ptr %17, align 8, !tbaa !5
  %55 = load ptr, ptr %17, align 8, !tbaa !5
  %56 = load i32, ptr %20, align 4, !tbaa !9
  %57 = load i32, ptr %21, align 4, !tbaa !9
  %58 = mul nsw i32 %56, %57
  %59 = load float, ptr %25, align 4, !tbaa !13
  %60 = load float, ptr %27, align 4, !tbaa !13
  %61 = load float, ptr %28, align 4, !tbaa !13
  call void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef %54, ptr noundef %55, i32 noundef %58, float noundef %59, float noundef %60, float noundef %61)
  %62 = load ptr, ptr %17, align 8, !tbaa !5
  %63 = load ptr, ptr %17, align 8, !tbaa !5
  %64 = load float, ptr %24, align 4, !tbaa !13
  %65 = fdiv float 1.000000e+00, %64
  %66 = load i32, ptr %20, align 4, !tbaa !9
  %67 = load i32, ptr %21, align 4, !tbaa !9
  %68 = mul nsw i32 %66, %67
  call void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %62, ptr noundef %63, float noundef %65, i32 noundef %68)
  %69 = load ptr, ptr %17, align 8, !tbaa !5
  %70 = load ptr, ptr %18, align 8, !tbaa !5
  %71 = load ptr, ptr %16, align 8, !tbaa !5
  %72 = load i32, ptr %20, align 4, !tbaa !9
  %73 = load i32, ptr %20, align 4, !tbaa !9
  %74 = load i32, ptr %21, align 4, !tbaa !9
  %75 = load i32, ptr %26, align 4, !tbaa !9
  call void @_ZN12cudaCompress4util24predictor7_tiles_wnllCPUEPKfPfPsiiii(ptr noundef %69, ptr noundef %70, ptr noundef %71, i32 noundef %72, i32 noundef %73, i32 noundef %74, i32 noundef %75)
  br label %107

76:                                               ; preds = %14
  %77 = load ptr, ptr %17, align 8, !tbaa !5
  %78 = load ptr, ptr %17, align 8, !tbaa !5
  %79 = load i32, ptr %20, align 4, !tbaa !9
  %80 = load i32, ptr %21, align 4, !tbaa !9
  %81 = mul nsw i32 %79, %80
  %82 = load float, ptr %25, align 4, !tbaa !13
  %83 = load float, ptr %27, align 4, !tbaa !13
  %84 = load float, ptr %28, align 4, !tbaa !13
  call void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef %77, ptr noundef %78, i32 noundef %81, float noundef %82, float noundef %83, float noundef %84)
  %85 = load ptr, ptr %17, align 8, !tbaa !5
  %86 = load ptr, ptr %17, align 8, !tbaa !5
  %87 = load float, ptr %24, align 4, !tbaa !13
  %88 = fdiv float 1.000000e+00, %87
  %89 = load i32, ptr %20, align 4, !tbaa !9
  %90 = load i32, ptr %21, align 4, !tbaa !9
  %91 = mul nsw i32 %89, %90
  call void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %85, ptr noundef %86, float noundef %88, i32 noundef %91)
  %92 = load ptr, ptr %17, align 8, !tbaa !5
  %93 = load ptr, ptr %18, align 8, !tbaa !5
  %94 = load i32, ptr %20, align 4, !tbaa !9
  %95 = load i32, ptr %21, align 4, !tbaa !9
  %96 = mul nsw i32 %94, %95
  call void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef %92, ptr noundef %93, i32 noundef %96)
  %97 = load ptr, ptr %18, align 8, !tbaa !5
  %98 = load ptr, ptr %16, align 8, !tbaa !5
  %99 = load i32, ptr %20, align 4, !tbaa !9
  %100 = sext i32 %99 to i64
  %101 = mul i64 %100, 2
  %102 = trunc i64 %101 to i32
  %103 = load i32, ptr %20, align 4, !tbaa !9
  %104 = load i32, ptr %21, align 4, !tbaa !9
  %105 = load i32, ptr %26, align 4, !tbaa !9
  call void @_ZN12cudaCompress4util19predictor7_tilesCPUEPKsPsiiii(ptr noundef %97, ptr noundef %98, i32 noundef %102, i32 noundef %103, i32 noundef %104, i32 noundef %105)
  br label %107

106:                                              ; preds = %14
  br label %107

107:                                              ; preds = %106, %76, %53
  call void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 508)
  %108 = load ptr, ptr %19, align 8, !tbaa !5
  %109 = load ptr, ptr %16, align 8, !tbaa !5
  %110 = load i32, ptr %20, align 4, !tbaa !9
  %111 = load i32, ptr %21, align 4, !tbaa !9
  %112 = load i32, ptr %22, align 4, !tbaa !9
  call void @_ZN12cudaCompress4util12symbolizeCPUEPtPKsjjjjj(ptr noundef %108, ptr noundef %109, i32 noundef %110, i32 noundef %111, i32 noundef %112, i32 noundef 0, i32 noundef 0)
  call void @llvm.lifetime.start.p0(i64 48, ptr %30) #7
  %113 = load ptr, ptr %15, align 8, !tbaa !5
  call void @_ZN12cudaCompress9BitStreamC2EPSt6vectorIjSaIjEE(ptr noundef nonnull align 8 dereferenceable(41) %30, ptr noundef %113)
  call void @llvm.lifetime.start.p0(i64 8, ptr %31) #7
  store ptr %30, ptr %31, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 24, ptr %32) #7
  %114 = load ptr, ptr %19, align 8, !tbaa !5
  %115 = load ptr, ptr %19, align 8, !tbaa !5
  %116 = load i32, ptr %20, align 4, !tbaa !9
  %117 = load i32, ptr %21, align 4, !tbaa !9
  %118 = mul nsw i32 %116, %117
  %119 = sext i32 %118 to i64
  %120 = getelementptr inbounds i16, ptr %115, i64 %119
  call void @llvm.lifetime.start.p0(i64 1, ptr %33) #7
  call void @_ZNSaItEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %33) #7
  invoke void @_ZNSt6vectorItSaItEEC2IPtvEET_S4_RKS0_(ptr noundef nonnull align 8 dereferenceable(24) %32, ptr noundef %114, ptr noundef %120, ptr noundef nonnull align 1 dereferenceable(1) %33)
          to label %121 unwind label %124

121:                                              ; preds = %107
  call void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %33) #7
  call void @llvm.lifetime.end.p0(i64 1, ptr %33) #7
  call void @llvm.lifetime.start.p0(i64 8, ptr %36) #7
  store ptr %32, ptr %36, align 8, !tbaa !5
  %122 = invoke noundef zeroext i1 @_ZN12cudaCompress15encodeRLHuffCPUEPPNS_9BitStreamEPPSt6vectorItSaItEEjjb(ptr noundef %31, ptr noundef %36, i32 noundef 1, i32 noundef 128, i1 noundef zeroext true)
          to label %123 unwind label %128

123:                                              ; preds = %121
  call void @llvm.lifetime.end.p0(i64 8, ptr %36) #7
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %32) #7
  call void @llvm.lifetime.end.p0(i64 24, ptr %32) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %31) #7
  call void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41) %30) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr %30) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #7
  ret void

124:                                              ; preds = %107
  %125 = landingpad { ptr, i32 }
          cleanup
  %126 = extractvalue { ptr, i32 } %125, 0
  store ptr %126, ptr %34, align 8
  %127 = extractvalue { ptr, i32 } %125, 1
  store i32 %127, ptr %35, align 4
  call void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %33) #7
  call void @llvm.lifetime.end.p0(i64 1, ptr %33) #7
  br label %132

128:                                              ; preds = %121
  %129 = landingpad { ptr, i32 }
          cleanup
  %130 = extractvalue { ptr, i32 } %129, 0
  store ptr %130, ptr %34, align 8
  %131 = extractvalue { ptr, i32 } %129, 1
  store i32 %131, ptr %35, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %36) #7
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %32) #7
  br label %132

132:                                              ; preds = %128, %124
  call void @llvm.lifetime.end.p0(i64 24, ptr %32) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %31) #7
  call void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41) %30) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr %30) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #7
  br label %133

133:                                              ; preds = %132
  %134 = load ptr, ptr %34, align 8
  %135 = load i32, ptr %35, align 4
  %136 = insertvalue { ptr, i32 } poison, ptr %134, 0
  %137 = insertvalue { ptr, i32 } %136, i32 %135, 1
  resume { ptr, i32 } %137
}

declare void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef, ptr noundef, i32 noundef) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #6

declare void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef, ptr noundef, i32 noundef, float noundef, float noundef, float noundef) #3

declare void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef, ptr noundef, float noundef, i32 noundef) #3

declare void @_ZN12cudaCompress4util24predictor7_tiles_wnllCPUEPKfPfPsiiii(ptr noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

declare void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef, ptr noundef, i32 noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #4 align 2

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"float", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cudaCompress::BitStream" = type <{ %"class.cudaCompress::BitStreamReadOnly.base", [4 x i8], ptr, i8, [7 x i8] }>
%"class.cudaCompress::BitStreamReadOnly.base" = type <{ ptr, ptr, i32, i32, i32 }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::allocator.2" = type { i8 }

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [107 x i8], align 1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN12cudaCompress9BitStreamC2EPSt6vectorIjSaIjEE(ptr noundef nonnull align 8 dereferenceable(41), ptr noundef) unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

declare void @_ZN12cudaCompress4util19predictor7_tilesCPUEPKsPsiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #3

declare void @_ZN12cudaCompress4util12symbolizeCPUEPtPKsjjjjj(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaItEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorItSaItEEC2IPtvEET_S4_RKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef, ptr noundef, ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #5 align 2

declare noundef zeroext i1 @_ZN12cudaCompress15encodeRLHuffCPUEPPNS_9BitStreamEPPSt6vectorItSaItEEjjb(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i1 noundef zeroext) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12cudaCompress16compressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i64 noundef %8, float noundef %9, float noundef %10, i32 noundef %11, float noundef %12, float noundef %13) local_unnamed_addr #5 personality ptr @__gxx_personality_v0 {
  %15 = alloca %"class.cudaCompress::BitStream", align 8
  %16 = alloca ptr, align 8
  %17 = alloca %"class.std::vector.0", align 8
  %18 = alloca %"class.std::allocator.2", align 1
  %19 = alloca ptr, align 8
  %20 = mul nsw i32 %7, %6
  %21 = mul nsw i32 %20, %5
  tail call void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef %1, ptr noundef %2, i32 noundef %21)
  %22 = sext i32 %21 to i64
  %23 = shl nsw i64 %22, 1
  tail call void @llvm.memset.p0.i64(ptr align 4 %3, i8 0, i64 %23, i1 false)
  switch i64 %8, label %29 [
    i64 1, label %24
    i64 3, label %24
    i64 11, label %24
    i64 2, label %26
  ]

24:                                               ; preds = %14, %14, %14
  tail call void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef %2, ptr noundef %2, i32 noundef %21, float noundef %10, float noundef %12, float noundef %13)
  %25 = fdiv float 1.000000e+00, %9
  tail call void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %2, ptr noundef %2, float noundef %25, i32 noundef %21)
  tail call void @_ZN12cudaCompress4util24predictor7_tiles_wnllCPUEPKfPfPsiiii(ptr noundef %2, ptr noundef %3, ptr noundef %1, i32 noundef %5, i32 noundef %5, i32 noundef %20, i32 noundef %11)
  br label %29

26:                                               ; preds = %14
  tail call void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef %2, ptr noundef %2, i32 noundef %21, float noundef %10, float noundef %12, float noundef %13)
  %27 = fdiv float 1.000000e+00, %9
  tail call void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %2, ptr noundef %2, float noundef %27, i32 noundef %21)
  tail call void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef %2, ptr noundef %3, i32 noundef %21)
  %28 = shl i32 %5, 1
  tail call void @_ZN12cudaCompress4util19predictor7_tilesCPUEPKsPsiiii(ptr noundef %3, ptr noundef %1, i32 noundef %28, i32 noundef %5, i32 noundef %20, i32 noundef %11)
  br label %29

29:                                               ; preds = %14, %26, %24
  tail call void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 508)
  tail call void @_ZN12cudaCompress4util12symbolizeCPUEPtPKsjjjjj(ptr noundef %4, ptr noundef %1, i32 noundef %5, i32 noundef %20, i32 noundef 1, i32 noundef 0, i32 noundef 0)
  call void @llvm.lifetime.start.p0(i64 48, ptr nonnull %15) #7
  call void @_ZN12cudaCompress9BitStreamC2EPSt6vectorIjSaIjEE(ptr noundef nonnull align 8 dereferenceable(41) %15, ptr noundef nonnull %0)
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %16) #7
  store ptr %15, ptr %16, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %17) #7
  %30 = getelementptr inbounds i16, ptr %4, i64 %22
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %18) #7
  call void @_ZNSaItEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %18) #7
  invoke void @_ZNSt6vectorItSaItEEC2IPtvEET_S4_RKS0_(ptr noundef nonnull align 8 dereferenceable(24) %17, ptr noundef %4, ptr noundef %30, ptr noundef nonnull align 1 dereferenceable(1) %18)
          to label %31 unwind label %34

31:                                               ; preds = %29
  call void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %18) #7
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %18) #7
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %19) #7
  store ptr %17, ptr %19, align 8, !tbaa !5
  %32 = invoke noundef zeroext i1 @_ZN12cudaCompress15encodeRLHuffCPUEPPNS_9BitStreamEPPSt6vectorItSaItEEjjb(ptr noundef nonnull %16, ptr noundef nonnull %19, i32 noundef 1, i32 noundef 128, i1 noundef zeroext true)
          to label %33 unwind label %36

33:                                               ; preds = %31
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %19) #7
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #7
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %17) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %16) #7
  call void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41) %15) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr nonnull %15) #7
  ret void

34:                                               ; preds = %29
  %35 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %18) #7
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %18) #7
  br label %38

36:                                               ; preds = %31
  %37 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %19) #7
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #7
  br label %38

38:                                               ; preds = %36, %34
  %.pn = phi { ptr, i32 } [ %37, %36 ], [ %35, %34 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %17) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %16) #7
  call void @_ZN12cudaCompress9BitStreamD2Ev(ptr noundef nonnull align 8 dereferenceable(41) %15) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr nonnull %15) #7
  resume { ptr, i32 } %.pn
}

declare void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #6

declare void @_ZN12cudaCompress4util6vstCPUEPfS1_ifff(ptr noundef, ptr noundef, i32 noundef, float noundef, float noundef, float noundef) local_unnamed_addr #3

declare void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef, ptr noundef, float noundef, i32 noundef) local_unnamed_addr #3

declare void @_ZN12cudaCompress4util24predictor7_tiles_wnllCPUEPKfPfPsiiii(ptr noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #3

declare void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorItED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #4 align 2

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass