; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (hs_mmcsd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @HSMMCSDIntClock(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HSMMCSDIsIntClockStable(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HSMMCSDBusFreqSet(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store volatile i32 0, ptr %10, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  store volatile i32 0, ptr %11, align 4, !tbaa !5
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = call i32 @HSMMCSDIntClock(i32 noundef %13, i32 noundef 1)
  %15 = icmp eq i32 %14, -1
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 -1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %78

17:                                               ; preds = %4
  %18 = load i32, ptr %9, align 4, !tbaa !5
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %77

20:                                               ; preds = %17
  %21 = load i32, ptr %7, align 4, !tbaa !5
  %22 = load i32, ptr %8, align 4, !tbaa !5
  %23 = udiv i32 %21, %22
  store volatile i32 %23, ptr %10, align 4, !tbaa !5
  %24 = load volatile i32, ptr %10, align 4, !tbaa !5
  %25 = icmp ult i32 %24, 2
  br i1 %25, label %26, label %27

26:                                               ; preds = %20
  br label %29

27:                                               ; preds = %20
  %28 = load volatile i32, ptr %10, align 4, !tbaa !5
  br label %29

29:                                               ; preds = %27, %26
  %30 = phi i32 [ 2, %26 ], [ %28, %27 ]
  store volatile i32 %30, ptr %10, align 4, !tbaa !5
  %31 = load volatile i32, ptr %10, align 4, !tbaa !5
  %32 = icmp ugt i32 %31, 1023
  br i1 %32, label %33, label %34

33:                                               ; preds = %29
  br label %36

34:                                               ; preds = %29
  %35 = load volatile i32, ptr %10, align 4, !tbaa !5
  br label %36

36:                                               ; preds = %34, %33
  %37 = phi i32 [ 1023, %33 ], [ %35, %34 ]
  store volatile i32 %37, ptr %10, align 4, !tbaa !5
  br label %38

38:                                               ; preds = %48, %36
  %39 = load i32, ptr %7, align 4, !tbaa !5
  %40 = load volatile i32, ptr %10, align 4, !tbaa !5
  %41 = udiv i32 %39, %40
  %42 = load i32, ptr %8, align 4, !tbaa !5
  %43 = icmp ugt i32 %41, %42
  br i1 %43, label %44, label %51

44:                                               ; preds = %38
  %45 = load volatile i32, ptr %10, align 4, !tbaa !5
  %46 = icmp eq i32 %45, 1023
  br i1 %46, label %47, label %48

47:                                               ; preds = %44
  store i32 -1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %78

48:                                               ; preds = %44
  %49 = load volatile i32, ptr %10, align 4, !tbaa !5
  %50 = add i32 %49, 1
  store volatile i32 %50, ptr %10, align 4, !tbaa !5
  br label %38, !llvm.loop !9

51:                                               ; preds = %38
  %52 = load i32, ptr %6, align 4, !tbaa !5
  %53 = add i32 %52, 556
  %54 = zext i32 %53 to i64
  %55 = inttoptr i64 %54 to ptr
  %56 = load volatile i32, ptr %55, align 4, !tbaa !5
  %57 = and i32 %56, -65473
  store volatile i32 %57, ptr %11, align 4, !tbaa !5
  %58 = load volatile i32, ptr %11, align 4, !tbaa !5
  %59 = load volatile i32, ptr %10, align 4, !tbaa !5
  %60 = shl i32 %59, 6
  %61 = or i32 %58, %60
  %62 = load i32, ptr %6, align 4, !tbaa !5
  %63 = add i32 %62, 556
  %64 = zext i32 %63 to i64
  %65 = inttoptr i64 %64 to ptr
  store volatile i32 %61, ptr %65, align 4, !tbaa !5
  %66 = load i32, ptr %6, align 4, !tbaa !5
  %67 = call i32 @HSMMCSDIsIntClockStable(i32 noundef %66, i32 noundef 65535)
  %68 = icmp eq i32 %67, 0
  br i1 %68, label %69, label %70

69:                                               ; preds = %51
  store i32 -1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %78

70:                                               ; preds = %51
  %71 = load i32, ptr %6, align 4, !tbaa !5
  %72 = add i32 %71, 556
  %73 = zext i32 %72 to i64
  %74 = inttoptr i64 %73 to ptr
  %75 = load volatile i32, ptr %74, align 4, !tbaa !5
  %76 = or i32 %75, 4
  store volatile i32 %76, ptr %74, align 4, !tbaa !5
  br label %77

77:                                               ; preds = %70, %17
  store i32 0, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %78

78:                                               ; preds = %77, %69, %47, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %79 = load i32, ptr %5, align 4
  ret i32 %79
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @HSMMCSDIntClock(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HSMMCSDIsIntClockStable(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @HSMMCSDBusFreqSet(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5)
  store volatile i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6)
  store volatile i32 0, ptr %6, align 4, !tbaa !5
  %7 = tail call i32 @HSMMCSDIntClock(i32 noundef %0, i32 noundef 1)
  %8 = icmp eq i32 %7, -1
  br i1 %8, label %.loopexit, label %9

9:                                                ; preds = %4
  %10 = icmp eq i32 %3, 0
  br i1 %10, label %11, label %.loopexit

11:                                               ; preds = %9
  %12 = udiv i32 %1, %2
  store volatile i32 %12, ptr %5, align 4, !tbaa !5
  %.0..0..0..0.1 = load volatile i32, ptr %5, align 4, !tbaa !5
  %13 = icmp ult i32 %.0..0..0..0.1, 2
  br i1 %13, label %15, label %14

14:                                               ; preds = %11
  %.0..0..0..0.2 = load volatile i32, ptr %5, align 4, !tbaa !5
  br label %15

15:                                               ; preds = %11, %14
  %16 = phi i32 [ %.0..0..0..0.2, %14 ], [ 2, %11 ]
  store volatile i32 %16, ptr %5, align 4, !tbaa !5
  %.0..0..0..0.3 = load volatile i32, ptr %5, align 4, !tbaa !5
  %17 = icmp ugt i32 %.0..0..0..0.3, 1023
  br i1 %17, label %19, label %18

18:                                               ; preds = %15
  %.0..0..0..0.4 = load volatile i32, ptr %5, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %15, %18
  %20 = phi i32 [ %.0..0..0..0.4, %18 ], [ 1023, %15 ]
  store volatile i32 %20, ptr %5, align 4, !tbaa !5
  %.0..0..0..0.519 = load volatile i32, ptr %5, align 4, !tbaa !5
  %21 = udiv i32 %1, %.0..0..0..0.519
  %22 = icmp ugt i32 %21, %2
  br i1 %22, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %19, %24
  %.0..0..0..0.6 = load volatile i32, ptr %5, align 4, !tbaa !5
  %23 = icmp eq i32 %.0..0..0..0.6, 1023
  br i1 %23, label %.loopexit, label %24

24:                                               ; preds = %.lr.ph
  %.0..0..0..0.7 = load volatile i32, ptr %5, align 4, !tbaa !5
  %25 = add i32 %.0..0..0..0.7, 1
  store volatile i32 %25, ptr %5, align 4, !tbaa !5
  %.0..0..0..0.5 = load volatile i32, ptr %5, align 4, !tbaa !5
  %26 = udiv i32 %1, %.0..0..0..0.5
  %27 = icmp ugt i32 %26, %2
  br i1 %27, label %.lr.ph, label %._crit_edge, !llvm.loop !9

._crit_edge:                                      ; preds = %24, %19
  %28 = add i32 %0, 556
  %29 = zext i32 %28 to i64
  %30 = inttoptr i64 %29 to ptr
  %31 = load volatile i32, ptr %30, align 4, !tbaa !5
  %32 = and i32 %31, -65473
  store volatile i32 %32, ptr %6, align 4, !tbaa !5
  %.0..0..0..0. = load volatile i32, ptr %6, align 4, !tbaa !5
  %.0..0..0..0.8 = load volatile i32, ptr %5, align 4, !tbaa !5
  %33 = shl i32 %.0..0..0..0.8, 6
  %34 = or i32 %33, %.0..0..0..0.
  store volatile i32 %34, ptr %30, align 4, !tbaa !5
  %35 = tail call i32 @HSMMCSDIsIntClockStable(i32 noundef %0, i32 noundef 65535)
  %36 = icmp eq i32 %35, 0
  br i1 %36, label %.loopexit, label %37

37:                                               ; preds = %._crit_edge
  %38 = load volatile i32, ptr %30, align 4, !tbaa !5
  %39 = or i32 %38, 4
  store volatile i32 %39, ptr %30, align 4, !tbaa !5
  br label %.loopexit

.loopexit:                                        ; preds = %.lr.ph, %9, %37, %._crit_edge, %4
  %.0 = phi i32 [ -1, %4 ], [ -1, %._crit_edge ], [ 0, %37 ], [ 0, %9 ], [ -1, %.lr.ph ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5)
  ret i32 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass