; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (uart_irda_cir)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTRegConfigModeEnable(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @UARTCharGetTimeout(i32 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 -1, ptr %6, align 4, !tbaa !5
  %7 = load i32, ptr %3, align 4, !tbaa !5
  %8 = call i32 @UARTRegConfigModeEnable(i32 noundef %7, i32 noundef 127)
  store i32 %8, ptr %5, align 4, !tbaa !5
  br label %9

9:                                                ; preds = %22, %2
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = add i32 %10, 20
  %12 = zext i32 %11 to i64
  %13 = inttoptr i64 %12 to ptr
  %14 = load volatile i32, ptr %13, align 4, !tbaa !5
  %15 = and i32 %14, 1
  %16 = icmp eq i32 0, %15
  br i1 %16, label %17, label %20

17:                                               ; preds = %9
  %18 = load i32, ptr %4, align 4, !tbaa !5
  %19 = icmp ne i32 %18, 0
  br label %20

20:                                               ; preds = %17, %9
  %21 = phi i1 [ false, %9 ], [ %19, %17 ]
  br i1 %21, label %22, label %25

22:                                               ; preds = %20
  %23 = load i32, ptr %4, align 4, !tbaa !5
  %24 = add i32 %23, -1
  store i32 %24, ptr %4, align 4, !tbaa !5
  br label %9, !llvm.loop !9

25:                                               ; preds = %20
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %35

28:                                               ; preds = %25
  %29 = load i32, ptr %3, align 4, !tbaa !5
  %30 = add i32 %29, 0
  %31 = zext i32 %30 to i64
  %32 = inttoptr i64 %31 to ptr
  %33 = load volatile i32, ptr %32, align 4, !tbaa !5
  %34 = and i32 %33, 255
  store i32 %34, ptr %6, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %28, %25
  %36 = load i32, ptr %5, align 4, !tbaa !5
  %37 = load i32, ptr %3, align 4, !tbaa !5
  %38 = add i32 %37, 12
  %39 = zext i32 %38 to i64
  %40 = inttoptr i64 %39 to ptr
  store volatile i32 %36, ptr %40, align 4, !tbaa !5
  %41 = load i32, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 %41
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @UARTRegConfigModeEnable(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 256) i32 @UARTCharGetTimeout(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call i32 @UARTRegConfigModeEnable(i32 noundef %0, i32 noundef 127)
  %4 = add i32 %0, 20
  %5 = zext i32 %4 to i64
  %6 = inttoptr i64 %5 to ptr
  br label %7

7:                                                ; preds = %7, %2
  %.09 = phi i32 [ %1, %2 ], [ %13, %7 ]
  %8 = load volatile i32, ptr %6, align 4, !tbaa !5
  %9 = and i32 %8, 1
  %10 = icmp eq i32 %9, 0
  %11 = icmp ne i32 %.09, 0
  %12 = select i1 %10, i1 %11, i1 false
  %13 = add i32 %.09, -1
  br i1 %12, label %7, label %14, !llvm.loop !9

14:                                               ; preds = %7
  br i1 %11, label %15, label %20

15:                                               ; preds = %14
  %16 = zext i32 %0 to i64
  %17 = inttoptr i64 %16 to ptr
  %18 = load volatile i32, ptr %17, align 4, !tbaa !5
  %19 = and i32 %18, 255
  br label %20

20:                                               ; preds = %15, %14
  %.0 = phi i32 [ %19, %15 ], [ -1, %14 ]
  %21 = add i32 %0, 12
  %22 = zext i32 %21 to i64
  %23 = inttoptr i64 %22 to ptr
  store volatile i32 %3, ptr %23, align 4, !tbaa !5
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass