; LLVM IR from balintbalazs/B3D :: source/src/B3D_cudaCompress/B3D (B3DcompressFunctions)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cudaCompress::BitStreamReadOnly" = type <{ ptr, ptr, i32, i32, i32, [4 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.1 = external hidden unnamed_addr constant [107 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [39 x i8], align 1
@__PRETTY_FUNCTION__._ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff = external hidden unnamed_addr constant [156 x i8], align 1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorIjSaIjEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIjSaIjEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress17BitStreamReadOnlyC2EPKjj(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

declare noundef zeroext i1 @_ZN12cudaCompress15decodeRLHuffCPUEPPNS_17BitStreamReadOnlyEPPSt6vectorItSaItEEjjjb(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i1 noundef zeroext) #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorItSaItEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorItSaItEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

declare void @_ZN12cudaCompress4util14unsymbolizeCPUEPsPKtjjjjj(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #5

declare void @_ZN12cudaCompress4util21unPredictor7_tilesCPUEPKsPsiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #5

declare void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef, ptr noundef, i32 noundef) #5

declare void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef, ptr noundef, float noundef, i32 noundef) #5

declare void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef, ptr noundef, i32 noundef) #5

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i64 noundef %8, float noundef %9, float noundef %10, i32 noundef %11, float noundef %12, float noundef %13) #7 personality ptr @__gxx_personality_v0 {
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i64, align 8
  %24 = alloca float, align 4
  %25 = alloca float, align 4
  %26 = alloca i32, align 4
  %27 = alloca float, align 4
  %28 = alloca float, align 4
  %29 = alloca %"class.cudaCompress::BitStreamReadOnly", align 8
  %30 = alloca ptr, align 8
  %31 = alloca %"class.std::vector.0", align 8
  %32 = alloca ptr, align 8
  %33 = alloca ptr, align 8
  %34 = alloca i32, align 4
  store ptr %0, ptr %15, align 8, !tbaa !5
  store ptr %1, ptr %16, align 8, !tbaa !5
  store ptr %2, ptr %17, align 8, !tbaa !5
  store ptr %3, ptr %18, align 8, !tbaa !5
  store ptr %4, ptr %19, align 8, !tbaa !5
  store i32 %5, ptr %20, align 4, !tbaa !9
  store i32 %6, ptr %21, align 4, !tbaa !9
  store i32 %7, ptr %22, align 4, !tbaa !9
  store i64 %8, ptr %23, align 8, !tbaa !11
  store float %9, ptr %24, align 4, !tbaa !13
  store float %10, ptr %25, align 4, !tbaa !13
  store i32 %11, ptr %26, align 4, !tbaa !9
  store float %12, ptr %27, align 4, !tbaa !13
  store float %13, ptr %28, align 4, !tbaa !13
  %35 = load i32, ptr %21, align 4, !tbaa !9
  %36 = load i32, ptr %22, align 4, !tbaa !9
  %37 = mul nsw i32 %35, %36
  store i32 %37, ptr %21, align 4, !tbaa !9
  store i32 1, ptr %22, align 4, !tbaa !9
  %38 = load i64, ptr %23, align 8, !tbaa !11
  %39 = sub i64 %38, 100
  store i64 %39, ptr %23, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 32, ptr %29) #8
  %40 = load ptr, ptr %15, align 8, !tbaa !5
  %41 = call noundef ptr @_ZNSt6vectorIjSaIjEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %40) #8
  %42 = load ptr, ptr %15, align 8, !tbaa !5
  %43 = call noundef i64 @_ZNKSt6vectorIjSaIjEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %42) #8
  %44 = mul i64 %43, 4
  %45 = mul i64 %44, 8
  %46 = trunc i64 %45 to i32
  call void @_ZN12cudaCompress17BitStreamReadOnlyC2EPKjj(ptr noundef nonnull align 8 dereferenceable(28) %29, ptr noundef %41, i32 noundef %46)
  call void @llvm.lifetime.start.p0(i64 8, ptr %30) #8
  store ptr %29, ptr %30, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 24, ptr %31) #8
  call void @_ZNSt6vectorItSaItEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %31) #8
  call void @llvm.lifetime.start.p0(i64 8, ptr %32) #8
  store ptr %31, ptr %32, align 8, !tbaa !5
  %47 = load i32, ptr %20, align 4, !tbaa !9
  %48 = load i32, ptr %21, align 4, !tbaa !9
  %49 = mul nsw i32 %47, %48
  %50 = invoke noundef zeroext i1 @_ZN12cudaCompress15decodeRLHuffCPUEPPNS_17BitStreamReadOnlyEPPSt6vectorItSaItEEjjjb(ptr noundef %30, ptr noundef %32, i32 noundef %49, i32 noundef 1, i32 noundef 128, i1 noundef zeroext true)
          to label %51 unwind label %60

51:                                               ; preds = %14
  %52 = call noundef i64 @_ZNKSt6vectorItSaItEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %31) #8
  %53 = load i32, ptr %20, align 4, !tbaa !9
  %54 = load i32, ptr %21, align 4, !tbaa !9
  %55 = mul nsw i32 %53, %54
  %56 = sext i32 %55 to i64
  %57 = icmp eq i64 %52, %56
  br i1 %57, label %58, label %59

58:                                               ; preds = %51
  br label %65

59:                                               ; preds = %51
  call void @__assert_fail(ptr noundef @.str.3, ptr noundef @.str.1, i32 noundef 542, ptr noundef @__PRETTY_FUNCTION__._ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff) #9
  unreachable

60:                                               ; preds = %153, %145, %136, %129, %123, %113, %106, %97, %90, %80, %65, %14
  %61 = landingpad { ptr, i32 }
          cleanup
  %62 = extractvalue { ptr, i32 } %61, 0
  store ptr %62, ptr %33, align 8
  %63 = extractvalue { ptr, i32 } %61, 1
  store i32 %63, ptr %34, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %32) #8
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %31) #8
  call void @llvm.lifetime.end.p0(i64 24, ptr %31) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %30) #8
  call void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28) %29) #8
  call void @llvm.lifetime.end.p0(i64 32, ptr %29) #8
  br label %155

64:                                               ; No predecessors!
  br label %65

65:                                               ; preds = %64, %58
  %66 = load ptr, ptr %19, align 8, !tbaa !5
  %67 = call noundef ptr @_ZNSt6vectorItSaItEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %31) #8
  %68 = load i32, ptr %20, align 4, !tbaa !9
  %69 = load i32, ptr %21, align 4, !tbaa !9
  %70 = mul nsw i32 %68, %69
  %71 = sext i32 %70 to i64
  %72 = mul i64 %71, 2
  call void @llvm.memcpy.p0.p0.i64(ptr align 2 %66, ptr align 2 %67, i64 %72, i1 false)
  %73 = load ptr, ptr %16, align 8, !tbaa !5
  %74 = load ptr, ptr %19, align 8, !tbaa !5
  %75 = load i32, ptr %20, align 4, !tbaa !9
  %76 = load i32, ptr %21, align 4, !tbaa !9
  %77 = load i32, ptr %22, align 4, !tbaa !9
  invoke void @_ZN12cudaCompress4util14unsymbolizeCPUEPsPKtjjjjj(ptr noundef %73, ptr noundef %74, i32 noundef %75, i32 noundef %76, i32 noundef %77, i32 noundef 0, i32 noundef 0)
          to label %78 unwind label %60

78:                                               ; preds = %65
  %79 = load i64, ptr %23, align 8, !tbaa !11
  switch i64 %79, label %152 [
    i64 1, label %80
    i64 11, label %80
    i64 2, label %113
  ]

80:                                               ; preds = %78, %78
  %81 = load ptr, ptr %16, align 8, !tbaa !5
  %82 = load ptr, ptr %17, align 8, !tbaa !5
  %83 = load i32, ptr %20, align 4, !tbaa !9
  %84 = sext i32 %83 to i64
  %85 = mul i64 %84, 2
  %86 = trunc i64 %85 to i32
  %87 = load i32, ptr %20, align 4, !tbaa !9
  %88 = load i32, ptr %21, align 4, !tbaa !9
  %89 = load i32, ptr %26, align 4, !tbaa !9
  invoke void @_ZN12cudaCompress4util26unPredictor7_tiles_wnllCPUEPKsPfiiii(ptr noundef %81, ptr noundef %82, i32 noundef %86, i32 noundef %87, i32 noundef %88, i32 noundef %89)
          to label %90 unwind label %60

90:                                               ; preds = %80
  %91 = load ptr, ptr %17, align 8, !tbaa !5
  %92 = load ptr, ptr %17, align 8, !tbaa !5
  %93 = load float, ptr %24, align 4, !tbaa !13
  %94 = load i32, ptr %20, align 4, !tbaa !9
  %95 = load i32, ptr %21, align 4, !tbaa !9
  %96 = mul nsw i32 %94, %95
  invoke void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %91, ptr noundef %92, float noundef %93, i32 noundef %96)
          to label %97 unwind label %60

97:                                               ; preds = %90
  %98 = load ptr, ptr %17, align 8, !tbaa !5
  %99 = load ptr, ptr %17, align 8, !tbaa !5
  %100 = load i32, ptr %20, align 4, !tbaa !9
  %101 = load i32, ptr %21, align 4, !tbaa !9
  %102 = mul nsw i32 %100, %101
  %103 = load float, ptr %25, align 4, !tbaa !13
  %104 = load float, ptr %27, align 4, !tbaa !13
  %105 = load float, ptr %28, align 4, !tbaa !13
  invoke void @_ZN12cudaCompress4util9invVstCPUEPfS1_ifff(ptr noundef %98, ptr noundef %99, i32 noundef %102, float noundef %103, float noundef %104, float noundef %105)
          to label %106 unwind label %60

106:                                              ; preds = %97
  %107 = load ptr, ptr %17, align 8, !tbaa !5
  %108 = load ptr, ptr %16, align 8, !tbaa !5
  %109 = load i32, ptr %20, align 4, !tbaa !9
  %110 = load i32, ptr %21, align 4, !tbaa !9
  %111 = mul nsw i32 %109, %110
  invoke void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef %107, ptr noundef %108, i32 noundef %111)
          to label %112 unwind label %60

112:                                              ; preds = %106
  br label %153

113:                                              ; preds = %78
  %114 = load ptr, ptr %16, align 8, !tbaa !5
  %115 = load ptr, ptr %18, align 8, !tbaa !5
  %116 = load i32, ptr %20, align 4, !tbaa !9
  %117 = sext i32 %116 to i64
  %118 = mul i64 %117, 2
  %119 = trunc i64 %118 to i32
  %120 = load i32, ptr %20, align 4, !tbaa !9
  %121 = load i32, ptr %21, align 4, !tbaa !9
  %122 = load i32, ptr %26, align 4, !tbaa !9
  invoke void @_ZN12cudaCompress4util21unPredictor7_tilesCPUEPKsPsiiii(ptr noundef %114, ptr noundef %115, i32 noundef %119, i32 noundef %120, i32 noundef %121, i32 noundef %122)
          to label %123 unwind label %60

123:                                              ; preds = %113
  %124 = load ptr, ptr %18, align 8, !tbaa !5
  %125 = load ptr, ptr %17, align 8, !tbaa !5
  %126 = load i32, ptr %20, align 4, !tbaa !9
  %127 = load i32, ptr %21, align 4, !tbaa !9
  %128 = mul nsw i32 %126, %127
  invoke void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef %124, ptr noundef %125, i32 noundef %128)
          to label %129 unwind label %60

129:                                              ; preds = %123
  %130 = load ptr, ptr %17, align 8, !tbaa !5
  %131 = load ptr, ptr %17, align 8, !tbaa !5
  %132 = load float, ptr %24, align 4, !tbaa !13
  %133 = load i32, ptr %20, align 4, !tbaa !9
  %134 = load i32, ptr %21, align 4, !tbaa !9
  %135 = mul nsw i32 %133, %134
  invoke void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %130, ptr noundef %131, float noundef %132, i32 noundef %135)
          to label %136 unwind label %60

136:                                              ; preds = %129
  %137 = load ptr, ptr %17, align 8, !tbaa !5
  %138 = load ptr, ptr %17, align 8, !tbaa !5
  %139 = load i32, ptr %20, align 4, !tbaa !9
  %140 = load i32, ptr %21, align 4, !tbaa !9
  %141 = mul nsw i32 %139, %140
  %142 = load float, ptr %25, align 4, !tbaa !13
  %143 = load float, ptr %27, align 4, !tbaa !13
  %144 = load float, ptr %28, align 4, !tbaa !13
  invoke void @_ZN12cudaCompress4util9invVstCPUEPfS1_ifff(ptr noundef %137, ptr noundef %138, i32 noundef %141, float noundef %142, float noundef %143, float noundef %144)
          to label %145 unwind label %60

145:                                              ; preds = %136
  %146 = load ptr, ptr %17, align 8, !tbaa !5
  %147 = load ptr, ptr %16, align 8, !tbaa !5
  %148 = load i32, ptr %20, align 4, !tbaa !9
  %149 = load i32, ptr %21, align 4, !tbaa !9
  %150 = mul nsw i32 %148, %149
  invoke void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef %146, ptr noundef %147, i32 noundef %150)
          to label %151 unwind label %60

151:                                              ; preds = %145
  br label %153

152:                                              ; preds = %78
  br label %153

153:                                              ; preds = %152, %151, %112
  invoke void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 572)
          to label %154 unwind label %60

154:                                              ; preds = %153
  call void @llvm.lifetime.end.p0(i64 8, ptr %32) #8
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %31) #8
  call void @llvm.lifetime.end.p0(i64 24, ptr %31) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %30) #8
  call void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28) %29) #8
  call void @llvm.lifetime.end.p0(i64 32, ptr %29) #8
  ret void

155:                                              ; preds = %60
  %156 = load ptr, ptr %33, align 8
  %157 = load i32, ptr %34, align 4
  %158 = insertvalue { ptr, i32 } poison, ptr %156, 0
  %159 = insertvalue { ptr, i32 } %158, i32 %157, 1
  resume { ptr, i32 } %159
}

declare void @_ZN12cudaCompress4util26unPredictor7_tiles_wnllCPUEPKsPfiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #5

declare void @_ZN12cudaCompress4util9invVstCPUEPfS1_ifff(ptr noundef, ptr noundef, i32 noundef, float noundef, float noundef, float noundef) #5

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"float", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cudaCompress::BitStreamReadOnly" = type <{ ptr, ptr, i32, i32, i32, [4 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.1 = external hidden unnamed_addr constant [107 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [19 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [39 x i8], align 1
@__PRETTY_FUNCTION__._ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff = external hidden unnamed_addr constant [156 x i8], align 1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorIjSaIjEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIjSaIjEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN12cudaCompress17BitStreamReadOnlyC2EPKjj(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorItSaItEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

declare noundef zeroext i1 @_ZN12cudaCompress15decodeRLHuffCPUEPPNS_17BitStreamReadOnlyEPPSt6vectorItSaItEEjjjb(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i1 noundef zeroext) local_unnamed_addr #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorItSaItEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorItSaItEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

declare void @_ZN12cudaCompress4util14unsymbolizeCPUEPsPKtjjjjj(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN12cudaCompress4util21unPredictor7_tilesCPUEPKsPsiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef, ptr noundef, float noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #5

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i64 noundef %8, float noundef %9, float noundef %10, i32 noundef %11, float noundef %12, float noundef %13) local_unnamed_addr #7 personality ptr @__gxx_personality_v0 {
  %15 = alloca %"class.cudaCompress::BitStreamReadOnly", align 8
  %16 = alloca ptr, align 8
  %17 = alloca %"class.std::vector.0", align 8
  %18 = alloca ptr, align 8
  %19 = mul nsw i32 %7, %6
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %15) #8
  %20 = tail call noundef ptr @_ZNSt6vectorIjSaIjEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #8
  %21 = tail call noundef i64 @_ZNKSt6vectorIjSaIjEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #8
  %.tr = trunc i64 %21 to i32
  %22 = shl i32 %.tr, 5
  call void @_ZN12cudaCompress17BitStreamReadOnlyC2EPKjj(ptr noundef nonnull align 8 dereferenceable(28) %15, ptr noundef %20, i32 noundef %22)
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %16) #8
  store ptr %15, ptr %16, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %17) #8
  call void @_ZNSt6vectorItSaItEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %18) #8
  store ptr %17, ptr %18, align 8, !tbaa !5
  %23 = mul nsw i32 %19, %5
  %24 = invoke noundef zeroext i1 @_ZN12cudaCompress15decodeRLHuffCPUEPPNS_17BitStreamReadOnlyEPPSt6vectorItSaItEEjjjb(ptr noundef nonnull %16, ptr noundef nonnull %18, i32 noundef %23, i32 noundef 1, i32 noundef 128, i1 noundef zeroext true)
          to label %25 unwind label %30

25:                                               ; preds = %14
  %26 = call noundef i64 @_ZNKSt6vectorItSaItEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #8
  %27 = sext i32 %23 to i64
  %28 = icmp eq i64 %26, %27
  br i1 %28, label %32, label %29

29:                                               ; preds = %25
  call void @__assert_fail(ptr noundef nonnull @.str.3, ptr noundef nonnull @.str.1, i32 noundef 542, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN12cudaCompress18decompressImageCPUERSt6vectorIjSaIjEEPsPfS5_Ptiiimffiff) #9
  unreachable

30:                                               ; preds = %.invoke68, %.invoke67, %.invoke, %41, %40, %38, %36, %32, %14
  %31 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %18) #8
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #8
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %17) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %16) #8
  call void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28) %15) #8
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %15) #8
  resume { ptr, i32 } %31

32:                                               ; preds = %25
  %33 = call noundef ptr @_ZNSt6vectorItSaItEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #8
  %34 = shl nsw i64 %26, 1
  call void @llvm.memcpy.p0.p0.i64(ptr align 2 %4, ptr align 2 %33, i64 %34, i1 false)
  invoke void @_ZN12cudaCompress4util14unsymbolizeCPUEPsPKtjjjjj(ptr noundef %1, ptr noundef %4, i32 noundef %5, i32 noundef %19, i32 noundef 1, i32 noundef 0, i32 noundef 0)
          to label %35 unwind label %30

35:                                               ; preds = %32
  switch i64 %8, label %41 [
    i64 101, label %36
    i64 111, label %36
    i64 102, label %38
  ]

36:                                               ; preds = %35, %35
  %37 = shl i32 %5, 1
  invoke void @_ZN12cudaCompress4util26unPredictor7_tiles_wnllCPUEPKsPfiiii(ptr noundef %1, ptr noundef %2, i32 noundef %37, i32 noundef %5, i32 noundef %19, i32 noundef %11)
          to label %.invoke68 unwind label %30

38:                                               ; preds = %35
  %39 = shl i32 %5, 1
  invoke void @_ZN12cudaCompress4util21unPredictor7_tilesCPUEPKsPsiiii(ptr noundef %1, ptr noundef %3, i32 noundef %39, i32 noundef %5, i32 noundef %19, i32 noundef %11)
          to label %40 unwind label %30

40:                                               ; preds = %38
  invoke void @_ZN12cudaCompress4util6u2fCPUEPtPfi(ptr noundef %3, ptr noundef %2, i32 noundef %23)
          to label %.invoke68 unwind label %30

.invoke68:                                        ; preds = %40, %36
  invoke void @_ZN12cudaCompress4util11multiplyCPUEPfS1_fi(ptr noundef %2, ptr noundef %2, float noundef %9, i32 noundef %23)
          to label %.invoke67 unwind label %30

.invoke67:                                        ; preds = %.invoke68
  invoke void @_ZN12cudaCompress4util9invVstCPUEPfS1_ifff(ptr noundef %2, ptr noundef %2, i32 noundef %23, float noundef %10, float noundef %12, float noundef %13)
          to label %.invoke unwind label %30

.invoke:                                          ; preds = %.invoke67
  invoke void @_ZN12cudaCompress4util6f2uCPUEPfPti(ptr noundef %2, ptr noundef %1, i32 noundef %23)
          to label %41 unwind label %30

41:                                               ; preds = %.invoke, %35
  invoke void @_Z14__cudaCheckMsgPKcS0_i(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 572)
          to label %42 unwind label %30

42:                                               ; preds = %41
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %18) #8
  call void @_ZNSt6vectorItSaItEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #8
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %17) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %16) #8
  call void @_ZN12cudaCompress17BitStreamReadOnlyD2Ev(ptr noundef nonnull align 8 dereferenceable(28) %15) #8
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %15) #8
  ret void
}

declare void @_ZN12cudaCompress4util26unPredictor7_tiles_wnllCPUEPKsPfiiii(ptr noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #5

declare void @_ZN12cudaCompress4util9invVstCPUEPfS1_ifff(ptr noundef, ptr noundef, i32 noundef, float noundef, float noundef, float noundef) local_unnamed_addr #5

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass