; LLVM IR from Eslam-Rizk/Elite-DriveGuard :: Application/Middlewares/Third_Party/FreeRTOS/Source (queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8, i8, i64, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortValidateInterruptPriority() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueReceiveFromISR(ptr noundef %0, ptr noundef %1, ptr noundef %2) #3 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %12, ptr %9, align 8, !tbaa !5
  %13 = load ptr, ptr %9, align 8, !tbaa !5
  %14 = icmp eq ptr %13, null
  br i1 %14, label %15, label %17

15:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %16

16:                                               ; preds = %16, %15
  br label %16

17:                                               ; preds = %3
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = icmp eq ptr %18, null
  br i1 %19, label %20, label %25

20:                                               ; preds = %17
  %21 = load ptr, ptr %9, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.QueueDefinition, ptr %21, i32 0, i32 7
  %23 = load i64, ptr %22, align 8, !tbaa !9
  %24 = icmp ne i64 %23, 0
  br label %25

25:                                               ; preds = %20, %17
  %26 = phi i1 [ false, %17 ], [ %24, %20 ]
  %27 = xor i1 %26, true
  %28 = zext i1 %27 to i32
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %32

30:                                               ; preds = %25
  call void @vPortRaiseBASEPRI()
  br label %31

31:                                               ; preds = %31, %30
  br label %31

32:                                               ; preds = %25
  call void @vPortValidateInterruptPriority()
  %33 = call i32 @ulPortRaiseBASEPRI()
  %34 = zext i32 %33 to i64
  store i64 %34, ptr %8, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %35 = load ptr, ptr %9, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.QueueDefinition, ptr %35, i32 0, i32 5
  %37 = load volatile i64, ptr %36, align 8, !tbaa !16
  store i64 %37, ptr %10, align 8, !tbaa !15
  %38 = load i64, ptr %10, align 8, !tbaa !15
  %39 = icmp ugt i64 %38, 0
  br i1 %39, label %40, label %86

40:                                               ; preds = %32
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #4
  %41 = load ptr, ptr %9, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.QueueDefinition, ptr %41, i32 0, i32 8
  %43 = load volatile i8, ptr %42, align 8, !tbaa !17
  store i8 %43, ptr %11, align 1, !tbaa !18
  %44 = load ptr, ptr %9, align 8, !tbaa !5
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  call void @prvCopyDataFromQueue(ptr noundef %44, ptr noundef %45)
  %46 = load i64, ptr %10, align 8, !tbaa !15
  %47 = sub i64 %46, 1
  %48 = load ptr, ptr %9, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.QueueDefinition, ptr %48, i32 0, i32 5
  store volatile i64 %47, ptr %49, align 8, !tbaa !16
  %50 = load i8, ptr %11, align 1, !tbaa !18
  %51 = sext i8 %50 to i32
  %52 = icmp eq i32 %51, -1
  br i1 %52, label %53, label %78

53:                                               ; preds = %40
  %54 = load ptr, ptr %9, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.QueueDefinition, ptr %54, i32 0, i32 3
  %56 = getelementptr inbounds %struct.xLIST, ptr %55, i32 0, i32 0
  %57 = load volatile i64, ptr %56, align 8, !tbaa !19
  %58 = icmp eq i64 %57, 0
  %59 = zext i1 %58 to i64
  %60 = select i1 %58, i64 1, i64 0
  %61 = icmp eq i64 %60, 0
  br i1 %61, label %62, label %76

62:                                               ; preds = %53
  %63 = load ptr, ptr %9, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.QueueDefinition, ptr %63, i32 0, i32 3
  %65 = call i64 @xTaskRemoveFromEventList(ptr noundef %64)
  %66 = icmp ne i64 %65, 0
  br i1 %66, label %67, label %74

67:                                               ; preds = %62
  %68 = load ptr, ptr %6, align 8, !tbaa !5
  %69 = icmp ne ptr %68, null
  br i1 %69, label %70, label %72

70:                                               ; preds = %67
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  store i64 1, ptr %71, align 8, !tbaa !15
  br label %73

72:                                               ; preds = %67
  br label %73

73:                                               ; preds = %72, %70
  br label %75

74:                                               ; preds = %62
  br label %75

75:                                               ; preds = %74, %73
  br label %77

76:                                               ; preds = %53
  br label %77

77:                                               ; preds = %76, %75
  br label %85

78:                                               ; preds = %40
  %79 = load i8, ptr %11, align 1, !tbaa !18
  %80 = sext i8 %79 to i32
  %81 = add nsw i32 %80, 1
  %82 = trunc i32 %81 to i8
  %83 = load ptr, ptr %9, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.QueueDefinition, ptr %83, i32 0, i32 8
  store volatile i8 %82, ptr %84, align 8, !tbaa !17
  br label %85

85:                                               ; preds = %78, %77
  store i64 1, ptr %7, align 8, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #4
  br label %87

86:                                               ; preds = %32
  store i64 0, ptr %7, align 8, !tbaa !15
  br label %87

87:                                               ; preds = %86, %85
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  %88 = load i64, ptr %8, align 8, !tbaa !15
  %89 = trunc i64 %88 to i32
  call void @vPortSetBASEPRI(i32 noundef %89)
  %90 = load i64, ptr %7, align 8, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret i64 %90
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 128}
!10 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !11, i64 32, !11, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137, !7, i64 138, !12, i64 144, !7, i64 152}
!11 = !{!"xLIST", !12, i64 0, !6, i64 8, !13, i64 16}
!12 = !{!"long", !7, i64 0}
!13 = !{!"xMINI_LIST_ITEM", !14, i64 0, !6, i64 8, !6, i64 16}
!14 = !{!"int", !7, i64 0}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !12, i64 112}
!17 = !{!10, !7, i64 136}
!18 = !{!7, !7, i64 0}
!19 = !{!10, !12, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #1

declare void @vPortValidateInterruptPriority() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xQueueReceiveFromISR(ptr noundef %0, ptr noundef %1, ptr noundef writeonly %2) local_unnamed_addr #2 {
  %4 = icmp eq ptr %0, null
  br i1 %4, label %5, label %7

5:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %6

6:                                                ; preds = %6, %5
  br label %6

7:                                                ; preds = %3
  %8 = icmp eq ptr %1, null
  br i1 %8, label %9, label %.critedge

9:                                                ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 128
  %11 = load i64, ptr %10, align 8, !tbaa !5
  %.not25 = icmp eq i64 %11, 0
  br i1 %.not25, label %.critedge, label %12

12:                                               ; preds = %9
  tail call void @vPortRaiseBASEPRI()
  br label %13

13:                                               ; preds = %13, %12
  br label %13

.critedge:                                        ; preds = %7, %9
  tail call void @vPortValidateInterruptPriority() #3
  %14 = tail call i32 @ulPortRaiseBASEPRI()
  %15 = getelementptr inbounds i8, ptr %0, i64 112
  %16 = load volatile i64, ptr %15, align 8, !tbaa !14
  %.not = icmp eq i64 %16, 0
  br i1 %.not, label %32, label %17

17:                                               ; preds = %.critedge
  %18 = getelementptr inbounds i8, ptr %0, i64 136
  %19 = load volatile i8, ptr %18, align 8, !tbaa !15
  tail call void @prvCopyDataFromQueue(ptr noundef nonnull %0, ptr noundef %1)
  %20 = add i64 %16, -1
  store volatile i64 %20, ptr %15, align 8, !tbaa !14
  %21 = icmp eq i8 %19, -1
  br i1 %21, label %22, label %30

22:                                               ; preds = %17
  %23 = getelementptr inbounds i8, ptr %0, i64 32
  %24 = load volatile i64, ptr %23, align 8, !tbaa !16
  %.not24 = icmp eq i64 %24, 0
  br i1 %.not24, label %32, label %25

25:                                               ; preds = %22
  %26 = tail call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %23) #3
  %27 = icmp ne i64 %26, 0
  %28 = icmp ne ptr %2, null
  %or.cond = and i1 %28, %27
  br i1 %or.cond, label %29, label %32

29:                                               ; preds = %25
  store i64 1, ptr %2, align 8, !tbaa !17
  br label %32

30:                                               ; preds = %17
  %31 = add nuw i8 %19, 1
  store volatile i8 %31, ptr %18, align 8, !tbaa !15
  br label %32

32:                                               ; preds = %.critedge, %30, %22, %29, %25
  %.0 = phi i64 [ 1, %25 ], [ 1, %29 ], [ 1, %22 ], [ 1, %30 ], [ 0, %.critedge ]
  tail call void @vPortSetBASEPRI(i32 noundef %14)
  ret i64 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 128}
!6 = !{!"QueueDefinition", !7, i64 0, !7, i64 8, !8, i64 16, !10, i64 32, !10, i64 72, !11, i64 112, !11, i64 120, !11, i64 128, !8, i64 136, !8, i64 137, !8, i64 138, !11, i64 144, !8, i64 152}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !7, i64 8, !12, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"xMINI_LIST_ITEM", !13, i64 0, !7, i64 8, !7, i64 16}
!13 = !{!"int", !8, i64 0}
!14 = !{!6, !11, i64 112}
!15 = !{!6, !8, i64 136}
!16 = !{!6, !11, i64 32}
!17 = !{!11, !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass