; LLVM IR from Simple-XX/SimpleKernel :: src/drv/tui/tui.ll (ZN3TUI7set_posE5pos_t)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.pos_t = type { i8, i8 }

@_ZN3TUI3posE = external dso_local global %class.pos_t, align 1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3TUI7set_posE5pos_t(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i16, align 2
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 2, ptr %5) #4
  %7 = getelementptr inbounds %class.pos_t, ptr %1, i32 0, i32 1
  %8 = load i8, ptr %7, align 1, !tbaa !9
  %9 = zext i8 %8 to i64
  %10 = mul i64 %9, 80
  %11 = getelementptr inbounds %class.pos_t, ptr %1, i32 0, i32 0
  %12 = load i8, ptr %11, align 1, !tbaa !11
  %13 = zext i8 %12 to i64
  %14 = add i64 %10, %13
  %15 = trunc i64 %14 to i16
  store i16 %15, ptr %5, align 2, !tbaa !12
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 @_ZN3TUI3posE, ptr align 1 %1, i64 2, i1 false), !tbaa.struct !14
  call void @_ZN4PORT4outbEjh(i32 noundef 980, i8 noundef zeroext 14)
  %16 = load i16, ptr %5, align 2, !tbaa !12
  %17 = zext i16 %16 to i32
  %18 = ashr i32 %17, 8
  %19 = trunc i32 %18 to i8
  call void @_ZN4PORT4outbEjh(i32 noundef 981, i8 noundef zeroext %19)
  call void @_ZN4PORT4outbEjh(i32 noundef 980, i8 noundef zeroext 15)
  %20 = load i16, ptr %5, align 2, !tbaa !12
  %21 = trunc i16 %20 to i8
  call void @_ZN4PORT4outbEjh(i32 noundef 981, i8 noundef zeroext %21)
  call void @llvm.lifetime.end.p0(i64 2, ptr %5) #4
  ret void
}

declare void @_ZN4PORT4outbEjh(i32 noundef, i8 noundef zeroext) #3

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !7, i64 1}
!10 = !{!"_ZTS5pos_t", !7, i64 0, !7, i64 1}
!11 = !{!10, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"short", !7, i64 0}
!14 = !{i64 0, i64 1, !15, i64 1, i64 1, !15}
!15 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.pos_t = type { i8, i8 }

@_ZN3TUI3posE = external dso_local local_unnamed_addr global %class.pos_t, align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3TUI7set_posE5pos_t(ptr nocapture noundef nonnull readnone align 8 dereferenceable(8) %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %1, i64 1
  %4 = load i8, ptr %3, align 1, !tbaa !5
  %5 = zext i8 %4 to i16
  %6 = mul nuw nsw i16 %5, 80
  %7 = load i8, ptr %1, align 1, !tbaa !9
  %8 = zext i8 %7 to i16
  %9 = add nuw nsw i16 %6, %8
  %10 = load i16, ptr %1, align 1
  store i16 %10, ptr @_ZN3TUI3posE, align 1
  tail call void @_ZN4PORT4outbEjh(i32 noundef 980, i8 noundef zeroext 14)
  %11 = lshr i16 %9, 8
  %12 = trunc nuw nsw i16 %11 to i8
  tail call void @_ZN4PORT4outbEjh(i32 noundef 981, i8 noundef zeroext %12)
  tail call void @_ZN4PORT4outbEjh(i32 noundef 980, i8 noundef zeroext 15)
  %13 = trunc i16 %9 to i8
  tail call void @_ZN4PORT4outbEjh(i32 noundef 981, i8 noundef zeroext %13)
  ret void
}

declare void @_ZN4PORT4outbEjh(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 1}
!6 = !{!"_ZTS5pos_t", !7, i64 0, !7, i64 1}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!6, !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass