; LLVM IR from Columbitech/rohc :: src/dprofile.ll (ZNK4ROHC8DProfile9UpdateMSNEtjRt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.ROHC::DProfile" = type <{ ptr, ptr, i16, [2 x i8], i32, i16, i16, i32, i32, i32, i64, i64, i8, [3 x i8], %"struct.ROHC::iphdr", i64, i32, [4 x i8] }>
%"struct.ROHC::iphdr" = type { i8, i8, i16, i16, i16, i8, i8, i16, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i16 @_ZNK4ROHC8DProfile9UpdateMSNEtjRt(ptr noundef nonnull align 8 dereferenceable(92) %0, i16 noundef zeroext %1, i32 noundef %2, ptr noundef nonnull align 2 dereferenceable(2) %3) #1 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca i16, align 2
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !11
  store ptr %3, ptr %8, align 8, !tbaa !5
  %13 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #3
  %14 = getelementptr inbounds %"class.ROHC::DProfile", ptr %13, i32 0, i32 5
  %15 = load i16, ptr %14, align 8, !tbaa !13
  store i16 %15, ptr %9, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %16 = getelementptr inbounds %"class.ROHC::DProfile", ptr %13, i32 0, i32 5
  %17 = load i16, ptr %16, align 8, !tbaa !13
  %18 = zext i16 %17 to i32
  %19 = getelementptr inbounds %"class.ROHC::DProfile", ptr %13, i32 0, i32 16
  %20 = load i32, ptr %19, align 8, !tbaa !21
  %21 = load i32, ptr %7, align 4, !tbaa !11
  %22 = zext i32 %21 to i64
  %23 = call noundef i32 @_ZN4ROHC23LSBWindowPForReorderingENS_12Reordering_tEm(i32 noundef %20, i64 noundef %22)
  %24 = sub nsw i32 %18, %23
  store i32 %24, ptr %10, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #3
  %25 = load i32, ptr %7, align 4, !tbaa !11
  %26 = shl i32 1, %25
  %27 = sub nsw i32 %26, 1
  %28 = trunc i32 %27 to i16
  store i16 %28, ptr %11, align 2, !tbaa !9
  %29 = getelementptr inbounds %"class.ROHC::DProfile", ptr %13, i32 0, i32 5
  %30 = load i16, ptr %29, align 8, !tbaa !13
  %31 = zext i16 %30 to i32
  %32 = load i16, ptr %11, align 2, !tbaa !9
  %33 = zext i16 %32 to i32
  %34 = xor i32 %33, -1
  %35 = and i32 %31, %34
  %36 = load i16, ptr %6, align 2, !tbaa !9
  %37 = zext i16 %36 to i32
  %38 = load i16, ptr %11, align 2, !tbaa !9
  %39 = zext i16 %38 to i32
  %40 = and i32 %37, %39
  %41 = or i32 %35, %40
  %42 = trunc i32 %41 to i16
  %43 = load ptr, ptr %8, align 8, !tbaa !5
  store i16 %42, ptr %43, align 2, !tbaa !9
  %44 = load ptr, ptr %8, align 8, !tbaa !5
  %45 = load i16, ptr %44, align 2, !tbaa !9
  %46 = zext i16 %45 to i32
  %47 = load i32, ptr %10, align 4, !tbaa !11
  %48 = icmp slt i32 %46, %47
  br i1 %48, label %49, label %57

49:                                               ; preds = %4
  %50 = load i32, ptr %7, align 4, !tbaa !11
  %51 = shl i32 1, %50
  %52 = load ptr, ptr %8, align 8, !tbaa !5
  %53 = load i16, ptr %52, align 2, !tbaa !9
  %54 = zext i16 %53 to i32
  %55 = add nsw i32 %54, %51
  %56 = trunc i32 %55 to i16
  store i16 %56, ptr %52, align 2, !tbaa !9
  br label %57

57:                                               ; preds = %49, %4
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #3
  %58 = load ptr, ptr %8, align 8, !tbaa !5
  %59 = load i16, ptr %58, align 2, !tbaa !9
  %60 = zext i16 %59 to i32
  %61 = load i16, ptr %9, align 2, !tbaa !9
  %62 = zext i16 %61 to i32
  %63 = sub nsw i32 %60, %62
  %64 = trunc i32 %63 to i16
  store i16 %64, ptr %12, align 2, !tbaa !9
  %65 = load i16, ptr %12, align 2, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #3
  ret i16 %65
}

declare noundef i32 @_ZN4ROHC23LSBWindowPForReorderingENS_12Reordering_tEm(i32 noundef, i64 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !10, i64 24}
!14 = !{!"_ZTSN4ROHC8DProfileE", !6, i64 8, !10, i64 16, !15, i64 20, !10, i64 24, !10, i64 26, !16, i64 28, !12, i64 32, !12, i64 36, !17, i64 40, !17, i64 48, !18, i64 56, !19, i64 60, !17, i64 80, !20, i64 88}
!15 = !{!"_ZTSN4ROHC8DProfileUt_E", !7, i64 0}
!16 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !7, i64 0}
!17 = !{!"long", !7, i64 0}
!18 = !{!"bool", !7, i64 0}
!19 = !{!"_ZTSN4ROHC5iphdrE", !7, i64 0, !7, i64 0, !7, i64 1, !10, i64 2, !10, i64 4, !10, i64 6, !7, i64 8, !7, i64 9, !10, i64 10, !12, i64 12, !12, i64 16}
!20 = !{!"_ZTSN4ROHC12Reordering_tE", !7, i64 0}
!21 = !{!14, !20, i64 88}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i16 @_ZNK4ROHC8DProfile9UpdateMSNEtjRt(ptr nocapture noundef nonnull readonly align 8 dereferenceable(92) %0, i16 noundef zeroext %1, i32 noundef %2, ptr nocapture noundef nonnull writeonly align 2 dereferenceable(2) %3) local_unnamed_addr #0 align 2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 24
  %6 = load i16, ptr %5, align 8, !tbaa !5
  %7 = zext i16 %6 to i32
  %8 = getelementptr inbounds i8, ptr %0, i64 88
  %9 = load i32, ptr %8, align 8, !tbaa !18
  %10 = zext i32 %2 to i64
  %11 = tail call noundef i32 @_ZN4ROHC23LSBWindowPForReorderingENS_12Reordering_tEm(i32 noundef %9, i64 noundef %10)
  %12 = sub nsw i32 %7, %11
  %13 = shl nuw i32 1, %2
  %14 = add nuw i32 %13, 65535
  %15 = load i16, ptr %5, align 8, !tbaa !5
  %16 = zext i16 %15 to i32
  %17 = sub i32 0, %13
  %18 = and i32 %16, %17
  %19 = zext i16 %1 to i32
  %20 = and i32 %14, %19
  %21 = or i32 %18, %20
  %22 = icmp slt i32 %21, %12
  %23 = select i1 %22, i32 %13, i32 0
  %spec.select = add nuw nsw i32 %23, %21
  %storemerge = trunc i32 %spec.select to i16
  store i16 %storemerge, ptr %3, align 2, !tbaa !19
  %24 = sub i16 %storemerge, %6
  ret i16 %24
}

declare noundef i32 @_ZN4ROHC23LSBWindowPForReorderingENS_12Reordering_tEm(i32 noundef, i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 24}
!6 = !{!"_ZTSN4ROHC8DProfileE", !7, i64 8, !10, i64 16, !11, i64 20, !10, i64 24, !10, i64 26, !12, i64 28, !13, i64 32, !13, i64 36, !14, i64 40, !14, i64 48, !15, i64 56, !16, i64 60, !14, i64 80, !17, i64 88}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"short", !8, i64 0}
!11 = !{!"_ZTSN4ROHC8DProfileUt_E", !8, i64 0}
!12 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"long", !8, i64 0}
!15 = !{!"bool", !8, i64 0}
!16 = !{!"_ZTSN4ROHC5iphdrE", !8, i64 0, !8, i64 0, !8, i64 1, !10, i64 2, !10, i64 4, !10, i64 6, !8, i64 8, !8, i64 9, !10, i64 10, !13, i64 12, !13, i64 16}
!17 = !{!"_ZTSN4ROHC12Reordering_tE", !8, i64 0}
!18 = !{!6, !17, i64 88}
!19 = !{!10, !10, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass