; LLVM IR from Columbitech/rohc :: src/drtp_profile.ll (ZN4ROHC11DRTPProfile15UpdateTimestampEjj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.ROHC::DRTPProfile" = type { %"class.ROHC::DProfile.base", i32, i32, i32, i32, i8, %"struct.ROHC::udphdr", %"struct.ROHC::rtphdr", [4 x i8] }
%"class.ROHC::DProfile.base" = type <{ ptr, ptr, i16, [2 x i8], i32, i16, i16, i32, i32, i32, i64, i64, i8, [3 x i8], %"struct.ROHC::iphdr", i64, i32 }>
%"struct.ROHC::iphdr" = type { i8, i8, i16, i16, i16, i8, i8, i16, i32, i32 }
%"struct.ROHC::udphdr" = type { i16, i16, i16, i16 }
%"struct.ROHC::rtphdr" = type { i16, i16, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4ROHC10rohc_htonlEj(i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4ROHC11DRTPProfile15UpdateTimestampEjj(ptr noundef nonnull align 8 dereferenceable(132) %0, i32 noundef %1, i32 noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !9
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %12 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 3
  %13 = load i32, ptr %12, align 4, !tbaa !11
  store i32 %13, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = shl i32 1, %14
  %16 = sub nsw i32 %15, 1
  store i32 %16, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %17 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 3
  %18 = load i32, ptr %17, align 4, !tbaa !11
  %19 = load i32, ptr %8, align 4, !tbaa !9
  %20 = xor i32 %19, -1
  %21 = and i32 %18, %20
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = load i32, ptr %8, align 4, !tbaa !9
  %24 = and i32 %22, %23
  %25 = or i32 %21, %24
  store i32 %25, ptr %9, align 4, !tbaa !9
  %26 = load i32, ptr %9, align 4, !tbaa !9
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = icmp ult i32 %26, %27
  br i1 %28, label %29, label %34

29:                                               ; preds = %3
  %30 = load i32, ptr %6, align 4, !tbaa !9
  %31 = shl i32 1, %30
  %32 = load i32, ptr %9, align 4, !tbaa !9
  %33 = add i32 %32, %31
  store i32 %33, ptr %9, align 4, !tbaa !9
  br label %34

34:                                               ; preds = %29, %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %35 = load i32, ptr %9, align 4, !tbaa !9
  %36 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !23
  %38 = mul i32 %35, %37
  %39 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 4
  %40 = load i32, ptr %39, align 8, !tbaa !24
  %41 = add i32 %38, %40
  store i32 %41, ptr %10, align 4, !tbaa !9
  %42 = load i32, ptr %10, align 4, !tbaa !9
  %43 = call noundef i32 @_ZN4ROHC10rohc_htonlEj(i32 noundef %42)
  %44 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 7
  %45 = getelementptr inbounds %"struct.ROHC::rtphdr", ptr %44, i32 0, i32 2
  store i32 %43, ptr %45, align 4, !tbaa !25
  %46 = load i32, ptr %9, align 4, !tbaa !9
  %47 = getelementptr inbounds %"class.ROHC::DRTPProfile", ptr %11, i32 0, i32 3
  store i32 %46, ptr %47, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 100}
!12 = !{!"_ZTSN4ROHC11DRTPProfileE", !13, i64 0, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104, !18, i64 108, !21, i64 110, !22, i64 120}
!13 = !{!"_ZTSN4ROHC8DProfileE", !6, i64 8, !14, i64 16, !15, i64 20, !14, i64 24, !14, i64 26, !16, i64 28, !10, i64 32, !10, i64 36, !17, i64 40, !17, i64 48, !18, i64 56, !19, i64 60, !17, i64 80, !20, i64 88}
!14 = !{!"short", !7, i64 0}
!15 = !{!"_ZTSN4ROHC8DProfileUt_E", !7, i64 0}
!16 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !7, i64 0}
!17 = !{!"long", !7, i64 0}
!18 = !{!"bool", !7, i64 0}
!19 = !{!"_ZTSN4ROHC5iphdrE", !7, i64 0, !7, i64 0, !7, i64 1, !14, i64 2, !14, i64 4, !14, i64 6, !7, i64 8, !7, i64 9, !14, i64 10, !10, i64 12, !10, i64 16}
!20 = !{!"_ZTSN4ROHC12Reordering_tE", !7, i64 0}
!21 = !{!"_ZTSN4ROHC6udphdrE", !14, i64 0, !14, i64 2, !14, i64 4, !14, i64 6}
!22 = !{!"_ZTSN4ROHC6rtphdrE", !7, i64 0, !7, i64 0, !7, i64 0, !7, i64 0, !7, i64 1, !7, i64 1, !14, i64 2, !10, i64 4, !10, i64 8}
!23 = !{!12, !10, i64 92}
!24 = !{!12, !10, i64 104}
!25 = !{!12, !10, i64 124}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4ROHC10rohc_htonlEj(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4ROHC11DRTPProfile15UpdateTimestampEjj(ptr nocapture noundef nonnull align 8 dereferenceable(132) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 100
  %5 = load i32, ptr %4, align 4, !tbaa !5
  %6 = shl nuw i32 1, %2
  %7 = add nsw i32 %6, -1
  %8 = sub i32 0, %6
  %9 = and i32 %5, %8
  %10 = and i32 %7, %1
  %11 = or i32 %9, %10
  %12 = icmp ult i32 %11, %5
  %13 = select i1 %12, i32 %6, i32 0
  %spec.select = add i32 %13, %11
  %14 = getelementptr inbounds i8, ptr %0, i64 92
  %15 = load i32, ptr %14, align 4, !tbaa !21
  %16 = mul i32 %spec.select, %15
  %17 = getelementptr inbounds i8, ptr %0, i64 104
  %18 = load i32, ptr %17, align 8, !tbaa !22
  %19 = add i32 %16, %18
  %20 = tail call noundef i32 @_ZN4ROHC10rohc_htonlEj(i32 noundef %19)
  %21 = getelementptr inbounds i8, ptr %0, i64 124
  store i32 %20, ptr %21, align 4, !tbaa !23
  store i32 %spec.select, ptr %4, align 4, !tbaa !5
  ret void
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 100}
!6 = !{!"_ZTSN4ROHC11DRTPProfileE", !7, i64 0, !14, i64 92, !14, i64 96, !14, i64 100, !14, i64 104, !16, i64 108, !19, i64 110, !20, i64 120}
!7 = !{!"_ZTSN4ROHC8DProfileE", !8, i64 8, !11, i64 16, !12, i64 20, !11, i64 24, !11, i64 26, !13, i64 28, !14, i64 32, !14, i64 36, !15, i64 40, !15, i64 48, !16, i64 56, !17, i64 60, !15, i64 80, !18, i64 88}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"short", !9, i64 0}
!12 = !{!"_ZTSN4ROHC8DProfileUt_E", !9, i64 0}
!13 = !{!"_ZTSN4ROHC15IPIDBehaviour_tE", !9, i64 0}
!14 = !{!"int", !9, i64 0}
!15 = !{!"long", !9, i64 0}
!16 = !{!"bool", !9, i64 0}
!17 = !{!"_ZTSN4ROHC5iphdrE", !9, i64 0, !9, i64 0, !9, i64 1, !11, i64 2, !11, i64 4, !11, i64 6, !9, i64 8, !9, i64 9, !11, i64 10, !14, i64 12, !14, i64 16}
!18 = !{!"_ZTSN4ROHC12Reordering_tE", !9, i64 0}
!19 = !{!"_ZTSN4ROHC6udphdrE", !11, i64 0, !11, i64 2, !11, i64 4, !11, i64 6}
!20 = !{!"_ZTSN4ROHC6rtphdrE", !9, i64 0, !9, i64 0, !9, i64 0, !9, i64 0, !9, i64 1, !9, i64 1, !11, i64 2, !14, i64 4, !14, i64 8}
!21 = !{!6, !14, i64 92}
!22 = !{!6, !14, i64 104}
!23 = !{!6, !14, i64 124}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass