; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (ascii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @DigitToASCII(i8 noundef zeroext %0, i32 noundef %1) #1 {
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  store i8 %0, ptr %4, align 1, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !8
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !8
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  %9 = load i8, ptr %4, align 1, !tbaa !5
  %10 = zext i8 %9 to i32
  %11 = and i32 15, %10
  %12 = trunc i32 %11 to i8
  store i8 %12, ptr %7, align 1, !tbaa !5
  %13 = load i32, ptr %5, align 4, !tbaa !8
  %14 = icmp ne i32 %13, 10
  br i1 %14, label %15, label %19

15:                                               ; preds = %2
  %16 = load i32, ptr %5, align 4, !tbaa !8
  %17 = icmp ne i32 %16, 16
  br i1 %17, label %18, label %19

18:                                               ; preds = %15
  br label %48

19:                                               ; preds = %15, %2
  %20 = load i8, ptr %7, align 1, !tbaa !5
  %21 = zext i8 %20 to i32
  %22 = icmp sle i32 %21, 9
  br i1 %22, label %23, label %29

23:                                               ; preds = %19
  %24 = load i8, ptr %7, align 1, !tbaa !5
  %25 = zext i8 %24 to i32
  %26 = add nsw i32 %25, 48
  store i32 %26, ptr %6, align 4, !tbaa !8
  %27 = load i32, ptr %6, align 4, !tbaa !8
  %28 = trunc i32 %27 to i8
  store i8 %28, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %49

29:                                               ; preds = %19
  %30 = load i32, ptr %5, align 4, !tbaa !8
  %31 = icmp eq i32 %30, 16
  br i1 %31, label %32, label %46

32:                                               ; preds = %29
  %33 = load i8, ptr %7, align 1, !tbaa !5
  %34 = zext i8 %33 to i32
  %35 = icmp sge i32 %34, 10
  br i1 %35, label %36, label %46

36:                                               ; preds = %32
  %37 = load i8, ptr %7, align 1, !tbaa !5
  %38 = zext i8 %37 to i32
  %39 = icmp sle i32 %38, 15
  br i1 %39, label %40, label %46

40:                                               ; preds = %36
  %41 = load i8, ptr %7, align 1, !tbaa !5
  %42 = zext i8 %41 to i32
  %43 = add nsw i32 %42, 55
  store i32 %43, ptr %6, align 4, !tbaa !8
  %44 = load i32, ptr %6, align 4, !tbaa !8
  %45 = trunc i32 %44 to i8
  store i8 %45, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %49

46:                                               ; preds = %36, %32, %29
  br label %47

47:                                               ; preds = %46
  br label %48

48:                                               ; preds = %47, %18
  store i8 -1, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %49

49:                                               ; preds = %48, %40, %23
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %50 = load i8, ptr %3, align 1
  ret i8 %50
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local zeroext range(i8 -1, 71) i8 @DigitToASCII(i8 noundef zeroext %0, i32 noundef %1) local_unnamed_addr #0 {
  switch i32 %1, label %11 [
    i32 16, label %3
    i32 10, label %3
  ]

3:                                                ; preds = %2, %2
  %4 = and i8 %0, 15
  %5 = icmp ult i8 %4, 10
  br i1 %5, label %6, label %8

6:                                                ; preds = %3
  %7 = or disjoint i8 %4, 48
  br label %11

8:                                                ; preds = %3
  %9 = icmp eq i32 %1, 16
  %10 = add nuw nsw i8 %4, 55
  %spec.select = select i1 %9, i8 %10, i8 -1
  br label %11

11:                                               ; preds = %8, %2, %6
  %.0 = phi i8 [ %7, %6 ], [ -1, %2 ], [ %spec.select, %8 ]
  ret i8 %.0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass