; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_32BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_16BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_8BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_32BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_16BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_8BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_TransmitReceive_IT(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #2
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %14, i32 0, i32 0
  %16 = load ptr, ptr %15, align 8, !tbaa !13
  %17 = getelementptr inbounds %struct.SPI_TypeDef, ptr %16, i32 0, i32 8
  store ptr %17, ptr %12, align 8, !tbaa !5
  br label %18

18:                                               ; preds = %4
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %19, i32 0, i32 13
  %21 = load i32, ptr %20, align 8, !tbaa !16
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 2, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %273

24:                                               ; preds = %18
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %25, i32 0, i32 13
  store i32 1, ptr %26, align 8, !tbaa !16
  br label %27

27:                                               ; preds = %24
  br label %28

28:                                               ; preds = %27
  br label %29

29:                                               ; preds = %28
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %30, i32 0, i32 14
  %32 = load volatile i32, ptr %31, align 4, !tbaa !17
  %33 = icmp ne i32 %32, 1
  br i1 %33, label %34, label %41

34:                                               ; preds = %29
  store i32 2, ptr %10, align 4, !tbaa !11
  br label %35

35:                                               ; preds = %34
  %36 = load ptr, ptr %6, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %36, i32 0, i32 13
  store i32 0, ptr %37, align 8, !tbaa !16
  br label %38

38:                                               ; preds = %35
  br label %39

39:                                               ; preds = %38
  %40 = load i32, ptr %10, align 4, !tbaa !11
  store i32 %40, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %273

41:                                               ; preds = %29
  %42 = load ptr, ptr %7, align 8, !tbaa !5
  %43 = icmp eq ptr %42, null
  br i1 %43, label %51, label %44

44:                                               ; preds = %41
  %45 = load ptr, ptr %8, align 8, !tbaa !5
  %46 = icmp eq ptr %45, null
  br i1 %46, label %51, label %47

47:                                               ; preds = %44
  %48 = load i16, ptr %9, align 2, !tbaa !9
  %49 = zext i16 %48 to i64
  %50 = icmp eq i64 %49, 0
  br i1 %50, label %51, label %58

51:                                               ; preds = %47, %44, %41
  store i32 1, ptr %10, align 4, !tbaa !11
  br label %52

52:                                               ; preds = %51
  %53 = load ptr, ptr %6, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %53, i32 0, i32 13
  store i32 0, ptr %54, align 8, !tbaa !16
  br label %55

55:                                               ; preds = %52
  br label %56

56:                                               ; preds = %55
  %57 = load i32, ptr %10, align 4, !tbaa !11
  store i32 %57, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %273

58:                                               ; preds = %47
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %59, i32 0, i32 14
  store volatile i32 5, ptr %60, align 4, !tbaa !17
  %61 = load ptr, ptr %6, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %61, i32 0, i32 15
  store volatile i32 0, ptr %62, align 8, !tbaa !18
  %63 = load ptr, ptr %7, align 8, !tbaa !5
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %64, i32 0, i32 2
  store ptr %63, ptr %65, align 8, !tbaa !19
  %66 = load i16, ptr %9, align 2, !tbaa !9
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %67, i32 0, i32 3
  store i16 %66, ptr %68, align 8, !tbaa !20
  %69 = load i16, ptr %9, align 2, !tbaa !9
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %70, i32 0, i32 4
  store volatile i16 %69, ptr %71, align 2, !tbaa !21
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %73, i32 0, i32 5
  store ptr %72, ptr %74, align 8, !tbaa !22
  %75 = load i16, ptr %9, align 2, !tbaa !9
  %76 = load ptr, ptr %6, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %76, i32 0, i32 6
  store i16 %75, ptr %77, align 8, !tbaa !23
  %78 = load i16, ptr %9, align 2, !tbaa !9
  %79 = load ptr, ptr %6, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %79, i32 0, i32 7
  store volatile i16 %78, ptr %80, align 2, !tbaa !24
  %81 = load ptr, ptr %6, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %81, i32 0, i32 4
  %83 = load volatile i16, ptr %82, align 2, !tbaa !21
  %84 = zext i16 %83 to i32
  store i32 %84, ptr %11, align 4, !tbaa !11
  %85 = load ptr, ptr %6, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %85, i32 0, i32 1
  %87 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %86, i32 0, i32 2
  %88 = load i32, ptr %87, align 8, !tbaa !25
  %89 = zext i32 %88 to i64
  %90 = icmp ugt i64 %89, 15
  br i1 %90, label %91, label %96

91:                                               ; preds = %58
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %92, i32 0, i32 10
  store ptr @SPI_TxISR_32BIT, ptr %93, align 8, !tbaa !26
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %94, i32 0, i32 9
  store ptr @SPI_RxISR_32BIT, ptr %95, align 8, !tbaa !27
  br label %114

96:                                               ; preds = %58
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %97, i32 0, i32 1
  %99 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %98, i32 0, i32 2
  %100 = load i32, ptr %99, align 8, !tbaa !25
  %101 = zext i32 %100 to i64
  %102 = icmp ugt i64 %101, 7
  br i1 %102, label %103, label %108

103:                                              ; preds = %96
  %104 = load ptr, ptr %6, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %104, i32 0, i32 9
  store ptr @SPI_RxISR_16BIT, ptr %105, align 8, !tbaa !27
  %106 = load ptr, ptr %6, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %106, i32 0, i32 10
  store ptr @SPI_TxISR_16BIT, ptr %107, align 8, !tbaa !26
  br label %113

108:                                              ; preds = %96
  %109 = load ptr, ptr %6, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %109, i32 0, i32 9
  store ptr @SPI_RxISR_8BIT, ptr %110, align 8, !tbaa !27
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %111, i32 0, i32 10
  store ptr @SPI_TxISR_8BIT, ptr %112, align 8, !tbaa !26
  br label %113

113:                                              ; preds = %108, %103
  br label %114

114:                                              ; preds = %113, %91
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !13
  %118 = getelementptr inbounds %struct.SPI_TypeDef, ptr %117, i32 0, i32 3
  %119 = load volatile i32, ptr %118, align 4, !tbaa !28
  %120 = zext i32 %119 to i64
  %121 = and i64 %120, -393217
  %122 = or i64 %121, 0
  %123 = trunc i64 %122 to i32
  %124 = load ptr, ptr %6, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !13
  %127 = getelementptr inbounds %struct.SPI_TypeDef, ptr %126, i32 0, i32 3
  store volatile i32 %123, ptr %127, align 4, !tbaa !28
  %128 = load ptr, ptr %6, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %128, i32 0, i32 0
  %130 = load ptr, ptr %129, align 8, !tbaa !13
  %131 = getelementptr inbounds %struct.SPI_TypeDef, ptr %130, i32 0, i32 1
  %132 = load volatile i32, ptr %131, align 4, !tbaa !30
  %133 = zext i32 %132 to i64
  %134 = and i64 %133, -65536
  %135 = load i16, ptr %9, align 2, !tbaa !9
  %136 = zext i16 %135 to i64
  %137 = or i64 %134, %136
  %138 = trunc i64 %137 to i32
  %139 = load ptr, ptr %6, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %139, i32 0, i32 0
  %141 = load ptr, ptr %140, align 8, !tbaa !13
  %142 = getelementptr inbounds %struct.SPI_TypeDef, ptr %141, i32 0, i32 1
  store volatile i32 %138, ptr %142, align 4, !tbaa !30
  %143 = load ptr, ptr %6, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %143, i32 0, i32 0
  %145 = load ptr, ptr %144, align 8, !tbaa !13
  %146 = getelementptr inbounds %struct.SPI_TypeDef, ptr %145, i32 0, i32 0
  %147 = load volatile i32, ptr %146, align 4, !tbaa !31
  %148 = zext i32 %147 to i64
  %149 = or i64 %148, 1
  %150 = trunc i64 %149 to i32
  store volatile i32 %150, ptr %146, align 4, !tbaa !31
  br label %151

151:                                              ; preds = %241, %114
  %152 = load ptr, ptr %6, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !13
  %155 = getelementptr inbounds %struct.SPI_TypeDef, ptr %154, i32 0, i32 5
  %156 = load volatile i32, ptr %155, align 4, !tbaa !32
  %157 = zext i32 %156 to i64
  %158 = and i64 %157, 2
  %159 = icmp eq i64 %158, 2
  br i1 %159, label %160, label %164

160:                                              ; preds = %151
  %161 = load i32, ptr %11, align 4, !tbaa !11
  %162 = zext i32 %161 to i64
  %163 = icmp ne i64 %162, 0
  br label %164

164:                                              ; preds = %160, %151
  %165 = phi i1 [ false, %151 ], [ %163, %160 ]
  br i1 %165, label %166, label %242

166:                                              ; preds = %164
  %167 = load ptr, ptr %6, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %167, i32 0, i32 1
  %169 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %168, i32 0, i32 2
  %170 = load i32, ptr %169, align 8, !tbaa !25
  %171 = zext i32 %170 to i64
  %172 = icmp ugt i64 %171, 15
  br i1 %172, label %173, label %194

173:                                              ; preds = %166
  %174 = load ptr, ptr %6, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %174, i32 0, i32 2
  %176 = load ptr, ptr %175, align 8, !tbaa !19
  %177 = load i32, ptr %176, align 4, !tbaa !11
  %178 = load ptr, ptr %6, align 8, !tbaa !5
  %179 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %178, i32 0, i32 0
  %180 = load ptr, ptr %179, align 8, !tbaa !13
  %181 = getelementptr inbounds %struct.SPI_TypeDef, ptr %180, i32 0, i32 8
  store volatile i32 %177, ptr %181, align 4, !tbaa !11
  %182 = load ptr, ptr %6, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %182, i32 0, i32 2
  %184 = load ptr, ptr %183, align 8, !tbaa !19
  %185 = getelementptr inbounds i8, ptr %184, i64 4
  store ptr %185, ptr %183, align 8, !tbaa !19
  %186 = load ptr, ptr %6, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %186, i32 0, i32 4
  %188 = load volatile i16, ptr %187, align 2, !tbaa !21
  %189 = add i16 %188, -1
  store volatile i16 %189, ptr %187, align 2, !tbaa !21
  %190 = load ptr, ptr %6, align 8, !tbaa !5
  %191 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %190, i32 0, i32 4
  %192 = load volatile i16, ptr %191, align 2, !tbaa !21
  %193 = zext i16 %192 to i32
  store i32 %193, ptr %11, align 4, !tbaa !11
  br label %241

194:                                              ; preds = %166
  %195 = load ptr, ptr %6, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %195, i32 0, i32 1
  %197 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %196, i32 0, i32 2
  %198 = load i32, ptr %197, align 8, !tbaa !25
  %199 = zext i32 %198 to i64
  %200 = icmp ugt i64 %199, 7
  br i1 %200, label %201, label %219

201:                                              ; preds = %194
  %202 = load ptr, ptr %6, align 8, !tbaa !5
  %203 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %202, i32 0, i32 2
  %204 = load ptr, ptr %203, align 8, !tbaa !19
  %205 = load i16, ptr %204, align 2, !tbaa !9
  %206 = load ptr, ptr %12, align 8, !tbaa !5
  store volatile i16 %205, ptr %206, align 2, !tbaa !9
  %207 = load ptr, ptr %6, align 8, !tbaa !5
  %208 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %207, i32 0, i32 2
  %209 = load ptr, ptr %208, align 8, !tbaa !19
  %210 = getelementptr inbounds i8, ptr %209, i64 2
  store ptr %210, ptr %208, align 8, !tbaa !19
  %211 = load ptr, ptr %6, align 8, !tbaa !5
  %212 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %211, i32 0, i32 4
  %213 = load volatile i16, ptr %212, align 2, !tbaa !21
  %214 = add i16 %213, -1
  store volatile i16 %214, ptr %212, align 2, !tbaa !21
  %215 = load ptr, ptr %6, align 8, !tbaa !5
  %216 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %215, i32 0, i32 4
  %217 = load volatile i16, ptr %216, align 2, !tbaa !21
  %218 = zext i16 %217 to i32
  store i32 %218, ptr %11, align 4, !tbaa !11
  br label %240

219:                                              ; preds = %194
  %220 = load ptr, ptr %6, align 8, !tbaa !5
  %221 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %220, i32 0, i32 2
  %222 = load ptr, ptr %221, align 8, !tbaa !19
  %223 = load i8, ptr %222, align 1, !tbaa !33
  %224 = load ptr, ptr %6, align 8, !tbaa !5
  %225 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %224, i32 0, i32 0
  %226 = load ptr, ptr %225, align 8, !tbaa !13
  %227 = getelementptr inbounds %struct.SPI_TypeDef, ptr %226, i32 0, i32 8
  store volatile i8 %223, ptr %227, align 4, !tbaa !33
  %228 = load ptr, ptr %6, align 8, !tbaa !5
  %229 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %228, i32 0, i32 2
  %230 = load ptr, ptr %229, align 8, !tbaa !19
  %231 = getelementptr inbounds i8, ptr %230, i64 1
  store ptr %231, ptr %229, align 8, !tbaa !19
  %232 = load ptr, ptr %6, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %232, i32 0, i32 4
  %234 = load volatile i16, ptr %233, align 2, !tbaa !21
  %235 = add i16 %234, -1
  store volatile i16 %235, ptr %233, align 2, !tbaa !21
  %236 = load ptr, ptr %6, align 8, !tbaa !5
  %237 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %236, i32 0, i32 4
  %238 = load volatile i16, ptr %237, align 2, !tbaa !21
  %239 = zext i16 %238 to i32
  store i32 %239, ptr %11, align 4, !tbaa !11
  br label %240

240:                                              ; preds = %219, %201
  br label %241

241:                                              ; preds = %240, %173
  br label %151, !llvm.loop !34

242:                                              ; preds = %164
  %243 = load ptr, ptr %6, align 8, !tbaa !5
  %244 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %243, i32 0, i32 0
  %245 = load ptr, ptr %244, align 8, !tbaa !13
  %246 = getelementptr inbounds %struct.SPI_TypeDef, ptr %245, i32 0, i32 4
  %247 = load volatile i32, ptr %246, align 4, !tbaa !36
  %248 = zext i32 %247 to i64
  %249 = or i64 %248, 1900
  %250 = trunc i64 %249 to i32
  store volatile i32 %250, ptr %246, align 4, !tbaa !36
  %251 = load ptr, ptr %6, align 8, !tbaa !5
  %252 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %251, i32 0, i32 1
  %253 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %252, i32 0, i32 0
  %254 = load i32, ptr %253, align 8, !tbaa !37
  %255 = zext i32 %254 to i64
  %256 = icmp eq i64 %255, 4194304
  br i1 %256, label %257, label %266

257:                                              ; preds = %242
  %258 = load ptr, ptr %6, align 8, !tbaa !5
  %259 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %258, i32 0, i32 0
  %260 = load ptr, ptr %259, align 8, !tbaa !13
  %261 = getelementptr inbounds %struct.SPI_TypeDef, ptr %260, i32 0, i32 0
  %262 = load volatile i32, ptr %261, align 4, !tbaa !31
  %263 = zext i32 %262 to i64
  %264 = or i64 %263, 512
  %265 = trunc i64 %264 to i32
  store volatile i32 %265, ptr %261, align 4, !tbaa !31
  br label %266

266:                                              ; preds = %257, %242
  br label %267

267:                                              ; preds = %266
  %268 = load ptr, ptr %6, align 8, !tbaa !5
  %269 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %268, i32 0, i32 13
  store i32 0, ptr %269, align 8, !tbaa !16
  br label %270

270:                                              ; preds = %267
  br label %271

271:                                              ; preds = %270
  %272 = load i32, ptr %10, align 4, !tbaa !11
  store i32 %272, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %273

273:                                              ; preds = %271, %56, %39, %23
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %274 = load i32, ptr %5, align 4
  ret i32 %274
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 0}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 160}
!17 = !{!14, !12, i64 164}
!18 = !{!14, !12, i64 168}
!19 = !{!14, !6, i64 96}
!20 = !{!14, !10, i64 104}
!21 = !{!14, !10, i64 106}
!22 = !{!14, !6, i64 112}
!23 = !{!14, !10, i64 120}
!24 = !{!14, !10, i64 122}
!25 = !{!14, !12, i64 16}
!26 = !{!14, !6, i64 136}
!27 = !{!14, !6, i64 128}
!28 = !{!29, !12, i64 12}
!29 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!30 = !{!29, !12, i64 4}
!31 = !{!29, !12, i64 0}
!32 = !{!29, !12, i64 20}
!33 = !{!7, !7, i64 0}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}
!36 = !{!29, !12, i64 16}
!37 = !{!14, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_32BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_16BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_TxISR_8BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_32BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_16BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_8BIT(ptr noundef) #0

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SPI_TransmitReceive_IT(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3) local_unnamed_addr #1 {
  %5 = load ptr, ptr %0, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %5, i64 32
  %7 = getelementptr inbounds i8, ptr %0, i64 160
  %8 = load i32, ptr %7, align 8, !tbaa !13
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %97, label %10

10:                                               ; preds = %4
  store i32 1, ptr %7, align 8, !tbaa !13
  %11 = getelementptr inbounds i8, ptr %0, i64 164
  %12 = load volatile i32, ptr %11, align 4, !tbaa !14
  %.not = icmp eq i32 %12, 1
  br i1 %.not, label %13, label %.sink.split

13:                                               ; preds = %10
  %14 = icmp eq ptr %1, null
  %15 = icmp eq ptr %2, null
  %or.cond = or i1 %14, %15
  %16 = icmp eq i16 %3, 0
  %or.cond4 = or i1 %or.cond, %16
  br i1 %or.cond4, label %.sink.split, label %17

17:                                               ; preds = %13
  store volatile i32 5, ptr %11, align 4, !tbaa !14
  %18 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %18, align 8, !tbaa !15
  %19 = getelementptr inbounds i8, ptr %0, i64 96
  store ptr %1, ptr %19, align 8, !tbaa !16
  %20 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 %3, ptr %20, align 8, !tbaa !17
  %21 = getelementptr inbounds i8, ptr %0, i64 106
  store volatile i16 %3, ptr %21, align 2, !tbaa !18
  %22 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr %2, ptr %22, align 8, !tbaa !19
  %23 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 %3, ptr %23, align 8, !tbaa !20
  %24 = getelementptr inbounds i8, ptr %0, i64 122
  store volatile i16 %3, ptr %24, align 2, !tbaa !21
  %25 = load volatile i16, ptr %21, align 2, !tbaa !18
  %26 = getelementptr inbounds i8, ptr %0, i64 8
  %27 = getelementptr inbounds i8, ptr %0, i64 16
  %28 = load i32, ptr %27, align 8, !tbaa !22
  %29 = icmp ugt i32 %28, 15
  br i1 %29, label %30, label %33

30:                                               ; preds = %17
  %31 = getelementptr inbounds i8, ptr %0, i64 136
  store ptr @SPI_TxISR_32BIT, ptr %31, align 8, !tbaa !23
  %32 = getelementptr inbounds i8, ptr %0, i64 128
  store ptr @SPI_RxISR_32BIT, ptr %32, align 8, !tbaa !24
  br label %39

33:                                               ; preds = %17
  %34 = icmp ugt i32 %28, 7
  %35 = getelementptr inbounds i8, ptr %0, i64 128
  %36 = getelementptr inbounds i8, ptr %0, i64 136
  br i1 %34, label %37, label %38

37:                                               ; preds = %33
  store ptr @SPI_RxISR_16BIT, ptr %35, align 8, !tbaa !24
  store ptr @SPI_TxISR_16BIT, ptr %36, align 8, !tbaa !23
  br label %39

38:                                               ; preds = %33
  store ptr @SPI_RxISR_8BIT, ptr %35, align 8, !tbaa !24
  store ptr @SPI_TxISR_8BIT, ptr %36, align 8, !tbaa !23
  br label %39

39:                                               ; preds = %37, %38, %30
  %40 = getelementptr inbounds i8, ptr %5, i64 12
  %41 = load volatile i32, ptr %40, align 4, !tbaa !25
  %42 = and i32 %41, -393217
  store volatile i32 %42, ptr %40, align 4, !tbaa !25
  %43 = getelementptr inbounds i8, ptr %5, i64 4
  %44 = load volatile i32, ptr %43, align 4, !tbaa !27
  %45 = and i32 %44, -65536
  %46 = zext i16 %3 to i32
  %47 = or disjoint i32 %45, %46
  store volatile i32 %47, ptr %43, align 4, !tbaa !27
  %48 = load volatile i32, ptr %5, align 4, !tbaa !28
  %49 = or i32 %48, 1
  store volatile i32 %49, ptr %5, align 4, !tbaa !28
  %50 = getelementptr inbounds i8, ptr %5, i64 20
  %51 = load volatile i32, ptr %50, align 4, !tbaa !29
  %52 = and i32 %51, 2
  %53 = icmp ne i32 %52, 0
  %54 = icmp ne i16 %25, 0
  %55 = select i1 %53, i1 %54, i1 false
  br i1 %55, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %39, %80
  %56 = phi ptr [ %81, %80 ], [ %5, %39 ]
  %57 = phi ptr [ %82, %80 ], [ %1, %39 ]
  %58 = load i32, ptr %27, align 8, !tbaa !22
  %59 = icmp ugt i32 %58, 15
  br i1 %59, label %60, label %66

60:                                               ; preds = %.lr.ph
  %61 = load i32, ptr %57, align 4, !tbaa !30
  %62 = getelementptr inbounds i8, ptr %56, i64 32
  store volatile i32 %61, ptr %62, align 4, !tbaa !30
  %63 = getelementptr inbounds i8, ptr %57, i64 4
  store ptr %63, ptr %19, align 8, !tbaa !16
  %64 = load volatile i16, ptr %21, align 2, !tbaa !18
  %65 = add i16 %64, -1
  store volatile i16 %65, ptr %21, align 2, !tbaa !18
  br label %80

66:                                               ; preds = %.lr.ph
  %67 = icmp ugt i32 %58, 7
  br i1 %67, label %68, label %73

68:                                               ; preds = %66
  %69 = load i16, ptr %57, align 2, !tbaa !31
  store volatile i16 %69, ptr %6, align 2, !tbaa !31
  %70 = getelementptr inbounds i8, ptr %57, i64 2
  store ptr %70, ptr %19, align 8, !tbaa !16
  %71 = load volatile i16, ptr %21, align 2, !tbaa !18
  %72 = add i16 %71, -1
  store volatile i16 %72, ptr %21, align 2, !tbaa !18
  br label %80

73:                                               ; preds = %66
  %74 = load i8, ptr %57, align 1, !tbaa !32
  %75 = getelementptr inbounds i8, ptr %56, i64 32
  store volatile i8 %74, ptr %75, align 4, !tbaa !32
  %76 = load ptr, ptr %19, align 8, !tbaa !16
  %77 = getelementptr inbounds i8, ptr %76, i64 1
  store ptr %77, ptr %19, align 8, !tbaa !16
  %78 = load volatile i16, ptr %21, align 2, !tbaa !18
  %79 = add i16 %78, -1
  store volatile i16 %79, ptr %21, align 2, !tbaa !18
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  br label %80

80:                                               ; preds = %68, %73, %60
  %81 = phi ptr [ %56, %68 ], [ %.pre, %73 ], [ %56, %60 ]
  %82 = phi ptr [ %70, %68 ], [ %77, %73 ], [ %63, %60 ]
  %.1.in = load volatile i16, ptr %21, align 2, !tbaa !18
  %83 = getelementptr inbounds i8, ptr %81, i64 20
  %84 = load volatile i32, ptr %83, align 4, !tbaa !29
  %85 = and i32 %84, 2
  %86 = icmp ne i32 %85, 0
  %87 = icmp ne i16 %.1.in, 0
  %88 = select i1 %86, i1 %87, i1 false
  br i1 %88, label %.lr.ph, label %._crit_edge, !llvm.loop !33

._crit_edge:                                      ; preds = %80, %39
  %.lcssa = phi ptr [ %5, %39 ], [ %81, %80 ]
  %89 = getelementptr inbounds i8, ptr %.lcssa, i64 16
  %90 = load volatile i32, ptr %89, align 4, !tbaa !35
  %91 = or i32 %90, 1900
  store volatile i32 %91, ptr %89, align 4, !tbaa !35
  %92 = load i32, ptr %26, align 8, !tbaa !36
  %93 = icmp eq i32 %92, 4194304
  br i1 %93, label %94, label %.sink.split

94:                                               ; preds = %._crit_edge
  %95 = load volatile i32, ptr %.lcssa, align 4, !tbaa !28
  %96 = or i32 %95, 512
  store volatile i32 %96, ptr %.lcssa, align 4, !tbaa !28
  br label %.sink.split

.sink.split:                                      ; preds = %94, %._crit_edge, %13, %10
  %.0.ph = phi i32 [ 2, %10 ], [ 1, %13 ], [ 0, %._crit_edge ], [ 0, %94 ]
  store i32 0, ptr %7, align 8, !tbaa !13
  br label %97

97:                                               ; preds = %.sink.split, %4
  %.0 = phi i32 [ 2, %4 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 160}
!14 = !{!6, !11, i64 164}
!15 = !{!6, !11, i64 168}
!16 = !{!6, !7, i64 96}
!17 = !{!6, !12, i64 104}
!18 = !{!6, !12, i64 106}
!19 = !{!6, !7, i64 112}
!20 = !{!6, !12, i64 120}
!21 = !{!6, !12, i64 122}
!22 = !{!6, !11, i64 16}
!23 = !{!6, !7, i64 136}
!24 = !{!6, !7, i64 128}
!25 = !{!26, !11, i64 12}
!26 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!27 = !{!26, !11, i64 4}
!28 = !{!26, !11, i64 0}
!29 = !{!26, !11, i64 20}
!30 = !{!11, !11, i64 0}
!31 = !{!12, !12, i64 0}
!32 = !{!8, !8, i64 0}
!33 = distinct !{!33, !34}
!34 = !{!"llvm.loop.mustprogress"}
!35 = !{!26, !11, i64 16}
!36 = !{!6, !11, i64 8}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass