; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_HallSensor_Start(ptr noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %10, i32 0, i32 6
  %12 = getelementptr inbounds [6 x i32], ptr %11, i64 0, i64 0
  %13 = load volatile i32, ptr %12, align 8, !tbaa !9
  store i32 %13, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %14, i32 0, i32 6
  %16 = getelementptr inbounds [6 x i32], ptr %15, i64 0, i64 1
  %17 = load volatile i32, ptr %16, align 4, !tbaa !9
  store i32 %17, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %18 = load ptr, ptr %3, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %18, i32 0, i32 7
  %20 = getelementptr inbounds [4 x i32], ptr %19, i64 0, i64 0
  %21 = load volatile i32, ptr %20, align 8, !tbaa !9
  store i32 %21, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %22, i32 0, i32 7
  %24 = getelementptr inbounds [4 x i32], ptr %23, i64 0, i64 1
  %25 = load volatile i32, ptr %24, align 4, !tbaa !9
  store i32 %25, ptr %8, align 4, !tbaa !9
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = icmp ne i32 %26, 1
  br i1 %27, label %37, label %28

28:                                               ; preds = %1
  %29 = load i32, ptr %6, align 4, !tbaa !9
  %30 = icmp ne i32 %29, 1
  br i1 %30, label %37, label %31

31:                                               ; preds = %28
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = icmp ne i32 %32, 1
  br i1 %33, label %37, label %34

34:                                               ; preds = %31
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = icmp ne i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %34, %31, %28, %1
  store i32 1, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %139

38:                                               ; preds = %34
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %39, i32 0, i32 6
  %41 = getelementptr inbounds [6 x i32], ptr %40, i64 0, i64 0
  store volatile i32 2, ptr %41, align 8, !tbaa !9
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %42, i32 0, i32 6
  %44 = getelementptr inbounds [6 x i32], ptr %43, i64 0, i64 1
  store volatile i32 2, ptr %44, align 4, !tbaa !9
  %45 = load ptr, ptr %3, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %45, i32 0, i32 7
  %47 = getelementptr inbounds [4 x i32], ptr %46, i64 0, i64 0
  store volatile i32 2, ptr %47, align 8, !tbaa !9
  %48 = load ptr, ptr %3, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %48, i32 0, i32 7
  %50 = getelementptr inbounds [4 x i32], ptr %49, i64 0, i64 1
  store volatile i32 2, ptr %50, align 4, !tbaa !9
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %51, i32 0, i32 0
  %53 = load ptr, ptr %52, align 8, !tbaa !11
  call void @TIM_CCxChannelCmd(ptr noundef %53, i32 noundef 0, i32 noundef 1)
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !11
  %57 = icmp eq ptr %56, inttoptr (i64 1073807360 to ptr)
  br i1 %57, label %103, label %58

58:                                               ; preds = %38
  %59 = load ptr, ptr %3, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !11
  %62 = icmp eq ptr %61, inttoptr (i64 1073741824 to ptr)
  br i1 %62, label %103, label %63

63:                                               ; preds = %58
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %64, i32 0, i32 0
  %66 = load ptr, ptr %65, align 8, !tbaa !11
  %67 = icmp eq ptr %66, inttoptr (i64 1073742848 to ptr)
  br i1 %67, label %103, label %68

68:                                               ; preds = %63
  %69 = load ptr, ptr %3, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %69, i32 0, i32 0
  %71 = load ptr, ptr %70, align 8, !tbaa !11
  %72 = icmp eq ptr %71, inttoptr (i64 1073743872 to ptr)
  br i1 %72, label %103, label %73

73:                                               ; preds = %68
  %74 = load ptr, ptr %3, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %74, i32 0, i32 0
  %76 = load ptr, ptr %75, align 8, !tbaa !11
  %77 = icmp eq ptr %76, inttoptr (i64 1073744896 to ptr)
  br i1 %77, label %103, label %78

78:                                               ; preds = %73
  %79 = load ptr, ptr %3, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %79, i32 0, i32 0
  %81 = load ptr, ptr %80, align 8, !tbaa !11
  %82 = icmp eq ptr %81, inttoptr (i64 1073808384 to ptr)
  br i1 %82, label %103, label %83

83:                                               ; preds = %78
  %84 = load ptr, ptr %3, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %84, i32 0, i32 0
  %86 = load ptr, ptr %85, align 8, !tbaa !11
  %87 = icmp eq ptr %86, inttoptr (i64 1073747968 to ptr)
  br i1 %87, label %103, label %88

88:                                               ; preds = %83
  %89 = load ptr, ptr %3, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %89, i32 0, i32 0
  %91 = load ptr, ptr %90, align 8, !tbaa !11
  %92 = icmp eq ptr %91, inttoptr (i64 1073823744 to ptr)
  br i1 %92, label %103, label %93

93:                                               ; preds = %88
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !11
  %97 = icmp eq ptr %96, inttoptr (i64 1073799168 to ptr)
  br i1 %97, label %103, label %98

98:                                               ; preds = %93
  %99 = load ptr, ptr %3, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %99, i32 0, i32 0
  %101 = load ptr, ptr %100, align 8, !tbaa !11
  %102 = icmp eq ptr %101, inttoptr (i64 1073800192 to ptr)
  br i1 %102, label %103, label %129

103:                                              ; preds = %98, %93, %88, %83, %78, %73, %68, %63, %58, %38
  %104 = load ptr, ptr %3, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %104, i32 0, i32 0
  %106 = load ptr, ptr %105, align 8, !tbaa !11
  %107 = getelementptr inbounds %struct.TIM_TypeDef, ptr %106, i32 0, i32 2
  %108 = load volatile i32, ptr %107, align 4, !tbaa !14
  %109 = zext i32 %108 to i64
  %110 = and i64 %109, 65543
  %111 = trunc i64 %110 to i32
  store i32 %111, ptr %4, align 4, !tbaa !9
  %112 = load i32, ptr %4, align 4, !tbaa !9
  %113 = zext i32 %112 to i64
  %114 = icmp eq i64 %113, 6
  br i1 %114, label %128, label %115

115:                                              ; preds = %103
  %116 = load i32, ptr %4, align 4, !tbaa !9
  %117 = zext i32 %116 to i64
  %118 = icmp eq i64 %117, 65536
  br i1 %118, label %128, label %119

119:                                              ; preds = %115
  %120 = load ptr, ptr %3, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %120, i32 0, i32 0
  %122 = load ptr, ptr %121, align 8, !tbaa !11
  %123 = getelementptr inbounds %struct.TIM_TypeDef, ptr %122, i32 0, i32 0
  %124 = load volatile i32, ptr %123, align 4, !tbaa !16
  %125 = zext i32 %124 to i64
  %126 = or i64 %125, 1
  %127 = trunc i64 %126 to i32
  store volatile i32 %127, ptr %123, align 4, !tbaa !16
  br label %128

128:                                              ; preds = %119, %115, %103
  br label %138

129:                                              ; preds = %98
  %130 = load ptr, ptr %3, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %130, i32 0, i32 0
  %132 = load ptr, ptr %131, align 8, !tbaa !11
  %133 = getelementptr inbounds %struct.TIM_TypeDef, ptr %132, i32 0, i32 0
  %134 = load volatile i32, ptr %133, align 4, !tbaa !16
  %135 = zext i32 %134 to i64
  %136 = or i64 %135, 1
  %137 = trunc i64 %136 to i32
  store volatile i32 %137, ptr %133, align 4, !tbaa !16
  br label %138

138:                                              ; preds = %129, %128
  store i32 0, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %139

139:                                              ; preds = %138, %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %140 = load i32, ptr %2, align 4
  ret i32 %140
}

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 8}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_TIMEx_HallSensor_Start(ptr noundef %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 104
  %3 = load volatile i32, ptr %2, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 108
  %5 = load volatile i32, ptr %4, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 128
  %7 = load volatile i32, ptr %6, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 132
  %9 = load volatile i32, ptr %8, align 4, !tbaa !5
  %10 = icmp ne i32 %3, 1
  %11 = icmp ne i32 %5, 1
  %or.cond = select i1 %10, i1 true, i1 %11
  %12 = icmp ne i32 %7, 1
  %or.cond3 = select i1 %or.cond, i1 true, i1 %12
  %13 = icmp ne i32 %9, 1
  %or.cond5 = select i1 %or.cond3, i1 true, i1 %13
  br i1 %or.cond5, label %23, label %14

14:                                               ; preds = %1
  store volatile i32 2, ptr %2, align 8, !tbaa !5
  store volatile i32 2, ptr %4, align 4, !tbaa !5
  store volatile i32 2, ptr %6, align 8, !tbaa !5
  store volatile i32 2, ptr %8, align 4, !tbaa !5
  %15 = load ptr, ptr %0, align 8, !tbaa !9
  tail call void @TIM_CCxChannelCmd(ptr noundef %15, i32 noundef 0, i32 noundef 1) #2
  %16 = load ptr, ptr %0, align 8, !tbaa !9
  %magicptr = ptrtoint ptr %16 to i64
  switch i64 %magicptr, label %.sink.split [
    i64 1073807360, label %17
    i64 1073741824, label %17
    i64 1073742848, label %17
    i64 1073743872, label %17
    i64 1073744896, label %17
    i64 1073808384, label %17
    i64 1073747968, label %17
    i64 1073823744, label %17
    i64 1073799168, label %17
    i64 1073800192, label %17
  ]

17:                                               ; preds = %14, %14, %14, %14, %14, %14, %14, %14, %14, %14
  %18 = getelementptr inbounds i8, ptr %16, i64 8
  %19 = load volatile i32, ptr %18, align 4, !tbaa !13
  %20 = and i32 %19, 65543
  switch i32 %20, label %.sink.split [
    i32 65536, label %23
    i32 6, label %23
  ]

.sink.split:                                      ; preds = %14, %17
  %21 = load volatile i32, ptr %16, align 4, !tbaa !15
  %22 = or i32 %21, 1
  store volatile i32 %22, ptr %16, align 4, !tbaa !15
  br label %23

23:                                               ; preds = %.sink.split, %17, %17, %1
  %.0 = phi i32 [ 1, %1 ], [ 0, %17 ], [ 0, %17 ], [ 0, %.sink.split ]
  ret i32 %.0
}

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !12, i64 8, !6, i64 32, !7, i64 40, !6, i64 96, !6, i64 100, !7, i64 104, !7, i64 128, !6, i64 144}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92, !6, i64 96, !6, i64 100, !6, i64 104}
!15 = !{!14, !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass