; LLVM IR from Mithreindeir/VelocityRaptor :: VelocityRaptor/src (vrCollision)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.vrVec2 = type { float, float }

@.str = external hidden unnamed_addr constant [36 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare <2 x float> @vrSub(<2 x float>, <2 x float>) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare float @vrDot(<2 x float>, <2 x float>) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @Clip(<2 x float> %0, <2 x float> %1, <2 x float> %2, float noundef %3, ptr noundef %4) #3 {
  %6 = alloca %struct.vrVec2, align 4
  %7 = alloca %struct.vrVec2, align 4
  %8 = alloca %struct.vrVec2, align 4
  %9 = alloca float, align 4
  %10 = alloca ptr, align 8
  %11 = alloca float, align 4
  %12 = alloca float, align 4
  %13 = alloca i32, align 4
  %14 = alloca float, align 4
  %15 = alloca %struct.vrVec2, align 4
  %16 = alloca %struct.vrVec2, align 4
  %17 = alloca %struct.vrVec2, align 4
  store <2 x float> %0, ptr %6, align 4
  store <2 x float> %1, ptr %7, align 4
  store <2 x float> %2, ptr %8, align 4
  store float %3, ptr %9, align 4, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  %18 = load <2 x float>, ptr %8, align 4
  %19 = load <2 x float>, ptr %6, align 4
  %20 = call float @vrDot(<2 x float> %18, <2 x float> %19)
  %21 = load float, ptr %9, align 4, !tbaa !5
  %22 = fsub float %20, %21
  store float %22, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  %23 = load <2 x float>, ptr %8, align 4
  %24 = load <2 x float>, ptr %7, align 4
  %25 = call float @vrDot(<2 x float> %23, <2 x float> %24)
  %26 = load float, ptr %9, align 4, !tbaa !5
  %27 = fsub float %25, %26
  store float %27, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  store i32 0, ptr %13, align 4, !tbaa !11
  %28 = load float, ptr %11, align 4, !tbaa !5
  %29 = fpext float %28 to double
  %30 = fcmp oge double %29, 0.000000e+00
  br i1 %30, label %31, label %38

31:                                               ; preds = %5
  %32 = load ptr, ptr %10, align 8, !tbaa !9
  %33 = load i32, ptr %13, align 4, !tbaa !11
  %34 = sext i32 %33 to i64
  %35 = getelementptr inbounds %struct.vrVec2, ptr %32, i64 %34
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %35, ptr align 4 %6, i64 8, i1 false), !tbaa.struct !13
  %36 = load i32, ptr %13, align 4, !tbaa !11
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %13, align 4, !tbaa !11
  br label %38

38:                                               ; preds = %31, %5
  %39 = load float, ptr %12, align 4, !tbaa !5
  %40 = fpext float %39 to double
  %41 = fcmp oge double %40, 0.000000e+00
  br i1 %41, label %42, label %49

42:                                               ; preds = %38
  %43 = load ptr, ptr %10, align 8, !tbaa !9
  %44 = load i32, ptr %13, align 4, !tbaa !11
  %45 = sext i32 %44 to i64
  %46 = getelementptr inbounds %struct.vrVec2, ptr %43, i64 %45
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %46, ptr align 4 %7, i64 8, i1 false), !tbaa.struct !13
  %47 = load i32, ptr %13, align 4, !tbaa !11
  %48 = add nsw i32 %47, 1
  store i32 %48, ptr %13, align 4, !tbaa !11
  br label %49

49:                                               ; preds = %42, %38
  %50 = load float, ptr %11, align 4, !tbaa !5
  %51 = load float, ptr %12, align 4, !tbaa !5
  %52 = fmul float %50, %51
  %53 = fpext float %52 to double
  %54 = fcmp olt double %53, 0.000000e+00
  br i1 %54, label %55, label %79

55:                                               ; preds = %49
  %56 = load i32, ptr %13, align 4, !tbaa !11
  %57 = icmp slt i32 %56, 2
  br i1 %57, label %58, label %79

58:                                               ; preds = %55
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #5
  %59 = load float, ptr %11, align 4, !tbaa !5
  %60 = load float, ptr %11, align 4, !tbaa !5
  %61 = load float, ptr %12, align 4, !tbaa !5
  %62 = fsub float %60, %61
  %63 = fdiv float %59, %62
  store float %63, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #5
  %64 = load <2 x float>, ptr %7, align 4
  %65 = load <2 x float>, ptr %6, align 4
  %66 = call <2 x float> @vrSub(<2 x float> %64, <2 x float> %65)
  store <2 x float> %66, ptr %17, align 4
  %67 = load float, ptr %14, align 4, !tbaa !5
  %68 = load <2 x float>, ptr %17, align 4
  %69 = call <2 x float> @vrScale(<2 x float> %68, float noundef %67)
  store <2 x float> %69, ptr %16, align 4
  %70 = load <2 x float>, ptr %6, align 4
  %71 = load <2 x float>, ptr %16, align 4
  %72 = call <2 x float> @vrAdd(<2 x float> %70, <2 x float> %71)
  store <2 x float> %72, ptr %15, align 4
  %73 = load ptr, ptr %10, align 8, !tbaa !9
  %74 = load i32, ptr %13, align 4, !tbaa !11
  %75 = sext i32 %74 to i64
  %76 = getelementptr inbounds %struct.vrVec2, ptr %73, i64 %75
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %76, ptr align 4 %15, i64 8, i1 false), !tbaa.struct !13
  %77 = load i32, ptr %13, align 4, !tbaa !11
  %78 = add nsw i32 %77, 1
  store i32 %78, ptr %13, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #5
  br label %79

79:                                               ; preds = %58, %55, %49
  %80 = load i32, ptr %13, align 4, !tbaa !11
  %81 = icmp ne i32 %80, 0
  %82 = xor i1 %81, true
  %83 = zext i1 %82 to i32
  %84 = icmp sge i32 %83, 3
  br i1 %84, label %85, label %87

85:                                               ; preds = %79
  %86 = call i32 (ptr, ...) @printf(ptr noundef @.str)
  call void @abort() #6
  unreachable

87:                                               ; preds = %79
  %88 = load i32, ptr %13, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  ret i32 %88
}

declare <2 x float> @vrAdd(<2 x float>, <2 x float>) #1

declare <2 x float> @vrScale(<2 x float>, float noundef) #1

declare i32 @printf(ptr noundef, ...) #1

; Function Attrs: noreturn nounwind
declare void @abort() #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{i64 0, i64 4, !5, i64 4, i64 4, !5}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.vrVec2 = type { float, float }

declare <2 x float> @vrSub(<2 x float>, <2 x float>) local_unnamed_addr #0

declare float @vrDot(<2 x float>, <2 x float>) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @Clip(<2 x float> %0, <2 x float> %1, <2 x float> %2, float noundef %3, ptr nocapture noundef writeonly %4) local_unnamed_addr #1 {
  %6 = tail call float @vrDot(<2 x float> %2, <2 x float> %0) #2
  %7 = fsub float %6, %3
  %8 = tail call float @vrDot(<2 x float> %2, <2 x float> %1) #2
  %9 = fsub float %8, %3
  %10 = fcmp ult float %7, 0.000000e+00
  br i1 %10, label %12, label %11

11:                                               ; preds = %5
  store <2 x float> %0, ptr %4, align 4
  br label %12

12:                                               ; preds = %11, %5
  %.0 = phi i32 [ 1, %11 ], [ 0, %5 ]
  %13 = fcmp ult float %9, 0.000000e+00
  br i1 %13, label %18, label %14

14:                                               ; preds = %12
  %15 = zext nneg i32 %.0 to i64
  %16 = getelementptr inbounds %struct.vrVec2, ptr %4, i64 %15
  store <2 x float> %1, ptr %16, align 4
  %17 = add nuw nsw i32 %.0, 1
  br label %18

18:                                               ; preds = %14, %12
  %.1 = phi i32 [ %17, %14 ], [ %.0, %12 ]
  %19 = fmul float %7, %9
  %20 = fcmp olt float %19, 0.000000e+00
  %21 = icmp ult i32 %.1, 2
  %or.cond = select i1 %20, i1 %21, i1 false
  br i1 %or.cond, label %22, label %31

22:                                               ; preds = %18
  %23 = fsub float %7, %9
  %24 = fdiv float %7, %23
  %25 = tail call <2 x float> @vrSub(<2 x float> %1, <2 x float> %0) #2
  %26 = tail call <2 x float> @vrScale(<2 x float> %25, float noundef %24) #2
  %27 = tail call <2 x float> @vrAdd(<2 x float> %0, <2 x float> %26) #2
  %28 = zext nneg i32 %.1 to i64
  %29 = getelementptr inbounds %struct.vrVec2, ptr %4, i64 %28
  store <2 x float> %27, ptr %29, align 4
  %30 = add nuw nsw i32 %.1, 1
  br label %31

31:                                               ; preds = %18, %22
  %.2 = phi i32 [ %30, %22 ], [ %.1, %18 ]
  ret i32 %.2
}

declare <2 x float> @vrAdd(<2 x float>, <2 x float>) local_unnamed_addr #0

declare <2 x float> @vrScale(<2 x float>, float noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass