; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (edma_bb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @EDMA3CrossBarChannelMap(i32 noundef %0, i32 noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  store i32 0, ptr %9, align 4, !tbaa !5
  %10 = load i32, ptr %6, align 4, !tbaa !5
  %11 = udiv i32 %10, 4
  store i32 %11, ptr %7, align 4, !tbaa !5
  %12 = load i32, ptr %6, align 4, !tbaa !5
  %13 = load i32, ptr %7, align 4, !tbaa !5
  %14 = mul i32 %13, 4
  %15 = sub i32 %12, %14
  store i32 %15, ptr %8, align 4, !tbaa !5
  %16 = load i32, ptr %8, align 4, !tbaa !5
  switch i32 %16, label %21 [
    i32 0, label %17
    i32 1, label %18
    i32 2, label %19
    i32 3, label %20
  ]

17:                                               ; preds = %3
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %22

18:                                               ; preds = %3
  store i32 8, ptr %9, align 4, !tbaa !5
  br label %22

19:                                               ; preds = %3
  store i32 16, ptr %9, align 4, !tbaa !5
  br label %22

20:                                               ; preds = %3
  store i32 24, ptr %9, align 4, !tbaa !5
  br label %22

21:                                               ; preds = %3
  br label %22

22:                                               ; preds = %21, %20, %19, %18, %17
  %23 = load i32, ptr %5, align 4, !tbaa !5
  %24 = load i32, ptr %9, align 4, !tbaa !5
  %25 = shl i32 %23, %24
  %26 = xor i32 %25, -1
  %27 = load i32, ptr %4, align 4, !tbaa !5
  %28 = add i32 %27, 3984
  %29 = load i32, ptr %7, align 4, !tbaa !5
  %30 = mul i32 %29, 4
  %31 = add i32 %28, %30
  %32 = zext i32 %31 to i64
  %33 = inttoptr i64 %32 to ptr
  %34 = load volatile i32, ptr %33, align 4, !tbaa !5
  %35 = and i32 %34, %26
  store volatile i32 %35, ptr %33, align 4, !tbaa !5
  %36 = load i32, ptr %5, align 4, !tbaa !5
  %37 = load i32, ptr %9, align 4, !tbaa !5
  %38 = shl i32 %36, %37
  %39 = load i32, ptr %4, align 4, !tbaa !5
  %40 = add i32 %39, 3984
  %41 = load i32, ptr %7, align 4, !tbaa !5
  %42 = mul i32 %41, 4
  %43 = add i32 %40, %42
  %44 = zext i32 %43 to i64
  %45 = inttoptr i64 %44 to ptr
  %46 = load volatile i32, ptr %45, align 4, !tbaa !5
  %47 = or i32 %46, %38
  store volatile i32 %47, ptr %45, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local noundef i32 @EDMA3CrossBarChannelMap(i32 noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
switch.lookup:
  %3 = shl i32 %2, 3
  %switch.idx.mult = and i32 %3, 24
  %4 = and i32 %2, -4
  %5 = shl i32 %1, %switch.idx.mult
  %6 = xor i32 %5, -1
  %7 = add i32 %0, 3984
  %8 = add i32 %7, %4
  %9 = zext i32 %8 to i64
  %10 = inttoptr i64 %9 to ptr
  %11 = load volatile i32, ptr %10, align 4, !tbaa !5
  %12 = and i32 %11, %6
  store volatile i32 %12, ptr %10, align 4, !tbaa !5
  %13 = load volatile i32, ptr %10, align 4, !tbaa !5
  %14 = or i32 %13, %5
  store volatile i32 %14, ptr %10, align 4, !tbaa !5
  ret i32 0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass