; LLVM IR from lfarcaro/ARINC653_ARMV7A_AM335X :: Hardware (dcan_frame)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._dcan_hw_params = type { i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @canUpdatSamPt(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, ptr noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !5
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = add nsw i32 %11, 1
  %13 = load i32, ptr %7, align 4, !tbaa !9
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = add nsw i32 %14, 1
  %16 = mul nsw i32 %13, %15
  %17 = sdiv i32 %16, 1000
  %18 = sub nsw i32 %12, %17
  %19 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %18, ptr %19, align 4, !tbaa !9
  %20 = load ptr, ptr %10, align 8, !tbaa !5
  %21 = load i32, ptr %20, align 4, !tbaa !9
  %22 = load ptr, ptr %6, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct._dcan_hw_params, ptr %22, i32 0, i32 2
  %24 = load i32, ptr %23, align 4, !tbaa !11
  %25 = icmp ult i32 %21, %24
  br i1 %25, label %26, label %31

26:                                               ; preds = %5
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct._dcan_hw_params, ptr %27, i32 0, i32 2
  %29 = load i32, ptr %28, align 4, !tbaa !11
  %30 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %29, ptr %30, align 4, !tbaa !9
  br label %31

31:                                               ; preds = %26, %5
  %32 = load ptr, ptr %10, align 8, !tbaa !5
  %33 = load i32, ptr %32, align 4, !tbaa !9
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct._dcan_hw_params, ptr %34, i32 0, i32 3
  %36 = load i32, ptr %35, align 4, !tbaa !13
  %37 = icmp ugt i32 %33, %36
  br i1 %37, label %38, label %43

38:                                               ; preds = %31
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct._dcan_hw_params, ptr %39, i32 0, i32 3
  %41 = load i32, ptr %40, align 4, !tbaa !13
  %42 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %41, ptr %42, align 4, !tbaa !9
  br label %43

43:                                               ; preds = %38, %31
  %44 = load i32, ptr %8, align 4, !tbaa !9
  %45 = load ptr, ptr %10, align 8, !tbaa !5
  %46 = load i32, ptr %45, align 4, !tbaa !9
  %47 = sub nsw i32 %44, %46
  %48 = load ptr, ptr %9, align 8, !tbaa !5
  store i32 %47, ptr %48, align 4, !tbaa !9
  %49 = load ptr, ptr %9, align 8, !tbaa !5
  %50 = load i32, ptr %49, align 4, !tbaa !9
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct._dcan_hw_params, ptr %51, i32 0, i32 1
  %53 = load i32, ptr %52, align 4, !tbaa !14
  %54 = icmp ugt i32 %50, %53
  br i1 %54, label %55, label %65

55:                                               ; preds = %43
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct._dcan_hw_params, ptr %56, i32 0, i32 1
  %58 = load i32, ptr %57, align 4, !tbaa !14
  %59 = load ptr, ptr %9, align 8, !tbaa !5
  store i32 %58, ptr %59, align 4, !tbaa !9
  %60 = load i32, ptr %8, align 4, !tbaa !9
  %61 = load ptr, ptr %9, align 8, !tbaa !5
  %62 = load i32, ptr %61, align 4, !tbaa !9
  %63 = sub nsw i32 %60, %62
  %64 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %63, ptr %64, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %55, %43
  %66 = load i32, ptr %8, align 4, !tbaa !9
  %67 = add nsw i32 %66, 1
  %68 = load ptr, ptr %10, align 8, !tbaa !5
  %69 = load i32, ptr %68, align 4, !tbaa !9
  %70 = sub nsw i32 %67, %69
  %71 = mul nsw i32 1000, %70
  %72 = load i32, ptr %8, align 4, !tbaa !9
  %73 = add nsw i32 %72, 1
  %74 = sdiv i32 %71, %73
  ret i32 %74
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"_dcan_hw_params", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}
!13 = !{!12, !10, i64 12}
!14 = !{!12, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
define dso_local i32 @canUpdatSamPt(ptr nocapture noundef readonly %0, i32 noundef %1, i32 noundef %2, ptr nocapture noundef writeonly %3, ptr nocapture noundef %4) local_unnamed_addr #0 {
  %6 = add nsw i32 %2, 1
  %7 = mul nsw i32 %6, %1
  %.neg = sdiv i32 %7, -1000
  %8 = add i32 %.neg, %6
  store i32 %8, ptr %4, align 4, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 8
  %10 = load i32, ptr %9, align 4, !tbaa !9
  %spec.store.select = tail call i32 @llvm.umax.i32(i32 %8, i32 %10)
  store i32 %spec.store.select, ptr %4, align 4
  %11 = getelementptr inbounds i8, ptr %0, i64 12
  %12 = load i32, ptr %11, align 4, !tbaa !11
  %spec.store.select26 = tail call i32 @llvm.umin.i32(i32 %spec.store.select, i32 %12)
  store i32 %spec.store.select26, ptr %4, align 4
  %13 = sub nsw i32 %2, %spec.store.select26
  store i32 %13, ptr %3, align 4, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %0, i64 4
  %15 = load i32, ptr %14, align 4, !tbaa !12
  %16 = icmp ugt i32 %13, %15
  br i1 %16, label %17, label %._crit_edge

._crit_edge:                                      ; preds = %5
  %.pre = load i32, ptr %4, align 4, !tbaa !5
  br label %19

17:                                               ; preds = %5
  store i32 %15, ptr %3, align 4, !tbaa !5
  %18 = sub nsw i32 %2, %15
  store i32 %18, ptr %4, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %._crit_edge, %17
  %20 = phi i32 [ %.pre, %._crit_edge ], [ %18, %17 ]
  %21 = sub nsw i32 %6, %20
  %22 = mul nsw i32 %21, 1000
  %23 = sdiv i32 %22, %6
  ret i32 %23
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"_dcan_hw_params", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28}
!11 = !{!10, !6, i64 12}
!12 = !{!10, !6, i64 4}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass