; LLVM IR from reazon-research/OpenArm :: control/canfd_control/Drivers/STM32H7xx_HAL_Driver/Src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@SystemCoreClock = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Abort(ptr noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  br label %7

7:                                                ; preds = %1
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %8, i32 0, i32 13
  %10 = load i32, ptr %9, align 8, !tbaa !9
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %12, label %13

12:                                               ; preds = %7
  store i32 2, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %225

13:                                               ; preds = %7
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %14, i32 0, i32 13
  store i32 1, ptr %15, align 8, !tbaa !9
  br label %16

16:                                               ; preds = %13
  br label %17

17:                                               ; preds = %16
  br label %18

18:                                               ; preds = %17
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %19, i32 0, i32 14
  store volatile i32 7, ptr %20, align 4, !tbaa !14
  store i32 0, ptr %4, align 4, !tbaa !15
  %21 = load i32, ptr @SystemCoreClock, align 4, !tbaa !15
  %22 = zext i32 %21 to i64
  %23 = udiv i64 %22, 24
  %24 = udiv i64 %23, 1000
  %25 = mul i64 100, %24
  %26 = trunc i64 %25 to i32
  store volatile i32 %26, ptr %5, align 4, !tbaa !15
  %27 = load ptr, ptr %3, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %27, i32 0, i32 0
  %29 = load ptr, ptr %28, align 8, !tbaa !16
  %30 = getelementptr inbounds %struct.SPI_TypeDef, ptr %29, i32 0, i32 0
  %31 = load volatile i32, ptr %30, align 4, !tbaa !17
  %32 = zext i32 %31 to i64
  %33 = and i64 %32, 512
  %34 = icmp eq i64 %33, 512
  br i1 %34, label %35, label %132

35:                                               ; preds = %18
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !16
  %39 = getelementptr inbounds %struct.SPI_TypeDef, ptr %38, i32 0, i32 4
  %40 = load volatile i32, ptr %39, align 4, !tbaa !19
  %41 = zext i32 %40 to i64
  %42 = and i64 %41, -9
  %43 = trunc i64 %42 to i32
  store volatile i32 %43, ptr %39, align 4, !tbaa !19
  br label %44

44:                                               ; preds = %58, %35
  %45 = load volatile i32, ptr %5, align 4, !tbaa !15
  %46 = add i32 %45, -1
  store volatile i32 %46, ptr %5, align 4, !tbaa !15
  %47 = load volatile i32, ptr %5, align 4, !tbaa !15
  %48 = zext i32 %47 to i64
  %49 = icmp eq i64 %48, 0
  br i1 %49, label %50, label %57

50:                                               ; preds = %44
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %51, i32 0, i32 15
  %53 = load volatile i32, ptr %52, align 8, !tbaa !20
  %54 = zext i32 %53 to i64
  %55 = or i64 %54, 64
  %56 = trunc i64 %55 to i32
  store volatile i32 %56, ptr %52, align 8, !tbaa !20
  br label %67

57:                                               ; preds = %44
  br label %58

58:                                               ; preds = %57
  %59 = load ptr, ptr %3, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !16
  %62 = getelementptr inbounds %struct.SPI_TypeDef, ptr %61, i32 0, i32 4
  %63 = load volatile i32, ptr %62, align 4, !tbaa !19
  %64 = zext i32 %63 to i64
  %65 = and i64 %64, 8
  %66 = icmp eq i64 %65, 8
  br i1 %66, label %44, label %67, !llvm.loop !21

67:                                               ; preds = %58, %50
  %68 = load ptr, ptr %3, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %68, i32 0, i32 0
  %70 = load ptr, ptr %69, align 8, !tbaa !16
  %71 = getelementptr inbounds %struct.SPI_TypeDef, ptr %70, i32 0, i32 0
  %72 = load volatile i32, ptr %71, align 4, !tbaa !17
  %73 = zext i32 %72 to i64
  %74 = or i64 %73, 1024
  %75 = trunc i64 %74 to i32
  store volatile i32 %75, ptr %71, align 4, !tbaa !17
  br label %76

76:                                               ; preds = %90, %67
  %77 = load volatile i32, ptr %5, align 4, !tbaa !15
  %78 = add i32 %77, -1
  store volatile i32 %78, ptr %5, align 4, !tbaa !15
  %79 = load volatile i32, ptr %5, align 4, !tbaa !15
  %80 = zext i32 %79 to i64
  %81 = icmp eq i64 %80, 0
  br i1 %81, label %82, label %89

82:                                               ; preds = %76
  %83 = load ptr, ptr %3, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %83, i32 0, i32 15
  %85 = load volatile i32, ptr %84, align 8, !tbaa !20
  %86 = zext i32 %85 to i64
  %87 = or i64 %86, 64
  %88 = trunc i64 %87 to i32
  store volatile i32 %88, ptr %84, align 8, !tbaa !20
  br label %99

89:                                               ; preds = %76
  br label %90

90:                                               ; preds = %89
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !16
  %94 = getelementptr inbounds %struct.SPI_TypeDef, ptr %93, i32 0, i32 0
  %95 = load volatile i32, ptr %94, align 4, !tbaa !17
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, 512
  %98 = icmp eq i64 %97, 512
  br i1 %98, label %76, label %99, !llvm.loop !23

99:                                               ; preds = %90, %82
  %100 = load ptr, ptr %3, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %100, i32 0, i32 0
  %102 = load ptr, ptr %101, align 8, !tbaa !16
  %103 = getelementptr inbounds %struct.SPI_TypeDef, ptr %102, i32 0, i32 6
  %104 = load volatile i32, ptr %103, align 4, !tbaa !24
  %105 = zext i32 %104 to i64
  %106 = or i64 %105, 2048
  %107 = trunc i64 %106 to i32
  store volatile i32 %107, ptr %103, align 4, !tbaa !24
  br label %108

108:                                              ; preds = %122, %99
  %109 = load volatile i32, ptr %5, align 4, !tbaa !15
  %110 = add i32 %109, -1
  store volatile i32 %110, ptr %5, align 4, !tbaa !15
  %111 = load volatile i32, ptr %5, align 4, !tbaa !15
  %112 = zext i32 %111 to i64
  %113 = icmp eq i64 %112, 0
  br i1 %113, label %114, label %121

114:                                              ; preds = %108
  %115 = load ptr, ptr %3, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %115, i32 0, i32 15
  %117 = load volatile i32, ptr %116, align 8, !tbaa !20
  %118 = zext i32 %117 to i64
  %119 = or i64 %118, 64
  %120 = trunc i64 %119 to i32
  store volatile i32 %120, ptr %116, align 8, !tbaa !20
  br label %131

121:                                              ; preds = %108
  br label %122

122:                                              ; preds = %121
  %123 = load ptr, ptr %3, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %123, i32 0, i32 0
  %125 = load ptr, ptr %124, align 8, !tbaa !16
  %126 = getelementptr inbounds %struct.SPI_TypeDef, ptr %125, i32 0, i32 5
  %127 = load volatile i32, ptr %126, align 4, !tbaa !25
  %128 = zext i32 %127 to i64
  %129 = and i64 %128, 2048
  %130 = icmp eq i64 %129, 2048
  br i1 %130, label %108, label %131, !llvm.loop !26

131:                                              ; preds = %122, %114
  br label %132

132:                                              ; preds = %131, %18
  %133 = load ptr, ptr %3, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %133, i32 0, i32 0
  %135 = load ptr, ptr %134, align 8, !tbaa !16
  %136 = getelementptr inbounds %struct.SPI_TypeDef, ptr %135, i32 0, i32 2
  %137 = load volatile i32, ptr %136, align 4, !tbaa !27
  %138 = zext i32 %137 to i64
  %139 = and i64 %138, 32768
  %140 = icmp eq i64 %139, 32768
  br i1 %140, label %141, label %168

141:                                              ; preds = %132
  %142 = load ptr, ptr %3, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %142, i32 0, i32 11
  %144 = load ptr, ptr %143, align 8, !tbaa !28
  %145 = icmp ne ptr %144, null
  br i1 %145, label %146, label %167

146:                                              ; preds = %141
  %147 = load ptr, ptr %3, align 8, !tbaa !5
  %148 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %147, i32 0, i32 11
  %149 = load ptr, ptr %148, align 8, !tbaa !28
  %150 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %149, i32 0, i32 10
  store ptr null, ptr %150, align 8, !tbaa !29
  %151 = load ptr, ptr %3, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %151, i32 0, i32 11
  %153 = load ptr, ptr %152, align 8, !tbaa !28
  %154 = call i32 @HAL_DMA_Abort(ptr noundef %153)
  %155 = icmp ne i32 %154, 0
  br i1 %155, label %156, label %166

156:                                              ; preds = %146
  %157 = load ptr, ptr %3, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %157, i32 0, i32 11
  %159 = load ptr, ptr %158, align 8, !tbaa !28
  %160 = call i32 @HAL_DMA_GetError(ptr noundef %159)
  %161 = icmp eq i32 %160, 32
  br i1 %161, label %162, label %165

162:                                              ; preds = %156
  %163 = load ptr, ptr %3, align 8, !tbaa !5
  %164 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %163, i32 0, i32 15
  store volatile i32 64, ptr %164, align 8, !tbaa !20
  br label %165

165:                                              ; preds = %162, %156
  br label %166

166:                                              ; preds = %165, %146
  br label %167

167:                                              ; preds = %166, %141
  br label %168

168:                                              ; preds = %167, %132
  %169 = load ptr, ptr %3, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %169, i32 0, i32 0
  %171 = load ptr, ptr %170, align 8, !tbaa !16
  %172 = getelementptr inbounds %struct.SPI_TypeDef, ptr %171, i32 0, i32 2
  %173 = load volatile i32, ptr %172, align 4, !tbaa !27
  %174 = zext i32 %173 to i64
  %175 = and i64 %174, 16384
  %176 = icmp eq i64 %175, 16384
  br i1 %176, label %177, label %204

177:                                              ; preds = %168
  %178 = load ptr, ptr %3, align 8, !tbaa !5
  %179 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %178, i32 0, i32 12
  %180 = load ptr, ptr %179, align 8, !tbaa !32
  %181 = icmp ne ptr %180, null
  br i1 %181, label %182, label %203

182:                                              ; preds = %177
  %183 = load ptr, ptr %3, align 8, !tbaa !5
  %184 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %183, i32 0, i32 12
  %185 = load ptr, ptr %184, align 8, !tbaa !32
  %186 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %185, i32 0, i32 10
  store ptr null, ptr %186, align 8, !tbaa !29
  %187 = load ptr, ptr %3, align 8, !tbaa !5
  %188 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %187, i32 0, i32 12
  %189 = load ptr, ptr %188, align 8, !tbaa !32
  %190 = call i32 @HAL_DMA_Abort(ptr noundef %189)
  %191 = icmp ne i32 %190, 0
  br i1 %191, label %192, label %202

192:                                              ; preds = %182
  %193 = load ptr, ptr %3, align 8, !tbaa !5
  %194 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %193, i32 0, i32 12
  %195 = load ptr, ptr %194, align 8, !tbaa !32
  %196 = call i32 @HAL_DMA_GetError(ptr noundef %195)
  %197 = icmp eq i32 %196, 32
  br i1 %197, label %198, label %201

198:                                              ; preds = %192
  %199 = load ptr, ptr %3, align 8, !tbaa !5
  %200 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %199, i32 0, i32 15
  store volatile i32 64, ptr %200, align 8, !tbaa !20
  br label %201

201:                                              ; preds = %198, %192
  br label %202

202:                                              ; preds = %201, %182
  br label %203

203:                                              ; preds = %202, %177
  br label %204

204:                                              ; preds = %203, %168
  %205 = load ptr, ptr %3, align 8, !tbaa !5
  call void @SPI_AbortTransfer(ptr noundef %205)
  %206 = load ptr, ptr %3, align 8, !tbaa !5
  %207 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %206, i32 0, i32 15
  %208 = load volatile i32, ptr %207, align 8, !tbaa !20
  %209 = zext i32 %208 to i64
  %210 = and i64 %209, 64
  %211 = icmp eq i64 %210, 64
  br i1 %211, label %212, label %213

212:                                              ; preds = %204
  store i32 1, ptr %4, align 4, !tbaa !15
  br label %216

213:                                              ; preds = %204
  %214 = load ptr, ptr %3, align 8, !tbaa !5
  %215 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %214, i32 0, i32 15
  store volatile i32 0, ptr %215, align 8, !tbaa !20
  br label %216

216:                                              ; preds = %213, %212
  br label %217

217:                                              ; preds = %216
  %218 = load ptr, ptr %3, align 8, !tbaa !5
  %219 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %218, i32 0, i32 13
  store i32 0, ptr %219, align 8, !tbaa !9
  br label %220

220:                                              ; preds = %217
  br label %221

221:                                              ; preds = %220
  %222 = load ptr, ptr %3, align 8, !tbaa !5
  %223 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %222, i32 0, i32 14
  store volatile i32 1, ptr %223, align 4, !tbaa !14
  %224 = load i32, ptr %4, align 4, !tbaa !15
  store i32 %224, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %225

225:                                              ; preds = %221, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %226 = load i32, ptr %2, align 4
  ret i32 %226
}

declare i32 @HAL_DMA_Abort(ptr noundef) #2

declare i32 @HAL_DMA_GetError(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @SPI_AbortTransfer(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 160}
!10 = !{!"__SPI_HandleTypeDef", !6, i64 0, !11, i64 8, !6, i64 96, !13, i64 104, !13, i64 106, !6, i64 112, !13, i64 120, !13, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!12 = !{!"int", !7, i64 0}
!13 = !{!"short", !7, i64 0}
!14 = !{!10, !12, i64 164}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !6, i64 0}
!17 = !{!18, !12, i64 0}
!18 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!19 = !{!18, !12, i64 16}
!20 = !{!10, !12, i64 168}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = distinct !{!23, !22}
!24 = !{!18, !12, i64 24}
!25 = !{!18, !12, i64 20}
!26 = distinct !{!26, !22}
!27 = !{!18, !12, i64 8}
!28 = !{!10, !6, i64 144}
!29 = !{!30, !6, i64 112}
!30 = !{!"__DMA_HandleTypeDef", !6, i64 0, !31, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!31 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!32 = !{!10, !6, i64 152}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SPI_Abort(ptr noundef %0) local_unnamed_addr #1 {
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
  %3 = getelementptr inbounds i8, ptr %0, i64 160
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %91, label %6

6:                                                ; preds = %1
  store i32 1, ptr %3, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 164
  store volatile i32 7, ptr %7, align 4, !tbaa !13
  %8 = load i32, ptr @SystemCoreClock, align 4, !tbaa !14
  %9 = udiv i32 %8, 24000
  %narrow = mul nuw nsw i32 %9, 100
  store volatile i32 %narrow, ptr %2, align 4, !tbaa !14
  %10 = load ptr, ptr %0, align 8, !tbaa !15
  %11 = load volatile i32, ptr %10, align 4, !tbaa !16
  %12 = and i32 %11, 512
  %.not = icmp eq i32 %12, 0
  br i1 %.not, label %.loopexit, label %13

13:                                               ; preds = %6
  %14 = getelementptr inbounds i8, ptr %10, i64 16
  %15 = load volatile i32, ptr %14, align 4, !tbaa !18
  %16 = and i32 %15, -9
  store volatile i32 %16, ptr %14, align 4, !tbaa !18
  br label %17

17:                                               ; preds = %24, %13
  %.0..0..0..0. = load volatile i32, ptr %2, align 4, !tbaa !14
  %18 = add i32 %.0..0..0..0., -1
  store volatile i32 %18, ptr %2, align 4, !tbaa !14
  %.0..0..0..0.1 = load volatile i32, ptr %2, align 4, !tbaa !14
  %19 = icmp eq i32 %.0..0..0..0.1, 0
  br i1 %19, label %20, label %24

20:                                               ; preds = %17
  %21 = getelementptr inbounds i8, ptr %0, i64 168
  %22 = load volatile i32, ptr %21, align 8, !tbaa !19
  %23 = or i32 %22, 64
  store volatile i32 %23, ptr %21, align 8, !tbaa !19
  br label %.loopexit51

24:                                               ; preds = %17
  %25 = load volatile i32, ptr %14, align 4, !tbaa !18
  %26 = and i32 %25, 8
  %.not40 = icmp eq i32 %26, 0
  br i1 %.not40, label %.loopexit51, label %17, !llvm.loop !20

.loopexit51:                                      ; preds = %24, %20
  %27 = load volatile i32, ptr %10, align 4, !tbaa !16
  %28 = or i32 %27, 1024
  store volatile i32 %28, ptr %10, align 4, !tbaa !16
  br label %29

29:                                               ; preds = %36, %.loopexit51
  %.0..0..0..0.2 = load volatile i32, ptr %2, align 4, !tbaa !14
  %30 = add i32 %.0..0..0..0.2, -1
  store volatile i32 %30, ptr %2, align 4, !tbaa !14
  %.0..0..0..0.3 = load volatile i32, ptr %2, align 4, !tbaa !14
  %31 = icmp eq i32 %.0..0..0..0.3, 0
  br i1 %31, label %32, label %36

32:                                               ; preds = %29
  %33 = getelementptr inbounds i8, ptr %0, i64 168
  %34 = load volatile i32, ptr %33, align 8, !tbaa !19
  %35 = or i32 %34, 64
  store volatile i32 %35, ptr %33, align 8, !tbaa !19
  br label %.loopexit50

36:                                               ; preds = %29
  %37 = load volatile i32, ptr %10, align 4, !tbaa !16
  %38 = and i32 %37, 512
  %.not41 = icmp eq i32 %38, 0
  br i1 %.not41, label %.loopexit50, label %29, !llvm.loop !22

.loopexit50:                                      ; preds = %36, %32
  %39 = getelementptr inbounds i8, ptr %10, i64 24
  %40 = load volatile i32, ptr %39, align 4, !tbaa !23
  %41 = or i32 %40, 2048
  store volatile i32 %41, ptr %39, align 4, !tbaa !23
  %42 = getelementptr inbounds i8, ptr %10, i64 20
  br label %43

43:                                               ; preds = %50, %.loopexit50
  %.0..0..0..0.4 = load volatile i32, ptr %2, align 4, !tbaa !14
  %44 = add i32 %.0..0..0..0.4, -1
  store volatile i32 %44, ptr %2, align 4, !tbaa !14
  %.0..0..0..0.5 = load volatile i32, ptr %2, align 4, !tbaa !14
  %45 = icmp eq i32 %.0..0..0..0.5, 0
  br i1 %45, label %46, label %50

46:                                               ; preds = %43
  %47 = getelementptr inbounds i8, ptr %0, i64 168
  %48 = load volatile i32, ptr %47, align 8, !tbaa !19
  %49 = or i32 %48, 64
  store volatile i32 %49, ptr %47, align 8, !tbaa !19
  br label %.loopexit

50:                                               ; preds = %43
  %51 = load volatile i32, ptr %42, align 4, !tbaa !24
  %52 = and i32 %51, 2048
  %.not42 = icmp eq i32 %52, 0
  br i1 %.not42, label %.loopexit, label %43, !llvm.loop !25

.loopexit:                                        ; preds = %50, %46, %6
  %53 = getelementptr inbounds i8, ptr %10, i64 8
  %54 = load volatile i32, ptr %53, align 4, !tbaa !26
  %55 = and i32 %54, 32768
  %.not43 = icmp eq i32 %55, 0
  br i1 %.not43, label %68, label %56

56:                                               ; preds = %.loopexit
  %57 = getelementptr inbounds i8, ptr %0, i64 144
  %58 = load ptr, ptr %57, align 8, !tbaa !27
  %.not44 = icmp eq ptr %58, null
  br i1 %.not44, label %68, label %59

59:                                               ; preds = %56
  %60 = getelementptr inbounds i8, ptr %58, i64 112
  store ptr null, ptr %60, align 8, !tbaa !28
  %61 = tail call i32 @HAL_DMA_Abort(ptr noundef nonnull %58) #3
  %.not45 = icmp eq i32 %61, 0
  br i1 %.not45, label %68, label %62

62:                                               ; preds = %59
  %63 = load ptr, ptr %57, align 8, !tbaa !27
  %64 = tail call i32 @HAL_DMA_GetError(ptr noundef %63) #3
  %65 = icmp eq i32 %64, 32
  br i1 %65, label %66, label %68

66:                                               ; preds = %62
  %67 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 64, ptr %67, align 8, !tbaa !19
  br label %68

68:                                               ; preds = %56, %62, %66, %59, %.loopexit
  %69 = load ptr, ptr %0, align 8, !tbaa !15
  %70 = getelementptr inbounds i8, ptr %69, i64 8
  %71 = load volatile i32, ptr %70, align 4, !tbaa !26
  %72 = and i32 %71, 16384
  %.not46 = icmp eq i32 %72, 0
  br i1 %.not46, label %85, label %73

73:                                               ; preds = %68
  %74 = getelementptr inbounds i8, ptr %0, i64 152
  %75 = load ptr, ptr %74, align 8, !tbaa !31
  %.not47 = icmp eq ptr %75, null
  br i1 %.not47, label %85, label %76

76:                                               ; preds = %73
  %77 = getelementptr inbounds i8, ptr %75, i64 112
  store ptr null, ptr %77, align 8, !tbaa !28
  %78 = tail call i32 @HAL_DMA_Abort(ptr noundef nonnull %75) #3
  %.not48 = icmp eq i32 %78, 0
  br i1 %.not48, label %85, label %79

79:                                               ; preds = %76
  %80 = load ptr, ptr %74, align 8, !tbaa !31
  %81 = tail call i32 @HAL_DMA_GetError(ptr noundef %80) #3
  %82 = icmp eq i32 %81, 32
  br i1 %82, label %83, label %85

83:                                               ; preds = %79
  %84 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 64, ptr %84, align 8, !tbaa !19
  br label %85

85:                                               ; preds = %73, %79, %83, %76, %68
  tail call void @SPI_AbortTransfer(ptr noundef nonnull %0)
  %86 = getelementptr inbounds i8, ptr %0, i64 168
  %87 = load volatile i32, ptr %86, align 8, !tbaa !19
  %88 = and i32 %87, 64
  %.not49 = icmp eq i32 %88, 0
  br i1 %.not49, label %89, label %90

89:                                               ; preds = %85
  store volatile i32 0, ptr %86, align 8, !tbaa !19
  br label %90

90:                                               ; preds = %85, %89
  %.0 = phi i32 [ 0, %89 ], [ 1, %85 ]
  store i32 0, ptr %3, align 8, !tbaa !5
  store volatile i32 1, ptr %7, align 4, !tbaa !13
  br label %91

91:                                               ; preds = %1, %90
  %.037 = phi i32 [ %.0, %90 ], [ 2, %1 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
  ret i32 %.037
}

declare i32 @HAL_DMA_Abort(ptr noundef) local_unnamed_addr #2

declare i32 @HAL_DMA_GetError(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @SPI_AbortTransfer(ptr noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 160}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 164}
!14 = !{!11, !11, i64 0}
!15 = !{!6, !7, i64 0}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!18 = !{!17, !11, i64 16}
!19 = !{!6, !11, i64 168}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = distinct !{!22, !21}
!23 = !{!17, !11, i64 24}
!24 = !{!17, !11, i64 20}
!25 = distinct !{!25, !21}
!26 = !{!17, !11, i64 8}
!27 = !{!6, !7, i64 144}
!28 = !{!29, !7, i64 112}
!29 = !{!"__DMA_HandleTypeDef", !7, i64 0, !30, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!30 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!31 = !{!6, !7, i64 152}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass