; LLVM IR from ShahjalalShohag/code-library :: Number Theory/Powerful Number Sieve.ll (Z5bruteixx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@primes = external dso_local global %"class.std::vector", align 8
@n = external dso_local global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z3mulxx(i64 noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z12g_prefix_sumx(i64 noundef) #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z5get_hiix(i32 noundef, i32 noundef, i64 noundef) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5bruteixx(i32 noundef %0, i64 noundef %1, i64 noundef %2) #3 {
  %4 = alloca i32, align 4
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i64, align 8
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store i64 %2, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %11 = load i64, ptr %6, align 8, !tbaa !9
  %12 = load i64, ptr @n, align 8, !tbaa !9
  %13 = load i64, ptr %5, align 8, !tbaa !9
  %14 = sdiv i64 %12, %13
  %15 = call noundef i64 @_Z12g_prefix_sumx(i64 noundef %14)
  %16 = call noundef i64 @_Z3mulxx(i64 noundef %11, i64 noundef %15)
  store i64 %16, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %17 = load i64, ptr @n, align 8, !tbaa !9
  %18 = load i64, ptr %5, align 8, !tbaa !9
  %19 = sdiv i64 %17, %18
  store i64 %19, ptr %8, align 8, !tbaa !9
  br label %20

20:                                               ; preds = %86, %3
  %21 = load i32, ptr %4, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @primes) #4
  %24 = icmp ult i64 %22, %23
  br i1 %24, label %25, label %40

25:                                               ; preds = %20
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %27) #4
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = mul nsw i64 1, %30
  %32 = load i32, ptr %4, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %33) #4
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = mul nsw i64 %31, %36
  %38 = load i64, ptr %8, align 8, !tbaa !9
  %39 = icmp sle i64 %37, %38
  br label %40

40:                                               ; preds = %25, %20
  %41 = phi i1 [ false, %20 ], [ %39, %25 ]
  br i1 %41, label %42, label %89

42:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  store i32 2, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %43 = load i32, ptr %4, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %44) #4
  %46 = load i32, ptr %45, align 4, !tbaa !5
  %47 = sext i32 %46 to i64
  %48 = mul nsw i64 1, %47
  %49 = load i32, ptr %4, align 4, !tbaa !5
  %50 = sext i32 %49 to i64
  %51 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %50) #4
  %52 = load i32, ptr %51, align 4, !tbaa !5
  %53 = sext i32 %52 to i64
  %54 = mul nsw i64 %48, %53
  store i64 %54, ptr %10, align 8, !tbaa !9
  br label %55

55:                                               ; preds = %59, %42
  %56 = load i64, ptr %10, align 8, !tbaa !9
  %57 = load i64, ptr %8, align 8, !tbaa !9
  %58 = icmp sle i64 %56, %57
  br i1 %58, label %59, label %86

59:                                               ; preds = %55
  %60 = load i64, ptr %7, align 8, !tbaa !9
  %61 = load i32, ptr %4, align 4, !tbaa !5
  %62 = add nsw i32 %61, 1
  %63 = load i64, ptr %5, align 8, !tbaa !9
  %64 = load i64, ptr %10, align 8, !tbaa !9
  %65 = mul nsw i64 %63, %64
  %66 = load i64, ptr %6, align 8, !tbaa !9
  %67 = load i32, ptr %4, align 4, !tbaa !5
  %68 = sext i32 %67 to i64
  %69 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %68) #4
  %70 = load i32, ptr %69, align 4, !tbaa !5
  %71 = load i32, ptr %9, align 4, !tbaa !5
  %72 = load i64, ptr %10, align 8, !tbaa !9
  %73 = call noundef i64 @_Z5get_hiix(i32 noundef %70, i32 noundef %71, i64 noundef %72)
  %74 = call noundef i64 @_Z3mulxx(i64 noundef %66, i64 noundef %73)
  %75 = call noundef i64 @_Z5bruteixx(i32 noundef %62, i64 noundef %65, i64 noundef %74)
  %76 = call noundef i64 @_Z3addxx(i64 noundef %60, i64 noundef %75)
  store i64 %76, ptr %7, align 8, !tbaa !9
  %77 = load i32, ptr %9, align 4, !tbaa !5
  %78 = add nsw i32 %77, 1
  store i32 %78, ptr %9, align 4, !tbaa !5
  %79 = load i32, ptr %4, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %80) #4
  %82 = load i32, ptr %81, align 4, !tbaa !5
  %83 = sext i32 %82 to i64
  %84 = load i64, ptr %10, align 8, !tbaa !9
  %85 = mul nsw i64 %84, %83
  store i64 %85, ptr %10, align 8, !tbaa !9
  br label %55, !llvm.loop !11

86:                                               ; preds = %55
  %87 = load i32, ptr %4, align 4, !tbaa !5
  %88 = add nsw i32 %87, 1
  store i32 %88, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %20, !llvm.loop !13

89:                                               ; preds = %40
  %90 = load i64, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret i64 %90
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z3addxx(i64 noundef, i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@primes = external dso_local global %"class.std::vector", align 8
@n = external dso_local local_unnamed_addr global i64, align 8

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z3mulxx(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z12g_prefix_sumx(i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z5get_hiix(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5bruteixx(i32 noundef %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #2 {
  %4 = load i64, ptr @n, align 8, !tbaa !5
  %5 = sdiv i64 %4, %1
  %6 = tail call noundef i64 @_Z12g_prefix_sumx(i64 noundef %5)
  %7 = tail call noundef i64 @_Z3mulxx(i64 noundef %2, i64 noundef %6)
  %8 = load i64, ptr @n, align 8, !tbaa !5
  %9 = sdiv i64 %8, %1
  %10 = sext i32 %0 to i64
  %11 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @primes) #3
  %12 = icmp ugt i64 %11, %10
  br i1 %12, label %.lr.ph37, label %.critedge

.lr.ph37:                                         ; preds = %3, %._crit_edge
  %indvars.iv = phi i64 [ %.pre, %._crit_edge ], [ %10, %3 ]
  %.02634 = phi i64 [ %.1.lcssa, %._crit_edge ], [ %7, %3 ]
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %14 = load i32, ptr %13, align 4, !tbaa !9
  %15 = sext i32 %14 to i64
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %17 = load i32, ptr %16, align 4, !tbaa !9
  %18 = sext i32 %17 to i64
  %19 = mul nsw i64 %18, %15
  %.not = icmp sgt i64 %19, %9
  br i1 %.not, label %.critedge, label %20

20:                                               ; preds = %.lr.ph37
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %22 = load i32, ptr %21, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %25 = load i32, ptr %24, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = mul nsw i64 %26, %23
  %.not2930 = icmp sgt i64 %27, %9
  %.pre = add nuw nsw i64 %indvars.iv, 1
  br i1 %.not2930, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %20
  %28 = trunc nsw i64 %.pre to i32
  br label %29

29:                                               ; preds = %.lr.ph, %29
  %.033 = phi i64 [ %27, %.lr.ph ], [ %41, %29 ]
  %.02432 = phi i32 [ 2, %.lr.ph ], [ %37, %29 ]
  %.131 = phi i64 [ %.02634, %.lr.ph ], [ %36, %29 ]
  %30 = mul nsw i64 %.033, %1
  %31 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %32 = load i32, ptr %31, align 4, !tbaa !9
  %33 = tail call noundef i64 @_Z5get_hiix(i32 noundef %32, i32 noundef %.02432, i64 noundef %.033)
  %34 = tail call noundef i64 @_Z3mulxx(i64 noundef %2, i64 noundef %33)
  %35 = tail call noundef i64 @_Z5bruteixx(i32 noundef %28, i64 noundef %30, i64 noundef %34)
  %36 = tail call noundef i64 @_Z3addxx(i64 noundef %.131, i64 noundef %35)
  %37 = add nuw nsw i32 %.02432, 1
  %38 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @primes, i64 noundef %indvars.iv) #3
  %39 = load i32, ptr %38, align 4, !tbaa !9
  %40 = sext i32 %39 to i64
  %41 = mul nsw i64 %.033, %40
  %.not29 = icmp sgt i64 %41, %9
  br i1 %.not29, label %._crit_edge, label %29, !llvm.loop !11

._crit_edge:                                      ; preds = %29, %20
  %.1.lcssa = phi i64 [ %.02634, %20 ], [ %36, %29 ]
  %42 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @primes) #3
  %43 = icmp ugt i64 %42, %.pre
  br i1 %43, label %.lr.ph37, label %.critedge, !llvm.loop !13

.critedge:                                        ; preds = %.lr.ph37, %._crit_edge, %3
  %.026.lcssa = phi i64 [ %7, %3 ], [ %.1.lcssa, %._crit_edge ], [ %.02634, %.lr.ph37 ]
  ret i64 %.026.lcssa
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z3addxx(i64 noundef, i64 noundef) local_unnamed_addr #0

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass