; LLVM IR from tensorflow/tflite-micro :: tensorflow/lite/core/c (common)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TfLiteTensor = type { i32, %union.TfLitePtrUnion, ptr, %struct.TfLiteQuantizationParams, i32, i64, ptr, ptr, ptr, i32, i8, i8, %struct.TfLiteQuantization, ptr, ptr }
%union.TfLitePtrUnion = type { ptr }
%struct.TfLiteQuantizationParams = type { float, i32 }
%struct.TfLiteQuantization = type { i32, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local i32 @TfLiteTensorGetAllocationStrategy(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %4 = load ptr, ptr %3, align 8, !tbaa !5
  %5 = getelementptr inbounds %struct.TfLiteTensor, ptr %4, i32 0, i32 4
  %6 = load i32, ptr %5, align 8, !tbaa !9
  switch i32 %6, label %16 [
    i32 0, label %7
    i32 1, label %8
    i32 2, label %9
    i32 3, label %10
    i32 4, label %11
    i32 5, label %12
    i32 6, label %13
    i32 7, label %14
    i32 8, label %15
  ]

7:                                                ; preds = %1
  store i32 1, ptr %2, align 4
  br label %17

8:                                                ; preds = %1
  store i32 2, ptr %2, align 4
  br label %17

9:                                                ; preds = %1
  store i32 3, ptr %2, align 4
  br label %17

10:                                               ; preds = %1
  store i32 3, ptr %2, align 4
  br label %17

11:                                               ; preds = %1
  store i32 4, ptr %2, align 4
  br label %17

12:                                               ; preds = %1
  store i32 4, ptr %2, align 4
  br label %17

13:                                               ; preds = %1
  store i32 0, ptr %2, align 4
  br label %17

14:                                               ; preds = %1
  store i32 5, ptr %2, align 4
  br label %17

15:                                               ; preds = %1
  store i32 0, ptr %2, align 4
  br label %17

16:                                               ; preds = %1
  store i32 0, ptr %2, align 4
  br label %17

17:                                               ; preds = %16, %15, %14, %13, %12, %11, %10, %9, %8, %7
  %18 = load i32, ptr %2, align 4
  ret i32 %18
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !15, i64 32}
!10 = !{!"_ZTS12TfLiteTensor", !11, i64 0, !7, i64 8, !6, i64 16, !12, i64 24, !15, i64 32, !16, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !14, i64 72, !17, i64 76, !17, i64 77, !18, i64 80, !6, i64 96, !6, i64 104}
!11 = !{!"_ZTS10TfLiteType", !7, i64 0}
!12 = !{!"_ZTS24TfLiteQuantizationParams", !13, i64 0, !14, i64 4}
!13 = !{!"float", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTS20TfLiteAllocationType", !7, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!"bool", !7, i64 0}
!18 = !{!"_ZTS18TfLiteQuantization", !19, i64 0, !6, i64 8}
!19 = !{!"_ZTS22TfLiteQuantizationType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.TfLiteTensorGetAllocationStrategy = private unnamed_addr constant [9 x i32] [i32 1, i32 2, i32 3, i32 3, i32 4, i32 4, i32 0, i32 5, i32 0], align 4

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable
define dso_local range(i32 0, 6) i32 @TfLiteTensorGetAllocationStrategy(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 32
  %3 = load i32, ptr %2, align 8, !tbaa !5
  %4 = icmp ult i32 %3, 9
  br i1 %4, label %switch.lookup, label %6

switch.lookup:                                    ; preds = %1
  %5 = zext nneg i32 %3 to i64
  %switch.gep = getelementptr inbounds [9 x i32], ptr @switch.table.TfLiteTensorGetAllocationStrategy, i64 0, i64 %5
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %6

6:                                                ; preds = %1, %switch.lookup
  %.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %1 ]
  ret i32 %.0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 32}
!6 = !{!"_ZTS12TfLiteTensor", !7, i64 0, !8, i64 8, !10, i64 16, !11, i64 24, !14, i64 32, !15, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !13, i64 72, !16, i64 76, !16, i64 77, !17, i64 80, !10, i64 96, !10, i64 104}
!7 = !{!"_ZTS10TfLiteType", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!"_ZTS24TfLiteQuantizationParams", !12, i64 0, !13, i64 4}
!12 = !{!"float", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!"_ZTS20TfLiteAllocationType", !8, i64 0}
!15 = !{!"long", !8, i64 0}
!16 = !{!"bool", !8, i64 0}
!17 = !{!"_ZTS18TfLiteQuantization", !18, i64 0, !10, i64 8}
!18 = !{!"_ZTS22TfLiteQuantizationType", !8, i64 0}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass