; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl8_xl_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_lp2_bandwidth_get(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %struct.lsm6dsl_ctrl8_xl_t, align 1
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = call i32 @lsm6dsl_read_reg(ptr noundef %7, i8 noundef zeroext 23, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %8, ptr %6, align 4, !tbaa !9
  %9 = load i32, ptr %6, align 4, !tbaa !9
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %11, label %55

11:                                               ; preds = %2
  %12 = load i8, ptr %5, align 1
  %13 = lshr i8 %12, 7
  %14 = zext i8 %13 to i32
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %22, label %16

16:                                               ; preds = %11
  %17 = load i8, ptr %5, align 1
  %18 = lshr i8 %17, 2
  %19 = and i8 %18, 1
  %20 = zext i8 %19 to i32
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %24

22:                                               ; preds = %16, %11
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 32, ptr %23, align 4, !tbaa !9
  br label %54

24:                                               ; preds = %16
  %25 = load i8, ptr %5, align 1
  %26 = lshr i8 %25, 3
  %27 = and i8 %26, 1
  %28 = zext i8 %27 to i32
  %29 = shl i32 %28, 4
  %30 = load i8, ptr %5, align 1
  %31 = lshr i8 %30, 5
  %32 = and i8 %31, 3
  %33 = zext i8 %32 to i32
  %34 = add nsw i32 %29, %33
  switch i32 %34, label %51 [
    i32 0, label %35
    i32 1, label %37
    i32 2, label %39
    i32 3, label %41
    i32 16, label %43
    i32 17, label %45
    i32 18, label %47
    i32 19, label %49
  ]

35:                                               ; preds = %24
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 0, ptr %36, align 4, !tbaa !9
  br label %53

37:                                               ; preds = %24
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 1, ptr %38, align 4, !tbaa !9
  br label %53

39:                                               ; preds = %24
  %40 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 2, ptr %40, align 4, !tbaa !9
  br label %53

41:                                               ; preds = %24
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 3, ptr %42, align 4, !tbaa !9
  br label %53

43:                                               ; preds = %24
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 16, ptr %44, align 4, !tbaa !9
  br label %53

45:                                               ; preds = %24
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 17, ptr %46, align 4, !tbaa !9
  br label %53

47:                                               ; preds = %24
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 18, ptr %48, align 4, !tbaa !9
  br label %53

49:                                               ; preds = %24
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 19, ptr %50, align 4, !tbaa !9
  br label %53

51:                                               ; preds = %24
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 32, ptr %52, align 4, !tbaa !9
  br label %53

53:                                               ; preds = %51, %49, %47, %45, %43, %41, %39, %37, %35
  br label %54

54:                                               ; preds = %53, %22
  br label %55

55:                                               ; preds = %54, %2
  %56 = load i32, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %56
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl8_xl_t = type { i8 }

@switch.table.lsm6dsl_xl_lp2_bandwidth_get = private unnamed_addr constant [20 x i32] [i32 0, i32 1, i32 2, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 17, i32 18, i32 19], align 4

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_lp2_bandwidth_get(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_ctrl8_xl_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  %4 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 23, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %5 = icmp eq i32 %4, 0
  br i1 %5, label %6, label %15

6:                                                ; preds = %2
  %7 = load i8, ptr %3, align 1
  %8 = and i8 %7, -124
  %or.cond = icmp eq i8 %8, -128
  br i1 %or.cond, label %switch.lookup, label %.sink.split

switch.lookup:                                    ; preds = %6
  %9 = shl i8 %7, 1
  %10 = and i8 %9, 16
  %11 = lshr i8 %7, 5
  %12 = and i8 %11, 3
  %13 = or disjoint i8 %10, %12
  %14 = zext nneg i8 %13 to i64
  %switch.gep = getelementptr inbounds [20 x i32], ptr @switch.table.lsm6dsl_xl_lp2_bandwidth_get, i64 0, i64 %14
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %.sink.split

.sink.split:                                      ; preds = %switch.lookup, %6
  %.sink = phi i32 [ 32, %6 ], [ %switch.load, %switch.lookup ]
  store i32 %.sink, ptr %1, align 4, !tbaa !5
  br label %15

15:                                               ; preds = %.sink.split, %2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %4
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass