; LLVM IR from IOsonata/IOsonata :: ARM/Nordic/nRF52/nRF52840/exemples/BoschAppBoard/src (bmi3)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.bmi3_int_pin_config = type { i8, i8, [2 x %struct.bmi3_int_pin_cfg] }
%struct.bmi3_int_pin_cfg = type { i8, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_int_pin_config(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca [3 x i8], align 1
  %7 = alloca i8, align 1
  %8 = alloca i16, align 2
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 3, ptr %6) #3
  call void @llvm.memset.p0.i64(ptr align 1 %6, i8 0, i64 3, i1 false)
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  store i8 0, ptr %7, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #3
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = icmp ne ptr %9, null
  br i1 %10, label %11, label %98

11:                                               ; preds = %2
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %12, i32 0, i32 0
  %14 = load i8, ptr %13, align 1, !tbaa !10
  store i8 %14, ptr %7, align 1, !tbaa !9
  %15 = getelementptr inbounds [3 x i8], ptr %6, i64 0, i64 0
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 56, ptr noundef %15, i16 noundef zeroext 3, ptr noundef %16)
  store i8 %17, ptr %5, align 1, !tbaa !9
  %18 = load i8, ptr %5, align 1, !tbaa !9
  %19 = sext i8 %18 to i32
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %97

21:                                               ; preds = %11
  %22 = load i8, ptr %7, align 1, !tbaa !9
  %23 = zext i8 %22 to i32
  %24 = icmp eq i32 %23, 1
  br i1 %24, label %25, label %55

25:                                               ; preds = %21
  %26 = getelementptr inbounds [3 x i8], ptr %6, i64 0, i64 0
  %27 = load i8, ptr %26, align 1, !tbaa !9
  %28 = zext i8 %27 to i32
  %29 = and i32 %28, 1
  %30 = trunc i32 %29 to i8
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %31, i32 0, i32 2
  %33 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %32, i64 0, i64 0
  %34 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %33, i32 0, i32 0
  store i8 %30, ptr %34, align 1, !tbaa !12
  %35 = getelementptr inbounds [3 x i8], ptr %6, i64 0, i64 0
  %36 = load i8, ptr %35, align 1, !tbaa !9
  %37 = zext i8 %36 to i32
  %38 = and i32 %37, 2
  %39 = ashr i32 %38, 1
  %40 = trunc i32 %39 to i8
  %41 = load ptr, ptr %3, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %41, i32 0, i32 2
  %43 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %42, i64 0, i64 0
  %44 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %43, i32 0, i32 1
  store i8 %40, ptr %44, align 1, !tbaa !14
  %45 = getelementptr inbounds [3 x i8], ptr %6, i64 0, i64 0
  %46 = load i8, ptr %45, align 1, !tbaa !9
  %47 = zext i8 %46 to i32
  %48 = and i32 %47, 4
  %49 = ashr i32 %48, 2
  %50 = trunc i32 %49 to i8
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %51, i32 0, i32 2
  %53 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %52, i64 0, i64 0
  %54 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %53, i32 0, i32 2
  store i8 %50, ptr %54, align 1, !tbaa !15
  br label %55

55:                                               ; preds = %25, %21
  %56 = load i8, ptr %7, align 1, !tbaa !9
  %57 = zext i8 %56 to i32
  %58 = icmp eq i32 %57, 2
  br i1 %58, label %59, label %93

59:                                               ; preds = %55
  %60 = getelementptr inbounds [3 x i8], ptr %6, i64 0, i64 1
  %61 = load i8, ptr %60, align 1, !tbaa !9
  %62 = zext i8 %61 to i16
  %63 = zext i16 %62 to i32
  %64 = shl i32 %63, 8
  %65 = trunc i32 %64 to i16
  store i16 %65, ptr %8, align 2, !tbaa !16
  %66 = load i16, ptr %8, align 2, !tbaa !16
  %67 = zext i16 %66 to i32
  %68 = and i32 %67, 256
  %69 = ashr i32 %68, 8
  %70 = trunc i32 %69 to i8
  %71 = load ptr, ptr %3, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %71, i32 0, i32 2
  %73 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %72, i64 0, i64 1
  %74 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %73, i32 0, i32 0
  store i8 %70, ptr %74, align 1, !tbaa !12
  %75 = load i16, ptr %8, align 2, !tbaa !16
  %76 = zext i16 %75 to i32
  %77 = and i32 %76, 512
  %78 = ashr i32 %77, 9
  %79 = trunc i32 %78 to i8
  %80 = load ptr, ptr %3, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %80, i32 0, i32 2
  %82 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %81, i64 0, i64 1
  %83 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %82, i32 0, i32 1
  store i8 %79, ptr %83, align 1, !tbaa !14
  %84 = load i16, ptr %8, align 2, !tbaa !16
  %85 = zext i16 %84 to i32
  %86 = and i32 %85, 1024
  %87 = ashr i32 %86, 10
  %88 = trunc i32 %87 to i8
  %89 = load ptr, ptr %3, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.bmi3_int_pin_config, ptr %89, i32 0, i32 2
  %91 = getelementptr inbounds [2 x %struct.bmi3_int_pin_cfg], ptr %90, i64 0, i64 1
  %92 = getelementptr inbounds %struct.bmi3_int_pin_cfg, ptr %91, i32 0, i32 2
  store i8 %88, ptr %92, align 1, !tbaa !15
  br label %93

93:                                               ; preds = %59, %55
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = load ptr, ptr %4, align 8, !tbaa !5
  %96 = call signext i8 @get_latch_mode(ptr noundef %94, ptr noundef %95)
  store i8 %96, ptr %5, align 1, !tbaa !9
  br label %97

97:                                               ; preds = %93, %11
  br label %99

98:                                               ; preds = %2
  store i8 -1, ptr %5, align 1, !tbaa !9
  br label %99

99:                                               ; preds = %98, %97
  %100 = load i8, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 3, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  ret i8 %100
}

; Function Attrs: nounwind uwtable
declare hidden signext i8 @get_latch_mode(ptr noundef, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !7, i64 0}
!11 = !{!"bmi3_int_pin_config", !7, i64 0, !7, i64 1, !7, i64 2}
!12 = !{!13, !7, i64 0}
!13 = !{!"bmi3_int_pin_cfg", !7, i64 0, !7, i64 1, !7, i64 2}
!14 = !{!13, !7, i64 1}
!15 = !{!13, !7, i64 2}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_int_pin_config(ptr noundef %0, ptr noundef %1) local_unnamed_addr #2 {
  %3 = alloca [3 x i8], align 1
  call void @llvm.lifetime.start.p0(i64 3, ptr nonnull %3) #3
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(3) %3, i8 0, i64 3, i1 false)
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %24, label %4

4:                                                ; preds = %2
  %5 = load i8, ptr %0, align 1, !tbaa !5
  %6 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 56, ptr noundef nonnull %3, i16 noundef zeroext 3, ptr noundef %1)
  %7 = icmp eq i8 %6, 0
  br i1 %7, label %8, label %24

8:                                                ; preds = %4
  switch i8 %5, label %22 [
    i8 1, label %9
    i8 2, label %11
  ]

9:                                                ; preds = %8
  %10 = load i8, ptr %3, align 1, !tbaa !9
  br label %.sink.split

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %3, i64 1
  %13 = load i8, ptr %12, align 1, !tbaa !9
  br label %.sink.split

.sink.split:                                      ; preds = %11, %9
  %.sink29 = phi i8 [ %10, %9 ], [ %13, %11 ]
  %.sink28 = phi i64 [ 2, %9 ], [ 5, %11 ]
  %.sink23 = phi i64 [ 3, %9 ], [ 6, %11 ]
  %.sink19 = phi i64 [ 4, %9 ], [ 7, %11 ]
  %14 = and i8 %.sink29, 1
  %15 = getelementptr inbounds i8, ptr %0, i64 %.sink28
  store i8 %14, ptr %15, align 1, !tbaa !10
  %16 = lshr i8 %.sink29, 1
  %17 = and i8 %16, 1
  %18 = getelementptr inbounds i8, ptr %0, i64 %.sink23
  store i8 %17, ptr %18, align 1, !tbaa !12
  %19 = lshr i8 %.sink29, 2
  %20 = and i8 %19, 1
  %21 = getelementptr inbounds i8, ptr %0, i64 %.sink19
  store i8 %20, ptr %21, align 1, !tbaa !13
  br label %22

22:                                               ; preds = %.sink.split, %8
  %23 = call signext i8 @get_latch_mode(ptr noundef nonnull %0, ptr noundef %1)
  br label %24

24:                                               ; preds = %2, %4, %22
  %.0 = phi i8 [ %23, %22 ], [ %6, %4 ], [ -1, %2 ]
  call void @llvm.lifetime.end.p0(i64 3, ptr nonnull %3) #3
  ret i8 %.0
}

; Function Attrs: nounwind uwtable
declare hidden signext i8 @get_latch_mode(ptr noundef, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"bmi3_int_pin_config", !7, i64 0, !7, i64 1, !7, i64 2}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !7, i64 0}
!11 = !{!"bmi3_int_pin_cfg", !7, i64 0, !7, i64 1, !7, i64 2}
!12 = !{!11, !7, i64 1}
!13 = !{!11, !7, i64 2}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass