; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_master_config_t = type { i8 }
%struct.lsm6dsl_ctrl10_c_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_mag_hard_iron_set(ptr noundef %0, i8 noundef zeroext %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca %struct.lsm6dsl_master_config_t, align 1
  %6 = alloca %struct.lsm6dsl_ctrl10_c_t, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call i32 @lsm6dsl_read_reg(ptr noundef %8, i8 noundef zeroext 26, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %9, ptr %7, align 4, !tbaa !10
  %10 = load i32, ptr %7, align 4, !tbaa !10
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %44

12:                                               ; preds = %2
  %13 = load i8, ptr %4, align 1, !tbaa !9
  %14 = load i8, ptr %5, align 1
  %15 = and i8 %13, 1
  %16 = shl i8 %15, 1
  %17 = and i8 %14, -3
  %18 = or i8 %17, %16
  store i8 %18, ptr %5, align 1
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = call i32 @lsm6dsl_write_reg(ptr noundef %19, i8 noundef zeroext 26, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %20, ptr %7, align 4, !tbaa !10
  %21 = load i32, ptr %7, align 4, !tbaa !10
  %22 = icmp eq i32 %21, 0
  br i1 %22, label %23, label %43

23:                                               ; preds = %12
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = call i32 @lsm6dsl_read_reg(ptr noundef %24, i8 noundef zeroext 25, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %25, ptr %7, align 4, !tbaa !10
  %26 = load i32, ptr %7, align 4, !tbaa !10
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %42

28:                                               ; preds = %23
  %29 = load i8, ptr %4, align 1, !tbaa !9
  %30 = zext i8 %29 to i32
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %39

32:                                               ; preds = %28
  %33 = load i8, ptr %4, align 1, !tbaa !9
  %34 = load i8, ptr %6, align 1
  %35 = and i8 %33, 1
  %36 = shl i8 %35, 2
  %37 = and i8 %34, -5
  %38 = or i8 %37, %36
  store i8 %38, ptr %6, align 1
  br label %39

39:                                               ; preds = %32, %28
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = call i32 @lsm6dsl_write_reg(ptr noundef %40, i8 noundef zeroext 25, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %41, ptr %7, align 4, !tbaa !10
  br label %42

42:                                               ; preds = %39, %23
  br label %43

43:                                               ; preds = %42, %12
  br label %44

44:                                               ; preds = %43, %2
  %45 = load i32, ptr %7, align 4, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %45
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_master_config_t = type { i8 }
%struct.lsm6dsl_ctrl10_c_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_mag_hard_iron_set(ptr noundef %0, i8 noundef zeroext %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_master_config_t, align 1
  %4 = alloca %struct.lsm6dsl_ctrl10_c_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  %5 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 26, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %7, label %26

7:                                                ; preds = %2
  %8 = load i8, ptr %3, align 1
  %9 = and i8 %1, 1
  %10 = shl nuw nsw i8 %9, 1
  %11 = and i8 %8, -3
  %12 = or disjoint i8 %11, %10
  store i8 %12, ptr %3, align 1
  %13 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 26, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %14 = icmp eq i32 %13, 0
  br i1 %14, label %15, label %26

15:                                               ; preds = %7
  %16 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 25, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %26

18:                                               ; preds = %15
  %.not = icmp eq i8 %1, 0
  br i1 %.not, label %24, label %19

19:                                               ; preds = %18
  %20 = load i8, ptr %4, align 1
  %21 = shl nuw nsw i8 %9, 2
  %22 = and i8 %20, -5
  %23 = or disjoint i8 %22, %21
  store i8 %23, ptr %4, align 1
  br label %24

24:                                               ; preds = %19, %18
  %25 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 25, ptr noundef nonnull %4, i16 noundef zeroext 1)
  br label %26

26:                                               ; preds = %7, %24, %15, %2
  %.0 = phi i32 [ %25, %24 ], [ %16, %15 ], [ %13, %7 ], [ %5, %2 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass