; LLVM IR from zsiciarz/aquila :: aquila/source/generator/SquareGenerator.ll (ZN6Aquila15SquareGenerator8generateEm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Aquila::SignalSource" = type { ptr, %"class.std::vector", double }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.Aquila::Generator" = type { %"class.Aquila::SignalSource", double, double, double }
%"class.Aquila::SquareGenerator" = type { %"class.Aquila::Generator", double }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6Aquila15SquareGenerator8generateEm(ptr noundef nonnull align 8 dereferenceable(72) %0, i64 noundef %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !9
  %9 = load ptr, ptr %3, align 8
  %10 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %9, i32 0, i32 1
  %11 = load i64, ptr %4, align 8, !tbaa !9
  call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %11)
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  %12 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %9, i32 0, i32 2
  %13 = load double, ptr %12, align 8, !tbaa !11
  %14 = getelementptr inbounds %"class.Aquila::Generator", ptr %9, i32 0, i32 1
  %15 = load double, ptr %14, align 8, !tbaa !18
  %16 = fdiv double %13, %15
  %17 = fptoui double %16 to i64
  store i64 %17, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %18 = getelementptr inbounds %"class.Aquila::SquareGenerator", ptr %9, i32 0, i32 1
  %19 = load double, ptr %18, align 8, !tbaa !20
  %20 = load i64, ptr %5, align 8, !tbaa !9
  %21 = uitofp i64 %20 to double
  %22 = fmul double %19, %21
  %23 = fptoui double %22 to i64
  store i64 %23, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store i64 0, ptr %7, align 8, !tbaa !9
  br label %24

24:                                               ; preds = %45, %2
  %25 = load i64, ptr %7, align 8, !tbaa !9
  %26 = load i64, ptr %4, align 8, !tbaa !9
  %27 = icmp ult i64 %25, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  br label %48

29:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  %30 = load i64, ptr %7, align 8, !tbaa !9
  %31 = load i64, ptr %5, align 8, !tbaa !9
  %32 = urem i64 %30, %31
  store i64 %32, ptr %8, align 8, !tbaa !9
  %33 = getelementptr inbounds %"class.Aquila::Generator", ptr %9, i32 0, i32 2
  %34 = load double, ptr %33, align 8, !tbaa !22
  %35 = load i64, ptr %8, align 8, !tbaa !9
  %36 = load i64, ptr %6, align 8, !tbaa !9
  %37 = icmp ult i64 %35, %36
  %38 = zext i1 %37 to i64
  %39 = select i1 %37, i32 1, i32 -1
  %40 = sitofp i32 %39 to double
  %41 = fmul double %34, %40
  %42 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %9, i32 0, i32 1
  %43 = load i64, ptr %7, align 8, !tbaa !9
  %44 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %43) #3
  store double %41, ptr %44, align 8, !tbaa !23
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  br label %45

45:                                               ; preds = %29
  %46 = load i64, ptr %7, align 8, !tbaa !9
  %47 = add i64 %46, 1
  store i64 %47, ptr %7, align 8, !tbaa !9
  br label %24, !llvm.loop !24

48:                                               ; preds = %28
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !17, i64 32}
!12 = !{!"_ZTSN6Aquila12SignalSourceE", !13, i64 8, !17, i64 32}
!13 = !{!"_ZTSSt6vectorIdSaIdEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"double", !7, i64 0}
!18 = !{!19, !17, i64 40}
!19 = !{!"_ZTSN6Aquila9GeneratorE", !12, i64 0, !17, i64 40, !17, i64 48, !17, i64 56}
!20 = !{!21, !17, i64 64}
!21 = !{!"_ZTSN6Aquila15SquareGeneratorE", !19, i64 0, !17, i64 64}
!22 = !{!19, !17, i64 48}
!23 = !{!17, !17, i64 0}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6Aquila15SquareGenerator8generateEm(ptr noundef nonnull align 8 dereferenceable(72) %0, i64 noundef %1) unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %1)
  %4 = getelementptr inbounds i8, ptr %0, i64 32
  %5 = load double, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 40
  %7 = load double, ptr %6, align 8, !tbaa !15
  %8 = fdiv double %5, %7
  %9 = fptoui double %8 to i64
  %10 = getelementptr inbounds i8, ptr %0, i64 64
  %11 = load double, ptr %10, align 8, !tbaa !17
  %12 = uitofp i64 %9 to double
  %13 = fmul double %11, %12
  %14 = fptoui double %13 to i64
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %15 = getelementptr inbounds i8, ptr %0, i64 48
  br label %16

._crit_edge:                                      ; preds = %16, %2
  ret void

16:                                               ; preds = %.lr.ph, %16
  %.010 = phi i64 [ 0, %.lr.ph ], [ %23, %16 ]
  %17 = urem i64 %.010, %9
  %18 = load double, ptr %15, align 8, !tbaa !19
  %19 = icmp ult i64 %17, %14
  %20 = fneg double %18
  %21 = select i1 %19, double %18, double %20
  %22 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %.010) #2
  store double %21, ptr %22, align 8, !tbaa !20
  %23 = add nuw i64 %.010, 1
  %exitcond.not = icmp eq i64 %23, %1
  br i1 %exitcond.not, label %._crit_edge, label %16, !llvm.loop !21
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 32}
!6 = !{!"_ZTSN6Aquila12SignalSourceE", !7, i64 8, !14, i64 32}
!7 = !{!"_ZTSSt6vectorIdSaIdEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"double", !12, i64 0}
!15 = !{!16, !14, i64 40}
!16 = !{!"_ZTSN6Aquila9GeneratorE", !6, i64 0, !14, i64 40, !14, i64 48, !14, i64 56}
!17 = !{!18, !14, i64 64}
!18 = !{!"_ZTSN6Aquila15SquareGeneratorE", !16, i64 0, !14, i64 64}
!19 = !{!16, !14, i64 48}
!20 = !{!14, !14, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass