; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl4_c_t = type { i8 }
%struct.lsm6dsl_ctrl6_c_t = type { i8 }
%struct.lsm6dsl_ctrl7_g_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_gy_band_pass_get(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %struct.lsm6dsl_ctrl4_c_t, align 1
  %6 = alloca %struct.lsm6dsl_ctrl6_c_t, align 1
  %7 = alloca %struct.lsm6dsl_ctrl7_g_t, align 1
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = call i32 @lsm6dsl_read_reg(ptr noundef %9, i8 noundef zeroext 21, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %10, ptr %8, align 4, !tbaa !9
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = icmp eq i32 %11, 0
  br i1 %12, label %13, label %70

13:                                               ; preds = %2
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = call i32 @lsm6dsl_read_reg(ptr noundef %14, i8 noundef zeroext 19, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %15, ptr %8, align 4, !tbaa !9
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %69

18:                                               ; preds = %13
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = call i32 @lsm6dsl_read_reg(ptr noundef %19, i8 noundef zeroext 22, ptr noundef %7, i16 noundef zeroext 1)
  store i32 %20, ptr %8, align 4, !tbaa !9
  %21 = load i8, ptr %7, align 1
  %22 = lshr i8 %21, 6
  %23 = and i8 %22, 1
  %24 = zext i8 %23 to i32
  %25 = shl i32 %24, 7
  %26 = load i8, ptr %7, align 1
  %27 = lshr i8 %26, 4
  %28 = and i8 %27, 3
  %29 = zext i8 %28 to i32
  %30 = shl i32 %29, 4
  %31 = add nsw i32 %25, %30
  %32 = load i8, ptr %5, align 1
  %33 = lshr i8 %32, 1
  %34 = and i8 %33, 1
  %35 = zext i8 %34 to i32
  %36 = shl i32 %35, 3
  %37 = add nsw i32 %31, %36
  %38 = load i8, ptr %6, align 1
  %39 = and i8 %38, 3
  %40 = zext i8 %39 to i32
  %41 = add nsw i32 %37, %40
  switch i32 %41, label %66 [
    i32 128, label %42
    i32 144, label %44
    i32 160, label %46
    i32 176, label %48
    i32 10, label %50
    i32 9, label %52
    i32 8, label %54
    i32 11, label %56
    i32 138, label %58
    i32 153, label %60
    i32 168, label %62
    i32 187, label %64
  ]

42:                                               ; preds = %18
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 128, ptr %43, align 4, !tbaa !9
  br label %68

44:                                               ; preds = %18
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 144, ptr %45, align 4, !tbaa !9
  br label %68

46:                                               ; preds = %18
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 160, ptr %47, align 4, !tbaa !9
  br label %68

48:                                               ; preds = %18
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 176, ptr %49, align 4, !tbaa !9
  br label %68

50:                                               ; preds = %18
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 10, ptr %51, align 4, !tbaa !9
  br label %68

52:                                               ; preds = %18
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 9, ptr %53, align 4, !tbaa !9
  br label %68

54:                                               ; preds = %18
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 8, ptr %55, align 4, !tbaa !9
  br label %68

56:                                               ; preds = %18
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 11, ptr %57, align 4, !tbaa !9
  br label %68

58:                                               ; preds = %18
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 138, ptr %59, align 4, !tbaa !9
  br label %68

60:                                               ; preds = %18
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 153, ptr %61, align 4, !tbaa !9
  br label %68

62:                                               ; preds = %18
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 168, ptr %63, align 4, !tbaa !9
  br label %68

64:                                               ; preds = %18
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 187, ptr %65, align 4, !tbaa !9
  br label %68

66:                                               ; preds = %18
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 255, ptr %67, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %66, %64, %62, %60, %58, %56, %54, %52, %50, %48, %46, %44, %42
  br label %69

69:                                               ; preds = %68, %13
  br label %70

70:                                               ; preds = %69, %2
  %71 = load i32, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %71
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl4_c_t = type { i8 }
%struct.lsm6dsl_ctrl6_c_t = type { i8 }
%struct.lsm6dsl_ctrl7_g_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_gy_band_pass_get(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_ctrl4_c_t, align 1
  %4 = alloca %struct.lsm6dsl_ctrl6_c_t, align 1
  %5 = alloca %struct.lsm6dsl_ctrl7_g_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  %6 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 21, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %8, label %37

8:                                                ; preds = %2
  %9 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 19, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %11, label %37

11:                                               ; preds = %8
  %12 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 22, ptr noundef nonnull %5, i16 noundef zeroext 1)
  %13 = load i8, ptr %5, align 1
  %14 = shl i8 %13, 1
  %15 = and i8 %14, -128
  %16 = and i8 %13, 48
  %17 = or disjoint i8 %15, %16
  %18 = load i8, ptr %3, align 1
  %19 = shl i8 %18, 2
  %20 = and i8 %19, 8
  %21 = or disjoint i8 %17, %20
  %22 = load i8, ptr %4, align 1
  %23 = and i8 %22, 3
  %24 = or disjoint i8 %21, %23
  switch i8 %24, label %36 [
    i8 -128, label %.sink.split
    i8 -112, label %25
    i8 -96, label %26
    i8 -80, label %27
    i8 10, label %28
    i8 9, label %29
    i8 8, label %30
    i8 11, label %31
    i8 -118, label %32
    i8 -103, label %33
    i8 -88, label %34
    i8 -69, label %35
  ]

25:                                               ; preds = %11
  br label %.sink.split

26:                                               ; preds = %11
  br label %.sink.split

27:                                               ; preds = %11
  br label %.sink.split

28:                                               ; preds = %11
  br label %.sink.split

29:                                               ; preds = %11
  br label %.sink.split

30:                                               ; preds = %11
  br label %.sink.split

31:                                               ; preds = %11
  br label %.sink.split

32:                                               ; preds = %11
  br label %.sink.split

33:                                               ; preds = %11
  br label %.sink.split

34:                                               ; preds = %11
  br label %.sink.split

35:                                               ; preds = %11
  br label %.sink.split

36:                                               ; preds = %11
  br label %.sink.split

.sink.split:                                      ; preds = %11, %25, %26, %27, %28, %29, %30, %31, %32, %33, %34, %35, %36
  %.sink = phi i32 [ 255, %36 ], [ 187, %35 ], [ 168, %34 ], [ 153, %33 ], [ 138, %32 ], [ 11, %31 ], [ 8, %30 ], [ 9, %29 ], [ 10, %28 ], [ 176, %27 ], [ 160, %26 ], [ 144, %25 ], [ 128, %11 ]
  store i32 %.sink, ptr %1, align 4, !tbaa !5
  br label %37

37:                                               ; preds = %.sink.split, %8, %2
  %.0 = phi i32 [ %9, %8 ], [ %6, %2 ], [ %12, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass