; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_slave0_config_t = type { i8 }
%struct.lsm6dsl_slv0_add_t = type { i8 }
%struct.lsm6dsl_sh_cfg_read_t = type { i8, i8, i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_mem_bank_set(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_sh_slv0_cfg_read(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %struct.lsm6dsl_slave0_config_t, align 1
  %6 = alloca %struct.lsm6dsl_slv0_add_t, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call i32 @lsm6dsl_mem_bank_set(ptr noundef %8, i32 noundef 4)
  store i32 %9, ptr %7, align 4, !tbaa !9
  %10 = load i32, ptr %7, align 4, !tbaa !9
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %59

12:                                               ; preds = %2
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.lsm6dsl_sh_cfg_read_t, ptr %13, i32 0, i32 0
  %15 = load i8, ptr %14, align 1, !tbaa !11
  %16 = load i8, ptr %6, align 1
  %17 = and i8 %15, 127
  %18 = shl i8 %17, 1
  %19 = and i8 %16, 1
  %20 = or i8 %19, %18
  store i8 %20, ptr %6, align 1
  %21 = load i8, ptr %6, align 1
  %22 = and i8 %21, -2
  %23 = or i8 %22, 1
  store i8 %23, ptr %6, align 1
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = call i32 @lsm6dsl_write_reg(ptr noundef %24, i8 noundef zeroext 2, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %25, ptr %7, align 4, !tbaa !9
  %26 = load i32, ptr %7, align 4, !tbaa !9
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %58

28:                                               ; preds = %12
  %29 = load ptr, ptr %3, align 8, !tbaa !5
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.lsm6dsl_sh_cfg_read_t, ptr %30, i32 0, i32 1
  %32 = call i32 @lsm6dsl_write_reg(ptr noundef %29, i8 noundef zeroext 3, ptr noundef %31, i16 noundef zeroext 1)
  store i32 %32, ptr %7, align 4, !tbaa !9
  %33 = load i32, ptr %7, align 4, !tbaa !9
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %35, label %57

35:                                               ; preds = %28
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = call i32 @lsm6dsl_read_reg(ptr noundef %36, i8 noundef zeroext 4, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %37, ptr %7, align 4, !tbaa !9
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.lsm6dsl_sh_cfg_read_t, ptr %38, i32 0, i32 2
  %40 = load i8, ptr %39, align 1, !tbaa !13
  %41 = load i8, ptr %5, align 1
  %42 = and i8 %40, 7
  %43 = and i8 %41, -8
  %44 = or i8 %43, %42
  store i8 %44, ptr %5, align 1
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = icmp eq i32 %45, 0
  br i1 %46, label %47, label %56

47:                                               ; preds = %35
  %48 = load ptr, ptr %3, align 8, !tbaa !5
  %49 = call i32 @lsm6dsl_write_reg(ptr noundef %48, i8 noundef zeroext 4, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %49, ptr %7, align 4, !tbaa !9
  %50 = load i32, ptr %7, align 4, !tbaa !9
  %51 = icmp eq i32 %50, 0
  br i1 %51, label %52, label %55

52:                                               ; preds = %47
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = call i32 @lsm6dsl_mem_bank_set(ptr noundef %53, i32 noundef 0)
  store i32 %54, ptr %7, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %52, %47
  br label %56

56:                                               ; preds = %55, %35
  br label %57

57:                                               ; preds = %56, %28
  br label %58

58:                                               ; preds = %57, %12
  br label %59

59:                                               ; preds = %58, %2
  %60 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %60
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 0}
!12 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2}
!13 = !{!12, !7, i64 2}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_slave0_config_t = type { i8 }
%struct.lsm6dsl_slv0_add_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_mem_bank_set(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_sh_slv0_cfg_read(ptr noundef %0, ptr noundef %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_slave0_config_t, align 1
  %4 = alloca %struct.lsm6dsl_slv0_add_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  %5 = tail call i32 @lsm6dsl_mem_bank_set(ptr noundef %0, i32 noundef 4)
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %7, label %31

7:                                                ; preds = %2
  %8 = load i8, ptr %1, align 1, !tbaa !5
  %9 = shl i8 %8, 1
  %10 = or disjoint i8 %9, 1
  store i8 %10, ptr %4, align 1
  %11 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 2, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %12 = icmp eq i32 %11, 0
  br i1 %12, label %13, label %31

13:                                               ; preds = %7
  %14 = getelementptr inbounds i8, ptr %1, i64 1
  %15 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 3, ptr noundef nonnull %14, i16 noundef zeroext 1)
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %31

17:                                               ; preds = %13
  %18 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 4, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %19 = getelementptr inbounds i8, ptr %1, i64 2
  %20 = load i8, ptr %19, align 1, !tbaa !9
  %21 = load i8, ptr %3, align 1
  %22 = and i8 %20, 7
  %23 = and i8 %21, -8
  %24 = or disjoint i8 %23, %22
  store i8 %24, ptr %3, align 1
  %25 = icmp eq i32 %18, 0
  br i1 %25, label %26, label %31

26:                                               ; preds = %17
  %27 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 4, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %29, label %31

29:                                               ; preds = %26
  %30 = call i32 @lsm6dsl_mem_bank_set(ptr noundef %0, i32 noundef 0)
  br label %31

31:                                               ; preds = %7, %17, %29, %26, %13, %2
  %.0 = phi i32 [ %30, %29 ], [ %27, %26 ], [ %18, %17 ], [ %15, %13 ], [ %11, %7 ], [ %5, %2 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!6, !7, i64 2}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass