; LLVM IR from zsiciarz/aquila :: aquila/source/generator/SineGenerator.ll (ZN6Aquila13SineGenerator8generateEm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Aquila::SignalSource" = type { ptr, %"class.std::vector", double }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.Aquila::Generator" = type { %"class.Aquila::SignalSource", double, double, double }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6Aquila13SineGenerator8generateEm(ptr noundef nonnull align 8 dereferenceable(64) %0, i64 noundef %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca double, align 8
  %6 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !9
  %7 = load ptr, ptr %3, align 8
  %8 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %7, i32 0, i32 1
  %9 = load i64, ptr %4, align 8, !tbaa !9
  call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %9)
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  %10 = getelementptr inbounds %"class.Aquila::Generator", ptr %7, i32 0, i32 1
  %11 = load double, ptr %10, align 8, !tbaa !11
  %12 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %7, i32 0, i32 2
  %13 = load double, ptr %12, align 8, !tbaa !19
  %14 = fdiv double %11, %13
  store double %14, ptr %5, align 8, !tbaa !20
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #5
  store i64 0, ptr %6, align 8, !tbaa !9
  br label %15

15:                                               ; preds = %37, %2
  %16 = load i64, ptr %6, align 8, !tbaa !9
  %17 = load i64, ptr %4, align 8, !tbaa !9
  %18 = icmp ult i64 %16, %17
  br i1 %18, label %20, label %19

19:                                               ; preds = %15
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #5
  br label %40

20:                                               ; preds = %15
  %21 = getelementptr inbounds %"class.Aquila::Generator", ptr %7, i32 0, i32 2
  %22 = load double, ptr %21, align 8, !tbaa !21
  %23 = load double, ptr %5, align 8, !tbaa !20
  %24 = fmul double 0x401921FB54442D18, %23
  %25 = load i64, ptr %6, align 8, !tbaa !9
  %26 = uitofp i64 %25 to double
  %27 = getelementptr inbounds %"class.Aquila::Generator", ptr %7, i32 0, i32 3
  %28 = load double, ptr %27, align 8, !tbaa !22
  %29 = fmul double %28, 2.000000e+00
  %30 = fmul double %29, 0x400921FB54442D18
  %31 = call double @llvm.fmuladd.f64(double %24, double %26, double %30)
  %32 = call double @sin(double noundef %31) #5
  %33 = fmul double %22, %32
  %34 = getelementptr inbounds %"class.Aquila::SignalSource", ptr %7, i32 0, i32 1
  %35 = load i64, ptr %6, align 8, !tbaa !9
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %35) #5
  store double %33, ptr %36, align 8, !tbaa !20
  br label %37

37:                                               ; preds = %20
  %38 = load i64, ptr %6, align 8, !tbaa !9
  %39 = add i64 %38, 1
  store i64 %39, ptr %6, align 8, !tbaa !9
  br label %15, !llvm.loop !23

40:                                               ; preds = %19
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare double @sin(double noundef) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #4 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !18, i64 40}
!12 = !{!"_ZTSN6Aquila9GeneratorE", !13, i64 0, !18, i64 40, !18, i64 48, !18, i64 56}
!13 = !{!"_ZTSN6Aquila12SignalSourceE", !14, i64 8, !18, i64 32}
!14 = !{!"_ZTSSt6vectorIdSaIdEE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"double", !7, i64 0}
!19 = !{!13, !18, i64 32}
!20 = !{!18, !18, i64 0}
!21 = !{!12, !18, i64 48}
!22 = !{!12, !18, i64 56}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6Aquila13SineGenerator8generateEm(ptr noundef nonnull align 8 dereferenceable(64) %0, i64 noundef %1) unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %1)
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %4 = getelementptr inbounds i8, ptr %0, i64 40
  %5 = load double, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 32
  %7 = load double, ptr %6, align 8, !tbaa !16
  %8 = fdiv double %5, %7
  %9 = getelementptr inbounds i8, ptr %0, i64 48
  %10 = fmul double %8, 0x401921FB54442D18
  %11 = getelementptr inbounds i8, ptr %0, i64 56
  br label %12

._crit_edge:                                      ; preds = %12, %2
  ret void

12:                                               ; preds = %.lr.ph, %12
  %.07 = phi i64 [ 0, %.lr.ph ], [ %22, %12 ]
  %13 = load double, ptr %9, align 8, !tbaa !17
  %14 = uitofp i64 %.07 to double
  %15 = load double, ptr %11, align 8, !tbaa !18
  %16 = fmul double %15, 2.000000e+00
  %17 = fmul double %16, 0x400921FB54442D18
  %18 = tail call double @llvm.fmuladd.f64(double %10, double %14, double %17)
  %19 = tail call double @sin(double noundef %18) #4
  %20 = fmul double %13, %19
  %21 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %.07) #4
  store double %20, ptr %21, align 8, !tbaa !19
  %22 = add nuw i64 %.07, 1
  %exitcond.not = icmp eq i64 %22, %1
  br i1 %exitcond.not, label %._crit_edge, label %12, !llvm.loop !20
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @sin(double noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 40}
!6 = !{!"_ZTSN6Aquila9GeneratorE", !7, i64 0, !15, i64 40, !15, i64 48, !15, i64 56}
!7 = !{!"_ZTSN6Aquila12SignalSourceE", !8, i64 8, !15, i64 32}
!8 = !{!"_ZTSSt6vectorIdSaIdEE", !9, i64 0}
!9 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !11, i64 0}
!11 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!12 = !{!"any pointer", !13, i64 0}
!13 = !{!"omnipotent char", !14, i64 0}
!14 = !{!"Simple C++ TBAA"}
!15 = !{!"double", !13, i64 0}
!16 = !{!7, !15, i64 32}
!17 = !{!6, !15, i64 48}
!18 = !{!6, !15, i64 56}
!19 = !{!15, !15, i64 0}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass