; LLVM IR from IOsonata/IOsonata :: ARM/Nordic/nRF52/nRF52840/exemples/BoschAppBoard/src (bmi3)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.bmi3_get_acc_gyr_off_gain_reset.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_acc_gyr_off_gain_reset(ptr noundef %0, ptr noundef %1, ptr noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca [2 x i8], align 1
  %9 = alloca [2 x i8], align 1
  %10 = alloca i8, align 1
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  %13 = alloca i16, align 2
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #4
  call void @llvm.memset.p0.i64(ptr align 1 %8, i8 0, i64 2, i1 false)
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %9, ptr align 1 @__const.bmi3_get_acc_gyr_off_gain_reset.base_addr, i64 2, i1 false)
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  store i8 0, ptr %10, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %13) #4
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %70

16:                                               ; preds = %3
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %70

19:                                               ; preds = %16
  %20 = getelementptr inbounds [2 x i8], ptr %9, i64 0, i64 0
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef %20, i16 noundef zeroext 2, ptr noundef %21)
  store i8 %22, ptr %7, align 1, !tbaa !9
  %23 = load i8, ptr %7, align 1, !tbaa !9
  %24 = sext i8 %23 to i32
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %69

26:                                               ; preds = %19
  %27 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 0
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 66, ptr noundef %27, i16 noundef zeroext 2, ptr noundef %28)
  store i8 %29, ptr %7, align 1, !tbaa !9
  %30 = load i8, ptr %7, align 1, !tbaa !9
  %31 = sext i8 %30 to i32
  %32 = icmp eq i32 %31, 0
  br i1 %32, label %33, label %68

33:                                               ; preds = %26
  %34 = load i8, ptr %10, align 1, !tbaa !9
  %35 = add i8 %34, 1
  store i8 %35, ptr %10, align 1, !tbaa !9
  %36 = zext i8 %34 to i64
  %37 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 %36
  %38 = load i8, ptr %37, align 1, !tbaa !9
  %39 = zext i8 %38 to i16
  store i16 %39, ptr %11, align 2, !tbaa !10
  %40 = load i8, ptr %10, align 1, !tbaa !9
  %41 = add i8 %40, 1
  store i8 %41, ptr %10, align 1, !tbaa !9
  %42 = zext i8 %40 to i64
  %43 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 %42
  %44 = load i8, ptr %43, align 1, !tbaa !9
  %45 = zext i8 %44 to i16
  %46 = zext i16 %45 to i32
  %47 = shl i32 %46, 8
  %48 = trunc i32 %47 to i16
  store i16 %48, ptr %12, align 2, !tbaa !10
  %49 = load i16, ptr %11, align 2, !tbaa !10
  %50 = zext i16 %49 to i32
  %51 = load i16, ptr %12, align 2, !tbaa !10
  %52 = zext i16 %51 to i32
  %53 = or i32 %50, %52
  %54 = trunc i32 %53 to i16
  store i16 %54, ptr %13, align 2, !tbaa !10
  %55 = load i16, ptr %13, align 2, !tbaa !10
  %56 = zext i16 %55 to i32
  %57 = and i32 %56, 1
  %58 = trunc i32 %57 to i8
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 %58, ptr %59, align 1, !tbaa !9
  %60 = load i16, ptr %13, align 2, !tbaa !10
  %61 = zext i16 %60 to i32
  %62 = and i32 %61, 2
  %63 = trunc i32 %62 to i8
  %64 = zext i8 %63 to i32
  %65 = ashr i32 %64, 1
  %66 = trunc i32 %65 to i8
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 %66, ptr %67, align 1, !tbaa !9
  br label %68

68:                                               ; preds = %33, %26
  br label %69

69:                                               ; preds = %68, %19
  br label %71

70:                                               ; preds = %16, %3
  store i8 -1, ptr %7, align 1, !tbaa !9
  br label %71

71:                                               ; preds = %70, %69
  %72 = load i8, ptr %7, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  ret i8 %72
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.bmi3_get_acc_gyr_off_gain_reset.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_acc_gyr_off_gain_reset(ptr noundef writeonly %0, ptr noundef writeonly %1, ptr noundef %2) local_unnamed_addr #1 {
  %4 = alloca [2 x i8], align 2
  %5 = alloca [2 x i8], align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %4) #2
  store i16 0, ptr %4, align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %5) #2
  %6 = load i16, ptr @__const.bmi3_get_acc_gyr_off_gain_reset.base_addr, align 1
  store i16 %6, ptr %5, align 2
  %7 = icmp ne ptr %0, null
  %8 = icmp ne ptr %1, null
  %or.cond = and i1 %7, %8
  br i1 %or.cond, label %9, label %20

9:                                                ; preds = %3
  %10 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef nonnull %5, i16 noundef zeroext 2, ptr noundef %2)
  %11 = icmp eq i8 %10, 0
  br i1 %11, label %12, label %20

12:                                               ; preds = %9
  %13 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 66, ptr noundef nonnull %4, i16 noundef zeroext 2, ptr noundef %2)
  %14 = icmp eq i8 %13, 0
  br i1 %14, label %15, label %20

15:                                               ; preds = %12
  %16 = load i8, ptr %4, align 2, !tbaa !5
  %17 = and i8 %16, 1
  store i8 %17, ptr %0, align 1, !tbaa !5
  %18 = lshr i8 %16, 1
  %19 = and i8 %18, 1
  store i8 %19, ptr %1, align 1, !tbaa !5
  br label %20

20:                                               ; preds = %3, %9, %15, %12
  %.0 = phi i8 [ 0, %15 ], [ %13, %12 ], [ %10, %9 ], [ -1, %3 ]
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %5) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %4) #2
  ret i8 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass