; LLVM IR from stan-dev/math :: lib/tbb_2020.3/src/test/test_reader_writer_lock.ll (Z30TestReaderWriterLockOnNThreadsi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Harness::internal::Tracer" = type <{ i32, [4 x i8], ptr, ptr, i64, [8 x i8] }>
%"struct.tbb::atomic.4" = type { %"struct.tbb::internal::atomic_impl_with_arithmetic.5" }
%"struct.tbb::internal::atomic_impl_with_arithmetic.5" = type { %"struct.tbb::internal::atomic_impl.6" }
%"struct.tbb::internal::atomic_impl.6" = type { %"struct.tbb::internal::aligned_storage.7" }
%"struct.tbb::internal::aligned_storage.7" = type { i64 }
%"struct.tbb::atomic.8" = type { %"struct.tbb::internal::atomic_impl.9" }
%"struct.tbb::internal::atomic_impl.9" = type { %"struct.tbb::internal::aligned_storage.10" }
%"struct.tbb::internal::aligned_storage.10" = type { i8 }
%struct.StressRWLBody = type { i32, i32 }
%"class.Harness::SpinBarrier" = type <{ i32, %"struct.tbb::atomic.11", %"struct.tbb::atomic.11", i8, [3 x i8] }>
%"struct.tbb::atomic.11" = type { %"struct.tbb::internal::atomic_impl_with_arithmetic.12" }
%"struct.tbb::internal::atomic_impl_with_arithmetic.12" = type { %"struct.tbb::internal::atomic_impl.13" }
%"struct.tbb::internal::atomic_impl.13" = type { %"struct.tbb::internal::aligned_storage.14" }
%"struct.tbb::internal::aligned_storage.14" = type { i32 }
%struct.CorrectRWLBody = type { i32, ptr }
%struct.CorrectRWLScopedBody = type { i32, ptr }

@_ZN7Harness8internalL6tracerE = external hidden global %"class.Harness::internal::Tracer", align 8
@active_readers = external dso_local global %"struct.tbb::atomic.4", align 8
@active_writers = external dso_local global %"struct.tbb::atomic.4", align 8
@sim_readers = external dso_local global %"struct.tbb::atomic.8", align 1
@n_tested__sim_readers = external dso_local global i64, align 8
@_ZL7Verbose = external hidden global i8, align 1
@.str.18 = external hidden unnamed_addr constant [99 x i8], align 1
@__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi = external hidden unnamed_addr constant [31 x i8], align 1
@.str.19 = external hidden unnamed_addr constant [51 x i8], align 1
@.str.20 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.21 = external hidden unnamed_addr constant [57 x i8], align 1
@.str.22 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.23 = external hidden unnamed_addr constant [36 x i8], align 1
@.str.24 = external hidden unnamed_addr constant [48 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33), i32 noundef, ptr noundef, i64 noundef, ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef, ...) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z11ReportErrorPKciS0_S0_(ptr noundef, i32 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z30TestReaderWriterLockOnNThreadsi(i32 noundef %0) #2 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca %struct.StressRWLBody, align 4
  %5 = alloca i32, align 4
  %6 = alloca %"class.Harness::SpinBarrier", align 4
  %7 = alloca %struct.CorrectRWLBody, align 8
  %8 = alloca i32, align 4
  %9 = alloca %"class.Harness::SpinBarrier", align 4
  %10 = alloca %struct.CorrectRWLScopedBody, align 8
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %11

11:                                               ; preds = %33, %1
  %12 = load i32, ptr %3, align 4, !tbaa !5
  %13 = icmp sle i32 %12, 100
  br i1 %13, label %15, label %14

14:                                               ; preds = %11
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %36

15:                                               ; preds = %11
  %16 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %17 = trunc i8 %16 to i1
  br i1 %17, label %19, label %18

18:                                               ; preds = %15
  br label %23

19:                                               ; preds = %15
  %20 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 178, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  %21 = load i32, ptr %2, align 4, !tbaa !5
  %22 = load i32, ptr %3, align 4, !tbaa !5
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %20, ptr noundef @.str.19, i32 noundef %21, i32 noundef %22)
  br label %23

23:                                               ; preds = %19, %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #3
  %24 = load i32, ptr %2, align 4, !tbaa !5
  %25 = load i32, ptr %3, align 4, !tbaa !5
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %4, i32 noundef %24, i32 noundef %25)
  %26 = load i32, ptr %2, align 4, !tbaa !5
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %26, ptr noundef nonnull align 4 dereferenceable(8) %4)
  %27 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %28 = trunc i8 %27 to i1
  br i1 %28, label %30, label %29

29:                                               ; preds = %23
  br label %32

30:                                               ; preds = %23
  %31 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 181, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %31, ptr noundef @.str.20)
  br label %32

32:                                               ; preds = %30, %29
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #3
  br label %33

33:                                               ; preds = %32
  %34 = load i32, ptr %3, align 4, !tbaa !5
  %35 = add nsw i32 %34, 20
  store i32 %35, ptr %3, align 4, !tbaa !5
  br label %11, !llvm.loop !13

36:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i64 0, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %37 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %38 = trunc i8 %37 to i1
  br i1 %38, label %40, label %39

39:                                               ; preds = %36
  br label %43

40:                                               ; preds = %36
  %41 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 186, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  %42 = load i32, ptr %2, align 4, !tbaa !5
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %41, ptr noundef @.str.21, i32 noundef %42)
  br label %43

43:                                               ; preds = %40, %39
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %44

44:                                               ; preds = %68, %43
  %45 = load i32, ptr %5, align 4, !tbaa !5
  %46 = icmp slt i32 %45, 100
  br i1 %46, label %47, label %71

47:                                               ; preds = %44
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #3
  %48 = load i32, ptr %2, align 4, !tbaa !5
  call void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13) %6, i32 noundef %48, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 16, ptr %7) #3
  %49 = load i32, ptr %2, align 4, !tbaa !5
  call void @_ZN14CorrectRWLBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16) %7, i32 noundef %49, ptr noundef nonnull align 4 dereferenceable(13) %6)
  %50 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_readers, i64 noundef 0)
  %51 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_writers, i64 noundef %50)
  %52 = call noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers, i1 noundef zeroext false)
  %53 = load i32, ptr %2, align 4, !tbaa !5
  call void @_Z17NativeParallelForIi14CorrectRWLBodyEvT_RKT0_(i32 noundef %53, ptr noundef nonnull align 8 dereferenceable(16) %7)
  %54 = call noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers)
  br i1 %54, label %58, label %55

55:                                               ; preds = %47
  %56 = load i32, ptr %2, align 4, !tbaa !5
  %57 = icmp eq i32 %56, 1
  br i1 %57, label %58, label %64

58:                                               ; preds = %55, %47
  %59 = load i64, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %60 = add i64 %59, 1
  store i64 %60, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %61 = icmp ugt i64 %60, 5
  br i1 %61, label %62, label %63

62:                                               ; preds = %58
  store i32 5, ptr %8, align 4
  br label %65

63:                                               ; preds = %58
  br label %64

64:                                               ; preds = %63, %55
  store i32 0, ptr %8, align 4
  br label %65

65:                                               ; preds = %64, %62
  call void @llvm.lifetime.end.p0(i64 16, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #3
  %66 = load i32, ptr %8, align 4
  switch i32 %66, label %129 [
    i32 0, label %67
    i32 5, label %71
  ]

67:                                               ; preds = %65
  br label %68

68:                                               ; preds = %67
  %69 = load i32, ptr %5, align 4, !tbaa !5
  %70 = add nsw i32 %69, 1
  store i32 %70, ptr %5, align 4, !tbaa !5
  br label %44, !llvm.loop !17

71:                                               ; preds = %65, %44
  %72 = load i32, ptr %5, align 4, !tbaa !5
  %73 = icmp slt i32 %72, 100
  br i1 %73, label %74, label %75

74:                                               ; preds = %71
  br label %76

75:                                               ; preds = %71
  call void @_Z11ReportErrorPKciS0_S0_(ptr noundef @.str.18, i32 noundef 201, ptr noundef @.str.22, ptr noundef @.str.23)
  br label %76

76:                                               ; preds = %75, %74
  %77 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %78 = trunc i8 %77 to i1
  br i1 %78, label %80, label %79

79:                                               ; preds = %76
  br label %82

80:                                               ; preds = %76
  %81 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 202, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %81, ptr noundef @.str.20)
  br label %82

82:                                               ; preds = %80, %79
  store i64 0, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %83 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %84 = trunc i8 %83 to i1
  br i1 %84, label %86, label %85

85:                                               ; preds = %82
  br label %89

86:                                               ; preds = %82
  %87 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 205, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  %88 = load i32, ptr %2, align 4, !tbaa !5
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %87, ptr noundef @.str.24, i32 noundef %88)
  br label %89

89:                                               ; preds = %86, %85
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %90

90:                                               ; preds = %114, %89
  %91 = load i32, ptr %5, align 4, !tbaa !5
  %92 = icmp slt i32 %91, 100
  br i1 %92, label %93, label %117

93:                                               ; preds = %90
  call void @llvm.lifetime.start.p0(i64 16, ptr %9) #3
  %94 = load i32, ptr %2, align 4, !tbaa !5
  call void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13) %9, i32 noundef %94, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 16, ptr %10) #3
  %95 = load i32, ptr %2, align 4, !tbaa !5
  call void @_ZN20CorrectRWLScopedBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16) %10, i32 noundef %95, ptr noundef nonnull align 4 dereferenceable(13) %9)
  %96 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_readers, i64 noundef 0)
  %97 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_writers, i64 noundef %96)
  %98 = call noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers, i1 noundef zeroext false)
  %99 = load i32, ptr %2, align 4, !tbaa !5
  call void @_Z17NativeParallelForIi20CorrectRWLScopedBodyEvT_RKT0_(i32 noundef %99, ptr noundef nonnull align 8 dereferenceable(16) %10)
  %100 = call noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers)
  br i1 %100, label %104, label %101

101:                                              ; preds = %93
  %102 = load i32, ptr %2, align 4, !tbaa !5
  %103 = icmp eq i32 %102, 1
  br i1 %103, label %104, label %110

104:                                              ; preds = %101, %93
  %105 = load i64, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %106 = add i64 %105, 1
  store i64 %106, ptr @n_tested__sim_readers, align 8, !tbaa !15
  %107 = icmp ugt i64 %106, 5
  br i1 %107, label %108, label %109

108:                                              ; preds = %104
  store i32 8, ptr %8, align 4
  br label %111

109:                                              ; preds = %104
  br label %110

110:                                              ; preds = %109, %101
  store i32 0, ptr %8, align 4
  br label %111

111:                                              ; preds = %110, %108
  call void @llvm.lifetime.end.p0(i64 16, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr %9) #3
  %112 = load i32, ptr %8, align 4
  switch i32 %112, label %129 [
    i32 0, label %113
    i32 8, label %117
  ]

113:                                              ; preds = %111
  br label %114

114:                                              ; preds = %113
  %115 = load i32, ptr %5, align 4, !tbaa !5
  %116 = add nsw i32 %115, 1
  store i32 %116, ptr %5, align 4, !tbaa !5
  br label %90, !llvm.loop !18

117:                                              ; preds = %111, %90
  %118 = load i32, ptr %5, align 4, !tbaa !5
  %119 = icmp slt i32 %118, 100
  br i1 %119, label %120, label %121

120:                                              ; preds = %117
  br label %122

121:                                              ; preds = %117
  call void @_Z11ReportErrorPKciS0_S0_(ptr noundef @.str.18, i32 noundef 217, ptr noundef @.str.22, ptr noundef @.str.23)
  br label %122

122:                                              ; preds = %121, %120
  %123 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !9, !range !11, !noundef !12
  %124 = trunc i8 %123 to i1
  br i1 %124, label %126, label %125

125:                                              ; preds = %122
  br label %128

126:                                              ; preds = %122
  %127 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef @.str.18, i64 noundef 218, ptr noundef @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %127, ptr noundef @.str.20)
  br label %128

128:                                              ; preds = %126, %125
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void

129:                                              ; preds = %111, %65
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(8)) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13), i32 noundef, i1 noundef zeroext) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN14CorrectRWLBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef, ptr noundef nonnull align 4 dereferenceable(13)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1), i1 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi14CorrectRWLBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 8 dereferenceable(16)) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN20CorrectRWLScopedBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef, ptr noundef nonnull align 4 dereferenceable(13)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi20CorrectRWLScopedBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 8 dereferenceable(16)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = !{!16, !16, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = distinct !{!17, !14}
!18 = distinct !{!18, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Harness::internal::Tracer" = type <{ i32, [4 x i8], ptr, ptr, i64, [8 x i8] }>
%"struct.tbb::atomic.4" = type { %"struct.tbb::internal::atomic_impl_with_arithmetic.5" }
%"struct.tbb::internal::atomic_impl_with_arithmetic.5" = type { %"struct.tbb::internal::atomic_impl.6" }
%"struct.tbb::internal::atomic_impl.6" = type { %"struct.tbb::internal::aligned_storage.7" }
%"struct.tbb::internal::aligned_storage.7" = type { i64 }
%"struct.tbb::atomic.8" = type { %"struct.tbb::internal::atomic_impl.9" }
%"struct.tbb::internal::atomic_impl.9" = type { %"struct.tbb::internal::aligned_storage.10" }
%"struct.tbb::internal::aligned_storage.10" = type { i8 }
%struct.StressRWLBody = type { i32, i32 }
%"class.Harness::SpinBarrier" = type <{ i32, %"struct.tbb::atomic.11", %"struct.tbb::atomic.11", i8, [3 x i8] }>
%"struct.tbb::atomic.11" = type { %"struct.tbb::internal::atomic_impl_with_arithmetic.12" }
%"struct.tbb::internal::atomic_impl_with_arithmetic.12" = type { %"struct.tbb::internal::atomic_impl.13" }
%"struct.tbb::internal::atomic_impl.13" = type { %"struct.tbb::internal::aligned_storage.14" }
%"struct.tbb::internal::aligned_storage.14" = type { i32 }
%struct.CorrectRWLBody = type { i32, ptr }
%struct.CorrectRWLScopedBody = type { i32, ptr }

@_ZN7Harness8internalL6tracerE = external hidden global %"class.Harness::internal::Tracer", align 8
@active_readers = external dso_local global %"struct.tbb::atomic.4", align 8
@active_writers = external dso_local global %"struct.tbb::atomic.4", align 8
@sim_readers = external dso_local global %"struct.tbb::atomic.8", align 1
@n_tested__sim_readers = external dso_local local_unnamed_addr global i64, align 8
@_ZL7Verbose = external hidden local_unnamed_addr global i8, align 1
@.str.18 = external hidden unnamed_addr constant [99 x i8], align 1
@__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi = external hidden unnamed_addr constant [31 x i8], align 1
@.str.19 = external hidden unnamed_addr constant [51 x i8], align 1
@.str.20 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.21 = external hidden unnamed_addr constant [57 x i8], align 1
@.str.22 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.23 = external hidden unnamed_addr constant [36 x i8], align 1
@.str.24 = external hidden unnamed_addr constant [48 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33), i32 noundef, ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33), ptr noundef, ...) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z11ReportErrorPKciS0_S0_(ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z30TestReaderWriterLockOnNThreadsi(i32 noundef %0) local_unnamed_addr #2 {
  %2 = alloca %struct.StressRWLBody, align 4
  %3 = alloca %"class.Harness::SpinBarrier", align 4
  %4 = alloca %struct.CorrectRWLBody, align 8
  %5 = alloca %"class.Harness::SpinBarrier", align 4
  %6 = alloca %struct.CorrectRWLScopedBody, align 8
  %7 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %8 = trunc nuw i8 %7 to i1
  br i1 %8, label %9, label %11

9:                                                ; preds = %1
  %10 = tail call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  tail call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %10, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 0)
  br label %11

11:                                               ; preds = %1, %9
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 0)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %12 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %13 = trunc nuw i8 %12 to i1
  br i1 %13, label %14, label %16

14:                                               ; preds = %11
  %15 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %15, ptr noundef nonnull @.str.20)
  %.pre = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %16

16:                                               ; preds = %11, %14
  %17 = phi i8 [ %12, %11 ], [ %.pre, %14 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %18 = trunc nuw i8 %17 to i1
  br i1 %18, label %19, label %21

19:                                               ; preds = %16
  %20 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %20, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 20)
  br label %21

21:                                               ; preds = %19, %16
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 20)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %22 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %23 = trunc nuw i8 %22 to i1
  br i1 %23, label %24, label %26

24:                                               ; preds = %21
  %25 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %25, ptr noundef nonnull @.str.20)
  %.pre49 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %26

26:                                               ; preds = %24, %21
  %27 = phi i8 [ %.pre49, %24 ], [ %22, %21 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %28 = trunc nuw i8 %27 to i1
  br i1 %28, label %29, label %31

29:                                               ; preds = %26
  %30 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %30, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 40)
  br label %31

31:                                               ; preds = %29, %26
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 40)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %32 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %33 = trunc nuw i8 %32 to i1
  br i1 %33, label %34, label %36

34:                                               ; preds = %31
  %35 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %35, ptr noundef nonnull @.str.20)
  %.pre50 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %36

36:                                               ; preds = %34, %31
  %37 = phi i8 [ %.pre50, %34 ], [ %32, %31 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %38 = trunc nuw i8 %37 to i1
  br i1 %38, label %39, label %41

39:                                               ; preds = %36
  %40 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %40, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 60)
  br label %41

41:                                               ; preds = %39, %36
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 60)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %42 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %43 = trunc nuw i8 %42 to i1
  br i1 %43, label %44, label %46

44:                                               ; preds = %41
  %45 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %45, ptr noundef nonnull @.str.20)
  %.pre51 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %46

46:                                               ; preds = %44, %41
  %47 = phi i8 [ %.pre51, %44 ], [ %42, %41 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %48 = trunc nuw i8 %47 to i1
  br i1 %48, label %49, label %51

49:                                               ; preds = %46
  %50 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %50, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 80)
  br label %51

51:                                               ; preds = %49, %46
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 80)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %52 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %53 = trunc nuw i8 %52 to i1
  br i1 %53, label %54, label %56

54:                                               ; preds = %51
  %55 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %55, ptr noundef nonnull @.str.20)
  %.pre52 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %56

56:                                               ; preds = %54, %51
  %57 = phi i8 [ %.pre52, %54 ], [ %52, %51 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %58 = trunc nuw i8 %57 to i1
  br i1 %58, label %59, label %61

59:                                               ; preds = %56
  %60 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 178, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %60, ptr noundef nonnull @.str.19, i32 noundef %0, i32 noundef 100)
  br label %61

61:                                               ; preds = %59, %56
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  call void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %0, i32 noundef 100)
  call void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(8) %2)
  %62 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %63 = trunc nuw i8 %62 to i1
  br i1 %63, label %64, label %66

64:                                               ; preds = %61
  %65 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 181, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %65, ptr noundef nonnull @.str.20)
  %.pre53 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %66

66:                                               ; preds = %64, %61
  %67 = phi i8 [ %.pre53, %64 ], [ %62, %61 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  store i64 0, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %68 = trunc nuw i8 %67 to i1
  br i1 %68, label %69, label %71

69:                                               ; preds = %66
  %70 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 186, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %70, ptr noundef nonnull @.str.21, i32 noundef %0)
  br label %71

71:                                               ; preds = %66, %69
  %72 = icmp eq i32 %0, 1
  br i1 %72, label %.split.us, label %.split

.split.us:                                        ; preds = %71, %80
  %.02841.us = phi i32 [ %81, %80 ], [ 0, %71 ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) #3
  call void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13) %3, i32 noundef 1, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #3
  call void @_ZN14CorrectRWLBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16) %4, i32 noundef 1, ptr noundef nonnull align 4 dereferenceable(13) %3)
  %73 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_readers, i64 noundef 0)
  %74 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_writers, i64 noundef %73)
  %75 = call noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers, i1 noundef zeroext false)
  call void @_Z17NativeParallelForIi14CorrectRWLBodyEvT_RKT0_(i32 noundef 1, ptr noundef nonnull align 8 dereferenceable(16) %4)
  %76 = call noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers)
  %77 = load i64, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %78 = add i64 %77, 1
  store i64 %78, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %79 = icmp ugt i64 %78, 5
  br i1 %79, label %.split43.us, label %80

80:                                               ; preds = %.split.us
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  %81 = add nuw nsw i32 %.02841.us, 1
  %exitcond47.not = icmp eq i32 %81, 100
  br i1 %exitcond47.not, label %.critedge, label %.split.us, !llvm.loop !13

.split:                                           ; preds = %71, %90
  %.02841 = phi i32 [ %91, %90 ], [ 0, %71 ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) #3
  call void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13) %3, i32 noundef %0, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #3
  call void @_ZN14CorrectRWLBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16) %4, i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(13) %3)
  %82 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_readers, i64 noundef 0)
  %83 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_writers, i64 noundef %82)
  %84 = call noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers, i1 noundef zeroext false)
  call void @_Z17NativeParallelForIi14CorrectRWLBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 8 dereferenceable(16) %4)
  %85 = call noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers)
  br i1 %85, label %86, label %90

86:                                               ; preds = %.split
  %87 = load i64, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %88 = add i64 %87, 1
  store i64 %88, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %89 = icmp ugt i64 %88, 5
  br i1 %89, label %.split43.us, label %90

90:                                               ; preds = %.split, %86
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  %91 = add nuw nsw i32 %.02841, 1
  %exitcond.not = icmp eq i32 %91, 100
  br i1 %exitcond.not, label %.critedge, label %.split, !llvm.loop !13

.split43.us:                                      ; preds = %86, %.split.us
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  br label %92

.critedge:                                        ; preds = %90, %80
  call void @_Z11ReportErrorPKciS0_S0_(ptr noundef nonnull @.str.18, i32 noundef 201, ptr noundef nonnull @.str.22, ptr noundef nonnull @.str.23)
  br label %92

92:                                               ; preds = %.split43.us, %.critedge
  %93 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %94 = trunc nuw i8 %93 to i1
  br i1 %94, label %95, label %97

95:                                               ; preds = %92
  %96 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 202, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %96, ptr noundef nonnull @.str.20)
  %.pre54 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9
  br label %97

97:                                               ; preds = %92, %95
  %98 = phi i8 [ %93, %92 ], [ %.pre54, %95 ]
  store i64 0, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %99 = trunc nuw i8 %98 to i1
  br i1 %99, label %100, label %.preheader

100:                                              ; preds = %97
  %101 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 205, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %101, ptr noundef nonnull @.str.24, i32 noundef %0)
  br label %.preheader

.preheader:                                       ; preds = %97, %100
  br label %102

102:                                              ; preds = %.preheader, %111
  %.12944 = phi i32 [ %112, %111 ], [ 0, %.preheader ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #3
  call void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13) %5, i32 noundef %0, i1 noundef zeroext false)
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #3
  call void @_ZN20CorrectRWLScopedBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16) %6, i32 noundef %0, ptr noundef nonnull align 4 dereferenceable(13) %5)
  %103 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_readers, i64 noundef 0)
  %104 = call noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8) @active_writers, i64 noundef %103)
  %105 = call noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers, i1 noundef zeroext false)
  call void @_Z17NativeParallelForIi20CorrectRWLScopedBodyEvT_RKT0_(i32 noundef %0, ptr noundef nonnull align 8 dereferenceable(16) %6)
  %106 = call noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1) @sim_readers)
  %or.cond3 = or i1 %72, %106
  br i1 %or.cond3, label %107, label %111

107:                                              ; preds = %102
  %108 = load i64, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %109 = add i64 %108, 1
  store i64 %109, ptr @n_tested__sim_readers, align 8, !tbaa !11
  %110 = icmp ugt i64 %109, 5
  br i1 %110, label %113, label %111

111:                                              ; preds = %102, %107
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #3
  %112 = add nuw nsw i32 %.12944, 1
  %exitcond48.not = icmp eq i32 %112, 100
  br i1 %exitcond48.not, label %.critedge34, label %102, !llvm.loop !15

113:                                              ; preds = %107
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #3
  br label %114

.critedge34:                                      ; preds = %111
  call void @_Z11ReportErrorPKciS0_S0_(ptr noundef nonnull @.str.18, i32 noundef 217, ptr noundef nonnull @.str.22, ptr noundef nonnull @.str.23)
  br label %114

114:                                              ; preds = %113, %.critedge34
  %115 = load i8, ptr @_ZL7Verbose, align 1, !tbaa !5, !range !9, !noundef !10
  %116 = trunc nuw i8 %115 to i1
  br i1 %116, label %117, label %119

117:                                              ; preds = %114
  %118 = call noundef ptr @_ZN7Harness8internal6Tracer14set_trace_infoEiPKcmS3_(ptr noundef nonnull align 8 dereferenceable(33) @_ZN7Harness8internalL6tracerE, i32 noundef 0, ptr noundef nonnull @.str.18, i64 noundef 218, ptr noundef nonnull @__FUNCTION__._Z30TestReaderWriterLockOnNThreadsi)
  call void (ptr, ptr, ...) @_ZN7Harness8internal6Tracer5traceEPKcz(ptr noundef nonnull align 8 dereferenceable(33) %118, ptr noundef nonnull @.str.20)
  br label %119

119:                                              ; preds = %114, %117
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN13StressRWLBodyC2Eii(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi13StressRWLBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7Harness11SpinBarrierC2Ejb(ptr noundef nonnull align 4 dereferenceable(13), i32 noundef, i1 noundef zeroext) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN14CorrectRWLBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef, ptr noundef nonnull align 4 dereferenceable(13)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN3tbb6atomicImEaSEm(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN3tbb6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1), i1 noundef zeroext) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi14CorrectRWLBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZNVK3tbb8internal11atomic_implIbEcvbEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN20CorrectRWLScopedBodyC2EiRN7Harness11SpinBarrierE(ptr noundef nonnull align 8 dereferenceable(16), i32 noundef, ptr noundef nonnull align 4 dereferenceable(13)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z17NativeParallelForIi20CorrectRWLScopedBodyEvT_RKT0_(i32 noundef, ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass