; LLVM IR from VastoLorde95/Competitive-Programming :: Codeforces/179 Division 1/Problem A/A.ll (Z6updatexxxxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i64 }

@tree = external dso_local global [524288 x %struct.node], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4node7combineERS_S0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z3updxxxx(i64 noundef, i64 noundef, i64 noundef, i64 noundef) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5shiftxxx(i64 noundef, i64 noundef, i64 noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) #2 {
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  store i64 %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !5
  store i64 %2, ptr %9, align 8, !tbaa !5
  store i64 %3, ptr %10, align 8, !tbaa !5
  store i64 %4, ptr %11, align 8, !tbaa !5
  store i64 %5, ptr %12, align 8, !tbaa !5
  %16 = load i64, ptr %7, align 8, !tbaa !5
  %17 = load i64, ptr %12, align 8, !tbaa !5
  %18 = icmp sge i64 %16, %17
  br i1 %18, label %23, label %19

19:                                               ; preds = %6
  %20 = load i64, ptr %11, align 8, !tbaa !5
  %21 = load i64, ptr %8, align 8, !tbaa !5
  %22 = icmp sge i64 %20, %21
  br i1 %22, label %23, label %24

23:                                               ; preds = %19, %6
  br label %67

24:                                               ; preds = %19
  %25 = load i64, ptr %7, align 8, !tbaa !5
  %26 = load i64, ptr %11, align 8, !tbaa !5
  %27 = icmp sle i64 %25, %26
  br i1 %27, label %28, label %37

28:                                               ; preds = %24
  %29 = load i64, ptr %12, align 8, !tbaa !5
  %30 = load i64, ptr %8, align 8, !tbaa !5
  %31 = icmp sle i64 %29, %30
  br i1 %31, label %32, label %37

32:                                               ; preds = %28
  %33 = load i64, ptr %10, align 8, !tbaa !5
  %34 = load i64, ptr %11, align 8, !tbaa !5
  %35 = load i64, ptr %12, align 8, !tbaa !5
  %36 = load i64, ptr %9, align 8, !tbaa !5
  call void @_Z3updxxxx(i64 noundef %33, i64 noundef %34, i64 noundef %35, i64 noundef %36)
  br label %67

37:                                               ; preds = %28, %24
  %38 = load i64, ptr %10, align 8, !tbaa !5
  %39 = load i64, ptr %11, align 8, !tbaa !5
  %40 = load i64, ptr %12, align 8, !tbaa !5
  call void @_Z5shiftxxx(i64 noundef %38, i64 noundef %39, i64 noundef %40)
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  %41 = load i64, ptr %10, align 8, !tbaa !5
  %42 = shl i64 %41, 1
  store i64 %42, ptr %13, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  %43 = load i64, ptr %13, align 8, !tbaa !5
  %44 = add nsw i64 %43, 1
  store i64 %44, ptr %14, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  %45 = load i64, ptr %11, align 8, !tbaa !5
  %46 = load i64, ptr %12, align 8, !tbaa !5
  %47 = add nsw i64 %45, %46
  %48 = ashr i64 %47, 1
  store i64 %48, ptr %15, align 8, !tbaa !5
  %49 = load i64, ptr %7, align 8, !tbaa !5
  %50 = load i64, ptr %8, align 8, !tbaa !5
  %51 = load i64, ptr %9, align 8, !tbaa !5
  %52 = load i64, ptr %13, align 8, !tbaa !5
  %53 = load i64, ptr %11, align 8, !tbaa !5
  %54 = load i64, ptr %15, align 8, !tbaa !5
  call void @_Z6updatexxxxxx(i64 noundef %49, i64 noundef %50, i64 noundef %51, i64 noundef %52, i64 noundef %53, i64 noundef %54)
  %55 = load i64, ptr %7, align 8, !tbaa !5
  %56 = load i64, ptr %8, align 8, !tbaa !5
  %57 = load i64, ptr %9, align 8, !tbaa !5
  %58 = load i64, ptr %14, align 8, !tbaa !5
  %59 = load i64, ptr %15, align 8, !tbaa !5
  %60 = load i64, ptr %12, align 8, !tbaa !5
  call void @_Z6updatexxxxxx(i64 noundef %55, i64 noundef %56, i64 noundef %57, i64 noundef %58, i64 noundef %59, i64 noundef %60)
  %61 = load i64, ptr %10, align 8, !tbaa !5
  %62 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %61
  %63 = load i64, ptr %13, align 8, !tbaa !5
  %64 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %63
  %65 = load i64, ptr %14, align 8, !tbaa !5
  %66 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %65
  call void @_ZN4node7combineERS_S0_(ptr noundef nonnull align 8 dereferenceable(8) %62, ptr noundef nonnull align 8 dereferenceable(8) %64, ptr noundef nonnull align 8 dereferenceable(8) %66)
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  br label %67

67:                                               ; preds = %37, %32, %23
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i64 }

@tree = external dso_local global [524288 x %struct.node], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4node7combineERS_S0_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z3updxxxx(i64 noundef, i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5shiftxxx(i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) local_unnamed_addr #1 {
  %.not = icmp slt i64 %0, %5
  %.not37 = icmp slt i64 %4, %1
  %or.cond = and i1 %.not37, %.not
  br i1 %or.cond, label %7, label %common.ret41

7:                                                ; preds = %6
  %.not38 = icmp sgt i64 %0, %4
  %.not39 = icmp sgt i64 %5, %1
  %or.cond40 = or i1 %.not38, %.not39
  br i1 %or.cond40, label %9, label %8

8:                                                ; preds = %7
  tail call void @_Z3updxxxx(i64 noundef %3, i64 noundef %4, i64 noundef %5, i64 noundef %2)
  br label %common.ret41

common.ret41:                                     ; preds = %6, %8, %9
  ret void

9:                                                ; preds = %7
  tail call void @_Z5shiftxxx(i64 noundef %3, i64 noundef %4, i64 noundef %5)
  %10 = shl i64 %3, 1
  %11 = or disjoint i64 %10, 1
  %12 = add nsw i64 %5, %4
  %13 = ashr i64 %12, 1
  tail call void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %10, i64 noundef %4, i64 noundef %13)
  tail call void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %11, i64 noundef %13, i64 noundef %5)
  %14 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %3
  %15 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %10
  %16 = getelementptr inbounds [524288 x %struct.node], ptr @tree, i64 0, i64 %11
  tail call void @_ZN4node7combineERS_S0_(ptr noundef nonnull align 8 dereferenceable(8) %14, ptr noundef nonnull align 8 dereferenceable(8) %15, ptr noundef nonnull align 8 dereferenceable(8) %16)
  br label %common.ret41
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass