; LLVM IR from IOsonata/IOsonata :: src (uart_retarget)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__Uart_Dev = type <{ i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32, %struct.__device_intrf, ptr, ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, [2 x i8] }>
%struct.__device_intrf = type <{ ptr, i32, ptr, %struct.atomic_flag, [3 x i8], i32, i32, i32, i8, i8, i8, i8, i64, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }>
%struct.atomic_flag = type { i8 }

; Function Attrs: nounwind uwtable
define dso_local i32 @UARTStdDevRead(ptr noundef %0, i32 noundef %1, ptr noundef %2, i64 noundef %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store i64 %3, ptr %8, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %13, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !9
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = load ptr, ptr %9, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.__Uart_Dev, ptr %15, i32 0, i32 18
  %17 = load i32, ptr %16, align 4, !tbaa !13
  %18 = icmp eq i32 %14, %17
  br i1 %18, label %19, label %53

19:                                               ; preds = %4
  br label %20

20:                                               ; preds = %51, %19
  %21 = load i32, ptr %10, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = load i64, ptr %8, align 8, !tbaa !11
  %24 = icmp ult i64 %22, %23
  br i1 %24, label %25, label %52

25:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %26 = load ptr, ptr %9, align 8, !tbaa !5
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = load i64, ptr %8, align 8, !tbaa !11
  %29 = trunc i64 %28 to i32
  %30 = call i32 @UARTRx(ptr noundef %26, ptr noundef %27, i32 noundef %29)
  store i32 %30, ptr %11, align 4, !tbaa !9
  %31 = load i32, ptr %11, align 4, !tbaa !9
  %32 = icmp sgt i32 %31, 0
  br i1 %32, label %33, label %43

33:                                               ; preds = %25
  %34 = load i32, ptr %10, align 4, !tbaa !9
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %10, align 4, !tbaa !9
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = getelementptr inbounds i8, ptr %36, i32 1
  store ptr %37, ptr %7, align 8, !tbaa !5
  %38 = load i8, ptr %36, align 1, !tbaa !18
  %39 = zext i8 %38 to i32
  %40 = icmp eq i32 %39, 13
  br i1 %40, label %41, label %42

41:                                               ; preds = %33
  store i32 3, ptr %12, align 4
  br label %49

42:                                               ; preds = %33
  br label %48

43:                                               ; preds = %25
  %44 = load i32, ptr %10, align 4, !tbaa !9
  %45 = icmp sgt i32 %44, 0
  br i1 %45, label %46, label %47

46:                                               ; preds = %43
  store i32 3, ptr %12, align 4
  br label %49

47:                                               ; preds = %43
  br label %48

48:                                               ; preds = %47, %42
  store i32 0, ptr %12, align 4
  br label %49

49:                                               ; preds = %48, %46, %41
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  %50 = load i32, ptr %12, align 4
  switch i32 %50, label %59 [
    i32 0, label %51
    i32 3, label %52
  ]

51:                                               ; preds = %49
  br label %20, !llvm.loop !19

52:                                               ; preds = %49, %20
  br label %53

53:                                               ; preds = %52, %4
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = icmp eq i32 %54, 0
  br i1 %55, label %56, label %57

56:                                               ; preds = %53
  store i32 -1, ptr %10, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %56, %53
  %58 = load i32, ptr %10, align 4, !tbaa !9
  store i32 1, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret i32 %58

59:                                               ; preds = %49
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @UARTRx(ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !10, i64 232}
!14 = !{!"__Uart_Dev", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !15, i64 28, !15, i64 29, !15, i64 30, !10, i64 32, !16, i64 36, !6, i64 196, !6, i64 204, !6, i64 212, !6, i64 220, !10, i64 228, !10, i64 232, !10, i64 236, !10, i64 240, !10, i64 244, !10, i64 248, !10, i64 252, !10, i64 256, !15, i64 260, !15, i64 261}
!15 = !{!"_Bool", !7, i64 0}
!16 = !{!"__device_intrf", !6, i64 0, !10, i64 8, !6, i64 12, !17, i64 20, !10, i64 24, !7, i64 28, !10, i64 32, !15, i64 36, !15, i64 37, !7, i64 38, !7, i64 39, !12, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152}
!17 = !{!"atomic_flag", !7, i64 0}
!18 = !{!7, !7, i64 0}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @UARTStdDevRead(ptr noundef %0, i32 noundef %1, ptr noundef %2, i64 noundef %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 232
  %6 = load i32, ptr %5, align 4, !tbaa !5
  %7 = icmp ne i32 %6, %1
  %.not = icmp eq i64 %3, 0
  %or.cond = or i1 %7, %.not
  br i1 %or.cond, label %.thread23, label %.lr.ph

.lr.ph:                                           ; preds = %4
  %8 = trunc i64 %3 to i32
  br label %9

9:                                                ; preds = %.lr.ph, %19
  %.01430 = phi ptr [ %2, %.lr.ph ], [ %.1, %19 ]
  %.01529 = phi i32 [ 0, %.lr.ph ], [ %.116, %19 ]
  %10 = tail call i32 @UARTRx(ptr noundef %0, ptr noundef %.01430, i32 noundef %8)
  %11 = icmp sgt i32 %10, 0
  br i1 %11, label %12, label %17

12:                                               ; preds = %9
  %13 = add nsw i32 %.01529, 1
  %14 = getelementptr inbounds i8, ptr %.01430, i64 1
  %15 = load i8, ptr %.01430, align 1, !tbaa !15
  %16 = icmp eq i8 %15, 13
  br i1 %16, label %.thread, label %19

17:                                               ; preds = %9
  %18 = icmp sgt i32 %.01529, 0
  br i1 %18, label %.thread.thread, label %19

19:                                               ; preds = %12, %17
  %.116 = phi i32 [ %13, %12 ], [ %.01529, %17 ]
  %.1 = phi ptr [ %14, %12 ], [ %.01430, %17 ]
  %20 = sext i32 %.116 to i64
  %21 = icmp ult i64 %20, %3
  br i1 %21, label %9, label %.thread

.thread:                                          ; preds = %19, %12
  %.3.ph = phi i32 [ %.116, %19 ], [ %13, %12 ]
  %22 = freeze i32 %.3.ph
  %23 = icmp eq i32 %22, 0
  br i1 %23, label %.thread23, label %.thread.thread

.thread23:                                        ; preds = %4, %.thread
  br label %.thread.thread

.thread.thread:                                   ; preds = %17, %.thread, %.thread23
  %24 = phi i32 [ -1, %.thread23 ], [ %22, %.thread ], [ %.01529, %17 ]
  ret i32 %24
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @UARTRx(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 232}
!6 = !{!"__Uart_Dev", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !10, i64 28, !10, i64 29, !10, i64 30, !7, i64 32, !11, i64 36, !12, i64 196, !12, i64 204, !12, i64 212, !12, i64 220, !7, i64 228, !7, i64 232, !7, i64 236, !7, i64 240, !7, i64 244, !7, i64 248, !7, i64 252, !7, i64 256, !10, i64 260, !10, i64 261}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"_Bool", !8, i64 0}
!11 = !{!"__device_intrf", !12, i64 0, !7, i64 8, !12, i64 12, !13, i64 20, !7, i64 24, !8, i64 28, !7, i64 32, !10, i64 36, !10, i64 37, !8, i64 38, !8, i64 39, !14, i64 40, !12, i64 48, !12, i64 56, !12, i64 64, !12, i64 72, !12, i64 80, !12, i64 88, !12, i64 96, !12, i64 104, !12, i64 112, !12, i64 120, !12, i64 128, !12, i64 136, !12, i64 144, !12, i64 152}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"atomic_flag", !8, i64 0}
!14 = !{!"long", !8, i64 0}
!15 = !{!8, !8, i64 0}


; Effective O3 passes: GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass