; LLVM IR from FidoProject/Fido :: src/WireFitQLearn.ll (ZN2rl13WireFitQLearn13highestRewardESt6vectorIdSaIdEE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.rl::Wire" = type { %"class.std::vector", double }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN2rl4WireESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN2rl13WireFitQLearn8getWiresESt6vectorIdSaIdEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector.8") align 8, ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef double @_ZN2rl13WireFitQLearn13highestRewardESt6vectorIdSaIdEE(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef %1) #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %"class.std::vector.8", align 8
  %6 = alloca %"class.std::vector", align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca double, align 8
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %11 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 24, ptr %5) #3
  call void @_ZNSt6vectorIdSaIdEEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %1)
  invoke void @_ZN2rl13WireFitQLearn8getWiresESt6vectorIdSaIdEE(ptr dead_on_unwind writable sret(%"class.std::vector.8") align 8 %5, ptr noundef nonnull align 8 dereferenceable(184) %11, ptr noundef %6)
          to label %12 unwind label %19

12:                                               ; preds = %2
  call void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  store double -9.999900e+04, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !11
  br label %13

13:                                               ; preds = %38, %12
  %14 = load i32, ptr %10, align 4, !tbaa !11
  %15 = zext i32 %14 to i64
  %16 = call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  %17 = icmp ult i64 %15, %16
  br i1 %17, label %23, label %18

18:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %41

19:                                               ; preds = %2
  %20 = landingpad { ptr, i32 }
          cleanup
  %21 = extractvalue { ptr, i32 } %20, 0
  store ptr %21, ptr %7, align 8
  %22 = extractvalue { ptr, i32 } %20, 1
  store i32 %22, ptr %8, align 4
  call void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  br label %43

23:                                               ; preds = %13
  %24 = load i32, ptr %10, align 4, !tbaa !11
  %25 = zext i32 %24 to i64
  %26 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %25) #3
  %27 = getelementptr inbounds %"struct.rl::Wire", ptr %26, i32 0, i32 1
  %28 = load double, ptr %27, align 8, !tbaa !13
  %29 = load double, ptr %9, align 8, !tbaa !9
  %30 = fcmp ogt double %28, %29
  br i1 %30, label %31, label %37

31:                                               ; preds = %23
  %32 = load i32, ptr %10, align 4, !tbaa !11
  %33 = zext i32 %32 to i64
  %34 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %33) #3
  %35 = getelementptr inbounds %"struct.rl::Wire", ptr %34, i32 0, i32 1
  %36 = load double, ptr %35, align 8, !tbaa !13
  store double %36, ptr %9, align 8, !tbaa !9
  br label %37

37:                                               ; preds = %31, %23
  br label %38

38:                                               ; preds = %37
  %39 = load i32, ptr %10, align 4, !tbaa !11
  %40 = add i32 %39, 1
  store i32 %40, ptr %10, align 4, !tbaa !11
  br label %13, !llvm.loop !19

41:                                               ; preds = %18
  %42 = load double, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @_ZNSt6vectorIN2rl4WireESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #3
  ret double %42

43:                                               ; preds = %19
  %44 = load ptr, ptr %7, align 8
  %45 = load i32, ptr %8, align 4
  %46 = insertvalue { ptr, i32 } poison, ptr %44, 0
  %47 = insertvalue { ptr, i32 } %46, i32 %45, 1
  resume { ptr, i32 } %47
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !10, i64 24}
!14 = !{!"_ZTSN2rl4WireE", !15, i64 0, !10, i64 24}
!15 = !{!"_ZTSSt6vectorIdSaIdEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN2rl4WireESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN2rl13WireFitQLearn8getWiresESt6vectorIdSaIdEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector.8") align 8, ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef double @_ZN2rl13WireFitQLearn13highestRewardESt6vectorIdSaIdEE(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef nonnull %1) local_unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca %"class.std::vector.8", align 8
  %4 = alloca %"class.std::vector", align 8
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %3) #3
  call void @_ZNSt6vectorIdSaIdEEC2ERKS1_(ptr noundef nonnull align 8 dereferenceable(24) %4, ptr noundef nonnull align 8 dereferenceable(24) %1)
  invoke void @_ZN2rl13WireFitQLearn8getWiresESt6vectorIdSaIdEE(ptr dead_on_unwind nonnull writable sret(%"class.std::vector.8") align 8 %3, ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef nonnull %4)
          to label %5 unwind label %7

5:                                                ; preds = %2
  call void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %6 = call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  %.not = icmp eq i64 %6, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %18, %5
  %.08.lcssa = phi double [ -9.999900e+04, %5 ], [ %.1, %18 ]
  call void @_ZNSt6vectorIN2rl4WireESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #3
  ret double %.08.lcssa

7:                                                ; preds = %2
  %8 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt6vectorIdSaIdEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #3
  resume { ptr, i32 } %8

.lr.ph:                                           ; preds = %5, %18
  %9 = phi i64 [ %20, %18 ], [ 0, %5 ]
  %.011 = phi i32 [ %19, %18 ], [ 0, %5 ]
  %.0810 = phi double [ %.1, %18 ], [ -9.999900e+04, %5 ]
  %10 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %9) #3
  %11 = getelementptr inbounds i8, ptr %10, i64 24
  %12 = load double, ptr %11, align 8, !tbaa !5
  %13 = fcmp ogt double %12, %.0810
  br i1 %13, label %14, label %18

14:                                               ; preds = %.lr.ph
  %15 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %9) #3
  %16 = getelementptr inbounds i8, ptr %15, i64 24
  %17 = load double, ptr %16, align 8, !tbaa !5
  br label %18

18:                                               ; preds = %.lr.ph, %14
  %.1 = phi double [ %17, %14 ], [ %.0810, %.lr.ph ]
  %19 = add i32 %.011, 1
  %20 = zext i32 %19 to i64
  %21 = call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  %22 = icmp ugt i64 %21, %20
  br i1 %22, label %.lr.ph, label %._crit_edge, !llvm.loop !15
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 24}
!6 = !{!"_ZTSN2rl4WireE", !7, i64 0, !14, i64 24}
!7 = !{!"_ZTSSt6vectorIdSaIdEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"double", !12, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass