; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl4_c_t = type { i8 }
%struct.lsm6dsl_ctrl6_c_t = type { i8 }
%struct.lsm6dsl_ctrl7_g_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_gy_band_pass_set(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca %struct.lsm6dsl_ctrl4_c_t, align 1
  %6 = alloca %struct.lsm6dsl_ctrl6_c_t, align 1
  %7 = alloca %struct.lsm6dsl_ctrl7_g_t, align 1
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = call i32 @lsm6dsl_read_reg(ptr noundef %9, i8 noundef zeroext 22, ptr noundef %7, i16 noundef zeroext 1)
  store i32 %10, ptr %8, align 4, !tbaa !9
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = icmp eq i32 %11, 0
  br i1 %12, label %13, label %82

13:                                               ; preds = %2
  %14 = load i32, ptr %4, align 4, !tbaa !9
  %15 = trunc i32 %14 to i8
  %16 = zext i8 %15 to i32
  %17 = and i32 %16, 48
  %18 = lshr i32 %17, 4
  %19 = trunc i32 %18 to i8
  %20 = load i8, ptr %7, align 1
  %21 = and i8 %19, 3
  %22 = shl i8 %21, 4
  %23 = and i8 %20, -49
  %24 = or i8 %23, %22
  store i8 %24, ptr %7, align 1
  %25 = load i32, ptr %4, align 4, !tbaa !9
  %26 = trunc i32 %25 to i8
  %27 = zext i8 %26 to i32
  %28 = and i32 %27, 128
  %29 = lshr i32 %28, 7
  %30 = trunc i32 %29 to i8
  %31 = load i8, ptr %7, align 1
  %32 = and i8 %30, 1
  %33 = shl i8 %32, 6
  %34 = and i8 %31, -65
  %35 = or i8 %34, %33
  store i8 %35, ptr %7, align 1
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = call i32 @lsm6dsl_write_reg(ptr noundef %36, i8 noundef zeroext 22, ptr noundef %7, i16 noundef zeroext 1)
  store i32 %37, ptr %8, align 4, !tbaa !9
  %38 = load i32, ptr %8, align 4, !tbaa !9
  %39 = icmp eq i32 %38, 0
  br i1 %39, label %40, label %81

40:                                               ; preds = %13
  %41 = load ptr, ptr %3, align 8, !tbaa !5
  %42 = call i32 @lsm6dsl_read_reg(ptr noundef %41, i8 noundef zeroext 21, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %42, ptr %8, align 4, !tbaa !9
  %43 = load i32, ptr %8, align 4, !tbaa !9
  %44 = icmp eq i32 %43, 0
  br i1 %44, label %45, label %80

45:                                               ; preds = %40
  %46 = load i32, ptr %4, align 4, !tbaa !9
  %47 = trunc i32 %46 to i8
  %48 = zext i8 %47 to i32
  %49 = and i32 %48, 3
  %50 = trunc i32 %49 to i8
  %51 = load i8, ptr %6, align 1
  %52 = and i8 %50, 3
  %53 = and i8 %51, -4
  %54 = or i8 %53, %52
  store i8 %54, ptr %6, align 1
  %55 = load ptr, ptr %3, align 8, !tbaa !5
  %56 = call i32 @lsm6dsl_write_reg(ptr noundef %55, i8 noundef zeroext 21, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %56, ptr %8, align 4, !tbaa !9
  %57 = load i32, ptr %8, align 4, !tbaa !9
  %58 = icmp eq i32 %57, 0
  br i1 %58, label %59, label %79

59:                                               ; preds = %45
  %60 = load ptr, ptr %3, align 8, !tbaa !5
  %61 = call i32 @lsm6dsl_read_reg(ptr noundef %60, i8 noundef zeroext 19, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %61, ptr %8, align 4, !tbaa !9
  %62 = load i32, ptr %8, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 0
  br i1 %63, label %64, label %78

64:                                               ; preds = %59
  %65 = load i32, ptr %4, align 4, !tbaa !9
  %66 = trunc i32 %65 to i8
  %67 = zext i8 %66 to i32
  %68 = and i32 %67, 8
  %69 = lshr i32 %68, 3
  %70 = trunc i32 %69 to i8
  %71 = load i8, ptr %5, align 1
  %72 = and i8 %70, 1
  %73 = shl i8 %72, 1
  %74 = and i8 %71, -3
  %75 = or i8 %74, %73
  store i8 %75, ptr %5, align 1
  %76 = load ptr, ptr %3, align 8, !tbaa !5
  %77 = call i32 @lsm6dsl_write_reg(ptr noundef %76, i8 noundef zeroext 19, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %77, ptr %8, align 4, !tbaa !9
  br label %78

78:                                               ; preds = %64, %59
  br label %79

79:                                               ; preds = %78, %45
  br label %80

80:                                               ; preds = %79, %40
  br label %81

81:                                               ; preds = %80, %13
  br label %82

82:                                               ; preds = %81, %2
  %83 = load i32, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %83
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl4_c_t = type { i8 }
%struct.lsm6dsl_ctrl6_c_t = type { i8 }
%struct.lsm6dsl_ctrl7_g_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_write_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_gy_band_pass_set(ptr noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_ctrl4_c_t, align 1
  %4 = alloca %struct.lsm6dsl_ctrl6_c_t, align 1
  %5 = alloca %struct.lsm6dsl_ctrl7_g_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #2
  %6 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 22, ptr noundef nonnull %5, i16 noundef zeroext 1)
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %8, label %39

8:                                                ; preds = %2
  %9 = trunc i32 %1 to i8
  %10 = and i8 %9, 48
  %11 = load i8, ptr %5, align 1
  %12 = and i8 %11, -113
  %13 = lshr i8 %9, 1
  %14 = and i8 %13, 64
  %15 = or disjoint i8 %14, %10
  %16 = or disjoint i8 %15, %12
  store i8 %16, ptr %5, align 1
  %17 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 22, ptr noundef nonnull %5, i16 noundef zeroext 1)
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %39

19:                                               ; preds = %8
  %20 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 21, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %39

22:                                               ; preds = %19
  %23 = and i8 %9, 3
  %24 = load i8, ptr %4, align 1
  %25 = and i8 %24, -4
  %26 = or disjoint i8 %25, %23
  store i8 %26, ptr %4, align 1
  %27 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 21, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %29, label %39

29:                                               ; preds = %22
  %30 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 19, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %39

32:                                               ; preds = %29
  %33 = load i8, ptr %3, align 1
  %34 = lshr i8 %9, 2
  %35 = and i8 %34, 2
  %36 = and i8 %33, -3
  %37 = or disjoint i8 %36, %35
  store i8 %37, ptr %3, align 1
  %38 = call i32 @lsm6dsl_write_reg(ptr noundef %0, i8 noundef zeroext 19, ptr noundef nonnull %3, i16 noundef zeroext 1)
  br label %39

39:                                               ; preds = %8, %22, %32, %29, %19, %2
  %.0 = phi i32 [ %38, %32 ], [ %30, %29 ], [ %27, %22 ], [ %20, %19 ], [ %17, %8 ], [ %6, %2 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass