; LLVM IR from IOsonata/IOsonata :: ARM/Nordic/nRF52/nRF52840/exemples/BoschAppBoard/src (bmi3)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.bmi3_get_i3c_sync_i3c_tc_res.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_i3c_sync_i3c_tc_res(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca [2 x i8], align 1
  %7 = alloca [2 x i8], align 1
  %8 = alloca i8, align 1
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #4
  call void @llvm.memset.p0.i64(ptr align 1 %6, i8 0, i64 2, i1 false)
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %7, ptr align 1 @__const.bmi3_get_i3c_sync_i3c_tc_res.base_addr, i64 2, i1 false)
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  store i8 0, ptr %8, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %57

14:                                               ; preds = %2
  %15 = getelementptr inbounds [2 x i8], ptr %7, i64 0, i64 0
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef %15, i16 noundef zeroext 2, ptr noundef %16)
  store i8 %17, ptr %5, align 1, !tbaa !9
  %18 = load i8, ptr %5, align 1, !tbaa !9
  %19 = sext i8 %18 to i32
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %56

21:                                               ; preds = %14
  %22 = getelementptr inbounds [2 x i8], ptr %6, i64 0, i64 0
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 66, ptr noundef %22, i16 noundef zeroext 2, ptr noundef %23)
  store i8 %24, ptr %5, align 1, !tbaa !9
  %25 = load i8, ptr %5, align 1, !tbaa !9
  %26 = sext i8 %25 to i32
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %55

28:                                               ; preds = %21
  %29 = load i8, ptr %8, align 1, !tbaa !9
  %30 = add i8 %29, 1
  store i8 %30, ptr %8, align 1, !tbaa !9
  %31 = zext i8 %29 to i64
  %32 = getelementptr inbounds [2 x i8], ptr %6, i64 0, i64 %31
  %33 = load i8, ptr %32, align 1, !tbaa !9
  %34 = zext i8 %33 to i16
  store i16 %34, ptr %9, align 2, !tbaa !10
  %35 = load i8, ptr %8, align 1, !tbaa !9
  %36 = add i8 %35, 1
  store i8 %36, ptr %8, align 1, !tbaa !9
  %37 = zext i8 %35 to i64
  %38 = getelementptr inbounds [2 x i8], ptr %6, i64 0, i64 %37
  %39 = load i8, ptr %38, align 1, !tbaa !9
  %40 = zext i8 %39 to i16
  %41 = zext i16 %40 to i32
  %42 = shl i32 %41, 8
  %43 = trunc i32 %42 to i16
  store i16 %43, ptr %10, align 2, !tbaa !10
  %44 = load i16, ptr %9, align 2, !tbaa !10
  %45 = zext i16 %44 to i32
  %46 = load i16, ptr %10, align 2, !tbaa !10
  %47 = zext i16 %46 to i32
  %48 = or i32 %45, %47
  %49 = trunc i32 %48 to i16
  store i16 %49, ptr %11, align 2, !tbaa !10
  %50 = load i16, ptr %11, align 2, !tbaa !10
  %51 = zext i16 %50 to i32
  %52 = and i32 %51, 1
  %53 = trunc i32 %52 to i8
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  store i8 %53, ptr %54, align 1, !tbaa !9
  br label %55

55:                                               ; preds = %28, %21
  br label %56

56:                                               ; preds = %55, %14
  br label %58

57:                                               ; preds = %2
  store i8 -1, ptr %5, align 1, !tbaa !9
  br label %58

58:                                               ; preds = %57, %56
  %59 = load i8, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i8 %59
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.bmi3_get_i3c_sync_i3c_tc_res.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_get_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_get_i3c_sync_i3c_tc_res(ptr noundef writeonly %0, ptr noundef %1) local_unnamed_addr #1 {
  %3 = alloca [2 x i8], align 2
  %4 = alloca [2 x i8], align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %3) #2
  store i16 0, ptr %3, align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %4) #2
  %5 = load i16, ptr @__const.bmi3_get_i3c_sync_i3c_tc_res.base_addr, align 1
  store i16 %5, ptr %4, align 2
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %15, label %6

6:                                                ; preds = %2
  %7 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef nonnull %4, i16 noundef zeroext 2, ptr noundef %1)
  %8 = icmp eq i8 %7, 0
  br i1 %8, label %9, label %15

9:                                                ; preds = %6
  %10 = call signext i8 @bmi3_get_regs(i8 noundef zeroext 66, ptr noundef nonnull %3, i16 noundef zeroext 2, ptr noundef %1)
  %11 = icmp eq i8 %10, 0
  br i1 %11, label %12, label %15

12:                                               ; preds = %9
  %13 = load i8, ptr %3, align 2, !tbaa !5
  %14 = and i8 %13, 1
  store i8 %14, ptr %0, align 1, !tbaa !5
  br label %15

15:                                               ; preds = %2, %6, %12, %9
  %.0 = phi i8 [ 0, %12 ], [ %10, %9 ], [ %7, %6 ], [ -1, %2 ]
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %3) #2
  ret i8 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass