; LLVM IR from siara-cc/Unishox_Arduino_lib :: src/unishox2.ll (Z12readVCodeIdxPKciPi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@usx_vsections = external dso_local global [5 x i8], align 1
@usx_vsection_pos = external dso_local global [5 x i8], align 1
@usx_vsection_mask = external dso_local global [5 x i8], align 1
@usx_vsection_shift = external dso_local global [5 x i8], align 1
@usx_vcode_lookup = external dso_local global [36 x i8], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z12read8bitCodePKcii(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z12readVCodeIdxPKciPi(ptr noundef %0, i32 noundef %1, ptr noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  %12 = load ptr, ptr %7, align 8, !tbaa !5
  %13 = load i32, ptr %12, align 4, !tbaa !9
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %16, label %82

16:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #2
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = load i32, ptr %6, align 4, !tbaa !9
  %19 = load ptr, ptr %7, align 8, !tbaa !5
  %20 = load i32, ptr %19, align 4, !tbaa !9
  %21 = call noundef i32 @_Z12read8bitCodePKcii(ptr noundef %17, i32 noundef %18, i32 noundef %20)
  %22 = trunc i32 %21 to i8
  store i8 %22, ptr %8, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %23

23:                                               ; preds = %74, %16
  %24 = load i8, ptr %8, align 1, !tbaa !11
  %25 = zext i8 %24 to i32
  %26 = load i32, ptr %9, align 4, !tbaa !9
  %27 = sext i32 %26 to i64
  %28 = getelementptr inbounds [5 x i8], ptr @usx_vsections, i64 0, i64 %27
  %29 = load i8, ptr %28, align 1, !tbaa !11
  %30 = zext i8 %29 to i32
  %31 = icmp sle i32 %25, %30
  br i1 %31, label %32, label %73

32:                                               ; preds = %23
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #2
  %33 = load i32, ptr %9, align 4, !tbaa !9
  %34 = sext i32 %33 to i64
  %35 = getelementptr inbounds [5 x i8], ptr @usx_vsection_pos, i64 0, i64 %34
  %36 = load i8, ptr %35, align 1, !tbaa !11
  %37 = zext i8 %36 to i32
  %38 = load i8, ptr %8, align 1, !tbaa !11
  %39 = zext i8 %38 to i32
  %40 = load i32, ptr %9, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds [5 x i8], ptr @usx_vsection_mask, i64 0, i64 %41
  %43 = load i8, ptr %42, align 1, !tbaa !11
  %44 = zext i8 %43 to i32
  %45 = and i32 %39, %44
  %46 = load i32, ptr %9, align 4, !tbaa !9
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds [5 x i8], ptr @usx_vsection_shift, i64 0, i64 %47
  %49 = load i8, ptr %48, align 1, !tbaa !11
  %50 = zext i8 %49 to i32
  %51 = ashr i32 %45, %50
  %52 = add nsw i32 %37, %51
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds [36 x i8], ptr @usx_vcode_lookup, i64 0, i64 %53
  %55 = load i8, ptr %54, align 1, !tbaa !11
  store i8 %55, ptr %10, align 1, !tbaa !11
  %56 = load i8, ptr %10, align 1, !tbaa !11
  %57 = zext i8 %56 to i32
  %58 = ashr i32 %57, 5
  %59 = add nsw i32 %58, 1
  %60 = load ptr, ptr %7, align 8, !tbaa !5
  %61 = load i32, ptr %60, align 4, !tbaa !9
  %62 = add nsw i32 %61, %59
  store i32 %62, ptr %60, align 4, !tbaa !9
  %63 = load ptr, ptr %7, align 8, !tbaa !5
  %64 = load i32, ptr %63, align 4, !tbaa !9
  %65 = load i32, ptr %6, align 4, !tbaa !9
  %66 = icmp sgt i32 %64, %65
  br i1 %66, label %67, label %68

67:                                               ; preds = %32
  store i32 99, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %72

68:                                               ; preds = %32
  %69 = load i8, ptr %10, align 1, !tbaa !11
  %70 = zext i8 %69 to i32
  %71 = and i32 %70, 31
  store i32 %71, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %72

72:                                               ; preds = %68, %67
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #2
  br label %79

73:                                               ; preds = %23
  br label %74

74:                                               ; preds = %73
  %75 = load i32, ptr %9, align 4, !tbaa !9
  %76 = add nsw i32 %75, 1
  store i32 %76, ptr %9, align 4, !tbaa !9
  %77 = icmp slt i32 %76, 5
  br i1 %77, label %23, label %78, !llvm.loop !12

78:                                               ; preds = %74
  store i32 0, ptr %11, align 4
  br label %79

79:                                               ; preds = %78, %72
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #2
  %80 = load i32, ptr %11, align 4
  switch i32 %80, label %85 [
    i32 0, label %81
    i32 1, label %83
  ]

81:                                               ; preds = %79
  br label %82

82:                                               ; preds = %81, %3
  store i32 99, ptr %4, align 4
  br label %83

83:                                               ; preds = %82, %79
  %84 = load i32, ptr %4, align 4
  ret i32 %84

85:                                               ; preds = %79
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@usx_vsections = external dso_local local_unnamed_addr global [5 x i8], align 1
@usx_vsection_pos = external dso_local local_unnamed_addr global [5 x i8], align 1
@usx_vsection_mask = external dso_local local_unnamed_addr global [5 x i8], align 1
@usx_vsection_shift = external dso_local local_unnamed_addr global [5 x i8], align 1
@usx_vcode_lookup = external dso_local local_unnamed_addr global [36 x i8], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z12read8bitCodePKcii(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z12readVCodeIdxPKciPi(ptr noundef %0, i32 noundef %1, ptr nocapture noundef %2) local_unnamed_addr #0 {
  %4 = load i32, ptr %2, align 4, !tbaa !5
  %5 = icmp slt i32 %4, %1
  br i1 %5, label %6, label %.thread

6:                                                ; preds = %3
  %7 = tail call noundef i32 @_Z12read8bitCodePKcii(ptr noundef %0, i32 noundef %1, i32 noundef %4)
  %8 = trunc i32 %7 to i8
  %9 = load i8, ptr @usx_vsections, align 1, !tbaa !9
  %.not.not = icmp ult i8 %9, %8
  br i1 %.not.not, label %10, label %18

10:                                               ; preds = %6
  %11 = load i8, ptr getelementptr inbounds (i8, ptr @usx_vsections, i64 1), align 1, !tbaa !9
  %.not.not.1 = icmp ult i8 %11, %8
  br i1 %.not.not.1, label %12, label %18

12:                                               ; preds = %10
  %13 = load i8, ptr getelementptr inbounds (i8, ptr @usx_vsections, i64 2), align 1, !tbaa !9
  %.not.not.2 = icmp ult i8 %13, %8
  br i1 %.not.not.2, label %14, label %18

14:                                               ; preds = %12
  %15 = load i8, ptr getelementptr inbounds (i8, ptr @usx_vsections, i64 3), align 1, !tbaa !9
  %.not.not.3 = icmp ult i8 %15, %8
  br i1 %.not.not.3, label %16, label %18

16:                                               ; preds = %14
  %17 = load i8, ptr getelementptr inbounds (i8, ptr @usx_vsections, i64 4), align 1, !tbaa !9
  %.not.not.4 = icmp ult i8 %17, %8
  br i1 %.not.not.4, label %.thread, label %18

18:                                               ; preds = %16, %14, %12, %10, %6
  %.lcssa = phi i64 [ 0, %6 ], [ 1, %10 ], [ 2, %12 ], [ 3, %14 ], [ 4, %16 ]
  %19 = getelementptr inbounds [5 x i8], ptr @usx_vsection_pos, i64 0, i64 %.lcssa
  %20 = load i8, ptr %19, align 1, !tbaa !9
  %21 = zext i8 %20 to i32
  %22 = getelementptr inbounds [5 x i8], ptr @usx_vsection_mask, i64 0, i64 %.lcssa
  %23 = load i8, ptr %22, align 1, !tbaa !9
  %24 = zext i8 %23 to i32
  %25 = and i32 %7, %24
  %26 = getelementptr inbounds [5 x i8], ptr @usx_vsection_shift, i64 0, i64 %.lcssa
  %27 = load i8, ptr %26, align 1, !tbaa !9
  %28 = zext nneg i8 %27 to i32
  %29 = lshr i32 %25, %28
  %30 = add nuw nsw i32 %29, %21
  %31 = zext nneg i32 %30 to i64
  %32 = getelementptr inbounds [36 x i8], ptr @usx_vcode_lookup, i64 0, i64 %31
  %33 = load i8, ptr %32, align 1, !tbaa !9
  %34 = zext i8 %33 to i32
  %35 = lshr i32 %34, 5
  %36 = load i32, ptr %2, align 4, !tbaa !5
  %37 = add i32 %36, 1
  %38 = add i32 %37, %35
  store i32 %38, ptr %2, align 4, !tbaa !5
  %39 = icmp sgt i32 %38, %1
  %40 = and i32 %34, 31
  %.018 = select i1 %39, i32 99, i32 %40
  br label %.thread

.thread:                                          ; preds = %16, %3, %18
  %.2 = phi i32 [ %.018, %18 ], [ 99, %3 ], [ 99, %16 ]
  ret i32 %.2
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopSimplifyPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass