; LLVM IR from IOsonata/IOsonata :: ARM/NXP/src (spi_lpcxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__device_intrf = type <{ ptr, i32, ptr, %struct.atomic_flag, [3 x i8], i32, i32, i32, i8, i8, i8, i8, i64, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }>
%struct.atomic_flag = type { i8 }
%struct.SSPDEV = type { i32, i32, ptr, ptr }
%struct.LPCSSPREG = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__SPI_Device = type { %struct.__SPI_Config, %struct.__device_intrf, i32, i32, [4 x ptr], [4 x i32], [4 x ptr], [4 x i32] }
%struct.__SPI_Config = type <{ i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, [2 x i8], i32, i8, [3 x i8], ptr }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @LpcSSPSetRate(ptr noundef %0, i32 noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.__device_intrf, ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 4, !tbaa !11
  store ptr %10, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.SSPDEV, ptr %11, i32 0, i32 2
  %13 = load ptr, ptr %12, align 8, !tbaa !16
  %14 = getelementptr inbounds %struct.LPCSSPREG, ptr %13, i32 0, i32 4
  %15 = load volatile i32, ptr %14, align 4, !tbaa !18
  %16 = and i32 %15, 255
  store i32 %16, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 0, ptr %7, align 4, !tbaa !9
  %17 = load i32, ptr %6, align 4, !tbaa !9
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %20

19:                                               ; preds = %2
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %19, %2
  %21 = load i32, ptr %4, align 4, !tbaa !9
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = mul i32 %21, %22
  store i32 %23, ptr %7, align 4, !tbaa !9
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SSPDEV, ptr %24, i32 0, i32 1
  %26 = load i32, ptr %25, align 4, !tbaa !20
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = ashr i32 %27, 1
  %29 = add i32 %26, %28
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = udiv i32 %29, %30
  %32 = sub i32 %31, 1
  store i32 %32, ptr %7, align 4, !tbaa !9
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SSPDEV, ptr %33, i32 0, i32 2
  %35 = load ptr, ptr %34, align 8, !tbaa !16
  %36 = getelementptr inbounds %struct.LPCSSPREG, ptr %35, i32 0, i32 0
  %37 = load volatile i32, ptr %36, align 4, !tbaa !21
  %38 = and i32 %37, -65281
  store volatile i32 %38, ptr %36, align 4, !tbaa !21
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = shl i32 %39, 8
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.SSPDEV, ptr %41, i32 0, i32 2
  %43 = load ptr, ptr %42, align 8, !tbaa !16
  %44 = getelementptr inbounds %struct.LPCSSPREG, ptr %43, i32 0, i32 0
  %45 = load volatile i32, ptr %44, align 4, !tbaa !21
  %46 = or i32 %45, %40
  store volatile i32 %46, ptr %44, align 4, !tbaa !21
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.SSPDEV, ptr %47, i32 0, i32 1
  %49 = load i32, ptr %48, align 4, !tbaa !20
  %50 = load i32, ptr %7, align 4, !tbaa !9
  %51 = add nsw i32 %50, 1
  %52 = load i32, ptr %6, align 4, !tbaa !9
  %53 = mul nsw i32 %51, %52
  %54 = udiv i32 %49, %53
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.SSPDEV, ptr %55, i32 0, i32 3
  %57 = load ptr, ptr %56, align 8, !tbaa !22
  %58 = getelementptr inbounds %struct.__SPI_Device, ptr %57, i32 0, i32 0
  %59 = getelementptr inbounds %struct.__SPI_Config, ptr %58, i32 0, i32 5
  store i32 %54, ptr %59, align 4, !tbaa !23
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.SSPDEV, ptr %60, i32 0, i32 3
  %62 = load ptr, ptr %61, align 8, !tbaa !22
  %63 = getelementptr inbounds %struct.__SPI_Device, ptr %62, i32 0, i32 0
  %64 = getelementptr inbounds %struct.__SPI_Config, ptr %63, i32 0, i32 5
  %65 = load i32, ptr %64, align 4, !tbaa !23
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  ret i32 %65
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"__device_intrf", !6, i64 0, !10, i64 8, !6, i64 12, !13, i64 20, !10, i64 24, !7, i64 28, !10, i64 32, !14, i64 36, !14, i64 37, !7, i64 38, !7, i64 39, !15, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152}
!13 = !{!"atomic_flag", !7, i64 0}
!14 = !{!"_Bool", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!17, !6, i64 8}
!17 = !{!"", !10, i64 0, !10, i64 4, !6, i64 8, !6, i64 16}
!18 = !{!19, !10, i64 16}
!19 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32}
!20 = !{!17, !10, i64 4}
!21 = !{!19, !10, i64 0}
!22 = !{!17, !6, i64 16}
!23 = !{!24, !10, i64 24}
!24 = !{!"__SPI_Device", !25, i64 0, !12, i64 72, !10, i64 232, !10, i64 236, !7, i64 240, !7, i64 272, !7, i64 288, !7, i64 320}
!25 = !{!"__SPI_Config", !10, i64 0, !10, i64 4, !10, i64 8, !6, i64 12, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !14, i64 52, !14, i64 53, !10, i64 56, !7, i64 60, !6, i64 64}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local i32 @LpcSSPSetRate(ptr nocapture noundef readonly %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = load ptr, ptr %0, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %3, i64 8
  %5 = load ptr, ptr %4, align 8, !tbaa !14
  %6 = getelementptr inbounds i8, ptr %5, i64 16
  %7 = load volatile i32, ptr %6, align 4, !tbaa !16
  %8 = and i32 %7, 255
  %spec.store.select = tail call i32 @llvm.umax.i32(i32 %8, i32 1)
  %9 = mul i32 %spec.store.select, %1
  %10 = getelementptr inbounds i8, ptr %3, i64 4
  %11 = load i32, ptr %10, align 4, !tbaa !18
  %12 = ashr i32 %9, 1
  %13 = add i32 %12, %11
  %14 = udiv i32 %13, %9
  %15 = load volatile i32, ptr %5, align 4, !tbaa !19
  %16 = and i32 %15, -65281
  store volatile i32 %16, ptr %5, align 4, !tbaa !19
  %17 = shl i32 %14, 8
  %18 = add i32 %17, -256
  %19 = load volatile i32, ptr %5, align 4, !tbaa !19
  %20 = or i32 %19, %18
  store volatile i32 %20, ptr %5, align 4, !tbaa !19
  %21 = mul nsw i32 %14, %spec.store.select
  %22 = udiv i32 %11, %21
  %23 = getelementptr inbounds i8, ptr %3, i64 16
  %24 = load ptr, ptr %23, align 8, !tbaa !20
  %25 = getelementptr inbounds i8, ptr %24, i64 24
  store i32 %22, ptr %25, align 4, !tbaa !21
  ret i32 %22
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #1

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"__device_intrf", !7, i64 0, !10, i64 8, !7, i64 12, !11, i64 20, !10, i64 24, !8, i64 28, !10, i64 32, !12, i64 36, !12, i64 37, !8, i64 38, !8, i64 39, !13, i64 40, !7, i64 48, !7, i64 56, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"atomic_flag", !8, i64 0}
!12 = !{!"_Bool", !8, i64 0}
!13 = !{!"long", !8, i64 0}
!14 = !{!15, !7, i64 8}
!15 = !{!"", !10, i64 0, !10, i64 4, !7, i64 8, !7, i64 16}
!16 = !{!17, !10, i64 16}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32}
!18 = !{!15, !10, i64 4}
!19 = !{!17, !10, i64 0}
!20 = !{!15, !7, i64 16}
!21 = !{!22, !10, i64 24}
!22 = !{!"__SPI_Device", !23, i64 0, !6, i64 72, !10, i64 232, !10, i64 236, !8, i64 240, !8, i64 272, !8, i64 288, !8, i64 320}
!23 = !{!"__SPI_Config", !10, i64 0, !10, i64 4, !10, i64 8, !7, i64 12, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !12, i64 52, !12, i64 53, !10, i64 56, !8, i64 60, !7, i64 64}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass