; LLVM IR from siara-cc/Unishox_Arduino_lib :: src/unishox2.ll (Z10init_coderv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@usx_sets = external dso_local global [3 x [28 x i8]], align 16
@usx_code_94 = external dso_local global [94 x i8], align 16
@is_inited = external dso_local global i8, align 1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z10init_coderv() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = load i8, ptr @is_inited, align 1, !tbaa !5
  %6 = icmp ne i8 %5, 0
  br i1 %6, label %7, label %8

7:                                                ; preds = %0
  br label %69

8:                                                ; preds = %0
  call void @llvm.memset.p0.i64(ptr align 16 @usx_code_94, i8 0, i64 94, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #3
  store i32 0, ptr %1, align 4, !tbaa !8
  br label %9

9:                                                ; preds = %65, %8
  %10 = load i32, ptr %1, align 4, !tbaa !8
  %11 = icmp slt i32 %10, 3
  br i1 %11, label %13, label %12

12:                                               ; preds = %9
  store i32 2, ptr %2, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #3
  br label %68

13:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !8
  br label %14

14:                                               ; preds = %61, %13
  %15 = load i32, ptr %3, align 4, !tbaa !8
  %16 = icmp slt i32 %15, 28
  br i1 %16, label %18, label %17

17:                                               ; preds = %14
  store i32 5, ptr %2, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %64

18:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  %19 = load i32, ptr %1, align 4, !tbaa !8
  %20 = sext i32 %19 to i64
  %21 = getelementptr inbounds [3 x [28 x i8]], ptr @usx_sets, i64 0, i64 %20
  %22 = load i32, ptr %3, align 4, !tbaa !8
  %23 = sext i32 %22 to i64
  %24 = getelementptr inbounds [28 x i8], ptr %21, i64 0, i64 %23
  %25 = load i8, ptr %24, align 1, !tbaa !5
  store i8 %25, ptr %4, align 1, !tbaa !5
  %26 = load i8, ptr %4, align 1, !tbaa !5
  %27 = zext i8 %26 to i32
  %28 = icmp sgt i32 %27, 32
  br i1 %28, label %29, label %60

29:                                               ; preds = %18
  %30 = load i32, ptr %1, align 4, !tbaa !8
  %31 = shl i32 %30, 5
  %32 = load i32, ptr %3, align 4, !tbaa !8
  %33 = add nsw i32 %31, %32
  %34 = trunc i32 %33 to i8
  %35 = load i8, ptr %4, align 1, !tbaa !5
  %36 = zext i8 %35 to i32
  %37 = sub nsw i32 %36, 33
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %38
  store i8 %34, ptr %39, align 1, !tbaa !5
  %40 = load i8, ptr %4, align 1, !tbaa !5
  %41 = zext i8 %40 to i32
  %42 = icmp sge i32 %41, 97
  br i1 %42, label %43, label %59

43:                                               ; preds = %29
  %44 = load i8, ptr %4, align 1, !tbaa !5
  %45 = zext i8 %44 to i32
  %46 = icmp sle i32 %45, 122
  br i1 %46, label %47, label %59

47:                                               ; preds = %43
  %48 = load i32, ptr %1, align 4, !tbaa !8
  %49 = shl i32 %48, 5
  %50 = load i32, ptr %3, align 4, !tbaa !8
  %51 = add nsw i32 %49, %50
  %52 = trunc i32 %51 to i8
  %53 = load i8, ptr %4, align 1, !tbaa !5
  %54 = zext i8 %53 to i32
  %55 = sub nsw i32 %54, 33
  %56 = sub nsw i32 %55, 32
  %57 = sext i32 %56 to i64
  %58 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %57
  store i8 %52, ptr %58, align 1, !tbaa !5
  br label %59

59:                                               ; preds = %47, %43, %29
  br label %60

60:                                               ; preds = %59, %18
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  br label %61

61:                                               ; preds = %60
  %62 = load i32, ptr %3, align 4, !tbaa !8
  %63 = add nsw i32 %62, 1
  store i32 %63, ptr %3, align 4, !tbaa !8
  br label %14, !llvm.loop !10

64:                                               ; preds = %17
  br label %65

65:                                               ; preds = %64
  %66 = load i32, ptr %1, align 4, !tbaa !8
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %1, align 4, !tbaa !8
  br label %9, !llvm.loop !12

68:                                               ; preds = %12
  store i8 1, ptr @is_inited, align 1, !tbaa !5
  br label %69

69:                                               ; preds = %68, %7
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@usx_sets = external dso_local local_unnamed_addr global [3 x [28 x i8]], align 16
@usx_code_94 = external dso_local local_unnamed_addr global [94 x i8], align 16
@is_inited = external dso_local local_unnamed_addr global i8, align 1

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(readwrite, argmem: none, inaccessiblemem: none) uwtable
define dso_local void @_Z10init_coderv() local_unnamed_addr #0 {
  %1 = load i8, ptr @is_inited, align 1, !tbaa !5
  %.not = icmp eq i8 %1, 0
  br i1 %.not, label %.preheader, label %51

.preheader:                                       ; preds = %0
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(94) @usx_code_94, i8 0, i64 94, i1 false)
  br label %35

.preheader.1:                                     ; preds = %50, %17
  %indvars.iv.1 = phi i64 [ %indvars.iv.next.1, %17 ], [ 0, %50 ]
  %2 = getelementptr inbounds [3 x [28 x i8]], ptr @usx_sets, i64 0, i64 1, i64 %indvars.iv.1
  %3 = load i8, ptr %2, align 1, !tbaa !5
  %4 = icmp ugt i8 %3, 32
  br i1 %4, label %5, label %17

5:                                                ; preds = %.preheader.1
  %6 = zext i8 %3 to i32
  %7 = trunc i64 %indvars.iv.1 to i8
  %8 = add i8 %7, 32
  %9 = add nsw i32 %6, -33
  %10 = zext nneg i32 %9 to i64
  %11 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %10
  store i8 %8, ptr %11, align 1, !tbaa !5
  %12 = add i8 %3, -97
  %or.cond.1 = icmp ult i8 %12, 26
  br i1 %or.cond.1, label %13, label %17

13:                                               ; preds = %5
  %14 = add nsw i32 %6, -65
  %15 = zext nneg i32 %14 to i64
  %16 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %15
  store i8 %8, ptr %16, align 1, !tbaa !5
  br label %17

17:                                               ; preds = %13, %5, %.preheader.1
  %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv.1, 1
  %exitcond.1.not = icmp eq i64 %indvars.iv.next.1, 28
  br i1 %exitcond.1.not, label %.preheader.2, label %.preheader.1, !llvm.loop !8

.preheader.2:                                     ; preds = %17, %33
  %indvars.iv.2 = phi i64 [ %indvars.iv.next.2, %33 ], [ 0, %17 ]
  %18 = getelementptr inbounds [3 x [28 x i8]], ptr @usx_sets, i64 0, i64 2, i64 %indvars.iv.2
  %19 = load i8, ptr %18, align 1, !tbaa !5
  %20 = icmp ugt i8 %19, 32
  br i1 %20, label %21, label %33

21:                                               ; preds = %.preheader.2
  %22 = zext i8 %19 to i32
  %23 = trunc i64 %indvars.iv.2 to i8
  %24 = add i8 %23, 64
  %25 = add nsw i32 %22, -33
  %26 = zext nneg i32 %25 to i64
  %27 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %26
  store i8 %24, ptr %27, align 1, !tbaa !5
  %28 = add i8 %19, -97
  %or.cond.2 = icmp ult i8 %28, 26
  br i1 %or.cond.2, label %29, label %33

29:                                               ; preds = %21
  %30 = add nsw i32 %22, -65
  %31 = zext nneg i32 %30 to i64
  %32 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %31
  store i8 %24, ptr %32, align 1, !tbaa !5
  br label %33

33:                                               ; preds = %29, %21, %.preheader.2
  %indvars.iv.next.2 = add nuw nsw i64 %indvars.iv.2, 1
  %exitcond.2.not = icmp eq i64 %indvars.iv.next.2, 28
  br i1 %exitcond.2.not, label %34, label %.preheader.2, !llvm.loop !8

34:                                               ; preds = %33
  store i8 1, ptr @is_inited, align 1, !tbaa !5
  br label %51

35:                                               ; preds = %.preheader, %50
  %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %50 ]
  %36 = getelementptr inbounds [3 x [28 x i8]], ptr @usx_sets, i64 0, i64 0, i64 %indvars.iv
  %37 = load i8, ptr %36, align 1, !tbaa !5
  %38 = icmp ugt i8 %37, 32
  br i1 %38, label %39, label %50

39:                                               ; preds = %35
  %40 = zext i8 %37 to i32
  %41 = trunc i64 %indvars.iv to i8
  %42 = add nsw i32 %40, -33
  %43 = zext nneg i32 %42 to i64
  %44 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %43
  store i8 %41, ptr %44, align 1, !tbaa !5
  %45 = add i8 %37, -97
  %or.cond = icmp ult i8 %45, 26
  br i1 %or.cond, label %46, label %50

46:                                               ; preds = %39
  %47 = add nsw i32 %40, -65
  %48 = zext nneg i32 %47 to i64
  %49 = getelementptr inbounds [94 x i8], ptr @usx_code_94, i64 0, i64 %48
  store i8 %41, ptr %49, align 1, !tbaa !5
  br label %50

50:                                               ; preds = %39, %46, %35
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 28
  br i1 %exitcond.not, label %.preheader.1, label %35, !llvm.loop !8

51:                                               ; preds = %0, %34
  ret void
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(readwrite, argmem: none, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass