; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl1_xl_t = type { i8 }
%struct.lsm6dsl_ctrl8_xl_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_lp1_bandwidth_get(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %struct.lsm6dsl_ctrl1_xl_t, align 1
  %6 = alloca %struct.lsm6dsl_ctrl8_xl_t, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call i32 @lsm6dsl_read_reg(ptr noundef %8, i8 noundef zeroext 23, ptr noundef %6, i16 noundef zeroext 1)
  store i32 %9, ptr %7, align 4, !tbaa !9
  %10 = load i32, ptr %7, align 4, !tbaa !9
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %40

12:                                               ; preds = %2
  %13 = load i8, ptr %6, align 1
  %14 = lshr i8 %13, 7
  %15 = zext i8 %14 to i32
  %16 = icmp ne i32 %15, 0
  br i1 %16, label %23, label %17

17:                                               ; preds = %12
  %18 = load i8, ptr %6, align 1
  %19 = lshr i8 %18, 2
  %20 = and i8 %19, 1
  %21 = zext i8 %20 to i32
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %25

23:                                               ; preds = %17, %12
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 2, ptr %24, align 4, !tbaa !9
  br label %39

25:                                               ; preds = %17
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = call i32 @lsm6dsl_read_reg(ptr noundef %26, i8 noundef zeroext 16, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %27, ptr %7, align 4, !tbaa !9
  %28 = load i8, ptr %5, align 1
  %29 = lshr i8 %28, 1
  %30 = and i8 %29, 1
  %31 = zext i8 %30 to i32
  switch i32 %31, label %36 [
    i32 0, label %32
    i32 1, label %34
  ]

32:                                               ; preds = %25
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 0, ptr %33, align 4, !tbaa !9
  br label %38

34:                                               ; preds = %25
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 1, ptr %35, align 4, !tbaa !9
  br label %38

36:                                               ; preds = %25
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 2, ptr %37, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %36, %34, %32
  br label %39

39:                                               ; preds = %38, %23
  br label %40

40:                                               ; preds = %39, %2
  %41 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %41
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl1_xl_t = type { i8 }
%struct.lsm6dsl_ctrl8_xl_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_lp1_bandwidth_get(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_ctrl1_xl_t, align 1
  %4 = alloca %struct.lsm6dsl_ctrl8_xl_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #2
  %5 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 23, ptr noundef nonnull %4, i16 noundef zeroext 1)
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %7, label %14

7:                                                ; preds = %2
  %8 = load i8, ptr %4, align 1
  %9 = and i8 %8, -124
  %or.cond = icmp eq i8 %9, 0
  br i1 %or.cond, label %10, label %.sink.split

10:                                               ; preds = %7
  %11 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 16, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %12 = load i8, ptr %3, align 1
  %13 = lshr i8 %12, 1
  %.lobit = and i8 %13, 1
  %. = zext nneg i8 %.lobit to i32
  br label %.sink.split

.sink.split:                                      ; preds = %10, %7
  %.sink = phi i32 [ 2, %7 ], [ %., %10 ]
  %.0.ph = phi i32 [ 0, %7 ], [ %11, %10 ]
  store i32 %.sink, ptr %1, align 4, !tbaa !5
  br label %14

14:                                               ; preds = %.sink.split, %2
  %.0 = phi i32 [ %5, %2 ], [ %.0.ph, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass