; LLVM IR from siara-cc/Unishox_Arduino_lib :: src/unishox2.ll (Z20append_nibble_escapePciihPKhS1_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z11append_bitsPciihi(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z18append_switch_codePciih(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z20append_nibble_escapePciihPKhS1_(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, ptr noundef %4, ptr noundef %5) #1 {
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i8, align 1
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store i32 %1, ptr %9, align 4, !tbaa !9
  store i32 %2, ptr %10, align 4, !tbaa !9
  store i8 %3, ptr %11, align 1, !tbaa !11
  store ptr %4, ptr %12, align 8, !tbaa !5
  store ptr %5, ptr %13, align 8, !tbaa !5
  br label %18

18:                                               ; preds = %6
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = load i32, ptr %10, align 4, !tbaa !9
  %22 = load i8, ptr %11, align 1, !tbaa !11
  %23 = call noundef i32 @_Z18append_switch_codePciih(ptr noundef %19, i32 noundef %20, i32 noundef %21, i8 noundef zeroext %22)
  store i32 %23, ptr %10, align 4, !tbaa !9
  store i32 %23, ptr %14, align 4, !tbaa !9
  %24 = load i32, ptr %14, align 4, !tbaa !9
  %25 = icmp slt i32 %24, 0
  br i1 %25, label %26, label %28

26:                                               ; preds = %18
  %27 = load i32, ptr %14, align 4, !tbaa !9
  store i32 %27, ptr %7, align 4
  store i32 1, ptr %15, align 4
  br label %29

28:                                               ; preds = %18
  store i32 0, ptr %15, align 4
  br label %29

29:                                               ; preds = %28, %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  %30 = load i32, ptr %15, align 4
  switch i32 %30, label %71 [
    i32 0, label %31
    i32 1, label %69
  ]

31:                                               ; preds = %29
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  %34 = load ptr, ptr %8, align 8, !tbaa !5
  %35 = load i32, ptr %9, align 4, !tbaa !9
  %36 = load i32, ptr %10, align 4, !tbaa !9
  %37 = load ptr, ptr %12, align 8, !tbaa !5
  %38 = getelementptr inbounds i8, ptr %37, i64 2
  %39 = load i8, ptr %38, align 1, !tbaa !11
  %40 = load ptr, ptr %13, align 8, !tbaa !5
  %41 = getelementptr inbounds i8, ptr %40, i64 2
  %42 = load i8, ptr %41, align 1, !tbaa !11
  %43 = zext i8 %42 to i32
  %44 = call noundef i32 @_Z11append_bitsPciihi(ptr noundef %34, i32 noundef %35, i32 noundef %36, i8 noundef zeroext %39, i32 noundef %43)
  store i32 %44, ptr %10, align 4, !tbaa !9
  store i32 %44, ptr %16, align 4, !tbaa !9
  %45 = load i32, ptr %16, align 4, !tbaa !9
  %46 = icmp slt i32 %45, 0
  br i1 %46, label %47, label %49

47:                                               ; preds = %33
  %48 = load i32, ptr %16, align 4, !tbaa !9
  store i32 %48, ptr %7, align 4
  store i32 1, ptr %15, align 4
  br label %50

49:                                               ; preds = %33
  store i32 0, ptr %15, align 4
  br label %50

50:                                               ; preds = %49, %47
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  %51 = load i32, ptr %15, align 4
  switch i32 %51, label %71 [
    i32 0, label %52
    i32 1, label %69
  ]

52:                                               ; preds = %50
  br label %53

53:                                               ; preds = %52
  br label %54

54:                                               ; preds = %53
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #2
  %55 = load ptr, ptr %8, align 8, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !9
  %57 = load i32, ptr %10, align 4, !tbaa !9
  %58 = call noundef i32 @_Z11append_bitsPciihi(ptr noundef %55, i32 noundef %56, i32 noundef %57, i8 noundef zeroext 0, i32 noundef 2)
  store i32 %58, ptr %10, align 4, !tbaa !9
  store i32 %58, ptr %17, align 4, !tbaa !9
  %59 = load i32, ptr %17, align 4, !tbaa !9
  %60 = icmp slt i32 %59, 0
  br i1 %60, label %61, label %63

61:                                               ; preds = %54
  %62 = load i32, ptr %17, align 4, !tbaa !9
  store i32 %62, ptr %7, align 4
  store i32 1, ptr %15, align 4
  br label %64

63:                                               ; preds = %54
  store i32 0, ptr %15, align 4
  br label %64

64:                                               ; preds = %63, %61
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #2
  %65 = load i32, ptr %15, align 4
  switch i32 %65, label %71 [
    i32 0, label %66
    i32 1, label %69
  ]

66:                                               ; preds = %64
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %68, ptr %7, align 4
  br label %69

69:                                               ; preds = %67, %64, %50, %29
  %70 = load i32, ptr %7, align 4
  ret i32 %70

71:                                               ; preds = %64, %50, %29
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z11append_bitsPciihi(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z18append_switch_codePciih(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z20append_nibble_escapePciihPKhS1_(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, ptr nocapture noundef readonly %4, ptr nocapture noundef readonly %5) local_unnamed_addr #0 {
  %7 = tail call noundef i32 @_Z18append_switch_codePciih(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3)
  %8 = icmp sgt i32 %7, -1
  br i1 %8, label %9, label %19

9:                                                ; preds = %6
  %10 = getelementptr inbounds i8, ptr %4, i64 2
  %11 = load i8, ptr %10, align 1, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %5, i64 2
  %13 = load i8, ptr %12, align 1, !tbaa !5
  %14 = zext i8 %13 to i32
  %15 = tail call noundef i32 @_Z11append_bitsPciihi(ptr noundef %0, i32 noundef %1, i32 noundef %7, i8 noundef zeroext %11, i32 noundef %14)
  %16 = icmp sgt i32 %15, -1
  br i1 %16, label %17, label %19

17:                                               ; preds = %9
  %18 = tail call noundef i32 @_Z11append_bitsPciihi(ptr noundef %0, i32 noundef %1, i32 noundef %15, i8 noundef zeroext 0, i32 noundef 2)
  br label %19

19:                                               ; preds = %17, %9, %6
  %.3 = phi i32 [ %7, %6 ], [ %15, %9 ], [ %18, %17 ]
  ret i32 %.3
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass