; LLVM IR from VastoLorde95/Competitive-Programming :: Codeforces/256 Division 1/Problem C/C.ll (Z5queryiiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i32 }

@MOD = external dso_local global i32, align 4
@tree = external dso_local global [1048576 x %struct.node], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z5shiftiii(i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store i32 %0, ptr %7, align 4, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !5
  store i32 %3, ptr %10, align 4, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !5
  %16 = load i32, ptr %7, align 4, !tbaa !5
  %17 = load i32, ptr %11, align 4, !tbaa !5
  %18 = icmp sge i32 %16, %17
  br i1 %18, label %23, label %19

19:                                               ; preds = %5
  %20 = load i32, ptr %10, align 4, !tbaa !5
  %21 = load i32, ptr %8, align 4, !tbaa !5
  %22 = icmp sge i32 %20, %21
  br i1 %22, label %23, label %24

23:                                               ; preds = %19, %5
  store i32 0, ptr %6, align 4
  br label %72

24:                                               ; preds = %19
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = load i32, ptr %10, align 4, !tbaa !5
  %27 = icmp sle i32 %25, %26
  br i1 %27, label %28, label %38

28:                                               ; preds = %24
  %29 = load i32, ptr %11, align 4, !tbaa !5
  %30 = load i32, ptr %8, align 4, !tbaa !5
  %31 = icmp sle i32 %29, %30
  br i1 %31, label %32, label %38

32:                                               ; preds = %28
  %33 = load i32, ptr %9, align 4, !tbaa !5
  %34 = sext i32 %33 to i64
  %35 = getelementptr inbounds [1048576 x %struct.node], ptr @tree, i64 0, i64 %34
  %36 = getelementptr inbounds %struct.node, ptr %35, i32 0, i32 0
  %37 = load i32, ptr %36, align 4, !tbaa !9
  store i32 %37, ptr %6, align 4
  br label %72

38:                                               ; preds = %28, %24
  %39 = load i32, ptr %9, align 4, !tbaa !5
  %40 = load i32, ptr %10, align 4, !tbaa !5
  %41 = load i32, ptr %11, align 4, !tbaa !5
  call void @_Z5shiftiii(i32 noundef %39, i32 noundef %40, i32 noundef %41)
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %42 = load i32, ptr %9, align 4, !tbaa !5
  %43 = shl i32 %42, 1
  store i32 %43, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %44 = load i32, ptr %12, align 4, !tbaa !5
  %45 = add nsw i32 %44, 1
  store i32 %45, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  %46 = load i32, ptr %10, align 4, !tbaa !5
  %47 = load i32, ptr %11, align 4, !tbaa !5
  %48 = add nsw i32 %46, %47
  %49 = ashr i32 %48, 1
  store i32 %49, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %50 = load i32, ptr %7, align 4, !tbaa !5
  %51 = load i32, ptr %8, align 4, !tbaa !5
  %52 = load i32, ptr %12, align 4, !tbaa !5
  %53 = load i32, ptr %10, align 4, !tbaa !5
  %54 = load i32, ptr %14, align 4, !tbaa !5
  %55 = call noundef i32 @_Z5queryiiiii(i32 noundef %50, i32 noundef %51, i32 noundef %52, i32 noundef %53, i32 noundef %54)
  %56 = load i32, ptr %7, align 4, !tbaa !5
  %57 = load i32, ptr %8, align 4, !tbaa !5
  %58 = load i32, ptr %13, align 4, !tbaa !5
  %59 = load i32, ptr %14, align 4, !tbaa !5
  %60 = load i32, ptr %11, align 4, !tbaa !5
  %61 = call noundef i32 @_Z5queryiiiii(i32 noundef %56, i32 noundef %57, i32 noundef %58, i32 noundef %59, i32 noundef %60)
  %62 = add nsw i32 %55, %61
  store i32 %62, ptr %15, align 4, !tbaa !5
  %63 = load i32, ptr %15, align 4, !tbaa !5
  %64 = load i32, ptr @MOD, align 4, !tbaa !5
  %65 = icmp sge i32 %63, %64
  br i1 %65, label %66, label %70

66:                                               ; preds = %38
  %67 = load i32, ptr @MOD, align 4, !tbaa !5
  %68 = load i32, ptr %15, align 4, !tbaa !5
  %69 = sub nsw i32 %68, %67
  store i32 %69, ptr %15, align 4, !tbaa !5
  br label %70

70:                                               ; preds = %66, %38
  %71 = load i32, ptr %15, align 4, !tbaa !5
  store i32 %71, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %72

72:                                               ; preds = %70, %32, %23
  %73 = load i32, ptr %6, align 4
  ret i32 %73
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTS4node", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i32 }

@MOD = external dso_local local_unnamed_addr global i32, align 4
@tree = external dso_local local_unnamed_addr global [1048576 x %struct.node], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z5shiftiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %.not = icmp slt i32 %0, %4
  %.not37 = icmp slt i32 %3, %1
  %or.cond = and i1 %.not37, %.not
  br i1 %or.cond, label %6, label %common.ret42

6:                                                ; preds = %5
  %.not38 = icmp sgt i32 %0, %3
  %.not39 = icmp sgt i32 %4, %1
  %or.cond41 = or i1 %.not38, %.not39
  br i1 %or.cond41, label %11, label %7

7:                                                ; preds = %6
  %8 = sext i32 %2 to i64
  %9 = getelementptr inbounds [1048576 x %struct.node], ptr @tree, i64 0, i64 %8
  %10 = load i32, ptr %9, align 4, !tbaa !5
  br label %common.ret42

common.ret42:                                     ; preds = %5, %7, %11
  %common.ret42.op = phi i32 [ %spec.select, %11 ], [ %10, %7 ], [ 0, %5 ]
  ret i32 %common.ret42.op

11:                                               ; preds = %6
  tail call void @_Z5shiftiii(i32 noundef %2, i32 noundef %3, i32 noundef %4)
  %12 = shl i32 %2, 1
  %13 = or disjoint i32 %12, 1
  %14 = add nsw i32 %4, %3
  %15 = ashr i32 %14, 1
  %16 = tail call noundef i32 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %12, i32 noundef %3, i32 noundef %15)
  %17 = tail call noundef i32 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %13, i32 noundef %15, i32 noundef %4)
  %18 = add nsw i32 %17, %16
  %19 = load i32, ptr @MOD, align 4, !tbaa !10
  %.not40 = icmp slt i32 %18, %19
  %20 = select i1 %.not40, i32 0, i32 %19
  %spec.select = sub nsw i32 %18, %20
  br label %common.ret42
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS4node", !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass