; LLVM IR from Eclipse-SDV-Hackathon-Chapter-Two/challenge-threadx-and-beyond :: MXChip/AZ3166/lib/mxchip_bsp/stm_sensor/Src (lsm6dsl_reg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl1_xl_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_data_rate_get(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca %struct.lsm6dsl_ctrl1_xl_t, align 1
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = call i32 @lsm6dsl_read_reg(ptr noundef %7, i8 noundef zeroext 16, ptr noundef %5, i16 noundef zeroext 1)
  store i32 %8, ptr %6, align 4, !tbaa !9
  %9 = load i8, ptr %5, align 1
  %10 = lshr i8 %9, 4
  %11 = zext i8 %10 to i32
  switch i32 %11, label %36 [
    i32 0, label %12
    i32 1, label %14
    i32 2, label %16
    i32 3, label %18
    i32 4, label %20
    i32 5, label %22
    i32 6, label %24
    i32 7, label %26
    i32 8, label %28
    i32 9, label %30
    i32 10, label %32
    i32 11, label %34
  ]

12:                                               ; preds = %2
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %38

14:                                               ; preds = %2
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 1, ptr %15, align 4, !tbaa !9
  br label %38

16:                                               ; preds = %2
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 2, ptr %17, align 4, !tbaa !9
  br label %38

18:                                               ; preds = %2
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 3, ptr %19, align 4, !tbaa !9
  br label %38

20:                                               ; preds = %2
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 4, ptr %21, align 4, !tbaa !9
  br label %38

22:                                               ; preds = %2
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 5, ptr %23, align 4, !tbaa !9
  br label %38

24:                                               ; preds = %2
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 6, ptr %25, align 4, !tbaa !9
  br label %38

26:                                               ; preds = %2
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 7, ptr %27, align 4, !tbaa !9
  br label %38

28:                                               ; preds = %2
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 8, ptr %29, align 4, !tbaa !9
  br label %38

30:                                               ; preds = %2
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 9, ptr %31, align 4, !tbaa !9
  br label %38

32:                                               ; preds = %2
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 10, ptr %33, align 4, !tbaa !9
  br label %38

34:                                               ; preds = %2
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 11, ptr %35, align 4, !tbaa !9
  br label %38

36:                                               ; preds = %2
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  store i32 12, ptr %37, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %36, %34, %32, %30, %28, %26, %24, %22, %20, %18, %16, %14, %12
  %39 = load i32, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i32 %39
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.lsm6dsl_ctrl1_xl_t = type { i8 }

; Function Attrs: nounwind uwtable
declare dso_local i32 @lsm6dsl_read_reg(ptr noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @lsm6dsl_xl_data_rate_get(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = alloca %struct.lsm6dsl_ctrl1_xl_t, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #2
  %4 = call i32 @lsm6dsl_read_reg(ptr noundef %0, i8 noundef zeroext 16, ptr noundef nonnull %3, i16 noundef zeroext 1)
  %5 = load i8, ptr %3, align 1
  %6 = lshr i8 %5, 4
  %7 = icmp ult i8 %5, -64
  %narrow = select i1 %7, i8 %6, i8 12
  %.sink = zext nneg i8 %narrow to i32
  store i32 %.sink, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #2
  ret i32 %4
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass