; LLVM IR from IOsonata/IOsonata :: src/bluetooth (bt_uuid)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__Bt_Base_Uuid_Tbl_Entry = type { [16 x i8], i8 }

@_ZL15s_BtBaseUuidTbl = external hidden global [4 x %struct.__Bt_Base_Uuid_Tbl_Entry], align 4
@_ZL13s_NbUuidEntry = external hidden global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local i32 @BtUuidFindBase(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local i32 @BtUuidAddBase(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = call i32 @BtUuidFindBase(ptr noundef %7)
  %9 = trunc i32 %8 to i8
  store i8 %9, ptr %4, align 1, !tbaa !9
  %10 = load i8, ptr %4, align 1, !tbaa !9
  %11 = sext i8 %10 to i32
  %12 = icmp sge i32 %11, 0
  br i1 %12, label %13, label %16

13:                                               ; preds = %1
  %14 = load i8, ptr %4, align 1, !tbaa !9
  %15 = sext i8 %14 to i32
  store i32 %15, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %55

16:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 1, ptr %6, align 4, !tbaa !10
  br label %17

17:                                               ; preds = %49, %16
  %18 = load i32, ptr %6, align 4, !tbaa !10
  %19 = icmp slt i32 %18, 4
  br i1 %19, label %21, label %20

20:                                               ; preds = %17
  store i32 2, ptr %5, align 4
  br label %52

21:                                               ; preds = %17
  %22 = load i32, ptr %6, align 4, !tbaa !10
  %23 = sext i32 %22 to i64
  %24 = getelementptr inbounds [4 x %struct.__Bt_Base_Uuid_Tbl_Entry], ptr @_ZL15s_BtBaseUuidTbl, i64 0, i64 %23
  %25 = getelementptr inbounds %struct.__Bt_Base_Uuid_Tbl_Entry, ptr %24, i32 0, i32 1
  %26 = load i8, ptr %25, align 1, !tbaa !12, !range !15, !noundef !16
  %27 = trunc i8 %26 to i1
  %28 = zext i1 %27 to i32
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %48

30:                                               ; preds = %21
  %31 = load i32, ptr %6, align 4, !tbaa !10
  %32 = sext i32 %31 to i64
  %33 = getelementptr inbounds [4 x %struct.__Bt_Base_Uuid_Tbl_Entry], ptr @_ZL15s_BtBaseUuidTbl, i64 0, i64 %32
  %34 = getelementptr inbounds %struct.__Bt_Base_Uuid_Tbl_Entry, ptr %33, i32 0, i32 1
  store i8 1, ptr %34, align 1, !tbaa !12
  %35 = load i32, ptr %6, align 4, !tbaa !10
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds [4 x %struct.__Bt_Base_Uuid_Tbl_Entry], ptr @_ZL15s_BtBaseUuidTbl, i64 0, i64 %36
  %38 = getelementptr inbounds %struct.__Bt_Base_Uuid_Tbl_Entry, ptr %37, i32 0, i32 0
  %39 = getelementptr inbounds [16 x i8], ptr %38, i64 0, i64 0
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %39, ptr align 1 %40, i64 16, i1 false)
  %41 = load i32, ptr @_ZL13s_NbUuidEntry, align 4, !tbaa !10
  %42 = load i32, ptr %6, align 4, !tbaa !10
  %43 = icmp slt i32 %41, %42
  br i1 %43, label %44, label %46

44:                                               ; preds = %30
  %45 = load i32, ptr %6, align 4, !tbaa !10
  store i32 %45, ptr @_ZL13s_NbUuidEntry, align 4, !tbaa !10
  br label %46

46:                                               ; preds = %44, %30
  %47 = load i32, ptr %6, align 4, !tbaa !10
  store i32 %47, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %52

48:                                               ; preds = %21
  br label %49

49:                                               ; preds = %48
  %50 = load i32, ptr %6, align 4, !tbaa !10
  %51 = add nsw i32 %50, 1
  store i32 %51, ptr %6, align 4, !tbaa !10
  br label %17, !llvm.loop !17

52:                                               ; preds = %46, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %53 = load i32, ptr %5, align 4
  switch i32 %53, label %55 [
    i32 2, label %54
  ]

54:                                               ; preds = %52
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %55

55:                                               ; preds = %54, %52, %13
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  %56 = load i32, ptr %2, align 4
  ret i32 %56
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !14, i64 16}
!13 = !{!"_ZTS24__Bt_Base_Uuid_Tbl_Entry", !7, i64 0, !14, i64 16}
!14 = !{!"bool", !7, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__Bt_Base_Uuid_Tbl_Entry = type { [16 x i8], i8 }

@_ZL15s_BtBaseUuidTbl = external hidden local_unnamed_addr global [4 x %struct.__Bt_Base_Uuid_Tbl_Entry], align 4
@_ZL13s_NbUuidEntry = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local i32 @BtUuidFindBase(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local i32 @BtUuidAddBase(ptr noundef %0) local_unnamed_addr #0 {
  %2 = tail call i32 @BtUuidFindBase(ptr noundef %0)
  %sext = shl i32 %2, 24
  %3 = ashr exact i32 %sext, 24
  %4 = icmp sgt i32 %3, -1
  br i1 %4, label %.loopexit, label %.preheader.preheader

.preheader.preheader:                             ; preds = %1
  %5 = load i8, ptr getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 33), align 1, !tbaa !5, !range !10, !noundef !11
  %6 = icmp eq i8 %5, 0
  br i1 %6, label %7, label %.preheader.1

7:                                                ; preds = %.preheader.2, %.preheader.1, %.preheader.preheader
  %.019.lcssa.wide = phi i32 [ 1, %.preheader.preheader ], [ 2, %.preheader.1 ], [ 3, %.preheader.2 ]
  %.lcssa = phi ptr [ getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 17), %.preheader.preheader ], [ getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 34), %.preheader.1 ], [ getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 51), %.preheader.2 ]
  %8 = getelementptr inbounds i8, ptr %.lcssa, i64 16
  store i8 1, ptr %8, align 1, !tbaa !5
  tail call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(16) %.lcssa, ptr noundef nonnull align 1 dereferenceable(16) %0, i64 16, i1 false)
  %9 = load i32, ptr @_ZL13s_NbUuidEntry, align 4, !tbaa !12
  %10 = icmp slt i32 %9, %.019.lcssa.wide
  br i1 %10, label %11, label %.loopexit

11:                                               ; preds = %7
  store i32 %.019.lcssa.wide, ptr @_ZL13s_NbUuidEntry, align 4, !tbaa !12
  br label %.loopexit

.preheader.1:                                     ; preds = %.preheader.preheader
  %12 = load i8, ptr getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 50), align 2, !tbaa !5, !range !10, !noundef !11
  %13 = icmp eq i8 %12, 0
  br i1 %13, label %7, label %.preheader.2

.preheader.2:                                     ; preds = %.preheader.1
  %14 = load i8, ptr getelementptr inbounds (i8, ptr @_ZL15s_BtBaseUuidTbl, i64 67), align 1, !tbaa !5, !range !10, !noundef !11
  %15 = icmp eq i8 %14, 0
  br i1 %15, label %7, label %.loopexit

.loopexit:                                        ; preds = %.preheader.2, %11, %7, %1
  %.1 = phi i32 [ %3, %1 ], [ %.019.lcssa.wide, %7 ], [ %.019.lcssa.wide, %11 ], [ -1, %.preheader.2 ]
  ret i32 %.1
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 16}
!6 = !{!"_ZTS24__Bt_Base_Uuid_Tbl_Entry", !7, i64 0, !9, i64 16}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!"bool", !7, i64 0}
!10 = !{i8 0, i8 2}
!11 = !{}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass