; LLVM IR from FidoProject/Fido :: src (WireFitQLearn)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.rl::WireFitQLearn" = type { %"class.rl::Learner", ptr, ptr, ptr, i32, i32, double, double, double, double, i32, i32, %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", ptr }
%"class.rl::Learner" = type { ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.rl::Wire" = type { %"class.std::vector", double }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN2rl13WireFitQLearn15newControlWiresERKNS_4WireESt6vectorIS1_SaIS1_EE(ptr dead_on_unwind noalias writable sret(%"class.std::vector.8") align 8 %0, ptr noundef nonnull align 8 dereferenceable(184) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef %3) #2 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca double, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca double, align 8
  %14 = alloca i32, align 4
  %15 = alloca double, align 8
  store ptr %0, ptr %5, align 8
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %16 = load ptr, ptr %6, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #5
  store double 0.000000e+00, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 0, ptr %10, align 4, !tbaa !11
  br label %17

17:                                               ; preds = %169, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  store i32 0, ptr %11, align 4, !tbaa !11
  br label %18

18:                                               ; preds = %140, %17
  %19 = load i32, ptr %11, align 4, !tbaa !11
  %20 = zext i32 %19 to i64
  %21 = call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  %22 = icmp ult i64 %20, %21
  br i1 %22, label %24, label %23

23:                                               ; preds = %18
  store i32 4, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  br label %143

24:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #5
  %25 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 2
  %26 = load ptr, ptr %25, align 8, !tbaa !13
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = getelementptr inbounds %"struct.rl::Wire", ptr %27, i32 0, i32 0
  %29 = load ptr, ptr %26, align 8, !tbaa !20
  %30 = getelementptr inbounds ptr, ptr %29, i64 2
  %31 = load ptr, ptr %30, align 8
  %32 = call noundef double %31(ptr noundef nonnull align 8 dereferenceable(8) %26, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %28)
  %33 = fneg double %32
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = getelementptr inbounds %"struct.rl::Wire", ptr %34, i32 0, i32 1
  %36 = load double, ptr %35, align 8, !tbaa !22
  %37 = fadd double %33, %36
  %38 = fmul double -2.000000e+00, %37
  %39 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 2
  %40 = load ptr, ptr %39, align 8, !tbaa !13
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  %42 = getelementptr inbounds %"struct.rl::Wire", ptr %41, i32 0, i32 0
  %43 = load i32, ptr %11, align 4, !tbaa !11
  %44 = zext i32 %43 to i64
  %45 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %44) #5
  %46 = load ptr, ptr %40, align 8, !tbaa !20
  %47 = getelementptr inbounds ptr, ptr %46, i64 3
  %48 = load ptr, ptr %47, align 8
  %49 = call noundef double %48(ptr noundef nonnull align 8 dereferenceable(8) %40, ptr noundef nonnull align 8 dereferenceable(24) %42, ptr noundef nonnull align 8 dereferenceable(32) %45, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %50 = fmul double %38, %49
  store double %50, ptr %13, align 8, !tbaa !9
  %51 = load i32, ptr %11, align 4, !tbaa !11
  %52 = zext i32 %51 to i64
  %53 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %52) #5
  %54 = getelementptr inbounds %"struct.rl::Wire", ptr %53, i32 0, i32 1
  %55 = load double, ptr %54, align 8, !tbaa !22
  %56 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 9
  %57 = load double, ptr %56, align 8, !tbaa !24
  %58 = load double, ptr %13, align 8, !tbaa !9
  %59 = fneg double %57
  %60 = call double @llvm.fmuladd.f64(double %59, double %58, double %55)
  %61 = load i32, ptr %11, align 4, !tbaa !11
  %62 = zext i32 %61 to i64
  %63 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %62) #5
  %64 = getelementptr inbounds %"struct.rl::Wire", ptr %63, i32 0, i32 1
  store double %60, ptr %64, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #5
  store i32 0, ptr %14, align 4, !tbaa !11
  br label %65

65:                                               ; preds = %136, %24
  %66 = load i32, ptr %14, align 4, !tbaa !11
  %67 = zext i32 %66 to i64
  %68 = load i32, ptr %11, align 4, !tbaa !11
  %69 = zext i32 %68 to i64
  %70 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %69) #5
  %71 = getelementptr inbounds %"struct.rl::Wire", ptr %70, i32 0, i32 0
  %72 = call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %71) #5
  %73 = icmp ult i64 %67, %72
  br i1 %73, label %75, label %74

74:                                               ; preds = %65
  store i32 7, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #5
  br label %139

75:                                               ; preds = %65
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #5
  %76 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 2
  %77 = load ptr, ptr %76, align 8, !tbaa !13
  %78 = load ptr, ptr %7, align 8, !tbaa !5
  %79 = getelementptr inbounds %"struct.rl::Wire", ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %77, align 8, !tbaa !20
  %81 = getelementptr inbounds ptr, ptr %80, i64 2
  %82 = load ptr, ptr %81, align 8
  %83 = call noundef double %82(ptr noundef nonnull align 8 dereferenceable(8) %77, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %79)
  %84 = fneg double %83
  %85 = load ptr, ptr %7, align 8, !tbaa !5
  %86 = getelementptr inbounds %"struct.rl::Wire", ptr %85, i32 0, i32 1
  %87 = load double, ptr %86, align 8, !tbaa !22
  %88 = fadd double %84, %87
  %89 = fmul double -2.000000e+00, %88
  %90 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 2
  %91 = load ptr, ptr %90, align 8, !tbaa !13
  %92 = load ptr, ptr %7, align 8, !tbaa !5
  %93 = getelementptr inbounds %"struct.rl::Wire", ptr %92, i32 0, i32 0
  %94 = load i32, ptr %14, align 4, !tbaa !11
  %95 = zext i32 %94 to i64
  %96 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %93, i64 noundef %95) #5
  %97 = load double, ptr %96, align 8, !tbaa !9
  %98 = load i32, ptr %11, align 4, !tbaa !11
  %99 = zext i32 %98 to i64
  %100 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %99) #5
  %101 = getelementptr inbounds %"struct.rl::Wire", ptr %100, i32 0, i32 0
  %102 = load i32, ptr %14, align 4, !tbaa !11
  %103 = zext i32 %102 to i64
  %104 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %101, i64 noundef %103) #5
  %105 = load double, ptr %104, align 8, !tbaa !9
  %106 = load ptr, ptr %7, align 8, !tbaa !5
  %107 = getelementptr inbounds %"struct.rl::Wire", ptr %106, i32 0, i32 0
  %108 = load i32, ptr %11, align 4, !tbaa !11
  %109 = zext i32 %108 to i64
  %110 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %109) #5
  %111 = load ptr, ptr %91, align 8, !tbaa !20
  %112 = getelementptr inbounds ptr, ptr %111, i64 4
  %113 = load ptr, ptr %112, align 8
  %114 = call noundef double %113(ptr noundef nonnull align 8 dereferenceable(8) %91, double noundef %97, double noundef %105, ptr noundef nonnull align 8 dereferenceable(24) %107, ptr noundef nonnull align 8 dereferenceable(32) %110, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %115 = fmul double %89, %114
  store double %115, ptr %15, align 8, !tbaa !9
  %116 = load i32, ptr %11, align 4, !tbaa !11
  %117 = zext i32 %116 to i64
  %118 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %117) #5
  %119 = getelementptr inbounds %"struct.rl::Wire", ptr %118, i32 0, i32 0
  %120 = load i32, ptr %14, align 4, !tbaa !11
  %121 = zext i32 %120 to i64
  %122 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %119, i64 noundef %121) #5
  %123 = load double, ptr %122, align 8, !tbaa !9
  %124 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 9
  %125 = load double, ptr %124, align 8, !tbaa !24
  %126 = load double, ptr %15, align 8, !tbaa !9
  %127 = fneg double %125
  %128 = call double @llvm.fmuladd.f64(double %127, double %126, double %123)
  %129 = load i32, ptr %11, align 4, !tbaa !11
  %130 = zext i32 %129 to i64
  %131 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %130) #5
  %132 = getelementptr inbounds %"struct.rl::Wire", ptr %131, i32 0, i32 0
  %133 = load i32, ptr %14, align 4, !tbaa !11
  %134 = zext i32 %133 to i64
  %135 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %132, i64 noundef %134) #5
  store double %128, ptr %135, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #5
  br label %136

136:                                              ; preds = %75
  %137 = load i32, ptr %14, align 4, !tbaa !11
  %138 = add i32 %137, 1
  store i32 %138, ptr %14, align 4, !tbaa !11
  br label %65, !llvm.loop !25

139:                                              ; preds = %74
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #5
  br label %140

140:                                              ; preds = %139
  %141 = load i32, ptr %11, align 4, !tbaa !11
  %142 = add i32 %141, 1
  store i32 %142, ptr %11, align 4, !tbaa !11
  br label %18, !llvm.loop !27

143:                                              ; preds = %23
  %144 = load ptr, ptr %7, align 8, !tbaa !5
  %145 = getelementptr inbounds %"struct.rl::Wire", ptr %144, i32 0, i32 1
  %146 = load double, ptr %145, align 8, !tbaa !22
  %147 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 2
  %148 = load ptr, ptr %147, align 8, !tbaa !13
  %149 = load ptr, ptr %7, align 8, !tbaa !5
  %150 = getelementptr inbounds %"struct.rl::Wire", ptr %149, i32 0, i32 0
  %151 = load ptr, ptr %148, align 8, !tbaa !20
  %152 = getelementptr inbounds ptr, ptr %151, i64 2
  %153 = load ptr, ptr %152, align 8
  %154 = call noundef double %153(ptr noundef nonnull align 8 dereferenceable(8) %148, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %150)
  %155 = fsub double %146, %154
  %156 = call noundef double @_ZSt3powIdiEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(double noundef %155, i32 noundef 2)
  store double %156, ptr %9, align 8, !tbaa !9
  %157 = load i32, ptr %10, align 4, !tbaa !11
  %158 = add nsw i32 %157, 1
  store i32 %158, ptr %10, align 4, !tbaa !11
  br label %159

159:                                              ; preds = %143
  %160 = load double, ptr %9, align 8, !tbaa !9
  %161 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 8
  %162 = load double, ptr %161, align 8, !tbaa !28
  %163 = fcmp ogt double %160, %162
  br i1 %163, label %164, label %169

164:                                              ; preds = %159
  %165 = load i32, ptr %10, align 4, !tbaa !11
  %166 = getelementptr inbounds %"class.rl::WireFitQLearn", ptr %16, i32 0, i32 10
  %167 = load i32, ptr %166, align 8, !tbaa !29
  %168 = icmp slt i32 %165, %167
  br label %169

169:                                              ; preds = %164, %159
  %170 = phi i1 [ false, %159 ], [ %168, %164 ]
  br i1 %170, label %17, label %171, !llvm.loop !30

171:                                              ; preds = %169
  call void @_ZNSt6vectorIN2rl4WireESaIS1_EEC2EOS3_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  store i32 1, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef double @_ZSt3powIdiEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(double noundef, i32 noundef) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN2rl4WireESaIS1_EEC2EOS3_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 16}
!14 = !{!"_ZTSN2rl13WireFitQLearnE", !15, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !12, i64 32, !12, i64 36, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !12, i64 72, !12, i64 76, !16, i64 80, !16, i64 104, !16, i64 128, !16, i64 152, !6, i64 176}
!15 = !{!"_ZTSN2rl7LearnerE"}
!16 = !{!"_ZTSSt6vectorIdSaIdEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!21, !21, i64 0}
!21 = !{!"vtable pointer", !8, i64 0}
!22 = !{!23, !10, i64 24}
!23 = !{!"_ZTSN2rl4WireE", !16, i64 0, !10, i64 24}
!24 = !{!14, !10, i64 64}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = distinct !{!27, !26}
!28 = !{!14, !10, i64 56}
!29 = !{!14, !12, i64 72}
!30 = distinct !{!30, !26}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl" = type { %"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" }
%"struct.std::_Vector_base<rl::Wire, std::allocator<rl::Wire>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN2rl13WireFitQLearn15newControlWiresERKNS_4WireESt6vectorIS1_SaIS1_EE(ptr dead_on_unwind noalias writable sret(%"class.std::vector.8") align 8 %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(184) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef %3) local_unnamed_addr #1 align 2 {
  %5 = getelementptr inbounds i8, ptr %2, i64 24
  %6 = getelementptr inbounds i8, ptr %1, i64 16
  %7 = getelementptr inbounds i8, ptr %1, i64 64
  %8 = getelementptr inbounds i8, ptr %1, i64 56
  %9 = getelementptr inbounds i8, ptr %1, i64 72
  br label %10

10:                                               ; preds = %86, %4
  %.030 = phi i32 [ 0, %4 ], [ %87, %86 ]
  %11 = tail call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %.not = icmp eq i64 %11, 0
  br i1 %.not, label %._crit_edge39, label %.lr.ph38

._crit_edge39:                                    ; preds = %._crit_edge, %10
  %12 = load double, ptr %5, align 8, !tbaa !5
  %13 = load ptr, ptr %6, align 8, !tbaa !15
  %14 = load ptr, ptr %13, align 8, !tbaa !19
  %15 = getelementptr inbounds i8, ptr %14, i64 16
  %16 = load ptr, ptr %15, align 8
  %17 = tail call noundef double %16(ptr noundef nonnull align 8 dereferenceable(8) %13, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %18 = fsub double %12, %17
  %19 = tail call noundef double @_ZSt3powIdiEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(double noundef %18, i32 noundef 2)
  %20 = load double, ptr %8, align 8, !tbaa !21
  %21 = fcmp ogt double %19, %20
  br i1 %21, label %86, label %.critedge

.lr.ph38:                                         ; preds = %10, %._crit_edge
  %22 = phi i64 [ %49, %._crit_edge ], [ 0, %10 ]
  %.03136 = phi i32 [ %48, %._crit_edge ], [ 0, %10 ]
  %23 = load ptr, ptr %6, align 8, !tbaa !15
  %24 = load ptr, ptr %23, align 8, !tbaa !19
  %25 = getelementptr inbounds i8, ptr %24, i64 16
  %26 = load ptr, ptr %25, align 8
  %27 = tail call noundef double %26(ptr noundef nonnull align 8 dereferenceable(8) %23, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %28 = load double, ptr %5, align 8, !tbaa !5
  %29 = fsub double %28, %27
  %30 = fmul double %29, -2.000000e+00
  %31 = load ptr, ptr %6, align 8, !tbaa !15
  %32 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %33 = load ptr, ptr %31, align 8, !tbaa !19
  %34 = getelementptr inbounds i8, ptr %33, i64 24
  %35 = load ptr, ptr %34, align 8
  %36 = tail call noundef double %35(ptr noundef nonnull align 8 dereferenceable(8) %31, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(32) %32, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %37 = fmul double %30, %36
  %38 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %39 = getelementptr inbounds i8, ptr %38, i64 24
  %40 = load double, ptr %39, align 8, !tbaa !5
  %41 = load double, ptr %7, align 8, !tbaa !22
  %42 = fneg double %41
  %43 = tail call double @llvm.fmuladd.f64(double %42, double %37, double %40)
  %44 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %45 = getelementptr inbounds i8, ptr %44, i64 24
  store double %43, ptr %45, align 8, !tbaa !5
  %46 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %47 = tail call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %46) #4
  %.not40 = icmp eq i64 %47, 0
  br i1 %.not40, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %.lr.ph38
  %48 = add i32 %.03136, 1
  %49 = zext i32 %48 to i64
  %50 = tail call noundef i64 @_ZNKSt6vectorIN2rl4WireESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %51 = icmp ugt i64 %50, %49
  br i1 %51, label %.lr.ph38, label %._crit_edge39, !llvm.loop !23

.lr.ph:                                           ; preds = %.lr.ph38, %.lr.ph
  %52 = phi i64 [ %82, %.lr.ph ], [ 0, %.lr.ph38 ]
  %.035 = phi i32 [ %81, %.lr.ph ], [ 0, %.lr.ph38 ]
  %53 = load ptr, ptr %6, align 8, !tbaa !15
  %54 = load ptr, ptr %53, align 8, !tbaa !19
  %55 = getelementptr inbounds i8, ptr %54, i64 16
  %56 = load ptr, ptr %55, align 8
  %57 = tail call noundef double %56(ptr noundef nonnull align 8 dereferenceable(8) %53, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 8 dereferenceable(24) %2)
  %58 = load double, ptr %5, align 8, !tbaa !5
  %59 = fsub double %58, %57
  %60 = fmul double %59, -2.000000e+00
  %61 = load ptr, ptr %6, align 8, !tbaa !15
  %62 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %52) #4
  %63 = load double, ptr %62, align 8, !tbaa !25
  %64 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %65 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %64, i64 noundef %52) #4
  %66 = load double, ptr %65, align 8, !tbaa !25
  %67 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %68 = load ptr, ptr %61, align 8, !tbaa !19
  %69 = getelementptr inbounds i8, ptr %68, i64 32
  %70 = load ptr, ptr %69, align 8
  %71 = tail call noundef double %70(ptr noundef nonnull align 8 dereferenceable(8) %61, double noundef %63, double noundef %66, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(32) %67, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %72 = fmul double %60, %71
  %73 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %74 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %52) #4
  %75 = load double, ptr %74, align 8, !tbaa !25
  %76 = load double, ptr %7, align 8, !tbaa !22
  %77 = fneg double %76
  %78 = tail call double @llvm.fmuladd.f64(double %77, double %72, double %75)
  %79 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %80 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %79, i64 noundef %52) #4
  store double %78, ptr %80, align 8, !tbaa !25
  %81 = add i32 %.035, 1
  %82 = zext i32 %81 to i64
  %83 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorIN2rl4WireESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %22) #4
  %84 = tail call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %83) #4
  %85 = icmp ugt i64 %84, %82
  br i1 %85, label %.lr.ph, label %._crit_edge, !llvm.loop !26

86:                                               ; preds = %._crit_edge39
  %87 = add nuw nsw i32 %.030, 1
  %88 = load i32, ptr %9, align 8, !tbaa !27
  %89 = icmp slt i32 %87, %88
  br i1 %89, label %10, label %.critedge, !llvm.loop !28

.critedge:                                        ; preds = %._crit_edge39, %86
  tail call void @_ZNSt6vectorIN2rl4WireESaIS1_EEC2EOS3_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef double @_ZSt3powIdiEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(double noundef, i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN2rl4WireESaIS1_EEC2EOS3_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 24}
!6 = !{!"_ZTSN2rl4WireE", !7, i64 0, !14, i64 24}
!7 = !{!"_ZTSSt6vectorIdSaIdEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"double", !12, i64 0}
!15 = !{!16, !11, i64 16}
!16 = !{!"_ZTSN2rl13WireFitQLearnE", !17, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !18, i64 32, !18, i64 36, !14, i64 40, !14, i64 48, !14, i64 56, !14, i64 64, !18, i64 72, !18, i64 76, !7, i64 80, !7, i64 104, !7, i64 128, !7, i64 152, !11, i64 176}
!17 = !{!"_ZTSN2rl7LearnerE"}
!18 = !{!"int", !12, i64 0}
!19 = !{!20, !20, i64 0}
!20 = !{!"vtable pointer", !13, i64 0}
!21 = !{!16, !14, i64 56}
!22 = !{!16, !14, i64 64}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = !{!14, !14, i64 0}
!26 = distinct !{!26, !24}
!27 = !{!16, !18, i64 72}
!28 = distinct !{!28, !24}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass