; LLVM IR from IOsonata/IOsonata :: ARM/Nordic/nRF52/nRF52840/exemples/BoschAppBoard/src (bmi3)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.bmi3_axes_remap = type { i8, i8, i8, i8 }
%struct.bmi3_sens_config = type { i8, %union.bmi3_sens_config_types }
%union.bmi3_sens_config_types = type { %struct.bmi3_step_counter_config }
%struct.bmi3_step_counter_config = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }

@__const.bmi3_set_remap_axes.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_set_remap_axes(i32 %0, ptr noundef %1) #2 {
  %3 = alloca %struct.bmi3_axes_remap, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca %struct.bmi3_sens_config, align 8
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca [2 x i8], align 1
  %12 = alloca [4 x i8], align 1
  store i32 %0, ptr %3, align 1
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 46, ptr %6) #4
  call void @llvm.memset.p0.i64(ptr align 2 %6, i8 0, i64 46, i1 false)
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %11, ptr align 1 @__const.bmi3_set_remap_axes.base_addr, i64 2, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %13 = getelementptr inbounds [2 x i8], ptr %11, i64 0, i64 0
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef %13, i16 noundef zeroext 2, ptr noundef %14)
  store i8 %15, ptr %5, align 1, !tbaa !9
  %16 = load i8, ptr %5, align 1, !tbaa !9
  %17 = sext i8 %16 to i32
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %66

19:                                               ; preds = %2
  %20 = getelementptr inbounds %struct.bmi3_axes_remap, ptr %3, i32 0, i32 0
  %21 = load i8, ptr %20, align 1, !tbaa !10
  %22 = zext i8 %21 to i32
  %23 = and i32 %22, 7
  %24 = trunc i32 %23 to i8
  store i8 %24, ptr %7, align 1, !tbaa !9
  %25 = getelementptr inbounds %struct.bmi3_axes_remap, ptr %3, i32 0, i32 1
  %26 = load i8, ptr %25, align 1, !tbaa !12
  %27 = zext i8 %26 to i32
  %28 = shl i32 %27, 3
  %29 = and i32 %28, 8
  %30 = trunc i32 %29 to i8
  store i8 %30, ptr %8, align 1, !tbaa !9
  %31 = getelementptr inbounds %struct.bmi3_axes_remap, ptr %3, i32 0, i32 2
  %32 = load i8, ptr %31, align 1, !tbaa !13
  %33 = zext i8 %32 to i32
  %34 = shl i32 %33, 4
  %35 = and i32 %34, 16
  %36 = trunc i32 %35 to i8
  store i8 %36, ptr %9, align 1, !tbaa !9
  %37 = getelementptr inbounds %struct.bmi3_axes_remap, ptr %3, i32 0, i32 3
  %38 = load i8, ptr %37, align 1, !tbaa !14
  %39 = zext i8 %38 to i32
  %40 = shl i32 %39, 5
  %41 = and i32 %40, 32
  %42 = trunc i32 %41 to i8
  store i8 %42, ptr %10, align 1, !tbaa !9
  %43 = load i8, ptr %7, align 1, !tbaa !9
  %44 = zext i8 %43 to i32
  %45 = load i8, ptr %8, align 1, !tbaa !9
  %46 = zext i8 %45 to i32
  %47 = or i32 %44, %46
  %48 = load i8, ptr %9, align 1, !tbaa !9
  %49 = zext i8 %48 to i32
  %50 = or i32 %47, %49
  %51 = load i8, ptr %10, align 1, !tbaa !9
  %52 = zext i8 %51 to i32
  %53 = or i32 %50, %52
  %54 = trunc i32 %53 to i8
  %55 = getelementptr inbounds [4 x i8], ptr %12, i64 0, i64 0
  store i8 %54, ptr %55, align 1, !tbaa !9
  %56 = getelementptr inbounds [4 x i8], ptr %12, i64 0, i64 0
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 66, ptr noundef %56, i16 noundef zeroext 2, ptr noundef %57)
  store i8 %58, ptr %5, align 1, !tbaa !9
  %59 = load i8, ptr %5, align 1, !tbaa !9
  %60 = sext i8 %59 to i32
  %61 = icmp eq i32 %60, 0
  br i1 %61, label %62, label %65

62:                                               ; preds = %19
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  %64 = call signext i8 @axes_remap_acc_power_mode_status(ptr noundef byval(%struct.bmi3_sens_config) align 8 %6, ptr noundef %63)
  store i8 %64, ptr %5, align 1, !tbaa !9
  br label %65

65:                                               ; preds = %62, %19
  br label %66

66:                                               ; preds = %65, %2
  %67 = load i8, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 46, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i8 %67
}

; Function Attrs: nounwind uwtable
declare hidden signext i8 @axes_remap_acc_power_mode_status(ptr noundef byval(%struct.bmi3_sens_config) align 8, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !7, i64 0}
!11 = !{!"bmi3_axes_remap", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!12 = !{!11, !7, i64 1}
!13 = !{!11, !7, i64 2}
!14 = !{!11, !7, i64 3}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.bmi3_sens_config = type { i8, %union.bmi3_sens_config_types }
%union.bmi3_sens_config_types = type { %struct.bmi3_step_counter_config }
%struct.bmi3_step_counter_config = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }

@__const.bmi3_set_remap_axes.base_addr = external hidden unnamed_addr constant [2 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local signext i8 @bmi3_set_regs(i8 noundef zeroext, ptr noundef, i16 noundef zeroext, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local signext i8 @bmi3_set_remap_axes(i32 %0, ptr noundef %1) local_unnamed_addr #2 {
  %3 = alloca %struct.bmi3_sens_config, align 8
  %4 = alloca [2 x i8], align 2
  %5 = alloca [4 x i8], align 1
  call void @llvm.lifetime.start.p0(i64 46, ptr nonnull %3) #3
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(46) %3, i8 0, i64 46, i1 false)
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %4) #3
  %6 = load i16, ptr @__const.bmi3_set_remap_axes.base_addr, align 1
  store i16 %6, ptr %4, align 2
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #3
  %7 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 65, ptr noundef nonnull %4, i16 noundef zeroext 2, ptr noundef %1)
  %8 = icmp eq i8 %7, 0
  br i1 %8, label %9, label %25

9:                                                ; preds = %2
  %10 = and i32 %0, 7
  %11 = lshr i32 %0, 5
  %12 = and i32 %11, 8
  %13 = lshr i32 %0, 12
  %14 = and i32 %13, 16
  %15 = lshr i32 %0, 19
  %16 = and i32 %15, 32
  %17 = or disjoint i32 %12, %10
  %18 = or disjoint i32 %17, %14
  %19 = or disjoint i32 %18, %16
  %20 = trunc nuw nsw i32 %19 to i8
  store i8 %20, ptr %5, align 1, !tbaa !5
  %21 = call signext i8 @bmi3_set_regs(i8 noundef zeroext 66, ptr noundef nonnull %5, i16 noundef zeroext 2, ptr noundef %1)
  %22 = icmp eq i8 %21, 0
  br i1 %22, label %23, label %25

23:                                               ; preds = %9
  %24 = call signext i8 @axes_remap_acc_power_mode_status(ptr noundef nonnull byval(%struct.bmi3_sens_config) align 8 %3, ptr noundef %1)
  br label %25

25:                                               ; preds = %9, %23, %2
  %.0 = phi i8 [ %24, %23 ], [ %21, %9 ], [ %7, %2 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 46, ptr nonnull %3) #3
  ret i8 %.0
}

; Function Attrs: nounwind uwtable
declare hidden signext i8 @axes_remap_acc_power_mode_status(ptr noundef byval(%struct.bmi3_sens_config) align 8, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass