; LLVM IR from IOsonata/IOsonata :: src/bluetooth (bt_attreq)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__Bt_Hci_ACL_Data_Packet = type <{ %struct.__Bt_Hci_ACL_Data_Packet_Header, [1 x i8] }>
%struct.__Bt_Hci_ACL_Data_Packet_Header = type { i32 }
%struct.__Bt_L2Cap_Pdu = type <{ %struct.__Bt_L2Cap_Header, %union.anon }>
%struct.__Bt_L2Cap_Header = type { i16, i16 }
%union.anon = type <{ i32, [17 x i8] }>
%struct.__Bt_Attribute_Req_Rsp = type <{ i8, %union.anon.5 }>
%union.anon.5 = type { %struct.__Bt_Att_Read_By_Type_Req }
%struct.__Bt_Att_Read_By_Type_Req = type { i16, i16, %union.__Bt_Uuid_Val }
%union.__Bt_Uuid_Val = type { i32, [12 x i8] }
%struct.__Bt_Att_Read_By_Group_Type_Req = type { i16, i16, %union.__Bt_Uuid_Val }
%struct.__Bt_Uuid = type <{ i8, %union.anon.7 }>
%union.anon.7 = type { i32 }
%struct.__Bt_Hci_Device = type { ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare zeroext i1 @BtUuidTo128(ptr noundef, ptr noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local zeroext i1 @BtAttReadByGroupTypeRequest(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, ptr noundef %4) #2 {
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca ptr, align 8
  %11 = alloca [260 x i8], align 16
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i16 %1, ptr %7, align 2, !tbaa !9
  store i16 %2, ptr %8, align 2, !tbaa !9
  store i16 %3, ptr %9, align 2, !tbaa !9
  store ptr %4, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 260, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #3
  %15 = getelementptr inbounds [260 x i8], ptr %11, i64 0, i64 0
  store ptr %15, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  %16 = load ptr, ptr %12, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %16, i32 0, i32 1
  %18 = getelementptr inbounds [1 x i8], ptr %17, i64 0, i64 0
  store ptr %18, ptr %13, align 8, !tbaa !5
  %19 = load i16, ptr %7, align 2, !tbaa !9
  %20 = zext i16 %19 to i32
  %21 = load ptr, ptr %12, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %21, i32 0, i32 0
  %23 = load i32, ptr %22, align 1
  %24 = and i32 %20, 4095
  %25 = and i32 %23, -4096
  %26 = or i32 %25, %24
  store i32 %26, ptr %22, align 1
  %27 = load ptr, ptr %12, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 1
  %30 = and i32 %29, -12289
  %31 = or i32 %30, 12288
  store i32 %31, ptr %28, align 1
  %32 = load ptr, ptr %12, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %32, i32 0, i32 0
  %34 = load i32, ptr %33, align 1
  %35 = and i32 %34, -49153
  %36 = or i32 %35, 0
  store i32 %36, ptr %33, align 1
  %37 = load ptr, ptr %13, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %37, i32 0, i32 1
  %39 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %38, i32 0, i32 0
  store i8 16, ptr %39, align 1, !tbaa !11
  %40 = load i16, ptr %8, align 2, !tbaa !9
  %41 = load ptr, ptr %13, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %41, i32 0, i32 1
  %43 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %42, i32 0, i32 1
  %44 = getelementptr inbounds %struct.__Bt_Att_Read_By_Group_Type_Req, ptr %43, i32 0, i32 0
  store i16 %40, ptr %44, align 1, !tbaa !11
  %45 = load i16, ptr %9, align 2, !tbaa !9
  %46 = load ptr, ptr %13, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %46, i32 0, i32 1
  %48 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %47, i32 0, i32 1
  %49 = getelementptr inbounds %struct.__Bt_Att_Read_By_Group_Type_Req, ptr %48, i32 0, i32 1
  store i16 %45, ptr %49, align 1, !tbaa !11
  %50 = load ptr, ptr %13, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %50, i32 0, i32 0
  %52 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %51, i32 0, i32 0
  store i16 5, ptr %52, align 1, !tbaa !12
  %53 = load ptr, ptr %10, align 8, !tbaa !5
  %54 = load i8, ptr %53, align 1
  %55 = and i8 %54, 63
  %56 = zext i8 %55 to i32
  %57 = icmp sgt i32 %56, 0
  br i1 %57, label %58, label %73

58:                                               ; preds = %5
  %59 = load ptr, ptr %10, align 8, !tbaa !5
  %60 = load ptr, ptr %13, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %60, i32 0, i32 1
  %62 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %61, i32 0, i32 1
  %63 = getelementptr inbounds %struct.__Bt_Att_Read_By_Type_Req, ptr %62, i32 0, i32 2
  %64 = getelementptr inbounds [16 x i8], ptr %63, i64 0, i64 0
  %65 = call zeroext i1 @BtUuidTo128(ptr noundef %59, ptr noundef %64)
  %66 = load ptr, ptr %13, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %66, i32 0, i32 0
  %68 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %67, i32 0, i32 0
  %69 = load i16, ptr %68, align 1, !tbaa !12
  %70 = zext i16 %69 to i32
  %71 = add nsw i32 %70, 16
  %72 = trunc i32 %71 to i16
  store i16 %72, ptr %68, align 1, !tbaa !12
  br label %110

73:                                               ; preds = %5
  %74 = load ptr, ptr %10, align 8, !tbaa !5
  %75 = load i8, ptr %74, align 1
  %76 = lshr i8 %75, 6
  %77 = zext i8 %76 to i32
  %78 = icmp eq i32 %77, 1
  br i1 %78, label %79, label %94

79:                                               ; preds = %73
  %80 = load ptr, ptr %10, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.__Bt_Uuid, ptr %80, i32 0, i32 1
  %82 = load i32, ptr %81, align 1, !tbaa !11
  %83 = load ptr, ptr %13, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %83, i32 0, i32 1
  %85 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %84, i32 0, i32 1
  %86 = getelementptr inbounds %struct.__Bt_Att_Read_By_Type_Req, ptr %85, i32 0, i32 2
  store i32 %82, ptr %86, align 1, !tbaa !11
  %87 = load ptr, ptr %13, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %87, i32 0, i32 0
  %89 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %88, i32 0, i32 0
  %90 = load i16, ptr %89, align 1, !tbaa !12
  %91 = zext i16 %90 to i32
  %92 = add nsw i32 %91, 4
  %93 = trunc i32 %92 to i16
  store i16 %93, ptr %89, align 1, !tbaa !12
  br label %109

94:                                               ; preds = %73
  %95 = load ptr, ptr %10, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.__Bt_Uuid, ptr %95, i32 0, i32 1
  %97 = load i16, ptr %96, align 1, !tbaa !11
  %98 = load ptr, ptr %13, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %98, i32 0, i32 1
  %100 = getelementptr inbounds %struct.__Bt_Attribute_Req_Rsp, ptr %99, i32 0, i32 1
  %101 = getelementptr inbounds %struct.__Bt_Att_Read_By_Type_Req, ptr %100, i32 0, i32 2
  store i16 %97, ptr %101, align 1, !tbaa !11
  %102 = load ptr, ptr %13, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %102, i32 0, i32 0
  %104 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %103, i32 0, i32 0
  %105 = load i16, ptr %104, align 1, !tbaa !12
  %106 = zext i16 %105 to i32
  %107 = add nsw i32 %106, 2
  %108 = trunc i32 %107 to i16
  store i16 %108, ptr %104, align 1, !tbaa !12
  br label %109

109:                                              ; preds = %94, %79
  br label %110

110:                                              ; preds = %109, %58
  %111 = load ptr, ptr %13, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %111, i32 0, i32 0
  %113 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %112, i32 0, i32 1
  store i16 4, ptr %113, align 1, !tbaa !15
  %114 = load ptr, ptr %13, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.__Bt_L2Cap_Pdu, ptr %114, i32 0, i32 0
  %116 = getelementptr inbounds %struct.__Bt_L2Cap_Header, ptr %115, i32 0, i32 0
  %117 = load i16, ptr %116, align 1, !tbaa !12
  %118 = zext i16 %117 to i64
  %119 = add i64 %118, 4
  %120 = trunc i64 %119 to i32
  %121 = load ptr, ptr %12, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %121, i32 0, i32 0
  %123 = load i32, ptr %122, align 1
  %124 = and i32 %120, 65535
  %125 = shl i32 %124, 16
  %126 = and i32 %123, 65535
  %127 = or i32 %126, %125
  store i32 %127, ptr %122, align 1
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  %128 = load ptr, ptr %6, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.__Bt_Hci_Device, ptr %128, i32 0, i32 3
  %130 = load ptr, ptr %129, align 8, !tbaa !16
  %131 = load ptr, ptr %12, align 8, !tbaa !5
  %132 = load ptr, ptr %12, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.__Bt_Hci_ACL_Data_Packet, ptr %132, i32 0, i32 0
  %134 = load i32, ptr %133, align 1
  %135 = lshr i32 %134, 16
  %136 = zext i32 %135 to i64
  %137 = add i64 %136, 4
  %138 = trunc i64 %137 to i32
  %139 = call noundef i32 %130(ptr noundef %131, i32 noundef %138)
  store i32 %139, ptr %14, align 4, !tbaa !19
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 260, ptr %11) #3
  ret i1 true
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 0}
!13 = !{!"_ZTS14__Bt_L2Cap_Pdu", !14, i64 0, !7, i64 4}
!14 = !{!"_ZTS17__Bt_L2Cap_Header", !10, i64 0, !10, i64 2}
!15 = !{!13, !10, i64 2}
!16 = !{!17, !6, i64 16}
!17 = !{!"_ZTS15__Bt_Hci_Device", !6, i64 0, !18, i64 8, !18, i64 12, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !6, i64 64}
!18 = !{!"int", !7, i64 0}
!19 = !{!18, !18, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare zeroext i1 @BtUuidTo128(ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @BtAttReadByGroupTypeRequest(ptr nocapture noundef readonly %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, ptr noundef %4) local_unnamed_addr #2 {
  %6 = alloca [260 x i8], align 16
  call void @llvm.lifetime.start.p0(i64 260, ptr nonnull %6) #3
  %7 = getelementptr inbounds i8, ptr %6, i64 4
  %8 = and i16 %1, 4095
  %9 = or disjoint i16 %8, 12288
  %10 = zext nneg i16 %9 to i32
  store i32 %10, ptr %6, align 16
  %11 = getelementptr inbounds i8, ptr %6, i64 8
  store i8 16, ptr %11, align 8, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %6, i64 9
  store i16 %2, ptr %12, align 1, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %6, i64 11
  store i16 %3, ptr %13, align 1, !tbaa !5
  store i16 5, ptr %7, align 4, !tbaa !8
  %14 = load i8, ptr %4, align 1
  %15 = and i8 %14, 63
  %.not = icmp eq i8 %15, 0
  br i1 %.not, label %23, label %16

16:                                               ; preds = %5
  %17 = getelementptr inbounds i8, ptr %6, i64 13
  %18 = call zeroext i1 @BtUuidTo128(ptr noundef nonnull %4, ptr noundef nonnull %17)
  %19 = load i16, ptr %7, align 4, !tbaa !8
  %20 = add i16 %19, 16
  store i16 %20, ptr %7, align 4, !tbaa !8
  %.pre = load i32, ptr %6, align 16
  %21 = add i16 %19, 20
  %22 = zext i16 %21 to i32
  br label %31

23:                                               ; preds = %5
  %24 = icmp eq i8 %14, 64
  %25 = getelementptr inbounds i8, ptr %4, i64 1
  %26 = getelementptr inbounds i8, ptr %6, i64 13
  br i1 %24, label %27, label %29

27:                                               ; preds = %23
  %28 = load i32, ptr %25, align 1, !tbaa !5
  store i32 %28, ptr %26, align 1, !tbaa !5
  store i16 9, ptr %7, align 4, !tbaa !8
  br label %31

29:                                               ; preds = %23
  %30 = load i16, ptr %25, align 1, !tbaa !5
  store i16 %30, ptr %26, align 1, !tbaa !5
  store i16 7, ptr %7, align 4, !tbaa !8
  br label %31

31:                                               ; preds = %27, %29, %16
  %32 = phi i32 [ %10, %27 ], [ %10, %29 ], [ %.pre, %16 ]
  %33 = phi i32 [ 13, %27 ], [ 11, %29 ], [ %22, %16 ]
  %34 = getelementptr inbounds i8, ptr %6, i64 6
  store i16 4, ptr %34, align 2, !tbaa !12
  %35 = shl nuw i32 %33, 16
  %36 = and i32 %32, 65535
  %37 = or disjoint i32 %35, %36
  store i32 %37, ptr %6, align 16
  %38 = getelementptr inbounds i8, ptr %0, i64 16
  %39 = load ptr, ptr %38, align 8, !tbaa !13
  %40 = add nuw nsw i32 %33, 4
  %41 = call noundef i32 %39(ptr noundef nonnull %6, i32 noundef %40)
  call void @llvm.lifetime.end.p0(i64 260, ptr nonnull %6) #3
  ret i1 true
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !11, i64 0}
!9 = !{!"_ZTS14__Bt_L2Cap_Pdu", !10, i64 0, !6, i64 4}
!10 = !{!"_ZTS17__Bt_L2Cap_Header", !11, i64 0, !11, i64 2}
!11 = !{!"short", !6, i64 0}
!12 = !{!9, !11, i64 2}
!13 = !{!14, !15, i64 16}
!14 = !{!"_ZTS15__Bt_Hci_Device", !15, i64 0, !16, i64 8, !16, i64 12, !15, i64 16, !15, i64 24, !15, i64 32, !15, i64 40, !15, i64 48, !15, i64 56, !15, i64 64}
!15 = !{!"any pointer", !6, i64 0}
!16 = !{!"int", !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass