; LLVM IR from IOsonata/IOsonata :: src (device_intrf)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__device_intrf = type <{ ptr, i32, ptr, %"struct.std::atomic_flag", [3 x i8], i32, %"struct.std::atomic", i32, i8, i8, %"struct.std::atomic.0", %"struct.std::atomic.0", i64, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }>
%"struct.std::atomic_flag" = type { %"struct.std::__atomic_flag_base" }
%"struct.std::__atomic_flag_base" = type { i8 }
%"struct.std::atomic" = type { %"struct.std::__atomic_base" }
%"struct.std::__atomic_base" = type { i32 }
%"struct.std::atomic.0" = type { %"struct.std::__atomic_base.1" }
%"struct.std::__atomic_base.1" = type { i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1), i1 noundef zeroext) #1 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden void @_ZL17DeviceIntrfStopRxP14__device_intrf(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL18DeviceIntrfStartTxP14__device_intrfj(ptr noundef, i32 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z25DeviceIntrfWaitTxCompleteP14__device_intrfi(ptr noundef, i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local i32 @DeviceIntrfRead(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5) #3 {
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store i32 %1, ptr %9, align 4, !tbaa !9
  store ptr %2, ptr %10, align 8, !tbaa !5
  store i32 %3, ptr %11, align 4, !tbaa !9
  store ptr %4, ptr %12, align 8, !tbaa !5
  store i32 %5, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  store i32 0, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  %17 = load ptr, ptr %8, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__device_intrf, ptr %17, i32 0, i32 5
  %19 = load i32, ptr %18, align 4, !tbaa !11
  store i32 %19, ptr %15, align 4, !tbaa !9
  %20 = load ptr, ptr %12, align 8, !tbaa !5
  %21 = icmp eq ptr %20, null
  br i1 %21, label %25, label %22

22:                                               ; preds = %6
  %23 = load i32, ptr %13, align 4, !tbaa !9
  %24 = icmp sle i32 %23, 0
  br i1 %24, label %25, label %26

25:                                               ; preds = %22, %6
  store i32 0, ptr %7, align 4
  store i32 1, ptr %16, align 4
  br label %99

26:                                               ; preds = %22
  br label %27

27:                                               ; preds = %95, %26
  %28 = load ptr, ptr %8, align 8, !tbaa !5
  %29 = load i32, ptr %9, align 4, !tbaa !9
  %30 = call noundef zeroext i1 @_ZL18DeviceIntrfStartTxP14__device_intrfj(ptr noundef %28, i32 noundef %29)
  br i1 %30, label %31, label %87

31:                                               ; preds = %27
  %32 = load ptr, ptr %10, align 8, !tbaa !5
  %33 = icmp ne ptr %32, null
  br i1 %33, label %34, label %68

34:                                               ; preds = %31
  %35 = load ptr, ptr %8, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.__device_intrf, ptr %35, i32 0, i32 11
  %37 = call noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) %36, i1 noundef zeroext true) #4
  %38 = load ptr, ptr %8, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.__device_intrf, ptr %38, i32 0, i32 22
  %40 = load ptr, ptr %39, align 4, !tbaa !22
  %41 = icmp ne ptr %40, null
  br i1 %41, label %42, label %50

42:                                               ; preds = %34
  %43 = load ptr, ptr %8, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.__device_intrf, ptr %43, i32 0, i32 22
  %45 = load ptr, ptr %44, align 4, !tbaa !22
  %46 = load ptr, ptr %8, align 8, !tbaa !5
  %47 = load ptr, ptr %10, align 8, !tbaa !5
  %48 = load i32, ptr %11, align 4, !tbaa !9
  %49 = call noundef i32 %45(ptr noundef %46, ptr noundef %47, i32 noundef %48)
  store i32 %49, ptr %14, align 4, !tbaa !9
  br label %58

50:                                               ; preds = %34
  %51 = load ptr, ptr %8, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.__device_intrf, ptr %51, i32 0, i32 21
  %53 = load ptr, ptr %52, align 4, !tbaa !23
  %54 = load ptr, ptr %8, align 8, !tbaa !5
  %55 = load ptr, ptr %10, align 8, !tbaa !5
  %56 = load i32, ptr %11, align 4, !tbaa !9
  %57 = call noundef i32 %53(ptr noundef %54, ptr noundef %55, i32 noundef %56)
  store i32 %57, ptr %14, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %50, %42
  %59 = load i32, ptr %14, align 4, !tbaa !9
  %60 = icmp slt i32 %59, 0
  br i1 %60, label %61, label %64

61:                                               ; preds = %58
  %62 = load ptr, ptr %8, align 8, !tbaa !5
  %63 = call noundef zeroext i1 @_Z25DeviceIntrfWaitTxCompleteP14__device_intrfi(ptr noundef %62, i32 noundef 1000000)
  br label %64

64:                                               ; preds = %61, %58
  %65 = load ptr, ptr %8, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.__device_intrf, ptr %65, i32 0, i32 11
  %67 = call noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) %66, i1 noundef zeroext false) #4
  br label %68

68:                                               ; preds = %64, %31
  %69 = load ptr, ptr %8, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__device_intrf, ptr %69, i32 0, i32 17
  %71 = load ptr, ptr %70, align 4, !tbaa !24
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = load i32, ptr %9, align 4, !tbaa !9
  %74 = call noundef zeroext i1 %71(ptr noundef %72, i32 noundef %73)
  %75 = load ptr, ptr %8, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.__device_intrf, ptr %75, i32 0, i32 18
  %77 = load ptr, ptr %76, align 4, !tbaa !25
  %78 = load ptr, ptr %8, align 8, !tbaa !5
  %79 = load ptr, ptr %12, align 8, !tbaa !5
  %80 = load i32, ptr %13, align 4, !tbaa !9
  %81 = call noundef i32 %77(ptr noundef %78, ptr noundef %79, i32 noundef %80)
  store i32 %81, ptr %14, align 4, !tbaa !9
  %82 = load i32, ptr %14, align 4, !tbaa !9
  %83 = icmp slt i32 %82, 0
  br i1 %83, label %84, label %85

84:                                               ; preds = %68
  br label %97

85:                                               ; preds = %68
  %86 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_ZL17DeviceIntrfStopRxP14__device_intrf(ptr noundef %86)
  br label %87

87:                                               ; preds = %85, %27
  br label %88

88:                                               ; preds = %87
  %89 = load i32, ptr %14, align 4, !tbaa !9
  %90 = icmp sle i32 %89, 0
  br i1 %90, label %91, label %95

91:                                               ; preds = %88
  %92 = load i32, ptr %15, align 4, !tbaa !9
  %93 = add nsw i32 %92, -1
  store i32 %93, ptr %15, align 4, !tbaa !9
  %94 = icmp sgt i32 %92, 0
  br label %95

95:                                               ; preds = %91, %88
  %96 = phi i1 [ false, %88 ], [ %94, %91 ]
  br i1 %96, label %27, label %97, !llvm.loop !26

97:                                               ; preds = %95, %84
  %98 = load i32, ptr %14, align 4, !tbaa !9
  store i32 %98, ptr %7, align 4
  store i32 1, ptr %16, align 4
  br label %99

99:                                               ; preds = %97, %25
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  %100 = load i32, ptr %7, align 4
  ret i32 %100
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 24}
!12 = !{!"_ZTS14__device_intrf", !6, i64 0, !10, i64 8, !6, i64 12, !13, i64 20, !10, i64 24, !16, i64 28, !18, i64 32, !15, i64 36, !15, i64 37, !19, i64 38, !19, i64 39, !21, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152}
!13 = !{!"_ZTSSt11atomic_flag", !14, i64 0}
!14 = !{!"_ZTSSt18__atomic_flag_base", !15, i64 0}
!15 = !{!"bool", !7, i64 0}
!16 = !{!"_ZTSSt6atomicIiE", !17, i64 0}
!17 = !{!"_ZTSSt13__atomic_baseIiE", !10, i64 0}
!18 = !{!"_ZTS16__Dev_Intrf_Type", !7, i64 0}
!19 = !{!"_ZTSSt6atomicIbE", !20, i64 0}
!20 = !{!"_ZTSSt13__atomic_baseIbE", !15, i64 0}
!21 = !{!"long", !7, i64 0}
!22 = !{!12, !6, i64 120}
!23 = !{!12, !6, i64 112}
!24 = !{!12, !6, i64 80}
!25 = !{!12, !6, i64 88}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1), i1 noundef zeroext) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden void @_ZL17DeviceIntrfStopRxP14__device_intrf(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL18DeviceIntrfStartTxP14__device_intrfj(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z25DeviceIntrfWaitTxCompleteP14__device_intrfi(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local i32 @DeviceIntrfRead(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, ptr noundef %4, i32 noundef %5) local_unnamed_addr #2 {
  %7 = icmp eq ptr %4, null
  %8 = icmp slt i32 %5, 1
  %or.cond = or i1 %7, %8
  br i1 %or.cond, label %.critedge, label %.preheader

.preheader:                                       ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 24
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %.not = icmp eq ptr %2, null
  %11 = getelementptr inbounds i8, ptr %0, i64 39
  %12 = getelementptr inbounds i8, ptr %0, i64 120
  %13 = getelementptr inbounds i8, ptr %0, i64 112
  %14 = getelementptr inbounds i8, ptr %0, i64 80
  %15 = getelementptr inbounds i8, ptr %0, i64 88
  br i1 %.not, label %.preheader.split.us, label %.preheader.split

.preheader.split.us:                              ; preds = %.preheader, %24
  %.032.us = phi i32 [ %.2.us, %24 ], [ 0, %.preheader ]
  %.0.us = phi i32 [ %26, %24 ], [ %10, %.preheader ]
  %16 = tail call noundef zeroext i1 @_ZL18DeviceIntrfStartTxP14__device_intrfj(ptr noundef %0, i32 noundef %1)
  br i1 %16, label %17, label %24

17:                                               ; preds = %.preheader.split.us
  %18 = load ptr, ptr %14, align 4, !tbaa !20
  %19 = tail call noundef zeroext i1 %18(ptr noundef %0, i32 noundef %1)
  %20 = load ptr, ptr %15, align 4, !tbaa !21
  %21 = tail call noundef i32 %20(ptr noundef %0, ptr noundef %4, i32 noundef %5)
  %22 = icmp slt i32 %21, 0
  br i1 %22, label %.critedge, label %23

23:                                               ; preds = %17
  tail call void @_ZL17DeviceIntrfStopRxP14__device_intrf(ptr noundef nonnull %0)
  br label %24

24:                                               ; preds = %23, %.preheader.split.us
  %.2.us = phi i32 [ %21, %23 ], [ %.032.us, %.preheader.split.us ]
  %25 = icmp slt i32 %.2.us, 1
  %26 = add nsw i32 %.0.us, -1
  %27 = icmp sgt i32 %.0.us, 0
  %or.cond40.us = select i1 %25, i1 %27, i1 false
  br i1 %or.cond40.us, label %.preheader.split.us, label %.critedge, !llvm.loop !22

.preheader.split:                                 ; preds = %.preheader, %47
  %.032 = phi i32 [ %.2, %47 ], [ 0, %.preheader ]
  %.0 = phi i32 [ %49, %47 ], [ %10, %.preheader ]
  %28 = tail call noundef zeroext i1 @_ZL18DeviceIntrfStartTxP14__device_intrfj(ptr noundef %0, i32 noundef %1)
  br i1 %28, label %29, label %47

29:                                               ; preds = %.preheader.split
  %30 = tail call noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) %11, i1 noundef zeroext true) #3
  %31 = load ptr, ptr %12, align 4, !tbaa !24
  %.not38 = icmp eq ptr %31, null
  br i1 %.not38, label %32, label %34

32:                                               ; preds = %29
  %33 = load ptr, ptr %13, align 4, !tbaa !25
  br label %34

34:                                               ; preds = %29, %32
  %.sink = phi ptr [ %33, %32 ], [ %31, %29 ]
  %35 = tail call noundef i32 %.sink(ptr noundef nonnull %0, ptr noundef nonnull %2, i32 noundef %3)
  %36 = icmp slt i32 %35, 0
  br i1 %36, label %37, label %39

37:                                               ; preds = %34
  %38 = tail call noundef zeroext i1 @_Z25DeviceIntrfWaitTxCompleteP14__device_intrfi(ptr noundef nonnull %0, i32 noundef 1000000)
  br label %39

39:                                               ; preds = %37, %34
  %40 = tail call noundef zeroext i1 @_ZNSt6atomicIbEaSEb(ptr noundef nonnull align 1 dereferenceable(1) %11, i1 noundef zeroext false) #3
  %41 = load ptr, ptr %14, align 4, !tbaa !20
  %42 = tail call noundef zeroext i1 %41(ptr noundef nonnull %0, i32 noundef %1)
  %43 = load ptr, ptr %15, align 4, !tbaa !21
  %44 = tail call noundef i32 %43(ptr noundef nonnull %0, ptr noundef %4, i32 noundef %5)
  %45 = icmp slt i32 %44, 0
  br i1 %45, label %.critedge, label %46

46:                                               ; preds = %39
  tail call void @_ZL17DeviceIntrfStopRxP14__device_intrf(ptr noundef nonnull %0)
  br label %47

47:                                               ; preds = %.preheader.split, %46
  %.2 = phi i32 [ %44, %46 ], [ %.032, %.preheader.split ]
  %48 = icmp slt i32 %.2, 1
  %49 = add nsw i32 %.0, -1
  %50 = icmp sgt i32 %.0, 0
  %or.cond40 = select i1 %48, i1 %50, i1 false
  br i1 %or.cond40, label %.preheader.split, label %.critedge, !llvm.loop !22

.critedge:                                        ; preds = %47, %39, %24, %17, %6
  %.033 = phi i32 [ 0, %6 ], [ %.2.us, %24 ], [ %21, %17 ], [ %.2, %47 ], [ %44, %39 ]
  ret i32 %.033
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 24}
!6 = !{!"_ZTS14__device_intrf", !7, i64 0, !10, i64 8, !7, i64 12, !11, i64 20, !10, i64 24, !14, i64 28, !16, i64 32, !13, i64 36, !13, i64 37, !17, i64 38, !17, i64 39, !19, i64 40, !7, i64 48, !7, i64 56, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"_ZTSSt11atomic_flag", !12, i64 0}
!12 = !{!"_ZTSSt18__atomic_flag_base", !13, i64 0}
!13 = !{!"bool", !8, i64 0}
!14 = !{!"_ZTSSt6atomicIiE", !15, i64 0}
!15 = !{!"_ZTSSt13__atomic_baseIiE", !10, i64 0}
!16 = !{!"_ZTS16__Dev_Intrf_Type", !8, i64 0}
!17 = !{!"_ZTSSt6atomicIbE", !18, i64 0}
!18 = !{!"_ZTSSt13__atomic_baseIbE", !13, i64 0}
!19 = !{!"long", !8, i64 0}
!20 = !{!6, !7, i64 80}
!21 = !{!6, !7, i64 88}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = !{!6, !7, i64 120}
!25 = !{!6, !7, i64 112}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass