; LLVM IR from siara-cc/Unishox_Arduino_lib :: src/unishox2.ll (Z18append_switch_codePciih)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z11append_bitsPciihi(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z18append_switch_codePciih(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i8 %3, ptr %9, align 1, !tbaa !11
  %14 = load i8, ptr %9, align 1, !tbaa !11
  %15 = zext i8 %14 to i32
  %16 = icmp eq i32 %15, 4
  br i1 %16, label %17, label %46

17:                                               ; preds = %4
  br label %18

18:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = load i32, ptr %7, align 4, !tbaa !9
  %21 = load i32, ptr %8, align 4, !tbaa !9
  %22 = call noundef i32 @_Z11append_bitsPciihi(ptr noundef %19, i32 noundef %20, i32 noundef %21, i8 noundef zeroext -8, i32 noundef 5)
  store i32 %22, ptr %8, align 4, !tbaa !9
  store i32 %22, ptr %10, align 4, !tbaa !9
  %23 = load i32, ptr %10, align 4, !tbaa !9
  %24 = icmp slt i32 %23, 0
  br i1 %24, label %25, label %27

25:                                               ; preds = %18
  %26 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %26, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %28

27:                                               ; preds = %18
  store i32 0, ptr %11, align 4
  br label %28

28:                                               ; preds = %27, %25
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %29 = load i32, ptr %11, align 4
  switch i32 %29, label %65 [
    i32 0, label %30
    i32 1, label %63
  ]

30:                                               ; preds = %28
  br label %31

31:                                               ; preds = %30
  br label %32

32:                                               ; preds = %31
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = call noundef i32 @_Z11append_bitsPciihi(ptr noundef %33, i32 noundef %34, i32 noundef %35, i8 noundef zeroext -128, i32 noundef 2)
  store i32 %36, ptr %8, align 4, !tbaa !9
  store i32 %36, ptr %12, align 4, !tbaa !9
  %37 = load i32, ptr %12, align 4, !tbaa !9
  %38 = icmp slt i32 %37, 0
  br i1 %38, label %39, label %41

39:                                               ; preds = %32
  %40 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %40, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %42

41:                                               ; preds = %32
  store i32 0, ptr %11, align 4
  br label %42

42:                                               ; preds = %41, %39
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  %43 = load i32, ptr %11, align 4
  switch i32 %43, label %65 [
    i32 0, label %44
    i32 1, label %63
  ]

44:                                               ; preds = %42
  br label %45

45:                                               ; preds = %44
  br label %61

46:                                               ; preds = %4
  br label %47

47:                                               ; preds = %46
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = load i32, ptr %8, align 4, !tbaa !9
  %51 = call noundef i32 @_Z11append_bitsPciihi(ptr noundef %48, i32 noundef %49, i32 noundef %50, i8 noundef zeroext 0, i32 noundef 2)
  store i32 %51, ptr %8, align 4, !tbaa !9
  store i32 %51, ptr %13, align 4, !tbaa !9
  %52 = load i32, ptr %13, align 4, !tbaa !9
  %53 = icmp slt i32 %52, 0
  br i1 %53, label %54, label %56

54:                                               ; preds = %47
  %55 = load i32, ptr %13, align 4, !tbaa !9
  store i32 %55, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %57

56:                                               ; preds = %47
  store i32 0, ptr %11, align 4
  br label %57

57:                                               ; preds = %56, %54
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  %58 = load i32, ptr %11, align 4
  switch i32 %58, label %65 [
    i32 0, label %59
    i32 1, label %63
  ]

59:                                               ; preds = %57
  br label %60

60:                                               ; preds = %59
  br label %61

61:                                               ; preds = %60, %45
  %62 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %62, ptr %5, align 4
  br label %63

63:                                               ; preds = %61, %57, %42, %28
  %64 = load i32, ptr %5, align 4
  ret i32 %64

65:                                               ; preds = %57, %42, %28
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z11append_bitsPciihi(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z18append_switch_codePciih(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3) local_unnamed_addr #0 {
  %5 = icmp eq i8 %3, 4
  br i1 %5, label %6, label %11

6:                                                ; preds = %4
  %7 = tail call noundef i32 @_Z11append_bitsPciihi(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext -8, i32 noundef 5)
  %8 = icmp sgt i32 %7, -1
  br i1 %8, label %9, label %13

9:                                                ; preds = %6
  %10 = tail call noundef i32 @_Z11append_bitsPciihi(ptr noundef %0, i32 noundef %1, i32 noundef %7, i8 noundef zeroext -128, i32 noundef 2)
  br label %13

11:                                               ; preds = %4
  %12 = tail call noundef i32 @_Z11append_bitsPciihi(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext 0, i32 noundef 2)
  br label %13

13:                                               ; preds = %11, %9, %6
  %.3 = phi i32 [ %7, %6 ], [ %10, %9 ], [ %12, %11 ]
  ret i32 %.3
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass