; LLVM IR from brpapa/algorithms :: solutions/codeforces/1223-C.ll (Z3cani)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@prices = external dso_local global %"class.std::vector", align 8
@x = external dso_local global i64, align 8
@a = external dso_local global i64, align 8
@y = external dso_local global i64, align 8
@b = external dso_local global i64, align 8
@K = external dso_local global i64, align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z3cani(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #3
  store i64 0, ptr %3, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  %8 = load i64, ptr @x, align 8, !tbaa !9
  %9 = load i64, ptr @y, align 8, !tbaa !9
  %10 = icmp slt i64 %8, %9
  br i1 %10, label %11, label %12

11:                                               ; preds = %1
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) @x, ptr noundef nonnull align 8 dereferenceable(8) @y) #3
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) @a, ptr noundef nonnull align 8 dereferenceable(8) @b) #3
  br label %12

12:                                               ; preds = %11, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 1, ptr %5, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %44, %12
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = load i32, ptr %2, align 4, !tbaa !5
  %16 = icmp sle i32 %14, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %47

18:                                               ; preds = %13
  %19 = load i32, ptr %5, align 4, !tbaa !5
  %20 = sext i32 %19 to i64
  %21 = load i64, ptr @a, align 8, !tbaa !9
  %22 = srem i64 %20, %21
  %23 = icmp eq i64 %22, 0
  br i1 %23, label %24, label %43

24:                                               ; preds = %18
  %25 = load i32, ptr %5, align 4, !tbaa !5
  %26 = sext i32 %25 to i64
  %27 = load i64, ptr @b, align 8, !tbaa !9
  %28 = srem i64 %26, %27
  %29 = icmp eq i64 %28, 0
  br i1 %29, label %30, label %43

30:                                               ; preds = %24
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = add nsw i32 %31, 1
  store i32 %32, ptr %4, align 4, !tbaa !5
  %33 = sext i32 %31 to i64
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %33) #3
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = load i64, ptr @x, align 8, !tbaa !9
  %38 = load i64, ptr @y, align 8, !tbaa !9
  %39 = add nsw i64 %37, %38
  %40 = mul nsw i64 %36, %39
  %41 = load i64, ptr %3, align 8, !tbaa !9
  %42 = add nsw i64 %41, %40
  store i64 %42, ptr %3, align 8, !tbaa !9
  br label %43

43:                                               ; preds = %30, %24, %18
  br label %44

44:                                               ; preds = %43
  %45 = load i32, ptr %5, align 4, !tbaa !5
  %46 = add nsw i32 %45, 1
  store i32 %46, ptr %5, align 4, !tbaa !5
  br label %13, !llvm.loop !11

47:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 1, ptr %6, align 4, !tbaa !5
  br label %48

48:                                               ; preds = %77, %47
  %49 = load i32, ptr %6, align 4, !tbaa !5
  %50 = load i32, ptr %2, align 4, !tbaa !5
  %51 = icmp sle i32 %49, %50
  br i1 %51, label %53, label %52

52:                                               ; preds = %48
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %80

53:                                               ; preds = %48
  %54 = load i32, ptr %6, align 4, !tbaa !5
  %55 = sext i32 %54 to i64
  %56 = load i64, ptr @a, align 8, !tbaa !9
  %57 = srem i64 %55, %56
  %58 = icmp eq i64 %57, 0
  br i1 %58, label %59, label %76

59:                                               ; preds = %53
  %60 = load i32, ptr %6, align 4, !tbaa !5
  %61 = sext i32 %60 to i64
  %62 = load i64, ptr @b, align 8, !tbaa !9
  %63 = srem i64 %61, %62
  %64 = icmp ne i64 %63, 0
  br i1 %64, label %65, label %76

65:                                               ; preds = %59
  %66 = load i32, ptr %4, align 4, !tbaa !5
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %4, align 4, !tbaa !5
  %68 = sext i32 %66 to i64
  %69 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %68) #3
  %70 = load i32, ptr %69, align 4, !tbaa !5
  %71 = sext i32 %70 to i64
  %72 = load i64, ptr @x, align 8, !tbaa !9
  %73 = mul nsw i64 %71, %72
  %74 = load i64, ptr %3, align 8, !tbaa !9
  %75 = add nsw i64 %74, %73
  store i64 %75, ptr %3, align 8, !tbaa !9
  br label %76

76:                                               ; preds = %65, %59, %53
  br label %77

77:                                               ; preds = %76
  %78 = load i32, ptr %6, align 4, !tbaa !5
  %79 = add nsw i32 %78, 1
  store i32 %79, ptr %6, align 4, !tbaa !5
  br label %48, !llvm.loop !13

80:                                               ; preds = %52
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %81

81:                                               ; preds = %110, %80
  %82 = load i32, ptr %7, align 4, !tbaa !5
  %83 = load i32, ptr %2, align 4, !tbaa !5
  %84 = icmp sle i32 %82, %83
  br i1 %84, label %86, label %85

85:                                               ; preds = %81
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %113

86:                                               ; preds = %81
  %87 = load i32, ptr %7, align 4, !tbaa !5
  %88 = sext i32 %87 to i64
  %89 = load i64, ptr @a, align 8, !tbaa !9
  %90 = srem i64 %88, %89
  %91 = icmp ne i64 %90, 0
  br i1 %91, label %92, label %109

92:                                               ; preds = %86
  %93 = load i32, ptr %7, align 4, !tbaa !5
  %94 = sext i32 %93 to i64
  %95 = load i64, ptr @b, align 8, !tbaa !9
  %96 = srem i64 %94, %95
  %97 = icmp eq i64 %96, 0
  br i1 %97, label %98, label %109

98:                                               ; preds = %92
  %99 = load i32, ptr %4, align 4, !tbaa !5
  %100 = add nsw i32 %99, 1
  store i32 %100, ptr %4, align 4, !tbaa !5
  %101 = sext i32 %99 to i64
  %102 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %101) #3
  %103 = load i32, ptr %102, align 4, !tbaa !5
  %104 = sext i32 %103 to i64
  %105 = load i64, ptr @y, align 8, !tbaa !9
  %106 = mul nsw i64 %104, %105
  %107 = load i64, ptr %3, align 8, !tbaa !9
  %108 = add nsw i64 %107, %106
  store i64 %108, ptr %3, align 8, !tbaa !9
  br label %109

109:                                              ; preds = %98, %92, %86
  br label %110

110:                                              ; preds = %109
  %111 = load i32, ptr %7, align 4, !tbaa !5
  %112 = add nsw i32 %111, 1
  store i32 %112, ptr %7, align 4, !tbaa !5
  br label %81, !llvm.loop !14

113:                                              ; preds = %85
  %114 = load i64, ptr %3, align 8, !tbaa !9
  %115 = load i64, ptr @K, align 8, !tbaa !9
  %116 = icmp sge i64 %114, %115
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #3
  ret i1 %116
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@prices = external dso_local global %"class.std::vector", align 8
@x = external dso_local global i64, align 8
@a = external dso_local global i64, align 8
@y = external dso_local global i64, align 8
@b = external dso_local global i64, align 8
@K = external dso_local local_unnamed_addr global i64, align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z3cani(i32 noundef %0) local_unnamed_addr #0 {
  %2 = load i64, ptr @x, align 8, !tbaa !5
  %3 = load i64, ptr @y, align 8, !tbaa !5
  %4 = icmp slt i64 %2, %3
  br i1 %4, label %5, label %6

5:                                                ; preds = %1
  tail call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) @x, ptr noundef nonnull align 8 dereferenceable(8) @y) #2
  tail call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) @a, ptr noundef nonnull align 8 dereferenceable(8) @b) #2
  br label %6

6:                                                ; preds = %5, %1
  %.not37 = icmp slt i32 %0, 1
  br i1 %.not37, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %6
  %7 = add nuw i32 %0, 1
  %wide.trip.count = zext i32 %7 to i64
  %.pre66 = load i64, ptr @a, align 8, !tbaa !5
  br label %.lr.ph

.preheader36:                                     ; preds = %27
  br i1 %.not37, label %._crit_edge, label %.lr.ph46.preheader

.lr.ph46.preheader:                               ; preds = %.preheader36
  %8 = add nuw i32 %0, 1
  %wide.trip.count59 = zext i32 %8 to i64
  %.pre68 = load i64, ptr @a, align 8, !tbaa !5
  br label %.lr.ph46

.lr.ph:                                           ; preds = %.lr.ph.preheader, %27
  %9 = phi i64 [ %.pre66, %.lr.ph.preheader ], [ %28, %27 ]
  %indvars.iv = phi i64 [ 1, %.lr.ph.preheader ], [ %indvars.iv.next, %27 ]
  %.02439 = phi i32 [ 0, %.lr.ph.preheader ], [ %.1, %27 ]
  %.02538 = phi i64 [ 0, %.lr.ph.preheader ], [ %.126, %27 ]
  %10 = srem i64 %indvars.iv, %9
  %11 = icmp eq i64 %10, 0
  br i1 %11, label %12, label %27

12:                                               ; preds = %.lr.ph
  %13 = load i64, ptr @b, align 8, !tbaa !5
  %14 = srem i64 %indvars.iv, %13
  %15 = icmp eq i64 %14, 0
  br i1 %15, label %16, label %27

16:                                               ; preds = %12
  %17 = add nsw i32 %.02439, 1
  %18 = sext i32 %.02439 to i64
  %19 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %18) #2
  %20 = load i32, ptr %19, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = load i64, ptr @x, align 8, !tbaa !5
  %23 = load i64, ptr @y, align 8, !tbaa !5
  %24 = add nsw i64 %23, %22
  %25 = mul nsw i64 %24, %21
  %26 = add nsw i64 %25, %.02538
  %.pre = load i64, ptr @a, align 8, !tbaa !5
  br label %27

27:                                               ; preds = %.lr.ph, %12, %16
  %28 = phi i64 [ %.pre, %16 ], [ %9, %12 ], [ %9, %.lr.ph ]
  %.126 = phi i64 [ %26, %16 ], [ %.02538, %12 ], [ %.02538, %.lr.ph ]
  %.1 = phi i32 [ %17, %16 ], [ %.02439, %12 ], [ %.02439, %.lr.ph ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.preheader36, label %.lr.ph, !llvm.loop !11

.preheader:                                       ; preds = %45
  br i1 %.not37, label %._crit_edge, label %.lr.ph53.preheader

.lr.ph53.preheader:                               ; preds = %.preheader
  %29 = add nuw i32 %0, 1
  %wide.trip.count64 = zext i32 %29 to i64
  %.pre70 = load i64, ptr @a, align 8, !tbaa !5
  br label %.lr.ph53

.lr.ph46:                                         ; preds = %.lr.ph46.preheader, %45
  %30 = phi i64 [ %.pre68, %.lr.ph46.preheader ], [ %46, %45 ]
  %indvars.iv56 = phi i64 [ 1, %.lr.ph46.preheader ], [ %indvars.iv.next57, %45 ]
  %.244 = phi i32 [ %.1, %.lr.ph46.preheader ], [ %.3, %45 ]
  %.22743 = phi i64 [ %.126, %.lr.ph46.preheader ], [ %.328, %45 ]
  %31 = srem i64 %indvars.iv56, %30
  %32 = icmp eq i64 %31, 0
  br i1 %32, label %33, label %45

33:                                               ; preds = %.lr.ph46
  %34 = load i64, ptr @b, align 8, !tbaa !5
  %35 = srem i64 %indvars.iv56, %34
  %.not35 = icmp eq i64 %35, 0
  br i1 %.not35, label %45, label %36

36:                                               ; preds = %33
  %37 = add nsw i32 %.244, 1
  %38 = sext i32 %.244 to i64
  %39 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %38) #2
  %40 = load i32, ptr %39, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = load i64, ptr @x, align 8, !tbaa !5
  %43 = mul nsw i64 %42, %41
  %44 = add nsw i64 %43, %.22743
  %.pre67 = load i64, ptr @a, align 8, !tbaa !5
  br label %45

45:                                               ; preds = %.lr.ph46, %33, %36
  %46 = phi i64 [ %.pre67, %36 ], [ %30, %33 ], [ %30, %.lr.ph46 ]
  %.328 = phi i64 [ %44, %36 ], [ %.22743, %33 ], [ %.22743, %.lr.ph46 ]
  %.3 = phi i32 [ %37, %36 ], [ %.244, %33 ], [ %.244, %.lr.ph46 ]
  %indvars.iv.next57 = add nuw nsw i64 %indvars.iv56, 1
  %exitcond60.not = icmp eq i64 %indvars.iv.next57, %wide.trip.count59
  br i1 %exitcond60.not, label %.preheader, label %.lr.ph46, !llvm.loop !13

._crit_edge:                                      ; preds = %64, %6, %.preheader36, %.preheader
  %.429.lcssa = phi i64 [ %.328, %.preheader ], [ %.126, %.preheader36 ], [ 0, %6 ], [ %.530, %64 ]
  %47 = load i64, ptr @K, align 8, !tbaa !5
  %48 = icmp sge i64 %.429.lcssa, %47
  ret i1 %48

.lr.ph53:                                         ; preds = %.lr.ph53.preheader, %64
  %49 = phi i64 [ %.pre70, %.lr.ph53.preheader ], [ %65, %64 ]
  %indvars.iv61 = phi i64 [ 1, %.lr.ph53.preheader ], [ %indvars.iv.next62, %64 ]
  %.451 = phi i32 [ %.3, %.lr.ph53.preheader ], [ %.5, %64 ]
  %.42950 = phi i64 [ %.328, %.lr.ph53.preheader ], [ %.530, %64 ]
  %50 = srem i64 %indvars.iv61, %49
  %.not34 = icmp eq i64 %50, 0
  br i1 %.not34, label %64, label %51

51:                                               ; preds = %.lr.ph53
  %52 = load i64, ptr @b, align 8, !tbaa !5
  %53 = srem i64 %indvars.iv61, %52
  %54 = icmp eq i64 %53, 0
  br i1 %54, label %55, label %64

55:                                               ; preds = %51
  %56 = add nsw i32 %.451, 1
  %57 = sext i32 %.451 to i64
  %58 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @prices, i64 noundef %57) #2
  %59 = load i32, ptr %58, align 4, !tbaa !9
  %60 = sext i32 %59 to i64
  %61 = load i64, ptr @y, align 8, !tbaa !5
  %62 = mul nsw i64 %61, %60
  %63 = add nsw i64 %62, %.42950
  %.pre69 = load i64, ptr @a, align 8, !tbaa !5
  br label %64

64:                                               ; preds = %.lr.ph53, %51, %55
  %65 = phi i64 [ %.pre69, %55 ], [ %49, %51 ], [ %49, %.lr.ph53 ]
  %.530 = phi i64 [ %63, %55 ], [ %.42950, %51 ], [ %.42950, %.lr.ph53 ]
  %.5 = phi i32 [ %56, %55 ], [ %.451, %51 ], [ %.451, %.lr.ph53 ]
  %indvars.iv.next62 = add nuw nsw i64 %indvars.iv61, 1
  %exitcond65.not = icmp eq i64 %indvars.iv.next62, %wide.trip.count64
  br i1 %exitcond65.not, label %._crit_edge, label %.lr.ph53, !llvm.loop !14
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass