; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIMEx_BreakInputConfigTypeDef = type { i32, i32, i32 }
%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_ConfigBreakInput(ptr noundef %0, i32 noundef %1, ptr noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %15, i32 0, i32 0
  %17 = load i32, ptr %16, align 4, !tbaa !11
  %18 = icmp ne i32 %17, 8
  br i1 %18, label %19, label %20

19:                                               ; preds = %3
  br label %20

20:                                               ; preds = %19, %3
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %22, i32 0, i32 4
  %24 = load i32, ptr %23, align 8, !tbaa !13
  %25 = icmp eq i32 %24, 1
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 2, ptr %4, align 4
  store i32 1, ptr %14, align 4
  br label %137

27:                                               ; preds = %21
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 4
  store i32 1, ptr %29, align 8, !tbaa !13
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %33, i32 0, i32 0
  %35 = load i32, ptr %34, align 4, !tbaa !11
  switch i32 %35, label %40 [
    i32 1, label %36
    i32 2, label %37
    i32 4, label %38
    i32 8, label %39
  ]

36:                                               ; preds = %32
  store i32 1, ptr %10, align 4, !tbaa !9
  store i32 0, ptr %12, align 4, !tbaa !9
  store i32 512, ptr %11, align 4, !tbaa !9
  store i32 9, ptr %13, align 4, !tbaa !9
  br label %41

37:                                               ; preds = %32
  store i32 2, ptr %10, align 4, !tbaa !9
  store i32 1, ptr %12, align 4, !tbaa !9
  store i32 1024, ptr %11, align 4, !tbaa !9
  store i32 10, ptr %13, align 4, !tbaa !9
  br label %41

38:                                               ; preds = %32
  store i32 4, ptr %10, align 4, !tbaa !9
  store i32 2, ptr %12, align 4, !tbaa !9
  store i32 2048, ptr %11, align 4, !tbaa !9
  store i32 11, ptr %13, align 4, !tbaa !9
  br label %41

39:                                               ; preds = %32
  store i32 256, ptr %10, align 4, !tbaa !9
  store i32 8, ptr %12, align 4, !tbaa !9
  store i32 0, ptr %11, align 4, !tbaa !9
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %41

40:                                               ; preds = %32
  store i32 0, ptr %10, align 4, !tbaa !9
  store i32 0, ptr %11, align 4, !tbaa !9
  store i32 0, ptr %12, align 4, !tbaa !9
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %41

41:                                               ; preds = %40, %39, %38, %37, %36
  %42 = load i32, ptr %6, align 4, !tbaa !9
  switch i32 %42, label %129 [
    i32 1, label %43
    i32 2, label %86
  ]

43:                                               ; preds = %41
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !16
  %47 = getelementptr inbounds %struct.TIM_TypeDef, ptr %46, i32 0, i32 24
  %48 = load volatile i32, ptr %47, align 4, !tbaa !17
  store i32 %48, ptr %9, align 4, !tbaa !9
  %49 = load i32, ptr %10, align 4, !tbaa !9
  %50 = xor i32 %49, -1
  %51 = load i32, ptr %9, align 4, !tbaa !9
  %52 = and i32 %51, %50
  store i32 %52, ptr %9, align 4, !tbaa !9
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %53, i32 0, i32 1
  %55 = load i32, ptr %54, align 4, !tbaa !19
  %56 = load i32, ptr %12, align 4, !tbaa !9
  %57 = shl i32 %55, %56
  %58 = load i32, ptr %10, align 4, !tbaa !9
  %59 = and i32 %57, %58
  %60 = load i32, ptr %9, align 4, !tbaa !9
  %61 = or i32 %60, %59
  store i32 %61, ptr %9, align 4, !tbaa !9
  %62 = load ptr, ptr %7, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %62, i32 0, i32 0
  %64 = load i32, ptr %63, align 4, !tbaa !11
  %65 = icmp ne i32 %64, 8
  br i1 %65, label %66, label %80

66:                                               ; preds = %43
  %67 = load i32, ptr %11, align 4, !tbaa !9
  %68 = xor i32 %67, -1
  %69 = load i32, ptr %9, align 4, !tbaa !9
  %70 = and i32 %69, %68
  store i32 %70, ptr %9, align 4, !tbaa !9
  %71 = load ptr, ptr %7, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %71, i32 0, i32 2
  %73 = load i32, ptr %72, align 4, !tbaa !20
  %74 = load i32, ptr %13, align 4, !tbaa !9
  %75 = shl i32 %73, %74
  %76 = load i32, ptr %11, align 4, !tbaa !9
  %77 = and i32 %75, %76
  %78 = load i32, ptr %9, align 4, !tbaa !9
  %79 = or i32 %78, %77
  store i32 %79, ptr %9, align 4, !tbaa !9
  br label %80

80:                                               ; preds = %66, %43
  %81 = load i32, ptr %9, align 4, !tbaa !9
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !16
  %85 = getelementptr inbounds %struct.TIM_TypeDef, ptr %84, i32 0, i32 24
  store volatile i32 %81, ptr %85, align 4, !tbaa !17
  br label %130

86:                                               ; preds = %41
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !16
  %90 = getelementptr inbounds %struct.TIM_TypeDef, ptr %89, i32 0, i32 25
  %91 = load volatile i32, ptr %90, align 4, !tbaa !21
  store i32 %91, ptr %9, align 4, !tbaa !9
  %92 = load i32, ptr %10, align 4, !tbaa !9
  %93 = xor i32 %92, -1
  %94 = load i32, ptr %9, align 4, !tbaa !9
  %95 = and i32 %94, %93
  store i32 %95, ptr %9, align 4, !tbaa !9
  %96 = load ptr, ptr %7, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %96, i32 0, i32 1
  %98 = load i32, ptr %97, align 4, !tbaa !19
  %99 = load i32, ptr %12, align 4, !tbaa !9
  %100 = shl i32 %98, %99
  %101 = load i32, ptr %10, align 4, !tbaa !9
  %102 = and i32 %100, %101
  %103 = load i32, ptr %9, align 4, !tbaa !9
  %104 = or i32 %103, %102
  store i32 %104, ptr %9, align 4, !tbaa !9
  %105 = load ptr, ptr %7, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %105, i32 0, i32 0
  %107 = load i32, ptr %106, align 4, !tbaa !11
  %108 = icmp ne i32 %107, 8
  br i1 %108, label %109, label %123

109:                                              ; preds = %86
  %110 = load i32, ptr %11, align 4, !tbaa !9
  %111 = xor i32 %110, -1
  %112 = load i32, ptr %9, align 4, !tbaa !9
  %113 = and i32 %112, %111
  store i32 %113, ptr %9, align 4, !tbaa !9
  %114 = load ptr, ptr %7, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.TIMEx_BreakInputConfigTypeDef, ptr %114, i32 0, i32 2
  %116 = load i32, ptr %115, align 4, !tbaa !20
  %117 = load i32, ptr %13, align 4, !tbaa !9
  %118 = shl i32 %116, %117
  %119 = load i32, ptr %11, align 4, !tbaa !9
  %120 = and i32 %118, %119
  %121 = load i32, ptr %9, align 4, !tbaa !9
  %122 = or i32 %121, %120
  store i32 %122, ptr %9, align 4, !tbaa !9
  br label %123

123:                                              ; preds = %109, %86
  %124 = load i32, ptr %9, align 4, !tbaa !9
  %125 = load ptr, ptr %5, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %125, i32 0, i32 0
  %127 = load ptr, ptr %126, align 8, !tbaa !16
  %128 = getelementptr inbounds %struct.TIM_TypeDef, ptr %127, i32 0, i32 25
  store volatile i32 %124, ptr %128, align 4, !tbaa !21
  br label %130

129:                                              ; preds = %41
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %130

130:                                              ; preds = %129, %123, %80
  br label %131

131:                                              ; preds = %130
  %132 = load ptr, ptr %5, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %132, i32 0, i32 4
  store i32 0, ptr %133, align 8, !tbaa !13
  br label %134

134:                                              ; preds = %131
  br label %135

135:                                              ; preds = %134
  %136 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %136, ptr %4, align 4
  store i32 1, ptr %14, align 4
  br label %137

137:                                              ; preds = %135, %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %138 = load i32, ptr %4, align 4
  ret i32 %138
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!13 = !{!14, !10, i64 96}
!14 = !{!"", !6, i64 0, !15, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!16 = !{!14, !6, i64 0}
!17 = !{!18, !10, i64 96}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!19 = !{!12, !10, i64 4}
!20 = !{!12, !10, i64 8}
!21 = !{!18, !10, i64 100}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.HAL_TIMEx_ConfigBreakInput = private unnamed_addr constant [8 x i32] [i32 1, i32 2, i32 0, i32 4, i32 0, i32 0, i32 0, i32 256], align 4
@switch.table.HAL_TIMEx_ConfigBreakInput.1 = private unnamed_addr constant [8 x i32] [i32 512, i32 1024, i32 0, i32 2048, i32 0, i32 0, i32 0, i32 0], align 4
@switch.table.HAL_TIMEx_ConfigBreakInput.2 = private unnamed_addr constant [8 x i32] [i32 0, i32 1, i32 0, i32 2, i32 0, i32 0, i32 0, i32 8], align 4
@switch.table.HAL_TIMEx_ConfigBreakInput.3 = private unnamed_addr constant [8 x i32] [i32 9, i32 10, i32 0, i32 11, i32 0, i32 0, i32 0, i32 0], align 4

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIMEx_ConfigBreakInput(ptr nocapture noundef %0, i32 noundef %1, ptr nocapture noundef readonly %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %56, label %7

7:                                                ; preds = %3
  %8 = load i32, ptr %2, align 4, !tbaa !12
  %switch.tableidx = add i32 %8, -1
  %9 = icmp ult i32 %switch.tableidx, 8
  br i1 %9, label %switch.lookup, label %14

switch.lookup:                                    ; preds = %7
  %10 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.HAL_TIMEx_ConfigBreakInput, i64 0, i64 %10
  %switch.load = load i32, ptr %switch.gep, align 4
  %11 = zext nneg i32 %switch.tableidx to i64
  %switch.gep46 = getelementptr inbounds [8 x i32], ptr @switch.table.HAL_TIMEx_ConfigBreakInput.1, i64 0, i64 %11
  %switch.load47 = load i32, ptr %switch.gep46, align 4
  %12 = zext nneg i32 %switch.tableidx to i64
  %switch.gep48 = getelementptr inbounds [8 x i32], ptr @switch.table.HAL_TIMEx_ConfigBreakInput.2, i64 0, i64 %12
  %switch.load49 = load i32, ptr %switch.gep48, align 4
  %13 = zext nneg i32 %switch.tableidx to i64
  %switch.gep50 = getelementptr inbounds [8 x i32], ptr @switch.table.HAL_TIMEx_ConfigBreakInput.3, i64 0, i64 %13
  %switch.load51 = load i32, ptr %switch.gep50, align 4
  br label %14

14:                                               ; preds = %7, %switch.lookup
  %.041 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %7 ]
  %.040 = phi i32 [ %switch.load47, %switch.lookup ], [ 0, %7 ]
  %.039 = phi i32 [ %switch.load49, %switch.lookup ], [ 0, %7 ]
  %.0 = phi i32 [ %switch.load51, %switch.lookup ], [ 0, %7 ]
  switch i32 %1, label %55 [
    i32 1, label %15
    i32 2, label %35
  ]

15:                                               ; preds = %14
  %16 = load ptr, ptr %0, align 8, !tbaa !14
  %17 = getelementptr inbounds i8, ptr %16, i64 96
  %18 = load volatile i32, ptr %17, align 4, !tbaa !15
  %19 = xor i32 %.041, -1
  %20 = and i32 %18, %19
  %21 = getelementptr inbounds i8, ptr %2, i64 4
  %22 = load i32, ptr %21, align 4, !tbaa !17
  %23 = shl i32 %22, %.039
  %24 = and i32 %23, %.041
  %25 = or disjoint i32 %24, %20
  %.not45 = icmp eq i32 %8, 8
  br i1 %.not45, label %34, label %26

26:                                               ; preds = %15
  %27 = xor i32 %.040, -1
  %28 = and i32 %25, %27
  %29 = getelementptr inbounds i8, ptr %2, i64 8
  %30 = load i32, ptr %29, align 4, !tbaa !18
  %31 = shl i32 %30, %.0
  %32 = and i32 %31, %.040
  %33 = or disjoint i32 %32, %28
  br label %34

34:                                               ; preds = %26, %15
  %.042 = phi i32 [ %33, %26 ], [ %25, %15 ]
  store volatile i32 %.042, ptr %17, align 4, !tbaa !15
  br label %55

35:                                               ; preds = %14
  %36 = load ptr, ptr %0, align 8, !tbaa !14
  %37 = getelementptr inbounds i8, ptr %36, i64 100
  %38 = load volatile i32, ptr %37, align 4, !tbaa !19
  %39 = xor i32 %.041, -1
  %40 = and i32 %38, %39
  %41 = getelementptr inbounds i8, ptr %2, i64 4
  %42 = load i32, ptr %41, align 4, !tbaa !17
  %43 = shl i32 %42, %.039
  %44 = and i32 %43, %.041
  %45 = or disjoint i32 %44, %40
  %.not = icmp eq i32 %8, 8
  br i1 %.not, label %54, label %46

46:                                               ; preds = %35
  %47 = xor i32 %.040, -1
  %48 = and i32 %45, %47
  %49 = getelementptr inbounds i8, ptr %2, i64 8
  %50 = load i32, ptr %49, align 4, !tbaa !18
  %51 = shl i32 %50, %.0
  %52 = and i32 %51, %.040
  %53 = or disjoint i32 %52, %48
  br label %54

54:                                               ; preds = %46, %35
  %.1 = phi i32 [ %53, %46 ], [ %45, %35 ]
  store volatile i32 %.1, ptr %37, align 4, !tbaa !19
  br label %55

55:                                               ; preds = %14, %34, %54
  %.043 = phi i32 [ 0, %54 ], [ 0, %34 ], [ 1, %14 ]
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %56

56:                                               ; preds = %3, %55
  %.044 = phi i32 [ %.043, %55 ], [ 2, %3 ]
  ret i32 %.044
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 0}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !11, i64 96}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!17 = !{!13, !11, i64 4}
!18 = !{!13, !11, i64 8}
!19 = !{!16, !11, i64 100}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass