; LLVM IR from ritikbanger/Hacktoberfest2022-DSA :: 22. Segment Tree/seg.ll (Z10updateNodeRSt6vectorIxSaIxEExxxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) #2 {
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !9
  store i64 %2, ptr %9, align 8, !tbaa !9
  store i64 %3, ptr %10, align 8, !tbaa !9
  store i64 %4, ptr %11, align 8, !tbaa !9
  store i64 %5, ptr %12, align 8, !tbaa !9
  %14 = load i64, ptr %11, align 8, !tbaa !9
  %15 = load i64, ptr %8, align 8, !tbaa !9
  %16 = icmp slt i64 %14, %15
  br i1 %16, label %21, label %17

17:                                               ; preds = %6
  %18 = load i64, ptr %11, align 8, !tbaa !9
  %19 = load i64, ptr %9, align 8, !tbaa !9
  %20 = icmp sgt i64 %18, %19
  br i1 %20, label %21, label %22

21:                                               ; preds = %17, %6
  br label %69

22:                                               ; preds = %17
  %23 = load i64, ptr %8, align 8, !tbaa !9
  %24 = load i64, ptr %9, align 8, !tbaa !9
  %25 = icmp eq i64 %23, %24
  br i1 %25, label %26, label %33

26:                                               ; preds = %22
  %27 = load i64, ptr %12, align 8, !tbaa !9
  %28 = load ptr, ptr %7, align 8, !tbaa !5
  %29 = load i64, ptr %10, align 8, !tbaa !9
  %30 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %29) #3
  %31 = load i64, ptr %30, align 8, !tbaa !9
  %32 = add nsw i64 %31, %27
  store i64 %32, ptr %30, align 8, !tbaa !9
  br label %69

33:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  %34 = load i64, ptr %8, align 8, !tbaa !9
  %35 = load i64, ptr %9, align 8, !tbaa !9
  %36 = add nsw i64 %34, %35
  %37 = sdiv i64 %36, 2
  store i64 %37, ptr %13, align 8, !tbaa !9
  %38 = load ptr, ptr %7, align 8, !tbaa !5
  %39 = load i64, ptr %8, align 8, !tbaa !9
  %40 = load i64, ptr %13, align 8, !tbaa !9
  %41 = load i64, ptr %10, align 8, !tbaa !9
  %42 = mul nsw i64 2, %41
  %43 = load i64, ptr %11, align 8, !tbaa !9
  %44 = load i64, ptr %12, align 8, !tbaa !9
  call void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %39, i64 noundef %40, i64 noundef %42, i64 noundef %43, i64 noundef %44)
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = load i64, ptr %13, align 8, !tbaa !9
  %47 = add nsw i64 %46, 1
  %48 = load i64, ptr %9, align 8, !tbaa !9
  %49 = load i64, ptr %10, align 8, !tbaa !9
  %50 = mul nsw i64 2, %49
  %51 = add nsw i64 %50, 1
  %52 = load i64, ptr %11, align 8, !tbaa !9
  %53 = load i64, ptr %12, align 8, !tbaa !9
  call void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef %47, i64 noundef %48, i64 noundef %51, i64 noundef %52, i64 noundef %53)
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = load i64, ptr %10, align 8, !tbaa !9
  %56 = mul nsw i64 2, %55
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %54, i64 noundef %56) #3
  %58 = load i64, ptr %57, align 8, !tbaa !9
  %59 = load ptr, ptr %7, align 8, !tbaa !5
  %60 = load i64, ptr %10, align 8, !tbaa !9
  %61 = mul nsw i64 2, %60
  %62 = add nsw i64 %61, 1
  %63 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %59, i64 noundef %62) #3
  %64 = load i64, ptr %63, align 8, !tbaa !9
  %65 = add nsw i64 %58, %64
  %66 = load ptr, ptr %7, align 8, !tbaa !5
  %67 = load i64, ptr %10, align 8, !tbaa !9
  %68 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %66, i64 noundef %67) #3
  store i64 %65, ptr %68, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  br label %69

69:                                               ; preds = %33, %26, %21
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) local_unnamed_addr #0 {
  %7 = icmp slt i64 %4, %1
  %8 = icmp sgt i64 %4, %2
  %or.cond = or i1 %7, %8
  br i1 %or.cond, label %common.ret30, label %9

9:                                                ; preds = %6
  %10 = icmp eq i64 %1, %2
  br i1 %10, label %11, label %15

11:                                               ; preds = %9
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  %13 = load i64, ptr %12, align 8, !tbaa !5
  %14 = add nsw i64 %13, %5
  store i64 %14, ptr %12, align 8, !tbaa !5
  br label %common.ret30

common.ret30:                                     ; preds = %6, %11, %15
  ret void

15:                                               ; preds = %9
  %16 = add nsw i64 %2, %1
  %17 = sdiv i64 %16, 2
  %18 = shl nsw i64 %3, 1
  tail call void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1, i64 noundef %17, i64 noundef %18, i64 noundef %4, i64 noundef %5)
  %19 = add nsw i64 %17, 1
  %20 = or disjoint i64 %18, 1
  tail call void @_Z10updateNodeRSt6vectorIxSaIxEExxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %19, i64 noundef %2, i64 noundef %20, i64 noundef %4, i64 noundef %5)
  %21 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %18) #1
  %22 = load i64, ptr %21, align 8, !tbaa !5
  %23 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %20) #1
  %24 = load i64, ptr %23, align 8, !tbaa !5
  %25 = add nsw i64 %24, %22
  %26 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  store i64 %25, ptr %26, align 8, !tbaa !5
  br label %common.ret30
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass