; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_rcc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.RCC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_RCC_GetSysClockFreq() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca float, align 4
  %7 = alloca float, align 4
  %8 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %9 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 4), align 4, !tbaa !5
  %10 = zext i32 %9 to i64
  %11 = and i64 %10, 56
  switch i64 %11, label %164 [
    i64 0, label %12
    i64 8, label %31
    i64 16, label %32
    i64 24, label %33
  ]

12:                                               ; preds = %0
  %13 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %14 = zext i32 %13 to i64
  %15 = and i64 %14, 32
  %16 = icmp ne i64 %15, 0
  %17 = zext i1 %16 to i64
  %18 = select i1 %16, i32 1, i32 0
  %19 = icmp ne i32 %18, 0
  br i1 %19, label %20, label %29

20:                                               ; preds = %12
  %21 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %22 = zext i32 %21 to i64
  %23 = and i64 %22, 24
  %24 = trunc i64 %23 to i32
  %25 = lshr i32 %24, 3
  %26 = zext i32 %25 to i64
  %27 = lshr i64 64000000, %26
  %28 = trunc i64 %27 to i32
  store i32 %28, ptr %8, align 4, !tbaa !11
  br label %30

29:                                               ; preds = %12
  store i32 64000000, ptr %8, align 4, !tbaa !11
  br label %30

30:                                               ; preds = %29, %20
  br label %165

31:                                               ; preds = %0
  store i32 4000000, ptr %8, align 4, !tbaa !11
  br label %165

32:                                               ; preds = %0
  store i32 24000000, ptr %8, align 4, !tbaa !11
  br label %165

33:                                               ; preds = %0
  %34 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 10), align 4, !tbaa !12
  %35 = zext i32 %34 to i64
  %36 = and i64 %35, 3
  %37 = trunc i64 %36 to i32
  store i32 %37, ptr %2, align 4, !tbaa !11
  %38 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 10), align 4, !tbaa !12
  %39 = zext i32 %38 to i64
  %40 = and i64 %39, 1008
  %41 = lshr i64 %40, 4
  %42 = trunc i64 %41 to i32
  store i32 %42, ptr %3, align 4, !tbaa !11
  %43 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 11), align 4, !tbaa !13
  %44 = zext i32 %43 to i64
  %45 = and i64 %44, 1
  %46 = lshr i64 %45, 0
  %47 = trunc i64 %46 to i32
  store i32 %47, ptr %4, align 4, !tbaa !11
  %48 = load i32, ptr %4, align 4, !tbaa !11
  %49 = zext i32 %48 to i64
  %50 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 13), align 4, !tbaa !14
  %51 = zext i32 %50 to i64
  %52 = and i64 %51, 65528
  %53 = lshr i64 %52, 3
  %54 = mul i64 %49, %53
  %55 = trunc i64 %54 to i32
  %56 = uitofp i32 %55 to float
  store float %56, ptr %6, align 4, !tbaa !15
  %57 = load i32, ptr %3, align 4, !tbaa !11
  %58 = icmp ne i32 %57, 0
  br i1 %58, label %59, label %162

59:                                               ; preds = %33
  %60 = load i32, ptr %2, align 4, !tbaa !11
  switch i32 %60, label %136 [
    i32 0, label %61
    i32 1, label %108
    i32 2, label %122
  ]

61:                                               ; preds = %59
  %62 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %63 = zext i32 %62 to i64
  %64 = and i64 %63, 32
  %65 = icmp ne i64 %64, 0
  %66 = zext i1 %65 to i64
  %67 = select i1 %65, i32 1, i32 0
  %68 = icmp ne i32 %67, 0
  br i1 %68, label %69, label %93

69:                                               ; preds = %61
  %70 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %71 = zext i32 %70 to i64
  %72 = and i64 %71, 24
  %73 = trunc i64 %72 to i32
  %74 = lshr i32 %73, 3
  %75 = zext i32 %74 to i64
  %76 = lshr i64 64000000, %75
  %77 = trunc i64 %76 to i32
  store i32 %77, ptr %5, align 4, !tbaa !11
  %78 = load i32, ptr %5, align 4, !tbaa !11
  %79 = uitofp i32 %78 to float
  %80 = load i32, ptr %3, align 4, !tbaa !11
  %81 = uitofp i32 %80 to float
  %82 = fdiv float %79, %81
  %83 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %84 = zext i32 %83 to i64
  %85 = and i64 %84, 511
  %86 = trunc i64 %85 to i32
  %87 = uitofp i32 %86 to float
  %88 = load float, ptr %6, align 4, !tbaa !15
  %89 = fdiv float %88, 8.192000e+03
  %90 = fadd float %87, %89
  %91 = fadd float %90, 1.000000e+00
  %92 = fmul float %82, %91
  store float %92, ptr %7, align 4, !tbaa !15
  br label %107

93:                                               ; preds = %61
  %94 = load i32, ptr %3, align 4, !tbaa !11
  %95 = uitofp i32 %94 to float
  %96 = fdiv float 6.400000e+07, %95
  %97 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %98 = zext i32 %97 to i64
  %99 = and i64 %98, 511
  %100 = trunc i64 %99 to i32
  %101 = uitofp i32 %100 to float
  %102 = load float, ptr %6, align 4, !tbaa !15
  %103 = fdiv float %102, 8.192000e+03
  %104 = fadd float %101, %103
  %105 = fadd float %104, 1.000000e+00
  %106 = fmul float %96, %105
  store float %106, ptr %7, align 4, !tbaa !15
  br label %107

107:                                              ; preds = %93, %69
  br label %150

108:                                              ; preds = %59
  %109 = load i32, ptr %3, align 4, !tbaa !11
  %110 = uitofp i32 %109 to float
  %111 = fdiv float 4.000000e+06, %110
  %112 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %113 = zext i32 %112 to i64
  %114 = and i64 %113, 511
  %115 = trunc i64 %114 to i32
  %116 = uitofp i32 %115 to float
  %117 = load float, ptr %6, align 4, !tbaa !15
  %118 = fdiv float %117, 8.192000e+03
  %119 = fadd float %116, %118
  %120 = fadd float %119, 1.000000e+00
  %121 = fmul float %111, %120
  store float %121, ptr %7, align 4, !tbaa !15
  br label %150

122:                                              ; preds = %59
  %123 = load i32, ptr %3, align 4, !tbaa !11
  %124 = uitofp i32 %123 to float
  %125 = fdiv float 2.400000e+07, %124
  %126 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %127 = zext i32 %126 to i64
  %128 = and i64 %127, 511
  %129 = trunc i64 %128 to i32
  %130 = uitofp i32 %129 to float
  %131 = load float, ptr %6, align 4, !tbaa !15
  %132 = fdiv float %131, 8.192000e+03
  %133 = fadd float %130, %132
  %134 = fadd float %133, 1.000000e+00
  %135 = fmul float %125, %134
  store float %135, ptr %7, align 4, !tbaa !15
  br label %150

136:                                              ; preds = %59
  %137 = load i32, ptr %3, align 4, !tbaa !11
  %138 = uitofp i32 %137 to float
  %139 = fdiv float 4.000000e+06, %138
  %140 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %141 = zext i32 %140 to i64
  %142 = and i64 %141, 511
  %143 = trunc i64 %142 to i32
  %144 = uitofp i32 %143 to float
  %145 = load float, ptr %6, align 4, !tbaa !15
  %146 = fdiv float %145, 8.192000e+03
  %147 = fadd float %144, %146
  %148 = fadd float %147, 1.000000e+00
  %149 = fmul float %139, %148
  store float %149, ptr %7, align 4, !tbaa !15
  br label %150

150:                                              ; preds = %136, %122, %108, %107
  %151 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %152 = zext i32 %151 to i64
  %153 = and i64 %152, 65024
  %154 = lshr i64 %153, 9
  %155 = add i64 %154, 1
  %156 = trunc i64 %155 to i32
  store i32 %156, ptr %1, align 4, !tbaa !11
  %157 = load float, ptr %7, align 4, !tbaa !15
  %158 = load i32, ptr %1, align 4, !tbaa !11
  %159 = uitofp i32 %158 to float
  %160 = fdiv float %157, %159
  %161 = fptoui float %160 to i32
  store i32 %161, ptr %8, align 4, !tbaa !11
  br label %163

162:                                              ; preds = %33
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %163

163:                                              ; preds = %162, %150
  br label %165

164:                                              ; preds = %0
  store i32 4000000, ptr %8, align 4, !tbaa !11
  br label %165

165:                                              ; preds = %164, %163, %32, %31, %30
  %166 = load i32, ptr %8, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret i32 %166
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 16}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !7, i64 88, !7, i64 92, !7, i64 96, !7, i64 100, !7, i64 104, !7, i64 108, !7, i64 112, !7, i64 116, !7, i64 120, !7, i64 124, !7, i64 128, !7, i64 132, !7, i64 136, !7, i64 140, !7, i64 144, !7, i64 148, !7, i64 152, !7, i64 156, !7, i64 160, !7, i64 164, !7, i64 168, !8, i64 172, !7, i64 208, !7, i64 212, !7, i64 216, !7, i64 220, !7, i64 224, !7, i64 228, !7, i64 232, !7, i64 236, !7, i64 240, !7, i64 244, !7, i64 248, !7, i64 252, !7, i64 256, !7, i64 260, !7, i64 264, !7, i64 268, !7, i64 272, !7, i64 276, !7, i64 280, !7, i64 284, !8, i64 288}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !7, i64 40}
!13 = !{!6, !7, i64 44}
!14 = !{!6, !7, i64 52}
!15 = !{!16, !16, i64 0}
!16 = !{!"float", !8, i64 0}
!17 = !{!6, !7, i64 48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nounwind willreturn uwtable
define dso_local i32 @HAL_RCC_GetSysClockFreq() local_unnamed_addr #0 {
  %1 = load volatile i32, ptr inttoptr (i64 1476543504 to ptr), align 16, !tbaa !5
  %2 = lshr i32 %1, 3
  %3 = and i32 %2, 7
  switch i32 %3, label %53 [
    i32 0, label %4
    i32 3, label %13
    i32 2, label %12
  ]

4:                                                ; preds = %0
  %5 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %6 = and i32 %5, 32
  %.not19 = icmp eq i32 %6, 0
  br i1 %.not19, label %53, label %7

7:                                                ; preds = %4
  %8 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %9 = lshr i32 %8, 3
  %10 = and i32 %9, 3
  %11 = lshr exact i32 64000000, %10
  br label %53

12:                                               ; preds = %0
  br label %53

13:                                               ; preds = %0
  %14 = load volatile i32, ptr inttoptr (i64 1476543528 to ptr), align 8, !tbaa !11
  %15 = load volatile i32, ptr inttoptr (i64 1476543528 to ptr), align 8, !tbaa !11
  %16 = lshr i32 %15, 4
  %17 = and i32 %16, 63
  %18 = load volatile i32, ptr inttoptr (i64 1476543532 to ptr), align 4, !tbaa !12
  %19 = load volatile i32, ptr inttoptr (i64 1476543540 to ptr), align 4, !tbaa !13
  %20 = lshr i32 %19, 3
  %21 = and i32 %20, 8191
  %22 = trunc i32 %18 to i1
  %23 = uitofp nneg i32 %21 to float
  %24 = fmul float %23, 0x3F20000000000000
  %.not = icmp eq i32 %17, 0
  br i1 %.not, label %53, label %25

25:                                               ; preds = %13
  %26 = and i32 %14, 3
  switch i32 %26, label %default.unreachable [
    i32 0, label %27
    i32 1, label %37
    i32 2, label %36
    i32 3, label %37
  ]

27:                                               ; preds = %25
  %28 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %29 = and i32 %28, 32
  %.not18 = icmp eq i32 %29, 0
  br i1 %.not18, label %37, label %30

30:                                               ; preds = %27
  %31 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %32 = lshr i32 %31, 3
  %33 = and i32 %32, 3
  %34 = lshr exact i32 64000000, %33
  %35 = uitofp nneg i32 %34 to float
  br label %37

36:                                               ; preds = %25
  br label %37

default.unreachable:                              ; preds = %25
  unreachable

37:                                               ; preds = %25, %25, %27, %30, %36
  %.sink26 = phi float [ %35, %30 ], [ 2.400000e+07, %36 ], [ 6.400000e+07, %27 ], [ 4.000000e+06, %25 ], [ 4.000000e+06, %25 ]
  %38 = uitofp nneg i32 %17 to float
  %39 = fdiv float %.sink26, %38
  %40 = load volatile i32, ptr inttoptr (i64 1476543536 to ptr), align 16, !tbaa !14
  %41 = and i32 %40, 511
  %42 = uitofp nneg i32 %41 to float
  %43 = select i1 %22, float %24, float 0.000000e+00
  %44 = fadd float %43, %42
  %45 = fadd float %44, 1.000000e+00
  %46 = fmul float %39, %45
  %47 = load volatile i32, ptr inttoptr (i64 1476543536 to ptr), align 16, !tbaa !14
  %48 = lshr i32 %47, 9
  %49 = and i32 %48, 127
  %narrow = add nuw nsw i32 %49, 1
  %50 = uitofp nneg i32 %narrow to float
  %51 = fdiv float %46, %50
  %52 = fptoui float %51 to i32
  br label %53

53:                                               ; preds = %0, %13, %4, %37, %7, %12
  %.0 = phi i32 [ %52, %37 ], [ 24000000, %12 ], [ %11, %7 ], [ 64000000, %4 ], [ 0, %13 ], [ 4000000, %0 ]
  ret i32 %.0
}

attributes #0 = { mustprogress nofree norecurse nounwind willreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 16}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !7, i64 88, !7, i64 92, !7, i64 96, !7, i64 100, !7, i64 104, !7, i64 108, !7, i64 112, !7, i64 116, !7, i64 120, !7, i64 124, !7, i64 128, !7, i64 132, !7, i64 136, !7, i64 140, !7, i64 144, !7, i64 148, !7, i64 152, !7, i64 156, !7, i64 160, !7, i64 164, !7, i64 168, !8, i64 172, !7, i64 208, !7, i64 212, !7, i64 216, !7, i64 220, !7, i64 224, !7, i64 228, !7, i64 232, !7, i64 236, !7, i64 240, !7, i64 244, !7, i64 248, !7, i64 252, !7, i64 256, !7, i64 260, !7, i64 264, !7, i64 268, !7, i64 272, !7, i64 276, !7, i64 280, !7, i64 284, !8, i64 288}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = !{!6, !7, i64 40}
!12 = !{!6, !7, i64 44}
!13 = !{!6, !7, i64 52}
!14 = !{!6, !7, i64 48}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass