; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@SystemCoreClock = external global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Init(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store volatile i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = icmp eq ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %1
  store i32 1, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %469

14:                                               ; preds = %1
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %15, i32 0, i32 1
  %17 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %16, i32 0, i32 2
  %18 = load i32, ptr %17, align 8, !tbaa !11
  %19 = zext i32 %18 to i64
  %20 = icmp ne i64 %19, 0
  br i1 %20, label %21, label %29

21:                                               ; preds = %14
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %22, i32 0, i32 1
  %24 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %23, i32 0, i32 7
  %25 = load i32, ptr %24, align 4, !tbaa !16
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %21
  br label %28

28:                                               ; preds = %27, %21
  br label %29

29:                                               ; preds = %28, %14
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 4
  %32 = load volatile i32, ptr %31, align 4, !tbaa !17
  %33 = zext i32 %32 to i64
  %34 = icmp eq i64 %33, 0
  br i1 %34, label %35, label %41

35:                                               ; preds = %29
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  call void @HAL_ADC_MspInit(ptr noundef %36)
  %37 = load ptr, ptr %3, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %37, i32 0, i32 5
  store volatile i32 0, ptr %38, align 8, !tbaa !18
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 3
  store i32 0, ptr %40, align 8, !tbaa !19
  br label %41

41:                                               ; preds = %35, %29
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %42, i32 0, i32 0
  %44 = load ptr, ptr %43, align 8, !tbaa !20
  %45 = call i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef %44)
  %46 = zext i32 %45 to i64
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %48, label %52

48:                                               ; preds = %41
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !20
  call void @LL_ADC_DisableDeepPowerDown(ptr noundef %51)
  br label %52

52:                                               ; preds = %48, %41
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %53, i32 0, i32 0
  %55 = load ptr, ptr %54, align 8, !tbaa !20
  %56 = call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %55)
  %57 = zext i32 %56 to i64
  %58 = icmp eq i64 %57, 0
  br i1 %58, label %59, label %77

59:                                               ; preds = %52
  %60 = load ptr, ptr %3, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %60, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8, !tbaa !20
  call void @LL_ADC_EnableInternalRegulator(ptr noundef %62)
  %63 = load i32, ptr @SystemCoreClock, align 4, !tbaa !9
  %64 = zext i32 %63 to i64
  %65 = udiv i64 %64, 200000
  %66 = add i64 %65, 1
  %67 = mul i64 1, %66
  %68 = trunc i64 %67 to i32
  store volatile i32 %68, ptr %7, align 4, !tbaa !9
  br label %69

69:                                               ; preds = %73, %59
  %70 = load volatile i32, ptr %7, align 4, !tbaa !9
  %71 = zext i32 %70 to i64
  %72 = icmp ne i64 %71, 0
  br i1 %72, label %73, label %76

73:                                               ; preds = %69
  %74 = load volatile i32, ptr %7, align 4, !tbaa !9
  %75 = add i32 %74, -1
  store volatile i32 %75, ptr %7, align 4, !tbaa !9
  br label %69, !llvm.loop !21

76:                                               ; preds = %69
  br label %77

77:                                               ; preds = %76, %52
  %78 = load ptr, ptr %3, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !20
  %81 = call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %80)
  %82 = zext i32 %81 to i64
  %83 = icmp eq i64 %82, 0
  br i1 %83, label %84, label %95

84:                                               ; preds = %77
  %85 = load ptr, ptr %3, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %85, i32 0, i32 4
  %87 = load volatile i32, ptr %86, align 4, !tbaa !17
  %88 = zext i32 %87 to i64
  %89 = or i64 %88, 16
  %90 = trunc i64 %89 to i32
  store volatile i32 %90, ptr %86, align 4, !tbaa !17
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %91, i32 0, i32 5
  %93 = load volatile i32, ptr %92, align 8, !tbaa !18
  %94 = or i32 %93, 1
  store volatile i32 %94, ptr %92, align 8, !tbaa !18
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %95

95:                                               ; preds = %84, %77
  %96 = load ptr, ptr %3, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %96, i32 0, i32 0
  %98 = load ptr, ptr %97, align 8, !tbaa !20
  %99 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %98)
  store i32 %99, ptr %6, align 4, !tbaa !9
  %100 = load ptr, ptr %3, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %100, i32 0, i32 4
  %102 = load volatile i32, ptr %101, align 4, !tbaa !17
  %103 = zext i32 %102 to i64
  %104 = and i64 %103, 16
  %105 = icmp eq i64 %104, 0
  br i1 %105, label %106, label %460

106:                                              ; preds = %95
  %107 = load i32, ptr %6, align 4, !tbaa !9
  %108 = zext i32 %107 to i64
  %109 = icmp eq i64 %108, 0
  br i1 %109, label %110, label %460

110:                                              ; preds = %106
  %111 = load ptr, ptr %3, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %111, i32 0, i32 4
  %113 = load volatile i32, ptr %112, align 4, !tbaa !17
  %114 = zext i32 %113 to i64
  %115 = and i64 %114, -257
  %116 = or i64 %115, 2
  %117 = trunc i64 %116 to i32
  %118 = load ptr, ptr %3, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %118, i32 0, i32 4
  store volatile i32 %117, ptr %119, align 4, !tbaa !17
  %120 = load ptr, ptr %3, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %120, i32 0, i32 0
  %122 = load ptr, ptr %121, align 8, !tbaa !20
  %123 = call i32 @LL_ADC_IsEnabled(ptr noundef %122)
  %124 = zext i32 %123 to i64
  %125 = icmp eq i64 %124, 0
  br i1 %125, label %126, label %170

126:                                              ; preds = %110
  %127 = load ptr, ptr %3, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %127, i32 0, i32 0
  %129 = load ptr, ptr %128, align 8, !tbaa !20
  %130 = icmp eq ptr %129, inttoptr (i64 1073881088 to ptr)
  br i1 %130, label %136, label %131

131:                                              ; preds = %126
  %132 = load ptr, ptr %3, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %132, i32 0, i32 0
  %134 = load ptr, ptr %133, align 8, !tbaa !20
  %135 = icmp eq ptr %134, inttoptr (i64 1073881344 to ptr)
  br label %136

136:                                              ; preds = %131, %126
  %137 = phi i1 [ true, %126 ], [ %135, %131 ]
  %138 = zext i1 %137 to i64
  %139 = select i1 %137, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %140 = icmp eq ptr %139, inttoptr (i64 1073881856 to ptr)
  br i1 %140, label %141, label %145

141:                                              ; preds = %136
  %142 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %143 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %144 = or i32 %142, %143
  br label %147

145:                                              ; preds = %136
  %146 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %147

147:                                              ; preds = %145, %141
  %148 = phi i32 [ %144, %141 ], [ %146, %145 ]
  %149 = zext i32 %148 to i64
  %150 = icmp eq i64 %149, 0
  br i1 %150, label %151, label %169

151:                                              ; preds = %147
  %152 = load ptr, ptr %3, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !20
  %155 = icmp eq ptr %154, inttoptr (i64 1073881088 to ptr)
  br i1 %155, label %161, label %156

156:                                              ; preds = %151
  %157 = load ptr, ptr %3, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %157, i32 0, i32 0
  %159 = load ptr, ptr %158, align 8, !tbaa !20
  %160 = icmp eq ptr %159, inttoptr (i64 1073881344 to ptr)
  br label %161

161:                                              ; preds = %156, %151
  %162 = phi i1 [ true, %151 ], [ %160, %156 ]
  %163 = zext i1 %162 to i64
  %164 = select i1 %162, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %165 = load ptr, ptr %3, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %165, i32 0, i32 1
  %167 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %166, i32 0, i32 0
  %168 = load i32, ptr %167, align 8, !tbaa !23
  call void @LL_ADC_SetCommonClock(ptr noundef %164, i32 noundef %168)
  br label %169

169:                                              ; preds = %161, %147
  br label %170

170:                                              ; preds = %169, %110
  %171 = call i32 @HAL_GetREVID()
  %172 = icmp ugt i32 %171, 4099
  br i1 %172, label %173, label %206

173:                                              ; preds = %170
  %174 = load ptr, ptr %3, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %174, i32 0, i32 1
  %176 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %175, i32 0, i32 1
  %177 = load i32, ptr %176, align 4, !tbaa !24
  %178 = zext i32 %177 to i64
  %179 = icmp eq i64 16, %178
  br i1 %179, label %180, label %206

180:                                              ; preds = %173
  %181 = load ptr, ptr %3, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %181, i32 0, i32 1
  %183 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %182, i32 0, i32 5
  %184 = load i32, ptr %183, align 4, !tbaa !25
  %185 = shl i32 %184, 13
  %186 = load ptr, ptr %3, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %186, i32 0, i32 1
  %188 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %187, i32 0, i32 12
  %189 = load i32, ptr %188, align 8, !tbaa !26
  %190 = or i32 %185, %189
  %191 = load ptr, ptr %3, align 8, !tbaa !5
  %192 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %191, i32 0, i32 1
  %193 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %192, i32 0, i32 1
  %194 = load i32, ptr %193, align 4, !tbaa !24
  %195 = or i32 %190, %194
  %196 = zext i32 %195 to i64
  %197 = or i64 %196, 12
  %198 = load ptr, ptr %3, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %198, i32 0, i32 1
  %200 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %199, i32 0, i32 7
  %201 = load i32, ptr %200, align 4, !tbaa !16
  %202 = shl i32 %201, 16
  %203 = zext i32 %202 to i64
  %204 = or i64 %197, %203
  %205 = trunc i64 %204 to i32
  store i32 %205, ptr %5, align 4, !tbaa !9
  br label %228

206:                                              ; preds = %173, %170
  %207 = load ptr, ptr %3, align 8, !tbaa !5
  %208 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %207, i32 0, i32 1
  %209 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %208, i32 0, i32 5
  %210 = load i32, ptr %209, align 4, !tbaa !25
  %211 = shl i32 %210, 13
  %212 = load ptr, ptr %3, align 8, !tbaa !5
  %213 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %212, i32 0, i32 1
  %214 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %213, i32 0, i32 12
  %215 = load i32, ptr %214, align 8, !tbaa !26
  %216 = or i32 %211, %215
  %217 = load ptr, ptr %3, align 8, !tbaa !5
  %218 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %217, i32 0, i32 1
  %219 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %218, i32 0, i32 1
  %220 = load i32, ptr %219, align 4, !tbaa !24
  %221 = or i32 %216, %220
  %222 = load ptr, ptr %3, align 8, !tbaa !5
  %223 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %222, i32 0, i32 1
  %224 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %223, i32 0, i32 7
  %225 = load i32, ptr %224, align 4, !tbaa !16
  %226 = shl i32 %225, 16
  %227 = or i32 %221, %226
  store i32 %227, ptr %5, align 4, !tbaa !9
  br label %228

228:                                              ; preds = %206, %180
  %229 = load ptr, ptr %3, align 8, !tbaa !5
  %230 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %229, i32 0, i32 1
  %231 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %230, i32 0, i32 7
  %232 = load i32, ptr %231, align 4, !tbaa !16
  %233 = icmp eq i32 %232, 1
  br i1 %233, label %234, label %246

234:                                              ; preds = %228
  %235 = load ptr, ptr %3, align 8, !tbaa !5
  %236 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %235, i32 0, i32 1
  %237 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %236, i32 0, i32 8
  %238 = load i32, ptr %237, align 8, !tbaa !27
  %239 = zext i32 %238 to i64
  %240 = sub i64 %239, 1
  %241 = shl i64 %240, 17
  %242 = load i32, ptr %5, align 4, !tbaa !9
  %243 = zext i32 %242 to i64
  %244 = or i64 %243, %241
  %245 = trunc i64 %244 to i32
  store i32 %245, ptr %5, align 4, !tbaa !9
  br label %246

246:                                              ; preds = %234, %228
  %247 = load ptr, ptr %3, align 8, !tbaa !5
  %248 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %247, i32 0, i32 1
  %249 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %248, i32 0, i32 9
  %250 = load i32, ptr %249, align 4, !tbaa !28
  %251 = zext i32 %250 to i64
  %252 = icmp ne i64 %251, 0
  br i1 %252, label %253, label %270

253:                                              ; preds = %246
  %254 = load ptr, ptr %3, align 8, !tbaa !5
  %255 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %254, i32 0, i32 1
  %256 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %255, i32 0, i32 9
  %257 = load i32, ptr %256, align 4, !tbaa !28
  %258 = zext i32 %257 to i64
  %259 = and i64 %258, 992
  %260 = load ptr, ptr %3, align 8, !tbaa !5
  %261 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %260, i32 0, i32 1
  %262 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %261, i32 0, i32 10
  %263 = load i32, ptr %262, align 8, !tbaa !29
  %264 = zext i32 %263 to i64
  %265 = or i64 %259, %264
  %266 = load i32, ptr %5, align 4, !tbaa !9
  %267 = zext i32 %266 to i64
  %268 = or i64 %267, %265
  %269 = trunc i64 %268 to i32
  store i32 %269, ptr %5, align 4, !tbaa !9
  br label %270

270:                                              ; preds = %253, %246
  %271 = load ptr, ptr %3, align 8, !tbaa !5
  %272 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %271, i32 0, i32 0
  %273 = load ptr, ptr %272, align 8, !tbaa !20
  %274 = getelementptr inbounds %struct.ADC_TypeDef, ptr %273, i32 0, i32 3
  %275 = load volatile i32, ptr %274, align 4, !tbaa !30
  %276 = and i32 %275, -999421
  %277 = load i32, ptr %5, align 4, !tbaa !9
  %278 = or i32 %276, %277
  %279 = load ptr, ptr %3, align 8, !tbaa !5
  %280 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %279, i32 0, i32 0
  %281 = load ptr, ptr %280, align 8, !tbaa !20
  %282 = getelementptr inbounds %struct.ADC_TypeDef, ptr %281, i32 0, i32 3
  store volatile i32 %278, ptr %282, align 4, !tbaa !30
  %283 = load ptr, ptr %3, align 8, !tbaa !5
  %284 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %283, i32 0, i32 0
  %285 = load ptr, ptr %284, align 8, !tbaa !20
  %286 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %285)
  store i32 %286, ptr %8, align 4, !tbaa !9
  %287 = load ptr, ptr %3, align 8, !tbaa !5
  %288 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %287, i32 0, i32 0
  %289 = load ptr, ptr %288, align 8, !tbaa !20
  %290 = call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %289)
  store i32 %290, ptr %9, align 4, !tbaa !9
  %291 = load i32, ptr %8, align 4, !tbaa !9
  %292 = zext i32 %291 to i64
  %293 = icmp eq i64 %292, 0
  br i1 %293, label %294, label %414

294:                                              ; preds = %270
  %295 = load i32, ptr %9, align 4, !tbaa !9
  %296 = zext i32 %295 to i64
  %297 = icmp eq i64 %296, 0
  br i1 %297, label %298, label %414

298:                                              ; preds = %294
  %299 = load ptr, ptr %3, align 8, !tbaa !5
  %300 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %299, i32 0, i32 1
  %301 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %300, i32 0, i32 4
  %302 = load i32, ptr %301, align 8, !tbaa !32
  %303 = shl i32 %302, 14
  %304 = load ptr, ptr %3, align 8, !tbaa !5
  %305 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %304, i32 0, i32 1
  %306 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %305, i32 0, i32 11
  %307 = load i32, ptr %306, align 4, !tbaa !33
  %308 = or i32 %303, %307
  store i32 %308, ptr %5, align 4, !tbaa !9
  %309 = load ptr, ptr %3, align 8, !tbaa !5
  %310 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %309, i32 0, i32 0
  %311 = load ptr, ptr %310, align 8, !tbaa !20
  %312 = getelementptr inbounds %struct.ADC_TypeDef, ptr %311, i32 0, i32 3
  %313 = load volatile i32, ptr %312, align 4, !tbaa !30
  %314 = and i32 %313, -16388
  %315 = load i32, ptr %5, align 4, !tbaa !9
  %316 = or i32 %314, %315
  %317 = load ptr, ptr %3, align 8, !tbaa !5
  %318 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %317, i32 0, i32 0
  %319 = load ptr, ptr %318, align 8, !tbaa !20
  %320 = getelementptr inbounds %struct.ADC_TypeDef, ptr %319, i32 0, i32 3
  store volatile i32 %316, ptr %320, align 4, !tbaa !30
  %321 = load ptr, ptr %3, align 8, !tbaa !5
  %322 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %321, i32 0, i32 1
  %323 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %322, i32 0, i32 14
  %324 = load i32, ptr %323, align 8, !tbaa !34
  %325 = icmp eq i32 %324, 1
  br i1 %325, label %326, label %385

326:                                              ; preds = %298
  %327 = load ptr, ptr %3, align 8, !tbaa !5
  %328 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %327, i32 0, i32 1
  %329 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %328, i32 0, i32 9
  %330 = load i32, ptr %329, align 4, !tbaa !28
  %331 = zext i32 %330 to i64
  %332 = icmp eq i64 %331, 0
  br i1 %332, label %340, label %333

333:                                              ; preds = %326
  %334 = load ptr, ptr %3, align 8, !tbaa !5
  %335 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %334, i32 0, i32 1
  %336 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %335, i32 0, i32 10
  %337 = load i32, ptr %336, align 8, !tbaa !29
  %338 = zext i32 %337 to i64
  %339 = icmp eq i64 %338, 0
  br i1 %339, label %340, label %341

340:                                              ; preds = %333, %326
  br label %341

341:                                              ; preds = %340, %333
  %342 = load ptr, ptr %3, align 8, !tbaa !5
  %343 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %342, i32 0, i32 0
  %344 = load ptr, ptr %343, align 8, !tbaa !20
  %345 = getelementptr inbounds %struct.ADC_TypeDef, ptr %344, i32 0, i32 4
  %346 = load volatile i32, ptr %345, align 4, !tbaa !35
  %347 = and i32 %346, -67045346
  %348 = zext i32 %347 to i64
  %349 = load ptr, ptr %3, align 8, !tbaa !5
  %350 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %349, i32 0, i32 1
  %351 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %350, i32 0, i32 15
  %352 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %351, i32 0, i32 0
  %353 = load i32, ptr %352, align 4, !tbaa !36
  %354 = zext i32 %353 to i64
  %355 = sub i64 %354, 1
  %356 = shl i64 %355, 16
  %357 = or i64 1, %356
  %358 = load ptr, ptr %3, align 8, !tbaa !5
  %359 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %358, i32 0, i32 1
  %360 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %359, i32 0, i32 15
  %361 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %360, i32 0, i32 1
  %362 = load i32, ptr %361, align 4, !tbaa !37
  %363 = zext i32 %362 to i64
  %364 = or i64 %357, %363
  %365 = load ptr, ptr %3, align 8, !tbaa !5
  %366 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %365, i32 0, i32 1
  %367 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %366, i32 0, i32 15
  %368 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %367, i32 0, i32 2
  %369 = load i32, ptr %368, align 4, !tbaa !38
  %370 = zext i32 %369 to i64
  %371 = or i64 %364, %370
  %372 = load ptr, ptr %3, align 8, !tbaa !5
  %373 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %372, i32 0, i32 1
  %374 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %373, i32 0, i32 15
  %375 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %374, i32 0, i32 3
  %376 = load i32, ptr %375, align 4, !tbaa !39
  %377 = zext i32 %376 to i64
  %378 = or i64 %371, %377
  %379 = or i64 %348, %378
  %380 = trunc i64 %379 to i32
  %381 = load ptr, ptr %3, align 8, !tbaa !5
  %382 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %381, i32 0, i32 0
  %383 = load ptr, ptr %382, align 8, !tbaa !20
  %384 = getelementptr inbounds %struct.ADC_TypeDef, ptr %383, i32 0, i32 4
  store volatile i32 %380, ptr %384, align 4, !tbaa !35
  br label %394

385:                                              ; preds = %298
  %386 = load ptr, ptr %3, align 8, !tbaa !5
  %387 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %386, i32 0, i32 0
  %388 = load ptr, ptr %387, align 8, !tbaa !20
  %389 = getelementptr inbounds %struct.ADC_TypeDef, ptr %388, i32 0, i32 4
  %390 = load volatile i32, ptr %389, align 4, !tbaa !35
  %391 = zext i32 %390 to i64
  %392 = and i64 %391, -2
  %393 = trunc i64 %392 to i32
  store volatile i32 %393, ptr %389, align 4, !tbaa !35
  br label %394

394:                                              ; preds = %385, %341
  %395 = load ptr, ptr %3, align 8, !tbaa !5
  %396 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %395, i32 0, i32 0
  %397 = load ptr, ptr %396, align 8, !tbaa !20
  %398 = getelementptr inbounds %struct.ADC_TypeDef, ptr %397, i32 0, i32 4
  %399 = load volatile i32, ptr %398, align 4, !tbaa !35
  %400 = zext i32 %399 to i64
  %401 = and i64 %400, -4026531841
  %402 = load ptr, ptr %3, align 8, !tbaa !5
  %403 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %402, i32 0, i32 1
  %404 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %403, i32 0, i32 13
  %405 = load i32, ptr %404, align 4, !tbaa !40
  %406 = zext i32 %405 to i64
  %407 = or i64 %401, %406
  %408 = trunc i64 %407 to i32
  %409 = load ptr, ptr %3, align 8, !tbaa !5
  %410 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %409, i32 0, i32 0
  %411 = load ptr, ptr %410, align 8, !tbaa !20
  %412 = getelementptr inbounds %struct.ADC_TypeDef, ptr %411, i32 0, i32 4
  store volatile i32 %408, ptr %412, align 4, !tbaa !35
  %413 = load ptr, ptr %3, align 8, !tbaa !5
  call void @ADC_ConfigureBoostMode(ptr noundef %413)
  br label %414

414:                                              ; preds = %394, %294, %270
  %415 = load ptr, ptr %3, align 8, !tbaa !5
  %416 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %415, i32 0, i32 1
  %417 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %416, i32 0, i32 2
  %418 = load i32, ptr %417, align 8, !tbaa !11
  %419 = zext i32 %418 to i64
  %420 = icmp eq i64 %419, 1
  br i1 %420, label %421, label %441

421:                                              ; preds = %414
  %422 = load ptr, ptr %3, align 8, !tbaa !5
  %423 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %422, i32 0, i32 0
  %424 = load ptr, ptr %423, align 8, !tbaa !20
  %425 = getelementptr inbounds %struct.ADC_TypeDef, ptr %424, i32 0, i32 12
  %426 = load volatile i32, ptr %425, align 4, !tbaa !41
  %427 = zext i32 %426 to i64
  %428 = and i64 %427, -16
  %429 = load ptr, ptr %3, align 8, !tbaa !5
  %430 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %429, i32 0, i32 1
  %431 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %430, i32 0, i32 6
  %432 = load i32, ptr %431, align 8, !tbaa !42
  %433 = sub i32 %432, 1
  %434 = zext i32 %433 to i64
  %435 = or i64 %428, %434
  %436 = trunc i64 %435 to i32
  %437 = load ptr, ptr %3, align 8, !tbaa !5
  %438 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %437, i32 0, i32 0
  %439 = load ptr, ptr %438, align 8, !tbaa !20
  %440 = getelementptr inbounds %struct.ADC_TypeDef, ptr %439, i32 0, i32 12
  store volatile i32 %436, ptr %440, align 4, !tbaa !41
  br label %450

441:                                              ; preds = %414
  %442 = load ptr, ptr %3, align 8, !tbaa !5
  %443 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %442, i32 0, i32 0
  %444 = load ptr, ptr %443, align 8, !tbaa !20
  %445 = getelementptr inbounds %struct.ADC_TypeDef, ptr %444, i32 0, i32 12
  %446 = load volatile i32, ptr %445, align 4, !tbaa !41
  %447 = zext i32 %446 to i64
  %448 = and i64 %447, -16
  %449 = trunc i64 %448 to i32
  store volatile i32 %449, ptr %445, align 4, !tbaa !41
  br label %450

450:                                              ; preds = %441, %421
  %451 = load ptr, ptr %3, align 8, !tbaa !5
  %452 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %451, i32 0, i32 4
  %453 = load volatile i32, ptr %452, align 4, !tbaa !17
  %454 = zext i32 %453 to i64
  %455 = and i64 %454, -3
  %456 = or i64 %455, 1
  %457 = trunc i64 %456 to i32
  %458 = load ptr, ptr %3, align 8, !tbaa !5
  %459 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %458, i32 0, i32 4
  store volatile i32 %457, ptr %459, align 4, !tbaa !17
  br label %467

460:                                              ; preds = %106, %95
  %461 = load ptr, ptr %3, align 8, !tbaa !5
  %462 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %461, i32 0, i32 4
  %463 = load volatile i32, ptr %462, align 4, !tbaa !17
  %464 = zext i32 %463 to i64
  %465 = or i64 %464, 16
  %466 = trunc i64 %465 to i32
  store volatile i32 %466, ptr %462, align 4, !tbaa !17
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %467

467:                                              ; preds = %460, %450
  %468 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %468, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %469

469:                                              ; preds = %467, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %470 = load i32, ptr %2, align 4
  ret i32 %470
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_MspInit(ptr noundef) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_DisableDeepPowerDown(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_EnableInternalRegulator(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_SetCommonClock(ptr noundef, i32 noundef) #2

declare i32 @HAL_GetREVID() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_ConfigureBoostMode(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 36}
!17 = !{!12, !10, i64 100}
!18 = !{!12, !10, i64 104}
!19 = !{!12, !10, i64 96}
!20 = !{!12, !6, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!12, !10, i64 8}
!24 = !{!12, !10, i64 12}
!25 = !{!12, !10, i64 28}
!26 = !{!12, !10, i64 56}
!27 = !{!12, !10, i64 40}
!28 = !{!12, !10, i64 44}
!29 = !{!12, !10, i64 48}
!30 = !{!31, !10, i64 12}
!31 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!32 = !{!12, !10, i64 24}
!33 = !{!12, !10, i64 52}
!34 = !{!12, !10, i64 64}
!35 = !{!31, !10, i64 16}
!36 = !{!12, !10, i64 68}
!37 = !{!12, !10, i64 72}
!38 = !{!12, !10, i64 76}
!39 = !{!12, !10, i64 80}
!40 = !{!12, !10, i64 60}
!41 = !{!31, !10, i64 48}
!42 = !{!12, !10, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_ADC_Init(ptr noundef %0) local_unnamed_addr #0 {
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
  store volatile i32 0, ptr %2, align 4, !tbaa !5
  %3 = icmp eq ptr %0, null
  br i1 %3, label %171, label %4

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = getelementptr inbounds i8, ptr %0, i64 16
  %7 = getelementptr inbounds i8, ptr %0, i64 100
  %8 = load volatile i32, ptr %7, align 4, !tbaa !9
  %9 = icmp eq i32 %8, 0
  br i1 %9, label %10, label %13

10:                                               ; preds = %4
  tail call void @HAL_ADC_MspInit(ptr noundef nonnull %0)
  %11 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 0, ptr %11, align 8, !tbaa !15
  %12 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 0, ptr %12, align 8, !tbaa !16
  br label %13

13:                                               ; preds = %10, %4
  %14 = load ptr, ptr %0, align 8, !tbaa !17
  %15 = tail call i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef %14)
  %.not89 = icmp eq i32 %15, 0
  br i1 %.not89, label %18, label %16

16:                                               ; preds = %13
  %17 = load ptr, ptr %0, align 8, !tbaa !17
  tail call void @LL_ADC_DisableDeepPowerDown(ptr noundef %17)
  br label %18

18:                                               ; preds = %16, %13
  %19 = load ptr, ptr %0, align 8, !tbaa !17
  %20 = tail call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %19)
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %.loopexit

22:                                               ; preds = %18
  %23 = load ptr, ptr %0, align 8, !tbaa !17
  tail call void @LL_ADC_EnableInternalRegulator(ptr noundef %23)
  %24 = load i32, ptr @SystemCoreClock, align 4, !tbaa !5
  %25 = udiv i32 %24, 200000
  %narrow = add nuw nsw i32 %25, 1
  store volatile i32 %narrow, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.93 = load volatile i32, ptr %2, align 4, !tbaa !5
  %.not9094 = icmp eq i32 %.0..0..0..0.93, 0
  br i1 %.not9094, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %22, %.lr.ph
  %.0..0..0..0.7 = load volatile i32, ptr %2, align 4, !tbaa !5
  %26 = add i32 %.0..0..0..0.7, -1
  store volatile i32 %26, ptr %2, align 4, !tbaa !5
  %.0..0..0..0. = load volatile i32, ptr %2, align 4, !tbaa !5
  %.not90 = icmp eq i32 %.0..0..0..0., 0
  br i1 %.not90, label %.loopexit, label %.lr.ph, !llvm.loop !18

.loopexit:                                        ; preds = %.lr.ph, %22, %18
  %27 = load ptr, ptr %0, align 8, !tbaa !17
  %28 = tail call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %27)
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %36

30:                                               ; preds = %.loopexit
  %31 = load volatile i32, ptr %7, align 4, !tbaa !9
  %32 = or i32 %31, 16
  store volatile i32 %32, ptr %7, align 4, !tbaa !9
  %33 = getelementptr inbounds i8, ptr %0, i64 104
  %34 = load volatile i32, ptr %33, align 8, !tbaa !15
  %35 = or i32 %34, 1
  store volatile i32 %35, ptr %33, align 8, !tbaa !15
  br label %36

36:                                               ; preds = %30, %.loopexit
  %.082 = phi i32 [ 1, %30 ], [ 0, %.loopexit ]
  %37 = load ptr, ptr %0, align 8, !tbaa !17
  %38 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %37)
  %39 = load volatile i32, ptr %7, align 4, !tbaa !9
  %40 = and i32 %39, 16
  %41 = icmp eq i32 %40, 0
  %42 = icmp eq i32 %38, 0
  %or.cond = select i1 %41, i1 %42, i1 false
  %43 = load volatile i32, ptr %7, align 4, !tbaa !9
  br i1 %or.cond, label %44, label %169

44:                                               ; preds = %36
  %45 = and i32 %43, -259
  %46 = or disjoint i32 %45, 2
  store volatile i32 %46, ptr %7, align 4, !tbaa !9
  %47 = load ptr, ptr %0, align 8, !tbaa !17
  %48 = tail call i32 @LL_ADC_IsEnabled(ptr noundef %47)
  %49 = icmp eq i32 %48, 0
  br i1 %49, label %50, label %67

50:                                               ; preds = %44
  %51 = load ptr, ptr %0, align 8, !tbaa !17
  %magicptr = ptrtoint ptr %51 to i64
  switch i64 %magicptr, label %56 [
    i64 1073881344, label %52
    i64 1073881088, label %52
  ]

52:                                               ; preds = %50, %50
  %53 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %54 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %55 = or i32 %54, %53
  br label %58

56:                                               ; preds = %50
  %57 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %58

58:                                               ; preds = %56, %52
  %59 = phi i32 [ %55, %52 ], [ %57, %56 ]
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %67

61:                                               ; preds = %58
  %62 = load ptr, ptr %0, align 8, !tbaa !17
  %63 = icmp eq ptr %62, inttoptr (i64 1073881088 to ptr)
  %64 = icmp eq ptr %62, inttoptr (i64 1073881344 to ptr)
  %spec.select92 = or i1 %63, %64
  %65 = select i1 %spec.select92, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %66 = load i32, ptr %5, align 8, !tbaa !20
  tail call void @LL_ADC_SetCommonClock(ptr noundef nonnull %65, i32 noundef %66)
  br label %67

67:                                               ; preds = %58, %61, %44
  %68 = tail call i32 @HAL_GetREVID() #4
  %69 = icmp ugt i32 %68, 4099
  %70 = getelementptr inbounds i8, ptr %0, i64 12
  %71 = load i32, ptr %70, align 4, !tbaa !21
  %72 = icmp eq i32 %71, 16
  %or.cond95 = select i1 %69, i1 %72, i1 false
  %73 = getelementptr inbounds i8, ptr %0, i64 28
  %74 = load i32, ptr %73, align 4, !tbaa !22
  %75 = shl i32 %74, 13
  %76 = getelementptr inbounds i8, ptr %0, i64 56
  %77 = load i32, ptr %76, align 8, !tbaa !23
  %78 = getelementptr inbounds i8, ptr %0, i64 36
  %79 = load i32, ptr %78, align 4, !tbaa !24
  %80 = shl i32 %79, 16
  %. = select i1 %or.cond95, i32 %75, i32 %77
  %.103 = select i1 %or.cond95, i32 %77, i32 %75
  %.104 = select i1 %or.cond95, i32 28, i32 %71
  %81 = or i32 %., %80
  %82 = or i32 %81, %.103
  %83 = or i32 %82, %.104
  %84 = icmp eq i32 %79, 1
  br i1 %84, label %85, label %91

85:                                               ; preds = %67
  %86 = getelementptr inbounds i8, ptr %0, i64 40
  %87 = load i32, ptr %86, align 8, !tbaa !25
  %88 = shl i32 %87, 17
  %89 = add i32 %88, -131072
  %90 = or i32 %89, %83
  br label %91

91:                                               ; preds = %85, %67
  %.184 = phi i32 [ %90, %85 ], [ %83, %67 ]
  %92 = getelementptr inbounds i8, ptr %0, i64 44
  %93 = load i32, ptr %92, align 4, !tbaa !26
  %.not91 = icmp eq i32 %93, 0
  br i1 %.not91, label %100, label %94

94:                                               ; preds = %91
  %95 = and i32 %93, 992
  %96 = getelementptr inbounds i8, ptr %0, i64 48
  %97 = load i32, ptr %96, align 8, !tbaa !27
  %98 = or i32 %95, %97
  %99 = or i32 %98, %.184
  br label %100

100:                                              ; preds = %94, %91
  %.2 = phi i32 [ %99, %94 ], [ %.184, %91 ]
  %101 = load ptr, ptr %0, align 8, !tbaa !17
  %102 = getelementptr inbounds i8, ptr %101, i64 12
  %103 = load volatile i32, ptr %102, align 4, !tbaa !28
  %104 = and i32 %103, -999421
  %105 = or i32 %104, %.2
  store volatile i32 %105, ptr %102, align 4, !tbaa !28
  %106 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %101)
  %107 = load ptr, ptr %0, align 8, !tbaa !17
  %108 = tail call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %107)
  %109 = icmp eq i32 %106, 0
  %110 = icmp eq i32 %108, 0
  %or.cond5 = select i1 %109, i1 %110, i1 false
  br i1 %or.cond5, label %111, label %153

111:                                              ; preds = %100
  %112 = getelementptr inbounds i8, ptr %0, i64 24
  %113 = load i32, ptr %112, align 8, !tbaa !30
  %114 = shl i32 %113, 14
  %115 = getelementptr inbounds i8, ptr %0, i64 52
  %116 = load i32, ptr %115, align 4, !tbaa !31
  %117 = or i32 %114, %116
  %118 = load ptr, ptr %0, align 8, !tbaa !17
  %119 = getelementptr inbounds i8, ptr %118, i64 12
  %120 = load volatile i32, ptr %119, align 4, !tbaa !28
  %121 = and i32 %120, -16388
  %122 = or i32 %117, %121
  store volatile i32 %122, ptr %119, align 4, !tbaa !28
  %123 = getelementptr inbounds i8, ptr %0, i64 64
  %124 = load i32, ptr %123, align 8, !tbaa !32
  %125 = icmp eq i32 %124, 1
  %126 = getelementptr inbounds i8, ptr %118, i64 16
  %127 = load volatile i32, ptr %126, align 4, !tbaa !33
  br i1 %125, label %128, label %144

128:                                              ; preds = %111
  %129 = and i32 %127, -67045346
  %130 = getelementptr inbounds i8, ptr %0, i64 68
  %131 = load i32, ptr %130, align 4, !tbaa !34
  %132 = shl i32 %131, 16
  %133 = add i32 %132, -65535
  %134 = getelementptr inbounds i8, ptr %0, i64 72
  %135 = load i32, ptr %134, align 4, !tbaa !35
  %136 = getelementptr inbounds i8, ptr %0, i64 76
  %137 = load i32, ptr %136, align 4, !tbaa !36
  %138 = getelementptr inbounds i8, ptr %0, i64 80
  %139 = load i32, ptr %138, align 4, !tbaa !37
  %140 = or i32 %135, %129
  %141 = or i32 %140, %133
  %142 = or i32 %141, %137
  %143 = or i32 %142, %139
  br label %146

144:                                              ; preds = %111
  %145 = and i32 %127, -2
  br label %146

146:                                              ; preds = %144, %128
  %.sink = phi i32 [ %145, %144 ], [ %143, %128 ]
  store volatile i32 %.sink, ptr %126, align 4, !tbaa !33
  %147 = getelementptr inbounds i8, ptr %118, i64 16
  %148 = load volatile i32, ptr %147, align 4, !tbaa !33
  %149 = and i32 %148, 268435455
  %150 = getelementptr inbounds i8, ptr %0, i64 60
  %151 = load i32, ptr %150, align 4, !tbaa !38
  %152 = or i32 %149, %151
  store volatile i32 %152, ptr %147, align 4, !tbaa !33
  tail call void @ADC_ConfigureBoostMode(ptr noundef nonnull %0)
  br label %153

153:                                              ; preds = %146, %100
  %154 = load i32, ptr %6, align 8, !tbaa !39
  %155 = icmp eq i32 %154, 1
  %156 = load ptr, ptr %0, align 8, !tbaa !17
  %157 = getelementptr inbounds i8, ptr %156, i64 48
  %158 = load volatile i32, ptr %157, align 4, !tbaa !40
  %159 = and i32 %158, -16
  br i1 %155, label %160, label %165

160:                                              ; preds = %153
  %161 = getelementptr inbounds i8, ptr %0, i64 32
  %162 = load i32, ptr %161, align 8, !tbaa !41
  %163 = add i32 %162, -1
  %164 = or i32 %163, %159
  br label %165

165:                                              ; preds = %153, %160
  %.sink96 = phi i32 [ %164, %160 ], [ %159, %153 ]
  store volatile i32 %.sink96, ptr %157, align 4, !tbaa !40
  %166 = load volatile i32, ptr %7, align 4, !tbaa !9
  %167 = and i32 %166, -4
  %168 = or disjoint i32 %167, 1
  br label %.sink.split

169:                                              ; preds = %36
  %170 = or i32 %43, 16
  br label %.sink.split

.sink.split:                                      ; preds = %169, %165
  %.sink97 = phi i32 [ %168, %165 ], [ %170, %169 ]
  %.0.ph = phi i32 [ %.082, %165 ], [ 1, %169 ]
  store volatile i32 %.sink97, ptr %7, align 4, !tbaa !9
  br label %171

171:                                              ; preds = %.sink.split, %1
  %.0 = phi i32 [ 1, %1 ], [ %.0.ph, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
  ret i32 %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_MspInit(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_DisableDeepPowerDown(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_EnableInternalRegulator(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_SetCommonClock(ptr noundef, i32 noundef) local_unnamed_addr #2

declare i32 @HAL_GetREVID() local_unnamed_addr #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_ConfigureBoostMode(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 100}
!10 = !{!"", !11, i64 0, !12, i64 8, !11, i64 88, !6, i64 96, !6, i64 100, !6, i64 104, !14, i64 108}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !13, i64 60}
!13 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12}
!14 = !{!"", !6, i64 0, !6, i64 4}
!15 = !{!10, !6, i64 104}
!16 = !{!10, !6, i64 96}
!17 = !{!10, !11, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!10, !6, i64 8}
!21 = !{!10, !6, i64 12}
!22 = !{!10, !6, i64 28}
!23 = !{!10, !6, i64 56}
!24 = !{!10, !6, i64 36}
!25 = !{!10, !6, i64 40}
!26 = !{!10, !6, i64 44}
!27 = !{!10, !6, i64 48}
!28 = !{!29, !6, i64 12}
!29 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !7, i64 80, !6, i64 96, !6, i64 100, !6, i64 104, !6, i64 108, !7, i64 112, !6, i64 128, !6, i64 132, !6, i64 136, !6, i64 140, !7, i64 144, !6, i64 160, !6, i64 164, !6, i64 168, !6, i64 172, !6, i64 176, !6, i64 180, !6, i64 184, !6, i64 188, !6, i64 192, !6, i64 196, !6, i64 200}
!30 = !{!10, !6, i64 24}
!31 = !{!10, !6, i64 52}
!32 = !{!10, !6, i64 64}
!33 = !{!29, !6, i64 16}
!34 = !{!10, !6, i64 68}
!35 = !{!10, !6, i64 72}
!36 = !{!10, !6, i64 76}
!37 = !{!10, !6, i64 80}
!38 = !{!10, !6, i64 60}
!39 = !{!10, !6, i64 16}
!40 = !{!29, !6, i64 48}
!41 = !{!10, !6, i64 32}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass