; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_InjectedPollForConversion(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %14, i32 0, i32 0
  %16 = load ptr, ptr %15, align 8, !tbaa !11
  %17 = icmp eq ptr %16, inttoptr (i64 1073881088 to ptr)
  br i1 %17, label %23, label %18

18:                                               ; preds = %2
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %19, i32 0, i32 0
  %21 = load ptr, ptr %20, align 8, !tbaa !11
  %22 = icmp eq ptr %21, inttoptr (i64 1073881344 to ptr)
  br label %23

23:                                               ; preds = %18, %2
  %24 = phi i1 [ true, %2 ], [ %22, %18 ]
  %25 = zext i1 %24 to i64
  %26 = select i1 %24, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %27 = call i32 @LL_ADC_GetMultimode(ptr noundef %26)
  store i32 %27, ptr %12, align 4, !tbaa !9
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %28, i32 0, i32 1
  %30 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %29, i32 0, i32 3
  %31 = load i32, ptr %30, align 4, !tbaa !16
  %32 = zext i32 %31 to i64
  %33 = icmp eq i64 %32, 8
  br i1 %33, label %34, label %35

34:                                               ; preds = %23
  store i32 64, ptr %7, align 4, !tbaa !9
  br label %36

35:                                               ; preds = %23
  store i32 32, ptr %7, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %35, %34
  %37 = call i32 @HAL_GetTick()
  store i32 %37, ptr %6, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %85, %36
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 0
  %41 = load ptr, ptr %40, align 8, !tbaa !11
  %42 = getelementptr inbounds %struct.ADC_TypeDef, ptr %41, i32 0, i32 0
  %43 = load volatile i32, ptr %42, align 4, !tbaa !17
  %44 = load i32, ptr %7, align 4, !tbaa !9
  %45 = and i32 %43, %44
  %46 = zext i32 %45 to i64
  %47 = icmp eq i64 %46, 0
  br i1 %47, label %48, label %86

48:                                               ; preds = %38
  %49 = load i32, ptr %5, align 4, !tbaa !9
  %50 = icmp ne i32 %49, -1
  br i1 %50, label %51, label %85

51:                                               ; preds = %48
  %52 = call i32 @HAL_GetTick()
  %53 = load i32, ptr %6, align 4, !tbaa !9
  %54 = sub i32 %52, %53
  %55 = load i32, ptr %5, align 4, !tbaa !9
  %56 = icmp ugt i32 %54, %55
  br i1 %56, label %61, label %57

57:                                               ; preds = %51
  %58 = load i32, ptr %5, align 4, !tbaa !9
  %59 = zext i32 %58 to i64
  %60 = icmp eq i64 %59, 0
  br i1 %60, label %61, label %84

61:                                               ; preds = %57, %51
  %62 = load ptr, ptr %4, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !11
  %65 = getelementptr inbounds %struct.ADC_TypeDef, ptr %64, i32 0, i32 0
  %66 = load volatile i32, ptr %65, align 4, !tbaa !17
  %67 = load i32, ptr %7, align 4, !tbaa !9
  %68 = and i32 %66, %67
  %69 = zext i32 %68 to i64
  %70 = icmp eq i64 %69, 0
  br i1 %70, label %71, label %83

71:                                               ; preds = %61
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %72, i32 0, i32 4
  %74 = load volatile i32, ptr %73, align 4, !tbaa !19
  %75 = zext i32 %74 to i64
  %76 = or i64 %75, 4
  %77 = trunc i64 %76 to i32
  store volatile i32 %77, ptr %73, align 4, !tbaa !19
  br label %78

78:                                               ; preds = %71
  %79 = load ptr, ptr %4, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %79, i32 0, i32 3
  store i32 0, ptr %80, align 8, !tbaa !20
  br label %81

81:                                               ; preds = %78
  br label %82

82:                                               ; preds = %81
  store i32 3, ptr %3, align 4
  store i32 1, ptr %13, align 4
  br label %225

83:                                               ; preds = %61
  br label %84

84:                                               ; preds = %83, %57
  br label %85

85:                                               ; preds = %84, %48
  br label %38, !llvm.loop !21

86:                                               ; preds = %38
  %87 = load ptr, ptr %4, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !11
  %90 = call i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef %89)
  store i32 %90, ptr %8, align 4, !tbaa !9
  %91 = load ptr, ptr %4, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !11
  %94 = call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef %93)
  store i32 %94, ptr %9, align 4, !tbaa !9
  %95 = load ptr, ptr %4, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %95, i32 0, i32 0
  %97 = load ptr, ptr %96, align 8, !tbaa !11
  %98 = icmp eq ptr %97, inttoptr (i64 1073881344 to ptr)
  br i1 %98, label %99, label %100

99:                                               ; preds = %86
  br label %104

100:                                              ; preds = %86
  %101 = load ptr, ptr %4, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %101, i32 0, i32 0
  %103 = load ptr, ptr %102, align 8, !tbaa !11
  br label %104

104:                                              ; preds = %100, %99
  %105 = phi ptr [ inttoptr (i64 1073881088 to ptr), %99 ], [ %103, %100 ]
  %106 = load ptr, ptr %4, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %106, i32 0, i32 0
  %108 = load ptr, ptr %107, align 8, !tbaa !11
  %109 = icmp eq ptr %105, %108
  br i1 %109, label %122, label %110

110:                                              ; preds = %104
  %111 = load i32, ptr %12, align 4, !tbaa !9
  %112 = zext i32 %111 to i64
  %113 = icmp eq i64 %112, 0
  br i1 %113, label %122, label %114

114:                                              ; preds = %110
  %115 = load i32, ptr %12, align 4, !tbaa !9
  %116 = zext i32 %115 to i64
  %117 = icmp eq i64 %116, 6
  br i1 %117, label %122, label %118

118:                                              ; preds = %114
  %119 = load i32, ptr %12, align 4, !tbaa !9
  %120 = zext i32 %119 to i64
  %121 = icmp eq i64 %120, 7
  br i1 %121, label %122, label %128

122:                                              ; preds = %118, %114, %110, %104
  %123 = load ptr, ptr %4, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %123, i32 0, i32 0
  %125 = load ptr, ptr %124, align 8, !tbaa !11
  %126 = getelementptr inbounds %struct.ADC_TypeDef, ptr %125, i32 0, i32 3
  %127 = load volatile i32, ptr %126, align 4, !tbaa !23
  store i32 %127, ptr %10, align 4, !tbaa !9
  br label %143

128:                                              ; preds = %118
  %129 = load ptr, ptr %4, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %129, i32 0, i32 0
  %131 = load ptr, ptr %130, align 8, !tbaa !11
  %132 = icmp eq ptr %131, inttoptr (i64 1073881344 to ptr)
  br i1 %132, label %133, label %134

133:                                              ; preds = %128
  br label %138

134:                                              ; preds = %128
  %135 = load ptr, ptr %4, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %135, i32 0, i32 0
  %137 = load ptr, ptr %136, align 8, !tbaa !11
  br label %138

138:                                              ; preds = %134, %133
  %139 = phi ptr [ inttoptr (i64 1073881088 to ptr), %133 ], [ %137, %134 ]
  store ptr %139, ptr %11, align 8, !tbaa !5
  %140 = load ptr, ptr %11, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.ADC_TypeDef, ptr %140, i32 0, i32 3
  %142 = load volatile i32, ptr %141, align 4, !tbaa !23
  store i32 %142, ptr %10, align 4, !tbaa !9
  br label %143

143:                                              ; preds = %138, %122
  %144 = load ptr, ptr %4, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %144, i32 0, i32 4
  %146 = load volatile i32, ptr %145, align 4, !tbaa !19
  %147 = zext i32 %146 to i64
  %148 = or i64 %147, 8192
  %149 = trunc i64 %148 to i32
  store volatile i32 %149, ptr %145, align 4, !tbaa !19
  %150 = load i32, ptr %8, align 4, !tbaa !9
  %151 = zext i32 %150 to i64
  %152 = icmp ne i64 %151, 0
  br i1 %152, label %167, label %153

153:                                              ; preds = %143
  %154 = load i32, ptr %10, align 4, !tbaa !9
  %155 = zext i32 %154 to i64
  %156 = and i64 %155, 33554432
  %157 = icmp eq i64 %156, 0
  br i1 %157, label %158, label %204

158:                                              ; preds = %153
  %159 = load i32, ptr %9, align 4, !tbaa !9
  %160 = zext i32 %159 to i64
  %161 = icmp ne i64 %160, 0
  br i1 %161, label %162, label %204

162:                                              ; preds = %158
  %163 = load i32, ptr %10, align 4, !tbaa !9
  %164 = zext i32 %163 to i64
  %165 = and i64 %164, 8192
  %166 = icmp eq i64 %165, 0
  br i1 %166, label %167, label %204

167:                                              ; preds = %162, %143
  %168 = load ptr, ptr %4, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %168, i32 0, i32 0
  %170 = load ptr, ptr %169, align 8, !tbaa !11
  %171 = getelementptr inbounds %struct.ADC_TypeDef, ptr %170, i32 0, i32 0
  %172 = load volatile i32, ptr %171, align 4, !tbaa !17
  %173 = zext i32 %172 to i64
  %174 = and i64 %173, 64
  %175 = icmp eq i64 %174, 64
  br i1 %175, label %176, label %203

176:                                              ; preds = %167
  %177 = load i32, ptr %10, align 4, !tbaa !9
  %178 = zext i32 %177 to i64
  %179 = and i64 %178, 2097152
  %180 = icmp eq i64 %179, 0
  br i1 %180, label %181, label %202

181:                                              ; preds = %176
  %182 = load ptr, ptr %4, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %182, i32 0, i32 4
  %184 = load volatile i32, ptr %183, align 4, !tbaa !19
  %185 = zext i32 %184 to i64
  %186 = and i64 %185, -4097
  %187 = trunc i64 %186 to i32
  store volatile i32 %187, ptr %183, align 4, !tbaa !19
  %188 = load ptr, ptr %4, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %188, i32 0, i32 4
  %190 = load volatile i32, ptr %189, align 4, !tbaa !19
  %191 = zext i32 %190 to i64
  %192 = and i64 %191, 256
  %193 = icmp eq i64 %192, 0
  br i1 %193, label %194, label %201

194:                                              ; preds = %181
  %195 = load ptr, ptr %4, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %195, i32 0, i32 4
  %197 = load volatile i32, ptr %196, align 4, !tbaa !19
  %198 = zext i32 %197 to i64
  %199 = or i64 %198, 1
  %200 = trunc i64 %199 to i32
  store volatile i32 %200, ptr %196, align 4, !tbaa !19
  br label %201

201:                                              ; preds = %194, %181
  br label %202

202:                                              ; preds = %201, %176
  br label %203

203:                                              ; preds = %202, %167
  br label %204

204:                                              ; preds = %203, %162, %158, %153
  %205 = load i32, ptr %7, align 4, !tbaa !9
  %206 = zext i32 %205 to i64
  %207 = icmp eq i64 %206, 64
  br i1 %207, label %208, label %219

208:                                              ; preds = %204
  %209 = load i32, ptr %10, align 4, !tbaa !9
  %210 = zext i32 %209 to i64
  %211 = and i64 %210, 16384
  %212 = icmp eq i64 %211, 0
  br i1 %212, label %213, label %218

213:                                              ; preds = %208
  %214 = load ptr, ptr %4, align 8, !tbaa !5
  %215 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %214, i32 0, i32 0
  %216 = load ptr, ptr %215, align 8, !tbaa !11
  %217 = getelementptr inbounds %struct.ADC_TypeDef, ptr %216, i32 0, i32 0
  store volatile i32 96, ptr %217, align 4, !tbaa !17
  br label %218

218:                                              ; preds = %213, %208
  br label %224

219:                                              ; preds = %204
  %220 = load ptr, ptr %4, align 8, !tbaa !5
  %221 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %220, i32 0, i32 0
  %222 = load ptr, ptr %221, align 8, !tbaa !11
  %223 = getelementptr inbounds %struct.ADC_TypeDef, ptr %222, i32 0, i32 0
  store volatile i32 32, ptr %223, align 4, !tbaa !17
  br label %224

224:                                              ; preds = %219, %218
  store i32 0, ptr %3, align 4
  store i32 1, ptr %13, align 4
  br label %225

225:                                              ; preds = %224, %82
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %226 = load i32, ptr %3, align 4
  ret i32 %226
}

declare i32 @HAL_GetTick() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 20}
!17 = !{!18, !10, i64 0}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!19 = !{!12, !10, i64 100}
!20 = !{!12, !10, i64 96}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!18, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_ADCEx_InjectedPollForConversion(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = icmp eq ptr %3, inttoptr (i64 1073881088 to ptr)
  %5 = icmp eq ptr %3, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %4, %5
  %6 = select i1 %spec.select, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %7 = tail call i32 @LL_ADC_GetMultimode(ptr noundef nonnull %6)
  %8 = getelementptr inbounds i8, ptr %0, i64 20
  %9 = load i32, ptr %8, align 4, !tbaa !14
  %10 = icmp eq i32 %9, 8
  %.053 = select i1 %10, i32 64, i32 32
  %11 = tail call i32 @HAL_GetTick() #3
  %12 = load ptr, ptr %0, align 8, !tbaa !5
  %13 = load volatile i32, ptr %12, align 4, !tbaa !15
  %14 = and i32 %13, %.053
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %2
  switch i32 %1, label %.lr.ph.split.split [
    i32 -1, label %.lr.ph.split.us
    i32 0, label %.lr.ph.split.split.us
  ]

.lr.ph.split.us:                                  ; preds = %.lr.ph, %.lr.ph.split.us
  %16 = load volatile i32, ptr %12, align 4, !tbaa !15
  %17 = and i32 %16, %.053
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %.lr.ph.split.us, label %._crit_edge, !llvm.loop !17

.lr.ph.split.split.us:                            ; preds = %.lr.ph, %24
  %19 = tail call i32 @HAL_GetTick() #3
  %20 = load ptr, ptr %0, align 8, !tbaa !5
  %21 = load volatile i32, ptr %20, align 4, !tbaa !15
  %22 = and i32 %21, %.053
  %23 = icmp eq i32 %22, 0
  br i1 %23, label %.split.us, label %24

24:                                               ; preds = %.lr.ph.split.split.us
  %25 = load volatile i32, ptr %20, align 4, !tbaa !15
  %26 = and i32 %25, %.053
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %.lr.ph.split.split.us, label %._crit_edge, !llvm.loop !17

.lr.ph.split.split:                               ; preds = %.lr.ph, %39
  %28 = tail call i32 @HAL_GetTick() #3
  %29 = sub i32 %28, %11
  %30 = icmp ugt i32 %29, %1
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  br i1 %30, label %31, label %39

31:                                               ; preds = %.lr.ph.split.split
  %32 = load volatile i32, ptr %.pre, align 4, !tbaa !15
  %33 = and i32 %32, %.053
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %.split.us, label %39

.split.us:                                        ; preds = %.lr.ph.split.split.us, %31
  %35 = getelementptr inbounds i8, ptr %0, i64 100
  %36 = load volatile i32, ptr %35, align 4, !tbaa !19
  %37 = or i32 %36, 4
  store volatile i32 %37, ptr %35, align 4, !tbaa !19
  %38 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 0, ptr %38, align 8, !tbaa !20
  br label %80

39:                                               ; preds = %.lr.ph.split.split, %31
  %40 = load volatile i32, ptr %.pre, align 4, !tbaa !15
  %41 = and i32 %40, %.053
  %42 = icmp eq i32 %41, 0
  br i1 %42, label %.lr.ph.split.split, label %._crit_edge, !llvm.loop !17

._crit_edge:                                      ; preds = %24, %.lr.ph.split.us, %39, %2
  %.lcssa = phi ptr [ %12, %2 ], [ %.pre, %39 ], [ %12, %.lr.ph.split.us ], [ %20, %24 ]
  %43 = tail call i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef nonnull %.lcssa)
  %44 = load ptr, ptr %0, align 8, !tbaa !5
  %45 = tail call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef %44)
  %46 = load ptr, ptr %0, align 8, !tbaa !5
  %47 = icmp eq ptr %46, inttoptr (i64 1073881344 to ptr)
  %spec.select61 = select i1 %47, ptr inttoptr (i64 1073881088 to ptr), ptr %46
  %48 = icmp eq ptr %spec.select61, %46
  %49 = icmp eq i32 %7, 0
  %50 = and i32 %7, -2
  %51 = icmp eq i32 %50, 6
  %52 = or i1 %49, %51
  %or.cond11 = select i1 %48, i1 true, i1 %52
  %.pn = select i1 %or.cond11, ptr %46, ptr %spec.select61
  %.054.in = getelementptr inbounds i8, ptr %.pn, i64 12
  %.054 = load volatile i32, ptr %.054.in, align 4, !tbaa !21
  %53 = getelementptr inbounds i8, ptr %0, i64 100
  %54 = load volatile i32, ptr %53, align 4, !tbaa !19
  %55 = or i32 %54, 8192
  store volatile i32 %55, ptr %53, align 4, !tbaa !19
  %.not = icmp eq i32 %43, 0
  br i1 %.not, label %56, label %60

56:                                               ; preds = %._crit_edge
  %57 = icmp ne i32 %45, 0
  %58 = and i32 %.054, 33562624
  %59 = icmp eq i32 %58, 0
  %or.cond64 = select i1 %59, i1 %57, i1 false
  br i1 %or.cond64, label %60, label %74

60:                                               ; preds = %56, %._crit_edge
  %61 = load volatile i32, ptr %46, align 4, !tbaa !15
  %62 = and i32 %61, 64
  %.not59 = icmp ne i32 %62, 0
  %63 = and i32 %.054, 2097152
  %64 = icmp eq i32 %63, 0
  %or.cond66 = select i1 %.not59, i1 %64, i1 false
  br i1 %or.cond66, label %65, label %74

65:                                               ; preds = %60
  %66 = load volatile i32, ptr %53, align 4, !tbaa !19
  %67 = and i32 %66, -4097
  store volatile i32 %67, ptr %53, align 4, !tbaa !19
  %68 = load volatile i32, ptr %53, align 4, !tbaa !19
  %69 = and i32 %68, 256
  %70 = icmp eq i32 %69, 0
  br i1 %70, label %71, label %74

71:                                               ; preds = %65
  %72 = load volatile i32, ptr %53, align 4, !tbaa !19
  %73 = or i32 %72, 1
  store volatile i32 %73, ptr %53, align 4, !tbaa !19
  br label %74

74:                                               ; preds = %60, %65, %71, %56
  br i1 %10, label %75, label %79

75:                                               ; preds = %74
  %76 = and i32 %.054, 16384
  %77 = icmp eq i32 %76, 0
  br i1 %77, label %78, label %80

78:                                               ; preds = %75
  store volatile i32 96, ptr %46, align 4, !tbaa !15
  br label %80

79:                                               ; preds = %74
  store volatile i32 32, ptr %46, align 4, !tbaa !15
  br label %80

80:                                               ; preds = %79, %78, %75, %.split.us
  %.0 = phi i32 [ 3, %.split.us ], [ 0, %75 ], [ 0, %78 ], [ 0, %79 ]
  ret i32 %.0
}

declare i32 @HAL_GetTick() local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) local_unnamed_addr #0

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 20}
!15 = !{!16, !11, i64 0}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!6, !11, i64 100}
!20 = !{!6, !11, i64 96}
!21 = !{!16, !11, i64 12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass