; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_DMA_Abort_IT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_OC_Stop_DMA(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  %6 = load i32, ptr %4, align 4, !tbaa !9
  switch i32 %6, label %63 [
    i32 0, label %7
    i32 4, label %21
    i32 8, label %35
    i32 12, label %49
  ]

7:                                                ; preds = %2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !11
  %11 = getelementptr inbounds %struct.TIM_TypeDef, ptr %10, i32 0, i32 3
  %12 = load volatile i32, ptr %11, align 4, !tbaa !14
  %13 = zext i32 %12 to i64
  %14 = and i64 %13, -513
  %15 = trunc i64 %14 to i32
  store volatile i32 %15, ptr %11, align 4, !tbaa !14
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %16, i32 0, i32 3
  %18 = getelementptr inbounds [7 x ptr], ptr %17, i64 0, i64 1
  %19 = load ptr, ptr %18, align 8, !tbaa !5
  %20 = call i32 @HAL_DMA_Abort_IT(ptr noundef %19)
  br label %64

21:                                               ; preds = %2
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !11
  %25 = getelementptr inbounds %struct.TIM_TypeDef, ptr %24, i32 0, i32 3
  %26 = load volatile i32, ptr %25, align 4, !tbaa !14
  %27 = zext i32 %26 to i64
  %28 = and i64 %27, -1025
  %29 = trunc i64 %28 to i32
  store volatile i32 %29, ptr %25, align 4, !tbaa !14
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %30, i32 0, i32 3
  %32 = getelementptr inbounds [7 x ptr], ptr %31, i64 0, i64 2
  %33 = load ptr, ptr %32, align 8, !tbaa !5
  %34 = call i32 @HAL_DMA_Abort_IT(ptr noundef %33)
  br label %64

35:                                               ; preds = %2
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !11
  %39 = getelementptr inbounds %struct.TIM_TypeDef, ptr %38, i32 0, i32 3
  %40 = load volatile i32, ptr %39, align 4, !tbaa !14
  %41 = zext i32 %40 to i64
  %42 = and i64 %41, -2049
  %43 = trunc i64 %42 to i32
  store volatile i32 %43, ptr %39, align 4, !tbaa !14
  %44 = load ptr, ptr %3, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 3
  %46 = getelementptr inbounds [7 x ptr], ptr %45, i64 0, i64 3
  %47 = load ptr, ptr %46, align 8, !tbaa !5
  %48 = call i32 @HAL_DMA_Abort_IT(ptr noundef %47)
  br label %64

49:                                               ; preds = %2
  %50 = load ptr, ptr %3, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %50, i32 0, i32 0
  %52 = load ptr, ptr %51, align 8, !tbaa !11
  %53 = getelementptr inbounds %struct.TIM_TypeDef, ptr %52, i32 0, i32 3
  %54 = load volatile i32, ptr %53, align 4, !tbaa !14
  %55 = zext i32 %54 to i64
  %56 = and i64 %55, -4097
  %57 = trunc i64 %56 to i32
  store volatile i32 %57, ptr %53, align 4, !tbaa !14
  %58 = load ptr, ptr %3, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 3
  %60 = getelementptr inbounds [7 x ptr], ptr %59, i64 0, i64 4
  %61 = load ptr, ptr %60, align 8, !tbaa !5
  %62 = call i32 @HAL_DMA_Abort_IT(ptr noundef %61)
  br label %64

63:                                               ; preds = %2
  store i32 1, ptr %5, align 4, !tbaa !9
  br label %64

64:                                               ; preds = %63, %49, %35, %21, %7
  %65 = load i32, ptr %5, align 4, !tbaa !9
  %66 = icmp eq i32 %65, 0
  br i1 %66, label %67, label %212

67:                                               ; preds = %64
  %68 = load ptr, ptr %3, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %68, i32 0, i32 0
  %70 = load ptr, ptr %69, align 8, !tbaa !11
  %71 = load i32, ptr %4, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %70, i32 noundef %71, i32 noundef 0)
  %72 = load ptr, ptr %3, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !11
  %75 = icmp eq ptr %74, inttoptr (i64 1073807360 to ptr)
  br i1 %75, label %96, label %76

76:                                               ; preds = %67
  %77 = load ptr, ptr %3, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !11
  %80 = icmp eq ptr %79, inttoptr (i64 1073808384 to ptr)
  br i1 %80, label %96, label %81

81:                                               ; preds = %76
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !11
  %85 = icmp eq ptr %84, inttoptr (i64 1073823744 to ptr)
  br i1 %85, label %96, label %86

86:                                               ; preds = %81
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !11
  %90 = icmp eq ptr %89, inttoptr (i64 1073824768 to ptr)
  br i1 %90, label %96, label %91

91:                                               ; preds = %86
  %92 = load ptr, ptr %3, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %92, i32 0, i32 0
  %94 = load ptr, ptr %93, align 8, !tbaa !11
  %95 = icmp eq ptr %94, inttoptr (i64 1073825792 to ptr)
  br label %96

96:                                               ; preds = %91, %86, %81, %76, %67
  %97 = phi i1 [ true, %86 ], [ true, %81 ], [ true, %76 ], [ true, %67 ], [ %95, %91 ]
  %98 = zext i1 %97 to i32
  %99 = icmp ne i32 %98, 0
  br i1 %99, label %100, label %132

100:                                              ; preds = %96
  br label %101

101:                                              ; preds = %100
  %102 = load ptr, ptr %3, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !11
  %105 = getelementptr inbounds %struct.TIM_TypeDef, ptr %104, i32 0, i32 8
  %106 = load volatile i32, ptr %105, align 4, !tbaa !16
  %107 = and i32 %106, 4369
  %108 = zext i32 %107 to i64
  %109 = icmp eq i64 %108, 0
  br i1 %109, label %110, label %129

110:                                              ; preds = %101
  %111 = load ptr, ptr %3, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %111, i32 0, i32 0
  %113 = load ptr, ptr %112, align 8, !tbaa !11
  %114 = getelementptr inbounds %struct.TIM_TypeDef, ptr %113, i32 0, i32 8
  %115 = load volatile i32, ptr %114, align 4, !tbaa !16
  %116 = and i32 %115, 1092
  %117 = zext i32 %116 to i64
  %118 = icmp eq i64 %117, 0
  br i1 %118, label %119, label %128

119:                                              ; preds = %110
  %120 = load ptr, ptr %3, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %120, i32 0, i32 0
  %122 = load ptr, ptr %121, align 8, !tbaa !11
  %123 = getelementptr inbounds %struct.TIM_TypeDef, ptr %122, i32 0, i32 17
  %124 = load volatile i32, ptr %123, align 4, !tbaa !17
  %125 = zext i32 %124 to i64
  %126 = and i64 %125, -32769
  %127 = trunc i64 %126 to i32
  store volatile i32 %127, ptr %123, align 4, !tbaa !17
  br label %128

128:                                              ; preds = %119, %110
  br label %129

129:                                              ; preds = %128, %101
  br label %130

130:                                              ; preds = %129
  br label %131

131:                                              ; preds = %130
  br label %132

132:                                              ; preds = %131, %96
  br label %133

133:                                              ; preds = %132
  %134 = load ptr, ptr %3, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %134, i32 0, i32 0
  %136 = load ptr, ptr %135, align 8, !tbaa !11
  %137 = getelementptr inbounds %struct.TIM_TypeDef, ptr %136, i32 0, i32 8
  %138 = load volatile i32, ptr %137, align 4, !tbaa !16
  %139 = and i32 %138, 4369
  %140 = zext i32 %139 to i64
  %141 = icmp eq i64 %140, 0
  br i1 %141, label %142, label %161

142:                                              ; preds = %133
  %143 = load ptr, ptr %3, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %143, i32 0, i32 0
  %145 = load ptr, ptr %144, align 8, !tbaa !11
  %146 = getelementptr inbounds %struct.TIM_TypeDef, ptr %145, i32 0, i32 8
  %147 = load volatile i32, ptr %146, align 4, !tbaa !16
  %148 = and i32 %147, 1092
  %149 = zext i32 %148 to i64
  %150 = icmp eq i64 %149, 0
  br i1 %150, label %151, label %160

151:                                              ; preds = %142
  %152 = load ptr, ptr %3, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !11
  %155 = getelementptr inbounds %struct.TIM_TypeDef, ptr %154, i32 0, i32 0
  %156 = load volatile i32, ptr %155, align 4, !tbaa !18
  %157 = zext i32 %156 to i64
  %158 = and i64 %157, -2
  %159 = trunc i64 %158 to i32
  store volatile i32 %159, ptr %155, align 4, !tbaa !18
  br label %160

160:                                              ; preds = %151, %142
  br label %161

161:                                              ; preds = %160, %133
  br label %162

162:                                              ; preds = %161
  br label %163

163:                                              ; preds = %162
  %164 = load i32, ptr %4, align 4, !tbaa !9
  %165 = icmp eq i32 %164, 0
  br i1 %165, label %166, label %170

166:                                              ; preds = %163
  %167 = load ptr, ptr %3, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %167, i32 0, i32 6
  %169 = getelementptr inbounds [6 x i32], ptr %168, i64 0, i64 0
  store volatile i32 1, ptr %169, align 8, !tbaa !9
  br label %210

170:                                              ; preds = %163
  %171 = load i32, ptr %4, align 4, !tbaa !9
  %172 = icmp eq i32 %171, 4
  br i1 %172, label %173, label %177

173:                                              ; preds = %170
  %174 = load ptr, ptr %3, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %174, i32 0, i32 6
  %176 = getelementptr inbounds [6 x i32], ptr %175, i64 0, i64 1
  store volatile i32 1, ptr %176, align 4, !tbaa !9
  br label %208

177:                                              ; preds = %170
  %178 = load i32, ptr %4, align 4, !tbaa !9
  %179 = icmp eq i32 %178, 8
  br i1 %179, label %180, label %184

180:                                              ; preds = %177
  %181 = load ptr, ptr %3, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %181, i32 0, i32 6
  %183 = getelementptr inbounds [6 x i32], ptr %182, i64 0, i64 2
  store volatile i32 1, ptr %183, align 8, !tbaa !9
  br label %206

184:                                              ; preds = %177
  %185 = load i32, ptr %4, align 4, !tbaa !9
  %186 = icmp eq i32 %185, 12
  br i1 %186, label %187, label %191

187:                                              ; preds = %184
  %188 = load ptr, ptr %3, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %188, i32 0, i32 6
  %190 = getelementptr inbounds [6 x i32], ptr %189, i64 0, i64 3
  store volatile i32 1, ptr %190, align 4, !tbaa !9
  br label %204

191:                                              ; preds = %184
  %192 = load i32, ptr %4, align 4, !tbaa !9
  %193 = icmp eq i32 %192, 16
  br i1 %193, label %194, label %198

194:                                              ; preds = %191
  %195 = load ptr, ptr %3, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %195, i32 0, i32 6
  %197 = getelementptr inbounds [6 x i32], ptr %196, i64 0, i64 4
  store volatile i32 1, ptr %197, align 8, !tbaa !9
  br label %202

198:                                              ; preds = %191
  %199 = load ptr, ptr %3, align 8, !tbaa !5
  %200 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %199, i32 0, i32 6
  %201 = getelementptr inbounds [6 x i32], ptr %200, i64 0, i64 5
  store volatile i32 1, ptr %201, align 4, !tbaa !9
  br label %202

202:                                              ; preds = %198, %194
  %203 = phi i32 [ 1, %194 ], [ 1, %198 ]
  br label %204

204:                                              ; preds = %202, %187
  %205 = phi i32 [ 1, %187 ], [ %203, %202 ]
  br label %206

206:                                              ; preds = %204, %180
  %207 = phi i32 [ 1, %180 ], [ %205, %204 ]
  br label %208

208:                                              ; preds = %206, %173
  %209 = phi i32 [ 1, %173 ], [ %207, %206 ]
  br label %210

210:                                              ; preds = %208, %166
  %211 = phi i32 [ 1, %166 ], [ %209, %208 ]
  br label %212

212:                                              ; preds = %210, %64
  %213 = load i32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 %213
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 32}
!17 = !{!15, !10, i64 68}
!18 = !{!15, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.HAL_TIM_OC_Stop_DMA = private unnamed_addr constant [4 x i32] [i32 -513, i32 -1025, i32 -2049, i32 -4097], align 4

declare i32 @HAL_DMA_Abort_IT(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_TIM_OC_Stop_DMA(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  %4 = icmp ult i32 %3, 4
  br i1 %4, label %switch.lookup, label %51

switch.lookup:                                    ; preds = %2
  %5 = zext nneg i32 %3 to i64
  %switch.gep = getelementptr inbounds [4 x i32], ptr @switch.table.HAL_TIM_OC_Stop_DMA, i64 0, i64 %5
  %switch.load = load i32, ptr %switch.gep, align 4
  %6 = shl nuw nsw i32 %3, 3
  %7 = load ptr, ptr %0, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %7, i64 12
  %9 = load volatile i32, ptr %8, align 4, !tbaa !12
  %10 = and i32 %9, %switch.load
  store volatile i32 %10, ptr %8, align 4, !tbaa !12
  %11 = zext nneg i32 %6 to i64
  %12 = getelementptr inbounds i8, ptr %0, i64 %11
  %13 = getelementptr inbounds i8, ptr %12, i64 48
  %14 = load ptr, ptr %13, align 8, !tbaa !14
  %15 = tail call i32 @HAL_DMA_Abort_IT(ptr noundef %14) #3
  %16 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @TIM_CCxChannelCmd(ptr noundef %16, i32 noundef %1, i32 noundef 0)
  %17 = load ptr, ptr %0, align 8, !tbaa !5
  %magicptr37 = ptrtoint ptr %17 to i64
  switch i64 %magicptr37, label %30 [
    i64 1073807360, label %.critedge
    i64 1073808384, label %.critedge
    i64 1073823744, label %.critedge
    i64 1073824768, label %.critedge
    i64 1073825792, label %.critedge
  ]

.critedge:                                        ; preds = %switch.lookup, %switch.lookup, %switch.lookup, %switch.lookup, %switch.lookup
  %18 = getelementptr inbounds i8, ptr %17, i64 32
  %19 = load volatile i32, ptr %18, align 4, !tbaa !15
  %20 = and i32 %19, 4369
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %30

22:                                               ; preds = %.critedge
  %23 = load volatile i32, ptr %18, align 4, !tbaa !15
  %24 = and i32 %23, 1092
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %30

26:                                               ; preds = %22
  %27 = getelementptr inbounds i8, ptr %17, i64 68
  %28 = load volatile i32, ptr %27, align 4, !tbaa !16
  %29 = and i32 %28, -32769
  store volatile i32 %29, ptr %27, align 4, !tbaa !16
  br label %30

30:                                               ; preds = %switch.lookup, %22, %26, %.critedge
  %31 = getelementptr inbounds i8, ptr %17, i64 32
  %32 = load volatile i32, ptr %31, align 4, !tbaa !15
  %33 = and i32 %32, 4369
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %35, label %42

35:                                               ; preds = %30
  %36 = load volatile i32, ptr %31, align 4, !tbaa !15
  %37 = and i32 %36, 1092
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %39, label %42

39:                                               ; preds = %35
  %40 = load volatile i32, ptr %17, align 4, !tbaa !17
  %41 = and i32 %40, -2
  store volatile i32 %41, ptr %17, align 4, !tbaa !17
  br label %42

42:                                               ; preds = %35, %39, %30
  switch i32 %3, label %default.unreachable [
    i32 0, label %43
    i32 1, label %45
    i32 2, label %47
    i32 3, label %49
  ]

43:                                               ; preds = %42
  %44 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 1, ptr %44, align 8, !tbaa !18
  br label %51

45:                                               ; preds = %42
  %46 = getelementptr inbounds i8, ptr %0, i64 108
  store volatile i32 1, ptr %46, align 4, !tbaa !18
  br label %51

47:                                               ; preds = %42
  %48 = getelementptr inbounds i8, ptr %0, i64 112
  store volatile i32 1, ptr %48, align 8, !tbaa !18
  br label %51

49:                                               ; preds = %42
  %50 = getelementptr inbounds i8, ptr %0, i64 116
  store volatile i32 1, ptr %50, align 4, !tbaa !18
  br label %51

default.unreachable:                              ; preds = %42
  unreachable

51:                                               ; preds = %2, %43, %47, %49, %45
  %.039 = phi i32 [ 0, %43 ], [ 0, %47 ], [ 0, %49 ], [ 0, %45 ], [ 1, %2 ]
  ret i32 %.039
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!14 = !{!7, !7, i64 0}
!15 = !{!13, !11, i64 32}
!16 = !{!13, !11, i64 68}
!17 = !{!13, !11, i64 0}
!18 = !{!11, !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass