; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_pwr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.PWR_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SCB_Type = type { i32, i32, i32, i32, i32, i32, [12 x i8], i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, [4 x i32], [5 x i32], [1 x i32], i32, i32, i32, i32, i32, [93 x i32], i32, [15 x i32], i32, i32, i32, [1 x i32], i32, [1 x i32], i32, i32, i32, i32, i32, i32, i32, i32, [6 x i32], i32, i32, i32, i32, i32, [1 x i32], i32 }

; Function Attrs: nounwind uwtable
define dso_local void @HAL_PWR_EnterSTOPMode(i32 noundef %0, i8 noundef zeroext %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  %5 = load volatile i32, ptr inttoptr (i64 1476544512 to ptr), align 4, !tbaa !10
  %6 = zext i32 %5 to i64
  %7 = and i64 %6, -2
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = zext i32 %8 to i64
  %10 = or i64 %7, %9
  %11 = trunc i64 %10 to i32
  store volatile i32 %11, ptr inttoptr (i64 1476544512 to ptr), align 4, !tbaa !10
  %12 = load volatile i32, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 4), align 4, !tbaa !12
  %13 = zext i32 %12 to i64
  %14 = and i64 %13, -6
  %15 = trunc i64 %14 to i32
  store volatile i32 %15, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 4), align 4, !tbaa !12
  %16 = load volatile i32, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 4), align 4, !tbaa !12
  %17 = zext i32 %16 to i64
  %18 = and i64 %17, -3
  %19 = trunc i64 %18 to i32
  store volatile i32 %19, ptr getelementptr inbounds (%struct.PWR_TypeDef, ptr inttoptr (i64 1476544512 to ptr), i32 0, i32 4), align 4, !tbaa !12
  %20 = load volatile i32, ptr getelementptr inbounds (%struct.SCB_Type, ptr inttoptr (i64 3758157056 to ptr), i32 0, i32 4), align 4, !tbaa !13
  %21 = zext i32 %20 to i64
  %22 = or i64 %21, 4
  %23 = trunc i64 %22 to i32
  store volatile i32 %23, ptr getelementptr inbounds (%struct.SCB_Type, ptr inttoptr (i64 3758157056 to ptr), i32 0, i32 4), align 4, !tbaa !13
  call void @__DSB()
  call void @__ISB()
  %24 = load i8, ptr %4, align 1, !tbaa !9
  %25 = zext i8 %24 to i32
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %2
  call void asm sideeffect "wfi", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !15
  br label %29

28:                                               ; preds = %2
  call void asm sideeffect "wfe", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !16
  br label %29

29:                                               ; preds = %28, %27
  %30 = load volatile i32, ptr getelementptr inbounds (%struct.SCB_Type, ptr inttoptr (i64 3758157056 to ptr), i32 0, i32 4), align 4, !tbaa !13
  %31 = zext i32 %30 to i64
  %32 = and i64 %31, -5
  %33 = trunc i64 %32 to i32
  store volatile i32 %33, ptr getelementptr inbounds (%struct.SCB_Type, ptr inttoptr (i64 3758157056 to ptr), i32 0, i32 4), align 4, !tbaa !13
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__ISB() #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !6, i64 0}
!11 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40}
!12 = !{!11, !6, i64 16}
!13 = !{!14, !6, i64 16}
!14 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !7, i64 24, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !7, i64 64, !6, i64 72, !6, i64 76, !7, i64 80, !7, i64 96, !7, i64 116, !6, i64 120, !6, i64 124, !6, i64 128, !6, i64 132, !6, i64 136, !7, i64 140, !6, i64 512, !7, i64 516, !6, i64 576, !6, i64 580, !6, i64 584, !7, i64 588, !6, i64 592, !7, i64 596, !6, i64 600, !6, i64 604, !6, i64 608, !6, i64 612, !6, i64 616, !6, i64 620, !6, i64 624, !6, i64 628, !7, i64 632, !6, i64 656, !6, i64 660, !6, i64 664, !6, i64 668, !6, i64 672, !7, i64 676, !6, i64 680}
!15 = !{i64 2153484107}
!16 = !{i64 2153484136}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @HAL_PWR_EnterSTOPMode(i32 noundef %0, i8 noundef zeroext %1) local_unnamed_addr #0 {
  %3 = load volatile i32, ptr inttoptr (i64 1476544512 to ptr), align 2048, !tbaa !5
  %4 = and i32 %3, -2
  %5 = or i32 %4, %0
  store volatile i32 %5, ptr inttoptr (i64 1476544512 to ptr), align 2048, !tbaa !5
  %6 = load volatile i32, ptr inttoptr (i64 1476544528 to ptr), align 16, !tbaa !10
  %7 = and i32 %6, -6
  store volatile i32 %7, ptr inttoptr (i64 1476544528 to ptr), align 16, !tbaa !10
  %8 = load volatile i32, ptr inttoptr (i64 1476544528 to ptr), align 16, !tbaa !10
  %9 = and i32 %8, -3
  store volatile i32 %9, ptr inttoptr (i64 1476544528 to ptr), align 16, !tbaa !10
  %10 = load volatile i32, ptr inttoptr (i64 3758157072 to ptr), align 16, !tbaa !11
  %11 = or i32 %10, 4
  store volatile i32 %11, ptr inttoptr (i64 3758157072 to ptr), align 16, !tbaa !11
  tail call void @__DSB()
  tail call void @__ISB()
  %12 = icmp eq i8 %1, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %2
  tail call void asm sideeffect "wfi", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !13
  br label %15

14:                                               ; preds = %2
  tail call void asm sideeffect "wfe", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !14
  br label %15

15:                                               ; preds = %14, %13
  %16 = load volatile i32, ptr inttoptr (i64 3758157072 to ptr), align 16, !tbaa !11
  %17 = and i32 %16, -5
  store volatile i32 %17, ptr inttoptr (i64 3758157072 to ptr), align 16, !tbaa !11
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__ISB() local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 16}
!11 = !{!12, !7, i64 16}
!12 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !8, i64 24, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !8, i64 64, !7, i64 72, !7, i64 76, !8, i64 80, !8, i64 96, !8, i64 116, !7, i64 120, !7, i64 124, !7, i64 128, !7, i64 132, !7, i64 136, !8, i64 140, !7, i64 512, !8, i64 516, !7, i64 576, !7, i64 580, !7, i64 584, !8, i64 588, !7, i64 592, !8, i64 596, !7, i64 600, !7, i64 604, !7, i64 608, !7, i64 612, !7, i64 616, !7, i64 620, !7, i64 624, !7, i64 628, !8, i64 632, !7, i64 656, !7, i64 660, !7, i64 664, !7, i64 668, !7, i64 672, !8, i64 676, !7, i64 680}
!13 = !{i64 2153484107}
!14 = !{i64 2153484136}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,SROAPass,TailCallElimPass