; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DMA_RegisterCallback(ptr noundef %0, i32 noundef %1, ptr noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 1, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %66

13:                                               ; preds = %3
  br label %14

14:                                               ; preds = %13
  %15 = load ptr, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %15, i32 0, i32 2
  %17 = load i32, ptr %16, align 8, !tbaa !11
  %18 = icmp eq i32 %17, 1
  br i1 %18, label %19, label %20

19:                                               ; preds = %14
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %66

20:                                               ; preds = %14
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %21, i32 0, i32 2
  store i32 1, ptr %22, align 8, !tbaa !11
  br label %23

23:                                               ; preds = %20
  br label %24

24:                                               ; preds = %23
  br label %25

25:                                               ; preds = %24
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %26, i32 0, i32 3
  %28 = load volatile i32, ptr %27, align 4, !tbaa !14
  %29 = icmp eq i32 1, %28
  br i1 %29, label %30, label %58

30:                                               ; preds = %25
  %31 = load i32, ptr %6, align 4, !tbaa !9
  switch i32 %31, label %56 [
    i32 0, label %32
    i32 1, label %36
    i32 2, label %40
    i32 3, label %44
    i32 4, label %48
    i32 5, label %52
  ]

32:                                               ; preds = %30
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %34, i32 0, i32 5
  store ptr %33, ptr %35, align 8, !tbaa !15
  br label %57

36:                                               ; preds = %30
  %37 = load ptr, ptr %7, align 8, !tbaa !5
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %38, i32 0, i32 6
  store ptr %37, ptr %39, align 8, !tbaa !16
  br label %57

40:                                               ; preds = %30
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %42, i32 0, i32 7
  store ptr %41, ptr %43, align 8, !tbaa !17
  br label %57

44:                                               ; preds = %30
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = load ptr, ptr %5, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %46, i32 0, i32 8
  store ptr %45, ptr %47, align 8, !tbaa !18
  br label %57

48:                                               ; preds = %30
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %50, i32 0, i32 9
  store ptr %49, ptr %51, align 8, !tbaa !19
  br label %57

52:                                               ; preds = %30
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %54, i32 0, i32 10
  store ptr %53, ptr %55, align 8, !tbaa !20
  br label %57

56:                                               ; preds = %30
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %56, %52, %48, %44, %40, %36, %32
  br label %59

58:                                               ; preds = %25
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %58, %57
  br label %60

60:                                               ; preds = %59
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %61, i32 0, i32 2
  store i32 0, ptr %62, align 8, !tbaa !11
  br label %63

63:                                               ; preds = %60
  br label %64

64:                                               ; preds = %63
  %65 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %65, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %66

66:                                               ; preds = %64, %19, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %67 = load i32, ptr %4, align 4
  ret i32 %67
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 56}
!12 = !{!"__DMA_HandleTypeDef", !6, i64 0, !13, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!14 = !{!12, !10, i64 60}
!15 = !{!12, !6, i64 72}
!16 = !{!12, !6, i64 80}
!17 = !{!12, !6, i64 88}
!18 = !{!12, !6, i64 96}
!19 = !{!12, !6, i64 104}
!20 = !{!12, !6, i64 112}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable
define dso_local range(i32 0, 3) i32 @HAL_DMA_RegisterCallback(ptr noundef %0, i32 noundef %1, ptr noundef %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %0, null
  br i1 %4, label %19, label %5

5:                                                ; preds = %3
  %6 = getelementptr inbounds i8, ptr %0, i64 56
  %7 = load i32, ptr %6, align 8, !tbaa !5
  %8 = icmp eq i32 %7, 1
  br i1 %8, label %19, label %9

9:                                                ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 60
  %11 = load volatile i32, ptr %10, align 4, !tbaa !12
  %12 = icmp eq i32 %11, 1
  %13 = icmp ult i32 %1, 6
  %or.cond = and i1 %12, %13
  br i1 %or.cond, label %switch.lookup, label %18

switch.lookup:                                    ; preds = %9
  %14 = shl nuw nsw i32 %1, 3
  %15 = zext nneg i32 %14 to i64
  %16 = getelementptr inbounds i8, ptr %0, i64 %15
  %17 = getelementptr inbounds i8, ptr %16, i64 72
  store ptr %2, ptr %17, align 8, !tbaa !13
  br label %18

18:                                               ; preds = %switch.lookup, %9
  %.0 = phi i32 [ 1, %9 ], [ 0, %switch.lookup ]
  store i32 0, ptr %6, align 8, !tbaa !5
  br label %19

19:                                               ; preds = %5, %3, %18
  %.019 = phi i32 [ %.0, %18 ], [ 1, %3 ], [ 2, %5 ]
  ret i32 %.019
}

attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 56}
!6 = !{!"__DMA_HandleTypeDef", !7, i64 0, !10, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 60}
!13 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass