; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.ADC_Common_TypeDef = type { i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @ADC_Enable(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeStart_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) #3 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca %struct.ADC_HandleTypeDef, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 120, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %12, i32 0, i32 0
  %14 = load ptr, ptr %13, align 8, !tbaa !11
  %15 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %14)
  %16 = zext i32 %15 to i64
  %17 = icmp ne i64 %16, 0
  br i1 %17, label %18, label %19

18:                                               ; preds = %3
  store i32 2, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %144

19:                                               ; preds = %3
  br label %20

20:                                               ; preds = %19
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load i32, ptr %22, align 8, !tbaa !16
  %24 = icmp eq i32 %23, 1
  br i1 %24, label %25, label %26

25:                                               ; preds = %20
  store i32 2, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %144

26:                                               ; preds = %20
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %27, i32 0, i32 3
  store i32 1, ptr %28, align 8, !tbaa !16
  br label %29

29:                                               ; preds = %26
  br label %30

30:                                               ; preds = %29
  br label %31

31:                                               ; preds = %30
  %32 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %9, i32 0, i32 4
  store volatile i32 0, ptr %32, align 4, !tbaa !17
  %33 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %9, i32 0, i32 5
  store volatile i32 0, ptr %33, align 8, !tbaa !18
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !11
  %37 = icmp eq ptr %36, inttoptr (i64 1073881088 to ptr)
  br i1 %37, label %38, label %40

38:                                               ; preds = %31
  %39 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %9, i32 0, i32 0
  store ptr inttoptr (i64 1073881344 to ptr), ptr %39, align 8, !tbaa !11
  br label %42

40:                                               ; preds = %31
  %41 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %9, i32 0, i32 0
  store ptr null, ptr %41, align 8, !tbaa !11
  br label %42

42:                                               ; preds = %40, %38
  %43 = phi ptr [ inttoptr (i64 1073881344 to ptr), %38 ], [ null, %40 ]
  %44 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %9, i32 0, i32 0
  %45 = load ptr, ptr %44, align 8, !tbaa !11
  %46 = icmp eq ptr %45, null
  br i1 %46, label %47, label %59

47:                                               ; preds = %42
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %48, i32 0, i32 4
  %50 = load volatile i32, ptr %49, align 4, !tbaa !17
  %51 = zext i32 %50 to i64
  %52 = or i64 %51, 32
  %53 = trunc i64 %52 to i32
  store volatile i32 %53, ptr %49, align 4, !tbaa !17
  br label %54

54:                                               ; preds = %47
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %55, i32 0, i32 3
  store i32 0, ptr %56, align 8, !tbaa !16
  br label %57

57:                                               ; preds = %54
  br label %58

58:                                               ; preds = %57
  store i32 1, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %144

59:                                               ; preds = %42
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = call i32 @ADC_Enable(ptr noundef %60)
  store i32 %61, ptr %8, align 4, !tbaa !9
  %62 = load i32, ptr %8, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 0
  br i1 %63, label %64, label %66

64:                                               ; preds = %59
  %65 = call i32 @ADC_Enable(ptr noundef %9)
  store i32 %65, ptr %8, align 4, !tbaa !9
  br label %66

66:                                               ; preds = %64, %59
  %67 = load i32, ptr %8, align 4, !tbaa !9
  %68 = icmp eq i32 %67, 0
  br i1 %68, label %69, label %136

69:                                               ; preds = %66
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %70, i32 0, i32 4
  %72 = load volatile i32, ptr %71, align 4, !tbaa !17
  %73 = zext i32 %72 to i64
  %74 = and i64 %73, -3586
  %75 = or i64 %74, 256
  %76 = trunc i64 %75 to i32
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %77, i32 0, i32 4
  store volatile i32 %76, ptr %78, align 4, !tbaa !17
  %79 = load ptr, ptr %5, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %79, i32 0, i32 5
  store volatile i32 0, ptr %80, align 8, !tbaa !18
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %81, i32 0, i32 2
  %83 = load ptr, ptr %82, align 8, !tbaa !19
  %84 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %83, i32 0, i32 5
  store ptr @ADC_DMAConvCplt, ptr %84, align 8, !tbaa !20
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %85, i32 0, i32 2
  %87 = load ptr, ptr %86, align 8, !tbaa !19
  %88 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %87, i32 0, i32 6
  store ptr @ADC_DMAHalfConvCplt, ptr %88, align 8, !tbaa !23
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %89, i32 0, i32 2
  %91 = load ptr, ptr %90, align 8, !tbaa !19
  %92 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %91, i32 0, i32 9
  store ptr @ADC_DMAError, ptr %92, align 8, !tbaa !24
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %93, i32 0, i32 0
  %95 = load ptr, ptr %94, align 8, !tbaa !11
  %96 = icmp eq ptr %95, inttoptr (i64 1073881088 to ptr)
  br i1 %96, label %102, label %97

97:                                               ; preds = %69
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %98, i32 0, i32 0
  %100 = load ptr, ptr %99, align 8, !tbaa !11
  %101 = icmp eq ptr %100, inttoptr (i64 1073881344 to ptr)
  br label %102

102:                                              ; preds = %97, %69
  %103 = phi i1 [ true, %69 ], [ %101, %97 ]
  %104 = zext i1 %103 to i64
  %105 = select i1 %103, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  store ptr %105, ptr %10, align 8, !tbaa !5
  %106 = load ptr, ptr %5, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %106, i32 0, i32 0
  %108 = load ptr, ptr %107, align 8, !tbaa !11
  %109 = getelementptr inbounds %struct.ADC_TypeDef, ptr %108, i32 0, i32 0
  store volatile i32 28, ptr %109, align 4, !tbaa !25
  br label %110

110:                                              ; preds = %102
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %111, i32 0, i32 3
  store i32 0, ptr %112, align 8, !tbaa !16
  br label %113

113:                                              ; preds = %110
  br label %114

114:                                              ; preds = %113
  %115 = load ptr, ptr %5, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !11
  %118 = getelementptr inbounds %struct.ADC_TypeDef, ptr %117, i32 0, i32 1
  %119 = load volatile i32, ptr %118, align 4, !tbaa !27
  %120 = zext i32 %119 to i64
  %121 = or i64 %120, 16
  %122 = trunc i64 %121 to i32
  store volatile i32 %122, ptr %118, align 4, !tbaa !27
  %123 = load ptr, ptr %5, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %123, i32 0, i32 2
  %125 = load ptr, ptr %124, align 8, !tbaa !19
  %126 = load ptr, ptr %10, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %126, i32 0, i32 3
  %128 = ptrtoint ptr %127 to i32
  %129 = load ptr, ptr %6, align 8, !tbaa !5
  %130 = ptrtoint ptr %129 to i32
  %131 = load i32, ptr %7, align 4, !tbaa !9
  %132 = call i32 @HAL_DMA_Start_IT(ptr noundef %125, i32 noundef %128, i32 noundef %130, i32 noundef %131)
  store i32 %132, ptr %8, align 4, !tbaa !9
  %133 = load ptr, ptr %5, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %133, i32 0, i32 0
  %135 = load ptr, ptr %134, align 8, !tbaa !11
  call void @LL_ADC_REG_StartConversion(ptr noundef %135)
  br label %142

136:                                              ; preds = %66
  br label %137

137:                                              ; preds = %136
  %138 = load ptr, ptr %5, align 8, !tbaa !5
  %139 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %138, i32 0, i32 3
  store i32 0, ptr %139, align 8, !tbaa !16
  br label %140

140:                                              ; preds = %137
  br label %141

141:                                              ; preds = %140
  br label %142

142:                                              ; preds = %141, %114
  %143 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %143, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %144

144:                                              ; preds = %142, %58, %25, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 120, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %145 = load i32, ptr %4, align 4
  ret i32 %145
}

declare void @ADC_DMAConvCplt(ptr noundef) #1

declare void @ADC_DMAHalfConvCplt(ptr noundef) #1

declare void @ADC_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 96}
!17 = !{!12, !10, i64 100}
!18 = !{!12, !10, i64 104}
!19 = !{!12, !6, i64 88}
!20 = !{!21, !6, i64 72}
!21 = !{!"__DMA_HandleTypeDef", !6, i64 0, !22, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!22 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!23 = !{!21, !6, i64 80}
!24 = !{!21, !6, i64 104}
!25 = !{!26, !10, i64 0}
!26 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!27 = !{!26, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @ADC_Enable(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeStart_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #3 {
  %4 = alloca %struct.ADC_HandleTypeDef, align 8
  call void @llvm.lifetime.start.p0(i64 120, ptr nonnull %4) #4
  %5 = load ptr, ptr %0, align 8, !tbaa !5
  %6 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %5)
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %7, label %48

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 96
  %9 = load i32, ptr %8, align 8, !tbaa !14
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %48, label %11

11:                                               ; preds = %7
  store i32 1, ptr %8, align 8, !tbaa !14
  %12 = getelementptr inbounds i8, ptr %4, i64 100
  store volatile i32 0, ptr %12, align 4, !tbaa !15
  %13 = getelementptr inbounds i8, ptr %4, i64 104
  store volatile i32 0, ptr %13, align 8, !tbaa !16
  %14 = load ptr, ptr %0, align 8, !tbaa !5
  %.not30 = icmp eq ptr %14, inttoptr (i64 1073881088 to ptr)
  %. = select i1 %.not30, ptr inttoptr (i64 1073881344 to ptr), ptr null
  store ptr %., ptr %4, align 8, !tbaa !5
  br i1 %.not30, label %19, label %15

15:                                               ; preds = %11
  %16 = getelementptr inbounds i8, ptr %0, i64 100
  %17 = load volatile i32, ptr %16, align 4, !tbaa !15
  %18 = or i32 %17, 32
  store volatile i32 %18, ptr %16, align 4, !tbaa !15
  store i32 0, ptr %8, align 8, !tbaa !14
  br label %48

19:                                               ; preds = %11
  %20 = tail call i32 @ADC_Enable(ptr noundef nonnull %0) #4
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %.thread

22:                                               ; preds = %19
  %23 = call i32 @ADC_Enable(ptr noundef nonnull %4) #4
  %24 = icmp eq i32 %23, 0
  br i1 %24, label %25, label %.thread

25:                                               ; preds = %22
  %26 = getelementptr inbounds i8, ptr %0, i64 100
  %27 = load volatile i32, ptr %26, align 4, !tbaa !15
  %28 = and i32 %27, -3842
  %29 = or disjoint i32 %28, 256
  store volatile i32 %29, ptr %26, align 4, !tbaa !15
  %30 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 0, ptr %30, align 8, !tbaa !16
  %31 = getelementptr inbounds i8, ptr %0, i64 88
  %32 = load ptr, ptr %31, align 8, !tbaa !17
  %33 = getelementptr inbounds i8, ptr %32, i64 72
  store ptr @ADC_DMAConvCplt, ptr %33, align 8, !tbaa !18
  %34 = getelementptr inbounds i8, ptr %32, i64 80
  store ptr @ADC_DMAHalfConvCplt, ptr %34, align 8, !tbaa !21
  %35 = getelementptr inbounds i8, ptr %32, i64 104
  store ptr @ADC_DMAError, ptr %35, align 8, !tbaa !22
  %36 = load ptr, ptr %0, align 8, !tbaa !5
  %37 = icmp eq ptr %36, inttoptr (i64 1073881088 to ptr)
  %38 = icmp eq ptr %36, inttoptr (i64 1073881344 to ptr)
  %39 = or i1 %37, %38
  %40 = select i1 %39, i32 1073881868, i32 1476551436
  store volatile i32 28, ptr %36, align 4, !tbaa !23
  store i32 0, ptr %8, align 8, !tbaa !14
  %41 = getelementptr inbounds i8, ptr %36, i64 4
  %42 = load volatile i32, ptr %41, align 4, !tbaa !25
  %43 = or i32 %42, 16
  store volatile i32 %43, ptr %41, align 4, !tbaa !25
  %44 = ptrtoint ptr %1 to i64
  %45 = trunc i64 %44 to i32
  %46 = call i32 @HAL_DMA_Start_IT(ptr noundef %32, i32 noundef %40, i32 noundef %45, i32 noundef %2) #4
  %47 = load ptr, ptr %0, align 8, !tbaa !5
  call void @LL_ADC_REG_StartConversion(ptr noundef %47)
  br label %48

.thread:                                          ; preds = %19, %22
  %.02732 = phi i32 [ %23, %22 ], [ %20, %19 ]
  store i32 0, ptr %8, align 8, !tbaa !14
  br label %48

48:                                               ; preds = %25, %.thread, %7, %3, %15
  %.0 = phi i32 [ 1, %15 ], [ 2, %3 ], [ 2, %7 ], [ %46, %25 ], [ %.02732, %.thread ]
  call void @llvm.lifetime.end.p0(i64 120, ptr nonnull %4) #4
  ret i32 %.0
}

declare void @ADC_DMAConvCplt(ptr noundef) #1

declare void @ADC_DMAHalfConvCplt(ptr noundef) #1

declare void @ADC_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 96}
!15 = !{!6, !11, i64 100}
!16 = !{!6, !11, i64 104}
!17 = !{!6, !7, i64 88}
!18 = !{!19, !7, i64 72}
!19 = !{!"__DMA_HandleTypeDef", !7, i64 0, !20, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!21 = !{!19, !7, i64 80}
!22 = !{!19, !7, i64 104}
!23 = !{!24, !11, i64 0}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!25 = !{!24, !11, i64 4}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass