; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_MasterConfigTypeDef = type { i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  br label %9

9:                                                ; preds = %2
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %10, i32 0, i32 4
  %12 = load i32, ptr %11, align 8, !tbaa !9
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %14, label %15

14:                                               ; preds = %9
  store i32 2, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %129

15:                                               ; preds = %9
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %16, i32 0, i32 4
  store i32 1, ptr %17, align 8, !tbaa !9
  br label %18

18:                                               ; preds = %15
  br label %19

19:                                               ; preds = %18
  br label %20

20:                                               ; preds = %19
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %21, i32 0, i32 5
  store volatile i32 2, ptr %22, align 4, !tbaa !13
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %23, i32 0, i32 0
  %25 = load ptr, ptr %24, align 8, !tbaa !14
  %26 = getelementptr inbounds %struct.TIM_TypeDef, ptr %25, i32 0, i32 1
  %27 = load volatile i32, ptr %26, align 4, !tbaa !15
  store i32 %27, ptr %6, align 4, !tbaa !17
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 0
  %30 = load ptr, ptr %29, align 8, !tbaa !14
  %31 = getelementptr inbounds %struct.TIM_TypeDef, ptr %30, i32 0, i32 2
  %32 = load volatile i32, ptr %31, align 4, !tbaa !18
  store i32 %32, ptr %7, align 4, !tbaa !17
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !14
  %36 = icmp eq ptr %35, inttoptr (i64 1073807360 to ptr)
  br i1 %36, label %42, label %37

37:                                               ; preds = %20
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %38, i32 0, i32 0
  %40 = load ptr, ptr %39, align 8, !tbaa !14
  %41 = icmp eq ptr %40, inttoptr (i64 1073808384 to ptr)
  br i1 %41, label %42, label %52

42:                                               ; preds = %37, %20
  %43 = load i32, ptr %6, align 4, !tbaa !17
  %44 = zext i32 %43 to i64
  %45 = and i64 %44, -15728641
  %46 = trunc i64 %45 to i32
  store i32 %46, ptr %6, align 4, !tbaa !17
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %47, i32 0, i32 1
  %49 = load i32, ptr %48, align 4, !tbaa !19
  %50 = load i32, ptr %6, align 4, !tbaa !17
  %51 = or i32 %50, %49
  store i32 %51, ptr %6, align 4, !tbaa !17
  br label %52

52:                                               ; preds = %42, %37
  %53 = load i32, ptr %6, align 4, !tbaa !17
  %54 = zext i32 %53 to i64
  %55 = and i64 %54, -113
  %56 = trunc i64 %55 to i32
  store i32 %56, ptr %6, align 4, !tbaa !17
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %57, i32 0, i32 0
  %59 = load i32, ptr %58, align 4, !tbaa !21
  %60 = load i32, ptr %6, align 4, !tbaa !17
  %61 = or i32 %60, %59
  store i32 %61, ptr %6, align 4, !tbaa !17
  %62 = load i32, ptr %6, align 4, !tbaa !17
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %63, i32 0, i32 0
  %65 = load ptr, ptr %64, align 8, !tbaa !14
  %66 = getelementptr inbounds %struct.TIM_TypeDef, ptr %65, i32 0, i32 1
  store volatile i32 %62, ptr %66, align 4, !tbaa !15
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !14
  %70 = icmp eq ptr %69, inttoptr (i64 1073807360 to ptr)
  br i1 %70, label %106, label %71

71:                                               ; preds = %52
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !14
  %75 = icmp eq ptr %74, inttoptr (i64 1073741824 to ptr)
  br i1 %75, label %106, label %76

76:                                               ; preds = %71
  %77 = load ptr, ptr %4, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !14
  %80 = icmp eq ptr %79, inttoptr (i64 1073742848 to ptr)
  br i1 %80, label %106, label %81

81:                                               ; preds = %76
  %82 = load ptr, ptr %4, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !14
  %85 = icmp eq ptr %84, inttoptr (i64 1073743872 to ptr)
  br i1 %85, label %106, label %86

86:                                               ; preds = %81
  %87 = load ptr, ptr %4, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !14
  %90 = icmp eq ptr %89, inttoptr (i64 1073744896 to ptr)
  br i1 %90, label %106, label %91

91:                                               ; preds = %86
  %92 = load ptr, ptr %4, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %92, i32 0, i32 0
  %94 = load ptr, ptr %93, align 8, !tbaa !14
  %95 = icmp eq ptr %94, inttoptr (i64 1073808384 to ptr)
  br i1 %95, label %106, label %96

96:                                               ; preds = %91
  %97 = load ptr, ptr %4, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %97, i32 0, i32 0
  %99 = load ptr, ptr %98, align 8, !tbaa !14
  %100 = icmp eq ptr %99, inttoptr (i64 1073747968 to ptr)
  br i1 %100, label %106, label %101

101:                                              ; preds = %96
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !14
  %105 = icmp eq ptr %104, inttoptr (i64 1073823744 to ptr)
  br i1 %105, label %106, label %121

106:                                              ; preds = %101, %96, %91, %86, %81, %76, %71, %52
  %107 = load i32, ptr %7, align 4, !tbaa !17
  %108 = zext i32 %107 to i64
  %109 = and i64 %108, -129
  %110 = trunc i64 %109 to i32
  store i32 %110, ptr %7, align 4, !tbaa !17
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.TIM_MasterConfigTypeDef, ptr %111, i32 0, i32 2
  %113 = load i32, ptr %112, align 4, !tbaa !22
  %114 = load i32, ptr %7, align 4, !tbaa !17
  %115 = or i32 %114, %113
  store i32 %115, ptr %7, align 4, !tbaa !17
  %116 = load i32, ptr %7, align 4, !tbaa !17
  %117 = load ptr, ptr %4, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %117, i32 0, i32 0
  %119 = load ptr, ptr %118, align 8, !tbaa !14
  %120 = getelementptr inbounds %struct.TIM_TypeDef, ptr %119, i32 0, i32 2
  store volatile i32 %116, ptr %120, align 4, !tbaa !18
  br label %121

121:                                              ; preds = %106, %101
  %122 = load ptr, ptr %4, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %122, i32 0, i32 5
  store volatile i32 1, ptr %123, align 4, !tbaa !13
  br label %124

124:                                              ; preds = %121
  %125 = load ptr, ptr %4, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %125, i32 0, i32 4
  store i32 0, ptr %126, align 8, !tbaa !9
  br label %127

127:                                              ; preds = %124
  br label %128

128:                                              ; preds = %127
  store i32 0, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %129

129:                                              ; preds = %128, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %130 = load i32, ptr %3, align 4
  ret i32 %130
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 96}
!10 = !{!"", !6, i64 0, !11, i64 8, !12, i64 32, !7, i64 40, !12, i64 96, !12, i64 100, !7, i64 104, !7, i64 128, !12, i64 144}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 100}
!14 = !{!10, !6, i64 0}
!15 = !{!16, !12, i64 4}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!17 = !{!12, !12, i64 0}
!18 = !{!16, !12, i64 8}
!19 = !{!20, !12, i64 4}
!20 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8}
!21 = !{!20, !12, i64 0}
!22 = !{!20, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIMEx_MasterConfigSynchronization(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 96
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %28, label %6

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 100
  store volatile i32 2, ptr %7, align 4, !tbaa !12
  %8 = load ptr, ptr %0, align 8, !tbaa !13
  %9 = getelementptr inbounds i8, ptr %8, i64 4
  %10 = load volatile i32, ptr %9, align 4, !tbaa !14
  %11 = getelementptr inbounds i8, ptr %8, i64 8
  %12 = load volatile i32, ptr %11, align 4, !tbaa !16
  %magicptr = ptrtoint ptr %8 to i64
  switch i64 %magicptr, label %18 [
    i64 1073807360, label %13
    i64 1073808384, label %13
  ]

13:                                               ; preds = %6, %6
  %14 = and i32 %10, -15728641
  %15 = getelementptr inbounds i8, ptr %1, i64 4
  %16 = load i32, ptr %15, align 4, !tbaa !17
  %17 = or i32 %16, %14
  br label %18

18:                                               ; preds = %6, %13
  %.0 = phi i32 [ %17, %13 ], [ %10, %6 ]
  %19 = and i32 %.0, -113
  %20 = load i32, ptr %1, align 4, !tbaa !19
  %21 = or i32 %19, %20
  store volatile i32 %21, ptr %9, align 4, !tbaa !14
  switch i64 %magicptr, label %27 [
    i64 1073807360, label %22
    i64 1073741824, label %22
    i64 1073742848, label %22
    i64 1073743872, label %22
    i64 1073744896, label %22
    i64 1073808384, label %22
    i64 1073747968, label %22
    i64 1073823744, label %22
  ]

22:                                               ; preds = %18, %18, %18, %18, %18, %18, %18, %18
  %23 = and i32 %12, -129
  %24 = getelementptr inbounds i8, ptr %1, i64 8
  %25 = load i32, ptr %24, align 4, !tbaa !20
  %26 = or i32 %25, %23
  store volatile i32 %26, ptr %11, align 4, !tbaa !16
  br label %27

27:                                               ; preds = %18, %22
  store volatile i32 1, ptr %7, align 4, !tbaa !12
  store i32 0, ptr %3, align 8, !tbaa !5
  br label %28

28:                                               ; preds = %2, %27
  %.030 = phi i32 [ 0, %27 ], [ 2, %2 ]
  ret i32 %.030
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 100}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 4}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!16 = !{!15, !11, i64 8}
!17 = !{!18, !11, i64 4}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!19 = !{!18, !11, i64 0}
!20 = !{!18, !11, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass