; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.DMA_Stream_TypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.BDMA_Channel_TypeDef = type { i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DMA_Start(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !9
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = icmp eq ptr %12, null
  br i1 %13, label %14, label %15

14:                                               ; preds = %4
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %249

15:                                               ; preds = %4
  br label %16

16:                                               ; preds = %15
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %17, i32 0, i32 2
  %19 = load i32, ptr %18, align 8, !tbaa !11
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  store i32 2, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %249

22:                                               ; preds = %16
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %23, i32 0, i32 2
  store i32 1, ptr %24, align 8, !tbaa !11
  br label %25

25:                                               ; preds = %22
  br label %26

26:                                               ; preds = %25
  br label %27

27:                                               ; preds = %26
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %28, i32 0, i32 3
  %30 = load volatile i32, ptr %29, align 4, !tbaa !14
  %31 = icmp eq i32 1, %30
  br i1 %31, label %32, label %239

32:                                               ; preds = %27
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %33, i32 0, i32 3
  store volatile i32 2, ptr %34, align 4, !tbaa !14
  %35 = load ptr, ptr %6, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %35, i32 0, i32 11
  store volatile i32 0, ptr %36, align 8, !tbaa !15
  %37 = load ptr, ptr %6, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !16
  %40 = icmp eq ptr %39, inttoptr (i64 1073872912 to ptr)
  br i1 %40, label %116, label %41

41:                                               ; preds = %32
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %42, i32 0, i32 0
  %44 = load ptr, ptr %43, align 8, !tbaa !16
  %45 = icmp eq ptr %44, inttoptr (i64 1073872936 to ptr)
  br i1 %45, label %116, label %46

46:                                               ; preds = %41
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %47, i32 0, i32 0
  %49 = load ptr, ptr %48, align 8, !tbaa !16
  %50 = icmp eq ptr %49, inttoptr (i64 1073872960 to ptr)
  br i1 %50, label %116, label %51

51:                                               ; preds = %46
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !16
  %55 = icmp eq ptr %54, inttoptr (i64 1073872984 to ptr)
  br i1 %55, label %116, label %56

56:                                               ; preds = %51
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !16
  %60 = icmp eq ptr %59, inttoptr (i64 1073873008 to ptr)
  br i1 %60, label %116, label %61

61:                                               ; preds = %56
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !16
  %65 = icmp eq ptr %64, inttoptr (i64 1073873032 to ptr)
  br i1 %65, label %116, label %66

66:                                               ; preds = %61
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !16
  %70 = icmp eq ptr %69, inttoptr (i64 1073873056 to ptr)
  br i1 %70, label %116, label %71

71:                                               ; preds = %66
  %72 = load ptr, ptr %6, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !16
  %75 = icmp eq ptr %74, inttoptr (i64 1073873080 to ptr)
  br i1 %75, label %116, label %76

76:                                               ; preds = %71
  %77 = load ptr, ptr %6, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !16
  %80 = icmp eq ptr %79, inttoptr (i64 1073873936 to ptr)
  br i1 %80, label %116, label %81

81:                                               ; preds = %76
  %82 = load ptr, ptr %6, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !16
  %85 = icmp eq ptr %84, inttoptr (i64 1073873960 to ptr)
  br i1 %85, label %116, label %86

86:                                               ; preds = %81
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !16
  %90 = icmp eq ptr %89, inttoptr (i64 1073873984 to ptr)
  br i1 %90, label %116, label %91

91:                                               ; preds = %86
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %92, i32 0, i32 0
  %94 = load ptr, ptr %93, align 8, !tbaa !16
  %95 = icmp eq ptr %94, inttoptr (i64 1073874008 to ptr)
  br i1 %95, label %116, label %96

96:                                               ; preds = %91
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %97, i32 0, i32 0
  %99 = load ptr, ptr %98, align 8, !tbaa !16
  %100 = icmp eq ptr %99, inttoptr (i64 1073874032 to ptr)
  br i1 %100, label %116, label %101

101:                                              ; preds = %96
  %102 = load ptr, ptr %6, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !16
  %105 = icmp eq ptr %104, inttoptr (i64 1073874056 to ptr)
  br i1 %105, label %116, label %106

106:                                              ; preds = %101
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %107, i32 0, i32 0
  %109 = load ptr, ptr %108, align 8, !tbaa !16
  %110 = icmp eq ptr %109, inttoptr (i64 1073874080 to ptr)
  br i1 %110, label %116, label %111

111:                                              ; preds = %106
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %112, i32 0, i32 0
  %114 = load ptr, ptr %113, align 8, !tbaa !16
  %115 = icmp eq ptr %114, inttoptr (i64 1073874104 to ptr)
  br i1 %115, label %116, label %125

116:                                              ; preds = %111, %106, %101, %96, %91, %86, %81, %76, %71, %66, %61, %56, %51, %46, %41, %32
  %117 = load ptr, ptr %6, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %117, i32 0, i32 0
  %119 = load ptr, ptr %118, align 8, !tbaa !16
  %120 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %119, i32 0, i32 0
  %121 = load volatile i32, ptr %120, align 4, !tbaa !17
  %122 = zext i32 %121 to i64
  %123 = and i64 %122, -2
  %124 = trunc i64 %123 to i32
  store volatile i32 %124, ptr %120, align 4, !tbaa !17
  br label %134

125:                                              ; preds = %111
  %126 = load ptr, ptr %6, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %126, i32 0, i32 0
  %128 = load ptr, ptr %127, align 8, !tbaa !16
  %129 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %128, i32 0, i32 0
  %130 = load volatile i32, ptr %129, align 4, !tbaa !19
  %131 = zext i32 %130 to i64
  %132 = and i64 %131, -2
  %133 = trunc i64 %132 to i32
  store volatile i32 %133, ptr %129, align 4, !tbaa !19
  br label %134

134:                                              ; preds = %125, %116
  %135 = phi i32 [ %124, %116 ], [ %133, %125 ]
  %136 = load ptr, ptr %6, align 8, !tbaa !5
  %137 = load i32, ptr %7, align 4, !tbaa !9
  %138 = load i32, ptr %8, align 4, !tbaa !9
  %139 = load i32, ptr %9, align 4, !tbaa !9
  call void @DMA_SetConfig(ptr noundef %136, i32 noundef %137, i32 noundef %138, i32 noundef %139)
  %140 = load ptr, ptr %6, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %140, i32 0, i32 0
  %142 = load ptr, ptr %141, align 8, !tbaa !16
  %143 = icmp eq ptr %142, inttoptr (i64 1073872912 to ptr)
  br i1 %143, label %219, label %144

144:                                              ; preds = %134
  %145 = load ptr, ptr %6, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %145, i32 0, i32 0
  %147 = load ptr, ptr %146, align 8, !tbaa !16
  %148 = icmp eq ptr %147, inttoptr (i64 1073872936 to ptr)
  br i1 %148, label %219, label %149

149:                                              ; preds = %144
  %150 = load ptr, ptr %6, align 8, !tbaa !5
  %151 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %150, i32 0, i32 0
  %152 = load ptr, ptr %151, align 8, !tbaa !16
  %153 = icmp eq ptr %152, inttoptr (i64 1073872960 to ptr)
  br i1 %153, label %219, label %154

154:                                              ; preds = %149
  %155 = load ptr, ptr %6, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %155, i32 0, i32 0
  %157 = load ptr, ptr %156, align 8, !tbaa !16
  %158 = icmp eq ptr %157, inttoptr (i64 1073872984 to ptr)
  br i1 %158, label %219, label %159

159:                                              ; preds = %154
  %160 = load ptr, ptr %6, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %160, i32 0, i32 0
  %162 = load ptr, ptr %161, align 8, !tbaa !16
  %163 = icmp eq ptr %162, inttoptr (i64 1073873008 to ptr)
  br i1 %163, label %219, label %164

164:                                              ; preds = %159
  %165 = load ptr, ptr %6, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %165, i32 0, i32 0
  %167 = load ptr, ptr %166, align 8, !tbaa !16
  %168 = icmp eq ptr %167, inttoptr (i64 1073873032 to ptr)
  br i1 %168, label %219, label %169

169:                                              ; preds = %164
  %170 = load ptr, ptr %6, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %170, i32 0, i32 0
  %172 = load ptr, ptr %171, align 8, !tbaa !16
  %173 = icmp eq ptr %172, inttoptr (i64 1073873056 to ptr)
  br i1 %173, label %219, label %174

174:                                              ; preds = %169
  %175 = load ptr, ptr %6, align 8, !tbaa !5
  %176 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %175, i32 0, i32 0
  %177 = load ptr, ptr %176, align 8, !tbaa !16
  %178 = icmp eq ptr %177, inttoptr (i64 1073873080 to ptr)
  br i1 %178, label %219, label %179

179:                                              ; preds = %174
  %180 = load ptr, ptr %6, align 8, !tbaa !5
  %181 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %180, i32 0, i32 0
  %182 = load ptr, ptr %181, align 8, !tbaa !16
  %183 = icmp eq ptr %182, inttoptr (i64 1073873936 to ptr)
  br i1 %183, label %219, label %184

184:                                              ; preds = %179
  %185 = load ptr, ptr %6, align 8, !tbaa !5
  %186 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %185, i32 0, i32 0
  %187 = load ptr, ptr %186, align 8, !tbaa !16
  %188 = icmp eq ptr %187, inttoptr (i64 1073873960 to ptr)
  br i1 %188, label %219, label %189

189:                                              ; preds = %184
  %190 = load ptr, ptr %6, align 8, !tbaa !5
  %191 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %190, i32 0, i32 0
  %192 = load ptr, ptr %191, align 8, !tbaa !16
  %193 = icmp eq ptr %192, inttoptr (i64 1073873984 to ptr)
  br i1 %193, label %219, label %194

194:                                              ; preds = %189
  %195 = load ptr, ptr %6, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %195, i32 0, i32 0
  %197 = load ptr, ptr %196, align 8, !tbaa !16
  %198 = icmp eq ptr %197, inttoptr (i64 1073874008 to ptr)
  br i1 %198, label %219, label %199

199:                                              ; preds = %194
  %200 = load ptr, ptr %6, align 8, !tbaa !5
  %201 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %200, i32 0, i32 0
  %202 = load ptr, ptr %201, align 8, !tbaa !16
  %203 = icmp eq ptr %202, inttoptr (i64 1073874032 to ptr)
  br i1 %203, label %219, label %204

204:                                              ; preds = %199
  %205 = load ptr, ptr %6, align 8, !tbaa !5
  %206 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %205, i32 0, i32 0
  %207 = load ptr, ptr %206, align 8, !tbaa !16
  %208 = icmp eq ptr %207, inttoptr (i64 1073874056 to ptr)
  br i1 %208, label %219, label %209

209:                                              ; preds = %204
  %210 = load ptr, ptr %6, align 8, !tbaa !5
  %211 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %210, i32 0, i32 0
  %212 = load ptr, ptr %211, align 8, !tbaa !16
  %213 = icmp eq ptr %212, inttoptr (i64 1073874080 to ptr)
  br i1 %213, label %219, label %214

214:                                              ; preds = %209
  %215 = load ptr, ptr %6, align 8, !tbaa !5
  %216 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %215, i32 0, i32 0
  %217 = load ptr, ptr %216, align 8, !tbaa !16
  %218 = icmp eq ptr %217, inttoptr (i64 1073874104 to ptr)
  br i1 %218, label %219, label %228

219:                                              ; preds = %214, %209, %204, %199, %194, %189, %184, %179, %174, %169, %164, %159, %154, %149, %144, %134
  %220 = load ptr, ptr %6, align 8, !tbaa !5
  %221 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %220, i32 0, i32 0
  %222 = load ptr, ptr %221, align 8, !tbaa !16
  %223 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %222, i32 0, i32 0
  %224 = load volatile i32, ptr %223, align 4, !tbaa !17
  %225 = zext i32 %224 to i64
  %226 = or i64 %225, 1
  %227 = trunc i64 %226 to i32
  store volatile i32 %227, ptr %223, align 4, !tbaa !17
  br label %237

228:                                              ; preds = %214
  %229 = load ptr, ptr %6, align 8, !tbaa !5
  %230 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %229, i32 0, i32 0
  %231 = load ptr, ptr %230, align 8, !tbaa !16
  %232 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %231, i32 0, i32 0
  %233 = load volatile i32, ptr %232, align 4, !tbaa !19
  %234 = zext i32 %233 to i64
  %235 = or i64 %234, 1
  %236 = trunc i64 %235 to i32
  store volatile i32 %236, ptr %232, align 4, !tbaa !19
  br label %237

237:                                              ; preds = %228, %219
  %238 = phi i32 [ %227, %219 ], [ %236, %228 ]
  br label %247

239:                                              ; preds = %27
  %240 = load ptr, ptr %6, align 8, !tbaa !5
  %241 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %240, i32 0, i32 11
  store volatile i32 2048, ptr %241, align 8, !tbaa !15
  br label %242

242:                                              ; preds = %239
  %243 = load ptr, ptr %6, align 8, !tbaa !5
  %244 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %243, i32 0, i32 2
  store i32 0, ptr %244, align 8, !tbaa !11
  br label %245

245:                                              ; preds = %242
  br label %246

246:                                              ; preds = %245
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %247

247:                                              ; preds = %246, %237
  %248 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %248, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %249

249:                                              ; preds = %247, %21, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %250 = load i32, ptr %5, align 4
  ret i32 %250
}

; Function Attrs: nounwind uwtable
declare hidden void @DMA_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 56}
!12 = !{!"__DMA_HandleTypeDef", !6, i64 0, !13, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!14 = !{!12, !10, i64 60}
!15 = !{!12, !10, i64 120}
!16 = !{!12, !6, i64 0}
!17 = !{!18, !10, i64 0}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!19 = !{!20, !10, i64 0}
!20 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_DMA_Start(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = icmp eq ptr %0, null
  br i1 %5, label %28, label %6

6:                                                ; preds = %4
  %7 = getelementptr inbounds i8, ptr %0, i64 56
  %8 = load i32, ptr %7, align 8, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %28, label %10

10:                                               ; preds = %6
  store i32 1, ptr %7, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %0, i64 60
  %12 = load volatile i32, ptr %11, align 4, !tbaa !12
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %14, label %26

14:                                               ; preds = %10
  store volatile i32 2, ptr %11, align 4, !tbaa !12
  %15 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 0, ptr %15, align 8, !tbaa !13
  %16 = load ptr, ptr %0, align 8, !tbaa !14
  %17 = load volatile i32, ptr %16, align 4, !tbaa !15
  %18 = and i32 %17, -2
  store volatile i32 %18, ptr %16, align 4, !tbaa !15
  tail call void @DMA_SetConfig(ptr noundef nonnull %0, i32 noundef %1, i32 noundef %2, i32 noundef %3)
  %19 = load ptr, ptr %0, align 8, !tbaa !14
  %magicptr74 = ptrtoint ptr %19 to i64
  switch i64 %magicptr74, label %23 [
    i64 1073872912, label %20
    i64 1073872936, label %20
    i64 1073872960, label %20
    i64 1073872984, label %20
    i64 1073873008, label %20
    i64 1073873032, label %20
    i64 1073873056, label %20
    i64 1073873080, label %20
    i64 1073873936, label %20
    i64 1073873960, label %20
    i64 1073873984, label %20
    i64 1073874008, label %20
    i64 1073874032, label %20
    i64 1073874056, label %20
    i64 1073874080, label %20
    i64 1073874104, label %20
  ]

20:                                               ; preds = %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14, %14
  %21 = load volatile i32, ptr %19, align 4, !tbaa !16
  %22 = or i32 %21, 1
  store volatile i32 %22, ptr %19, align 4, !tbaa !16
  br label %28

23:                                               ; preds = %14
  %24 = load volatile i32, ptr %19, align 4, !tbaa !18
  %25 = or i32 %24, 1
  store volatile i32 %25, ptr %19, align 4, !tbaa !18
  br label %28

26:                                               ; preds = %10
  %27 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 2048, ptr %27, align 8, !tbaa !13
  store i32 0, ptr %7, align 8, !tbaa !5
  br label %28

28:                                               ; preds = %26, %23, %20, %6, %4
  %.049 = phi i32 [ 1, %4 ], [ 2, %6 ], [ 0, %20 ], [ 0, %23 ], [ 1, %26 ]
  ret i32 %.049
}

; Function Attrs: nounwind uwtable
declare hidden void @DMA_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 56}
!6 = !{!"__DMA_HandleTypeDef", !7, i64 0, !10, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 60}
!13 = !{!6, !11, i64 120}
!14 = !{!6, !7, i64 0}
!15 = !{!11, !11, i64 0}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!18 = !{!19, !11, i64 0}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass