; LLVM IR from ritikbanger/Hacktoberfest2022-DSA :: 04. Arrays/Merge Sorted Array.ll (Z5mergeRSt6vectorIiSaIiEEiS2_i)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5mergeRSt6vectorIiSaIiEEiS2_i(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  %12 = load i32, ptr %6, align 4, !tbaa !9
  %13 = sub nsw i32 %12, 1
  store i32 %13, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = sub nsw i32 %14, 1
  store i32 %15, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  %16 = load i32, ptr %6, align 4, !tbaa !9
  %17 = load i32, ptr %8, align 4, !tbaa !9
  %18 = add nsw i32 %16, %17
  %19 = sub nsw i32 %18, 1
  store i32 %19, ptr %11, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %68, %4
  %21 = load i32, ptr %9, align 4, !tbaa !9
  %22 = icmp sge i32 %21, 0
  br i1 %22, label %23, label %26

23:                                               ; preds = %20
  %24 = load i32, ptr %10, align 4, !tbaa !9
  %25 = icmp sge i32 %24, 0
  br label %26

26:                                               ; preds = %23, %20
  %27 = phi i1 [ false, %20 ], [ %25, %23 ]
  br i1 %27, label %28, label %69

28:                                               ; preds = %26
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = load i32, ptr %9, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #2
  %33 = load i32, ptr %32, align 4, !tbaa !9
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = load i32, ptr %10, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #2
  %38 = load i32, ptr %37, align 4, !tbaa !9
  %39 = icmp sgt i32 %33, %38
  br i1 %39, label %40, label %54

40:                                               ; preds = %28
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = load i32, ptr %9, align 4, !tbaa !9
  %43 = sext i32 %42 to i64
  %44 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %43) #2
  %45 = load i32, ptr %44, align 4, !tbaa !9
  %46 = load ptr, ptr %5, align 8, !tbaa !5
  %47 = load i32, ptr %11, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #2
  store i32 %45, ptr %49, align 4, !tbaa !9
  %50 = load i32, ptr %9, align 4, !tbaa !9
  %51 = add nsw i32 %50, -1
  store i32 %51, ptr %9, align 4, !tbaa !9
  %52 = load i32, ptr %11, align 4, !tbaa !9
  %53 = add nsw i32 %52, -1
  store i32 %53, ptr %11, align 4, !tbaa !9
  br label %68

54:                                               ; preds = %28
  %55 = load ptr, ptr %7, align 8, !tbaa !5
  %56 = load i32, ptr %10, align 4, !tbaa !9
  %57 = sext i32 %56 to i64
  %58 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %55, i64 noundef %57) #2
  %59 = load i32, ptr %58, align 4, !tbaa !9
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = load i32, ptr %11, align 4, !tbaa !9
  %62 = sext i32 %61 to i64
  %63 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %62) #2
  store i32 %59, ptr %63, align 4, !tbaa !9
  %64 = load i32, ptr %10, align 4, !tbaa !9
  %65 = add nsw i32 %64, -1
  store i32 %65, ptr %10, align 4, !tbaa !9
  %66 = load i32, ptr %11, align 4, !tbaa !9
  %67 = add nsw i32 %66, -1
  store i32 %67, ptr %11, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %54, %40
  br label %20, !llvm.loop !11

69:                                               ; preds = %26
  br label %70

70:                                               ; preds = %73, %69
  %71 = load i32, ptr %9, align 4, !tbaa !9
  %72 = icmp sge i32 %71, 0
  br i1 %72, label %73, label %85

73:                                               ; preds = %70
  %74 = load ptr, ptr %5, align 8, !tbaa !5
  %75 = load i32, ptr %9, align 4, !tbaa !9
  %76 = add nsw i32 %75, -1
  store i32 %76, ptr %9, align 4, !tbaa !9
  %77 = sext i32 %75 to i64
  %78 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %74, i64 noundef %77) #2
  %79 = load i32, ptr %78, align 4, !tbaa !9
  %80 = load ptr, ptr %5, align 8, !tbaa !5
  %81 = load i32, ptr %11, align 4, !tbaa !9
  %82 = add nsw i32 %81, -1
  store i32 %82, ptr %11, align 4, !tbaa !9
  %83 = sext i32 %81 to i64
  %84 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %80, i64 noundef %83) #2
  store i32 %79, ptr %84, align 4, !tbaa !9
  br label %70, !llvm.loop !13

85:                                               ; preds = %70
  br label %86

86:                                               ; preds = %89, %85
  %87 = load i32, ptr %10, align 4, !tbaa !9
  %88 = icmp sge i32 %87, 0
  br i1 %88, label %89, label %101

89:                                               ; preds = %86
  %90 = load ptr, ptr %7, align 8, !tbaa !5
  %91 = load i32, ptr %10, align 4, !tbaa !9
  %92 = add nsw i32 %91, -1
  store i32 %92, ptr %10, align 4, !tbaa !9
  %93 = sext i32 %91 to i64
  %94 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %90, i64 noundef %93) #2
  %95 = load i32, ptr %94, align 4, !tbaa !9
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = load i32, ptr %11, align 4, !tbaa !9
  %98 = add nsw i32 %97, -1
  store i32 %98, ptr %11, align 4, !tbaa !9
  %99 = sext i32 %97 to i64
  %100 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %96, i64 noundef %99) #2
  store i32 %95, ptr %100, align 4, !tbaa !9
  br label %86, !llvm.loop !14

101:                                              ; preds = %86
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5mergeRSt6vectorIiSaIiEEiS2_i(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = add nsw i32 %1, -1
  %6 = add nsw i32 %3, -1
  %7 = add i32 %3, %1
  %.038 = add i32 %7, -1
  %8 = icmp sgt i32 %1, 0
  %9 = icmp sgt i32 %3, 0
  %10 = and i1 %8, %9
  br i1 %10, label %.lr.ph.preheader, label %.preheader37

.lr.ph.preheader:                                 ; preds = %4
  %11 = sext i32 %.038 to i64
  br label %.lr.ph

.preheader37.loopexit:                            ; preds = %33
  %12 = trunc nsw i64 %indvars.iv.next to i32
  br label %.preheader37

.preheader37:                                     ; preds = %.preheader37.loopexit, %4
  %.034.lcssa = phi i32 [ %5, %4 ], [ %.135, %.preheader37.loopexit ]
  %.031.lcssa = phi i32 [ %6, %4 ], [ %.132, %.preheader37.loopexit ]
  %.0.lcssa = phi i32 [ %.038, %4 ], [ %12, %.preheader37.loopexit ]
  %13 = icmp sgt i32 %.034.lcssa, -1
  br i1 %13, label %.lr.ph46.preheader, label %.preheader

.lr.ph46.preheader:                               ; preds = %.preheader37
  %14 = sext i32 %.0.lcssa to i64
  %15 = zext nneg i32 %.034.lcssa to i64
  br label %.lr.ph46

.lr.ph:                                           ; preds = %.lr.ph.preheader, %33
  %indvars.iv = phi i64 [ %11, %.lr.ph.preheader ], [ %indvars.iv.next, %33 ]
  %.03140 = phi i32 [ %6, %.lr.ph.preheader ], [ %.132, %33 ]
  %.03439 = phi i32 [ %5, %.lr.ph.preheader ], [ %.135, %33 ]
  %16 = zext nneg i32 %.03439 to i64
  %17 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %16) #1
  %18 = load i32, ptr %17, align 4, !tbaa !5
  %19 = zext nneg i32 %.03140 to i64
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %19) #1
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = icmp sgt i32 %18, %21
  br i1 %22, label %23, label %28

23:                                               ; preds = %.lr.ph
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %16) #1
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #1
  store i32 %25, ptr %26, align 4, !tbaa !5
  %27 = add nsw i32 %.03439, -1
  br label %33

28:                                               ; preds = %.lr.ph
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %19) #1
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %31 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #1
  store i32 %30, ptr %31, align 4, !tbaa !5
  %32 = add nsw i32 %.03140, -1
  br label %33

33:                                               ; preds = %28, %23
  %.135 = phi i32 [ %27, %23 ], [ %.03439, %28 ]
  %.132 = phi i32 [ %.03140, %23 ], [ %32, %28 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %34 = icmp sgt i32 %.135, -1
  %35 = icmp sgt i32 %.132, -1
  %36 = select i1 %34, i1 %35, i1 false
  br i1 %36, label %.lr.ph, label %.preheader37.loopexit, !llvm.loop !9

.preheader.loopexit:                              ; preds = %.lr.ph46
  %37 = trunc nsw i64 %indvars.iv.next54 to i32
  br label %.preheader

.preheader:                                       ; preds = %.preheader.loopexit, %.preheader37
  %.2.lcssa = phi i32 [ %.0.lcssa, %.preheader37 ], [ %37, %.preheader.loopexit ]
  %38 = icmp sgt i32 %.031.lcssa, -1
  br i1 %38, label %.lr.ph50.preheader, label %._crit_edge

.lr.ph50.preheader:                               ; preds = %.preheader
  %39 = sext i32 %.2.lcssa to i64
  %40 = zext nneg i32 %.031.lcssa to i64
  br label %.lr.ph50

.lr.ph46:                                         ; preds = %.lr.ph46.preheader, %.lr.ph46
  %indvars.iv55 = phi i64 [ %15, %.lr.ph46.preheader ], [ %indvars.iv.next56, %.lr.ph46 ]
  %indvars.iv53 = phi i64 [ %14, %.lr.ph46.preheader ], [ %indvars.iv.next54, %.lr.ph46 ]
  %indvars.iv.next56 = add nsw i64 %indvars.iv55, -1
  %41 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv55) #1
  %42 = load i32, ptr %41, align 4, !tbaa !5
  %indvars.iv.next54 = add nsw i64 %indvars.iv53, -1
  %43 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv53) #1
  store i32 %42, ptr %43, align 4, !tbaa !5
  %.not = icmp eq i64 %indvars.iv55, 0
  br i1 %.not, label %.preheader.loopexit, label %.lr.ph46, !llvm.loop !11

.lr.ph50:                                         ; preds = %.lr.ph50.preheader, %.lr.ph50
  %indvars.iv62 = phi i64 [ %40, %.lr.ph50.preheader ], [ %indvars.iv.next63, %.lr.ph50 ]
  %indvars.iv60 = phi i64 [ %39, %.lr.ph50.preheader ], [ %indvars.iv.next61, %.lr.ph50 ]
  %indvars.iv.next63 = add nsw i64 %indvars.iv62, -1
  %44 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv62) #1
  %45 = load i32, ptr %44, align 4, !tbaa !5
  %indvars.iv.next61 = add nsw i64 %indvars.iv60, -1
  %46 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv60) #1
  store i32 %45, ptr %46, align 4, !tbaa !5
  %.not67 = icmp eq i64 %indvars.iv62, 0
  br i1 %.not67, label %._crit_edge, label %.lr.ph50, !llvm.loop !12

._crit_edge:                                      ; preds = %.lr.ph50, %.preheader
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass