; LLVM IR from ctlst-tech/catpilot :: os/freertos/core/src (queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @prvInitialiseNewQueue(i64 noundef, i64 noundef, ptr noundef, i8 noundef zeroext, ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local ptr @xQueueGenericCreate(i64 noundef %0, i64 noundef %1, i8 noundef zeroext %2) #2 {
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca ptr, align 8
  store i64 %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !5
  store i8 %2, ptr %6, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %10 = load i64, ptr %4, align 8, !tbaa !5
  %11 = icmp ugt i64 %10, 0
  %12 = zext i1 %11 to i32
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %14, label %16

14:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %15

15:                                               ; preds = %15, %14
  br label %15

16:                                               ; preds = %3
  %17 = load i64, ptr %4, align 8, !tbaa !5
  %18 = load i64, ptr %5, align 8, !tbaa !5
  %19 = mul i64 %17, %18
  store i64 %19, ptr %8, align 8, !tbaa !5
  %20 = load i64, ptr %5, align 8, !tbaa !5
  %21 = icmp eq i64 %20, 0
  br i1 %21, label %28, label %22

22:                                               ; preds = %16
  %23 = load i64, ptr %4, align 8, !tbaa !5
  %24 = load i64, ptr %8, align 8, !tbaa !5
  %25 = load i64, ptr %5, align 8, !tbaa !5
  %26 = udiv i64 %24, %25
  %27 = icmp eq i64 %23, %26
  br label %28

28:                                               ; preds = %22, %16
  %29 = phi i1 [ true, %16 ], [ %27, %22 ]
  %30 = zext i1 %29 to i32
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %34

32:                                               ; preds = %28
  call void @vPortRaiseBASEPRI()
  br label %33

33:                                               ; preds = %33, %32
  br label %33

34:                                               ; preds = %28
  %35 = load i64, ptr %8, align 8, !tbaa !5
  %36 = add i64 144, %35
  %37 = load i64, ptr %8, align 8, !tbaa !5
  %38 = icmp ugt i64 %36, %37
  %39 = zext i1 %38 to i32
  %40 = icmp eq i32 %39, 0
  br i1 %40, label %41, label %43

41:                                               ; preds = %34
  call void @vPortRaiseBASEPRI()
  br label %42

42:                                               ; preds = %42, %41
  br label %42

43:                                               ; preds = %34
  %44 = load i64, ptr %8, align 8, !tbaa !5
  %45 = add i64 144, %44
  %46 = call ptr @pvPortMalloc(i64 noundef %45)
  store ptr %46, ptr %7, align 8, !tbaa !10
  %47 = load ptr, ptr %7, align 8, !tbaa !10
  %48 = icmp ne ptr %47, null
  br i1 %48, label %49, label %60

49:                                               ; preds = %43
  %50 = load ptr, ptr %7, align 8, !tbaa !10
  store ptr %50, ptr %9, align 8, !tbaa !10
  %51 = load ptr, ptr %9, align 8, !tbaa !10
  %52 = getelementptr inbounds i8, ptr %51, i64 144
  store ptr %52, ptr %9, align 8, !tbaa !10
  %53 = load ptr, ptr %7, align 8, !tbaa !10
  %54 = getelementptr inbounds %struct.QueueDefinition, ptr %53, i32 0, i32 10
  store i8 0, ptr %54, align 2, !tbaa !12
  %55 = load i64, ptr %4, align 8, !tbaa !5
  %56 = load i64, ptr %5, align 8, !tbaa !5
  %57 = load ptr, ptr %9, align 8, !tbaa !10
  %58 = load i8, ptr %6, align 1, !tbaa !9
  %59 = load ptr, ptr %7, align 8, !tbaa !10
  call void @prvInitialiseNewQueue(i64 noundef %55, i64 noundef %56, ptr noundef %57, i8 noundef zeroext %58, ptr noundef %59)
  br label %61

60:                                               ; preds = %43
  br label %61

61:                                               ; preds = %60, %49
  %62 = load ptr, ptr %7, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret ptr %62
}

declare ptr @pvPortMalloc(i64 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!13, !7, i64 138}
!13 = !{!"QueueDefinition", !11, i64 0, !11, i64 8, !7, i64 16, !14, i64 32, !14, i64 72, !6, i64 112, !6, i64 120, !6, i64 128, !7, i64 136, !7, i64 137, !7, i64 138}
!14 = !{!"xLIST", !6, i64 0, !11, i64 8, !15, i64 16}
!15 = !{!"xMINI_LIST_ITEM", !16, i64 0, !11, i64 8, !11, i64 16}
!16 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @prvInitialiseNewQueue(i64 noundef, i64 noundef, ptr noundef, i8 noundef zeroext, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local ptr @xQueueGenericCreate(i64 noundef %0, i64 noundef %1, i8 noundef zeroext %2) local_unnamed_addr #1 {
  %.not = icmp eq i64 %0, 0
  br i1 %.not, label %4, label %6

4:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %5

5:                                                ; preds = %5, %4
  br label %5

6:                                                ; preds = %3
  %mul = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %1, i64 %0)
  %mul.val = extractvalue { i64, i1 } %mul, 0
  %mul.ov = extractvalue { i64, i1 } %mul, 1
  br i1 %mul.ov, label %7, label %9

7:                                                ; preds = %6
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %6
  %10 = icmp ugt i64 %mul.val, -145
  br i1 %10, label %11, label %13

11:                                               ; preds = %9
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

13:                                               ; preds = %9
  %14 = add nuw i64 %mul.val, 144
  %15 = tail call ptr @pvPortMalloc(i64 noundef %14) #4
  %.not20 = icmp eq ptr %15, null
  br i1 %.not20, label %19, label %16

16:                                               ; preds = %13
  %17 = getelementptr inbounds i8, ptr %15, i64 144
  %18 = getelementptr inbounds i8, ptr %15, i64 138
  store i8 0, ptr %18, align 2, !tbaa !5
  tail call void @prvInitialiseNewQueue(i64 noundef %0, i64 noundef %1, ptr noundef nonnull %17, i8 noundef zeroext %2, ptr noundef nonnull %15)
  br label %19

19:                                               ; preds = %13, %16
  ret ptr %15
}

declare ptr @pvPortMalloc(i64 noundef) local_unnamed_addr #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #3

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 138}
!6 = !{!"QueueDefinition", !7, i64 0, !7, i64 8, !8, i64 16, !10, i64 32, !10, i64 72, !11, i64 112, !11, i64 120, !11, i64 128, !8, i64 136, !8, i64 137, !8, i64 138}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !7, i64 8, !12, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"xMINI_LIST_ITEM", !13, i64 0, !7, i64 8, !7, i64 16}
!13 = !{!"int", !8, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass