; LLVM IR from ctlst-tech/catpilot :: os/freertos/core/src (tasks)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [24 x i8], ptr, i64, i64, ptr, [5 x ptr], [3 x i32], [3 x i8], i8, i8, i32 }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@xTickCount = external hidden global i32, align 4
@pxReadyTasksLists = external hidden global [32 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortEnterCritical() #2

declare i64 @uxListRemove(ptr noundef) #2

declare void @vListInsertEnd(ptr noundef, ptr noundef) #2

declare void @vPortExitCritical() #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xTaskGenericNotify(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4) #3 {
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i8, align 1
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i64 %1, ptr %7, align 8, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !11
  store i32 %3, ptr %9, align 4, !tbaa !11
  store ptr %4, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  store i64 1, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #4
  %14 = load i64, ptr %7, align 8, !tbaa !9
  %15 = icmp ult i64 %14, 3
  %16 = zext i1 %15 to i32
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %20

18:                                               ; preds = %5
  call void @vPortRaiseBASEPRI()
  br label %19

19:                                               ; preds = %19, %18
  br label %19

20:                                               ; preds = %5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %23, label %25

23:                                               ; preds = %20
  call void @vPortRaiseBASEPRI()
  br label %24

24:                                               ; preds = %24, %23
  br label %24

25:                                               ; preds = %20
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %26, ptr %11, align 8, !tbaa !5
  call void @vPortEnterCritical()
  %27 = load ptr, ptr %10, align 8, !tbaa !5
  %28 = icmp ne ptr %27, null
  br i1 %28, label %29, label %36

29:                                               ; preds = %25
  %30 = load ptr, ptr %11, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %30, i32 0, i32 11
  %32 = load i64, ptr %7, align 8, !tbaa !9
  %33 = getelementptr inbounds [3 x i32], ptr %31, i64 0, i64 %32
  %34 = load volatile i32, ptr %33, align 4, !tbaa !11
  %35 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %34, ptr %35, align 4, !tbaa !11
  br label %36

36:                                               ; preds = %29, %25
  %37 = load ptr, ptr %11, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %37, i32 0, i32 12
  %39 = load i64, ptr %7, align 8, !tbaa !9
  %40 = getelementptr inbounds [3 x i8], ptr %38, i64 0, i64 %39
  %41 = load volatile i8, ptr %40, align 1, !tbaa !13
  store i8 %41, ptr %13, align 1, !tbaa !13
  %42 = load ptr, ptr %11, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %42, i32 0, i32 12
  %44 = load i64, ptr %7, align 8, !tbaa !9
  %45 = getelementptr inbounds [3 x i8], ptr %43, i64 0, i64 %44
  store volatile i8 2, ptr %45, align 1, !tbaa !13
  %46 = load i32, ptr %9, align 4, !tbaa !11
  switch i32 %46, label %80 [
    i32 1, label %47
    i32 2, label %55
    i32 3, label %62
    i32 4, label %68
    i32 0, label %88
  ]

47:                                               ; preds = %36
  %48 = load i32, ptr %8, align 4, !tbaa !11
  %49 = load ptr, ptr %11, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %49, i32 0, i32 11
  %51 = load i64, ptr %7, align 8, !tbaa !9
  %52 = getelementptr inbounds [3 x i32], ptr %50, i64 0, i64 %51
  %53 = load volatile i32, ptr %52, align 4, !tbaa !11
  %54 = or i32 %53, %48
  store volatile i32 %54, ptr %52, align 4, !tbaa !11
  br label %88

55:                                               ; preds = %36
  %56 = load ptr, ptr %11, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %56, i32 0, i32 11
  %58 = load i64, ptr %7, align 8, !tbaa !9
  %59 = getelementptr inbounds [3 x i32], ptr %57, i64 0, i64 %58
  %60 = load volatile i32, ptr %59, align 4, !tbaa !11
  %61 = add i32 %60, 1
  store volatile i32 %61, ptr %59, align 4, !tbaa !11
  br label %88

62:                                               ; preds = %36
  %63 = load i32, ptr %8, align 4, !tbaa !11
  %64 = load ptr, ptr %11, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %64, i32 0, i32 11
  %66 = load i64, ptr %7, align 8, !tbaa !9
  %67 = getelementptr inbounds [3 x i32], ptr %65, i64 0, i64 %66
  store volatile i32 %63, ptr %67, align 4, !tbaa !11
  br label %88

68:                                               ; preds = %36
  %69 = load i8, ptr %13, align 1, !tbaa !13
  %70 = zext i8 %69 to i32
  %71 = icmp ne i32 %70, 2
  br i1 %71, label %72, label %78

72:                                               ; preds = %68
  %73 = load i32, ptr %8, align 4, !tbaa !11
  %74 = load ptr, ptr %11, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %74, i32 0, i32 11
  %76 = load i64, ptr %7, align 8, !tbaa !9
  %77 = getelementptr inbounds [3 x i32], ptr %75, i64 0, i64 %76
  store volatile i32 %73, ptr %77, align 4, !tbaa !11
  br label %79

78:                                               ; preds = %68
  store i64 0, ptr %12, align 8, !tbaa !9
  br label %79

79:                                               ; preds = %78, %72
  br label %88

80:                                               ; preds = %36
  %81 = load volatile i32, ptr @xTickCount, align 4, !tbaa !11
  %82 = icmp eq i32 %81, 0
  %83 = zext i1 %82 to i32
  %84 = icmp eq i32 %83, 0
  br i1 %84, label %85, label %87

85:                                               ; preds = %80
  call void @vPortRaiseBASEPRI()
  br label %86

86:                                               ; preds = %86, %85
  br label %86

87:                                               ; preds = %80
  br label %88

88:                                               ; preds = %87, %79, %62, %55, %47, %36
  %89 = load i8, ptr %13, align 1, !tbaa !13
  %90 = zext i8 %89 to i32
  %91 = icmp eq i32 %90, 1
  br i1 %91, label %92, label %132

92:                                               ; preds = %88
  %93 = load ptr, ptr %11, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %93, i32 0, i32 1
  %95 = call i64 @uxListRemove(ptr noundef %94)
  %96 = load ptr, ptr %11, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %96, i32 0, i32 3
  %98 = load i64, ptr %97, align 8, !tbaa !14
  %99 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %100 = icmp ugt i64 %98, %99
  br i1 %100, label %101, label %105

101:                                              ; preds = %92
  %102 = load ptr, ptr %11, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %102, i32 0, i32 3
  %104 = load i64, ptr %103, align 8, !tbaa !14
  store volatile i64 %104, ptr @uxTopReadyPriority, align 8, !tbaa !9
  br label %105

105:                                              ; preds = %101, %92
  %106 = load ptr, ptr %11, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %106, i32 0, i32 3
  %108 = load i64, ptr %107, align 8, !tbaa !14
  %109 = getelementptr inbounds [32 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %108
  %110 = load ptr, ptr %11, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %110, i32 0, i32 1
  call void @vListInsertEnd(ptr noundef %109, ptr noundef %111)
  %112 = load ptr, ptr %11, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %112, i32 0, i32 2
  %114 = getelementptr inbounds %struct.xLIST_ITEM, ptr %113, i32 0, i32 4
  %115 = load ptr, ptr %114, align 8, !tbaa !17
  %116 = icmp eq ptr %115, null
  %117 = zext i1 %116 to i32
  %118 = icmp eq i32 %117, 0
  br i1 %118, label %119, label %121

119:                                              ; preds = %105
  call void @vPortRaiseBASEPRI()
  br label %120

120:                                              ; preds = %120, %119
  br label %120

121:                                              ; preds = %105
  %122 = load ptr, ptr %11, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %122, i32 0, i32 3
  %124 = load i64, ptr %123, align 8, !tbaa !14
  %125 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %125, i32 0, i32 3
  %127 = load i64, ptr %126, align 8, !tbaa !14
  %128 = icmp ugt i64 %124, %127
  br i1 %128, label %129, label %130

129:                                              ; preds = %121
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !11
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %131

130:                                              ; preds = %121
  br label %131

131:                                              ; preds = %130, %129
  br label %133

132:                                              ; preds = %88
  br label %133

133:                                              ; preds = %132, %131
  call void @vPortExitCritical()
  %134 = load i64, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  ret i64 %134
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !10, i64 88}
!15 = !{!"tskTaskControlBlock", !6, i64 0, !16, i64 8, !16, i64 48, !10, i64 88, !6, i64 96, !7, i64 104, !6, i64 128, !10, i64 136, !10, i64 144, !6, i64 152, !7, i64 160, !7, i64 200, !7, i64 212, !7, i64 215, !7, i64 216, !12, i64 220}
!16 = !{!"xLIST_ITEM", !12, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!17 = !{!15, !6, i64 80}
!18 = !{i64 2148536548}
!19 = !{i64 2148536618}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@xTickCount = external hidden global i32, align 4
@pxReadyTasksLists = external hidden global [32 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare void @vPortEnterCritical() local_unnamed_addr #1

declare i64 @uxListRemove(ptr noundef) local_unnamed_addr #1

declare void @vListInsertEnd(ptr noundef, ptr noundef) local_unnamed_addr #1

declare void @vPortExitCritical() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xTaskGenericNotify(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef writeonly %4) local_unnamed_addr #2 {
  %6 = icmp ugt i64 %1, 2
  br i1 %6, label %7, label %9

7:                                                ; preds = %5
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %5
  %10 = icmp eq ptr %0, null
  br i1 %10, label %11, label %13

11:                                               ; preds = %9
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

13:                                               ; preds = %9
  tail call void @vPortEnterCritical() #3
  %.not = icmp eq ptr %4, null
  br i1 %.not, label %18, label %14

14:                                               ; preds = %13
  %15 = getelementptr inbounds i8, ptr %0, i64 200
  %16 = getelementptr inbounds [3 x i32], ptr %15, i64 0, i64 %1
  %17 = load volatile i32, ptr %16, align 4, !tbaa !5
  store i32 %17, ptr %4, align 4, !tbaa !5
  br label %18

18:                                               ; preds = %14, %13
  %19 = getelementptr inbounds i8, ptr %0, i64 212
  %20 = getelementptr inbounds [3 x i8], ptr %19, i64 0, i64 %1
  %21 = load volatile i8, ptr %20, align 1, !tbaa !9
  store volatile i8 2, ptr %20, align 1, !tbaa !9
  switch i32 %3, label %39 [
    i32 1, label %22
    i32 2, label %27
    i32 3, label %32
    i32 4, label %35
    i32 0, label %43
  ]

22:                                               ; preds = %18
  %23 = getelementptr inbounds i8, ptr %0, i64 200
  %24 = getelementptr inbounds [3 x i32], ptr %23, i64 0, i64 %1
  %25 = load volatile i32, ptr %24, align 4, !tbaa !5
  %26 = or i32 %25, %2
  store volatile i32 %26, ptr %24, align 4, !tbaa !5
  br label %43

27:                                               ; preds = %18
  %28 = getelementptr inbounds i8, ptr %0, i64 200
  %29 = getelementptr inbounds [3 x i32], ptr %28, i64 0, i64 %1
  %30 = load volatile i32, ptr %29, align 4, !tbaa !5
  %31 = add i32 %30, 1
  store volatile i32 %31, ptr %29, align 4, !tbaa !5
  br label %43

32:                                               ; preds = %18
  %33 = getelementptr inbounds i8, ptr %0, i64 200
  %34 = getelementptr inbounds [3 x i32], ptr %33, i64 0, i64 %1
  store volatile i32 %2, ptr %34, align 4, !tbaa !5
  br label %43

35:                                               ; preds = %18
  %.not34 = icmp eq i8 %21, 2
  br i1 %.not34, label %.thread, label %36

36:                                               ; preds = %35
  %37 = getelementptr inbounds i8, ptr %0, i64 200
  %38 = getelementptr inbounds [3 x i32], ptr %37, i64 0, i64 %1
  store volatile i32 %2, ptr %38, align 4, !tbaa !5
  br label %43

39:                                               ; preds = %18
  %40 = load volatile i32, ptr @xTickCount, align 4, !tbaa !5
  %.not35 = icmp eq i32 %40, 0
  br i1 %.not35, label %43, label %41

41:                                               ; preds = %39
  tail call void @vPortRaiseBASEPRI()
  br label %42

42:                                               ; preds = %42, %41
  br label %42

43:                                               ; preds = %39, %36, %32, %27, %22, %18
  %44 = icmp eq i8 %21, 1
  br i1 %44, label %45, label %.thread

45:                                               ; preds = %43
  %46 = getelementptr inbounds i8, ptr %0, i64 8
  %47 = tail call i64 @uxListRemove(ptr noundef nonnull %46) #3
  %48 = getelementptr inbounds i8, ptr %0, i64 88
  %49 = load i64, ptr %48, align 8, !tbaa !10
  %50 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %51 = icmp ugt i64 %49, %50
  br i1 %51, label %52, label %53

52:                                               ; preds = %45
  store volatile i64 %49, ptr @uxTopReadyPriority, align 8, !tbaa !15
  br label %53

53:                                               ; preds = %52, %45
  %54 = getelementptr inbounds [32 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %49
  tail call void @vListInsertEnd(ptr noundef nonnull %54, ptr noundef nonnull %46) #3
  %55 = getelementptr inbounds i8, ptr %0, i64 80
  %56 = load ptr, ptr %55, align 8, !tbaa !16
  %.not36 = icmp eq ptr %56, null
  br i1 %.not36, label %59, label %57

57:                                               ; preds = %53
  tail call void @vPortRaiseBASEPRI()
  br label %58

58:                                               ; preds = %58, %57
  br label %58

59:                                               ; preds = %53
  %60 = load i64, ptr %48, align 8, !tbaa !10
  %61 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !17
  %62 = getelementptr inbounds i8, ptr %61, i64 88
  %63 = load i64, ptr %62, align 8, !tbaa !10
  %64 = icmp ugt i64 %60, %63
  br i1 %64, label %65, label %.thread

65:                                               ; preds = %59
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !18
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !19
  br label %.thread

.thread:                                          ; preds = %35, %43, %65, %59
  %.038 = phi i64 [ 1, %43 ], [ 1, %65 ], [ 1, %59 ], [ 0, %35 ]
  tail call void @vPortExitCritical() #3
  ret i64 %.038
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !14, i64 88}
!11 = !{!"tskTaskControlBlock", !12, i64 0, !13, i64 8, !13, i64 48, !14, i64 88, !12, i64 96, !7, i64 104, !12, i64 128, !14, i64 136, !14, i64 144, !12, i64 152, !7, i64 160, !7, i64 200, !7, i64 212, !7, i64 215, !7, i64 216, !6, i64 220}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!"xLIST_ITEM", !6, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32}
!14 = !{!"long", !7, i64 0}
!15 = !{!14, !14, i64 0}
!16 = !{!11, !12, i64 80}
!17 = !{!12, !12, i64 0}
!18 = !{i64 2148536548}
!19 = !{i64 2148536618}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass