; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_HallSensor_Start_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 6
  %14 = getelementptr inbounds [6 x i32], ptr %13, i64 0, i64 0
  %15 = load volatile i32, ptr %14, align 8, !tbaa !11
  store i32 %15, ptr %9, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %16, i32 0, i32 7
  %18 = getelementptr inbounds [4 x i32], ptr %17, i64 0, i64 0
  %19 = load volatile i32, ptr %18, align 8, !tbaa !11
  store i32 %19, ptr %10, align 4, !tbaa !11
  %20 = load i32, ptr %9, align 4, !tbaa !11
  %21 = icmp eq i32 %20, 2
  br i1 %21, label %25, label %22

22:                                               ; preds = %3
  %23 = load i32, ptr %10, align 4, !tbaa !11
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %26

25:                                               ; preds = %22, %3
  store i32 2, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %169

26:                                               ; preds = %22
  %27 = load i32, ptr %9, align 4, !tbaa !11
  %28 = icmp eq i32 %27, 1
  br i1 %28, label %29, label %48

29:                                               ; preds = %26
  %30 = load i32, ptr %10, align 4, !tbaa !11
  %31 = icmp eq i32 %30, 1
  br i1 %31, label %32, label %48

32:                                               ; preds = %29
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = icmp eq ptr %33, null
  br i1 %34, label %35, label %40

35:                                               ; preds = %32
  %36 = load i16, ptr %7, align 2, !tbaa !9
  %37 = zext i16 %36 to i32
  %38 = icmp ugt i32 %37, 0
  br i1 %38, label %39, label %40

39:                                               ; preds = %35
  store i32 1, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %169

40:                                               ; preds = %35, %32
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %41, i32 0, i32 6
  %43 = getelementptr inbounds [6 x i32], ptr %42, i64 0, i64 0
  store volatile i32 2, ptr %43, align 8, !tbaa !11
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 7
  %46 = getelementptr inbounds [4 x i32], ptr %45, i64 0, i64 0
  store volatile i32 2, ptr %46, align 8, !tbaa !11
  br label %47

47:                                               ; preds = %40
  br label %49

48:                                               ; preds = %29, %26
  store i32 1, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %169

49:                                               ; preds = %47
  br label %50

50:                                               ; preds = %49
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %51, i32 0, i32 0
  %53 = load ptr, ptr %52, align 8, !tbaa !13
  call void @TIM_CCxChannelCmd(ptr noundef %53, i32 noundef 0, i32 noundef 1)
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 3
  %56 = getelementptr inbounds [7 x ptr], ptr %55, i64 0, i64 1
  %57 = load ptr, ptr %56, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %57, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %58, align 8, !tbaa !16
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %59, i32 0, i32 3
  %61 = getelementptr inbounds [7 x ptr], ptr %60, i64 0, i64 1
  %62 = load ptr, ptr %61, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %62, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %63, align 8, !tbaa !19
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %64, i32 0, i32 3
  %66 = getelementptr inbounds [7 x ptr], ptr %65, i64 0, i64 1
  %67 = load ptr, ptr %66, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %67, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %68, align 8, !tbaa !20
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %69, i32 0, i32 3
  %71 = getelementptr inbounds [7 x ptr], ptr %70, i64 0, i64 1
  %72 = load ptr, ptr %71, align 8, !tbaa !5
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %73, i32 0, i32 0
  %75 = load ptr, ptr %74, align 8, !tbaa !13
  %76 = getelementptr inbounds %struct.TIM_TypeDef, ptr %75, i32 0, i32 13
  %77 = ptrtoint ptr %76 to i32
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = ptrtoint ptr %78 to i32
  %80 = load i16, ptr %7, align 2, !tbaa !9
  %81 = zext i16 %80 to i32
  %82 = call i32 @HAL_DMA_Start_IT(ptr noundef %72, i32 noundef %77, i32 noundef %79, i32 noundef %81)
  %83 = icmp ne i32 %82, 0
  br i1 %83, label %84, label %85

84:                                               ; preds = %50
  store i32 1, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %169

85:                                               ; preds = %50
  %86 = load ptr, ptr %5, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %86, i32 0, i32 0
  %88 = load ptr, ptr %87, align 8, !tbaa !13
  %89 = getelementptr inbounds %struct.TIM_TypeDef, ptr %88, i32 0, i32 3
  %90 = load volatile i32, ptr %89, align 4, !tbaa !21
  %91 = zext i32 %90 to i64
  %92 = or i64 %91, 512
  %93 = trunc i64 %92 to i32
  store volatile i32 %93, ptr %89, align 4, !tbaa !21
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !13
  %97 = icmp eq ptr %96, inttoptr (i64 1073807360 to ptr)
  br i1 %97, label %133, label %98

98:                                               ; preds = %85
  %99 = load ptr, ptr %5, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %99, i32 0, i32 0
  %101 = load ptr, ptr %100, align 8, !tbaa !13
  %102 = icmp eq ptr %101, inttoptr (i64 1073741824 to ptr)
  br i1 %102, label %133, label %103

103:                                              ; preds = %98
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %104, i32 0, i32 0
  %106 = load ptr, ptr %105, align 8, !tbaa !13
  %107 = icmp eq ptr %106, inttoptr (i64 1073742848 to ptr)
  br i1 %107, label %133, label %108

108:                                              ; preds = %103
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %109, i32 0, i32 0
  %111 = load ptr, ptr %110, align 8, !tbaa !13
  %112 = icmp eq ptr %111, inttoptr (i64 1073743872 to ptr)
  br i1 %112, label %133, label %113

113:                                              ; preds = %108
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %114, i32 0, i32 0
  %116 = load ptr, ptr %115, align 8, !tbaa !13
  %117 = icmp eq ptr %116, inttoptr (i64 1073744896 to ptr)
  br i1 %117, label %133, label %118

118:                                              ; preds = %113
  %119 = load ptr, ptr %5, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !13
  %122 = icmp eq ptr %121, inttoptr (i64 1073808384 to ptr)
  br i1 %122, label %133, label %123

123:                                              ; preds = %118
  %124 = load ptr, ptr %5, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !13
  %127 = icmp eq ptr %126, inttoptr (i64 1073747968 to ptr)
  br i1 %127, label %133, label %128

128:                                              ; preds = %123
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %129, i32 0, i32 0
  %131 = load ptr, ptr %130, align 8, !tbaa !13
  %132 = icmp eq ptr %131, inttoptr (i64 1073823744 to ptr)
  br i1 %132, label %133, label %159

133:                                              ; preds = %128, %123, %118, %113, %108, %103, %98, %85
  %134 = load ptr, ptr %5, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %134, i32 0, i32 0
  %136 = load ptr, ptr %135, align 8, !tbaa !13
  %137 = getelementptr inbounds %struct.TIM_TypeDef, ptr %136, i32 0, i32 2
  %138 = load volatile i32, ptr %137, align 4, !tbaa !23
  %139 = zext i32 %138 to i64
  %140 = and i64 %139, 65543
  %141 = trunc i64 %140 to i32
  store i32 %141, ptr %8, align 4, !tbaa !11
  %142 = load i32, ptr %8, align 4, !tbaa !11
  %143 = zext i32 %142 to i64
  %144 = icmp eq i64 %143, 6
  br i1 %144, label %158, label %145

145:                                              ; preds = %133
  %146 = load i32, ptr %8, align 4, !tbaa !11
  %147 = zext i32 %146 to i64
  %148 = icmp eq i64 %147, 65536
  br i1 %148, label %158, label %149

149:                                              ; preds = %145
  %150 = load ptr, ptr %5, align 8, !tbaa !5
  %151 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %150, i32 0, i32 0
  %152 = load ptr, ptr %151, align 8, !tbaa !13
  %153 = getelementptr inbounds %struct.TIM_TypeDef, ptr %152, i32 0, i32 0
  %154 = load volatile i32, ptr %153, align 4, !tbaa !24
  %155 = zext i32 %154 to i64
  %156 = or i64 %155, 1
  %157 = trunc i64 %156 to i32
  store volatile i32 %157, ptr %153, align 4, !tbaa !24
  br label %158

158:                                              ; preds = %149, %145, %133
  br label %168

159:                                              ; preds = %128
  %160 = load ptr, ptr %5, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %160, i32 0, i32 0
  %162 = load ptr, ptr %161, align 8, !tbaa !13
  %163 = getelementptr inbounds %struct.TIM_TypeDef, ptr %162, i32 0, i32 0
  %164 = load volatile i32, ptr %163, align 4, !tbaa !24
  %165 = zext i32 %164 to i64
  %166 = or i64 %165, 1
  %167 = trunc i64 %166 to i32
  store volatile i32 %167, ptr %163, align 4, !tbaa !24
  br label %168

168:                                              ; preds = %159, %158
  store i32 0, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %169

169:                                              ; preds = %168, %84, %48, %39, %25
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %170 = load i32, ptr %4, align 4
  ret i32 %170
}

declare void @TIM_DMACaptureCplt(ptr noundef) #1

declare void @TIM_DMACaptureHalfCplt(ptr noundef) #1

declare void @TIM_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 0}
!14 = !{!"", !6, i64 0, !15, i64 8, !12, i64 32, !7, i64 40, !12, i64 96, !12, i64 100, !7, i64 104, !7, i64 128, !12, i64 144}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20}
!16 = !{!17, !6, i64 72}
!17 = !{!"__DMA_HandleTypeDef", !6, i64 0, !18, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!18 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!19 = !{!17, !6, i64 80}
!20 = !{!17, !6, i64 104}
!21 = !{!22, !12, i64 12}
!22 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!23 = !{!22, !12, i64 8}
!24 = !{!22, !12, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIMEx_HallSensor_Start_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #1 {
  %4 = getelementptr inbounds i8, ptr %0, i64 104
  %5 = load volatile i32, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 128
  %7 = load volatile i32, ptr %6, align 8, !tbaa !5
  %8 = icmp eq i32 %5, 2
  %9 = icmp eq i32 %7, 2
  %or.cond = select i1 %8, i1 true, i1 %9
  br i1 %or.cond, label %45, label %10

10:                                               ; preds = %3
  %11 = icmp eq i32 %5, 1
  %12 = icmp eq i32 %7, 1
  %or.cond3 = select i1 %11, i1 %12, i1 false
  br i1 %or.cond3, label %13, label %45

13:                                               ; preds = %10
  %14 = icmp eq ptr %1, null
  %15 = icmp ne i16 %2, 0
  %or.cond6 = and i1 %14, %15
  br i1 %or.cond6, label %45, label %16

16:                                               ; preds = %13
  %17 = zext i16 %2 to i32
  store volatile i32 2, ptr %4, align 8, !tbaa !5
  store volatile i32 2, ptr %6, align 8, !tbaa !5
  %18 = load ptr, ptr %0, align 8, !tbaa !9
  tail call void @TIM_CCxChannelCmd(ptr noundef %18, i32 noundef 0, i32 noundef 1) #2
  %19 = getelementptr inbounds i8, ptr %0, i64 48
  %20 = load ptr, ptr %19, align 8, !tbaa !13
  %21 = getelementptr inbounds i8, ptr %20, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %21, align 8, !tbaa !14
  %22 = load ptr, ptr %19, align 8, !tbaa !13
  %23 = getelementptr inbounds i8, ptr %22, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %23, align 8, !tbaa !17
  %24 = load ptr, ptr %19, align 8, !tbaa !13
  %25 = getelementptr inbounds i8, ptr %24, i64 104
  store ptr @TIM_DMAError, ptr %25, align 8, !tbaa !18
  %26 = load ptr, ptr %19, align 8, !tbaa !13
  %27 = load ptr, ptr %0, align 8, !tbaa !9
  %28 = getelementptr inbounds i8, ptr %27, i64 52
  %29 = ptrtoint ptr %28 to i64
  %30 = trunc i64 %29 to i32
  %31 = ptrtoint ptr %1 to i64
  %32 = trunc i64 %31 to i32
  %33 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %26, i32 noundef %30, i32 noundef %32, i32 noundef %17) #2
  %.not = icmp eq i32 %33, 0
  br i1 %.not, label %34, label %45

34:                                               ; preds = %16
  %35 = load ptr, ptr %0, align 8, !tbaa !9
  %36 = getelementptr inbounds i8, ptr %35, i64 12
  %37 = load volatile i32, ptr %36, align 4, !tbaa !19
  %38 = or i32 %37, 512
  store volatile i32 %38, ptr %36, align 4, !tbaa !19
  %magicptr = ptrtoint ptr %35 to i64
  switch i64 %magicptr, label %.sink.split [
    i64 1073807360, label %39
    i64 1073741824, label %39
    i64 1073742848, label %39
    i64 1073743872, label %39
    i64 1073744896, label %39
    i64 1073808384, label %39
    i64 1073747968, label %39
    i64 1073823744, label %39
  ]

39:                                               ; preds = %34, %34, %34, %34, %34, %34, %34, %34
  %40 = getelementptr inbounds i8, ptr %35, i64 8
  %41 = load volatile i32, ptr %40, align 4, !tbaa !21
  %42 = and i32 %41, 65543
  switch i32 %42, label %.sink.split [
    i32 65536, label %45
    i32 6, label %45
  ]

.sink.split:                                      ; preds = %34, %39
  %43 = load volatile i32, ptr %35, align 4, !tbaa !22
  %44 = or i32 %43, 1
  store volatile i32 %44, ptr %35, align 4, !tbaa !22
  br label %45

45:                                               ; preds = %.sink.split, %39, %39, %16, %10, %13, %3
  %.0 = phi i32 [ 2, %3 ], [ 1, %13 ], [ 1, %10 ], [ 1, %16 ], [ 0, %39 ], [ 0, %39 ], [ 0, %.sink.split ]
  ret i32 %.0
}

declare void @TIM_DMACaptureCplt(ptr noundef) #0

declare void @TIM_DMACaptureHalfCplt(ptr noundef) #0

declare void @TIM_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !12, i64 8, !6, i64 32, !7, i64 40, !6, i64 96, !6, i64 100, !7, i64 104, !7, i64 128, !6, i64 144}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20}
!13 = !{!11, !11, i64 0}
!14 = !{!15, !11, i64 72}
!15 = !{!"__DMA_HandleTypeDef", !11, i64 0, !16, i64 8, !6, i64 56, !6, i64 60, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !6, i64 120, !6, i64 124, !6, i64 128, !11, i64 136, !11, i64 144, !6, i64 152, !11, i64 160, !11, i64 168, !6, i64 176}
!16 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44}
!17 = !{!15, !11, i64 80}
!18 = !{!15, !11, i64 104}
!19 = !{!20, !6, i64 12}
!20 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92, !6, i64 96, !6, i64 100, !6, i64 104}
!21 = !{!20, !6, i64 8}
!22 = !{!20, !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass