; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_ll_sdmmc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SDMMC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, [8 x i32], i32, [222 x i32], i32 }

@SystemCoreClock = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @SDMMC_GetCmdResp3(ptr noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %7 = load i32, ptr @SystemCoreClock, align 4, !tbaa !9
  %8 = udiv i32 %7, 8
  %9 = udiv i32 %8, 1000
  %10 = mul i32 5000, %9
  store i32 %10, ptr %5, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %30, %1
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = add i32 %12, -1
  store i32 %13, ptr %5, align 4, !tbaa !9
  %14 = icmp eq i32 %12, 0
  br i1 %14, label %15, label %16

15:                                               ; preds = %11
  store i32 -2147483648, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %46

16:                                               ; preds = %11
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SDMMC_TypeDef, ptr %17, i32 0, i32 13
  %19 = load volatile i32, ptr %18, align 4, !tbaa !11
  store i32 %19, ptr %4, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %16
  %21 = load i32, ptr %4, align 4, !tbaa !9
  %22 = zext i32 %21 to i64
  %23 = and i64 %22, 69
  %24 = icmp eq i64 %23, 0
  br i1 %24, label %30, label %25

25:                                               ; preds = %20
  %26 = load i32, ptr %4, align 4, !tbaa !9
  %27 = zext i32 %26 to i64
  %28 = and i64 %27, 8192
  %29 = icmp ne i64 %28, 0
  br label %30

30:                                               ; preds = %25, %20
  %31 = phi i1 [ true, %20 ], [ %29, %25 ]
  br i1 %31, label %11, label %32, !llvm.loop !13

32:                                               ; preds = %30
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SDMMC_TypeDef, ptr %33, i32 0, i32 13
  %35 = load volatile i32, ptr %34, align 4, !tbaa !11
  %36 = zext i32 %35 to i64
  %37 = and i64 %36, 4
  %38 = icmp ne i64 %37, 0
  br i1 %38, label %39, label %42

39:                                               ; preds = %32
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.SDMMC_TypeDef, ptr %40, i32 0, i32 14
  store volatile i32 4, ptr %41, align 4, !tbaa !15
  store i32 4, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %46

42:                                               ; preds = %32
  %43 = load ptr, ptr %3, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.SDMMC_TypeDef, ptr %43, i32 0, i32 14
  store volatile i32 2097349, ptr %44, align 4, !tbaa !15
  br label %45

45:                                               ; preds = %42
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %46

46:                                               ; preds = %45, %39, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  %47 = load i32, ptr %2, align 4
  ret i32 %47
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 52}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !7, i64 68, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !7, i64 96, !10, i64 128, !7, i64 132, !10, i64 1020}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = !{!12, !10, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external local_unnamed_addr global i32, align 4

; Function Attrs: nofree norecurse nounwind memory(read, argmem: readwrite, inaccessiblemem: readwrite) uwtable
define dso_local range(i32 0, -2147483647) i32 @SDMMC_GetCmdResp3(ptr noundef %0) local_unnamed_addr #0 {
  %2 = load i32, ptr @SystemCoreClock, align 4, !tbaa !5
  %3 = udiv i32 %2, 8000
  %4 = mul nuw i32 %3, 5000
  %5 = getelementptr inbounds i8, ptr %0, i64 52
  br label %6

6:                                                ; preds = %8, %1
  %.0 = phi i32 [ %4, %1 ], [ %9, %8 ]
  %7 = icmp eq i32 %.0, 0
  br i1 %7, label %.loopexit, label %8

8:                                                ; preds = %6
  %9 = add i32 %.0, -1
  %10 = load volatile i32, ptr %5, align 4, !tbaa !9
  %11 = zext i32 %10 to i64
  %12 = and i64 %11, 69
  %13 = icmp eq i64 %12, 0
  %14 = and i64 %11, 8192
  %15 = icmp ne i64 %14, 0
  %16 = or i1 %13, %15
  br i1 %16, label %6, label %.loopexit.sink.split, !llvm.loop !11

.loopexit.sink.split:                             ; preds = %8
  %17 = load volatile i32, ptr %5, align 4, !tbaa !9
  %18 = and i32 %17, 4
  %.not = icmp eq i32 %18, 0
  %19 = getelementptr inbounds i8, ptr %0, i64 56
  %. = select i1 %.not, i32 2097349, i32 4
  store volatile i32 %., ptr %19, align 4, !tbaa !13
  br label %.loopexit

.loopexit:                                        ; preds = %6, %.loopexit.sink.split
  %.07 = phi i32 [ %18, %.loopexit.sink.split ], [ -2147483648, %6 ]
  ret i32 %.07
}

attributes #0 = { nofree norecurse nounwind memory(read, argmem: readwrite, inaccessiblemem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 52}
!10 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !7, i64 68, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92, !7, i64 96, !6, i64 128, !7, i64 132, !6, i64 1020}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!10, !6, i64 56}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass