; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_MultiModeTypeDef = type { i32, i32, i32 }
%struct.ADC_Common_TypeDef = type { i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeConfigChannel(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca %struct.ADC_HandleTypeDef, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 120, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %11, i32 0, i32 0
  %13 = load i32, ptr %12, align 4, !tbaa !11
  %14 = zext i32 %13 to i64
  %15 = icmp ne i64 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %2
  br label %17

17:                                               ; preds = %16, %2
  br label %18

18:                                               ; preds = %17
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %19, i32 0, i32 3
  %21 = load i32, ptr %20, align 8, !tbaa !13
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 2, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %201

24:                                               ; preds = %18
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %25, i32 0, i32 3
  store i32 1, ptr %26, align 8, !tbaa !13
  br label %27

27:                                               ; preds = %24
  br label %28

28:                                               ; preds = %27
  br label %29

29:                                               ; preds = %28
  %30 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 4
  store volatile i32 0, ptr %30, align 4, !tbaa !18
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 5
  store volatile i32 0, ptr %31, align 8, !tbaa !19
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %32, i32 0, i32 0
  %34 = load ptr, ptr %33, align 8, !tbaa !20
  %35 = icmp eq ptr %34, inttoptr (i64 1073881088 to ptr)
  br i1 %35, label %36, label %38

36:                                               ; preds = %29
  %37 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  store ptr inttoptr (i64 1073881344 to ptr), ptr %37, align 8, !tbaa !20
  br label %40

38:                                               ; preds = %29
  %39 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  store ptr null, ptr %39, align 8, !tbaa !20
  br label %40

40:                                               ; preds = %38, %36
  %41 = phi ptr [ inttoptr (i64 1073881344 to ptr), %36 ], [ null, %38 ]
  %42 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %43 = load ptr, ptr %42, align 8, !tbaa !20
  %44 = icmp eq ptr %43, null
  br i1 %44, label %45, label %57

45:                                               ; preds = %40
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %46, i32 0, i32 4
  %48 = load volatile i32, ptr %47, align 4, !tbaa !18
  %49 = zext i32 %48 to i64
  %50 = or i64 %49, 32
  %51 = trunc i64 %50 to i32
  store volatile i32 %51, ptr %47, align 4, !tbaa !18
  br label %52

52:                                               ; preds = %45
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %53, i32 0, i32 3
  store i32 0, ptr %54, align 8, !tbaa !13
  br label %55

55:                                               ; preds = %52
  br label %56

56:                                               ; preds = %55
  store i32 1, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %201

57:                                               ; preds = %40
  %58 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !20
  %60 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %59)
  store i32 %60, ptr %9, align 4, !tbaa !9
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !20
  %64 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %63)
  %65 = zext i32 %64 to i64
  %66 = icmp eq i64 %65, 0
  br i1 %66, label %67, label %187

67:                                               ; preds = %57
  %68 = load i32, ptr %9, align 4, !tbaa !9
  %69 = zext i32 %68 to i64
  %70 = icmp eq i64 %69, 0
  br i1 %70, label %71, label %187

71:                                               ; preds = %67
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !20
  %75 = icmp eq ptr %74, inttoptr (i64 1073881088 to ptr)
  br i1 %75, label %81, label %76

76:                                               ; preds = %71
  %77 = load ptr, ptr %4, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !20
  %80 = icmp eq ptr %79, inttoptr (i64 1073881344 to ptr)
  br label %81

81:                                               ; preds = %76, %71
  %82 = phi i1 [ true, %71 ], [ %80, %76 ]
  %83 = zext i1 %82 to i64
  %84 = select i1 %82, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  store ptr %84, ptr %7, align 8, !tbaa !5
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %85, i32 0, i32 0
  %87 = load i32, ptr %86, align 4, !tbaa !11
  %88 = zext i32 %87 to i64
  %89 = icmp ne i64 %88, 0
  br i1 %89, label %90, label %147

90:                                               ; preds = %81
  %91 = load ptr, ptr %7, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %91, i32 0, i32 2
  %93 = load volatile i32, ptr %92, align 4, !tbaa !21
  %94 = zext i32 %93 to i64
  %95 = and i64 %94, -49153
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %96, i32 0, i32 1
  %98 = load i32, ptr %97, align 4, !tbaa !23
  %99 = zext i32 %98 to i64
  %100 = or i64 %95, %99
  %101 = trunc i64 %100 to i32
  %102 = load ptr, ptr %7, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %102, i32 0, i32 2
  store volatile i32 %101, ptr %103, align 4, !tbaa !21
  %104 = load ptr, ptr %4, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %104, i32 0, i32 0
  %106 = load ptr, ptr %105, align 8, !tbaa !20
  %107 = icmp eq ptr %106, inttoptr (i64 1073881088 to ptr)
  br i1 %107, label %113, label %108

108:                                              ; preds = %90
  %109 = load ptr, ptr %4, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %109, i32 0, i32 0
  %111 = load ptr, ptr %110, align 8, !tbaa !20
  %112 = icmp eq ptr %111, inttoptr (i64 1073881344 to ptr)
  br label %113

113:                                              ; preds = %108, %90
  %114 = phi i1 [ true, %90 ], [ %112, %108 ]
  %115 = zext i1 %114 to i64
  %116 = select i1 %114, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %117 = icmp eq ptr %116, inttoptr (i64 1073881856 to ptr)
  br i1 %117, label %118, label %122

118:                                              ; preds = %113
  %119 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %120 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %121 = or i32 %119, %120
  br label %124

122:                                              ; preds = %113
  %123 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %124

124:                                              ; preds = %122, %118
  %125 = phi i32 [ %121, %118 ], [ %123, %122 ]
  %126 = zext i32 %125 to i64
  %127 = icmp eq i64 %126, 0
  br i1 %127, label %128, label %146

128:                                              ; preds = %124
  %129 = load ptr, ptr %7, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %129, i32 0, i32 2
  %131 = load volatile i32, ptr %130, align 4, !tbaa !21
  %132 = zext i32 %131 to i64
  %133 = and i64 %132, -3872
  %134 = load ptr, ptr %5, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %134, i32 0, i32 0
  %136 = load i32, ptr %135, align 4, !tbaa !11
  %137 = load ptr, ptr %5, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %137, i32 0, i32 2
  %139 = load i32, ptr %138, align 4, !tbaa !24
  %140 = or i32 %136, %139
  %141 = zext i32 %140 to i64
  %142 = or i64 %133, %141
  %143 = trunc i64 %142 to i32
  %144 = load ptr, ptr %7, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %144, i32 0, i32 2
  store volatile i32 %143, ptr %145, align 4, !tbaa !21
  br label %146

146:                                              ; preds = %128, %124
  br label %186

147:                                              ; preds = %81
  %148 = load ptr, ptr %7, align 8, !tbaa !5
  %149 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %148, i32 0, i32 2
  %150 = load volatile i32, ptr %149, align 4, !tbaa !21
  %151 = zext i32 %150 to i64
  %152 = and i64 %151, -49153
  %153 = trunc i64 %152 to i32
  store volatile i32 %153, ptr %149, align 4, !tbaa !21
  %154 = load ptr, ptr %4, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %154, i32 0, i32 0
  %156 = load ptr, ptr %155, align 8, !tbaa !20
  %157 = icmp eq ptr %156, inttoptr (i64 1073881088 to ptr)
  br i1 %157, label %163, label %158

158:                                              ; preds = %147
  %159 = load ptr, ptr %4, align 8, !tbaa !5
  %160 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %159, i32 0, i32 0
  %161 = load ptr, ptr %160, align 8, !tbaa !20
  %162 = icmp eq ptr %161, inttoptr (i64 1073881344 to ptr)
  br label %163

163:                                              ; preds = %158, %147
  %164 = phi i1 [ true, %147 ], [ %162, %158 ]
  %165 = zext i1 %164 to i64
  %166 = select i1 %164, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %167 = icmp eq ptr %166, inttoptr (i64 1073881856 to ptr)
  br i1 %167, label %168, label %172

168:                                              ; preds = %163
  %169 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %170 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %171 = or i32 %169, %170
  br label %174

172:                                              ; preds = %163
  %173 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %174

174:                                              ; preds = %172, %168
  %175 = phi i32 [ %171, %168 ], [ %173, %172 ]
  %176 = zext i32 %175 to i64
  %177 = icmp eq i64 %176, 0
  br i1 %177, label %178, label %185

178:                                              ; preds = %174
  %179 = load ptr, ptr %7, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %179, i32 0, i32 2
  %181 = load volatile i32, ptr %180, align 4, !tbaa !21
  %182 = zext i32 %181 to i64
  %183 = and i64 %182, -3872
  %184 = trunc i64 %183 to i32
  store volatile i32 %184, ptr %180, align 4, !tbaa !21
  br label %185

185:                                              ; preds = %178, %174
  br label %186

186:                                              ; preds = %185, %146
  br label %194

187:                                              ; preds = %67, %57
  %188 = load ptr, ptr %4, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %188, i32 0, i32 4
  %190 = load volatile i32, ptr %189, align 4, !tbaa !18
  %191 = zext i32 %190 to i64
  %192 = or i64 %191, 32
  %193 = trunc i64 %192 to i32
  store volatile i32 %193, ptr %189, align 4, !tbaa !18
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %194

194:                                              ; preds = %187, %186
  br label %195

195:                                              ; preds = %194
  %196 = load ptr, ptr %4, align 8, !tbaa !5
  %197 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %196, i32 0, i32 3
  store i32 0, ptr %197, align 8, !tbaa !13
  br label %198

198:                                              ; preds = %195
  br label %199

199:                                              ; preds = %198
  %200 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %200, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %201

201:                                              ; preds = %199, %56, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 120, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %202 = load i32, ptr %3, align 4
  ret i32 %202
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!13 = !{!14, !10, i64 96}
!14 = !{!"", !6, i64 0, !15, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !17, i64 108}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !16, i64 60}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!17 = !{!"", !10, i64 0, !10, i64 4}
!18 = !{!14, !10, i64 100}
!19 = !{!14, !10, i64 104}
!20 = !{!14, !6, i64 0}
!21 = !{!22, !10, i64 8}
!22 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16}
!23 = !{!12, !10, i64 4}
!24 = !{!12, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_ADCEx_MultiModeConfigChannel(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #2 {
  %.sroa.64 = alloca i32, align 4
  %.sroa.7 = alloca i32, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %.sroa.64)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %.sroa.7)
  %3 = getelementptr inbounds i8, ptr %0, i64 96
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %64, label %6

6:                                                ; preds = %2
  store i32 1, ptr %3, align 8, !tbaa !5
  store volatile i32 0, ptr %.sroa.64, align 4, !tbaa !14
  store volatile i32 0, ptr %.sroa.7, align 8, !tbaa !15
  %7 = load ptr, ptr %0, align 8, !tbaa !16
  %.not = icmp eq ptr %7, inttoptr (i64 1073881088 to ptr)
  br i1 %.not, label %12, label %8

8:                                                ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 100
  %10 = load volatile i32, ptr %9, align 4, !tbaa !14
  %11 = or i32 %10, 32
  store volatile i32 %11, ptr %9, align 4, !tbaa !14
  br label %.sink.split

12:                                               ; preds = %6
  %13 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %14 = load ptr, ptr %0, align 8, !tbaa !16
  %15 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %14)
  %16 = icmp eq i32 %15, 0
  %17 = icmp eq i32 %13, 0
  %or.cond = select i1 %16, i1 %17, i1 false
  br i1 %or.cond, label %18, label %60

18:                                               ; preds = %12
  %19 = load ptr, ptr %0, align 8, !tbaa !16
  %20 = icmp eq ptr %19, inttoptr (i64 1073881088 to ptr)
  %21 = icmp eq ptr %19, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %20, %21
  %22 = load i32, ptr %1, align 4, !tbaa !17
  %.not35 = icmp eq i32 %22, 0
  %23 = select i1 %spec.select, ptr inttoptr (i64 1073881864 to ptr), ptr inttoptr (i64 1476551432 to ptr)
  %24 = load volatile i32, ptr %23, align 8, !tbaa !19
  %25 = and i32 %24, -49153
  br i1 %.not35, label %47, label %26

26:                                               ; preds = %18
  %27 = getelementptr inbounds i8, ptr %1, i64 4
  %28 = load i32, ptr %27, align 4, !tbaa !21
  %29 = or i32 %25, %28
  store volatile i32 %29, ptr %23, align 8, !tbaa !19
  %magicptr = ptrtoint ptr %19 to i64
  switch i64 %magicptr, label %34 [
    i64 1073881344, label %30
    i64 1073881088, label %30
  ]

30:                                               ; preds = %26, %26
  %31 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %32 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %33 = or i32 %32, %31
  br label %36

34:                                               ; preds = %26
  %35 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %36

36:                                               ; preds = %34, %30
  %37 = phi i32 [ %33, %30 ], [ %35, %34 ]
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %39, label %.sink.split

39:                                               ; preds = %36
  %40 = load volatile i32, ptr %23, align 8, !tbaa !19
  %41 = and i32 %40, -3872
  %42 = load i32, ptr %1, align 4, !tbaa !17
  %43 = getelementptr inbounds i8, ptr %1, i64 8
  %44 = load i32, ptr %43, align 4, !tbaa !22
  %45 = or i32 %41, %42
  %46 = or i32 %45, %44
  store volatile i32 %46, ptr %23, align 8, !tbaa !19
  br label %.sink.split

47:                                               ; preds = %18
  store volatile i32 %25, ptr %23, align 8, !tbaa !19
  %magicptr38 = ptrtoint ptr %19 to i64
  switch i64 %magicptr38, label %52 [
    i64 1073881344, label %48
    i64 1073881088, label %48
  ]

48:                                               ; preds = %47, %47
  %49 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %50 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %51 = or i32 %50, %49
  br label %54

52:                                               ; preds = %47
  %53 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %54

54:                                               ; preds = %52, %48
  %55 = phi i32 [ %51, %48 ], [ %53, %52 ]
  %56 = icmp eq i32 %55, 0
  br i1 %56, label %57, label %.sink.split

57:                                               ; preds = %54
  %58 = load volatile i32, ptr %23, align 8, !tbaa !19
  %59 = and i32 %58, -3872
  store volatile i32 %59, ptr %23, align 8, !tbaa !19
  br label %.sink.split

60:                                               ; preds = %12
  %61 = getelementptr inbounds i8, ptr %0, i64 100
  %62 = load volatile i32, ptr %61, align 4, !tbaa !14
  %63 = or i32 %62, 32
  store volatile i32 %63, ptr %61, align 4, !tbaa !14
  br label %.sink.split

.sink.split:                                      ; preds = %39, %36, %57, %54, %60, %8
  %.0.ph = phi i32 [ 1, %8 ], [ 0, %39 ], [ 0, %36 ], [ 0, %57 ], [ 0, %54 ], [ 1, %60 ]
  store i32 0, ptr %3, align 8, !tbaa !5
  br label %64

64:                                               ; preds = %.sink.split, %2
  %.0 = phi i32 [ 2, %2 ], [ %.0.ph, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %.sroa.64)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %.sroa.7)
  ret i32 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 100}
!15 = !{!6, !11, i64 104}
!16 = !{!6, !7, i64 0}
!17 = !{!18, !11, i64 0}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!19 = !{!20, !11, i64 8}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16}
!21 = !{!18, !11, i64 4}
!22 = !{!18, !11, i64 8}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass