; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %11, i32 0, i32 13
  %13 = load i32, ptr %12, align 8, !tbaa !13
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %17, i32 0, i32 13
  store i32 1, ptr %18, align 8, !tbaa !13
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %22, i32 0, i32 14
  %24 = load volatile i32, ptr %23, align 4, !tbaa !16
  %25 = icmp ne i32 %24, 1
  br i1 %25, label %26, label %33

26:                                               ; preds = %21
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %27

27:                                               ; preds = %26
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %28, i32 0, i32 13
  store i32 0, ptr %29, align 8, !tbaa !13
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  %32 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %32, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

33:                                               ; preds = %21
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = icmp eq ptr %34, null
  br i1 %35, label %40, label %36

36:                                               ; preds = %33
  %37 = load i16, ptr %7, align 2, !tbaa !9
  %38 = zext i16 %37 to i64
  %39 = icmp eq i64 %38, 0
  br i1 %39, label %40, label %47

40:                                               ; preds = %36, %33
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %41

41:                                               ; preds = %40
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %42, i32 0, i32 13
  store i32 0, ptr %43, align 8, !tbaa !13
  br label %44

44:                                               ; preds = %41
  br label %45

45:                                               ; preds = %44
  %46 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %46, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

47:                                               ; preds = %36
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %48, i32 0, i32 14
  store volatile i32 3, ptr %49, align 4, !tbaa !16
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %50, i32 0, i32 15
  store volatile i32 0, ptr %51, align 8, !tbaa !17
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %53, i32 0, i32 2
  store ptr %52, ptr %54, align 8, !tbaa !18
  %55 = load i16, ptr %7, align 2, !tbaa !9
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %56, i32 0, i32 3
  store i16 %55, ptr %57, align 8, !tbaa !19
  %58 = load i16, ptr %7, align 2, !tbaa !9
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %59, i32 0, i32 4
  store volatile i16 %58, ptr %60, align 2, !tbaa !20
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %61, i32 0, i32 5
  store ptr null, ptr %62, align 8, !tbaa !21
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %63, i32 0, i32 10
  store ptr null, ptr %64, align 8, !tbaa !22
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %65, i32 0, i32 9
  store ptr null, ptr %66, align 8, !tbaa !23
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %67, i32 0, i32 6
  store i16 0, ptr %68, align 8, !tbaa !24
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %69, i32 0, i32 7
  store volatile i16 0, ptr %70, align 2, !tbaa !25
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %71, i32 0, i32 1
  %73 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %72, i32 0, i32 1
  %74 = load i32, ptr %73, align 4, !tbaa !26
  %75 = zext i32 %74 to i64
  %76 = icmp eq i64 %75, 393216
  br i1 %76, label %77, label %86

77:                                               ; preds = %47
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !27
  %81 = getelementptr inbounds %struct.SPI_TypeDef, ptr %80, i32 0, i32 0
  %82 = load volatile i32, ptr %81, align 4, !tbaa !28
  %83 = zext i32 %82 to i64
  %84 = or i64 %83, 2048
  %85 = trunc i64 %84 to i32
  store volatile i32 %85, ptr %81, align 4, !tbaa !28
  br label %86

86:                                               ; preds = %77, %47
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %87, i32 0, i32 1
  %89 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %88, i32 0, i32 2
  %90 = load i32, ptr %89, align 8, !tbaa !30
  %91 = zext i32 %90 to i64
  %92 = icmp ugt i64 %91, 15
  br i1 %92, label %93, label %101

93:                                               ; preds = %86
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %94, i32 0, i32 11
  %96 = load ptr, ptr %95, align 8, !tbaa !31
  %97 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %96, i32 0, i32 1
  %98 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %97, i32 0, i32 5
  %99 = load i32, ptr %98, align 4, !tbaa !32
  %100 = icmp ne i32 %99, 16384
  br i1 %100, label %124, label %101

101:                                              ; preds = %93, %86
  %102 = load ptr, ptr %5, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %102, i32 0, i32 1
  %104 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %103, i32 0, i32 2
  %105 = load i32, ptr %104, align 8, !tbaa !30
  %106 = zext i32 %105 to i64
  %107 = icmp ugt i64 %106, 7
  br i1 %107, label %108, label %131

108:                                              ; preds = %101
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %109, i32 0, i32 11
  %111 = load ptr, ptr %110, align 8, !tbaa !31
  %112 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %111, i32 0, i32 1
  %113 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %112, i32 0, i32 5
  %114 = load i32, ptr %113, align 4, !tbaa !32
  %115 = icmp ne i32 %114, 8192
  br i1 %115, label %116, label %131

116:                                              ; preds = %108
  %117 = load ptr, ptr %5, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %117, i32 0, i32 11
  %119 = load ptr, ptr %118, align 8, !tbaa !31
  %120 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %119, i32 0, i32 1
  %121 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %120, i32 0, i32 5
  %122 = load i32, ptr %121, align 4, !tbaa !32
  %123 = icmp ne i32 %122, 16384
  br i1 %123, label %124, label %131

124:                                              ; preds = %116, %93
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %125

125:                                              ; preds = %124
  %126 = load ptr, ptr %5, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %126, i32 0, i32 13
  store i32 0, ptr %127, align 8, !tbaa !13
  br label %128

128:                                              ; preds = %125
  br label %129

129:                                              ; preds = %128
  %130 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %130, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

131:                                              ; preds = %116, %108, %101
  %132 = load ptr, ptr %5, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %132, i32 0, i32 1
  %134 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %133, i32 0, i32 2
  %135 = load i32, ptr %134, align 8, !tbaa !30
  %136 = zext i32 %135 to i64
  %137 = icmp ule i64 %136, 7
  br i1 %137, label %138, label %175

138:                                              ; preds = %131
  %139 = load ptr, ptr %5, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %139, i32 0, i32 11
  %141 = load ptr, ptr %140, align 8, !tbaa !31
  %142 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %141, i32 0, i32 1
  %143 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %142, i32 0, i32 5
  %144 = load i32, ptr %143, align 4, !tbaa !32
  %145 = icmp eq i32 %144, 8192
  br i1 %145, label %146, label %156

146:                                              ; preds = %138
  %147 = load ptr, ptr %5, align 8, !tbaa !5
  %148 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %147, i32 0, i32 4
  %149 = load volatile i16, ptr %148, align 2, !tbaa !20
  %150 = zext i16 %149 to i32
  %151 = add nsw i32 %150, 1
  %152 = ashr i32 %151, 1
  %153 = trunc i32 %152 to i16
  %154 = load ptr, ptr %5, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %154, i32 0, i32 4
  store volatile i16 %153, ptr %155, align 2, !tbaa !20
  br label %156

156:                                              ; preds = %146, %138
  %157 = load ptr, ptr %5, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %157, i32 0, i32 11
  %159 = load ptr, ptr %158, align 8, !tbaa !31
  %160 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %159, i32 0, i32 1
  %161 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %160, i32 0, i32 5
  %162 = load i32, ptr %161, align 4, !tbaa !32
  %163 = icmp eq i32 %162, 16384
  br i1 %163, label %164, label %174

164:                                              ; preds = %156
  %165 = load ptr, ptr %5, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %165, i32 0, i32 4
  %167 = load volatile i16, ptr %166, align 2, !tbaa !20
  %168 = zext i16 %167 to i32
  %169 = add nsw i32 %168, 3
  %170 = ashr i32 %169, 2
  %171 = trunc i32 %170 to i16
  %172 = load ptr, ptr %5, align 8, !tbaa !5
  %173 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %172, i32 0, i32 4
  store volatile i16 %171, ptr %173, align 2, !tbaa !20
  br label %174

174:                                              ; preds = %164, %156
  br label %203

175:                                              ; preds = %131
  %176 = load ptr, ptr %5, align 8, !tbaa !5
  %177 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %176, i32 0, i32 1
  %178 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %177, i32 0, i32 2
  %179 = load i32, ptr %178, align 8, !tbaa !30
  %180 = zext i32 %179 to i64
  %181 = icmp ule i64 %180, 15
  br i1 %181, label %182, label %201

182:                                              ; preds = %175
  %183 = load ptr, ptr %5, align 8, !tbaa !5
  %184 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %183, i32 0, i32 11
  %185 = load ptr, ptr %184, align 8, !tbaa !31
  %186 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %185, i32 0, i32 1
  %187 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %186, i32 0, i32 5
  %188 = load i32, ptr %187, align 4, !tbaa !32
  %189 = icmp eq i32 %188, 16384
  br i1 %189, label %190, label %200

190:                                              ; preds = %182
  %191 = load ptr, ptr %5, align 8, !tbaa !5
  %192 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %191, i32 0, i32 4
  %193 = load volatile i16, ptr %192, align 2, !tbaa !20
  %194 = zext i16 %193 to i32
  %195 = add nsw i32 %194, 1
  %196 = ashr i32 %195, 1
  %197 = trunc i32 %196 to i16
  %198 = load ptr, ptr %5, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %198, i32 0, i32 4
  store volatile i16 %197, ptr %199, align 2, !tbaa !20
  br label %200

200:                                              ; preds = %190, %182
  br label %202

201:                                              ; preds = %175
  br label %202

202:                                              ; preds = %201, %200
  br label %203

203:                                              ; preds = %202, %174
  %204 = load ptr, ptr %5, align 8, !tbaa !5
  %205 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %204, i32 0, i32 11
  %206 = load ptr, ptr %205, align 8, !tbaa !31
  %207 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %206, i32 0, i32 6
  store ptr @SPI_DMAHalfTransmitCplt, ptr %207, align 8, !tbaa !35
  %208 = load ptr, ptr %5, align 8, !tbaa !5
  %209 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %208, i32 0, i32 11
  %210 = load ptr, ptr %209, align 8, !tbaa !31
  %211 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %210, i32 0, i32 5
  store ptr @SPI_DMATransmitCplt, ptr %211, align 8, !tbaa !36
  %212 = load ptr, ptr %5, align 8, !tbaa !5
  %213 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %212, i32 0, i32 11
  %214 = load ptr, ptr %213, align 8, !tbaa !31
  %215 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %214, i32 0, i32 9
  store ptr @SPI_DMAError, ptr %215, align 8, !tbaa !37
  %216 = load ptr, ptr %5, align 8, !tbaa !5
  %217 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %216, i32 0, i32 11
  %218 = load ptr, ptr %217, align 8, !tbaa !31
  %219 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %218, i32 0, i32 10
  store ptr null, ptr %219, align 8, !tbaa !38
  %220 = load ptr, ptr %5, align 8, !tbaa !5
  %221 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %220, i32 0, i32 0
  %222 = load ptr, ptr %221, align 8, !tbaa !27
  %223 = getelementptr inbounds %struct.SPI_TypeDef, ptr %222, i32 0, i32 2
  %224 = load volatile i32, ptr %223, align 4, !tbaa !39
  %225 = zext i32 %224 to i64
  %226 = and i64 %225, -32769
  %227 = trunc i64 %226 to i32
  store volatile i32 %227, ptr %223, align 4, !tbaa !39
  %228 = load ptr, ptr %5, align 8, !tbaa !5
  %229 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %228, i32 0, i32 11
  %230 = load ptr, ptr %229, align 8, !tbaa !31
  %231 = load ptr, ptr %5, align 8, !tbaa !5
  %232 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %231, i32 0, i32 2
  %233 = load ptr, ptr %232, align 8, !tbaa !18
  %234 = ptrtoint ptr %233 to i32
  %235 = load ptr, ptr %5, align 8, !tbaa !5
  %236 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %235, i32 0, i32 0
  %237 = load ptr, ptr %236, align 8, !tbaa !27
  %238 = getelementptr inbounds %struct.SPI_TypeDef, ptr %237, i32 0, i32 8
  %239 = ptrtoint ptr %238 to i32
  %240 = load ptr, ptr %5, align 8, !tbaa !5
  %241 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %240, i32 0, i32 4
  %242 = load volatile i16, ptr %241, align 2, !tbaa !20
  %243 = zext i16 %242 to i32
  %244 = call i32 @HAL_DMA_Start_IT(ptr noundef %230, i32 noundef %234, i32 noundef %239, i32 noundef %243)
  %245 = icmp ne i32 0, %244
  br i1 %245, label %246, label %261

246:                                              ; preds = %203
  %247 = load ptr, ptr %5, align 8, !tbaa !5
  %248 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %247, i32 0, i32 15
  %249 = load volatile i32, ptr %248, align 8, !tbaa !17
  %250 = zext i32 %249 to i64
  %251 = or i64 %250, 16
  %252 = trunc i64 %251 to i32
  store volatile i32 %252, ptr %248, align 8, !tbaa !17
  br label %253

253:                                              ; preds = %246
  %254 = load ptr, ptr %5, align 8, !tbaa !5
  %255 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %254, i32 0, i32 13
  store i32 0, ptr %255, align 8, !tbaa !13
  br label %256

256:                                              ; preds = %253
  br label %257

257:                                              ; preds = %256
  %258 = load ptr, ptr %5, align 8, !tbaa !5
  %259 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %258, i32 0, i32 14
  store volatile i32 1, ptr %259, align 4, !tbaa !16
  store i32 1, ptr %8, align 4, !tbaa !11
  %260 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %260, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

261:                                              ; preds = %203
  %262 = load ptr, ptr %5, align 8, !tbaa !5
  %263 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %262, i32 0, i32 11
  %264 = load ptr, ptr %263, align 8, !tbaa !31
  %265 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %264, i32 0, i32 1
  %266 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %265, i32 0, i32 6
  %267 = load i32, ptr %266, align 8, !tbaa !40
  %268 = icmp eq i32 %267, 256
  br i1 %268, label %269, label %283

269:                                              ; preds = %261
  %270 = load ptr, ptr %5, align 8, !tbaa !5
  %271 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %270, i32 0, i32 0
  %272 = load ptr, ptr %271, align 8, !tbaa !27
  %273 = getelementptr inbounds %struct.SPI_TypeDef, ptr %272, i32 0, i32 1
  %274 = load volatile i32, ptr %273, align 4, !tbaa !41
  %275 = zext i32 %274 to i64
  %276 = and i64 %275, -65536
  %277 = or i64 %276, 0
  %278 = trunc i64 %277 to i32
  %279 = load ptr, ptr %5, align 8, !tbaa !5
  %280 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %279, i32 0, i32 0
  %281 = load ptr, ptr %280, align 8, !tbaa !27
  %282 = getelementptr inbounds %struct.SPI_TypeDef, ptr %281, i32 0, i32 1
  store volatile i32 %278, ptr %282, align 4, !tbaa !41
  br label %299

283:                                              ; preds = %261
  %284 = load ptr, ptr %5, align 8, !tbaa !5
  %285 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %284, i32 0, i32 0
  %286 = load ptr, ptr %285, align 8, !tbaa !27
  %287 = getelementptr inbounds %struct.SPI_TypeDef, ptr %286, i32 0, i32 1
  %288 = load volatile i32, ptr %287, align 4, !tbaa !41
  %289 = zext i32 %288 to i64
  %290 = and i64 %289, -65536
  %291 = load i16, ptr %7, align 2, !tbaa !9
  %292 = zext i16 %291 to i64
  %293 = or i64 %290, %292
  %294 = trunc i64 %293 to i32
  %295 = load ptr, ptr %5, align 8, !tbaa !5
  %296 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %295, i32 0, i32 0
  %297 = load ptr, ptr %296, align 8, !tbaa !27
  %298 = getelementptr inbounds %struct.SPI_TypeDef, ptr %297, i32 0, i32 1
  store volatile i32 %294, ptr %298, align 4, !tbaa !41
  br label %299

299:                                              ; preds = %283, %269
  %300 = load ptr, ptr %5, align 8, !tbaa !5
  %301 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %300, i32 0, i32 0
  %302 = load ptr, ptr %301, align 8, !tbaa !27
  %303 = getelementptr inbounds %struct.SPI_TypeDef, ptr %302, i32 0, i32 2
  %304 = load volatile i32, ptr %303, align 4, !tbaa !39
  %305 = zext i32 %304 to i64
  %306 = or i64 %305, 32768
  %307 = trunc i64 %306 to i32
  store volatile i32 %307, ptr %303, align 4, !tbaa !39
  %308 = load ptr, ptr %5, align 8, !tbaa !5
  %309 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %308, i32 0, i32 0
  %310 = load ptr, ptr %309, align 8, !tbaa !27
  %311 = getelementptr inbounds %struct.SPI_TypeDef, ptr %310, i32 0, i32 4
  %312 = load volatile i32, ptr %311, align 4, !tbaa !42
  %313 = zext i32 %312 to i64
  %314 = or i64 %313, 800
  %315 = trunc i64 %314 to i32
  store volatile i32 %315, ptr %311, align 4, !tbaa !42
  %316 = load ptr, ptr %5, align 8, !tbaa !5
  %317 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %316, i32 0, i32 0
  %318 = load ptr, ptr %317, align 8, !tbaa !27
  %319 = getelementptr inbounds %struct.SPI_TypeDef, ptr %318, i32 0, i32 0
  %320 = load volatile i32, ptr %319, align 4, !tbaa !28
  %321 = zext i32 %320 to i64
  %322 = or i64 %321, 1
  %323 = trunc i64 %322 to i32
  store volatile i32 %323, ptr %319, align 4, !tbaa !28
  %324 = load ptr, ptr %5, align 8, !tbaa !5
  %325 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %324, i32 0, i32 1
  %326 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %325, i32 0, i32 0
  %327 = load i32, ptr %326, align 8, !tbaa !43
  %328 = zext i32 %327 to i64
  %329 = icmp eq i64 %328, 4194304
  br i1 %329, label %330, label %339

330:                                              ; preds = %299
  %331 = load ptr, ptr %5, align 8, !tbaa !5
  %332 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %331, i32 0, i32 0
  %333 = load ptr, ptr %332, align 8, !tbaa !27
  %334 = getelementptr inbounds %struct.SPI_TypeDef, ptr %333, i32 0, i32 0
  %335 = load volatile i32, ptr %334, align 4, !tbaa !28
  %336 = zext i32 %335 to i64
  %337 = or i64 %336, 512
  %338 = trunc i64 %337 to i32
  store volatile i32 %338, ptr %334, align 4, !tbaa !28
  br label %339

339:                                              ; preds = %330, %299
  br label %340

340:                                              ; preds = %339
  %341 = load ptr, ptr %5, align 8, !tbaa !5
  %342 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %341, i32 0, i32 13
  store i32 0, ptr %342, align 8, !tbaa !13
  br label %343

343:                                              ; preds = %340
  br label %344

344:                                              ; preds = %343
  %345 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %345, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %346

346:                                              ; preds = %344, %257, %129, %45, %31, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %347 = load i32, ptr %4, align 4
  ret i32 %347
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfTransmitCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATransmitCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 160}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 164}
!17 = !{!14, !12, i64 168}
!18 = !{!14, !6, i64 96}
!19 = !{!14, !10, i64 104}
!20 = !{!14, !10, i64 106}
!21 = !{!14, !6, i64 112}
!22 = !{!14, !6, i64 136}
!23 = !{!14, !6, i64 128}
!24 = !{!14, !10, i64 120}
!25 = !{!14, !10, i64 122}
!26 = !{!14, !12, i64 12}
!27 = !{!14, !6, i64 0}
!28 = !{!29, !12, i64 0}
!29 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!30 = !{!14, !12, i64 16}
!31 = !{!14, !6, i64 144}
!32 = !{!33, !12, i64 28}
!33 = !{!"__DMA_HandleTypeDef", !6, i64 0, !34, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!34 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!35 = !{!33, !6, i64 80}
!36 = !{!33, !6, i64 72}
!37 = !{!33, !6, i64 104}
!38 = !{!33, !6, i64 112}
!39 = !{!29, !12, i64 8}
!40 = !{!33, !12, i64 32}
!41 = !{!29, !12, i64 4}
!42 = !{!29, !12, i64 16}
!43 = !{!14, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SPI_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 160
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %98, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 164
  %9 = load volatile i32, ptr %8, align 4, !tbaa !13
  %.not = icmp eq i32 %9, 1
  br i1 %.not, label %11, label %10

10:                                               ; preds = %7
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %98

11:                                               ; preds = %7
  %12 = icmp eq ptr %1, null
  %13 = icmp eq i16 %2, 0
  %or.cond = or i1 %12, %13
  br i1 %or.cond, label %14, label %15

14:                                               ; preds = %11
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %98

15:                                               ; preds = %11
  store volatile i32 3, ptr %8, align 4, !tbaa !13
  %16 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %16, align 8, !tbaa !14
  %17 = getelementptr inbounds i8, ptr %0, i64 96
  store ptr %1, ptr %17, align 8, !tbaa !15
  %18 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 %2, ptr %18, align 8, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %0, i64 106
  store volatile i16 %2, ptr %19, align 2, !tbaa !17
  %20 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr null, ptr %20, align 8, !tbaa !18
  %21 = getelementptr inbounds i8, ptr %0, i64 128
  %22 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 0, ptr %22, align 8, !tbaa !19
  %23 = getelementptr inbounds i8, ptr %0, i64 122
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %21, i8 0, i64 16, i1 false)
  store volatile i16 0, ptr %23, align 2, !tbaa !20
  %24 = getelementptr inbounds i8, ptr %0, i64 8
  %25 = getelementptr inbounds i8, ptr %0, i64 12
  %26 = load i32, ptr %25, align 4, !tbaa !21
  %27 = icmp eq i32 %26, 393216
  br i1 %27, label %28, label %32

28:                                               ; preds = %15
  %29 = load ptr, ptr %0, align 8, !tbaa !22
  %30 = load volatile i32, ptr %29, align 4, !tbaa !23
  %31 = or i32 %30, 2048
  store volatile i32 %31, ptr %29, align 4, !tbaa !23
  br label %32

32:                                               ; preds = %28, %15
  %33 = getelementptr inbounds i8, ptr %0, i64 16
  %34 = load i32, ptr %33, align 8, !tbaa !25
  %35 = icmp ugt i32 %34, 15
  br i1 %35, label %36, label %41

36:                                               ; preds = %32
  %37 = getelementptr inbounds i8, ptr %0, i64 144
  %38 = load ptr, ptr %37, align 8, !tbaa !26
  %39 = getelementptr inbounds i8, ptr %38, i64 28
  %40 = load i32, ptr %39, align 4, !tbaa !27
  %.not74 = icmp eq i32 %40, 16384
  br i1 %.not74, label %51, label %43

41:                                               ; preds = %32
  %42 = icmp ugt i32 %34, 7
  %.phi.trans.insert = getelementptr inbounds i8, ptr %0, i64 144
  %.pre = load ptr, ptr %.phi.trans.insert, align 8, !tbaa !26
  %.phi.trans.insert80 = getelementptr inbounds i8, ptr %.pre, i64 28
  %.pre81 = load i32, ptr %.phi.trans.insert80, align 4, !tbaa !27
  br i1 %42, label %.thread, label %44

.thread:                                          ; preds = %41
  switch i32 %.pre81, label %43 [
    i32 16384, label %.sink.split
    i32 8192, label %51
  ]

43:                                               ; preds = %.thread, %36
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %98

44:                                               ; preds = %41
  switch i32 %.pre81, label %51 [
    i32 8192, label %.sink.split
    i32 16384, label %45
  ]

45:                                               ; preds = %44
  br label %.sink.split

.sink.split:                                      ; preds = %.thread, %44, %45
  %.sink86 = phi i32 [ 3, %45 ], [ 1, %44 ], [ 1, %.thread ]
  %.sink84 = phi i32 [ 2, %45 ], [ 1, %44 ], [ 1, %.thread ]
  %46 = load volatile i16, ptr %19, align 2, !tbaa !17
  %47 = zext i16 %46 to i32
  %48 = add nuw nsw i32 %.sink86, %47
  %49 = lshr i32 %48, %.sink84
  %50 = trunc nuw i32 %49 to i16
  store volatile i16 %50, ptr %19, align 2, !tbaa !17
  br label %51

51:                                               ; preds = %.sink.split, %.thread, %36, %44
  %52 = phi ptr [ %.pre, %44 ], [ %38, %36 ], [ %.pre, %.thread ], [ %.pre, %.sink.split ]
  %53 = getelementptr inbounds i8, ptr %52, i64 80
  store ptr @SPI_DMAHalfTransmitCplt, ptr %53, align 8, !tbaa !30
  %54 = getelementptr inbounds i8, ptr %52, i64 72
  store ptr @SPI_DMATransmitCplt, ptr %54, align 8, !tbaa !31
  %55 = getelementptr inbounds i8, ptr %52, i64 104
  store ptr @SPI_DMAError, ptr %55, align 8, !tbaa !32
  %56 = getelementptr inbounds i8, ptr %52, i64 112
  store ptr null, ptr %56, align 8, !tbaa !33
  %57 = load ptr, ptr %0, align 8, !tbaa !22
  %58 = getelementptr inbounds i8, ptr %57, i64 8
  %59 = load volatile i32, ptr %58, align 4, !tbaa !34
  %60 = and i32 %59, -32769
  store volatile i32 %60, ptr %58, align 4, !tbaa !34
  %61 = ptrtoint ptr %1 to i64
  %62 = trunc i64 %61 to i32
  %63 = getelementptr inbounds i8, ptr %57, i64 32
  %64 = ptrtoint ptr %63 to i64
  %65 = trunc i64 %64 to i32
  %66 = load volatile i16, ptr %19, align 2, !tbaa !17
  %67 = zext i16 %66 to i32
  %68 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %52, i32 noundef %62, i32 noundef %65, i32 noundef %67) #3
  %.not77 = icmp eq i32 %68, 0
  br i1 %.not77, label %72, label %69

69:                                               ; preds = %51
  %70 = load volatile i32, ptr %16, align 8, !tbaa !14
  %71 = or i32 %70, 16
  store volatile i32 %71, ptr %16, align 8, !tbaa !14
  store i32 0, ptr %4, align 8, !tbaa !5
  store volatile i32 1, ptr %8, align 4, !tbaa !13
  br label %98

72:                                               ; preds = %51
  %73 = getelementptr inbounds i8, ptr %0, i64 144
  %74 = load ptr, ptr %73, align 8, !tbaa !26
  %75 = getelementptr inbounds i8, ptr %74, i64 32
  %76 = load i32, ptr %75, align 8, !tbaa !35
  %77 = icmp eq i32 %76, 256
  %78 = load ptr, ptr %0, align 8, !tbaa !22
  %79 = getelementptr inbounds i8, ptr %78, i64 4
  %80 = load volatile i32, ptr %79, align 4, !tbaa !36
  %81 = and i32 %80, -65536
  %82 = zext i16 %2 to i32
  %83 = select i1 %77, i32 0, i32 %82
  %.sink = or disjoint i32 %81, %83
  store volatile i32 %.sink, ptr %79, align 4, !tbaa !36
  %84 = getelementptr inbounds i8, ptr %78, i64 8
  %85 = load volatile i32, ptr %84, align 4, !tbaa !34
  %86 = or i32 %85, 32768
  store volatile i32 %86, ptr %84, align 4, !tbaa !34
  %87 = getelementptr inbounds i8, ptr %78, i64 16
  %88 = load volatile i32, ptr %87, align 4, !tbaa !37
  %89 = or i32 %88, 800
  store volatile i32 %89, ptr %87, align 4, !tbaa !37
  %90 = load volatile i32, ptr %78, align 4, !tbaa !23
  %91 = or i32 %90, 1
  store volatile i32 %91, ptr %78, align 4, !tbaa !23
  %92 = load i32, ptr %24, align 8, !tbaa !38
  %93 = icmp eq i32 %92, 4194304
  br i1 %93, label %94, label %97

94:                                               ; preds = %72
  %95 = load volatile i32, ptr %78, align 4, !tbaa !23
  %96 = or i32 %95, 512
  store volatile i32 %96, ptr %78, align 4, !tbaa !23
  br label %97

97:                                               ; preds = %72, %94
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %98

98:                                               ; preds = %3, %97, %69, %43, %14, %10
  %.0 = phi i32 [ 2, %10 ], [ 1, %14 ], [ 1, %43 ], [ 1, %69 ], [ 0, %97 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfTransmitCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMATransmitCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 160}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 164}
!14 = !{!6, !11, i64 168}
!15 = !{!6, !7, i64 96}
!16 = !{!6, !12, i64 104}
!17 = !{!6, !12, i64 106}
!18 = !{!6, !7, i64 112}
!19 = !{!6, !12, i64 120}
!20 = !{!6, !12, i64 122}
!21 = !{!6, !11, i64 12}
!22 = !{!6, !7, i64 0}
!23 = !{!24, !11, i64 0}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!25 = !{!6, !11, i64 16}
!26 = !{!6, !7, i64 144}
!27 = !{!28, !11, i64 28}
!28 = !{!"__DMA_HandleTypeDef", !7, i64 0, !29, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!29 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!30 = !{!28, !7, i64 80}
!31 = !{!28, !7, i64 72}
!32 = !{!28, !7, i64 104}
!33 = !{!28, !7, i64 112}
!34 = !{!24, !11, i64 8}
!35 = !{!28, !11, i64 32}
!36 = !{!24, !11, i64 4}
!37 = !{!24, !11, i64 16}
!38 = !{!6, !11, i64 8}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass