; LLVM IR from ritikbanger/Hacktoberfest2022-DSA :: 27. LeetCode Problems/Search_in_Rotated_Sorted_Array.ll (Z6searchRSt6vectorIiSaIiEEi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z6searchRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #2
  %12 = sub i64 %11, 1
  %13 = trunc i64 %12 to i32
  store i32 %13, ptr %7, align 4, !tbaa !9
  br label %14

14:                                               ; preds = %121, %2
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = load i32, ptr %7, align 4, !tbaa !9
  %17 = icmp sle i32 %15, %16
  br i1 %17, label %18, label %122

18:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %19 = load i32, ptr %6, align 4, !tbaa !9
  %20 = load i32, ptr %7, align 4, !tbaa !9
  %21 = add nsw i32 %19, %20
  %22 = sdiv i32 %21, 2
  store i32 %22, ptr %8, align 4, !tbaa !9
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = load i32, ptr %8, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %26) #2
  %28 = load i32, ptr %27, align 4, !tbaa !9
  %29 = icmp eq i32 %23, %28
  br i1 %29, label %30, label %32

30:                                               ; preds = %18
  %31 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %31, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %119

32:                                               ; preds = %18
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  %34 = load i32, ptr %8, align 4, !tbaa !9
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %35) #2
  %37 = load i32, ptr %36, align 4, !tbaa !9
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %40) #2
  %42 = load i32, ptr %41, align 4, !tbaa !9
  %43 = icmp sgt i32 %37, %42
  br i1 %43, label %44, label %67

44:                                               ; preds = %32
  %45 = load i32, ptr %5, align 4, !tbaa !9
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = load i32, ptr %8, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #2
  %50 = load i32, ptr %49, align 4, !tbaa !9
  %51 = icmp slt i32 %45, %50
  br i1 %51, label %52, label %63

52:                                               ; preds = %44
  %53 = load i32, ptr %5, align 4, !tbaa !9
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = load i32, ptr %6, align 4, !tbaa !9
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %54, i64 noundef %56) #2
  %58 = load i32, ptr %57, align 4, !tbaa !9
  %59 = icmp sge i32 %53, %58
  br i1 %59, label %60, label %63

60:                                               ; preds = %52
  %61 = load i32, ptr %8, align 4, !tbaa !9
  %62 = sub nsw i32 %61, 1
  store i32 %62, ptr %7, align 4, !tbaa !9
  br label %66

63:                                               ; preds = %52, %44
  %64 = load i32, ptr %8, align 4, !tbaa !9
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %6, align 4, !tbaa !9
  br label %66

66:                                               ; preds = %63, %60
  br label %118

67:                                               ; preds = %32
  %68 = load ptr, ptr %4, align 8, !tbaa !5
  %69 = load i32, ptr %8, align 4, !tbaa !9
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %70) #2
  %72 = load i32, ptr %71, align 4, !tbaa !9
  %73 = load ptr, ptr %4, align 8, !tbaa !5
  %74 = load i32, ptr %6, align 4, !tbaa !9
  %75 = sext i32 %74 to i64
  %76 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %75) #2
  %77 = load i32, ptr %76, align 4, !tbaa !9
  %78 = icmp slt i32 %72, %77
  br i1 %78, label %79, label %102

79:                                               ; preds = %67
  %80 = load i32, ptr %5, align 4, !tbaa !9
  %81 = load ptr, ptr %4, align 8, !tbaa !5
  %82 = load i32, ptr %8, align 4, !tbaa !9
  %83 = sext i32 %82 to i64
  %84 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %83) #2
  %85 = load i32, ptr %84, align 4, !tbaa !9
  %86 = icmp sgt i32 %80, %85
  br i1 %86, label %87, label %98

87:                                               ; preds = %79
  %88 = load i32, ptr %5, align 4, !tbaa !9
  %89 = load ptr, ptr %4, align 8, !tbaa !5
  %90 = load i32, ptr %7, align 4, !tbaa !9
  %91 = sext i32 %90 to i64
  %92 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %89, i64 noundef %91) #2
  %93 = load i32, ptr %92, align 4, !tbaa !9
  %94 = icmp sle i32 %88, %93
  br i1 %94, label %95, label %98

95:                                               ; preds = %87
  %96 = load i32, ptr %8, align 4, !tbaa !9
  %97 = add nsw i32 %96, 1
  store i32 %97, ptr %6, align 4, !tbaa !9
  br label %101

98:                                               ; preds = %87, %79
  %99 = load i32, ptr %8, align 4, !tbaa !9
  %100 = sub nsw i32 %99, 1
  store i32 %100, ptr %7, align 4, !tbaa !9
  br label %101

101:                                              ; preds = %98, %95
  br label %117

102:                                              ; preds = %67
  %103 = load i32, ptr %5, align 4, !tbaa !9
  %104 = load ptr, ptr %4, align 8, !tbaa !5
  %105 = load i32, ptr %8, align 4, !tbaa !9
  %106 = sext i32 %105 to i64
  %107 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %104, i64 noundef %106) #2
  %108 = load i32, ptr %107, align 4, !tbaa !9
  %109 = icmp slt i32 %103, %108
  br i1 %109, label %110, label %113

110:                                              ; preds = %102
  %111 = load i32, ptr %8, align 4, !tbaa !9
  %112 = sub nsw i32 %111, 1
  store i32 %112, ptr %7, align 4, !tbaa !9
  br label %116

113:                                              ; preds = %102
  %114 = load i32, ptr %8, align 4, !tbaa !9
  %115 = add nsw i32 %114, 1
  store i32 %115, ptr %6, align 4, !tbaa !9
  br label %116

116:                                              ; preds = %113, %110
  br label %117

117:                                              ; preds = %116, %101
  br label %118

118:                                              ; preds = %117, %66
  store i32 0, ptr %9, align 4
  br label %119

119:                                              ; preds = %118, %30
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %120 = load i32, ptr %9, align 4
  switch i32 %120, label %123 [
    i32 0, label %121
  ]

121:                                              ; preds = %119
  br label %14, !llvm.loop !11

122:                                              ; preds = %14
  store i32 -1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %123

123:                                              ; preds = %122, %119
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %124 = load i32, ptr %3, align 4
  ret i32 %124
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z6searchRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %4 = trunc i64 %3 to i32
  %5 = add i32 %4, -1
  %.not53 = icmp slt i32 %5, 0
  br i1 %.not53, label %.thread, label %.lr.ph

.lr.ph:                                           ; preds = %2, %52
  %.04055 = phi i32 [ %.242, %52 ], [ %5, %2 ]
  %.04354 = phi i32 [ %.245, %52 ], [ 0, %2 ]
  %6 = add nuw nsw i32 %.04055, %.04354
  %7 = lshr i32 %6, 1
  %8 = zext nneg i32 %7 to i64
  %9 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #1
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %.not49 = icmp eq i32 %10, %1
  br i1 %.not49, label %.thread, label %11

11:                                               ; preds = %.lr.ph
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #1
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = zext nneg i32 %.04055 to i64
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %14) #1
  %16 = load i32, ptr %15, align 4, !tbaa !5
  %17 = icmp sgt i32 %13, %16
  %18 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #1
  %19 = load i32, ptr %18, align 4, !tbaa !5
  br i1 %17, label %20, label %30

20:                                               ; preds = %11
  %21 = icmp sgt i32 %19, %1
  br i1 %21, label %22, label %28

22:                                               ; preds = %20
  %23 = zext nneg i32 %.04354 to i64
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %23) #1
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %.not48 = icmp sgt i32 %25, %1
  br i1 %.not48, label %28, label %26

26:                                               ; preds = %22
  %27 = add nsw i32 %7, -1
  br label %52

28:                                               ; preds = %22, %20
  %29 = add nuw nsw i32 %7, 1
  br label %52

30:                                               ; preds = %11
  %31 = zext nneg i32 %.04354 to i64
  %32 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %31) #1
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = icmp slt i32 %19, %33
  %35 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #1
  %36 = load i32, ptr %35, align 4, !tbaa !5
  br i1 %34, label %37, label %46

37:                                               ; preds = %30
  %38 = icmp slt i32 %36, %1
  br i1 %38, label %39, label %44

39:                                               ; preds = %37
  %40 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %14) #1
  %41 = load i32, ptr %40, align 4, !tbaa !5
  %.not47 = icmp slt i32 %41, %1
  br i1 %.not47, label %44, label %42

42:                                               ; preds = %39
  %43 = add nuw nsw i32 %7, 1
  br label %52

44:                                               ; preds = %39, %37
  %45 = add nsw i32 %7, -1
  br label %52

46:                                               ; preds = %30
  %47 = icmp sgt i32 %36, %1
  br i1 %47, label %48, label %50

48:                                               ; preds = %46
  %49 = add nsw i32 %7, -1
  br label %52

50:                                               ; preds = %46
  %51 = add nuw nsw i32 %7, 1
  br label %52

52:                                               ; preds = %28, %26, %48, %50, %42, %44
  %.245 = phi i32 [ %.04354, %26 ], [ %29, %28 ], [ %43, %42 ], [ %.04354, %44 ], [ %.04354, %48 ], [ %51, %50 ]
  %.242 = phi i32 [ %27, %26 ], [ %.04055, %28 ], [ %.04055, %42 ], [ %45, %44 ], [ %49, %48 ], [ %.04055, %50 ]
  %.not = icmp sgt i32 %.245, %.242
  br i1 %.not, label %.thread, label %.lr.ph

.thread:                                          ; preds = %52, %.lr.ph, %2
  %.2 = phi i32 [ -1, %2 ], [ %7, %.lr.ph ], [ -1, %52 ]
  ret i32 %.2
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass