; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_CCxNChannelCmd(ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_OnePulseN_Start_IT(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = icmp eq i32 %12, 0
  %14 = zext i1 %13 to i64
  %15 = select i1 %13, i32 4, i32 0
  store i32 %15, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %16, i32 0, i32 6
  %18 = getelementptr inbounds [6 x i32], ptr %17, i64 0, i64 0
  %19 = load volatile i32, ptr %18, align 8, !tbaa !9
  store i32 %19, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %20, i32 0, i32 6
  %22 = getelementptr inbounds [6 x i32], ptr %21, i64 0, i64 1
  %23 = load volatile i32, ptr %22, align 4, !tbaa !9
  store i32 %23, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %24, i32 0, i32 7
  %26 = getelementptr inbounds [4 x i32], ptr %25, i64 0, i64 0
  %27 = load volatile i32, ptr %26, align 8, !tbaa !9
  store i32 %27, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 7
  %30 = getelementptr inbounds [4 x i32], ptr %29, i64 0, i64 1
  %31 = load volatile i32, ptr %30, align 4, !tbaa !9
  store i32 %31, ptr %10, align 4, !tbaa !9
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = icmp ne i32 %32, 1
  br i1 %33, label %43, label %34

34:                                               ; preds = %2
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = icmp ne i32 %35, 1
  br i1 %36, label %43, label %37

37:                                               ; preds = %34
  %38 = load i32, ptr %9, align 4, !tbaa !9
  %39 = icmp ne i32 %38, 1
  br i1 %39, label %43, label %40

40:                                               ; preds = %37
  %41 = load i32, ptr %10, align 4, !tbaa !9
  %42 = icmp ne i32 %41, 1
  br i1 %42, label %43, label %44

43:                                               ; preds = %40, %37, %34, %2
  store i32 1, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %89

44:                                               ; preds = %40
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %45, i32 0, i32 6
  %47 = getelementptr inbounds [6 x i32], ptr %46, i64 0, i64 0
  store volatile i32 2, ptr %47, align 8, !tbaa !9
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %48, i32 0, i32 6
  %50 = getelementptr inbounds [6 x i32], ptr %49, i64 0, i64 1
  store volatile i32 2, ptr %50, align 4, !tbaa !9
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %51, i32 0, i32 7
  %53 = getelementptr inbounds [4 x i32], ptr %52, i64 0, i64 0
  store volatile i32 2, ptr %53, align 8, !tbaa !9
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 7
  %56 = getelementptr inbounds [4 x i32], ptr %55, i64 0, i64 1
  store volatile i32 2, ptr %56, align 4, !tbaa !9
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !11
  %60 = getelementptr inbounds %struct.TIM_TypeDef, ptr %59, i32 0, i32 3
  %61 = load volatile i32, ptr %60, align 4, !tbaa !14
  %62 = zext i32 %61 to i64
  %63 = or i64 %62, 2
  %64 = trunc i64 %63 to i32
  store volatile i32 %64, ptr %60, align 4, !tbaa !14
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %65, i32 0, i32 0
  %67 = load ptr, ptr %66, align 8, !tbaa !11
  %68 = getelementptr inbounds %struct.TIM_TypeDef, ptr %67, i32 0, i32 3
  %69 = load volatile i32, ptr %68, align 4, !tbaa !14
  %70 = zext i32 %69 to i64
  %71 = or i64 %70, 4
  %72 = trunc i64 %71 to i32
  store volatile i32 %72, ptr %68, align 4, !tbaa !14
  %73 = load ptr, ptr %4, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %73, i32 0, i32 0
  %75 = load ptr, ptr %74, align 8, !tbaa !11
  %76 = load i32, ptr %5, align 4, !tbaa !9
  call void @TIM_CCxNChannelCmd(ptr noundef %75, i32 noundef %76, i32 noundef 4)
  %77 = load ptr, ptr %4, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !11
  %80 = load i32, ptr %6, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %79, i32 noundef %80, i32 noundef 1)
  %81 = load ptr, ptr %4, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !11
  %84 = getelementptr inbounds %struct.TIM_TypeDef, ptr %83, i32 0, i32 17
  %85 = load volatile i32, ptr %84, align 4, !tbaa !16
  %86 = zext i32 %85 to i64
  %87 = or i64 %86, 32768
  %88 = trunc i64 %87 to i32
  store volatile i32 %88, ptr %84, align 4, !tbaa !16
  store i32 0, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %89

89:                                               ; preds = %44, %43
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %90 = load i32, ptr %3, align 4
  ret i32 %90
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 68}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_CCxNChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_TIMEx_OnePulseN_Start_IT(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 104
  %4 = load volatile i32, ptr %3, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 108
  %6 = load volatile i32, ptr %5, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 128
  %8 = load volatile i32, ptr %7, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 132
  %10 = load volatile i32, ptr %9, align 4, !tbaa !5
  %11 = icmp ne i32 %4, 1
  %12 = icmp ne i32 %6, 1
  %or.cond = select i1 %11, i1 true, i1 %12
  %13 = icmp ne i32 %8, 1
  %or.cond3 = select i1 %or.cond, i1 true, i1 %13
  %14 = icmp ne i32 %10, 1
  %or.cond5 = select i1 %or.cond3, i1 true, i1 %14
  br i1 %or.cond5, label %29, label %15

15:                                               ; preds = %2
  %16 = icmp eq i32 %1, 0
  %17 = select i1 %16, i32 4, i32 0
  store volatile i32 2, ptr %3, align 8, !tbaa !5
  store volatile i32 2, ptr %5, align 4, !tbaa !5
  store volatile i32 2, ptr %7, align 8, !tbaa !5
  store volatile i32 2, ptr %9, align 4, !tbaa !5
  %18 = load ptr, ptr %0, align 8, !tbaa !9
  %19 = getelementptr inbounds i8, ptr %18, i64 12
  %20 = load volatile i32, ptr %19, align 4, !tbaa !13
  %21 = or i32 %20, 2
  store volatile i32 %21, ptr %19, align 4, !tbaa !13
  %22 = load volatile i32, ptr %19, align 4, !tbaa !13
  %23 = or i32 %22, 4
  store volatile i32 %23, ptr %19, align 4, !tbaa !13
  tail call void @TIM_CCxNChannelCmd(ptr noundef %18, i32 noundef %1, i32 noundef 4)
  %24 = load ptr, ptr %0, align 8, !tbaa !9
  tail call void @TIM_CCxChannelCmd(ptr noundef %24, i32 noundef %17, i32 noundef 1) #2
  %25 = load ptr, ptr %0, align 8, !tbaa !9
  %26 = getelementptr inbounds i8, ptr %25, i64 68
  %27 = load volatile i32, ptr %26, align 4, !tbaa !15
  %28 = or i32 %27, 32768
  store volatile i32 %28, ptr %26, align 4, !tbaa !15
  br label %29

29:                                               ; preds = %2, %15
  %.0 = phi i32 [ 0, %15 ], [ 1, %2 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !12, i64 8, !6, i64 32, !7, i64 40, !6, i64 96, !6, i64 100, !7, i64 104, !7, i64 128, !6, i64 144}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20}
!13 = !{!14, !6, i64 12}
!14 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92, !6, i64 96, !6, i64 100, !6, i64 104}
!15 = !{!14, !6, i64 68}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass