; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @ADC_Disable(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #2

declare i32 @ADC_ConversionStop(ptr noundef, i32 noundef) #1

declare i32 @HAL_GetTick() #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeStop_DMA(ptr noundef %0) #3 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca %struct.ADC_HandleTypeDef, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 120, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  br label %10

10:                                               ; preds = %1
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %11, i32 0, i32 3
  %13 = load i32, ptr %12, align 8, !tbaa !9
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %165

16:                                               ; preds = %10
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %17, i32 0, i32 3
  store i32 1, ptr %18, align 8, !tbaa !9
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = call i32 @ADC_ConversionStop(ptr noundef %22, i32 noundef 3)
  store i32 %23, ptr %4, align 4, !tbaa !15
  %24 = load i32, ptr %4, align 4, !tbaa !15
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %158

26:                                               ; preds = %21
  %27 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 4
  store volatile i32 0, ptr %27, align 4, !tbaa !16
  %28 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 5
  store volatile i32 0, ptr %28, align 8, !tbaa !17
  %29 = load ptr, ptr %3, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %29, i32 0, i32 0
  %31 = load ptr, ptr %30, align 8, !tbaa !18
  %32 = icmp eq ptr %31, inttoptr (i64 1073881088 to ptr)
  br i1 %32, label %33, label %35

33:                                               ; preds = %26
  %34 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  store ptr inttoptr (i64 1073881344 to ptr), ptr %34, align 8, !tbaa !18
  br label %37

35:                                               ; preds = %26
  %36 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  store ptr null, ptr %36, align 8, !tbaa !18
  br label %37

37:                                               ; preds = %35, %33
  %38 = phi ptr [ inttoptr (i64 1073881344 to ptr), %33 ], [ null, %35 ]
  %39 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  %40 = load ptr, ptr %39, align 8, !tbaa !18
  %41 = icmp eq ptr %40, null
  br i1 %41, label %42, label %54

42:                                               ; preds = %37
  %43 = load ptr, ptr %3, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %43, i32 0, i32 4
  %45 = load volatile i32, ptr %44, align 4, !tbaa !16
  %46 = zext i32 %45 to i64
  %47 = or i64 %46, 32
  %48 = trunc i64 %47 to i32
  store volatile i32 %48, ptr %44, align 4, !tbaa !16
  br label %49

49:                                               ; preds = %42
  %50 = load ptr, ptr %3, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %50, i32 0, i32 3
  store i32 0, ptr %51, align 8, !tbaa !9
  br label %52

52:                                               ; preds = %49
  br label %53

53:                                               ; preds = %52
  store i32 1, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %165

54:                                               ; preds = %37
  %55 = call i32 @HAL_GetTick()
  store i32 %55, ptr %5, align 4, !tbaa !15
  %56 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  %57 = load ptr, ptr %56, align 8, !tbaa !18
  %58 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %57)
  store i32 %58, ptr %7, align 4, !tbaa !15
  br label %59

59:                                               ; preds = %105, %54
  %60 = load ptr, ptr %3, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %60, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8, !tbaa !18
  %63 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %62)
  %64 = zext i32 %63 to i64
  %65 = icmp eq i64 %64, 1
  br i1 %65, label %70, label %66

66:                                               ; preds = %59
  %67 = load i32, ptr %7, align 4, !tbaa !15
  %68 = zext i32 %67 to i64
  %69 = icmp eq i64 %68, 1
  br label %70

70:                                               ; preds = %66, %59
  %71 = phi i1 [ true, %59 ], [ %69, %66 ]
  br i1 %71, label %72, label %109

72:                                               ; preds = %70
  %73 = call i32 @HAL_GetTick()
  %74 = load i32, ptr %5, align 4, !tbaa !15
  %75 = sub i32 %73, %74
  %76 = zext i32 %75 to i64
  %77 = icmp ugt i64 %76, 5
  br i1 %77, label %78, label %105

78:                                               ; preds = %72
  %79 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !18
  %81 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %80)
  store i32 %81, ptr %7, align 4, !tbaa !15
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !18
  %85 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %84)
  %86 = zext i32 %85 to i64
  %87 = icmp eq i64 %86, 1
  br i1 %87, label %92, label %88

88:                                               ; preds = %78
  %89 = load i32, ptr %7, align 4, !tbaa !15
  %90 = zext i32 %89 to i64
  %91 = icmp eq i64 %90, 1
  br i1 %91, label %92, label %104

92:                                               ; preds = %88, %78
  %93 = load ptr, ptr %3, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %93, i32 0, i32 4
  %95 = load volatile i32, ptr %94, align 4, !tbaa !16
  %96 = zext i32 %95 to i64
  %97 = or i64 %96, 16
  %98 = trunc i64 %97 to i32
  store volatile i32 %98, ptr %94, align 4, !tbaa !16
  br label %99

99:                                               ; preds = %92
  %100 = load ptr, ptr %3, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %100, i32 0, i32 3
  store i32 0, ptr %101, align 8, !tbaa !9
  br label %102

102:                                              ; preds = %99
  br label %103

103:                                              ; preds = %102
  store i32 1, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %165

104:                                              ; preds = %88
  br label %105

105:                                              ; preds = %104, %72
  %106 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %6, i32 0, i32 0
  %107 = load ptr, ptr %106, align 8, !tbaa !18
  %108 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %107)
  store i32 %108, ptr %7, align 4, !tbaa !15
  br label %59, !llvm.loop !19

109:                                              ; preds = %70
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %110, i32 0, i32 2
  %112 = load ptr, ptr %111, align 8, !tbaa !21
  %113 = call i32 @HAL_DMA_Abort(ptr noundef %112)
  store i32 %113, ptr %4, align 4, !tbaa !15
  %114 = load i32, ptr %4, align 4, !tbaa !15
  %115 = icmp eq i32 %114, 1
  br i1 %115, label %116, label %123

116:                                              ; preds = %109
  %117 = load ptr, ptr %3, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %117, i32 0, i32 4
  %119 = load volatile i32, ptr %118, align 4, !tbaa !16
  %120 = zext i32 %119 to i64
  %121 = or i64 %120, 64
  %122 = trunc i64 %121 to i32
  store volatile i32 %122, ptr %118, align 4, !tbaa !16
  br label %123

123:                                              ; preds = %116, %109
  %124 = load ptr, ptr %3, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !18
  %127 = getelementptr inbounds %struct.ADC_TypeDef, ptr %126, i32 0, i32 1
  %128 = load volatile i32, ptr %127, align 4, !tbaa !22
  %129 = zext i32 %128 to i64
  %130 = and i64 %129, -17
  %131 = trunc i64 %130 to i32
  store volatile i32 %131, ptr %127, align 4, !tbaa !22
  %132 = load i32, ptr %4, align 4, !tbaa !15
  %133 = icmp eq i32 %132, 0
  br i1 %133, label %134, label %144

134:                                              ; preds = %123
  %135 = call i32 @ADC_Disable(ptr noundef %6)
  store i32 %135, ptr %8, align 4, !tbaa !15
  %136 = load ptr, ptr %3, align 8, !tbaa !5
  %137 = call i32 @ADC_Disable(ptr noundef %136)
  %138 = icmp eq i32 %137, 0
  br i1 %138, label %139, label %143

139:                                              ; preds = %134
  %140 = load i32, ptr %8, align 4, !tbaa !15
  %141 = icmp eq i32 %140, 0
  br i1 %141, label %142, label %143

142:                                              ; preds = %139
  store i32 0, ptr %4, align 4, !tbaa !15
  br label %143

143:                                              ; preds = %142, %139, %134
  br label %148

144:                                              ; preds = %123
  %145 = load ptr, ptr %3, align 8, !tbaa !5
  %146 = call i32 @ADC_Disable(ptr noundef %145)
  %147 = call i32 @ADC_Disable(ptr noundef %6)
  br label %148

148:                                              ; preds = %144, %143
  %149 = load ptr, ptr %3, align 8, !tbaa !5
  %150 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %149, i32 0, i32 4
  %151 = load volatile i32, ptr %150, align 4, !tbaa !16
  %152 = zext i32 %151 to i64
  %153 = and i64 %152, -4353
  %154 = or i64 %153, 1
  %155 = trunc i64 %154 to i32
  %156 = load ptr, ptr %3, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %156, i32 0, i32 4
  store volatile i32 %155, ptr %157, align 4, !tbaa !16
  br label %158

158:                                              ; preds = %148, %21
  br label %159

159:                                              ; preds = %158
  %160 = load ptr, ptr %3, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %160, i32 0, i32 3
  store i32 0, ptr %161, align 8, !tbaa !9
  br label %162

162:                                              ; preds = %159
  br label %163

163:                                              ; preds = %162
  %164 = load i32, ptr %4, align 4, !tbaa !15
  store i32 %164, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %165

165:                                              ; preds = %163, %103, %53, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 120, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %166 = load i32, ptr %2, align 4
  ret i32 %166
}

declare i32 @HAL_DMA_Abort(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 96}
!10 = !{!"", !6, i64 0, !11, i64 8, !6, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !14, i64 108}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !13, i64 60}
!12 = !{!"int", !7, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!14 = !{!"", !12, i64 0, !12, i64 4}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !12, i64 100}
!17 = !{!10, !12, i64 104}
!18 = !{!10, !6, i64 0}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = !{!10, !6, i64 88}
!22 = !{!23, !12, i64 4}
!23 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !7, i64 112, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !7, i64 144, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @ADC_Disable(ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

declare i32 @ADC_ConversionStop(ptr noundef, i32 noundef) local_unnamed_addr #1

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeStop_DMA(ptr noundef %0) local_unnamed_addr #3 {
  %2 = alloca %struct.ADC_HandleTypeDef, align 8
  call void @llvm.lifetime.start.p0(i64 120, ptr nonnull %2) #4
  %3 = getelementptr inbounds i8, ptr %0, i64 96
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %72, label %6

6:                                                ; preds = %1
  store i32 1, ptr %3, align 8, !tbaa !5
  %7 = tail call i32 @ADC_ConversionStop(ptr noundef nonnull %0, i32 noundef 3) #4
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %.sink.split

9:                                                ; preds = %6
  %10 = getelementptr inbounds i8, ptr %2, i64 100
  store volatile i32 0, ptr %10, align 4, !tbaa !14
  %11 = getelementptr inbounds i8, ptr %2, i64 104
  store volatile i32 0, ptr %11, align 8, !tbaa !15
  %12 = load ptr, ptr %0, align 8, !tbaa !16
  %.not = icmp eq ptr %12, inttoptr (i64 1073881088 to ptr)
  %. = select i1 %.not, ptr inttoptr (i64 1073881344 to ptr), ptr null
  store ptr %., ptr %2, align 8, !tbaa !16
  br i1 %.not, label %17, label %13

13:                                               ; preds = %9
  %14 = getelementptr inbounds i8, ptr %0, i64 100
  %15 = load volatile i32, ptr %14, align 4, !tbaa !14
  %16 = or i32 %15, 32
  store volatile i32 %16, ptr %14, align 4, !tbaa !14
  br label %.sink.split

17:                                               ; preds = %9
  %18 = tail call i32 @HAL_GetTick() #4
  %19 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %20 = load ptr, ptr %0, align 8, !tbaa !16
  %21 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %20)
  %22 = icmp eq i32 %21, 1
  %23 = icmp eq i32 %19, 1
  %24 = select i1 %22, i1 true, i1 %23
  br i1 %24, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %17, %38
  %25 = tail call i32 @HAL_GetTick() #4
  %26 = sub i32 %25, %18
  %27 = icmp ugt i32 %26, 5
  br i1 %27, label %28, label %38

28:                                               ; preds = %.lr.ph
  %29 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %.)
  %30 = load ptr, ptr %0, align 8, !tbaa !16
  %31 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %30)
  %32 = icmp eq i32 %31, 1
  %33 = icmp eq i32 %29, 1
  %or.cond = select i1 %32, i1 true, i1 %33
  br i1 %or.cond, label %34, label %38

34:                                               ; preds = %28
  %35 = getelementptr inbounds i8, ptr %0, i64 100
  %36 = load volatile i32, ptr %35, align 4, !tbaa !14
  %37 = or i32 %36, 16
  store volatile i32 %37, ptr %35, align 4, !tbaa !14
  br label %.sink.split

38:                                               ; preds = %28, %.lr.ph
  %39 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %.)
  %40 = load ptr, ptr %0, align 8, !tbaa !16
  %41 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %40)
  %42 = icmp eq i32 %41, 1
  %43 = icmp eq i32 %39, 1
  %44 = select i1 %42, i1 true, i1 %43
  br i1 %44, label %.lr.ph, label %._crit_edge, !llvm.loop !17

._crit_edge:                                      ; preds = %38, %17
  %45 = getelementptr inbounds i8, ptr %0, i64 88
  %46 = load ptr, ptr %45, align 8, !tbaa !19
  %47 = tail call i32 @HAL_DMA_Abort(ptr noundef %46) #4
  %48 = icmp eq i32 %47, 1
  br i1 %48, label %.thread, label %56

.thread:                                          ; preds = %._crit_edge
  %49 = getelementptr inbounds i8, ptr %0, i64 100
  %50 = load volatile i32, ptr %49, align 4, !tbaa !14
  %51 = or i32 %50, 64
  store volatile i32 %51, ptr %49, align 4, !tbaa !14
  %52 = load ptr, ptr %0, align 8, !tbaa !16
  %53 = getelementptr inbounds i8, ptr %52, i64 4
  %54 = load volatile i32, ptr %53, align 4, !tbaa !20
  %55 = and i32 %54, -17
  store volatile i32 %55, ptr %53, align 4, !tbaa !20
  br label %64

56:                                               ; preds = %._crit_edge
  %57 = load ptr, ptr %0, align 8, !tbaa !16
  %58 = getelementptr inbounds i8, ptr %57, i64 4
  %59 = load volatile i32, ptr %58, align 4, !tbaa !20
  %60 = and i32 %59, -17
  store volatile i32 %60, ptr %58, align 4, !tbaa !20
  %61 = icmp eq i32 %47, 0
  br i1 %61, label %62, label %64

62:                                               ; preds = %56
  %63 = call i32 @ADC_Disable(ptr noundef nonnull %2) #4
  br label %66

64:                                               ; preds = %.thread, %56
  %65 = tail call i32 @ADC_Disable(ptr noundef nonnull %0) #4
  br label %66

66:                                               ; preds = %62, %64
  %.sink = phi ptr [ %0, %62 ], [ %2, %64 ]
  %67 = call i32 @ADC_Disable(ptr noundef nonnull %.sink) #4
  %68 = getelementptr inbounds i8, ptr %0, i64 100
  %69 = load volatile i32, ptr %68, align 4, !tbaa !14
  %70 = and i32 %69, -4354
  %71 = or disjoint i32 %70, 1
  store volatile i32 %71, ptr %68, align 4, !tbaa !14
  br label %.sink.split

.sink.split:                                      ; preds = %66, %6, %13, %34
  %.0.ph = phi i32 [ 1, %34 ], [ 1, %13 ], [ %47, %66 ], [ %7, %6 ]
  store i32 0, ptr %3, align 8, !tbaa !5
  br label %72

72:                                               ; preds = %.sink.split, %1
  %.0 = phi i32 [ 2, %1 ], [ %.0.ph, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 120, ptr nonnull %2) #4
  ret i32 %.0
}

declare i32 @HAL_DMA_Abort(ptr noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 100}
!15 = !{!6, !11, i64 104}
!16 = !{!6, !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!6, !7, i64 88}
!20 = !{!21, !11, i64 4}
!21 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass