; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/periph/adc/stm32 (adc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.adc_t = type { %struct.ADC_HandleTypeDef, %struct.dma_t, [16 x %struct.adc_channel_t], i32, %struct.adc_private_t }
%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.dma_t = type { %struct.__DMA_HandleTypeDef, i32, %struct.dma_private_t }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_private_t = type { i32 }
%struct.adc_channel_t = type { i32, %struct.ADC_ChannelConfTypeDef }
%struct.ADC_ChannelConfTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.adc_private_t = type { i32, [16 x i16], [16 x float], [16 x float], [16 x float], ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @adc_dma_handler(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #3
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  store ptr %6, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #3
  store i64 0, ptr %4, align 8, !tbaa !9
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.adc_t, ptr %7, i32 0, i32 1
  %9 = getelementptr inbounds %struct.dma_t, ptr %8, i32 0, i32 0
  call void @HAL_DMA_IRQHandler(ptr noundef %9)
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.adc_t, ptr %10, i32 0, i32 4
  %12 = getelementptr inbounds %struct.adc_private_t, ptr %11, i32 0, i32 6
  %13 = load ptr, ptr %12, align 8, !tbaa !11
  %14 = call i64 @xQueueReceiveFromISR(ptr noundef %13, ptr noundef null, ptr noundef %4)
  %15 = icmp ne i64 %14, 0
  br i1 %15, label %16, label %109

16:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !23
  br label %17

17:                                               ; preds = %100, %16
  %18 = load i32, ptr %5, align 4, !tbaa !23
  %19 = icmp slt i32 %18, 16
  br i1 %19, label %21, label %20

20:                                               ; preds = %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %103

21:                                               ; preds = %17
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.adc_t, ptr %22, i32 0, i32 4
  %24 = getelementptr inbounds %struct.adc_private_t, ptr %23, i32 0, i32 1
  %25 = load i32, ptr %5, align 4, !tbaa !23
  %26 = sext i32 %25 to i64
  %27 = getelementptr inbounds [16 x i16], ptr %24, i64 0, i64 %26
  %28 = load i16, ptr %27, align 2, !tbaa !24
  %29 = uitofp i16 %28 to float
  %30 = fdiv float %29, 6.553500e+04
  %31 = fpext float %30 to double
  %32 = fmul double %31, 3.300000e+00
  %33 = fptrunc double %32 to float
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.adc_t, ptr %34, i32 0, i32 4
  %36 = getelementptr inbounds %struct.adc_private_t, ptr %35, i32 0, i32 2
  %37 = load i32, ptr %5, align 4, !tbaa !23
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds [16 x float], ptr %36, i64 0, i64 %38
  store float %33, ptr %39, align 4, !tbaa !26
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.adc_t, ptr %40, i32 0, i32 4
  %42 = getelementptr inbounds %struct.adc_private_t, ptr %41, i32 0, i32 2
  %43 = load i32, ptr %5, align 4, !tbaa !23
  %44 = sext i32 %43 to i64
  %45 = getelementptr inbounds [16 x float], ptr %42, i64 0, i64 %44
  %46 = load float, ptr %45, align 4, !tbaa !26
  %47 = load ptr, ptr %3, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.adc_t, ptr %47, i32 0, i32 4
  %49 = getelementptr inbounds %struct.adc_private_t, ptr %48, i32 0, i32 3
  %50 = load i32, ptr %5, align 4, !tbaa !23
  %51 = sext i32 %50 to i64
  %52 = getelementptr inbounds [16 x float], ptr %49, i64 0, i64 %51
  %53 = load float, ptr %52, align 4, !tbaa !26
  %54 = fcmp ogt float %46, %53
  br i1 %54, label %55, label %69

55:                                               ; preds = %21
  %56 = load ptr, ptr %3, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.adc_t, ptr %56, i32 0, i32 4
  %58 = getelementptr inbounds %struct.adc_private_t, ptr %57, i32 0, i32 2
  %59 = load i32, ptr %5, align 4, !tbaa !23
  %60 = sext i32 %59 to i64
  %61 = getelementptr inbounds [16 x float], ptr %58, i64 0, i64 %60
  %62 = load float, ptr %61, align 4, !tbaa !26
  %63 = load ptr, ptr %3, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.adc_t, ptr %63, i32 0, i32 4
  %65 = getelementptr inbounds %struct.adc_private_t, ptr %64, i32 0, i32 3
  %66 = load i32, ptr %5, align 4, !tbaa !23
  %67 = sext i32 %66 to i64
  %68 = getelementptr inbounds [16 x float], ptr %65, i64 0, i64 %67
  store float %62, ptr %68, align 4, !tbaa !26
  br label %69

69:                                               ; preds = %55, %21
  %70 = load ptr, ptr %3, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.adc_t, ptr %70, i32 0, i32 4
  %72 = getelementptr inbounds %struct.adc_private_t, ptr %71, i32 0, i32 2
  %73 = load i32, ptr %5, align 4, !tbaa !23
  %74 = sext i32 %73 to i64
  %75 = getelementptr inbounds [16 x float], ptr %72, i64 0, i64 %74
  %76 = load float, ptr %75, align 4, !tbaa !26
  %77 = load ptr, ptr %3, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.adc_t, ptr %77, i32 0, i32 4
  %79 = getelementptr inbounds %struct.adc_private_t, ptr %78, i32 0, i32 4
  %80 = load i32, ptr %5, align 4, !tbaa !23
  %81 = sext i32 %80 to i64
  %82 = getelementptr inbounds [16 x float], ptr %79, i64 0, i64 %81
  %83 = load float, ptr %82, align 4, !tbaa !26
  %84 = fcmp olt float %76, %83
  br i1 %84, label %85, label %99

85:                                               ; preds = %69
  %86 = load ptr, ptr %3, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.adc_t, ptr %86, i32 0, i32 4
  %88 = getelementptr inbounds %struct.adc_private_t, ptr %87, i32 0, i32 2
  %89 = load i32, ptr %5, align 4, !tbaa !23
  %90 = sext i32 %89 to i64
  %91 = getelementptr inbounds [16 x float], ptr %88, i64 0, i64 %90
  %92 = load float, ptr %91, align 4, !tbaa !26
  %93 = load ptr, ptr %3, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.adc_t, ptr %93, i32 0, i32 4
  %95 = getelementptr inbounds %struct.adc_private_t, ptr %94, i32 0, i32 4
  %96 = load i32, ptr %5, align 4, !tbaa !23
  %97 = sext i32 %96 to i64
  %98 = getelementptr inbounds [16 x float], ptr %95, i64 0, i64 %97
  store float %92, ptr %98, align 4, !tbaa !26
  br label %99

99:                                               ; preds = %85, %69
  br label %100

100:                                              ; preds = %99
  %101 = load i32, ptr %5, align 4, !tbaa !23
  %102 = add nsw i32 %101, 1
  store i32 %102, ptr %5, align 4, !tbaa !23
  br label %17, !llvm.loop !28

103:                                              ; preds = %20
  %104 = load ptr, ptr %3, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.adc_t, ptr %104, i32 0, i32 4
  %106 = getelementptr inbounds %struct.adc_private_t, ptr %105, i32 0, i32 6
  %107 = load ptr, ptr %106, align 8, !tbaa !11
  %108 = call i64 @xQueueGiveFromISR(ptr noundef %107, ptr noundef %4)
  br label %109

109:                                              ; preds = %103, %1
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.adc_t, ptr %110, i32 0, i32 4
  %112 = getelementptr inbounds %struct.adc_private_t, ptr %111, i32 0, i32 5
  %113 = load ptr, ptr %112, align 8, !tbaa !30
  %114 = call i64 @xQueueGiveFromISR(ptr noundef %113, ptr noundef %4)
  %115 = load i64, ptr %4, align 8, !tbaa !9
  %116 = icmp eq i64 %115, 1
  br i1 %116, label %117, label %122

117:                                              ; preds = %109
  %118 = load i64, ptr %4, align 8, !tbaa !9
  %119 = icmp ne i64 %118, 0
  br i1 %119, label %120, label %121

120:                                              ; preds = %117
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !23
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !31
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !32
  br label %121

121:                                              ; preds = %120, %117
  br label %122

122:                                              ; preds = %121, %109
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @HAL_DMA_IRQHandler(ptr noundef) #2

declare i64 @xQueueReceiveFromISR(ptr noundef, ptr noundef, ptr noundef) #2

declare i64 @xQueueGiveFromISR(ptr noundef, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 1136}
!12 = !{!"", !13, i64 0, !18, i64 120, !7, i64 312, !15, i64 888, !22, i64 896}
!13 = !{!"", !6, i64 0, !14, i64 8, !6, i64 88, !15, i64 96, !15, i64 100, !15, i64 104, !17, i64 108}
!14 = !{!"", !15, i64 0, !15, i64 4, !15, i64 8, !15, i64 12, !15, i64 16, !15, i64 20, !15, i64 24, !15, i64 28, !15, i64 32, !15, i64 36, !15, i64 40, !15, i64 44, !15, i64 48, !15, i64 52, !15, i64 56, !16, i64 60}
!15 = !{!"int", !7, i64 0}
!16 = !{!"", !15, i64 0, !15, i64 4, !15, i64 8, !15, i64 12}
!17 = !{!"", !15, i64 0, !15, i64 4}
!18 = !{!"", !19, i64 0, !15, i64 184, !21, i64 188}
!19 = !{!"__DMA_HandleTypeDef", !6, i64 0, !20, i64 8, !15, i64 56, !15, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !15, i64 120, !15, i64 124, !15, i64 128, !6, i64 136, !6, i64 144, !15, i64 152, !6, i64 160, !6, i64 168, !15, i64 176}
!20 = !{!"", !15, i64 0, !15, i64 4, !15, i64 8, !15, i64 12, !15, i64 16, !15, i64 20, !15, i64 24, !15, i64 28, !15, i64 32, !15, i64 36, !15, i64 40, !15, i64 44}
!21 = !{!"", !15, i64 0}
!22 = !{!"", !15, i64 0, !7, i64 4, !7, i64 36, !7, i64 100, !7, i64 164, !6, i64 232, !6, i64 240}
!23 = !{!15, !15, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"short", !7, i64 0}
!26 = !{!27, !27, i64 0}
!27 = !{!"float", !7, i64 0}
!28 = distinct !{!28, !29}
!29 = !{!"llvm.loop.mustprogress"}
!30 = !{!12, !6, i64 1128}
!31 = !{i64 2154026640}
!32 = !{i64 2154026710}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @adc_dma_handler(ptr noundef %0) local_unnamed_addr #1 {
  %2 = alloca i64, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  store i64 0, ptr %2, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 120
  tail call void @HAL_DMA_IRQHandler(ptr noundef nonnull %3) #3
  %4 = getelementptr inbounds i8, ptr %0, i64 1136
  %5 = load ptr, ptr %4, align 8, !tbaa !9
  %6 = call i64 @xQueueReceiveFromISR(ptr noundef %5, ptr noundef null, ptr noundef nonnull %2) #3
  %.not = icmp eq i64 %6, 0
  br i1 %.not, label %33, label %.preheader

.preheader:                                       ; preds = %1
  %7 = getelementptr inbounds i8, ptr %0, i64 900
  %8 = getelementptr inbounds i8, ptr %0, i64 932
  %9 = getelementptr inbounds i8, ptr %0, i64 996
  %10 = getelementptr inbounds i8, ptr %0, i64 1060
  br label %14

11:                                               ; preds = %32
  %12 = load ptr, ptr %4, align 8, !tbaa !9
  %13 = call i64 @xQueueGiveFromISR(ptr noundef %12, ptr noundef nonnull %2) #3
  br label %33

14:                                               ; preds = %.preheader, %32
  %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %32 ]
  %15 = getelementptr inbounds [16 x i16], ptr %7, i64 0, i64 %indvars.iv
  %16 = load i16, ptr %15, align 2, !tbaa !22
  %17 = uitofp i16 %16 to float
  %18 = fdiv float %17, 6.553500e+04
  %19 = fpext float %18 to double
  %20 = fmul double %19, 3.300000e+00
  %21 = fptrunc double %20 to float
  %22 = getelementptr inbounds [16 x float], ptr %8, i64 0, i64 %indvars.iv
  store float %21, ptr %22, align 4, !tbaa !24
  %23 = getelementptr inbounds [16 x float], ptr %9, i64 0, i64 %indvars.iv
  %24 = load float, ptr %23, align 4, !tbaa !24
  %25 = fcmp olt float %24, %21
  br i1 %25, label %26, label %27

26:                                               ; preds = %14
  store float %21, ptr %23, align 4, !tbaa !24
  br label %27

27:                                               ; preds = %26, %14
  %28 = getelementptr inbounds [16 x float], ptr %10, i64 0, i64 %indvars.iv
  %29 = load float, ptr %28, align 4, !tbaa !24
  %30 = fcmp ogt float %29, %21
  br i1 %30, label %31, label %32

31:                                               ; preds = %27
  store float %21, ptr %28, align 4, !tbaa !24
  br label %32

32:                                               ; preds = %27, %31
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 16
  br i1 %exitcond.not, label %11, label %14, !llvm.loop !26

33:                                               ; preds = %11, %1
  %34 = getelementptr inbounds i8, ptr %0, i64 1128
  %35 = load ptr, ptr %34, align 8, !tbaa !28
  %36 = call i64 @xQueueGiveFromISR(ptr noundef %35, ptr noundef nonnull %2) #3
  %37 = load i64, ptr %2, align 8
  %38 = icmp eq i64 %37, 1
  br i1 %38, label %39, label %40

39:                                               ; preds = %33
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !29
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !30
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !31
  br label %40

40:                                               ; preds = %39, %33
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @HAL_DMA_IRQHandler(ptr noundef) local_unnamed_addr #2

declare i64 @xQueueReceiveFromISR(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

declare i64 @xQueueGiveFromISR(ptr noundef, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 1136}
!10 = !{!"", !11, i64 0, !17, i64 120, !7, i64 312, !14, i64 888, !21, i64 896}
!11 = !{!"", !12, i64 0, !13, i64 8, !12, i64 88, !14, i64 96, !14, i64 100, !14, i64 104, !16, i64 108}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44, !14, i64 48, !14, i64 52, !14, i64 56, !15, i64 60}
!14 = !{!"int", !7, i64 0}
!15 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12}
!16 = !{!"", !14, i64 0, !14, i64 4}
!17 = !{!"", !18, i64 0, !14, i64 184, !20, i64 188}
!18 = !{!"__DMA_HandleTypeDef", !12, i64 0, !19, i64 8, !14, i64 56, !14, i64 60, !12, i64 64, !12, i64 72, !12, i64 80, !12, i64 88, !12, i64 96, !12, i64 104, !12, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !12, i64 136, !12, i64 144, !14, i64 152, !12, i64 160, !12, i64 168, !14, i64 176}
!19 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44}
!20 = !{!"", !14, i64 0}
!21 = !{!"", !14, i64 0, !7, i64 4, !7, i64 36, !7, i64 100, !7, i64 164, !12, i64 232, !12, i64 240}
!22 = !{!23, !23, i64 0}
!23 = !{!"short", !7, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"float", !7, i64 0}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!10, !12, i64 1128}
!29 = !{!14, !14, i64 0}
!30 = !{i64 2154026640}
!31 = !{i64 2154026710}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass