; LLVM IR from ritikbanger/Hacktoberfest2022-DSA :: 28. Codechef Problems/Nuttela-Path-Unit.ll (Z3lcaxxxPxRSt6vectorIS0_IxSaIxEESaIS2_EE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z3lcaxxxPxRSt6vectorIS0_IxSaIxEESaIS2_EE(i64 noundef %0, i64 noundef %1, i64 noundef %2, ptr noundef %3, ptr noundef nonnull align 8 dereferenceable(24) %4) #2 {
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store i64 %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !5
  store i64 %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !9
  store ptr %4, ptr %11, align 8, !tbaa !9
  %14 = load ptr, ptr %10, align 8, !tbaa !9
  %15 = load i64, ptr %7, align 8, !tbaa !5
  %16 = getelementptr inbounds i64, ptr %14, i64 %15
  %17 = load i64, ptr %16, align 8, !tbaa !5
  %18 = load ptr, ptr %10, align 8, !tbaa !9
  %19 = load i64, ptr %8, align 8, !tbaa !5
  %20 = getelementptr inbounds i64, ptr %18, i64 %19
  %21 = load i64, ptr %20, align 8, !tbaa !5
  %22 = icmp slt i64 %17, %21
  br i1 %22, label %23, label %24

23:                                               ; preds = %5
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 8 dereferenceable(8) %8) #4
  br label %24

24:                                               ; preds = %23, %5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %25 = load i64, ptr %9, align 8, !tbaa !5
  store i64 %25, ptr %12, align 8, !tbaa !5
  br label %26

26:                                               ; preds = %53, %24
  %27 = load i64, ptr %12, align 8, !tbaa !5
  %28 = icmp sge i64 %27, 0
  br i1 %28, label %30, label %29

29:                                               ; preds = %26
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  br label %56

30:                                               ; preds = %26
  %31 = load ptr, ptr %10, align 8, !tbaa !9
  %32 = load i64, ptr %7, align 8, !tbaa !5
  %33 = getelementptr inbounds i64, ptr %31, i64 %32
  %34 = load i64, ptr %33, align 8, !tbaa !5
  %35 = sitofp i64 %34 to double
  %36 = load i64, ptr %12, align 8, !tbaa !5
  %37 = call noundef double @_ZSt3powIixEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(i32 noundef 2, i64 noundef %36)
  %38 = fsub double %35, %37
  %39 = load ptr, ptr %10, align 8, !tbaa !9
  %40 = load i64, ptr %8, align 8, !tbaa !5
  %41 = getelementptr inbounds i64, ptr %39, i64 %40
  %42 = load i64, ptr %41, align 8, !tbaa !5
  %43 = sitofp i64 %42 to double
  %44 = fcmp oge double %38, %43
  br i1 %44, label %45, label %52

45:                                               ; preds = %30
  %46 = load ptr, ptr %11, align 8, !tbaa !9
  %47 = load i64, ptr %7, align 8, !tbaa !5
  %48 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %47) #4
  %49 = load i64, ptr %12, align 8, !tbaa !5
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %49) #4
  %51 = load i64, ptr %50, align 8, !tbaa !5
  store i64 %51, ptr %7, align 8, !tbaa !5
  br label %52

52:                                               ; preds = %45, %30
  br label %53

53:                                               ; preds = %52
  %54 = load i64, ptr %12, align 8, !tbaa !5
  %55 = add nsw i64 %54, -1
  store i64 %55, ptr %12, align 8, !tbaa !5
  br label %26, !llvm.loop !11

56:                                               ; preds = %29
  %57 = load i64, ptr %7, align 8, !tbaa !5
  %58 = load i64, ptr %8, align 8, !tbaa !5
  %59 = icmp eq i64 %57, %58
  br i1 %59, label %60, label %62

60:                                               ; preds = %56
  %61 = load i64, ptr %7, align 8, !tbaa !5
  store i64 %61, ptr %6, align 8
  br label %105

62:                                               ; preds = %56
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %63 = load i64, ptr %9, align 8, !tbaa !5
  store i64 %63, ptr %13, align 8, !tbaa !5
  br label %64

64:                                               ; preds = %96, %62
  %65 = load i64, ptr %13, align 8, !tbaa !5
  %66 = icmp sge i64 %65, 0
  br i1 %66, label %68, label %67

67:                                               ; preds = %64
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %99

68:                                               ; preds = %64
  %69 = load ptr, ptr %11, align 8, !tbaa !9
  %70 = load i64, ptr %7, align 8, !tbaa !5
  %71 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %69, i64 noundef %70) #4
  %72 = load i64, ptr %13, align 8, !tbaa !5
  %73 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %71, i64 noundef %72) #4
  %74 = load i64, ptr %73, align 8, !tbaa !5
  %75 = load ptr, ptr %11, align 8, !tbaa !9
  %76 = load i64, ptr %8, align 8, !tbaa !5
  %77 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %75, i64 noundef %76) #4
  %78 = load i64, ptr %13, align 8, !tbaa !5
  %79 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %77, i64 noundef %78) #4
  %80 = load i64, ptr %79, align 8, !tbaa !5
  %81 = icmp ne i64 %74, %80
  br i1 %81, label %82, label %95

82:                                               ; preds = %68
  %83 = load ptr, ptr %11, align 8, !tbaa !9
  %84 = load i64, ptr %7, align 8, !tbaa !5
  %85 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %83, i64 noundef %84) #4
  %86 = load i64, ptr %13, align 8, !tbaa !5
  %87 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %85, i64 noundef %86) #4
  %88 = load i64, ptr %87, align 8, !tbaa !5
  store i64 %88, ptr %7, align 8, !tbaa !5
  %89 = load ptr, ptr %11, align 8, !tbaa !9
  %90 = load i64, ptr %8, align 8, !tbaa !5
  %91 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %89, i64 noundef %90) #4
  %92 = load i64, ptr %13, align 8, !tbaa !5
  %93 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %91, i64 noundef %92) #4
  %94 = load i64, ptr %93, align 8, !tbaa !5
  store i64 %94, ptr %8, align 8, !tbaa !5
  br label %95

95:                                               ; preds = %82, %68
  br label %96

96:                                               ; preds = %95
  %97 = load i64, ptr %13, align 8, !tbaa !5
  %98 = add nsw i64 %97, -1
  store i64 %98, ptr %13, align 8, !tbaa !5
  br label %64, !llvm.loop !13

99:                                               ; preds = %67
  %100 = load ptr, ptr %11, align 8, !tbaa !9
  %101 = load i64, ptr %7, align 8, !tbaa !5
  %102 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %100, i64 noundef %101) #4
  %103 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %102, i64 noundef 0) #4
  %104 = load i64, ptr %103, align 8, !tbaa !5
  store i64 %104, ptr %6, align 8
  br label %105

105:                                              ; preds = %99, %60
  %106 = load i64, ptr %6, align 8
  ret i64 %106
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef double @_ZSt3powIixEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(i32 noundef, i64 noundef) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z3lcaxxxPxRSt6vectorIS0_IxSaIxEESaIS2_EE(i64 noundef %0, i64 noundef %1, i64 noundef %2, ptr nocapture noundef readonly %3, ptr noundef nonnull align 8 dereferenceable(24) %4) local_unnamed_addr #0 {
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  store i64 %0, ptr %6, align 8, !tbaa !5
  store i64 %1, ptr %7, align 8, !tbaa !5
  %8 = getelementptr inbounds i64, ptr %3, i64 %0
  %9 = load i64, ptr %8, align 8, !tbaa !5
  %10 = getelementptr inbounds i64, ptr %3, i64 %1
  %11 = load i64, ptr %10, align 8, !tbaa !5
  %12 = icmp slt i64 %9, %11
  br i1 %12, label %13, label %14

13:                                               ; preds = %5
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %7) #2
  br label %14

14:                                               ; preds = %13, %5
  %15 = icmp sgt i64 %2, -1
  br i1 %15, label %.lr.ph, label %._crit_edge.thread

._crit_edge:                                      ; preds = %38
  %16 = load i64, ptr %6, align 8, !tbaa !5
  %17 = load i64, ptr %7, align 8, !tbaa !5
  %18 = icmp eq i64 %16, %17
  br i1 %18, label %65, label %.preheader

._crit_edge.thread:                               ; preds = %14
  %19 = load i64, ptr %6, align 8, !tbaa !5
  %20 = load i64, ptr %7, align 8, !tbaa !5
  %21 = icmp eq i64 %19, %20
  br i1 %21, label %65, label %._crit_edge28

.preheader:                                       ; preds = %._crit_edge
  br i1 %15, label %.lr.ph27, label %._crit_edge28

.lr.ph:                                           ; preds = %14, %38
  %.02225 = phi i64 [ %39, %38 ], [ %2, %14 ]
  %22 = load i64, ptr %6, align 8, !tbaa !5
  %23 = getelementptr inbounds i64, ptr %3, i64 %22
  %24 = load i64, ptr %23, align 8, !tbaa !5
  %25 = sitofp i64 %24 to double
  %26 = call noundef double @_ZSt3powIixEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(i32 noundef 2, i64 noundef %.02225)
  %27 = fsub double %25, %26
  %28 = load i64, ptr %7, align 8, !tbaa !5
  %29 = getelementptr inbounds i64, ptr %3, i64 %28
  %30 = load i64, ptr %29, align 8, !tbaa !5
  %31 = sitofp i64 %30 to double
  %32 = fcmp ult double %27, %31
  br i1 %32, label %38, label %33

33:                                               ; preds = %.lr.ph
  %34 = load i64, ptr %6, align 8, !tbaa !5
  %35 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %34) #2
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %.02225) #2
  %37 = load i64, ptr %36, align 8, !tbaa !5
  store i64 %37, ptr %6, align 8, !tbaa !5
  br label %38

38:                                               ; preds = %.lr.ph, %33
  %39 = add nsw i64 %.02225, -1
  %40 = icmp sgt i64 %.02225, 0
  br i1 %40, label %.lr.ph, label %._crit_edge, !llvm.loop !9

._crit_edge28.loopexit:                           ; preds = %62
  %.pre = load i64, ptr %6, align 8, !tbaa !5
  br label %._crit_edge28

._crit_edge28:                                    ; preds = %._crit_edge.thread, %._crit_edge28.loopexit, %.preheader
  %41 = phi i64 [ %.pre, %._crit_edge28.loopexit ], [ %16, %.preheader ], [ %19, %._crit_edge.thread ]
  %42 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %41) #2
  %43 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef 0) #2
  %44 = load i64, ptr %43, align 8, !tbaa !5
  br label %65

.lr.ph27:                                         ; preds = %.preheader, %62
  %.026 = phi i64 [ %63, %62 ], [ %2, %.preheader ]
  %45 = load i64, ptr %6, align 8, !tbaa !5
  %46 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %45) #2
  %47 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %.026) #2
  %48 = load i64, ptr %47, align 8, !tbaa !5
  %49 = load i64, ptr %7, align 8, !tbaa !5
  %50 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %49) #2
  %51 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %.026) #2
  %52 = load i64, ptr %51, align 8, !tbaa !5
  %.not = icmp eq i64 %48, %52
  br i1 %.not, label %62, label %53

53:                                               ; preds = %.lr.ph27
  %54 = load i64, ptr %6, align 8, !tbaa !5
  %55 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %54) #2
  %56 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %55, i64 noundef %.026) #2
  %57 = load i64, ptr %56, align 8, !tbaa !5
  store i64 %57, ptr %6, align 8, !tbaa !5
  %58 = load i64, ptr %7, align 8, !tbaa !5
  %59 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %58) #2
  %60 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %59, i64 noundef %.026) #2
  %61 = load i64, ptr %60, align 8, !tbaa !5
  store i64 %61, ptr %7, align 8, !tbaa !5
  br label %62

62:                                               ; preds = %.lr.ph27, %53
  %63 = add nsw i64 %.026, -1
  %64 = icmp sgt i64 %.026, 0
  br i1 %64, label %.lr.ph27, label %._crit_edge28.loopexit, !llvm.loop !11

65:                                               ; preds = %._crit_edge.thread, %._crit_edge, %._crit_edge28
  %.023 = phi i64 [ %44, %._crit_edge28 ], [ %16, %._crit_edge ], [ %19, %._crit_edge.thread ]
  ret i64 %.023
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef double @_ZSt3powIixEN9__gnu_cxx9__promoteIDTplcvNS1_IT_Xsr3std12__is_integerIS2_EE7__valueEE6__typeELi0EcvNS1_IT0_Xsr3std12__is_integerIS5_EE7__valueEE6__typeELi0EEXsr3std12__is_integerIS8_EE7__valueEE6__typeES2_S5_(i32 noundef, i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass