; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim_ex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_HallSensor_InitTypeDef = type { i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_HallSensor_Init(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca %struct.TIM_OC_InitTypeDef, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 28, ptr %6) #3
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %2
  store i32 1, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %139

11:                                               ; preds = %2
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 5
  %14 = load volatile i32, ptr %13, align 4, !tbaa !9
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %16, label %20

16:                                               ; preds = %11
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 4
  store i32 0, ptr %18, align 8, !tbaa !13
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  call void @HAL_TIMEx_HallSensor_MspInit(ptr noundef %19)
  br label %20

20:                                               ; preds = %16, %11
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %21, i32 0, i32 5
  store volatile i32 2, ptr %22, align 4, !tbaa !9
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %23, i32 0, i32 0
  %25 = load ptr, ptr %24, align 8, !tbaa !14
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %26, i32 0, i32 1
  call void @TIM_Base_SetConfig(ptr noundef %25, ptr noundef %27)
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 0
  %30 = load ptr, ptr %29, align 8, !tbaa !14
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.TIM_HallSensor_InitTypeDef, ptr %31, i32 0, i32 0
  %33 = load i32, ptr %32, align 4, !tbaa !15
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HallSensor_InitTypeDef, ptr %34, i32 0, i32 2
  %36 = load i32, ptr %35, align 4, !tbaa !17
  call void @TIM_TI1_SetConfig(ptr noundef %30, i32 noundef %33, i32 noundef 3, i32 noundef %36)
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !14
  %40 = getelementptr inbounds %struct.TIM_TypeDef, ptr %39, i32 0, i32 6
  %41 = load volatile i32, ptr %40, align 4, !tbaa !18
  %42 = zext i32 %41 to i64
  %43 = and i64 %42, -13
  %44 = trunc i64 %43 to i32
  store volatile i32 %44, ptr %40, align 4, !tbaa !18
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HallSensor_InitTypeDef, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !20
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %48, i32 0, i32 0
  %50 = load ptr, ptr %49, align 8, !tbaa !14
  %51 = getelementptr inbounds %struct.TIM_TypeDef, ptr %50, i32 0, i32 6
  %52 = load volatile i32, ptr %51, align 4, !tbaa !18
  %53 = or i32 %52, %47
  store volatile i32 %53, ptr %51, align 4, !tbaa !18
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !14
  %57 = getelementptr inbounds %struct.TIM_TypeDef, ptr %56, i32 0, i32 1
  %58 = load volatile i32, ptr %57, align 4, !tbaa !21
  %59 = zext i32 %58 to i64
  %60 = or i64 %59, 128
  %61 = trunc i64 %60 to i32
  store volatile i32 %61, ptr %57, align 4, !tbaa !21
  %62 = load ptr, ptr %4, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !14
  %65 = getelementptr inbounds %struct.TIM_TypeDef, ptr %64, i32 0, i32 2
  %66 = load volatile i32, ptr %65, align 4, !tbaa !22
  %67 = zext i32 %66 to i64
  %68 = and i64 %67, -3145841
  %69 = trunc i64 %68 to i32
  store volatile i32 %69, ptr %65, align 4, !tbaa !22
  %70 = load ptr, ptr %4, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %70, i32 0, i32 0
  %72 = load ptr, ptr %71, align 8, !tbaa !14
  %73 = getelementptr inbounds %struct.TIM_TypeDef, ptr %72, i32 0, i32 2
  %74 = load volatile i32, ptr %73, align 4, !tbaa !22
  %75 = zext i32 %74 to i64
  %76 = or i64 %75, 64
  %77 = trunc i64 %76 to i32
  store volatile i32 %77, ptr %73, align 4, !tbaa !22
  %78 = load ptr, ptr %4, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !14
  %81 = getelementptr inbounds %struct.TIM_TypeDef, ptr %80, i32 0, i32 2
  %82 = load volatile i32, ptr %81, align 4, !tbaa !22
  %83 = zext i32 %82 to i64
  %84 = and i64 %83, -65544
  %85 = trunc i64 %84 to i32
  store volatile i32 %85, ptr %81, align 4, !tbaa !22
  %86 = load ptr, ptr %4, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %86, i32 0, i32 0
  %88 = load ptr, ptr %87, align 8, !tbaa !14
  %89 = getelementptr inbounds %struct.TIM_TypeDef, ptr %88, i32 0, i32 2
  %90 = load volatile i32, ptr %89, align 4, !tbaa !22
  %91 = zext i32 %90 to i64
  %92 = or i64 %91, 4
  %93 = trunc i64 %92 to i32
  store volatile i32 %93, ptr %89, align 4, !tbaa !22
  %94 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 4
  store i32 0, ptr %94, align 4, !tbaa !23
  %95 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 5
  store i32 0, ptr %95, align 4, !tbaa !25
  %96 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 0
  store i32 112, ptr %96, align 4, !tbaa !26
  %97 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 6
  store i32 0, ptr %97, align 4, !tbaa !27
  %98 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 3
  store i32 0, ptr %98, align 4, !tbaa !28
  %99 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 2
  store i32 0, ptr %99, align 4, !tbaa !29
  %100 = load ptr, ptr %5, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.TIM_HallSensor_InitTypeDef, ptr %100, i32 0, i32 3
  %102 = load i32, ptr %101, align 4, !tbaa !30
  %103 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %6, i32 0, i32 1
  store i32 %102, ptr %103, align 4, !tbaa !31
  %104 = load ptr, ptr %4, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %104, i32 0, i32 0
  %106 = load ptr, ptr %105, align 8, !tbaa !14
  call void @TIM_OC2_SetConfig(ptr noundef %106, ptr noundef %6)
  %107 = load ptr, ptr %4, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %107, i32 0, i32 0
  %109 = load ptr, ptr %108, align 8, !tbaa !14
  %110 = getelementptr inbounds %struct.TIM_TypeDef, ptr %109, i32 0, i32 1
  %111 = load volatile i32, ptr %110, align 4, !tbaa !21
  %112 = zext i32 %111 to i64
  %113 = and i64 %112, -113
  %114 = trunc i64 %113 to i32
  store volatile i32 %114, ptr %110, align 4, !tbaa !21
  %115 = load ptr, ptr %4, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !14
  %118 = getelementptr inbounds %struct.TIM_TypeDef, ptr %117, i32 0, i32 1
  %119 = load volatile i32, ptr %118, align 4, !tbaa !21
  %120 = zext i32 %119 to i64
  %121 = or i64 %120, 80
  %122 = trunc i64 %121 to i32
  store volatile i32 %122, ptr %118, align 4, !tbaa !21
  %123 = load ptr, ptr %4, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %123, i32 0, i32 8
  store volatile i32 1, ptr %124, align 8, !tbaa !32
  %125 = load ptr, ptr %4, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %125, i32 0, i32 6
  %127 = getelementptr inbounds [6 x i32], ptr %126, i64 0, i64 0
  store volatile i32 1, ptr %127, align 8, !tbaa !33
  %128 = load ptr, ptr %4, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %128, i32 0, i32 6
  %130 = getelementptr inbounds [6 x i32], ptr %129, i64 0, i64 1
  store volatile i32 1, ptr %130, align 4, !tbaa !33
  %131 = load ptr, ptr %4, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %131, i32 0, i32 7
  %133 = getelementptr inbounds [4 x i32], ptr %132, i64 0, i64 0
  store volatile i32 1, ptr %133, align 8, !tbaa !33
  %134 = load ptr, ptr %4, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %134, i32 0, i32 7
  %136 = getelementptr inbounds [4 x i32], ptr %135, i64 0, i64 1
  store volatile i32 1, ptr %136, align 4, !tbaa !33
  %137 = load ptr, ptr %4, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %137, i32 0, i32 5
  store volatile i32 1, ptr %138, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %139

139:                                              ; preds = %20, %10
  call void @llvm.lifetime.end.p0(i64 28, ptr %6) #3
  %140 = load i32, ptr %3, align 4
  ret i32 %140
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_TIMEx_HallSensor_MspInit(ptr noundef) #0

declare void @TIM_Base_SetConfig(ptr noundef, ptr noundef) #2

declare void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 100}
!10 = !{!"", !6, i64 0, !11, i64 8, !12, i64 32, !7, i64 40, !12, i64 96, !12, i64 100, !7, i64 104, !7, i64 128, !12, i64 144}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 96}
!14 = !{!10, !6, i64 0}
!15 = !{!16, !12, i64 0}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!17 = !{!16, !12, i64 8}
!18 = !{!19, !12, i64 24}
!19 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!20 = !{!16, !12, i64 4}
!21 = !{!19, !12, i64 4}
!22 = !{!19, !12, i64 8}
!23 = !{!24, !12, i64 16}
!24 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24}
!25 = !{!24, !12, i64 20}
!26 = !{!24, !12, i64 0}
!27 = !{!24, !12, i64 24}
!28 = !{!24, !12, i64 12}
!29 = !{!24, !12, i64 8}
!30 = !{!16, !12, i64 12}
!31 = !{!24, !12, i64 4}
!32 = !{!10, !12, i64 144}
!33 = !{!12, !12, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_TIMEx_HallSensor_Init(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = alloca %struct.TIM_OC_InitTypeDef, align 4
  call void @llvm.lifetime.start.p0(i64 28, ptr nonnull %3) #3
  %4 = icmp eq ptr %0, null
  br i1 %4, label %54, label %5

5:                                                ; preds = %2
  %6 = getelementptr inbounds i8, ptr %0, i64 100
  %7 = load volatile i32, ptr %6, align 4, !tbaa !5
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %11

9:                                                ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 0, ptr %10, align 8, !tbaa !12
  tail call void @HAL_TIMEx_HallSensor_MspInit(ptr noundef nonnull %0)
  br label %11

11:                                               ; preds = %9, %5
  store volatile i32 2, ptr %6, align 4, !tbaa !5
  %12 = load ptr, ptr %0, align 8, !tbaa !13
  %13 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @TIM_Base_SetConfig(ptr noundef %12, ptr noundef nonnull %13) #3
  %14 = load ptr, ptr %0, align 8, !tbaa !13
  %15 = load i32, ptr %1, align 4, !tbaa !14
  %16 = getelementptr inbounds i8, ptr %1, i64 8
  %17 = load i32, ptr %16, align 4, !tbaa !16
  tail call void @TIM_TI1_SetConfig(ptr noundef %14, i32 noundef %15, i32 noundef 3, i32 noundef %17) #3
  %18 = load ptr, ptr %0, align 8, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %18, i64 24
  %20 = load volatile i32, ptr %19, align 4, !tbaa !17
  %21 = and i32 %20, -13
  store volatile i32 %21, ptr %19, align 4, !tbaa !17
  %22 = getelementptr inbounds i8, ptr %1, i64 4
  %23 = load i32, ptr %22, align 4, !tbaa !19
  %24 = load volatile i32, ptr %19, align 4, !tbaa !17
  %25 = or i32 %24, %23
  store volatile i32 %25, ptr %19, align 4, !tbaa !17
  %26 = getelementptr inbounds i8, ptr %18, i64 4
  %27 = load volatile i32, ptr %26, align 4, !tbaa !20
  %28 = or i32 %27, 128
  store volatile i32 %28, ptr %26, align 4, !tbaa !20
  %29 = getelementptr inbounds i8, ptr %18, i64 8
  %30 = load volatile i32, ptr %29, align 4, !tbaa !21
  %31 = and i32 %30, -3145841
  store volatile i32 %31, ptr %29, align 4, !tbaa !21
  %32 = load volatile i32, ptr %29, align 4, !tbaa !21
  %33 = or i32 %32, 64
  store volatile i32 %33, ptr %29, align 4, !tbaa !21
  %34 = load volatile i32, ptr %29, align 4, !tbaa !21
  %35 = and i32 %34, -65544
  store volatile i32 %35, ptr %29, align 4, !tbaa !21
  %36 = load volatile i32, ptr %29, align 4, !tbaa !21
  %37 = or i32 %36, 4
  store volatile i32 %37, ptr %29, align 4, !tbaa !21
  store i32 112, ptr %3, align 4, !tbaa !22
  %38 = getelementptr inbounds i8, ptr %3, i64 24
  store i32 0, ptr %38, align 4, !tbaa !24
  %39 = getelementptr inbounds i8, ptr %3, i64 8
  store <4 x i32> zeroinitializer, ptr %39, align 4, !tbaa !25
  %40 = getelementptr inbounds i8, ptr %1, i64 12
  %41 = load i32, ptr %40, align 4, !tbaa !26
  %42 = getelementptr inbounds i8, ptr %3, i64 4
  store i32 %41, ptr %42, align 4, !tbaa !27
  call void @TIM_OC2_SetConfig(ptr noundef %18, ptr noundef nonnull %3) #3
  %43 = load ptr, ptr %0, align 8, !tbaa !13
  %44 = getelementptr inbounds i8, ptr %43, i64 4
  %45 = load volatile i32, ptr %44, align 4, !tbaa !20
  %46 = and i32 %45, -113
  store volatile i32 %46, ptr %44, align 4, !tbaa !20
  %47 = load volatile i32, ptr %44, align 4, !tbaa !20
  %48 = or i32 %47, 80
  store volatile i32 %48, ptr %44, align 4, !tbaa !20
  %49 = getelementptr inbounds i8, ptr %0, i64 144
  store volatile i32 1, ptr %49, align 8, !tbaa !28
  %50 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 1, ptr %50, align 8, !tbaa !25
  %51 = getelementptr inbounds i8, ptr %0, i64 108
  store volatile i32 1, ptr %51, align 4, !tbaa !25
  %52 = getelementptr inbounds i8, ptr %0, i64 128
  store volatile i32 1, ptr %52, align 8, !tbaa !25
  %53 = getelementptr inbounds i8, ptr %0, i64 132
  store volatile i32 1, ptr %53, align 4, !tbaa !25
  store volatile i32 1, ptr %6, align 4, !tbaa !5
  br label %54

54:                                               ; preds = %2, %11
  %.0 = phi i32 [ 0, %11 ], [ 1, %2 ]
  call void @llvm.lifetime.end.p0(i64 28, ptr nonnull %3) #3
  ret i32 %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_TIMEx_HallSensor_MspInit(ptr noundef) local_unnamed_addr #0

declare void @TIM_Base_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

declare void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 100}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 96}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 0}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!16 = !{!15, !11, i64 8}
!17 = !{!18, !11, i64 24}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!19 = !{!15, !11, i64 4}
!20 = !{!18, !11, i64 4}
!21 = !{!18, !11, i64 8}
!22 = !{!23, !11, i64 0}
!23 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!24 = !{!23, !11, i64 24}
!25 = !{!11, !11, i64 0}
!26 = !{!15, !11, i64 12}
!27 = !{!23, !11, i64 4}
!28 = !{!6, !11, i64 144}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass