; LLVM IR from Leet-Us-Code/DSA-A-Z-Practice :: Sid's Levels/Level - 2/Arrays/MergeWithoutExtraSpace.ll (Z5mergePiS_ii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7nextGapi(i32 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5mergePiS_ii(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %12 = load i32, ptr %7, align 4, !tbaa !9
  %13 = load i32, ptr %8, align 4, !tbaa !9
  %14 = add nsw i32 %12, %13
  store i32 %14, ptr %11, align 4, !tbaa !9
  %15 = load i32, ptr %11, align 4, !tbaa !9
  %16 = call noundef i32 @_Z7nextGapi(i32 noundef %15)
  store i32 %16, ptr %11, align 4, !tbaa !9
  br label %17

17:                                               ; preds = %146, %4
  %18 = load i32, ptr %11, align 4, !tbaa !9
  %19 = icmp sgt i32 %18, 0
  br i1 %19, label %20, label %149

20:                                               ; preds = %17
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %53, %20
  %22 = load i32, ptr %9, align 4, !tbaa !9
  %23 = load i32, ptr %11, align 4, !tbaa !9
  %24 = add nsw i32 %22, %23
  %25 = load i32, ptr %7, align 4, !tbaa !9
  %26 = icmp slt i32 %24, %25
  br i1 %26, label %27, label %56

27:                                               ; preds = %21
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = load i32, ptr %9, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds i32, ptr %28, i64 %30
  %32 = load i32, ptr %31, align 4, !tbaa !9
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = load i32, ptr %9, align 4, !tbaa !9
  %35 = load i32, ptr %11, align 4, !tbaa !9
  %36 = add nsw i32 %34, %35
  %37 = sext i32 %36 to i64
  %38 = getelementptr inbounds i32, ptr %33, i64 %37
  %39 = load i32, ptr %38, align 4, !tbaa !9
  %40 = icmp sgt i32 %32, %39
  br i1 %40, label %41, label %52

41:                                               ; preds = %27
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = load i32, ptr %9, align 4, !tbaa !9
  %44 = sext i32 %43 to i64
  %45 = getelementptr inbounds i32, ptr %42, i64 %44
  %46 = load ptr, ptr %5, align 8, !tbaa !5
  %47 = load i32, ptr %9, align 4, !tbaa !9
  %48 = load i32, ptr %11, align 4, !tbaa !9
  %49 = add nsw i32 %47, %48
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds i32, ptr %46, i64 %50
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %45, ptr noundef nonnull align 4 dereferenceable(4) %51) #3
  br label %52

52:                                               ; preds = %41, %27
  br label %53

53:                                               ; preds = %52
  %54 = load i32, ptr %9, align 4, !tbaa !9
  %55 = add nsw i32 %54, 1
  store i32 %55, ptr %9, align 4, !tbaa !9
  br label %21, !llvm.loop !11

56:                                               ; preds = %21
  %57 = load i32, ptr %11, align 4, !tbaa !9
  %58 = load i32, ptr %7, align 4, !tbaa !9
  %59 = icmp sgt i32 %57, %58
  br i1 %59, label %60, label %64

60:                                               ; preds = %56
  %61 = load i32, ptr %11, align 4, !tbaa !9
  %62 = load i32, ptr %7, align 4, !tbaa !9
  %63 = sub nsw i32 %61, %62
  br label %65

64:                                               ; preds = %56
  br label %65

65:                                               ; preds = %64, %60
  %66 = phi i32 [ %63, %60 ], [ 0, %64 ]
  store i32 %66, ptr %10, align 4, !tbaa !9
  br label %67

67:                                               ; preds = %99, %65
  %68 = load i32, ptr %9, align 4, !tbaa !9
  %69 = load i32, ptr %7, align 4, !tbaa !9
  %70 = icmp slt i32 %68, %69
  br i1 %70, label %71, label %75

71:                                               ; preds = %67
  %72 = load i32, ptr %10, align 4, !tbaa !9
  %73 = load i32, ptr %8, align 4, !tbaa !9
  %74 = icmp slt i32 %72, %73
  br label %75

75:                                               ; preds = %71, %67
  %76 = phi i1 [ false, %67 ], [ %74, %71 ]
  br i1 %76, label %77, label %104

77:                                               ; preds = %75
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = load i32, ptr %9, align 4, !tbaa !9
  %80 = sext i32 %79 to i64
  %81 = getelementptr inbounds i32, ptr %78, i64 %80
  %82 = load i32, ptr %81, align 4, !tbaa !9
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = load i32, ptr %10, align 4, !tbaa !9
  %85 = sext i32 %84 to i64
  %86 = getelementptr inbounds i32, ptr %83, i64 %85
  %87 = load i32, ptr %86, align 4, !tbaa !9
  %88 = icmp sgt i32 %82, %87
  br i1 %88, label %89, label %98

89:                                               ; preds = %77
  %90 = load ptr, ptr %5, align 8, !tbaa !5
  %91 = load i32, ptr %9, align 4, !tbaa !9
  %92 = sext i32 %91 to i64
  %93 = getelementptr inbounds i32, ptr %90, i64 %92
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = load i32, ptr %10, align 4, !tbaa !9
  %96 = sext i32 %95 to i64
  %97 = getelementptr inbounds i32, ptr %94, i64 %96
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %93, ptr noundef nonnull align 4 dereferenceable(4) %97) #3
  br label %98

98:                                               ; preds = %89, %77
  br label %99

99:                                               ; preds = %98
  %100 = load i32, ptr %9, align 4, !tbaa !9
  %101 = add nsw i32 %100, 1
  store i32 %101, ptr %9, align 4, !tbaa !9
  %102 = load i32, ptr %10, align 4, !tbaa !9
  %103 = add nsw i32 %102, 1
  store i32 %103, ptr %10, align 4, !tbaa !9
  br label %67, !llvm.loop !13

104:                                              ; preds = %75
  %105 = load i32, ptr %10, align 4, !tbaa !9
  %106 = load i32, ptr %8, align 4, !tbaa !9
  %107 = icmp slt i32 %105, %106
  br i1 %107, label %108, label %145

108:                                              ; preds = %104
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %109

109:                                              ; preds = %141, %108
  %110 = load i32, ptr %10, align 4, !tbaa !9
  %111 = load i32, ptr %11, align 4, !tbaa !9
  %112 = add nsw i32 %110, %111
  %113 = load i32, ptr %8, align 4, !tbaa !9
  %114 = icmp slt i32 %112, %113
  br i1 %114, label %115, label %144

115:                                              ; preds = %109
  %116 = load ptr, ptr %6, align 8, !tbaa !5
  %117 = load i32, ptr %10, align 4, !tbaa !9
  %118 = sext i32 %117 to i64
  %119 = getelementptr inbounds i32, ptr %116, i64 %118
  %120 = load i32, ptr %119, align 4, !tbaa !9
  %121 = load ptr, ptr %6, align 8, !tbaa !5
  %122 = load i32, ptr %10, align 4, !tbaa !9
  %123 = load i32, ptr %11, align 4, !tbaa !9
  %124 = add nsw i32 %122, %123
  %125 = sext i32 %124 to i64
  %126 = getelementptr inbounds i32, ptr %121, i64 %125
  %127 = load i32, ptr %126, align 4, !tbaa !9
  %128 = icmp sgt i32 %120, %127
  br i1 %128, label %129, label %140

129:                                              ; preds = %115
  %130 = load ptr, ptr %6, align 8, !tbaa !5
  %131 = load i32, ptr %10, align 4, !tbaa !9
  %132 = sext i32 %131 to i64
  %133 = getelementptr inbounds i32, ptr %130, i64 %132
  %134 = load ptr, ptr %6, align 8, !tbaa !5
  %135 = load i32, ptr %10, align 4, !tbaa !9
  %136 = load i32, ptr %11, align 4, !tbaa !9
  %137 = add nsw i32 %135, %136
  %138 = sext i32 %137 to i64
  %139 = getelementptr inbounds i32, ptr %134, i64 %138
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %133, ptr noundef nonnull align 4 dereferenceable(4) %139) #3
  br label %140

140:                                              ; preds = %129, %115
  br label %141

141:                                              ; preds = %140
  %142 = load i32, ptr %10, align 4, !tbaa !9
  %143 = add nsw i32 %142, 1
  store i32 %143, ptr %10, align 4, !tbaa !9
  br label %109, !llvm.loop !14

144:                                              ; preds = %109
  br label %145

145:                                              ; preds = %144, %104
  br label %146

146:                                              ; preds = %145
  %147 = load i32, ptr %11, align 4, !tbaa !9
  %148 = call noundef i32 @_Z7nextGapi(i32 noundef %147)
  store i32 %148, ptr %11, align 4, !tbaa !9
  br label %17, !llvm.loop !15

149:                                              ; preds = %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z7nextGapi(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5mergePiS_ii(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = add nsw i32 %3, %2
  %6 = tail call noundef i32 @_Z7nextGapi(i32 noundef %5)
  %7 = icmp sgt i32 %6, 0
  br i1 %7, label %.preheader59.preheader, label %._crit_edge71

.preheader59.preheader:                           ; preds = %4
  %8 = sext i32 %3 to i64
  br label %.preheader59

.preheader59:                                     ; preds = %.preheader59.preheader, %.loopexit
  %.069 = phi i32 [ %46, %.loopexit ], [ %6, %.preheader59.preheader ]
  %9 = icmp slt i32 %.069, %2
  br i1 %9, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %.preheader59
  %10 = zext nneg i32 %.069 to i64
  %11 = sub nsw i32 %2, %.069
  %wide.trip.count = zext i32 %11 to i64
  %invariant.gep = getelementptr inbounds i32, ptr %0, i64 %10
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %17
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next, %17 ]
  %12 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %gep = getelementptr inbounds i32, ptr %invariant.gep, i64 %indvars.iv
  %14 = load i32, ptr %gep, align 4, !tbaa !5
  %15 = icmp sgt i32 %13, %14
  br i1 %15, label %16, label %17

16:                                               ; preds = %.lr.ph
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %12, ptr noundef nonnull align 4 dereferenceable(4) %gep) #2
  br label %17

17:                                               ; preds = %.lr.ph, %16
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %17, %.preheader59
  %.053.lcssa = phi i32 [ 0, %.preheader59 ], [ %11, %17 ]
  %18 = icmp sgt i32 %.069, %2
  %19 = sub i32 %.069, %2
  %20 = select i1 %18, i32 %19, i32 0
  %21 = icmp slt i32 %.053.lcssa, %2
  %22 = icmp slt i32 %20, %3
  %23 = and i1 %21, %22
  br i1 %23, label %.lr.ph64.preheader, label %._crit_edge65

.lr.ph64.preheader:                               ; preds = %._crit_edge
  %24 = sext i32 %20 to i64
  %25 = zext i32 %.053.lcssa to i64
  br label %.lr.ph64

.lr.ph64:                                         ; preds = %.lr.ph64.preheader, %32
  %indvars.iv77 = phi i64 [ %25, %.lr.ph64.preheader ], [ %indvars.iv.next78, %32 ]
  %indvars.iv75 = phi i64 [ %24, %.lr.ph64.preheader ], [ %indvars.iv.next76, %32 ]
  %26 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv77
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = getelementptr inbounds i32, ptr %1, i64 %indvars.iv75
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = icmp sgt i32 %27, %29
  br i1 %30, label %31, label %32

31:                                               ; preds = %.lr.ph64
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %26, ptr noundef nonnull align 4 dereferenceable(4) %28) #2
  br label %32

32:                                               ; preds = %.lr.ph64, %31
  %indvars.iv.next78 = add nuw nsw i64 %indvars.iv77, 1
  %indvars.iv.next76 = add nsw i64 %indvars.iv75, 1
  %33 = trunc nuw i64 %indvars.iv.next78 to i32
  %34 = icmp slt i32 %33, %2
  %35 = icmp slt i64 %indvars.iv.next76, %8
  %36 = select i1 %34, i1 %35, i1 false
  br i1 %36, label %.lr.ph64, label %._crit_edge65, !llvm.loop !11

._crit_edge65:                                    ; preds = %32, %._crit_edge
  %.lcssa = phi i1 [ %22, %._crit_edge ], [ %35, %32 ]
  %37 = icmp slt i32 %.069, %3
  %or.cond = and i1 %.lcssa, %37
  br i1 %or.cond, label %.lr.ph68.preheader, label %.loopexit

.lr.ph68.preheader:                               ; preds = %._crit_edge65
  %38 = zext nneg i32 %.069 to i64
  %39 = sub i32 %3, %.069
  %wide.trip.count85 = zext i32 %39 to i64
  %invariant.gep88 = getelementptr inbounds i32, ptr %1, i64 %38
  br label %.lr.ph68

.lr.ph68:                                         ; preds = %.lr.ph68.preheader, %45
  %indvars.iv82 = phi i64 [ 0, %.lr.ph68.preheader ], [ %indvars.iv.next83, %45 ]
  %40 = getelementptr inbounds i32, ptr %1, i64 %indvars.iv82
  %41 = load i32, ptr %40, align 4, !tbaa !5
  %gep89 = getelementptr inbounds i32, ptr %invariant.gep88, i64 %indvars.iv82
  %42 = load i32, ptr %gep89, align 4, !tbaa !5
  %43 = icmp sgt i32 %41, %42
  br i1 %43, label %44, label %45

44:                                               ; preds = %.lr.ph68
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %40, ptr noundef nonnull align 4 dereferenceable(4) %gep89) #2
  br label %45

45:                                               ; preds = %.lr.ph68, %44
  %indvars.iv.next83 = add nuw nsw i64 %indvars.iv82, 1
  %exitcond86.not = icmp eq i64 %indvars.iv.next83, %wide.trip.count85
  br i1 %exitcond86.not, label %.loopexit, label %.lr.ph68, !llvm.loop !12

.loopexit:                                        ; preds = %45, %._crit_edge65
  %46 = tail call noundef i32 @_Z7nextGapi(i32 noundef %.069)
  %47 = icmp sgt i32 %46, 0
  br i1 %47, label %.preheader59, label %._crit_edge71, !llvm.loop !13

._crit_edge71:                                    ; preds = %.loopexit, %4
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass