; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_fdcan)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FDCAN_TriggerTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FDCAN_HandleTypeDef = type { ptr, ptr, %struct.FDCAN_InitTypeDef, %struct.FDCAN_MsgRamAddressTypeDef, i32, i32, i32, i32 }
%struct.FDCAN_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FDCAN_MsgRamAddressTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__RBIT(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.ctlz.i32(i32, i1 immarg) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_FDCAN_TT_ConfigTrigger(ptr noundef %0, ptr noundef %1) #3 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %12, i32 0, i32 2
  %14 = load i32, ptr %13, align 4, !tbaa !9
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %2
  br label %17

17:                                               ; preds = %16, %2
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %18, i32 0, i32 6
  %20 = load i32, ptr %19, align 4, !tbaa !12
  %21 = icmp eq i32 %20, 2
  br i1 %21, label %37, label %22

22:                                               ; preds = %17
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %23, i32 0, i32 6
  %25 = load i32, ptr %24, align 4, !tbaa !12
  %26 = icmp eq i32 %25, 3
  br i1 %26, label %37, label %27

27:                                               ; preds = %22
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %28, i32 0, i32 6
  %30 = load i32, ptr %29, align 4, !tbaa !12
  %31 = icmp eq i32 %30, 4
  br i1 %31, label %37, label %32

32:                                               ; preds = %27
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %33, i32 0, i32 6
  %35 = load i32, ptr %34, align 4, !tbaa !12
  %36 = icmp eq i32 %35, 5
  br i1 %36, label %37, label %38

37:                                               ; preds = %32, %27, %22, %17
  br label %38

38:                                               ; preds = %37, %32
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %39, i32 0, i32 6
  %41 = load i32, ptr %40, align 4, !tbaa !12
  %42 = icmp eq i32 %41, 8
  br i1 %42, label %43, label %51

43:                                               ; preds = %38
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %44, i32 0, i32 7
  %46 = load i32, ptr %45, align 4, !tbaa !13
  %47 = icmp eq i32 %46, 0
  br i1 %47, label %48, label %49

48:                                               ; preds = %43
  br label %50

49:                                               ; preds = %43
  br label %50

50:                                               ; preds = %49, %48
  br label %51

51:                                               ; preds = %50, %38
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %52, i32 0, i32 5
  %54 = load volatile i32, ptr %53, align 8, !tbaa !14
  %55 = icmp eq i32 %54, 1
  br i1 %55, label %56, label %154

56:                                               ; preds = %51
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %57, i32 0, i32 2
  %59 = load i32, ptr %58, align 4, !tbaa !9
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %62

61:                                               ; preds = %56
  store i32 0, ptr %6, align 4, !tbaa !17
  br label %70

62:                                               ; preds = %56
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %63, i32 0, i32 2
  %65 = load i32, ptr %64, align 4, !tbaa !9
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %66, i32 0, i32 3
  %68 = load i32, ptr %67, align 4, !tbaa !18
  %69 = add i32 %65, %68
  store i32 %69, ptr %6, align 4, !tbaa !17
  br label %70

70:                                               ; preds = %62, %61
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %71, i32 0, i32 1
  %73 = load i32, ptr %72, align 4, !tbaa !19
  %74 = shl i32 %73, 16
  %75 = load i32, ptr %6, align 4, !tbaa !17
  %76 = shl i32 %75, 8
  %77 = or i32 %74, %76
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %78, i32 0, i32 4
  %80 = load i32, ptr %79, align 4, !tbaa !20
  %81 = or i32 %77, %80
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %82, i32 0, i32 5
  %84 = load i32, ptr %83, align 4, !tbaa !21
  %85 = or i32 %81, %84
  %86 = load ptr, ptr %5, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %86, i32 0, i32 6
  %88 = load i32, ptr %87, align 4, !tbaa !12
  %89 = or i32 %85, %88
  store i32 %89, ptr %8, align 4, !tbaa !17
  %90 = load ptr, ptr %5, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %90, i32 0, i32 6
  %92 = load i32, ptr %91, align 4, !tbaa !12
  %93 = icmp eq i32 %92, 8
  br i1 %93, label %94, label %98

94:                                               ; preds = %70
  %95 = load ptr, ptr %5, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %95, i32 0, i32 9
  %97 = load i32, ptr %96, align 4, !tbaa !22
  store i32 %97, ptr %7, align 4, !tbaa !17
  br label %128

98:                                               ; preds = %70
  %99 = load ptr, ptr %5, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %99, i32 0, i32 6
  %101 = load i32, ptr %100, align 4, !tbaa !12
  %102 = icmp eq i32 %101, 2
  br i1 %102, label %118, label %103

103:                                              ; preds = %98
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %104, i32 0, i32 6
  %106 = load i32, ptr %105, align 4, !tbaa !12
  %107 = icmp eq i32 %106, 3
  br i1 %107, label %118, label %108

108:                                              ; preds = %103
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %109, i32 0, i32 6
  %111 = load i32, ptr %110, align 4, !tbaa !12
  %112 = icmp eq i32 %111, 4
  br i1 %112, label %118, label %113

113:                                              ; preds = %108
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %114, i32 0, i32 6
  %116 = load i32, ptr %115, align 4, !tbaa !12
  %117 = icmp eq i32 %116, 5
  br i1 %117, label %118, label %126

118:                                              ; preds = %113, %108, %103, %98
  %119 = load ptr, ptr %5, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %119, i32 0, i32 8
  %121 = load i32, ptr %120, align 4, !tbaa !23
  %122 = call i32 @__RBIT(i32 noundef %121)
  %123 = call i32 @llvm.ctlz.i32(i32 %122, i1 true)
  %124 = trunc i32 %123 to i8
  %125 = zext i8 %124 to i32
  store i32 %125, ptr %7, align 4, !tbaa !17
  br label %127

126:                                              ; preds = %113
  store i32 0, ptr %7, align 4, !tbaa !17
  br label %127

127:                                              ; preds = %126, %118
  br label %128

128:                                              ; preds = %127, %94
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %129, i32 0, i32 7
  %131 = load i32, ptr %130, align 4, !tbaa !13
  %132 = lshr i32 %131, 7
  %133 = load i32, ptr %7, align 4, !tbaa !17
  %134 = shl i32 %133, 16
  %135 = or i32 %132, %134
  store i32 %135, ptr %9, align 4, !tbaa !17
  %136 = load ptr, ptr %4, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %136, i32 0, i32 3
  %138 = getelementptr inbounds %struct.FDCAN_MsgRamAddressTypeDef, ptr %137, i32 0, i32 8
  %139 = load i32, ptr %138, align 4, !tbaa !24
  %140 = load ptr, ptr %5, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.FDCAN_TriggerTypeDef, ptr %140, i32 0, i32 0
  %142 = load i32, ptr %141, align 4, !tbaa !25
  %143 = mul i32 %142, 4
  %144 = mul i32 %143, 2
  %145 = add i32 %139, %144
  %146 = zext i32 %145 to i64
  %147 = inttoptr i64 %146 to ptr
  store ptr %147, ptr %10, align 8, !tbaa !5
  %148 = load i32, ptr %8, align 4, !tbaa !17
  %149 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %148, ptr %149, align 4, !tbaa !17
  %150 = load ptr, ptr %10, align 8, !tbaa !5
  %151 = getelementptr inbounds i32, ptr %150, i32 1
  store ptr %151, ptr %10, align 8, !tbaa !5
  %152 = load i32, ptr %9, align 4, !tbaa !17
  %153 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %152, ptr %153, align 4, !tbaa !17
  store i32 0, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %159

154:                                              ; preds = %51
  %155 = load ptr, ptr %4, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %155, i32 0, i32 7
  %157 = load volatile i32, ptr %156, align 8, !tbaa !26
  %158 = or i32 %157, 4
  store volatile i32 %158, ptr %156, align 8, !tbaa !26
  store i32 1, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %159

159:                                              ; preds = %154, %128
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %160 = load i32, ptr %3, align 4
  ret i32 %160
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 8}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!11 = !{!"int", !7, i64 0}
!12 = !{!10, !11, i64 24}
!13 = !{!10, !11, i64 28}
!14 = !{!15, !11, i64 168}
!15 = !{!"", !6, i64 0, !6, i64 8, !16, i64 16, !10, i64 124, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!17 = !{!11, !11, i64 0}
!18 = !{!10, !11, i64 12}
!19 = !{!10, !11, i64 4}
!20 = !{!10, !11, i64 16}
!21 = !{!10, !11, i64 20}
!22 = !{!10, !11, i64 36}
!23 = !{!10, !11, i64 32}
!24 = !{!15, !11, i64 156}
!25 = !{!10, !11, i64 0}
!26 = !{!15, !11, i64 176}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__RBIT(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_FDCAN_TT_ConfigTrigger(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #2 {
  %3 = getelementptr inbounds i8, ptr %1, i64 24
  %4 = getelementptr inbounds i8, ptr %0, i64 168
  %5 = load volatile i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %7, label %51

7:                                                ; preds = %2
  %8 = getelementptr inbounds i8, ptr %1, i64 8
  %9 = load i32, ptr %8, align 4, !tbaa !13
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %16, label %11

11:                                               ; preds = %7
  %12 = getelementptr inbounds i8, ptr %1, i64 12
  %13 = load i32, ptr %12, align 4, !tbaa !14
  %14 = add i32 %13, %9
  %15 = shl i32 %14, 8
  br label %16

16:                                               ; preds = %7, %11
  %.029 = phi i32 [ %15, %11 ], [ 0, %7 ]
  %17 = getelementptr inbounds i8, ptr %1, i64 4
  %18 = load i32, ptr %17, align 4, !tbaa !15
  %19 = shl i32 %18, 16
  %20 = or i32 %19, %.029
  %21 = getelementptr inbounds i8, ptr %1, i64 16
  %22 = load i32, ptr %21, align 4, !tbaa !16
  %23 = or i32 %20, %22
  %24 = getelementptr inbounds i8, ptr %1, i64 20
  %25 = load i32, ptr %24, align 4, !tbaa !17
  %26 = or i32 %23, %25
  %27 = load i32, ptr %3, align 4, !tbaa !18
  %28 = or i32 %26, %27
  switch i32 %27, label %37 [
    i32 8, label %29
    i32 2, label %32
    i32 3, label %32
    i32 4, label %32
    i32 5, label %32
  ]

29:                                               ; preds = %16
  %30 = getelementptr inbounds i8, ptr %1, i64 36
  %31 = load i32, ptr %30, align 4, !tbaa !19
  br label %37

32:                                               ; preds = %16, %16, %16, %16
  %33 = getelementptr inbounds i8, ptr %1, i64 32
  %34 = load i32, ptr %33, align 4, !tbaa !20
  %35 = tail call i32 @__RBIT(i32 noundef %34)
  %36 = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %35, i1 true)
  br label %37

37:                                               ; preds = %16, %32, %29
  %.030 = phi i32 [ %31, %29 ], [ %36, %32 ], [ 0, %16 ]
  %38 = getelementptr inbounds i8, ptr %1, i64 28
  %39 = load i32, ptr %38, align 4, !tbaa !21
  %40 = lshr i32 %39, 7
  %41 = shl i32 %.030, 16
  %42 = or i32 %40, %41
  %43 = getelementptr inbounds i8, ptr %0, i64 156
  %44 = load i32, ptr %43, align 4, !tbaa !22
  %45 = load i32, ptr %1, align 4, !tbaa !23
  %46 = shl i32 %45, 3
  %47 = add i32 %46, %44
  %48 = zext i32 %47 to i64
  %49 = inttoptr i64 %48 to ptr
  store i32 %28, ptr %49, align 4, !tbaa !24
  %50 = getelementptr inbounds i8, ptr %49, i64 4
  store i32 %42, ptr %50, align 4, !tbaa !24
  br label %55

51:                                               ; preds = %2
  %52 = getelementptr inbounds i8, ptr %0, i64 176
  %53 = load volatile i32, ptr %52, align 8, !tbaa !25
  %54 = or i32 %53, 4
  store volatile i32 %54, ptr %52, align 8, !tbaa !25
  br label %55

55:                                               ; preds = %51, %37
  %.0 = phi i32 [ 0, %37 ], [ 1, %51 ]
  ret i32 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 168}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !12, i64 124, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!13 = !{!12, !11, i64 8}
!14 = !{!12, !11, i64 12}
!15 = !{!12, !11, i64 4}
!16 = !{!12, !11, i64 16}
!17 = !{!12, !11, i64 20}
!18 = !{!12, !11, i64 24}
!19 = !{!12, !11, i64 36}
!20 = !{!12, !11, i64 32}
!21 = !{!12, !11, i64 28}
!22 = !{!6, !11, i64 156}
!23 = !{!12, !11, i64 0}
!24 = !{!11, !11, i64 0}
!25 = !{!6, !11, i64 176}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass