; LLVM IR from xboot/libcg :: src (xft)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XCG_FT_Vector_ = type { i64, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @ft_trig_pseudo_rotate(ptr noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @ft_trig_prenorm(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XCG_FT_Vector_Rotate(ptr noundef %0, i64 noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  %6 = alloca %struct.XCG_FT_Vector_, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #3
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %6, ptr align 8 %9, i64 16, i1 false), !tbaa.struct !11
  %10 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  %11 = load i64, ptr %10, align 8, !tbaa !12
  %12 = icmp eq i64 %11, 0
  br i1 %12, label %13, label %18

13:                                               ; preds = %2
  %14 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  %15 = load i64, ptr %14, align 8, !tbaa !14
  %16 = icmp eq i64 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %13
  store i32 1, ptr %7, align 4
  br label %85

18:                                               ; preds = %13, %2
  %19 = call i32 @ft_trig_prenorm(ptr noundef %6)
  store i32 %19, ptr %5, align 4, !tbaa !15
  %20 = load i64, ptr %4, align 8, !tbaa !9
  call void @ft_trig_pseudo_rotate(ptr noundef %6, i64 noundef %20)
  %21 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  %22 = load i64, ptr %21, align 8, !tbaa !12
  %23 = call i64 @ft_trig_downscale(i64 noundef %22)
  %24 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  store i64 %23, ptr %24, align 8, !tbaa !12
  %25 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  %26 = load i64, ptr %25, align 8, !tbaa !14
  %27 = call i64 @ft_trig_downscale(i64 noundef %26)
  %28 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  store i64 %27, ptr %28, align 8, !tbaa !14
  %29 = load i32, ptr %5, align 4, !tbaa !15
  %30 = icmp sgt i32 %29, 0
  br i1 %30, label %31, label %67

31:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %32 = load i32, ptr %5, align 4, !tbaa !15
  %33 = sub nsw i32 %32, 1
  %34 = shl i32 1, %33
  store i32 %34, ptr %8, align 4, !tbaa !15
  %35 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  %36 = load i64, ptr %35, align 8, !tbaa !12
  %37 = load i32, ptr %8, align 4, !tbaa !15
  %38 = sext i32 %37 to i64
  %39 = add nsw i64 %36, %38
  %40 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  %41 = load i64, ptr %40, align 8, !tbaa !12
  %42 = icmp slt i64 %41, 0
  %43 = zext i1 %42 to i32
  %44 = sext i32 %43 to i64
  %45 = sub nsw i64 %39, %44
  %46 = load i32, ptr %5, align 4, !tbaa !15
  %47 = zext i32 %46 to i64
  %48 = ashr i64 %45, %47
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %49, i32 0, i32 0
  store i64 %48, ptr %50, align 8, !tbaa !12
  %51 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  %52 = load i64, ptr %51, align 8, !tbaa !14
  %53 = load i32, ptr %8, align 4, !tbaa !15
  %54 = sext i32 %53 to i64
  %55 = add nsw i64 %52, %54
  %56 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  %57 = load i64, ptr %56, align 8, !tbaa !14
  %58 = icmp slt i64 %57, 0
  %59 = zext i1 %58 to i32
  %60 = sext i32 %59 to i64
  %61 = sub nsw i64 %55, %60
  %62 = load i32, ptr %5, align 4, !tbaa !15
  %63 = zext i32 %62 to i64
  %64 = ashr i64 %61, %63
  %65 = load ptr, ptr %3, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %65, i32 0, i32 1
  store i64 %64, ptr %66, align 8, !tbaa !14
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %84

67:                                               ; preds = %18
  %68 = load i32, ptr %5, align 4, !tbaa !15
  %69 = sub nsw i32 0, %68
  store i32 %69, ptr %5, align 4, !tbaa !15
  %70 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 0
  %71 = load i64, ptr %70, align 8, !tbaa !12
  %72 = load i32, ptr %5, align 4, !tbaa !15
  %73 = zext i32 %72 to i64
  %74 = shl i64 %71, %73
  %75 = load ptr, ptr %3, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %75, i32 0, i32 0
  store i64 %74, ptr %76, align 8, !tbaa !12
  %77 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %6, i32 0, i32 1
  %78 = load i64, ptr %77, align 8, !tbaa !14
  %79 = load i32, ptr %5, align 4, !tbaa !15
  %80 = zext i32 %79 to i64
  %81 = shl i64 %78, %80
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.XCG_FT_Vector_, ptr %82, i32 0, i32 1
  store i64 %81, ptr %83, align 8, !tbaa !14
  br label %84

84:                                               ; preds = %67, %31
  store i32 0, ptr %7, align 4
  br label %85

85:                                               ; preds = %84, %17
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  %86 = load i32, ptr %7, align 4
  switch i32 %86, label %88 [
    i32 0, label %87
    i32 1, label %87
  ]

87:                                               ; preds = %85, %85
  ret void

88:                                               ; preds = %85
  unreachable
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @ft_trig_downscale(i64 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{i64 0, i64 8, !9, i64 8, i64 8, !9}
!12 = !{!13, !10, i64 0}
!13 = !{!"XCG_FT_Vector_", !10, i64 0, !10, i64 8}
!14 = !{!13, !10, i64 8}
!15 = !{!16, !16, i64 0}
!16 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XCG_FT_Vector_ = type { i64, i64 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @ft_trig_pseudo_rotate(ptr noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i32 @ft_trig_prenorm(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XCG_FT_Vector_Rotate(ptr nocapture noundef %0, i64 noundef %1) local_unnamed_addr #1 {
  %3 = alloca %struct.XCG_FT_Vector_, align 8
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) #3
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %3, ptr noundef nonnull align 8 dereferenceable(16) %0, i64 16, i1 false), !tbaa.struct !5
  %4 = load i64, ptr %3, align 8, !tbaa !10
  %5 = icmp eq i64 %4, 0
  %6 = getelementptr inbounds i8, ptr %3, i64 8
  %7 = load i64, ptr %6, align 8
  %8 = icmp eq i64 %7, 0
  %or.cond = select i1 %5, i1 %8, i1 false
  br i1 %or.cond, label %35, label %9

9:                                                ; preds = %2
  %10 = call i32 @ft_trig_prenorm(ptr noundef nonnull %3)
  call void @ft_trig_pseudo_rotate(ptr noundef nonnull %3, i64 noundef %1)
  %11 = load i64, ptr %3, align 8, !tbaa !10
  %12 = call i64 @ft_trig_downscale(i64 noundef %11)
  store i64 %12, ptr %3, align 8, !tbaa !10
  %13 = load i64, ptr %6, align 8, !tbaa !12
  %14 = call i64 @ft_trig_downscale(i64 noundef %13)
  %15 = icmp sgt i32 %10, 0
  br i1 %15, label %16, label %28

16:                                               ; preds = %9
  %17 = add nsw i32 %10, -1
  %18 = shl nuw i32 1, %17
  %19 = load i64, ptr %3, align 8, !tbaa !10
  %20 = sext i32 %18 to i64
  %21 = add nsw i64 %19, %20
  %.lobit.neg = ashr i64 %19, 63
  %22 = add i64 %21, %.lobit.neg
  %23 = zext nneg i32 %10 to i64
  %24 = ashr i64 %22, %23
  store i64 %24, ptr %0, align 8, !tbaa !10
  %25 = add nsw i64 %14, %20
  %.lobit.neg16 = ashr i64 %14, 63
  %26 = add i64 %25, %.lobit.neg16
  %27 = ashr i64 %26, %23
  br label %.sink.split

28:                                               ; preds = %9
  %29 = sub nsw i32 0, %10
  %30 = load i64, ptr %3, align 8, !tbaa !10
  %31 = zext nneg i32 %29 to i64
  %32 = shl i64 %30, %31
  store i64 %32, ptr %0, align 8, !tbaa !10
  %33 = shl i64 %14, %31
  br label %.sink.split

.sink.split:                                      ; preds = %28, %16
  %.sink = phi i64 [ %27, %16 ], [ %33, %28 ]
  %34 = getelementptr inbounds i8, ptr %0, i64 8
  store i64 %.sink, ptr %34, align 8, !tbaa !12
  br label %35

35:                                               ; preds = %.sink.split, %2
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @ft_trig_downscale(i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 0, i64 8, !6, i64 8, i64 8, !6}
!6 = !{!7, !7, i64 0}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!11, !7, i64 0}
!11 = !{!"XCG_FT_Vector_", !7, i64 0, !7, i64 8}
!12 = !{!11, !7, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass