; LLVM IR from mist64/perfect6502 :: perfect6502 (initAndResetChip)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.netlist_transdefs = type { i32, i32, i32 }

@netlist_6502_node_is_pullup = external dso_local global [1725 x i32], align 16
@netlist_6502_transdefs = external dso_local global [3510 x %struct.netlist_transdefs], align 16
@cycle = external dso_local global i32, align 4

; Function Attrs: nounwind uwtable
declare dso_local void @step(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @setNode(ptr noundef, i16 noundef zeroext, i32 noundef) #2

declare void @recalcNodeList(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local ptr @initAndResetChip() #0 {
  %1 = alloca i16, align 2
  %2 = alloca i16, align 2
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 2, ptr %1) #3
  store i16 1725, ptr %1, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %2) #3
  store i16 3510, ptr %2, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #3
  %5 = load i16, ptr %1, align 2, !tbaa !5
  %6 = load i16, ptr %2, align 2, !tbaa !5
  %7 = call ptr @setupNodesAndTransistors(ptr noundef @netlist_6502_transdefs, ptr noundef @netlist_6502_node_is_pullup, i16 noundef zeroext %5, i16 noundef zeroext %6, i16 noundef zeroext 558, i16 noundef zeroext 657)
  store ptr %7, ptr %3, align 8, !tbaa !9
  %8 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %8, i16 noundef zeroext 159, i32 noundef 0)
  %9 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %9, i16 noundef zeroext 1171, i32 noundef 1)
  %10 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %10, i16 noundef zeroext 89, i32 noundef 1)
  %11 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %11, i16 noundef zeroext 1672, i32 noundef 0)
  %12 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %12, i16 noundef zeroext 103, i32 noundef 1)
  %13 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %13, i16 noundef zeroext 1297, i32 noundef 1)
  %14 = load ptr, ptr %3, align 8, !tbaa !9
  call void @stabilizeChip(ptr noundef %14)
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !11
  br label %15

15:                                               ; preds = %21, %0
  %16 = load i32, ptr %4, align 4, !tbaa !11
  %17 = icmp slt i32 %16, 16
  br i1 %17, label %19, label %18

18:                                               ; preds = %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  br label %24

19:                                               ; preds = %15
  %20 = load ptr, ptr %3, align 8, !tbaa !9
  call void @step(ptr noundef %20)
  br label %21

21:                                               ; preds = %19
  %22 = load i32, ptr %4, align 4, !tbaa !11
  %23 = add nsw i32 %22, 1
  store i32 %23, ptr %4, align 4, !tbaa !11
  br label %15, !llvm.loop !13

24:                                               ; preds = %18
  %25 = load ptr, ptr %3, align 8, !tbaa !9
  call void @setNode(ptr noundef %25, i16 noundef zeroext 159, i32 noundef 1)
  %26 = load ptr, ptr %3, align 8, !tbaa !9
  call void @recalcNodeList(ptr noundef %26)
  store i32 0, ptr @cycle, align 4, !tbaa !11
  %27 = load ptr, ptr %3, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %2) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %1) #3
  ret ptr %27
}

declare ptr @setupNodesAndTransistors(ptr noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) #2

declare void @stabilizeChip(ptr noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.netlist_transdefs = type { i32, i32, i32 }

@netlist_6502_node_is_pullup = external dso_local global [1725 x i32], align 16
@netlist_6502_transdefs = external dso_local global [3510 x %struct.netlist_transdefs], align 16
@cycle = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
declare dso_local void @step(ptr noundef) local_unnamed_addr #0

declare void @setNode(ptr noundef, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

declare void @recalcNodeList(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @initAndResetChip() local_unnamed_addr #0 {
  %1 = tail call ptr @setupNodesAndTransistors(ptr noundef nonnull @netlist_6502_transdefs, ptr noundef nonnull @netlist_6502_node_is_pullup, i16 noundef zeroext 1725, i16 noundef zeroext 3510, i16 noundef zeroext 558, i16 noundef zeroext 657) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 159, i32 noundef 0) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 1171, i32 noundef 1) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 89, i32 noundef 1) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 1672, i32 noundef 0) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 103, i32 noundef 1) #2
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 1297, i32 noundef 1) #2
  tail call void @stabilizeChip(ptr noundef %1) #2
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @step(ptr noundef %1)
  tail call void @setNode(ptr noundef %1, i16 noundef zeroext 159, i32 noundef 1) #2
  tail call void @recalcNodeList(ptr noundef %1) #2
  store i32 0, ptr @cycle, align 4, !tbaa !5
  ret ptr %1
}

declare ptr @setupNodesAndTransistors(ptr noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

declare void @stabilizeChip(ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass