; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/periph/usart/stm32 (usart)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.usart_t = type { [32 x i8], [32 x i8], %struct.file_operations, %struct.__UART_HandleTypeDef, %struct.dma_t, %struct.dma_t, i32, ptr, ptr, i32, i32, i32, i32, i32, %struct.usart_private_t }
%struct.file_operations = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }
%struct.__UART_HandleTypeDef = type { ptr, %struct.UART_InitTypeDef, %struct.UART_AdvFeatureInitTypeDef, ptr, i16, i16, ptr, i16, i16, i16, i32, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32 }
%struct.UART_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.UART_AdvFeatureInitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_t = type { %struct.__DMA_HandleTypeDef, i32, %struct.dma_private_t }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_private_t = type { i32 }
%struct.usart_private_t = type { i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32, i8, i8, i8, i8, i8 }
%struct.USART_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) #1

declare i32 @HAL_UART_Transmit_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) #1

declare i32 @HAL_UART_Transmit_IT(ptr noundef, ptr noundef, i16 noundef zeroext) #1

declare i64 @xQueueGenericSend(ptr noundef, ptr noundef, i32 noundef, i64 noundef) #1

declare i32 @HAL_UART_Receive_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) #1

declare i32 @HAL_UART_Receive_IT(ptr noundef, ptr noundef, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @usart_transmit_receive(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3, i16 noundef zeroext %4) #2 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !5
  store i16 %3, ptr %10, align 2, !tbaa !9
  store i16 %4, ptr %11, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 0, ptr %12, align 4, !tbaa !11
  %14 = load i16, ptr %10, align 2, !tbaa !9
  %15 = zext i16 %14 to i32
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %27, label %17

17:                                               ; preds = %5
  %18 = load i16, ptr %11, align 2, !tbaa !9
  %19 = zext i16 %18 to i32
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %27, label %21

21:                                               ; preds = %17
  %22 = load ptr, ptr %8, align 8, !tbaa !5
  %23 = icmp eq ptr %22, null
  br i1 %23, label %27, label %24

24:                                               ; preds = %21
  %25 = load ptr, ptr %9, align 8, !tbaa !5
  %26 = icmp eq ptr %25, null
  br i1 %26, label %27, label %28

27:                                               ; preds = %24, %21, %17, %5
  store i32 22, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %144

28:                                               ; preds = %24
  %29 = load ptr, ptr %7, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.usart_t, ptr %29, i32 0, i32 14
  %31 = getelementptr inbounds %struct.usart_private_t, ptr %30, i32 0, i32 3
  %32 = load ptr, ptr %31, align 8, !tbaa !13
  %33 = call i64 @xQueueSemaphoreTake(ptr noundef %32, i32 noundef 0)
  %34 = icmp eq i64 %33, 0
  br i1 %34, label %42, label %35

35:                                               ; preds = %28
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.usart_t, ptr %36, i32 0, i32 14
  %38 = getelementptr inbounds %struct.usart_private_t, ptr %37, i32 0, i32 4
  %39 = load ptr, ptr %38, align 8, !tbaa !25
  %40 = call i64 @xQueueSemaphoreTake(ptr noundef %39, i32 noundef 0)
  %41 = icmp eq i64 %40, 0
  br i1 %41, label %42, label %43

42:                                               ; preds = %35, %28
  store i32 16, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %144

43:                                               ; preds = %35
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.usart_t, ptr %44, i32 0, i32 14
  %46 = getelementptr inbounds %struct.usart_private_t, ptr %45, i32 0, i32 2
  %47 = load ptr, ptr %46, align 8, !tbaa !26
  %48 = call i64 @xQueueSemaphoreTake(ptr noundef %47, i32 noundef 0)
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.usart_t, ptr %49, i32 0, i32 14
  %51 = getelementptr inbounds %struct.usart_private_t, ptr %50, i32 0, i32 5
  store i32 1, ptr %51, align 8, !tbaa !27
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.usart_t, ptr %52, i32 0, i32 14
  %54 = getelementptr inbounds %struct.usart_private_t, ptr %53, i32 0, i32 6
  store i32 2, ptr %54, align 4, !tbaa !28
  %55 = load ptr, ptr %7, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.usart_t, ptr %55, i32 0, i32 14
  %57 = getelementptr inbounds %struct.usart_private_t, ptr %56, i32 0, i32 8
  store i32 0, ptr %57, align 4, !tbaa !29
  %58 = load ptr, ptr %7, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.usart_t, ptr %58, i32 0, i32 14
  %60 = getelementptr inbounds %struct.usart_private_t, ptr %59, i32 0, i32 7
  store i32 0, ptr %60, align 8, !tbaa !30
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.usart_t, ptr %61, i32 0, i32 3
  %63 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !31
  %65 = getelementptr inbounds %struct.USART_TypeDef, ptr %64, i32 0, i32 8
  %66 = load volatile i32, ptr %65, align 4, !tbaa !32
  %67 = zext i32 %66 to i64
  %68 = or i64 %67, 16
  %69 = trunc i64 %68 to i32
  store volatile i32 %69, ptr %65, align 4, !tbaa !32
  %70 = load ptr, ptr %7, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.usart_t, ptr %70, i32 0, i32 3
  %72 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %71, i32 0, i32 0
  %73 = load ptr, ptr %72, align 8, !tbaa !31
  %74 = getelementptr inbounds %struct.USART_TypeDef, ptr %73, i32 0, i32 0
  %75 = load volatile i32, ptr %74, align 4, !tbaa !33
  %76 = zext i32 %75 to i64
  %77 = or i64 %76, 16
  %78 = trunc i64 %77 to i32
  store volatile i32 %78, ptr %74, align 4, !tbaa !33
  %79 = load ptr, ptr %7, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.usart_t, ptr %79, i32 0, i32 14
  %81 = getelementptr inbounds %struct.usart_private_t, ptr %80, i32 0, i32 17
  %82 = load i8, ptr %81, align 1, !tbaa !34, !range !35, !noundef !36
  %83 = trunc i8 %82 to i1
  br i1 %83, label %84, label %97

84:                                               ; preds = %43
  %85 = load ptr, ptr %7, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.usart_t, ptr %85, i32 0, i32 3
  %87 = load ptr, ptr %9, align 8, !tbaa !5
  %88 = load i16, ptr %11, align 2, !tbaa !9
  %89 = call i32 @HAL_UART_Receive_DMA(ptr noundef %86, ptr noundef %87, i16 noundef zeroext %88)
  store i32 %89, ptr %12, align 4, !tbaa !11
  %90 = load ptr, ptr %7, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.usart_t, ptr %90, i32 0, i32 3
  %92 = load ptr, ptr %8, align 8, !tbaa !5
  %93 = load i16, ptr %10, align 2, !tbaa !9
  %94 = call i32 @HAL_UART_Transmit_DMA(ptr noundef %91, ptr noundef %92, i16 noundef zeroext %93)
  %95 = load i32, ptr %12, align 4, !tbaa !11
  %96 = or i32 %95, %94
  store i32 %96, ptr %12, align 4, !tbaa !11
  br label %110

97:                                               ; preds = %43
  %98 = load ptr, ptr %7, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.usart_t, ptr %98, i32 0, i32 3
  %100 = load ptr, ptr %9, align 8, !tbaa !5
  %101 = load i16, ptr %11, align 2, !tbaa !9
  %102 = call i32 @HAL_UART_Receive_IT(ptr noundef %99, ptr noundef %100, i16 noundef zeroext %101)
  store i32 %102, ptr %12, align 4, !tbaa !11
  %103 = load ptr, ptr %7, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.usart_t, ptr %103, i32 0, i32 3
  %105 = load ptr, ptr %8, align 8, !tbaa !5
  %106 = load i16, ptr %10, align 2, !tbaa !9
  %107 = call i32 @HAL_UART_Transmit_IT(ptr noundef %104, ptr noundef %105, i16 noundef zeroext %106)
  %108 = load i32, ptr %12, align 4, !tbaa !11
  %109 = or i32 %108, %107
  store i32 %109, ptr %12, align 4, !tbaa !11
  br label %110

110:                                              ; preds = %97, %84
  %111 = load i32, ptr %12, align 4, !tbaa !11
  %112 = icmp eq i32 %111, 0
  br i1 %112, label %113, label %126

113:                                              ; preds = %110
  %114 = load ptr, ptr %7, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.usart_t, ptr %114, i32 0, i32 14
  %116 = getelementptr inbounds %struct.usart_private_t, ptr %115, i32 0, i32 2
  %117 = load ptr, ptr %116, align 8, !tbaa !26
  %118 = load ptr, ptr %7, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.usart_t, ptr %118, i32 0, i32 10
  %120 = load i32, ptr %119, align 4, !tbaa !37
  %121 = mul i32 %120, 1000
  %122 = udiv i32 %121, 1000
  %123 = call i64 @xQueueSemaphoreTake(ptr noundef %117, i32 noundef %122)
  %124 = icmp ne i64 %123, 0
  br i1 %124, label %126, label %125

125:                                              ; preds = %113
  store i32 116, ptr %12, align 4, !tbaa !11
  br label %126

126:                                              ; preds = %125, %113, %110
  %127 = load ptr, ptr %7, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.usart_t, ptr %127, i32 0, i32 14
  %129 = getelementptr inbounds %struct.usart_private_t, ptr %128, i32 0, i32 5
  store i32 0, ptr %129, align 8, !tbaa !27
  %130 = load ptr, ptr %7, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.usart_t, ptr %130, i32 0, i32 14
  %132 = getelementptr inbounds %struct.usart_private_t, ptr %131, i32 0, i32 6
  store i32 0, ptr %132, align 4, !tbaa !28
  %133 = load ptr, ptr %7, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.usart_t, ptr %133, i32 0, i32 14
  %135 = getelementptr inbounds %struct.usart_private_t, ptr %134, i32 0, i32 3
  %136 = load ptr, ptr %135, align 8, !tbaa !13
  %137 = call i64 @xQueueGenericSend(ptr noundef %136, ptr noundef null, i32 noundef 0, i64 noundef 0)
  %138 = load ptr, ptr %7, align 8, !tbaa !5
  %139 = getelementptr inbounds %struct.usart_t, ptr %138, i32 0, i32 14
  %140 = getelementptr inbounds %struct.usart_private_t, ptr %139, i32 0, i32 4
  %141 = load ptr, ptr %140, align 8, !tbaa !25
  %142 = call i64 @xQueueGenericSend(ptr noundef %141, ptr noundef null, i32 noundef 0, i64 noundef 0)
  %143 = load i32, ptr %12, align 4, !tbaa !11
  store i32 %143, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %144

144:                                              ; preds = %126, %42, %27
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  %145 = load i32, ptr %6, align 4
  ret i32 %145
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 792}
!14 = !{!"", !7, i64 0, !7, i64 32, !15, i64 64, !16, i64 152, !19, i64 336, !19, i64 528, !12, i64 720, !6, i64 728, !6, i64 736, !12, i64 744, !12, i64 748, !12, i64 752, !12, i64 756, !12, i64 760, !23, i64 768}
!15 = !{!"file_operations", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80}
!16 = !{!"__UART_HandleTypeDef", !6, i64 0, !17, i64 8, !18, i64 44, !6, i64 88, !10, i64 96, !10, i64 98, !6, i64 104, !10, i64 112, !10, i64 114, !10, i64 116, !12, i64 120, !10, i64 124, !10, i64 126, !12, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !6, i64 160, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180}
!17 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32}
!18 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36}
!19 = !{!"", !20, i64 0, !12, i64 184, !22, i64 188}
!20 = !{!"__DMA_HandleTypeDef", !6, i64 0, !21, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!21 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!22 = !{!"", !12, i64 0}
!23 = !{!"", !12, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80, !12, i64 88, !24, i64 92, !24, i64 93, !24, i64 94, !24, i64 95, !24, i64 96}
!24 = !{!"_Bool", !7, i64 0}
!25 = !{!14, !6, i64 800}
!26 = !{!14, !6, i64 784}
!27 = !{!14, !12, i64 808}
!28 = !{!14, !12, i64 812}
!29 = !{!14, !12, i64 820}
!30 = !{!14, !12, i64 816}
!31 = !{!14, !6, i64 152}
!32 = !{!21, !12, i64 32}
!33 = !{!21, !12, i64 0}
!34 = !{!14, !24, i64 863}
!35 = !{i8 0, i8 2}
!36 = !{}
!37 = !{!14, !12, i64 748}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) local_unnamed_addr #0

declare i32 @HAL_UART_Transmit_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

declare i32 @HAL_UART_Transmit_IT(ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

declare i64 @xQueueGenericSend(ptr noundef, ptr noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

declare i32 @HAL_UART_Receive_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

declare i32 @HAL_UART_Receive_IT(ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @usart_transmit_receive(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3, i16 noundef zeroext %4) local_unnamed_addr #1 {
  %6 = icmp eq i16 %3, 0
  %7 = icmp eq i16 %4, 0
  %or.cond = or i1 %6, %7
  %8 = icmp eq ptr %1, null
  %or.cond4 = or i1 %8, %or.cond
  %9 = icmp eq ptr %2, null
  %or.cond6 = or i1 %9, %or.cond4
  br i1 %or.cond6, label %58, label %10

10:                                               ; preds = %5
  %11 = getelementptr inbounds i8, ptr %0, i64 792
  %12 = load ptr, ptr %11, align 8, !tbaa !5
  %13 = tail call i64 @xQueueSemaphoreTake(ptr noundef %12, i32 noundef 0) #2
  %14 = icmp eq i64 %13, 0
  br i1 %14, label %58, label %15

15:                                               ; preds = %10
  %16 = getelementptr inbounds i8, ptr %0, i64 800
  %17 = load ptr, ptr %16, align 8, !tbaa !22
  %18 = tail call i64 @xQueueSemaphoreTake(ptr noundef %17, i32 noundef 0) #2
  %19 = icmp eq i64 %18, 0
  br i1 %19, label %58, label %20

20:                                               ; preds = %15
  %21 = getelementptr inbounds i8, ptr %0, i64 784
  %22 = load ptr, ptr %21, align 8, !tbaa !23
  %23 = tail call i64 @xQueueSemaphoreTake(ptr noundef %22, i32 noundef 0) #2
  %24 = getelementptr inbounds i8, ptr %0, i64 808
  %25 = getelementptr inbounds i8, ptr %0, i64 812
  store <4 x i32> <i32 1, i32 2, i32 0, i32 0>, ptr %24, align 8, !tbaa !24
  %26 = getelementptr inbounds i8, ptr %0, i64 152
  %27 = load ptr, ptr %26, align 8, !tbaa !25
  %28 = getelementptr inbounds i8, ptr %27, i64 32
  %29 = load volatile i32, ptr %28, align 4, !tbaa !26
  %30 = or i32 %29, 16
  store volatile i32 %30, ptr %28, align 4, !tbaa !26
  %31 = load volatile i32, ptr %27, align 4, !tbaa !27
  %32 = or i32 %31, 16
  store volatile i32 %32, ptr %27, align 4, !tbaa !27
  %33 = getelementptr inbounds i8, ptr %0, i64 863
  %34 = load i8, ptr %33, align 1, !tbaa !28, !range !29, !noundef !30
  %35 = trunc nuw i8 %34 to i1
  br i1 %35, label %36, label %40

36:                                               ; preds = %20
  %37 = tail call i32 @HAL_UART_Receive_DMA(ptr noundef nonnull %26, ptr noundef nonnull %2, i16 noundef zeroext %4) #2
  %38 = tail call i32 @HAL_UART_Transmit_DMA(ptr noundef nonnull %26, ptr noundef nonnull %1, i16 noundef zeroext %3) #2
  %39 = or i32 %38, %37
  br label %44

40:                                               ; preds = %20
  %41 = tail call i32 @HAL_UART_Receive_IT(ptr noundef nonnull %26, ptr noundef nonnull %2, i16 noundef zeroext %4) #2
  %42 = tail call i32 @HAL_UART_Transmit_IT(ptr noundef nonnull %26, ptr noundef nonnull %1, i16 noundef zeroext %3) #2
  %43 = or i32 %42, %41
  br label %44

44:                                               ; preds = %40, %36
  %.0 = phi i32 [ %39, %36 ], [ %43, %40 ]
  %45 = icmp eq i32 %.0, 0
  br i1 %45, label %46, label %53

46:                                               ; preds = %44
  %47 = load ptr, ptr %21, align 8, !tbaa !23
  %48 = getelementptr inbounds i8, ptr %0, i64 748
  %49 = load i32, ptr %48, align 4, !tbaa !31
  %50 = mul i32 %49, 1000
  %51 = udiv i32 %50, 1000
  %52 = tail call i64 @xQueueSemaphoreTake(ptr noundef %47, i32 noundef %51) #2
  %.not = icmp eq i64 %52, 0
  %spec.select = select i1 %.not, i32 116, i32 0
  br label %53

53:                                               ; preds = %46, %44
  %.1 = phi i32 [ %.0, %44 ], [ %spec.select, %46 ]
  store i32 0, ptr %24, align 8, !tbaa !32
  store i32 0, ptr %25, align 4, !tbaa !33
  %54 = load ptr, ptr %11, align 8, !tbaa !5
  %55 = tail call i64 @xQueueGenericSend(ptr noundef %54, ptr noundef null, i32 noundef 0, i64 noundef 0) #2
  %56 = load ptr, ptr %16, align 8, !tbaa !22
  %57 = tail call i64 @xQueueGenericSend(ptr noundef %56, ptr noundef null, i32 noundef 0, i64 noundef 0) #2
  br label %58

58:                                               ; preds = %10, %15, %5, %53
  %.042 = phi i32 [ %.1, %53 ], [ 22, %5 ], [ 16, %15 ], [ 16, %10 ]
  ret i32 %.042
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 792}
!6 = !{!"", !7, i64 0, !7, i64 32, !9, i64 64, !11, i64 152, !16, i64 336, !16, i64 528, !13, i64 720, !10, i64 728, !10, i64 736, !13, i64 744, !13, i64 748, !13, i64 752, !13, i64 756, !13, i64 760, !20, i64 768}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"file_operations", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!"__UART_HandleTypeDef", !10, i64 0, !12, i64 8, !14, i64 44, !10, i64 88, !15, i64 96, !15, i64 98, !10, i64 104, !15, i64 112, !15, i64 114, !15, i64 116, !13, i64 120, !15, i64 124, !15, i64 126, !13, i64 128, !10, i64 136, !10, i64 144, !10, i64 152, !10, i64 160, !13, i64 168, !13, i64 172, !13, i64 176, !13, i64 180}
!12 = !{!"", !13, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !13, i64 32}
!13 = !{!"int", !7, i64 0}
!14 = !{!"", !13, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !13, i64 32, !13, i64 36}
!15 = !{!"short", !7, i64 0}
!16 = !{!"", !17, i64 0, !13, i64 184, !19, i64 188}
!17 = !{!"__DMA_HandleTypeDef", !10, i64 0, !18, i64 8, !13, i64 56, !13, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !13, i64 120, !13, i64 124, !13, i64 128, !10, i64 136, !10, i64 144, !13, i64 152, !10, i64 160, !10, i64 168, !13, i64 176}
!18 = !{!"", !13, i64 0, !13, i64 4, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !13, i64 32, !13, i64 36, !13, i64 40, !13, i64 44}
!19 = !{!"", !13, i64 0}
!20 = !{!"", !13, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !13, i64 40, !13, i64 44, !13, i64 48, !13, i64 52, !10, i64 56, !10, i64 64, !10, i64 72, !10, i64 80, !13, i64 88, !21, i64 92, !21, i64 93, !21, i64 94, !21, i64 95, !21, i64 96}
!21 = !{!"_Bool", !7, i64 0}
!22 = !{!6, !10, i64 800}
!23 = !{!6, !10, i64 784}
!24 = !{!13, !13, i64 0}
!25 = !{!6, !10, i64 152}
!26 = !{!18, !13, i64 32}
!27 = !{!18, !13, i64 0}
!28 = !{!6, !21, i64 863}
!29 = !{i8 0, i8 2}
!30 = !{}
!31 = !{!6, !13, i64 748}
!32 = !{!6, !13, i64 808}
!33 = !{!6, !13, i64 812}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass