; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_DMA_Abort_IT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_IC_Stop_DMA(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  %6 = load ptr, ptr %3, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %6, i32 0, i32 0
  %8 = load ptr, ptr %7, align 8, !tbaa !11
  %9 = load i32, ptr %4, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %8, i32 noundef %9, i32 noundef 0)
  %10 = load i32, ptr %4, align 4, !tbaa !9
  switch i32 %10, label %67 [
    i32 0, label %11
    i32 4, label %25
    i32 8, label %39
    i32 12, label %53
  ]

11:                                               ; preds = %2
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 0
  %14 = load ptr, ptr %13, align 8, !tbaa !11
  %15 = getelementptr inbounds %struct.TIM_TypeDef, ptr %14, i32 0, i32 3
  %16 = load volatile i32, ptr %15, align 4, !tbaa !14
  %17 = zext i32 %16 to i64
  %18 = and i64 %17, -513
  %19 = trunc i64 %18 to i32
  store volatile i32 %19, ptr %15, align 4, !tbaa !14
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %20, i32 0, i32 3
  %22 = getelementptr inbounds [7 x ptr], ptr %21, i64 0, i64 1
  %23 = load ptr, ptr %22, align 8, !tbaa !5
  %24 = call i32 @HAL_DMA_Abort_IT(ptr noundef %23)
  br label %68

25:                                               ; preds = %2
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %26, i32 0, i32 0
  %28 = load ptr, ptr %27, align 8, !tbaa !11
  %29 = getelementptr inbounds %struct.TIM_TypeDef, ptr %28, i32 0, i32 3
  %30 = load volatile i32, ptr %29, align 4, !tbaa !14
  %31 = zext i32 %30 to i64
  %32 = and i64 %31, -1025
  %33 = trunc i64 %32 to i32
  store volatile i32 %33, ptr %29, align 4, !tbaa !14
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %34, i32 0, i32 3
  %36 = getelementptr inbounds [7 x ptr], ptr %35, i64 0, i64 2
  %37 = load ptr, ptr %36, align 8, !tbaa !5
  %38 = call i32 @HAL_DMA_Abort_IT(ptr noundef %37)
  br label %68

39:                                               ; preds = %2
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %40, i32 0, i32 0
  %42 = load ptr, ptr %41, align 8, !tbaa !11
  %43 = getelementptr inbounds %struct.TIM_TypeDef, ptr %42, i32 0, i32 3
  %44 = load volatile i32, ptr %43, align 4, !tbaa !14
  %45 = zext i32 %44 to i64
  %46 = and i64 %45, -2049
  %47 = trunc i64 %46 to i32
  store volatile i32 %47, ptr %43, align 4, !tbaa !14
  %48 = load ptr, ptr %3, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %48, i32 0, i32 3
  %50 = getelementptr inbounds [7 x ptr], ptr %49, i64 0, i64 3
  %51 = load ptr, ptr %50, align 8, !tbaa !5
  %52 = call i32 @HAL_DMA_Abort_IT(ptr noundef %51)
  br label %68

53:                                               ; preds = %2
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !11
  %57 = getelementptr inbounds %struct.TIM_TypeDef, ptr %56, i32 0, i32 3
  %58 = load volatile i32, ptr %57, align 4, !tbaa !14
  %59 = zext i32 %58 to i64
  %60 = and i64 %59, -4097
  %61 = trunc i64 %60 to i32
  store volatile i32 %61, ptr %57, align 4, !tbaa !14
  %62 = load ptr, ptr %3, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %62, i32 0, i32 3
  %64 = getelementptr inbounds [7 x ptr], ptr %63, i64 0, i64 4
  %65 = load ptr, ptr %64, align 8, !tbaa !5
  %66 = call i32 @HAL_DMA_Abort_IT(ptr noundef %65)
  br label %68

67:                                               ; preds = %2
  store i32 1, ptr %5, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %67, %53, %39, %25, %11
  %69 = load i32, ptr %5, align 4, !tbaa !9
  %70 = icmp eq i32 %69, 0
  br i1 %70, label %71, label %181

71:                                               ; preds = %68
  br label %72

72:                                               ; preds = %71
  %73 = load ptr, ptr %3, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %73, i32 0, i32 0
  %75 = load ptr, ptr %74, align 8, !tbaa !11
  %76 = getelementptr inbounds %struct.TIM_TypeDef, ptr %75, i32 0, i32 8
  %77 = load volatile i32, ptr %76, align 4, !tbaa !16
  %78 = and i32 %77, 4369
  %79 = zext i32 %78 to i64
  %80 = icmp eq i64 %79, 0
  br i1 %80, label %81, label %100

81:                                               ; preds = %72
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !11
  %85 = getelementptr inbounds %struct.TIM_TypeDef, ptr %84, i32 0, i32 8
  %86 = load volatile i32, ptr %85, align 4, !tbaa !16
  %87 = and i32 %86, 1092
  %88 = zext i32 %87 to i64
  %89 = icmp eq i64 %88, 0
  br i1 %89, label %90, label %99

90:                                               ; preds = %81
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !11
  %94 = getelementptr inbounds %struct.TIM_TypeDef, ptr %93, i32 0, i32 0
  %95 = load volatile i32, ptr %94, align 4, !tbaa !17
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, -2
  %98 = trunc i64 %97 to i32
  store volatile i32 %98, ptr %94, align 4, !tbaa !17
  br label %99

99:                                               ; preds = %90, %81
  br label %100

100:                                              ; preds = %99, %72
  br label %101

101:                                              ; preds = %100
  br label %102

102:                                              ; preds = %101
  %103 = load i32, ptr %4, align 4, !tbaa !9
  %104 = icmp eq i32 %103, 0
  br i1 %104, label %105, label %109

105:                                              ; preds = %102
  %106 = load ptr, ptr %3, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %106, i32 0, i32 6
  %108 = getelementptr inbounds [6 x i32], ptr %107, i64 0, i64 0
  store volatile i32 1, ptr %108, align 8, !tbaa !9
  br label %149

109:                                              ; preds = %102
  %110 = load i32, ptr %4, align 4, !tbaa !9
  %111 = icmp eq i32 %110, 4
  br i1 %111, label %112, label %116

112:                                              ; preds = %109
  %113 = load ptr, ptr %3, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %113, i32 0, i32 6
  %115 = getelementptr inbounds [6 x i32], ptr %114, i64 0, i64 1
  store volatile i32 1, ptr %115, align 4, !tbaa !9
  br label %147

116:                                              ; preds = %109
  %117 = load i32, ptr %4, align 4, !tbaa !9
  %118 = icmp eq i32 %117, 8
  br i1 %118, label %119, label %123

119:                                              ; preds = %116
  %120 = load ptr, ptr %3, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %120, i32 0, i32 6
  %122 = getelementptr inbounds [6 x i32], ptr %121, i64 0, i64 2
  store volatile i32 1, ptr %122, align 8, !tbaa !9
  br label %145

123:                                              ; preds = %116
  %124 = load i32, ptr %4, align 4, !tbaa !9
  %125 = icmp eq i32 %124, 12
  br i1 %125, label %126, label %130

126:                                              ; preds = %123
  %127 = load ptr, ptr %3, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %127, i32 0, i32 6
  %129 = getelementptr inbounds [6 x i32], ptr %128, i64 0, i64 3
  store volatile i32 1, ptr %129, align 4, !tbaa !9
  br label %143

130:                                              ; preds = %123
  %131 = load i32, ptr %4, align 4, !tbaa !9
  %132 = icmp eq i32 %131, 16
  br i1 %132, label %133, label %137

133:                                              ; preds = %130
  %134 = load ptr, ptr %3, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %134, i32 0, i32 6
  %136 = getelementptr inbounds [6 x i32], ptr %135, i64 0, i64 4
  store volatile i32 1, ptr %136, align 8, !tbaa !9
  br label %141

137:                                              ; preds = %130
  %138 = load ptr, ptr %3, align 8, !tbaa !5
  %139 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %138, i32 0, i32 6
  %140 = getelementptr inbounds [6 x i32], ptr %139, i64 0, i64 5
  store volatile i32 1, ptr %140, align 4, !tbaa !9
  br label %141

141:                                              ; preds = %137, %133
  %142 = phi i32 [ 1, %133 ], [ 1, %137 ]
  br label %143

143:                                              ; preds = %141, %126
  %144 = phi i32 [ 1, %126 ], [ %142, %141 ]
  br label %145

145:                                              ; preds = %143, %119
  %146 = phi i32 [ 1, %119 ], [ %144, %143 ]
  br label %147

147:                                              ; preds = %145, %112
  %148 = phi i32 [ 1, %112 ], [ %146, %145 ]
  br label %149

149:                                              ; preds = %147, %105
  %150 = phi i32 [ 1, %105 ], [ %148, %147 ]
  %151 = load i32, ptr %4, align 4, !tbaa !9
  %152 = icmp eq i32 %151, 0
  br i1 %152, label %153, label %157

153:                                              ; preds = %149
  %154 = load ptr, ptr %3, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %154, i32 0, i32 7
  %156 = getelementptr inbounds [4 x i32], ptr %155, i64 0, i64 0
  store volatile i32 1, ptr %156, align 8, !tbaa !9
  br label %179

157:                                              ; preds = %149
  %158 = load i32, ptr %4, align 4, !tbaa !9
  %159 = icmp eq i32 %158, 4
  br i1 %159, label %160, label %164

160:                                              ; preds = %157
  %161 = load ptr, ptr %3, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %161, i32 0, i32 7
  %163 = getelementptr inbounds [4 x i32], ptr %162, i64 0, i64 1
  store volatile i32 1, ptr %163, align 4, !tbaa !9
  br label %177

164:                                              ; preds = %157
  %165 = load i32, ptr %4, align 4, !tbaa !9
  %166 = icmp eq i32 %165, 8
  br i1 %166, label %167, label %171

167:                                              ; preds = %164
  %168 = load ptr, ptr %3, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %168, i32 0, i32 7
  %170 = getelementptr inbounds [4 x i32], ptr %169, i64 0, i64 2
  store volatile i32 1, ptr %170, align 8, !tbaa !9
  br label %175

171:                                              ; preds = %164
  %172 = load ptr, ptr %3, align 8, !tbaa !5
  %173 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %172, i32 0, i32 7
  %174 = getelementptr inbounds [4 x i32], ptr %173, i64 0, i64 3
  store volatile i32 1, ptr %174, align 4, !tbaa !9
  br label %175

175:                                              ; preds = %171, %167
  %176 = phi i32 [ 1, %167 ], [ 1, %171 ]
  br label %177

177:                                              ; preds = %175, %160
  %178 = phi i32 [ 1, %160 ], [ %176, %175 ]
  br label %179

179:                                              ; preds = %177, %153
  %180 = phi i32 [ 1, %153 ], [ %178, %177 ]
  br label %181

181:                                              ; preds = %179, %68
  %182 = load i32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 %182
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 32}
!17 = !{!15, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.HAL_TIM_IC_Stop_DMA = private unnamed_addr constant [4 x i32] [i32 -513, i32 -1025, i32 -2049, i32 -4097], align 4

declare i32 @HAL_DMA_Abort_IT(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_TIM_IC_Stop_DMA(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @TIM_CCxChannelCmd(ptr noundef %3, i32 noundef %1, i32 noundef 0)
  %4 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  %5 = icmp ult i32 %4, 4
  br i1 %5, label %switch.lookup, label %54

switch.lookup:                                    ; preds = %2
  %6 = zext nneg i32 %4 to i64
  %switch.gep = getelementptr inbounds [4 x i32], ptr @switch.table.HAL_TIM_IC_Stop_DMA, i64 0, i64 %6
  %switch.load = load i32, ptr %switch.gep, align 4
  %7 = shl nuw nsw i32 %4, 3
  %8 = load ptr, ptr %0, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %8, i64 12
  %10 = load volatile i32, ptr %9, align 4, !tbaa !12
  %11 = and i32 %10, %switch.load
  store volatile i32 %11, ptr %9, align 4, !tbaa !12
  %12 = zext nneg i32 %7 to i64
  %13 = getelementptr inbounds i8, ptr %0, i64 %12
  %14 = getelementptr inbounds i8, ptr %13, i64 48
  %15 = load ptr, ptr %14, align 8, !tbaa !14
  %16 = tail call i32 @HAL_DMA_Abort_IT(ptr noundef %15) #3
  %17 = load ptr, ptr %0, align 8, !tbaa !5
  %18 = getelementptr inbounds i8, ptr %17, i64 32
  %19 = load volatile i32, ptr %18, align 4, !tbaa !15
  %20 = and i32 %19, 4369
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %29

22:                                               ; preds = %switch.lookup
  %23 = load volatile i32, ptr %18, align 4, !tbaa !15
  %24 = and i32 %23, 1092
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %29

26:                                               ; preds = %22
  %27 = load volatile i32, ptr %17, align 4, !tbaa !16
  %28 = and i32 %27, -2
  store volatile i32 %28, ptr %17, align 4, !tbaa !16
  br label %29

29:                                               ; preds = %22, %26, %switch.lookup
  %30 = icmp eq i32 %1, 0
  br i1 %30, label %44, label %31

31:                                               ; preds = %29
  %32 = add i32 %1, -4
  %33 = tail call i32 @llvm.fshl.i32(i32 %32, i32 %32, i32 30)
  switch i32 %33, label %42 [
    i32 0, label %34
    i32 1, label %36
    i32 2, label %38
    i32 3, label %40
  ]

34:                                               ; preds = %31
  %35 = getelementptr inbounds i8, ptr %0, i64 108
  store volatile i32 1, ptr %35, align 4, !tbaa !17
  br label %47

36:                                               ; preds = %31
  %37 = getelementptr inbounds i8, ptr %0, i64 112
  store volatile i32 1, ptr %37, align 8, !tbaa !17
  br label %47

38:                                               ; preds = %31
  %39 = getelementptr inbounds i8, ptr %0, i64 116
  store volatile i32 1, ptr %39, align 4, !tbaa !17
  br label %47

40:                                               ; preds = %31
  %41 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 1, ptr %41, align 8, !tbaa !17
  br label %47

42:                                               ; preds = %31
  %43 = getelementptr inbounds i8, ptr %0, i64 124
  store volatile i32 1, ptr %43, align 4, !tbaa !17
  br label %47

44:                                               ; preds = %29
  %45 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 1, ptr %45, align 8, !tbaa !17
  %46 = getelementptr inbounds i8, ptr %0, i64 128
  store volatile i32 1, ptr %46, align 8, !tbaa !17
  br label %54

47:                                               ; preds = %40, %42, %34, %38, %36
  switch i32 %1, label %52 [
    i32 4, label %48
    i32 8, label %50
  ]

48:                                               ; preds = %47
  %49 = getelementptr inbounds i8, ptr %0, i64 132
  store volatile i32 1, ptr %49, align 4, !tbaa !17
  br label %54

50:                                               ; preds = %47
  %51 = getelementptr inbounds i8, ptr %0, i64 136
  store volatile i32 1, ptr %51, align 8, !tbaa !17
  br label %54

52:                                               ; preds = %47
  %53 = getelementptr inbounds i8, ptr %0, i64 140
  store volatile i32 1, ptr %53, align 4, !tbaa !17
  br label %54

54:                                               ; preds = %2, %50, %52, %44, %48
  %.035 = phi i32 [ 0, %50 ], [ 0, %52 ], [ 0, %44 ], [ 0, %48 ], [ 1, %2 ]
  ret i32 %.035
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!14 = !{!7, !7, i64 0}
!15 = !{!13, !11, i64 32}
!16 = !{!13, !11, i64 0}
!17 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass