; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_OnePulse_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_OnePulse_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca %struct.TIM_OC_InitTypeDef, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 28, ptr %11) #2
  %13 = load i32, ptr %8, align 4, !tbaa !9
  %14 = load i32, ptr %9, align 4, !tbaa !9
  %15 = icmp ne i32 %13, %14
  br i1 %15, label %16, label %187

16:                                               ; preds = %4
  br label %17

17:                                               ; preds = %16
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %18, i32 0, i32 4
  %20 = load i32, ptr %19, align 8, !tbaa !11
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 2, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %188

23:                                               ; preds = %17
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %24, i32 0, i32 4
  store i32 1, ptr %25, align 8, !tbaa !11
  br label %26

26:                                               ; preds = %23
  br label %27

27:                                               ; preds = %26
  br label %28

28:                                               ; preds = %27
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %29, i32 0, i32 5
  store volatile i32 2, ptr %30, align 4, !tbaa !14
  %31 = load ptr, ptr %7, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %31, i32 0, i32 0
  %33 = load i32, ptr %32, align 4, !tbaa !15
  %34 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 0
  store i32 %33, ptr %34, align 4, !tbaa !17
  %35 = load ptr, ptr %7, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !19
  %38 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 1
  store i32 %37, ptr %38, align 4, !tbaa !20
  %39 = load ptr, ptr %7, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %39, i32 0, i32 2
  %41 = load i32, ptr %40, align 4, !tbaa !21
  %42 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 2
  store i32 %41, ptr %42, align 4, !tbaa !22
  %43 = load ptr, ptr %7, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %43, i32 0, i32 3
  %45 = load i32, ptr %44, align 4, !tbaa !23
  %46 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 3
  store i32 %45, ptr %46, align 4, !tbaa !24
  %47 = load ptr, ptr %7, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %47, i32 0, i32 4
  %49 = load i32, ptr %48, align 4, !tbaa !25
  %50 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 5
  store i32 %49, ptr %50, align 4, !tbaa !26
  %51 = load ptr, ptr %7, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %51, i32 0, i32 5
  %53 = load i32, ptr %52, align 4, !tbaa !27
  %54 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %11, i32 0, i32 6
  store i32 %53, ptr %54, align 4, !tbaa !28
  %55 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %55, label %64 [
    i32 0, label %56
    i32 4, label %60
  ]

56:                                               ; preds = %28
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !29
  call void @TIM_OC1_SetConfig(ptr noundef %59, ptr noundef %11)
  br label %65

60:                                               ; preds = %28
  %61 = load ptr, ptr %6, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !29
  call void @TIM_OC2_SetConfig(ptr noundef %63, ptr noundef %11)
  br label %65

64:                                               ; preds = %28
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %64, %60, %56
  %66 = load i32, ptr %10, align 4, !tbaa !9
  %67 = icmp eq i32 %66, 0
  br i1 %67, label %68, label %178

68:                                               ; preds = %65
  %69 = load i32, ptr %9, align 4, !tbaa !9
  switch i32 %69, label %176 [
    i32 0, label %70
    i32 4, label %123
  ]

70:                                               ; preds = %68
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %71, i32 0, i32 0
  %73 = load ptr, ptr %72, align 8, !tbaa !29
  %74 = load ptr, ptr %7, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %74, i32 0, i32 6
  %76 = load i32, ptr %75, align 4, !tbaa !30
  %77 = load ptr, ptr %7, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %77, i32 0, i32 7
  %79 = load i32, ptr %78, align 4, !tbaa !31
  %80 = load ptr, ptr %7, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %80, i32 0, i32 8
  %82 = load i32, ptr %81, align 4, !tbaa !32
  call void @TIM_TI1_SetConfig(ptr noundef %73, i32 noundef %76, i32 noundef %79, i32 noundef %82)
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %83, i32 0, i32 0
  %85 = load ptr, ptr %84, align 8, !tbaa !29
  %86 = getelementptr inbounds %struct.TIM_TypeDef, ptr %85, i32 0, i32 6
  %87 = load volatile i32, ptr %86, align 4, !tbaa !33
  %88 = zext i32 %87 to i64
  %89 = and i64 %88, -13
  %90 = trunc i64 %89 to i32
  store volatile i32 %90, ptr %86, align 4, !tbaa !33
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !29
  %94 = getelementptr inbounds %struct.TIM_TypeDef, ptr %93, i32 0, i32 2
  %95 = load volatile i32, ptr %94, align 4, !tbaa !35
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, -3145841
  %98 = trunc i64 %97 to i32
  store volatile i32 %98, ptr %94, align 4, !tbaa !35
  %99 = load ptr, ptr %6, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %99, i32 0, i32 0
  %101 = load ptr, ptr %100, align 8, !tbaa !29
  %102 = getelementptr inbounds %struct.TIM_TypeDef, ptr %101, i32 0, i32 2
  %103 = load volatile i32, ptr %102, align 4, !tbaa !35
  %104 = zext i32 %103 to i64
  %105 = or i64 %104, 80
  %106 = trunc i64 %105 to i32
  store volatile i32 %106, ptr %102, align 4, !tbaa !35
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %107, i32 0, i32 0
  %109 = load ptr, ptr %108, align 8, !tbaa !29
  %110 = getelementptr inbounds %struct.TIM_TypeDef, ptr %109, i32 0, i32 2
  %111 = load volatile i32, ptr %110, align 4, !tbaa !35
  %112 = zext i32 %111 to i64
  %113 = and i64 %112, -65544
  %114 = trunc i64 %113 to i32
  store volatile i32 %114, ptr %110, align 4, !tbaa !35
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !29
  %118 = getelementptr inbounds %struct.TIM_TypeDef, ptr %117, i32 0, i32 2
  %119 = load volatile i32, ptr %118, align 4, !tbaa !35
  %120 = zext i32 %119 to i64
  %121 = or i64 %120, 6
  %122 = trunc i64 %121 to i32
  store volatile i32 %122, ptr %118, align 4, !tbaa !35
  br label %177

123:                                              ; preds = %68
  %124 = load ptr, ptr %6, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !29
  %127 = load ptr, ptr %7, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %127, i32 0, i32 6
  %129 = load i32, ptr %128, align 4, !tbaa !30
  %130 = load ptr, ptr %7, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %130, i32 0, i32 7
  %132 = load i32, ptr %131, align 4, !tbaa !31
  %133 = load ptr, ptr %7, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %133, i32 0, i32 8
  %135 = load i32, ptr %134, align 4, !tbaa !32
  call void @TIM_TI2_SetConfig(ptr noundef %126, i32 noundef %129, i32 noundef %132, i32 noundef %135)
  %136 = load ptr, ptr %6, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %136, i32 0, i32 0
  %138 = load ptr, ptr %137, align 8, !tbaa !29
  %139 = getelementptr inbounds %struct.TIM_TypeDef, ptr %138, i32 0, i32 6
  %140 = load volatile i32, ptr %139, align 4, !tbaa !33
  %141 = zext i32 %140 to i64
  %142 = and i64 %141, -3073
  %143 = trunc i64 %142 to i32
  store volatile i32 %143, ptr %139, align 4, !tbaa !33
  %144 = load ptr, ptr %6, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %144, i32 0, i32 0
  %146 = load ptr, ptr %145, align 8, !tbaa !29
  %147 = getelementptr inbounds %struct.TIM_TypeDef, ptr %146, i32 0, i32 2
  %148 = load volatile i32, ptr %147, align 4, !tbaa !35
  %149 = zext i32 %148 to i64
  %150 = and i64 %149, -3145841
  %151 = trunc i64 %150 to i32
  store volatile i32 %151, ptr %147, align 4, !tbaa !35
  %152 = load ptr, ptr %6, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !29
  %155 = getelementptr inbounds %struct.TIM_TypeDef, ptr %154, i32 0, i32 2
  %156 = load volatile i32, ptr %155, align 4, !tbaa !35
  %157 = zext i32 %156 to i64
  %158 = or i64 %157, 96
  %159 = trunc i64 %158 to i32
  store volatile i32 %159, ptr %155, align 4, !tbaa !35
  %160 = load ptr, ptr %6, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %160, i32 0, i32 0
  %162 = load ptr, ptr %161, align 8, !tbaa !29
  %163 = getelementptr inbounds %struct.TIM_TypeDef, ptr %162, i32 0, i32 2
  %164 = load volatile i32, ptr %163, align 4, !tbaa !35
  %165 = zext i32 %164 to i64
  %166 = and i64 %165, -65544
  %167 = trunc i64 %166 to i32
  store volatile i32 %167, ptr %163, align 4, !tbaa !35
  %168 = load ptr, ptr %6, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %168, i32 0, i32 0
  %170 = load ptr, ptr %169, align 8, !tbaa !29
  %171 = getelementptr inbounds %struct.TIM_TypeDef, ptr %170, i32 0, i32 2
  %172 = load volatile i32, ptr %171, align 4, !tbaa !35
  %173 = zext i32 %172 to i64
  %174 = or i64 %173, 6
  %175 = trunc i64 %174 to i32
  store volatile i32 %175, ptr %171, align 4, !tbaa !35
  br label %177

176:                                              ; preds = %68
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %177

177:                                              ; preds = %176, %123, %70
  br label %178

178:                                              ; preds = %177, %65
  %179 = load ptr, ptr %6, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %179, i32 0, i32 5
  store volatile i32 1, ptr %180, align 4, !tbaa !14
  br label %181

181:                                              ; preds = %178
  %182 = load ptr, ptr %6, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %182, i32 0, i32 4
  store i32 0, ptr %183, align 8, !tbaa !11
  br label %184

184:                                              ; preds = %181
  br label %185

185:                                              ; preds = %184
  %186 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %186, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %188

187:                                              ; preds = %4
  store i32 1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %188

188:                                              ; preds = %187, %185, %22
  call void @llvm.lifetime.end.p0(i64 28, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %189 = load i32, ptr %5, align 4
  ret i32 %189
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !10, i64 100}
!15 = !{!16, !10, i64 0}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32}
!17 = !{!18, !10, i64 0}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!19 = !{!16, !10, i64 4}
!20 = !{!18, !10, i64 4}
!21 = !{!16, !10, i64 8}
!22 = !{!18, !10, i64 8}
!23 = !{!16, !10, i64 12}
!24 = !{!18, !10, i64 12}
!25 = !{!16, !10, i64 16}
!26 = !{!18, !10, i64 20}
!27 = !{!16, !10, i64 20}
!28 = !{!18, !10, i64 24}
!29 = !{!12, !6, i64 0}
!30 = !{!16, !10, i64 24}
!31 = !{!16, !10, i64 28}
!32 = !{!16, !10, i64 32}
!33 = !{!34, !10, i64 24}
!34 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!35 = !{!34, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_OnePulse_ConfigChannel(ptr noundef %0, ptr nocapture noundef readonly %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = alloca %struct.TIM_OC_InitTypeDef, align 16
  call void @llvm.lifetime.start.p0(i64 28, ptr nonnull %5) #2
  %.not = icmp eq i32 %2, %3
  br i1 %.not, label %50, label %6

6:                                                ; preds = %4
  %7 = getelementptr inbounds i8, ptr %0, i64 96
  %8 = load i32, ptr %7, align 8, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %50, label %10

10:                                               ; preds = %6
  store i32 1, ptr %7, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %0, i64 100
  store volatile i32 2, ptr %11, align 4, !tbaa !12
  %12 = load <4 x i32>, ptr %1, align 4, !tbaa !13
  store <4 x i32> %12, ptr %5, align 16, !tbaa !13
  %13 = getelementptr inbounds i8, ptr %1, i64 16
  %14 = getelementptr inbounds i8, ptr %5, i64 20
  %15 = load <2 x i32>, ptr %13, align 4, !tbaa !13
  store <2 x i32> %15, ptr %14, align 4, !tbaa !13
  switch i32 %2, label %49 [
    i32 0, label %16
    i32 4, label %18
  ]

16:                                               ; preds = %10
  %17 = load ptr, ptr %0, align 8, !tbaa !14
  call void @TIM_OC1_SetConfig(ptr noundef %17, ptr noundef nonnull %5)
  br label %.critedge

18:                                               ; preds = %10
  %19 = load ptr, ptr %0, align 8, !tbaa !14
  call void @TIM_OC2_SetConfig(ptr noundef %19, ptr noundef nonnull %5)
  br label %.critedge

.critedge:                                        ; preds = %16, %18
  switch i32 %3, label %49 [
    i32 0, label %20
    i32 4, label %28
  ]

20:                                               ; preds = %.critedge
  %21 = load ptr, ptr %0, align 8, !tbaa !14
  %22 = getelementptr inbounds i8, ptr %1, i64 24
  %23 = load i32, ptr %22, align 4, !tbaa !15
  %24 = getelementptr inbounds i8, ptr %1, i64 28
  %25 = load i32, ptr %24, align 4, !tbaa !17
  %26 = getelementptr inbounds i8, ptr %1, i64 32
  %27 = load i32, ptr %26, align 4, !tbaa !18
  call void @TIM_TI1_SetConfig(ptr noundef %21, i32 noundef %23, i32 noundef %25, i32 noundef %27)
  br label %.sink.split

28:                                               ; preds = %.critedge
  %29 = load ptr, ptr %0, align 8, !tbaa !14
  %30 = getelementptr inbounds i8, ptr %1, i64 24
  %31 = load i32, ptr %30, align 4, !tbaa !15
  %32 = getelementptr inbounds i8, ptr %1, i64 28
  %33 = load i32, ptr %32, align 4, !tbaa !17
  %34 = getelementptr inbounds i8, ptr %1, i64 32
  %35 = load i32, ptr %34, align 4, !tbaa !18
  call void @TIM_TI2_SetConfig(ptr noundef %29, i32 noundef %31, i32 noundef %33, i32 noundef %35)
  br label %.sink.split

.sink.split:                                      ; preds = %28, %20
  %.sink58 = phi i32 [ -13, %20 ], [ -3073, %28 ]
  %.sink49 = phi i32 [ 80, %20 ], [ 96, %28 ]
  %36 = load ptr, ptr %0, align 8, !tbaa !14
  %37 = getelementptr inbounds i8, ptr %36, i64 24
  %38 = load volatile i32, ptr %37, align 4, !tbaa !19
  %39 = and i32 %38, %.sink58
  store volatile i32 %39, ptr %37, align 4, !tbaa !19
  %40 = getelementptr inbounds i8, ptr %36, i64 8
  %41 = load volatile i32, ptr %40, align 4, !tbaa !21
  %42 = and i32 %41, -3145841
  store volatile i32 %42, ptr %40, align 4, !tbaa !21
  %43 = load volatile i32, ptr %40, align 4, !tbaa !21
  %44 = or i32 %43, %.sink49
  store volatile i32 %44, ptr %40, align 4, !tbaa !21
  %45 = load volatile i32, ptr %40, align 4, !tbaa !21
  %46 = and i32 %45, -65544
  store volatile i32 %46, ptr %40, align 4, !tbaa !21
  %47 = load volatile i32, ptr %40, align 4, !tbaa !21
  %48 = or i32 %47, 6
  store volatile i32 %48, ptr %40, align 4, !tbaa !21
  br label %49

49:                                               ; preds = %.sink.split, %.critedge, %10
  %.1 = phi i32 [ 1, %10 ], [ 1, %.critedge ], [ 0, %.sink.split ]
  store volatile i32 1, ptr %11, align 4, !tbaa !12
  store i32 0, ptr %7, align 8, !tbaa !5
  br label %50

50:                                               ; preds = %4, %6, %49
  %.037 = phi i32 [ %.1, %49 ], [ 2, %6 ], [ 1, %4 ]
  call void @llvm.lifetime.end.p0(i64 28, ptr nonnull %5) #2
  ret i32 %.037
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 100}
!13 = !{!11, !11, i64 0}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !11, i64 24}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!17 = !{!16, !11, i64 28}
!18 = !{!16, !11, i64 32}
!19 = !{!20, !11, i64 24}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!21 = !{!20, !11, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass