; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_IC_InitTypeDef = type { i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_IC_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %11, i32 0, i32 4
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %166

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 4
  store i32 1, ptr %18, align 8, !tbaa !11
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load i32, ptr %7, align 4, !tbaa !9
  %23 = icmp eq i32 %22, 0
  br i1 %23, label %24, label %54

24:                                               ; preds = %21
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !14
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %28, i32 0, i32 0
  %30 = load i32, ptr %29, align 4, !tbaa !15
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %31, i32 0, i32 1
  %33 = load i32, ptr %32, align 4, !tbaa !17
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %34, i32 0, i32 3
  %36 = load i32, ptr %35, align 4, !tbaa !18
  call void @TIM_TI1_SetConfig(ptr noundef %27, i32 noundef %30, i32 noundef %33, i32 noundef %36)
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !14
  %40 = getelementptr inbounds %struct.TIM_TypeDef, ptr %39, i32 0, i32 6
  %41 = load volatile i32, ptr %40, align 4, !tbaa !19
  %42 = zext i32 %41 to i64
  %43 = and i64 %42, -13
  %44 = trunc i64 %43 to i32
  store volatile i32 %44, ptr %40, align 4, !tbaa !19
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %45, i32 0, i32 2
  %47 = load i32, ptr %46, align 4, !tbaa !21
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %48, i32 0, i32 0
  %50 = load ptr, ptr %49, align 8, !tbaa !14
  %51 = getelementptr inbounds %struct.TIM_TypeDef, ptr %50, i32 0, i32 6
  %52 = load volatile i32, ptr %51, align 4, !tbaa !19
  %53 = or i32 %52, %47
  store volatile i32 %53, ptr %51, align 4, !tbaa !19
  br label %159

54:                                               ; preds = %21
  %55 = load i32, ptr %7, align 4, !tbaa !9
  %56 = icmp eq i32 %55, 4
  br i1 %56, label %57, label %88

57:                                               ; preds = %54
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !14
  %61 = load ptr, ptr %6, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %61, i32 0, i32 0
  %63 = load i32, ptr %62, align 4, !tbaa !15
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %64, i32 0, i32 1
  %66 = load i32, ptr %65, align 4, !tbaa !17
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %67, i32 0, i32 3
  %69 = load i32, ptr %68, align 4, !tbaa !18
  call void @TIM_TI2_SetConfig(ptr noundef %60, i32 noundef %63, i32 noundef %66, i32 noundef %69)
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %70, i32 0, i32 0
  %72 = load ptr, ptr %71, align 8, !tbaa !14
  %73 = getelementptr inbounds %struct.TIM_TypeDef, ptr %72, i32 0, i32 6
  %74 = load volatile i32, ptr %73, align 4, !tbaa !19
  %75 = zext i32 %74 to i64
  %76 = and i64 %75, -3073
  %77 = trunc i64 %76 to i32
  store volatile i32 %77, ptr %73, align 4, !tbaa !19
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %78, i32 0, i32 2
  %80 = load i32, ptr %79, align 4, !tbaa !21
  %81 = shl i32 %80, 8
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !14
  %85 = getelementptr inbounds %struct.TIM_TypeDef, ptr %84, i32 0, i32 6
  %86 = load volatile i32, ptr %85, align 4, !tbaa !19
  %87 = or i32 %86, %81
  store volatile i32 %87, ptr %85, align 4, !tbaa !19
  br label %158

88:                                               ; preds = %54
  %89 = load i32, ptr %7, align 4, !tbaa !9
  %90 = icmp eq i32 %89, 8
  br i1 %90, label %91, label %121

91:                                               ; preds = %88
  %92 = load ptr, ptr %5, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %92, i32 0, i32 0
  %94 = load ptr, ptr %93, align 8, !tbaa !14
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %95, i32 0, i32 0
  %97 = load i32, ptr %96, align 4, !tbaa !15
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %98, i32 0, i32 1
  %100 = load i32, ptr %99, align 4, !tbaa !17
  %101 = load ptr, ptr %6, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %101, i32 0, i32 3
  %103 = load i32, ptr %102, align 4, !tbaa !18
  call void @TIM_TI3_SetConfig(ptr noundef %94, i32 noundef %97, i32 noundef %100, i32 noundef %103)
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %104, i32 0, i32 0
  %106 = load ptr, ptr %105, align 8, !tbaa !14
  %107 = getelementptr inbounds %struct.TIM_TypeDef, ptr %106, i32 0, i32 7
  %108 = load volatile i32, ptr %107, align 4, !tbaa !22
  %109 = zext i32 %108 to i64
  %110 = and i64 %109, -13
  %111 = trunc i64 %110 to i32
  store volatile i32 %111, ptr %107, align 4, !tbaa !22
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %112, i32 0, i32 2
  %114 = load i32, ptr %113, align 4, !tbaa !21
  %115 = load ptr, ptr %5, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !14
  %118 = getelementptr inbounds %struct.TIM_TypeDef, ptr %117, i32 0, i32 7
  %119 = load volatile i32, ptr %118, align 4, !tbaa !22
  %120 = or i32 %119, %114
  store volatile i32 %120, ptr %118, align 4, !tbaa !22
  br label %157

121:                                              ; preds = %88
  %122 = load i32, ptr %7, align 4, !tbaa !9
  %123 = icmp eq i32 %122, 12
  br i1 %123, label %124, label %155

124:                                              ; preds = %121
  %125 = load ptr, ptr %5, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %125, i32 0, i32 0
  %127 = load ptr, ptr %126, align 8, !tbaa !14
  %128 = load ptr, ptr %6, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %128, i32 0, i32 0
  %130 = load i32, ptr %129, align 4, !tbaa !15
  %131 = load ptr, ptr %6, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %131, i32 0, i32 1
  %133 = load i32, ptr %132, align 4, !tbaa !17
  %134 = load ptr, ptr %6, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %134, i32 0, i32 3
  %136 = load i32, ptr %135, align 4, !tbaa !18
  call void @TIM_TI4_SetConfig(ptr noundef %127, i32 noundef %130, i32 noundef %133, i32 noundef %136)
  %137 = load ptr, ptr %5, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %137, i32 0, i32 0
  %139 = load ptr, ptr %138, align 8, !tbaa !14
  %140 = getelementptr inbounds %struct.TIM_TypeDef, ptr %139, i32 0, i32 7
  %141 = load volatile i32, ptr %140, align 4, !tbaa !22
  %142 = zext i32 %141 to i64
  %143 = and i64 %142, -3073
  %144 = trunc i64 %143 to i32
  store volatile i32 %144, ptr %140, align 4, !tbaa !22
  %145 = load ptr, ptr %6, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %145, i32 0, i32 2
  %147 = load i32, ptr %146, align 4, !tbaa !21
  %148 = shl i32 %147, 8
  %149 = load ptr, ptr %5, align 8, !tbaa !5
  %150 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %149, i32 0, i32 0
  %151 = load ptr, ptr %150, align 8, !tbaa !14
  %152 = getelementptr inbounds %struct.TIM_TypeDef, ptr %151, i32 0, i32 7
  %153 = load volatile i32, ptr %152, align 4, !tbaa !22
  %154 = or i32 %153, %148
  store volatile i32 %154, ptr %152, align 4, !tbaa !22
  br label %156

155:                                              ; preds = %121
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %156

156:                                              ; preds = %155, %124
  br label %157

157:                                              ; preds = %156, %91
  br label %158

158:                                              ; preds = %157, %57
  br label %159

159:                                              ; preds = %158, %24
  br label %160

160:                                              ; preds = %159
  %161 = load ptr, ptr %5, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %161, i32 0, i32 4
  store i32 0, ptr %162, align 8, !tbaa !11
  br label %163

163:                                              ; preds = %160
  br label %164

164:                                              ; preds = %163
  %165 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %165, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %166

166:                                              ; preds = %164, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %167 = load i32, ptr %4, align 4
  ret i32 %167
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI3_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI4_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !6, i64 0}
!15 = !{!16, !10, i64 0}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!17 = !{!16, !10, i64 4}
!18 = !{!16, !10, i64 12}
!19 = !{!20, !10, i64 24}
!20 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!21 = !{!16, !10, i64 8}
!22 = !{!20, !10, i64 28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_IC_ConfigChannel(ptr nocapture noundef %0, ptr nocapture noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %66, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = tail call i32 @llvm.fshl.i32(i32 %2, i32 %2, i32 30)
  switch i32 %8, label %65 [
    i32 0, label %9
    i32 1, label %22
    i32 2, label %36
    i32 3, label %49
  ]

9:                                                ; preds = %7
  %10 = load ptr, ptr %0, align 8, !tbaa !12
  %11 = load i32, ptr %1, align 4, !tbaa !13
  %12 = getelementptr inbounds i8, ptr %1, i64 4
  %13 = load i32, ptr %12, align 4, !tbaa !15
  %14 = getelementptr inbounds i8, ptr %1, i64 12
  %15 = load i32, ptr %14, align 4, !tbaa !16
  tail call void @TIM_TI1_SetConfig(ptr noundef %10, i32 noundef %11, i32 noundef %13, i32 noundef %15)
  %16 = load ptr, ptr %0, align 8, !tbaa !12
  %17 = getelementptr inbounds i8, ptr %16, i64 24
  %18 = load volatile i32, ptr %17, align 4, !tbaa !17
  %19 = and i32 %18, -13
  store volatile i32 %19, ptr %17, align 4, !tbaa !17
  %20 = getelementptr inbounds i8, ptr %1, i64 8
  %21 = load i32, ptr %20, align 4, !tbaa !19
  br label %.sink.split

22:                                               ; preds = %7
  %23 = load ptr, ptr %0, align 8, !tbaa !12
  %24 = load i32, ptr %1, align 4, !tbaa !13
  %25 = getelementptr inbounds i8, ptr %1, i64 4
  %26 = load i32, ptr %25, align 4, !tbaa !15
  %27 = getelementptr inbounds i8, ptr %1, i64 12
  %28 = load i32, ptr %27, align 4, !tbaa !16
  tail call void @TIM_TI2_SetConfig(ptr noundef %23, i32 noundef %24, i32 noundef %26, i32 noundef %28)
  %29 = load ptr, ptr %0, align 8, !tbaa !12
  %30 = getelementptr inbounds i8, ptr %29, i64 24
  %31 = load volatile i32, ptr %30, align 4, !tbaa !17
  %32 = and i32 %31, -3073
  store volatile i32 %32, ptr %30, align 4, !tbaa !17
  %33 = getelementptr inbounds i8, ptr %1, i64 8
  %34 = load i32, ptr %33, align 4, !tbaa !19
  %35 = shl i32 %34, 8
  br label %.sink.split

36:                                               ; preds = %7
  %37 = load ptr, ptr %0, align 8, !tbaa !12
  %38 = load i32, ptr %1, align 4, !tbaa !13
  %39 = getelementptr inbounds i8, ptr %1, i64 4
  %40 = load i32, ptr %39, align 4, !tbaa !15
  %41 = getelementptr inbounds i8, ptr %1, i64 12
  %42 = load i32, ptr %41, align 4, !tbaa !16
  tail call void @TIM_TI3_SetConfig(ptr noundef %37, i32 noundef %38, i32 noundef %40, i32 noundef %42)
  %43 = load ptr, ptr %0, align 8, !tbaa !12
  %44 = getelementptr inbounds i8, ptr %43, i64 28
  %45 = load volatile i32, ptr %44, align 4, !tbaa !20
  %46 = and i32 %45, -13
  store volatile i32 %46, ptr %44, align 4, !tbaa !20
  %47 = getelementptr inbounds i8, ptr %1, i64 8
  %48 = load i32, ptr %47, align 4, !tbaa !19
  br label %.sink.split

49:                                               ; preds = %7
  %50 = load ptr, ptr %0, align 8, !tbaa !12
  %51 = load i32, ptr %1, align 4, !tbaa !13
  %52 = getelementptr inbounds i8, ptr %1, i64 4
  %53 = load i32, ptr %52, align 4, !tbaa !15
  %54 = getelementptr inbounds i8, ptr %1, i64 12
  %55 = load i32, ptr %54, align 4, !tbaa !16
  tail call void @TIM_TI4_SetConfig(ptr noundef %50, i32 noundef %51, i32 noundef %53, i32 noundef %55)
  %56 = load ptr, ptr %0, align 8, !tbaa !12
  %57 = getelementptr inbounds i8, ptr %56, i64 28
  %58 = load volatile i32, ptr %57, align 4, !tbaa !20
  %59 = and i32 %58, -3073
  store volatile i32 %59, ptr %57, align 4, !tbaa !20
  %60 = getelementptr inbounds i8, ptr %1, i64 8
  %61 = load i32, ptr %60, align 4, !tbaa !19
  %62 = shl i32 %61, 8
  br label %.sink.split

.sink.split:                                      ; preds = %22, %49, %36, %9
  %.sink = phi ptr [ %17, %9 ], [ %44, %36 ], [ %57, %49 ], [ %30, %22 ]
  %.sink40 = phi i32 [ %21, %9 ], [ %48, %36 ], [ %62, %49 ], [ %35, %22 ]
  %63 = load volatile i32, ptr %.sink, align 4, !tbaa !21
  %64 = or i32 %63, %.sink40
  store volatile i32 %64, ptr %.sink, align 4, !tbaa !21
  br label %65

65:                                               ; preds = %.sink.split, %7
  %.0 = phi i32 [ 1, %7 ], [ 0, %.sink.split ]
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %66

66:                                               ; preds = %3, %65
  %.036 = phi i32 [ %.0, %65 ], [ 2, %3 ]
  ret i32 %.036
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI3_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI4_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!14, !11, i64 0}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!15 = !{!14, !11, i64 4}
!16 = !{!14, !11, i64 12}
!17 = !{!18, !11, i64 24}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!19 = !{!14, !11, i64 8}
!20 = !{!18, !11, i64 28}
!21 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass