; LLVM IR from xing1357/SimpleOS :: src (ide)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @ide_polling(i8 noundef zeroext %0, i8 noundef zeroext %1) #1 {
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  store i8 %0, ptr %4, align 1, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !8
  br label %9

9:                                                ; preds = %16, %2
  %10 = load i32, ptr %6, align 4, !tbaa !8
  %11 = icmp slt i32 %10, 4
  br i1 %11, label %13, label %12

12:                                               ; preds = %9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %19

13:                                               ; preds = %9
  %14 = load i8, ptr %4, align 1, !tbaa !5
  %15 = call zeroext i8 @ide_read_register(i8 noundef zeroext %14, i8 noundef zeroext 12)
  br label %16

16:                                               ; preds = %13
  %17 = load i32, ptr %6, align 4, !tbaa !8
  %18 = add nsw i32 %17, 1
  store i32 %18, ptr %6, align 4, !tbaa !8
  br label %9, !llvm.loop !10

19:                                               ; preds = %12
  br label %20

20:                                               ; preds = %26, %19
  %21 = load i8, ptr %4, align 1, !tbaa !5
  %22 = call zeroext i8 @ide_read_register(i8 noundef zeroext %21, i8 noundef zeroext 7)
  %23 = zext i8 %22 to i32
  %24 = and i32 %23, 128
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %20
  br label %20, !llvm.loop !12

27:                                               ; preds = %20
  %28 = load i8, ptr %5, align 1, !tbaa !5
  %29 = icmp ne i8 %28, 0
  br i1 %29, label %30, label %54

30:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  %31 = load i8, ptr %4, align 1, !tbaa !5
  %32 = call zeroext i8 @ide_read_register(i8 noundef zeroext %31, i8 noundef zeroext 7)
  store i8 %32, ptr %7, align 1, !tbaa !5
  %33 = load i8, ptr %7, align 1, !tbaa !5
  %34 = zext i8 %33 to i32
  %35 = and i32 %34, 1
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %37, label %38

37:                                               ; preds = %30
  store i8 2, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %51

38:                                               ; preds = %30
  %39 = load i8, ptr %7, align 1, !tbaa !5
  %40 = zext i8 %39 to i32
  %41 = and i32 %40, 32
  %42 = icmp ne i32 %41, 0
  br i1 %42, label %43, label %44

43:                                               ; preds = %38
  store i8 1, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %51

44:                                               ; preds = %38
  %45 = load i8, ptr %7, align 1, !tbaa !5
  %46 = zext i8 %45 to i32
  %47 = and i32 %46, 8
  %48 = icmp eq i32 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %44
  store i8 3, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %51

50:                                               ; preds = %44
  store i32 0, ptr %8, align 4
  br label %51

51:                                               ; preds = %50, %49, %43, %37
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  %52 = load i32, ptr %8, align 4
  switch i32 %52, label %57 [
    i32 0, label %53
    i32 1, label %55
  ]

53:                                               ; preds = %51
  br label %54

54:                                               ; preds = %53, %27
  store i8 0, ptr %3, align 1
  br label %55

55:                                               ; preds = %54, %51
  %56 = load i8, ptr %3, align 1
  ret i8 %56

57:                                               ; preds = %51
  unreachable
}

; Function Attrs: nounwind uwtable
declare hidden zeroext i8 @ide_read_register(i8 noundef zeroext, i8 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local noundef zeroext i8 @ide_polling(i8 noundef zeroext %0, i8 noundef zeroext %1) local_unnamed_addr #0 {
.preheader.preheader:
  %2 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 12)
  %3 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 12)
  %4 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 12)
  %5 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 12)
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %.preheader
  %6 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 7)
  %.not = icmp sgt i8 %6, -1
  br i1 %.not, label %7, label %.preheader, !llvm.loop !5

7:                                                ; preds = %.preheader
  %.not13 = icmp eq i8 %1, 0
  br i1 %.not13, label %16, label %8

8:                                                ; preds = %7
  %9 = tail call zeroext i8 @ide_read_register(i8 noundef zeroext %0, i8 noundef zeroext 7)
  %10 = zext i8 %9 to i32
  %11 = and i32 %10, 1
  %.not14 = icmp eq i32 %11, 0
  br i1 %.not14, label %12, label %.thread

12:                                               ; preds = %8
  %13 = and i32 %10, 32
  %.not15 = icmp eq i32 %13, 0
  br i1 %.not15, label %14, label %.thread

14:                                               ; preds = %12
  %15 = and i32 %10, 8
  %.not20 = icmp eq i32 %15, 0
  br i1 %.not20, label %.thread, label %16

16:                                               ; preds = %14, %7
  br label %.thread

.thread:                                          ; preds = %12, %8, %14, %16
  %.1 = phi i8 [ 3, %14 ], [ 0, %16 ], [ 1, %12 ], [ 2, %8 ]
  ret i8 %.1
}

; Function Attrs: nounwind uwtable
declare hidden zeroext i8 @ide_read_register(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass