; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/periph/spi/stm32 (spi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.spi_t = type { %struct.__SPI_HandleTypeDef, ptr, ptr, ptr, %struct.dma_t, %struct.dma_t, i32, i32, %struct.spi_private_t }
%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_t = type { %struct.__DMA_HandleTypeDef, i32, %struct.dma_private_t }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_private_t = type { i32 }
%struct.spi_private_t = type { i32, ptr, ptr, ptr, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) #1

declare i64 @xQueueGenericSend(ptr noundef, ptr noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @spi_receive(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  %10 = load i16, ptr %7, align 2, !tbaa !9
  %11 = zext i16 %10 to i32
  %12 = icmp eq i32 %11, 0
  br i1 %12, label %16, label %13

13:                                               ; preds = %3
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %13, %3
  store i32 22, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %69

17:                                               ; preds = %13
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.spi_t, ptr %18, i32 0, i32 8
  %20 = getelementptr inbounds %struct.spi_private_t, ptr %19, i32 0, i32 2
  %21 = load ptr, ptr %20, align 8, !tbaa !13
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.spi_t, ptr %22, i32 0, i32 6
  %24 = load i32, ptr %23, align 8, !tbaa !22
  %25 = mul i32 %24, 1000
  %26 = udiv i32 %25, 1000
  %27 = call i64 @xQueueSemaphoreTake(ptr noundef %21, i32 noundef %26)
  %28 = icmp ne i64 %27, 0
  br i1 %28, label %30, label %29

29:                                               ; preds = %17
  store i32 116, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %69

30:                                               ; preds = %17
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.spi_t, ptr %31, i32 0, i32 8
  %33 = getelementptr inbounds %struct.spi_private_t, ptr %32, i32 0, i32 1
  %34 = load ptr, ptr %33, align 8, !tbaa !23
  %35 = call i64 @xQueueSemaphoreTake(ptr noundef %34, i32 noundef 0)
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.spi_t, ptr %36, i32 0, i32 8
  %38 = getelementptr inbounds %struct.spi_private_t, ptr %37, i32 0, i32 4
  store i32 2, ptr %38, align 8, !tbaa !24
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.spi_t, ptr %39, i32 0, i32 0
  %41 = load ptr, ptr %6, align 8, !tbaa !5
  %42 = load i16, ptr %7, align 2, !tbaa !9
  %43 = call i32 @HAL_SPI_Receive_DMA(ptr noundef %40, ptr noundef %41, i16 noundef zeroext %42)
  store i32 %43, ptr %8, align 4, !tbaa !11
  %44 = load i32, ptr %8, align 4, !tbaa !11
  %45 = icmp eq i32 %44, 0
  br i1 %45, label %46, label %59

46:                                               ; preds = %30
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.spi_t, ptr %47, i32 0, i32 8
  %49 = getelementptr inbounds %struct.spi_private_t, ptr %48, i32 0, i32 1
  %50 = load ptr, ptr %49, align 8, !tbaa !23
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.spi_t, ptr %51, i32 0, i32 6
  %53 = load i32, ptr %52, align 8, !tbaa !22
  %54 = mul i32 %53, 1000
  %55 = udiv i32 %54, 1000
  %56 = call i64 @xQueueSemaphoreTake(ptr noundef %50, i32 noundef %55)
  %57 = icmp ne i64 %56, 0
  br i1 %57, label %59, label %58

58:                                               ; preds = %46
  store i32 116, ptr %8, align 4, !tbaa !11
  br label %59

59:                                               ; preds = %58, %46, %30
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.spi_t, ptr %60, i32 0, i32 8
  %62 = getelementptr inbounds %struct.spi_private_t, ptr %61, i32 0, i32 4
  store i32 0, ptr %62, align 8, !tbaa !24
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.spi_t, ptr %63, i32 0, i32 8
  %65 = getelementptr inbounds %struct.spi_private_t, ptr %64, i32 0, i32 2
  %66 = load ptr, ptr %65, align 8, !tbaa !13
  %67 = call i64 @xQueueGenericSend(ptr noundef %66, ptr noundef null, i32 noundef 0, i64 noundef 0)
  %68 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %68, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %69

69:                                               ; preds = %59, %29, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %70 = load i32, ptr %4, align 4
  ret i32 %70
}

declare i32 @HAL_SPI_Receive_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !6, i64 608}
!14 = !{!"", !15, i64 0, !6, i64 176, !6, i64 184, !6, i64 192, !17, i64 200, !17, i64 392, !12, i64 584, !12, i64 588, !21, i64 592}
!15 = !{!"__SPI_HandleTypeDef", !6, i64 0, !16, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!17 = !{!"", !18, i64 0, !12, i64 184, !20, i64 188}
!18 = !{!"__DMA_HandleTypeDef", !6, i64 0, !19, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!19 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!20 = !{!"", !12, i64 0}
!21 = !{!"", !12, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !12, i64 32}
!22 = !{!14, !12, i64 584}
!23 = !{!14, !6, i64 600}
!24 = !{!14, !12, i64 624}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) local_unnamed_addr #0

declare i64 @xQueueGenericSend(ptr noundef, ptr noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @spi_receive(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #1 {
  %4 = icmp eq i16 %2, 0
  %5 = icmp eq ptr %1, null
  %or.cond = or i1 %5, %4
  br i1 %or.cond, label %30, label %6

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 608
  %8 = load ptr, ptr %7, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 584
  %10 = load i32, ptr %9, align 8, !tbaa !19
  %11 = mul i32 %10, 1000
  %12 = udiv i32 %11, 1000
  %13 = tail call i64 @xQueueSemaphoreTake(ptr noundef %8, i32 noundef %12) #2
  %.not = icmp eq i64 %13, 0
  br i1 %.not, label %30, label %14

14:                                               ; preds = %6
  %15 = getelementptr inbounds i8, ptr %0, i64 600
  %16 = load ptr, ptr %15, align 8, !tbaa !20
  %17 = tail call i64 @xQueueSemaphoreTake(ptr noundef %16, i32 noundef 0) #2
  %18 = getelementptr inbounds i8, ptr %0, i64 624
  store i32 2, ptr %18, align 8, !tbaa !21
  %19 = tail call i32 @HAL_SPI_Receive_DMA(ptr noundef nonnull %0, ptr noundef nonnull %1, i16 noundef zeroext %2) #2
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %27

21:                                               ; preds = %14
  %22 = load ptr, ptr %15, align 8, !tbaa !20
  %23 = load i32, ptr %9, align 8, !tbaa !19
  %24 = mul i32 %23, 1000
  %25 = udiv i32 %24, 1000
  %26 = tail call i64 @xQueueSemaphoreTake(ptr noundef %22, i32 noundef %25) #2
  %.not19 = icmp eq i64 %26, 0
  %spec.select = select i1 %.not19, i32 116, i32 0
  br label %27

27:                                               ; preds = %21, %14
  %.0 = phi i32 [ %19, %14 ], [ %spec.select, %21 ]
  store i32 0, ptr %18, align 8, !tbaa !21
  %28 = load ptr, ptr %7, align 8, !tbaa !5
  %29 = tail call i64 @xQueueGenericSend(ptr noundef %28, ptr noundef null, i32 noundef 0, i64 noundef 0) #2
  br label %30

30:                                               ; preds = %6, %3, %27
  %.016 = phi i32 [ %.0, %27 ], [ 22, %3 ], [ 116, %6 ]
  ret i32 %.016
}

declare i32 @HAL_SPI_Receive_DMA(ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 608}
!6 = !{!"", !7, i64 0, !8, i64 176, !8, i64 184, !8, i64 192, !14, i64 200, !14, i64 392, !12, i64 584, !12, i64 588, !18, i64 592}
!7 = !{!"__SPI_HandleTypeDef", !8, i64 0, !11, i64 8, !8, i64 96, !13, i64 104, !13, i64 106, !8, i64 112, !13, i64 120, !13, i64 122, !12, i64 124, !8, i64 128, !8, i64 136, !8, i64 144, !8, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!12 = !{!"int", !9, i64 0}
!13 = !{!"short", !9, i64 0}
!14 = !{!"", !15, i64 0, !12, i64 184, !17, i64 188}
!15 = !{!"__DMA_HandleTypeDef", !8, i64 0, !16, i64 8, !12, i64 56, !12, i64 60, !8, i64 64, !8, i64 72, !8, i64 80, !8, i64 88, !8, i64 96, !8, i64 104, !8, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !8, i64 136, !8, i64 144, !12, i64 152, !8, i64 160, !8, i64 168, !12, i64 176}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!17 = !{!"", !12, i64 0}
!18 = !{!"", !12, i64 0, !8, i64 8, !8, i64 16, !8, i64 24, !12, i64 32}
!19 = !{!6, !12, i64 584}
!20 = !{!6, !8, i64 600}
!21 = !{!6, !12, i64 624}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass