; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/periph/adc/stm32 (adc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.adc_t = type { %struct.ADC_HandleTypeDef, %struct.dma_t, [16 x %struct.adc_channel_t], i32, %struct.adc_private_t }
%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.dma_t = type { %struct.__DMA_HandleTypeDef, i32, %struct.dma_private_t }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.dma_private_t = type { i32 }
%struct.adc_channel_t = type { i32, %struct.ADC_ChannelConfTypeDef }
%struct.ADC_ChannelConfTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.adc_private_t = type { i32, [16 x i16], [16 x float], [16 x float], [16 x float], ptr, ptr }

; Function Attrs: nounwind uwtable
define dso_local i32 @adc_init(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store i32 22, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

11:                                               ; preds = %1
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = call i32 @adc_id_init(ptr noundef %12)
  store i32 %13, ptr %4, align 4, !tbaa !9
  %14 = icmp ne i32 %13, 0
  br i1 %14, label %15, label %17

15:                                               ; preds = %11
  %16 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %16, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

17:                                               ; preds = %11
  %18 = load ptr, ptr %3, align 8, !tbaa !5
  %19 = call i32 @adc_clock_init(ptr noundef %18)
  store i32 %19, ptr %4, align 4, !tbaa !9
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %21, label %23

21:                                               ; preds = %17
  %22 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %22, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

23:                                               ; preds = %17
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.adc_t, ptr %24, i32 0, i32 4
  %26 = getelementptr inbounds %struct.adc_private_t, ptr %25, i32 0, i32 0
  %27 = load i32, ptr %26, align 8, !tbaa !11
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.adc_t, ptr %28, i32 0, i32 3
  %30 = load i32, ptr %29, align 8, !tbaa !22
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = call i32 @irq_init(i32 noundef %27, i32 noundef %30, ptr noundef @adc_handler, ptr noundef %31)
  store i32 %32, ptr %4, align 4, !tbaa !9
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %36

34:                                               ; preds = %23
  %35 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %35, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

36:                                               ; preds = %23
  %37 = load ptr, ptr %3, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.adc_t, ptr %37, i32 0, i32 4
  %39 = getelementptr inbounds %struct.adc_private_t, ptr %38, i32 0, i32 0
  %40 = load i32, ptr %39, align 8, !tbaa !11
  %41 = call i32 @irq_enable(i32 noundef %40)
  store i32 %41, ptr %4, align 4, !tbaa !9
  %42 = icmp ne i32 %41, 0
  br i1 %42, label %43, label %45

43:                                               ; preds = %36
  %44 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %44, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

45:                                               ; preds = %36
  %46 = load ptr, ptr %3, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.adc_t, ptr %46, i32 0, i32 1
  %48 = load ptr, ptr %3, align 8, !tbaa !5
  %49 = call i32 @dma_init(ptr noundef %47, ptr noundef @adc_dma_handler, ptr noundef %48)
  store i32 %49, ptr %4, align 4, !tbaa !9
  %50 = icmp ne i32 %49, 0
  br i1 %50, label %51, label %53

51:                                               ; preds = %45
  %52 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %52, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

53:                                               ; preds = %45
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.adc_t, ptr %54, i32 0, i32 0
  %56 = call i32 @HAL_ADC_Init(ptr noundef %55)
  store i32 %56, ptr %4, align 4, !tbaa !9
  %57 = icmp ne i32 %56, 0
  br i1 %57, label %58, label %60

58:                                               ; preds = %53
  %59 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %59, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %154

60:                                               ; preds = %53
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.adc_t, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %3, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.adc_t, ptr %63, i32 0, i32 1
  %65 = getelementptr inbounds %struct.dma_t, ptr %64, i32 0, i32 0
  %66 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %65, i32 0, i32 4
  store ptr %62, ptr %66, align 8, !tbaa !23
  %67 = load ptr, ptr %3, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.adc_t, ptr %67, i32 0, i32 1
  %69 = getelementptr inbounds %struct.dma_t, ptr %68, i32 0, i32 0
  %70 = load ptr, ptr %3, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.adc_t, ptr %70, i32 0, i32 0
  %72 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %71, i32 0, i32 2
  store ptr %69, ptr %72, align 8, !tbaa !24
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %73

73:                                               ; preds = %104, %60
  %74 = load i32, ptr %7, align 4, !tbaa !9
  %75 = icmp slt i32 %74, 16
  br i1 %75, label %77, label %76

76:                                               ; preds = %73
  store i32 2, ptr %5, align 4
  br label %107

77:                                               ; preds = %73
  %78 = load ptr, ptr %3, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.adc_t, ptr %78, i32 0, i32 2
  %80 = load i32, ptr %7, align 4, !tbaa !9
  %81 = sext i32 %80 to i64
  %82 = getelementptr inbounds [16 x %struct.adc_channel_t], ptr %79, i64 0, i64 %81
  %83 = getelementptr inbounds %struct.adc_channel_t, ptr %82, i32 0, i32 0
  %84 = load i32, ptr %83, align 4, !tbaa !25
  %85 = icmp eq i32 %84, 1
  br i1 %85, label %86, label %103

86:                                               ; preds = %77
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.adc_t, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %3, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.adc_t, ptr %89, i32 0, i32 2
  %91 = load i32, ptr %7, align 4, !tbaa !9
  %92 = sext i32 %91 to i64
  %93 = getelementptr inbounds [16 x %struct.adc_channel_t], ptr %90, i64 0, i64 %92
  %94 = getelementptr inbounds %struct.adc_channel_t, ptr %93, i32 0, i32 1
  %95 = call i32 @HAL_ADC_ConfigChannel(ptr noundef %88, ptr noundef %94)
  store i32 %95, ptr %4, align 4, !tbaa !9
  %96 = load i32, ptr %6, align 4, !tbaa !9
  %97 = add i32 %96, 1
  store i32 %97, ptr %6, align 4, !tbaa !9
  %98 = load i32, ptr %4, align 4, !tbaa !9
  %99 = icmp ne i32 %98, 0
  br i1 %99, label %100, label %102

100:                                              ; preds = %86
  %101 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %101, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %107

102:                                              ; preds = %86
  br label %103

103:                                              ; preds = %102, %77
  br label %104

104:                                              ; preds = %103
  %105 = load i32, ptr %7, align 4, !tbaa !9
  %106 = add nsw i32 %105, 1
  store i32 %106, ptr %7, align 4, !tbaa !9
  br label %73, !llvm.loop !28

107:                                              ; preds = %100, %76
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  %108 = load i32, ptr %5, align 4
  switch i32 %108, label %153 [
    i32 2, label %109
  ]

109:                                              ; preds = %107
  %110 = call ptr @xQueueCreateMutex(i8 noundef zeroext 1)
  %111 = load ptr, ptr %3, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.adc_t, ptr %111, i32 0, i32 4
  %113 = getelementptr inbounds %struct.adc_private_t, ptr %112, i32 0, i32 6
  store ptr %110, ptr %113, align 8, !tbaa !30
  %114 = load ptr, ptr %3, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.adc_t, ptr %114, i32 0, i32 4
  %116 = getelementptr inbounds %struct.adc_private_t, ptr %115, i32 0, i32 6
  %117 = load ptr, ptr %116, align 8, !tbaa !30
  %118 = icmp eq ptr %117, null
  br i1 %118, label %119, label %120

119:                                              ; preds = %109
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %153

120:                                              ; preds = %109
  %121 = call ptr @xQueueGenericCreate(i64 noundef 1, i64 noundef 0, i8 noundef zeroext 3)
  %122 = load ptr, ptr %3, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.adc_t, ptr %122, i32 0, i32 4
  %124 = getelementptr inbounds %struct.adc_private_t, ptr %123, i32 0, i32 5
  store ptr %121, ptr %124, align 8, !tbaa !31
  %125 = load ptr, ptr %3, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.adc_t, ptr %125, i32 0, i32 4
  %127 = getelementptr inbounds %struct.adc_private_t, ptr %126, i32 0, i32 5
  %128 = load ptr, ptr %127, align 8, !tbaa !31
  %129 = icmp eq ptr %128, null
  br i1 %129, label %130, label %131

130:                                              ; preds = %120
  store i32 -1, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %153

131:                                              ; preds = %120
  %132 = load ptr, ptr %3, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.adc_t, ptr %132, i32 0, i32 4
  %134 = getelementptr inbounds %struct.adc_private_t, ptr %133, i32 0, i32 5
  %135 = load ptr, ptr %134, align 8, !tbaa !31
  %136 = call i64 @xQueueSemaphoreTake(ptr noundef %135, i32 noundef 0)
  %137 = load ptr, ptr %3, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.adc_t, ptr %137, i32 0, i32 0
  %139 = load ptr, ptr %3, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.adc_t, ptr %139, i32 0, i32 4
  %141 = getelementptr inbounds %struct.adc_private_t, ptr %140, i32 0, i32 1
  %142 = getelementptr inbounds [16 x i16], ptr %141, i64 0, i64 0
  %143 = load i32, ptr %6, align 4, !tbaa !9
  %144 = call i32 @HAL_ADC_Start_DMA(ptr noundef %138, ptr noundef %142, i32 noundef %143)
  store i32 %144, ptr %4, align 4, !tbaa !9
  %145 = load ptr, ptr %3, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.adc_t, ptr %145, i32 0, i32 4
  %147 = getelementptr inbounds %struct.adc_private_t, ptr %146, i32 0, i32 5
  %148 = load ptr, ptr %147, align 8, !tbaa !31
  %149 = call i64 @xQueueSemaphoreTake(ptr noundef %148, i32 noundef -1)
  %150 = load ptr, ptr %3, align 8, !tbaa !5
  %151 = call i32 @adc_reset_stat(ptr noundef %150)
  %152 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %152, ptr %2, align 4
  store i32 1, ptr %5, align 4
  br label %153

153:                                              ; preds = %131, %130, %119, %107
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %154

154:                                              ; preds = %153, %58, %51, %43, %34, %21, %15, %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %155 = load i32, ptr %2, align 4
  ret i32 %155
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @adc_id_init(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @adc_clock_init(ptr noundef) #0

declare i32 @irq_init(i32 noundef, i32 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @adc_handler(ptr noundef) #0

declare i32 @irq_enable(i32 noundef) #2

declare i32 @dma_init(ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @adc_dma_handler(ptr noundef) #0

declare i32 @HAL_ADC_Init(ptr noundef) #2

declare i32 @HAL_ADC_ConfigChannel(ptr noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare ptr @xQueueCreateMutex(i8 noundef zeroext) #2

declare ptr @xQueueGenericCreate(i64 noundef, i64 noundef, i8 noundef zeroext) #2

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) #2

declare i32 @HAL_ADC_Start_DMA(ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @adc_reset_stat(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 896}
!12 = !{!"", !13, i64 0, !17, i64 120, !7, i64 312, !10, i64 888, !21, i64 896}
!13 = !{!"", !6, i64 0, !14, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !16, i64 108}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !15, i64 60}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!16 = !{!"", !10, i64 0, !10, i64 4}
!17 = !{!"", !18, i64 0, !10, i64 184, !20, i64 188}
!18 = !{!"__DMA_HandleTypeDef", !6, i64 0, !19, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!19 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!20 = !{!"", !10, i64 0}
!21 = !{!"", !10, i64 0, !7, i64 4, !7, i64 36, !7, i64 100, !7, i64 164, !6, i64 232, !6, i64 240}
!22 = !{!12, !10, i64 888}
!23 = !{!12, !6, i64 184}
!24 = !{!12, !6, i64 88}
!25 = !{!26, !10, i64 0}
!26 = !{!"", !10, i64 0, !27, i64 4}
!27 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}
!28 = distinct !{!28, !29}
!29 = !{!"llvm.loop.mustprogress"}
!30 = !{!12, !6, i64 1136}
!31 = !{!12, !6, i64 1128}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @adc_init(ptr noundef %0) local_unnamed_addr #0 {
  %2 = icmp eq ptr %0, null
  br i1 %2, label %.loopexit, label %3

3:                                                ; preds = %1
  %4 = tail call i32 @adc_id_init(ptr noundef nonnull %0)
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %5, label %.loopexit

5:                                                ; preds = %3
  %6 = tail call i32 @adc_clock_init(ptr noundef nonnull %0)
  %.not56 = icmp eq i32 %6, 0
  br i1 %.not56, label %7, label %.loopexit

7:                                                ; preds = %5
  %8 = getelementptr inbounds i8, ptr %0, i64 896
  %9 = load i32, ptr %8, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %0, i64 888
  %11 = load i32, ptr %10, align 8, !tbaa !20
  %12 = tail call i32 @irq_init(i32 noundef %9, i32 noundef %11, ptr noundef nonnull @adc_handler, ptr noundef nonnull %0) #2
  %.not57 = icmp eq i32 %12, 0
  br i1 %.not57, label %13, label %.loopexit

13:                                               ; preds = %7
  %14 = load i32, ptr %8, align 8, !tbaa !5
  %15 = tail call i32 @irq_enable(i32 noundef %14) #2
  %.not58 = icmp eq i32 %15, 0
  br i1 %.not58, label %16, label %.loopexit

16:                                               ; preds = %13
  %17 = getelementptr inbounds i8, ptr %0, i64 120
  %18 = tail call i32 @dma_init(ptr noundef nonnull %17, ptr noundef nonnull @adc_dma_handler, ptr noundef nonnull %0) #2
  %.not59 = icmp eq i32 %18, 0
  br i1 %.not59, label %19, label %.loopexit

19:                                               ; preds = %16
  %20 = tail call i32 @HAL_ADC_Init(ptr noundef nonnull %0) #2
  %.not60 = icmp eq i32 %20, 0
  br i1 %.not60, label %21, label %.loopexit

21:                                               ; preds = %19
  %22 = getelementptr inbounds i8, ptr %0, i64 184
  store ptr %0, ptr %22, align 8, !tbaa !21
  %23 = getelementptr inbounds i8, ptr %0, i64 88
  store ptr %17, ptr %23, align 8, !tbaa !22
  %24 = getelementptr inbounds i8, ptr %0, i64 312
  %25 = load i32, ptr %24, align 4, !tbaa !23
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %30

27:                                               ; preds = %21
  %28 = getelementptr inbounds i8, ptr %0, i64 316
  %29 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %28) #2
  %.not61 = icmp eq i32 %29, 0
  br i1 %.not61, label %30, label %.loopexit

30:                                               ; preds = %21, %27
  %.1 = phi i32 [ 1, %27 ], [ 0, %21 ]
  %31 = getelementptr inbounds i8, ptr %0, i64 348
  %32 = load i32, ptr %31, align 4, !tbaa !23
  %33 = icmp eq i32 %32, 1
  br i1 %33, label %34, label %38

34:                                               ; preds = %30
  %35 = getelementptr inbounds i8, ptr %0, i64 352
  %36 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %35) #2
  %37 = add nuw nsw i32 %.1, 1
  %.not61.1 = icmp eq i32 %36, 0
  br i1 %.not61.1, label %38, label %.loopexit

38:                                               ; preds = %34, %30
  %.1.1 = phi i32 [ %37, %34 ], [ %.1, %30 ]
  %39 = getelementptr inbounds i8, ptr %0, i64 384
  %40 = load i32, ptr %39, align 4, !tbaa !23
  %41 = icmp eq i32 %40, 1
  br i1 %41, label %42, label %46

42:                                               ; preds = %38
  %43 = getelementptr inbounds i8, ptr %0, i64 388
  %44 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %43) #2
  %45 = add nuw nsw i32 %.1.1, 1
  %.not61.2 = icmp eq i32 %44, 0
  br i1 %.not61.2, label %46, label %.loopexit

46:                                               ; preds = %42, %38
  %.1.2 = phi i32 [ %45, %42 ], [ %.1.1, %38 ]
  %47 = getelementptr inbounds i8, ptr %0, i64 420
  %48 = load i32, ptr %47, align 4, !tbaa !23
  %49 = icmp eq i32 %48, 1
  br i1 %49, label %50, label %54

50:                                               ; preds = %46
  %51 = getelementptr inbounds i8, ptr %0, i64 424
  %52 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %51) #2
  %53 = add nuw nsw i32 %.1.2, 1
  %.not61.3 = icmp eq i32 %52, 0
  br i1 %.not61.3, label %54, label %.loopexit

54:                                               ; preds = %50, %46
  %.1.3 = phi i32 [ %53, %50 ], [ %.1.2, %46 ]
  %55 = getelementptr inbounds i8, ptr %0, i64 456
  %56 = load i32, ptr %55, align 4, !tbaa !23
  %57 = icmp eq i32 %56, 1
  br i1 %57, label %58, label %62

58:                                               ; preds = %54
  %59 = getelementptr inbounds i8, ptr %0, i64 460
  %60 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %59) #2
  %61 = add nuw nsw i32 %.1.3, 1
  %.not61.4 = icmp eq i32 %60, 0
  br i1 %.not61.4, label %62, label %.loopexit

62:                                               ; preds = %58, %54
  %.1.4 = phi i32 [ %61, %58 ], [ %.1.3, %54 ]
  %63 = getelementptr inbounds i8, ptr %0, i64 492
  %64 = load i32, ptr %63, align 4, !tbaa !23
  %65 = icmp eq i32 %64, 1
  br i1 %65, label %66, label %70

66:                                               ; preds = %62
  %67 = getelementptr inbounds i8, ptr %0, i64 496
  %68 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %67) #2
  %69 = add nuw nsw i32 %.1.4, 1
  %.not61.5 = icmp eq i32 %68, 0
  br i1 %.not61.5, label %70, label %.loopexit

70:                                               ; preds = %66, %62
  %.1.5 = phi i32 [ %69, %66 ], [ %.1.4, %62 ]
  %71 = getelementptr inbounds i8, ptr %0, i64 528
  %72 = load i32, ptr %71, align 4, !tbaa !23
  %73 = icmp eq i32 %72, 1
  br i1 %73, label %74, label %78

74:                                               ; preds = %70
  %75 = getelementptr inbounds i8, ptr %0, i64 532
  %76 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %75) #2
  %77 = add nuw nsw i32 %.1.5, 1
  %.not61.6 = icmp eq i32 %76, 0
  br i1 %.not61.6, label %78, label %.loopexit

78:                                               ; preds = %74, %70
  %.1.6 = phi i32 [ %77, %74 ], [ %.1.5, %70 ]
  %79 = getelementptr inbounds i8, ptr %0, i64 564
  %80 = load i32, ptr %79, align 4, !tbaa !23
  %81 = icmp eq i32 %80, 1
  br i1 %81, label %82, label %86

82:                                               ; preds = %78
  %83 = getelementptr inbounds i8, ptr %0, i64 568
  %84 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %83) #2
  %85 = add nuw nsw i32 %.1.6, 1
  %.not61.7 = icmp eq i32 %84, 0
  br i1 %.not61.7, label %86, label %.loopexit

86:                                               ; preds = %82, %78
  %.1.7 = phi i32 [ %85, %82 ], [ %.1.6, %78 ]
  %87 = getelementptr inbounds i8, ptr %0, i64 600
  %88 = load i32, ptr %87, align 4, !tbaa !23
  %89 = icmp eq i32 %88, 1
  br i1 %89, label %90, label %94

90:                                               ; preds = %86
  %91 = getelementptr inbounds i8, ptr %0, i64 604
  %92 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %91) #2
  %93 = add nuw nsw i32 %.1.7, 1
  %.not61.8 = icmp eq i32 %92, 0
  br i1 %.not61.8, label %94, label %.loopexit

94:                                               ; preds = %90, %86
  %.1.8 = phi i32 [ %93, %90 ], [ %.1.7, %86 ]
  %95 = getelementptr inbounds i8, ptr %0, i64 636
  %96 = load i32, ptr %95, align 4, !tbaa !23
  %97 = icmp eq i32 %96, 1
  br i1 %97, label %98, label %102

98:                                               ; preds = %94
  %99 = getelementptr inbounds i8, ptr %0, i64 640
  %100 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %99) #2
  %101 = add nuw nsw i32 %.1.8, 1
  %.not61.9 = icmp eq i32 %100, 0
  br i1 %.not61.9, label %102, label %.loopexit

102:                                              ; preds = %98, %94
  %.1.9 = phi i32 [ %101, %98 ], [ %.1.8, %94 ]
  %103 = getelementptr inbounds i8, ptr %0, i64 672
  %104 = load i32, ptr %103, align 4, !tbaa !23
  %105 = icmp eq i32 %104, 1
  br i1 %105, label %106, label %110

106:                                              ; preds = %102
  %107 = getelementptr inbounds i8, ptr %0, i64 676
  %108 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %107) #2
  %109 = add nuw nsw i32 %.1.9, 1
  %.not61.10 = icmp eq i32 %108, 0
  br i1 %.not61.10, label %110, label %.loopexit

110:                                              ; preds = %106, %102
  %.1.10 = phi i32 [ %109, %106 ], [ %.1.9, %102 ]
  %111 = getelementptr inbounds i8, ptr %0, i64 708
  %112 = load i32, ptr %111, align 4, !tbaa !23
  %113 = icmp eq i32 %112, 1
  br i1 %113, label %114, label %118

114:                                              ; preds = %110
  %115 = getelementptr inbounds i8, ptr %0, i64 712
  %116 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %115) #2
  %117 = add nuw nsw i32 %.1.10, 1
  %.not61.11 = icmp eq i32 %116, 0
  br i1 %.not61.11, label %118, label %.loopexit

118:                                              ; preds = %114, %110
  %.1.11 = phi i32 [ %117, %114 ], [ %.1.10, %110 ]
  %119 = getelementptr inbounds i8, ptr %0, i64 744
  %120 = load i32, ptr %119, align 4, !tbaa !23
  %121 = icmp eq i32 %120, 1
  br i1 %121, label %122, label %126

122:                                              ; preds = %118
  %123 = getelementptr inbounds i8, ptr %0, i64 748
  %124 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %123) #2
  %125 = add nuw nsw i32 %.1.11, 1
  %.not61.12 = icmp eq i32 %124, 0
  br i1 %.not61.12, label %126, label %.loopexit

126:                                              ; preds = %122, %118
  %.1.12 = phi i32 [ %125, %122 ], [ %.1.11, %118 ]
  %127 = getelementptr inbounds i8, ptr %0, i64 780
  %128 = load i32, ptr %127, align 4, !tbaa !23
  %129 = icmp eq i32 %128, 1
  br i1 %129, label %130, label %134

130:                                              ; preds = %126
  %131 = getelementptr inbounds i8, ptr %0, i64 784
  %132 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %131) #2
  %133 = add nuw nsw i32 %.1.12, 1
  %.not61.13 = icmp eq i32 %132, 0
  br i1 %.not61.13, label %134, label %.loopexit

134:                                              ; preds = %130, %126
  %.1.13 = phi i32 [ %133, %130 ], [ %.1.12, %126 ]
  %135 = getelementptr inbounds i8, ptr %0, i64 816
  %136 = load i32, ptr %135, align 4, !tbaa !23
  %137 = icmp eq i32 %136, 1
  br i1 %137, label %138, label %142

138:                                              ; preds = %134
  %139 = getelementptr inbounds i8, ptr %0, i64 820
  %140 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %139) #2
  %141 = add nuw nsw i32 %.1.13, 1
  %.not61.14 = icmp eq i32 %140, 0
  br i1 %.not61.14, label %142, label %.loopexit

142:                                              ; preds = %138, %134
  %.1.14 = phi i32 [ %141, %138 ], [ %.1.13, %134 ]
  %143 = getelementptr inbounds i8, ptr %0, i64 852
  %144 = load i32, ptr %143, align 4, !tbaa !23
  %145 = icmp eq i32 %144, 1
  br i1 %145, label %146, label %150

146:                                              ; preds = %142
  %147 = getelementptr inbounds i8, ptr %0, i64 856
  %148 = tail call i32 @HAL_ADC_ConfigChannel(ptr noundef nonnull %0, ptr noundef nonnull %147) #2
  %149 = add nuw nsw i32 %.1.14, 1
  %.not61.15 = icmp eq i32 %148, 0
  br i1 %.not61.15, label %150, label %.loopexit

150:                                              ; preds = %146, %142
  %.1.15 = phi i32 [ %149, %146 ], [ %.1.14, %142 ]
  %151 = tail call ptr @xQueueCreateMutex(i8 noundef zeroext 1) #2
  %152 = getelementptr inbounds i8, ptr %0, i64 1136
  store ptr %151, ptr %152, align 8, !tbaa !26
  %153 = icmp eq ptr %151, null
  br i1 %153, label %.loopexit, label %154

154:                                              ; preds = %150
  %155 = tail call ptr @xQueueGenericCreate(i64 noundef 1, i64 noundef 0, i8 noundef zeroext 3) #2
  %156 = getelementptr inbounds i8, ptr %0, i64 1128
  store ptr %155, ptr %156, align 8, !tbaa !27
  %157 = icmp eq ptr %155, null
  br i1 %157, label %.loopexit, label %158

158:                                              ; preds = %154
  %159 = tail call i64 @xQueueSemaphoreTake(ptr noundef nonnull %155, i32 noundef 0) #2
  %160 = getelementptr inbounds i8, ptr %0, i64 900
  %161 = tail call i32 @HAL_ADC_Start_DMA(ptr noundef nonnull %0, ptr noundef nonnull %160, i32 noundef %.1.15) #2
  %162 = load ptr, ptr %156, align 8, !tbaa !27
  %163 = tail call i64 @xQueueSemaphoreTake(ptr noundef %162, i32 noundef -1) #2
  %164 = tail call i32 @adc_reset_stat(ptr noundef nonnull %0)
  br label %.loopexit

.loopexit:                                        ; preds = %27, %34, %42, %50, %58, %66, %74, %82, %90, %98, %106, %114, %122, %130, %138, %146, %158, %150, %154, %19, %16, %13, %7, %5, %3, %1
  %.246 = phi i32 [ 22, %1 ], [ %4, %3 ], [ %6, %5 ], [ %12, %7 ], [ %15, %13 ], [ %18, %16 ], [ %20, %19 ], [ %161, %158 ], [ -1, %150 ], [ -1, %154 ], [ %29, %27 ], [ %36, %34 ], [ %44, %42 ], [ %52, %50 ], [ %60, %58 ], [ %68, %66 ], [ %76, %74 ], [ %84, %82 ], [ %92, %90 ], [ %100, %98 ], [ %108, %106 ], [ %116, %114 ], [ %124, %122 ], [ %132, %130 ], [ %140, %138 ], [ %148, %146 ]
  ret i32 %.246
}

; Function Attrs: nounwind uwtable
declare hidden i32 @adc_id_init(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @adc_clock_init(ptr noundef) local_unnamed_addr #0

declare i32 @irq_init(i32 noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @adc_handler(ptr noundef) #0

declare i32 @irq_enable(i32 noundef) local_unnamed_addr #1

declare i32 @dma_init(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @adc_dma_handler(ptr noundef) #0

declare i32 @HAL_ADC_Init(ptr noundef) local_unnamed_addr #1

declare i32 @HAL_ADC_ConfigChannel(ptr noundef, ptr noundef) local_unnamed_addr #1

declare ptr @xQueueCreateMutex(i8 noundef zeroext) local_unnamed_addr #1

declare ptr @xQueueGenericCreate(i64 noundef, i64 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare i64 @xQueueSemaphoreTake(ptr noundef, i32 noundef) local_unnamed_addr #1

declare i32 @HAL_ADC_Start_DMA(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @adc_reset_stat(ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 896}
!6 = !{!"", !7, i64 0, !15, i64 120, !9, i64 312, !12, i64 888, !19, i64 896}
!7 = !{!"", !8, i64 0, !11, i64 8, !8, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !14, i64 108}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !13, i64 60}
!12 = !{!"int", !9, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!14 = !{!"", !12, i64 0, !12, i64 4}
!15 = !{!"", !16, i64 0, !12, i64 184, !18, i64 188}
!16 = !{!"__DMA_HandleTypeDef", !8, i64 0, !17, i64 8, !12, i64 56, !12, i64 60, !8, i64 64, !8, i64 72, !8, i64 80, !8, i64 88, !8, i64 96, !8, i64 104, !8, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !8, i64 136, !8, i64 144, !12, i64 152, !8, i64 160, !8, i64 168, !12, i64 176}
!17 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!18 = !{!"", !12, i64 0}
!19 = !{!"", !12, i64 0, !9, i64 4, !9, i64 36, !9, i64 100, !9, i64 164, !8, i64 232, !8, i64 240}
!20 = !{!6, !12, i64 888}
!21 = !{!6, !8, i64 184}
!22 = !{!6, !8, i64 88}
!23 = !{!24, !12, i64 0}
!24 = !{!"", !12, i64 0, !25, i64 4}
!25 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28}
!26 = !{!6, !8, i64 1136}
!27 = !{!6, !8, i64 1128}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass