; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC3_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC4_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC5_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC6_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_PWM_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %11, i32 0, i32 4
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %214

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 4
  store i32 1, ptr %18, align 8, !tbaa !11
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load i32, ptr %7, align 4, !tbaa !9
  switch i32 %22, label %206 [
    i32 0, label %23
    i32 4, label %53
    i32 8, label %84
    i32 12, label %114
    i32 16, label %145
    i32 20, label %175
  ]

23:                                               ; preds = %21
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %25, align 8, !tbaa !14
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC1_SetConfig(ptr noundef %26, ptr noundef %27)
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 0
  %30 = load ptr, ptr %29, align 8, !tbaa !14
  %31 = getelementptr inbounds %struct.TIM_TypeDef, ptr %30, i32 0, i32 6
  %32 = load volatile i32, ptr %31, align 4, !tbaa !15
  %33 = zext i32 %32 to i64
  %34 = or i64 %33, 8
  %35 = trunc i64 %34 to i32
  store volatile i32 %35, ptr %31, align 4, !tbaa !15
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !14
  %39 = getelementptr inbounds %struct.TIM_TypeDef, ptr %38, i32 0, i32 6
  %40 = load volatile i32, ptr %39, align 4, !tbaa !15
  %41 = zext i32 %40 to i64
  %42 = and i64 %41, -5
  %43 = trunc i64 %42 to i32
  store volatile i32 %43, ptr %39, align 4, !tbaa !15
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %44, i32 0, i32 4
  %46 = load i32, ptr %45, align 4, !tbaa !17
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %47, i32 0, i32 0
  %49 = load ptr, ptr %48, align 8, !tbaa !14
  %50 = getelementptr inbounds %struct.TIM_TypeDef, ptr %49, i32 0, i32 6
  %51 = load volatile i32, ptr %50, align 4, !tbaa !15
  %52 = or i32 %51, %46
  store volatile i32 %52, ptr %50, align 4, !tbaa !15
  br label %207

53:                                               ; preds = %21
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !14
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC2_SetConfig(ptr noundef %56, ptr noundef %57)
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !14
  %61 = getelementptr inbounds %struct.TIM_TypeDef, ptr %60, i32 0, i32 6
  %62 = load volatile i32, ptr %61, align 4, !tbaa !15
  %63 = zext i32 %62 to i64
  %64 = or i64 %63, 2048
  %65 = trunc i64 %64 to i32
  store volatile i32 %65, ptr %61, align 4, !tbaa !15
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %66, i32 0, i32 0
  %68 = load ptr, ptr %67, align 8, !tbaa !14
  %69 = getelementptr inbounds %struct.TIM_TypeDef, ptr %68, i32 0, i32 6
  %70 = load volatile i32, ptr %69, align 4, !tbaa !15
  %71 = zext i32 %70 to i64
  %72 = and i64 %71, -1025
  %73 = trunc i64 %72 to i32
  store volatile i32 %73, ptr %69, align 4, !tbaa !15
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %74, i32 0, i32 4
  %76 = load i32, ptr %75, align 4, !tbaa !17
  %77 = shl i32 %76, 8
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !14
  %81 = getelementptr inbounds %struct.TIM_TypeDef, ptr %80, i32 0, i32 6
  %82 = load volatile i32, ptr %81, align 4, !tbaa !15
  %83 = or i32 %82, %77
  store volatile i32 %83, ptr %81, align 4, !tbaa !15
  br label %207

84:                                               ; preds = %21
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %85, i32 0, i32 0
  %87 = load ptr, ptr %86, align 8, !tbaa !14
  %88 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC3_SetConfig(ptr noundef %87, ptr noundef %88)
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %89, i32 0, i32 0
  %91 = load ptr, ptr %90, align 8, !tbaa !14
  %92 = getelementptr inbounds %struct.TIM_TypeDef, ptr %91, i32 0, i32 7
  %93 = load volatile i32, ptr %92, align 4, !tbaa !19
  %94 = zext i32 %93 to i64
  %95 = or i64 %94, 8
  %96 = trunc i64 %95 to i32
  store volatile i32 %96, ptr %92, align 4, !tbaa !19
  %97 = load ptr, ptr %5, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %97, i32 0, i32 0
  %99 = load ptr, ptr %98, align 8, !tbaa !14
  %100 = getelementptr inbounds %struct.TIM_TypeDef, ptr %99, i32 0, i32 7
  %101 = load volatile i32, ptr %100, align 4, !tbaa !19
  %102 = zext i32 %101 to i64
  %103 = and i64 %102, -5
  %104 = trunc i64 %103 to i32
  store volatile i32 %104, ptr %100, align 4, !tbaa !19
  %105 = load ptr, ptr %6, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %105, i32 0, i32 4
  %107 = load i32, ptr %106, align 4, !tbaa !17
  %108 = load ptr, ptr %5, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %108, i32 0, i32 0
  %110 = load ptr, ptr %109, align 8, !tbaa !14
  %111 = getelementptr inbounds %struct.TIM_TypeDef, ptr %110, i32 0, i32 7
  %112 = load volatile i32, ptr %111, align 4, !tbaa !19
  %113 = or i32 %112, %107
  store volatile i32 %113, ptr %111, align 4, !tbaa !19
  br label %207

114:                                              ; preds = %21
  %115 = load ptr, ptr %5, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !14
  %118 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC4_SetConfig(ptr noundef %117, ptr noundef %118)
  %119 = load ptr, ptr %5, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !14
  %122 = getelementptr inbounds %struct.TIM_TypeDef, ptr %121, i32 0, i32 7
  %123 = load volatile i32, ptr %122, align 4, !tbaa !19
  %124 = zext i32 %123 to i64
  %125 = or i64 %124, 2048
  %126 = trunc i64 %125 to i32
  store volatile i32 %126, ptr %122, align 4, !tbaa !19
  %127 = load ptr, ptr %5, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %127, i32 0, i32 0
  %129 = load ptr, ptr %128, align 8, !tbaa !14
  %130 = getelementptr inbounds %struct.TIM_TypeDef, ptr %129, i32 0, i32 7
  %131 = load volatile i32, ptr %130, align 4, !tbaa !19
  %132 = zext i32 %131 to i64
  %133 = and i64 %132, -1025
  %134 = trunc i64 %133 to i32
  store volatile i32 %134, ptr %130, align 4, !tbaa !19
  %135 = load ptr, ptr %6, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %135, i32 0, i32 4
  %137 = load i32, ptr %136, align 4, !tbaa !17
  %138 = shl i32 %137, 8
  %139 = load ptr, ptr %5, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %139, i32 0, i32 0
  %141 = load ptr, ptr %140, align 8, !tbaa !14
  %142 = getelementptr inbounds %struct.TIM_TypeDef, ptr %141, i32 0, i32 7
  %143 = load volatile i32, ptr %142, align 4, !tbaa !19
  %144 = or i32 %143, %138
  store volatile i32 %144, ptr %142, align 4, !tbaa !19
  br label %207

145:                                              ; preds = %21
  %146 = load ptr, ptr %5, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %146, i32 0, i32 0
  %148 = load ptr, ptr %147, align 8, !tbaa !14
  %149 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC5_SetConfig(ptr noundef %148, ptr noundef %149)
  %150 = load ptr, ptr %5, align 8, !tbaa !5
  %151 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %150, i32 0, i32 0
  %152 = load ptr, ptr %151, align 8, !tbaa !14
  %153 = getelementptr inbounds %struct.TIM_TypeDef, ptr %152, i32 0, i32 21
  %154 = load volatile i32, ptr %153, align 4, !tbaa !20
  %155 = zext i32 %154 to i64
  %156 = or i64 %155, 8
  %157 = trunc i64 %156 to i32
  store volatile i32 %157, ptr %153, align 4, !tbaa !20
  %158 = load ptr, ptr %5, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %158, i32 0, i32 0
  %160 = load ptr, ptr %159, align 8, !tbaa !14
  %161 = getelementptr inbounds %struct.TIM_TypeDef, ptr %160, i32 0, i32 21
  %162 = load volatile i32, ptr %161, align 4, !tbaa !20
  %163 = zext i32 %162 to i64
  %164 = and i64 %163, -5
  %165 = trunc i64 %164 to i32
  store volatile i32 %165, ptr %161, align 4, !tbaa !20
  %166 = load ptr, ptr %6, align 8, !tbaa !5
  %167 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %166, i32 0, i32 4
  %168 = load i32, ptr %167, align 4, !tbaa !17
  %169 = load ptr, ptr %5, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %169, i32 0, i32 0
  %171 = load ptr, ptr %170, align 8, !tbaa !14
  %172 = getelementptr inbounds %struct.TIM_TypeDef, ptr %171, i32 0, i32 21
  %173 = load volatile i32, ptr %172, align 4, !tbaa !20
  %174 = or i32 %173, %168
  store volatile i32 %174, ptr %172, align 4, !tbaa !20
  br label %207

175:                                              ; preds = %21
  %176 = load ptr, ptr %5, align 8, !tbaa !5
  %177 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %176, i32 0, i32 0
  %178 = load ptr, ptr %177, align 8, !tbaa !14
  %179 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC6_SetConfig(ptr noundef %178, ptr noundef %179)
  %180 = load ptr, ptr %5, align 8, !tbaa !5
  %181 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %180, i32 0, i32 0
  %182 = load ptr, ptr %181, align 8, !tbaa !14
  %183 = getelementptr inbounds %struct.TIM_TypeDef, ptr %182, i32 0, i32 21
  %184 = load volatile i32, ptr %183, align 4, !tbaa !20
  %185 = zext i32 %184 to i64
  %186 = or i64 %185, 2048
  %187 = trunc i64 %186 to i32
  store volatile i32 %187, ptr %183, align 4, !tbaa !20
  %188 = load ptr, ptr %5, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %188, i32 0, i32 0
  %190 = load ptr, ptr %189, align 8, !tbaa !14
  %191 = getelementptr inbounds %struct.TIM_TypeDef, ptr %190, i32 0, i32 21
  %192 = load volatile i32, ptr %191, align 4, !tbaa !20
  %193 = zext i32 %192 to i64
  %194 = and i64 %193, -1025
  %195 = trunc i64 %194 to i32
  store volatile i32 %195, ptr %191, align 4, !tbaa !20
  %196 = load ptr, ptr %6, align 8, !tbaa !5
  %197 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %196, i32 0, i32 4
  %198 = load i32, ptr %197, align 4, !tbaa !17
  %199 = shl i32 %198, 8
  %200 = load ptr, ptr %5, align 8, !tbaa !5
  %201 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %200, i32 0, i32 0
  %202 = load ptr, ptr %201, align 8, !tbaa !14
  %203 = getelementptr inbounds %struct.TIM_TypeDef, ptr %202, i32 0, i32 21
  %204 = load volatile i32, ptr %203, align 4, !tbaa !20
  %205 = or i32 %204, %199
  store volatile i32 %205, ptr %203, align 4, !tbaa !20
  br label %207

206:                                              ; preds = %21
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %207

207:                                              ; preds = %206, %175, %145, %114, %84, %53, %23
  br label %208

208:                                              ; preds = %207
  %209 = load ptr, ptr %5, align 8, !tbaa !5
  %210 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %209, i32 0, i32 4
  store i32 0, ptr %210, align 8, !tbaa !11
  br label %211

211:                                              ; preds = %208
  br label %212

212:                                              ; preds = %211
  %213 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %213, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %214

214:                                              ; preds = %212, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %215 = load i32, ptr %4, align 4
  ret i32 %215
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !6, i64 0}
!15 = !{!16, !10, i64 24}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!17 = !{!18, !10, i64 16}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!19 = !{!16, !10, i64 28}
!20 = !{!16, !10, i64 84}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC3_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC4_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC5_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC6_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_PWM_ConfigChannel(ptr nocapture noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %75, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = tail call i32 @llvm.fshl.i32(i32 %2, i32 %2, i32 30)
  switch i32 %8, label %74 [
    i32 0, label %9
    i32 1, label %19
    i32 2, label %30
    i32 3, label %40
    i32 4, label %51
    i32 5, label %61
  ]

9:                                                ; preds = %7
  %10 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC1_SetConfig(ptr noundef %10, ptr noundef %1)
  %11 = load ptr, ptr %0, align 8, !tbaa !12
  %12 = getelementptr inbounds i8, ptr %11, i64 24
  %13 = load volatile i32, ptr %12, align 4, !tbaa !13
  %14 = or i32 %13, 8
  store volatile i32 %14, ptr %12, align 4, !tbaa !13
  %15 = load volatile i32, ptr %12, align 4, !tbaa !13
  %16 = and i32 %15, -5
  store volatile i32 %16, ptr %12, align 4, !tbaa !13
  %17 = getelementptr inbounds i8, ptr %1, i64 16
  %18 = load i32, ptr %17, align 4, !tbaa !15
  br label %.sink.split

19:                                               ; preds = %7
  %20 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC2_SetConfig(ptr noundef %20, ptr noundef %1)
  %21 = load ptr, ptr %0, align 8, !tbaa !12
  %22 = getelementptr inbounds i8, ptr %21, i64 24
  %23 = load volatile i32, ptr %22, align 4, !tbaa !13
  %24 = or i32 %23, 2048
  store volatile i32 %24, ptr %22, align 4, !tbaa !13
  %25 = load volatile i32, ptr %22, align 4, !tbaa !13
  %26 = and i32 %25, -1025
  store volatile i32 %26, ptr %22, align 4, !tbaa !13
  %27 = getelementptr inbounds i8, ptr %1, i64 16
  %28 = load i32, ptr %27, align 4, !tbaa !15
  %29 = shl i32 %28, 8
  br label %.sink.split

30:                                               ; preds = %7
  %31 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC3_SetConfig(ptr noundef %31, ptr noundef %1)
  %32 = load ptr, ptr %0, align 8, !tbaa !12
  %33 = getelementptr inbounds i8, ptr %32, i64 28
  %34 = load volatile i32, ptr %33, align 4, !tbaa !17
  %35 = or i32 %34, 8
  store volatile i32 %35, ptr %33, align 4, !tbaa !17
  %36 = load volatile i32, ptr %33, align 4, !tbaa !17
  %37 = and i32 %36, -5
  store volatile i32 %37, ptr %33, align 4, !tbaa !17
  %38 = getelementptr inbounds i8, ptr %1, i64 16
  %39 = load i32, ptr %38, align 4, !tbaa !15
  br label %.sink.split

40:                                               ; preds = %7
  %41 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC4_SetConfig(ptr noundef %41, ptr noundef %1)
  %42 = load ptr, ptr %0, align 8, !tbaa !12
  %43 = getelementptr inbounds i8, ptr %42, i64 28
  %44 = load volatile i32, ptr %43, align 4, !tbaa !17
  %45 = or i32 %44, 2048
  store volatile i32 %45, ptr %43, align 4, !tbaa !17
  %46 = load volatile i32, ptr %43, align 4, !tbaa !17
  %47 = and i32 %46, -1025
  store volatile i32 %47, ptr %43, align 4, !tbaa !17
  %48 = getelementptr inbounds i8, ptr %1, i64 16
  %49 = load i32, ptr %48, align 4, !tbaa !15
  %50 = shl i32 %49, 8
  br label %.sink.split

51:                                               ; preds = %7
  %52 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC5_SetConfig(ptr noundef %52, ptr noundef %1)
  %53 = load ptr, ptr %0, align 8, !tbaa !12
  %54 = getelementptr inbounds i8, ptr %53, i64 84
  %55 = load volatile i32, ptr %54, align 4, !tbaa !18
  %56 = or i32 %55, 8
  store volatile i32 %56, ptr %54, align 4, !tbaa !18
  %57 = load volatile i32, ptr %54, align 4, !tbaa !18
  %58 = and i32 %57, -5
  store volatile i32 %58, ptr %54, align 4, !tbaa !18
  %59 = getelementptr inbounds i8, ptr %1, i64 16
  %60 = load i32, ptr %59, align 4, !tbaa !15
  br label %.sink.split

61:                                               ; preds = %7
  %62 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC6_SetConfig(ptr noundef %62, ptr noundef %1)
  %63 = load ptr, ptr %0, align 8, !tbaa !12
  %64 = getelementptr inbounds i8, ptr %63, i64 84
  %65 = load volatile i32, ptr %64, align 4, !tbaa !18
  %66 = or i32 %65, 2048
  store volatile i32 %66, ptr %64, align 4, !tbaa !18
  %67 = load volatile i32, ptr %64, align 4, !tbaa !18
  %68 = and i32 %67, -1025
  store volatile i32 %68, ptr %64, align 4, !tbaa !18
  %69 = getelementptr inbounds i8, ptr %1, i64 16
  %70 = load i32, ptr %69, align 4, !tbaa !15
  %71 = shl i32 %70, 8
  br label %.sink.split

.sink.split:                                      ; preds = %61, %51, %40, %30, %19, %9
  %.sink = phi ptr [ %12, %9 ], [ %22, %19 ], [ %33, %30 ], [ %43, %40 ], [ %54, %51 ], [ %64, %61 ]
  %.sink44 = phi i32 [ %18, %9 ], [ %29, %19 ], [ %39, %30 ], [ %50, %40 ], [ %60, %51 ], [ %71, %61 ]
  %72 = load volatile i32, ptr %.sink, align 4, !tbaa !19
  %73 = or i32 %72, %.sink44
  store volatile i32 %73, ptr %.sink, align 4, !tbaa !19
  br label %74

74:                                               ; preds = %.sink.split, %7
  %.0 = phi i32 [ 1, %7 ], [ 0, %.sink.split ]
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %75

75:                                               ; preds = %3, %74
  %.041 = phi i32 [ %.0, %74 ], [ 2, %3 ]
  ret i32 %.041
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!14, !11, i64 24}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!15 = !{!16, !11, i64 16}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!17 = !{!14, !11, i64 28}
!18 = !{!14, !11, i64 84}
!19 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass