; LLVM IR from ritikbanger/Hacktoberfest2022-DSA :: 22. Segment Tree/max_segtree_lazy.ll (Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %7) #3 {
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i64, align 8
  store ptr %0, ptr %9, align 8, !tbaa !5
  store ptr %1, ptr %10, align 8, !tbaa !5
  store i64 %2, ptr %11, align 8, !tbaa !9
  store i64 %3, ptr %12, align 8, !tbaa !9
  store i64 %4, ptr %13, align 8, !tbaa !9
  store i64 %5, ptr %14, align 8, !tbaa !9
  store i64 %6, ptr %15, align 8, !tbaa !9
  store i64 %7, ptr %16, align 8, !tbaa !9
  %18 = load ptr, ptr %10, align 8, !tbaa !5
  %19 = load i64, ptr %16, align 8, !tbaa !9
  %20 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %19) #4
  %21 = load i64, ptr %20, align 8, !tbaa !9
  %22 = icmp ne i64 %21, 0
  br i1 %22, label %23, label %63

23:                                               ; preds = %8
  %24 = load ptr, ptr %10, align 8, !tbaa !5
  %25 = load i64, ptr %16, align 8, !tbaa !9
  %26 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %25) #4
  %27 = load i64, ptr %26, align 8, !tbaa !9
  %28 = load ptr, ptr %9, align 8, !tbaa !5
  %29 = load i64, ptr %16, align 8, !tbaa !9
  %30 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %29) #4
  %31 = load i64, ptr %30, align 8, !tbaa !9
  %32 = add nsw i64 %31, %27
  store i64 %32, ptr %30, align 8, !tbaa !9
  %33 = load i64, ptr %11, align 8, !tbaa !9
  %34 = load i64, ptr %12, align 8, !tbaa !9
  %35 = icmp ne i64 %33, %34
  br i1 %35, label %36, label %59

36:                                               ; preds = %23
  %37 = load ptr, ptr %10, align 8, !tbaa !5
  %38 = load i64, ptr %16, align 8, !tbaa !9
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %38) #4
  %40 = load i64, ptr %39, align 8, !tbaa !9
  %41 = load ptr, ptr %10, align 8, !tbaa !5
  %42 = load i64, ptr %16, align 8, !tbaa !9
  %43 = mul nsw i64 2, %42
  %44 = add nsw i64 %43, 1
  %45 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %44) #4
  %46 = load i64, ptr %45, align 8, !tbaa !9
  %47 = add nsw i64 %46, %40
  store i64 %47, ptr %45, align 8, !tbaa !9
  %48 = load ptr, ptr %10, align 8, !tbaa !5
  %49 = load i64, ptr %16, align 8, !tbaa !9
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %49) #4
  %51 = load i64, ptr %50, align 8, !tbaa !9
  %52 = load ptr, ptr %10, align 8, !tbaa !5
  %53 = load i64, ptr %16, align 8, !tbaa !9
  %54 = mul nsw i64 2, %53
  %55 = add nsw i64 %54, 2
  %56 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %55) #4
  %57 = load i64, ptr %56, align 8, !tbaa !9
  %58 = add nsw i64 %57, %51
  store i64 %58, ptr %56, align 8, !tbaa !9
  br label %59

59:                                               ; preds = %36, %23
  %60 = load ptr, ptr %10, align 8, !tbaa !5
  %61 = load i64, ptr %16, align 8, !tbaa !9
  %62 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %61) #4
  store i64 0, ptr %62, align 8, !tbaa !9
  br label %63

63:                                               ; preds = %59, %8
  %64 = load i64, ptr %11, align 8, !tbaa !9
  %65 = load i64, ptr %12, align 8, !tbaa !9
  %66 = icmp sgt i64 %64, %65
  br i1 %66, label %75, label %67

67:                                               ; preds = %63
  %68 = load i64, ptr %14, align 8, !tbaa !9
  %69 = load i64, ptr %11, align 8, !tbaa !9
  %70 = icmp slt i64 %68, %69
  br i1 %70, label %75, label %71

71:                                               ; preds = %67
  %72 = load i64, ptr %13, align 8, !tbaa !9
  %73 = load i64, ptr %12, align 8, !tbaa !9
  %74 = icmp sgt i64 %72, %73
  br i1 %74, label %75, label %76

75:                                               ; preds = %71, %67, %63
  br label %153

76:                                               ; preds = %71
  %77 = load i64, ptr %11, align 8, !tbaa !9
  %78 = load i64, ptr %13, align 8, !tbaa !9
  %79 = icmp sge i64 %77, %78
  br i1 %79, label %80, label %112

80:                                               ; preds = %76
  %81 = load i64, ptr %12, align 8, !tbaa !9
  %82 = load i64, ptr %14, align 8, !tbaa !9
  %83 = icmp sle i64 %81, %82
  br i1 %83, label %84, label %112

84:                                               ; preds = %80
  %85 = load i64, ptr %15, align 8, !tbaa !9
  %86 = load ptr, ptr %9, align 8, !tbaa !5
  %87 = load i64, ptr %16, align 8, !tbaa !9
  %88 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %86, i64 noundef %87) #4
  %89 = load i64, ptr %88, align 8, !tbaa !9
  %90 = add nsw i64 %89, %85
  store i64 %90, ptr %88, align 8, !tbaa !9
  %91 = load i64, ptr %11, align 8, !tbaa !9
  %92 = load i64, ptr %12, align 8, !tbaa !9
  %93 = icmp ne i64 %91, %92
  br i1 %93, label %94, label %111

94:                                               ; preds = %84
  %95 = load i64, ptr %15, align 8, !tbaa !9
  %96 = load ptr, ptr %10, align 8, !tbaa !5
  %97 = load i64, ptr %16, align 8, !tbaa !9
  %98 = mul nsw i64 2, %97
  %99 = add nsw i64 %98, 1
  %100 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %96, i64 noundef %99) #4
  %101 = load i64, ptr %100, align 8, !tbaa !9
  %102 = add nsw i64 %101, %95
  store i64 %102, ptr %100, align 8, !tbaa !9
  %103 = load i64, ptr %15, align 8, !tbaa !9
  %104 = load ptr, ptr %10, align 8, !tbaa !5
  %105 = load i64, ptr %16, align 8, !tbaa !9
  %106 = mul nsw i64 2, %105
  %107 = add nsw i64 %106, 2
  %108 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %104, i64 noundef %107) #4
  %109 = load i64, ptr %108, align 8, !tbaa !9
  %110 = add nsw i64 %109, %103
  store i64 %110, ptr %108, align 8, !tbaa !9
  br label %111

111:                                              ; preds = %94, %84
  br label %153

112:                                              ; preds = %80, %76
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %113 = load i64, ptr %11, align 8, !tbaa !9
  %114 = load i64, ptr %12, align 8, !tbaa !9
  %115 = add nsw i64 %113, %114
  %116 = sdiv i64 %115, 2
  store i64 %116, ptr %17, align 8, !tbaa !9
  %117 = load ptr, ptr %9, align 8, !tbaa !5
  %118 = load ptr, ptr %10, align 8, !tbaa !5
  %119 = load i64, ptr %11, align 8, !tbaa !9
  %120 = load i64, ptr %17, align 8, !tbaa !9
  %121 = load i64, ptr %13, align 8, !tbaa !9
  %122 = load i64, ptr %14, align 8, !tbaa !9
  %123 = load i64, ptr %15, align 8, !tbaa !9
  %124 = load i64, ptr %16, align 8, !tbaa !9
  %125 = mul nsw i64 2, %124
  %126 = add nsw i64 %125, 1
  call void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %117, ptr noundef nonnull align 8 dereferenceable(24) %118, i64 noundef %119, i64 noundef %120, i64 noundef %121, i64 noundef %122, i64 noundef %123, i64 noundef %126)
  %127 = load ptr, ptr %9, align 8, !tbaa !5
  %128 = load ptr, ptr %10, align 8, !tbaa !5
  %129 = load i64, ptr %17, align 8, !tbaa !9
  %130 = add nsw i64 %129, 1
  %131 = load i64, ptr %12, align 8, !tbaa !9
  %132 = load i64, ptr %13, align 8, !tbaa !9
  %133 = load i64, ptr %14, align 8, !tbaa !9
  %134 = load i64, ptr %15, align 8, !tbaa !9
  %135 = load i64, ptr %16, align 8, !tbaa !9
  %136 = mul nsw i64 2, %135
  %137 = add nsw i64 %136, 2
  call void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %127, ptr noundef nonnull align 8 dereferenceable(24) %128, i64 noundef %130, i64 noundef %131, i64 noundef %132, i64 noundef %133, i64 noundef %134, i64 noundef %137)
  %138 = load ptr, ptr %9, align 8, !tbaa !5
  %139 = load i64, ptr %16, align 8, !tbaa !9
  %140 = mul nsw i64 2, %139
  %141 = add nsw i64 %140, 1
  %142 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %138, i64 noundef %141) #4
  %143 = load ptr, ptr %9, align 8, !tbaa !5
  %144 = load i64, ptr %16, align 8, !tbaa !9
  %145 = mul nsw i64 2, %144
  %146 = add nsw i64 %145, 2
  %147 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %143, i64 noundef %146) #4
  %148 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %142, ptr noundef nonnull align 8 dereferenceable(8) %147)
  %149 = load i64, ptr %148, align 8, !tbaa !9
  %150 = load ptr, ptr %9, align 8, !tbaa !5
  %151 = load i64, ptr %16, align 8, !tbaa !9
  %152 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %150, i64 noundef %151) #4
  store i64 %149, ptr %152, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  br label %153

153:                                              ; preds = %112, %111, %75
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %7) local_unnamed_addr #0 {
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %7) #2
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %.not = icmp eq i64 %10, 0
  br i1 %.not, label %33, label %11

11:                                               ; preds = %8
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %7) #2
  %13 = load i64, ptr %12, align 8, !tbaa !5
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %7) #2
  %15 = load i64, ptr %14, align 8, !tbaa !5
  %16 = add nsw i64 %15, %13
  store i64 %16, ptr %14, align 8, !tbaa !5
  %.not65 = icmp eq i64 %2, %3
  br i1 %.not65, label %31, label %17

17:                                               ; preds = %11
  %18 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %7) #2
  %19 = load i64, ptr %18, align 8, !tbaa !5
  %20 = shl nsw i64 %7, 1
  %21 = or disjoint i64 %20, 1
  %22 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %21) #2
  %23 = load i64, ptr %22, align 8, !tbaa !5
  %24 = add nsw i64 %23, %19
  store i64 %24, ptr %22, align 8, !tbaa !5
  %25 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %7) #2
  %26 = load i64, ptr %25, align 8, !tbaa !5
  %27 = add nsw i64 %20, 2
  %28 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %27) #2
  %29 = load i64, ptr %28, align 8, !tbaa !5
  %30 = add nsw i64 %29, %26
  store i64 %30, ptr %28, align 8, !tbaa !5
  br label %31

31:                                               ; preds = %17, %11
  %32 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %7) #2
  store i64 0, ptr %32, align 8, !tbaa !5
  br label %33

33:                                               ; preds = %31, %8
  %34 = icmp sgt i64 %2, %3
  %35 = icmp slt i64 %5, %2
  %or.cond = or i1 %34, %35
  %36 = icmp sgt i64 %4, %3
  %or.cond69 = or i1 %36, %or.cond
  br i1 %or.cond69, label %common.ret71, label %37

37:                                               ; preds = %33
  %.not66 = icmp slt i64 %2, %4
  %.not67 = icmp sgt i64 %3, %5
  %or.cond70 = or i1 %.not66, %.not67
  br i1 %or.cond70, label %52, label %38

38:                                               ; preds = %37
  %39 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %7) #2
  %40 = load i64, ptr %39, align 8, !tbaa !5
  %41 = add nsw i64 %40, %6
  store i64 %41, ptr %39, align 8, !tbaa !5
  %.not68 = icmp eq i64 %2, %3
  br i1 %.not68, label %common.ret71, label %42

42:                                               ; preds = %38
  %43 = shl nsw i64 %7, 1
  %44 = or disjoint i64 %43, 1
  %45 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %44) #2
  %46 = load i64, ptr %45, align 8, !tbaa !5
  %47 = add nsw i64 %46, %6
  store i64 %47, ptr %45, align 8, !tbaa !5
  %48 = add nsw i64 %43, 2
  %49 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %48) #2
  %50 = load i64, ptr %49, align 8, !tbaa !5
  %51 = add nsw i64 %50, %6
  store i64 %51, ptr %49, align 8, !tbaa !5
  br label %common.ret71

common.ret71:                                     ; preds = %38, %42, %33, %52
  ret void

52:                                               ; preds = %37
  %53 = add nsw i64 %3, %2
  %54 = sdiv i64 %53, 2
  %55 = shl nsw i64 %7, 1
  %56 = or disjoint i64 %55, 1
  tail call void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2, i64 noundef %54, i64 noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %56)
  %57 = add nsw i64 %54, 1
  %58 = add nsw i64 %55, 2
  tail call void @_Z13updateRangeSTRSt6vectorIxSaIxEES2_xxxxxx(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %57, i64 noundef %3, i64 noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %58)
  %59 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %56) #2
  %60 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %58) #2
  %61 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %59, ptr noundef nonnull align 8 dereferenceable(8) %60)
  %62 = load i64, ptr %61, align 8, !tbaa !5
  %63 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %7) #2
  store i64 %62, ptr %63, align 8, !tbaa !5
  br label %common.ret71
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass