; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_tim)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32, [6 x i32], [4 x i32], i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_OC_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %10

10:                                               ; preds = %3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %11, i32 0, i32 4
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

16:                                               ; preds = %10
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 4
  store i32 1, ptr %18, align 8, !tbaa !11
  br label %19

19:                                               ; preds = %16
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  %22 = load i32, ptr %7, align 4, !tbaa !9
  switch i32 %22, label %53 [
    i32 0, label %23
    i32 4, label %28
    i32 8, label %33
    i32 12, label %38
    i32 16, label %43
    i32 20, label %48
  ]

23:                                               ; preds = %21
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %25, align 8, !tbaa !14
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC1_SetConfig(ptr noundef %26, ptr noundef %27)
  br label %54

28:                                               ; preds = %21
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %29, i32 0, i32 0
  %31 = load ptr, ptr %30, align 8, !tbaa !14
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC2_SetConfig(ptr noundef %31, ptr noundef %32)
  br label %54

33:                                               ; preds = %21
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !14
  %37 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC3_SetConfig(ptr noundef %36, ptr noundef %37)
  br label %54

38:                                               ; preds = %21
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %39, i32 0, i32 0
  %41 = load ptr, ptr %40, align 8, !tbaa !14
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC4_SetConfig(ptr noundef %41, ptr noundef %42)
  br label %54

43:                                               ; preds = %21
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !14
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC5_SetConfig(ptr noundef %46, ptr noundef %47)
  br label %54

48:                                               ; preds = %21
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !14
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  call void @TIM_OC6_SetConfig(ptr noundef %51, ptr noundef %52)
  br label %54

53:                                               ; preds = %21
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %54

54:                                               ; preds = %53, %48, %43, %38, %33, %28, %23
  br label %55

55:                                               ; preds = %54
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %56, i32 0, i32 4
  store i32 0, ptr %57, align 8, !tbaa !11
  br label %58

58:                                               ; preds = %55
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %60, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

61:                                               ; preds = %59, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %62 = load i32, ptr %4, align 4
  ret i32 %62
}

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC3_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC4_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC5_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC6_SetConfig(ptr noundef, ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100, !7, i64 104, !7, i64 128, !10, i64 144}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_OC_ConfigChannel(ptr nocapture noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %22, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = tail call i32 @llvm.fshl.i32(i32 %2, i32 %2, i32 30)
  switch i32 %8, label %21 [
    i32 0, label %9
    i32 1, label %11
    i32 2, label %13
    i32 3, label %15
    i32 4, label %17
    i32 5, label %19
  ]

9:                                                ; preds = %7
  %10 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC1_SetConfig(ptr noundef %10, ptr noundef %1)
  br label %21

11:                                               ; preds = %7
  %12 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC2_SetConfig(ptr noundef %12, ptr noundef %1)
  br label %21

13:                                               ; preds = %7
  %14 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC3_SetConfig(ptr noundef %14, ptr noundef %1)
  br label %21

15:                                               ; preds = %7
  %16 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC4_SetConfig(ptr noundef %16, ptr noundef %1)
  br label %21

17:                                               ; preds = %7
  %18 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC5_SetConfig(ptr noundef %18, ptr noundef %1)
  br label %21

19:                                               ; preds = %7
  %20 = load ptr, ptr %0, align 8, !tbaa !12
  tail call void @TIM_OC6_SetConfig(ptr noundef %20, ptr noundef %1)
  br label %21

21:                                               ; preds = %7, %9, %11, %13, %15, %17, %19
  %.0 = phi i32 [ 0, %19 ], [ 0, %17 ], [ 0, %15 ], [ 0, %13 ], [ 0, %11 ], [ 0, %9 ], [ 1, %7 ]
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %22

22:                                               ; preds = %3, %21
  %.017 = phi i32 [ %.0, %21 ], [ 2, %3 ]
  ret i32 %.017
}

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC3_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC4_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC5_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC6_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100, !8, i64 104, !8, i64 128, !11, i64 144}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass