; LLVM IR from ctlst-tech/catpilot :: bsp/mcu/core/stm32/h753/hal/src (stm32h7xx_hal_adc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @ADC_Disable(ptr noundef %0) #2 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %7, i32 0, i32 0
  %9 = load ptr, ptr %8, align 8, !tbaa !9
  %10 = call i32 @LL_ADC_IsDisableOngoing(ptr noundef %9)
  store i32 %10, ptr %5, align 4, !tbaa !15
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %11, i32 0, i32 0
  %13 = load ptr, ptr %12, align 8, !tbaa !9
  %14 = call i32 @LL_ADC_IsEnabled(ptr noundef %13)
  %15 = zext i32 %14 to i64
  %16 = icmp ne i64 %15, 0
  br i1 %16, label %17, label %89

17:                                               ; preds = %1
  %18 = load i32, ptr %5, align 4, !tbaa !15
  %19 = zext i32 %18 to i64
  %20 = icmp eq i64 %19, 0
  br i1 %20, label %21, label %89

21:                                               ; preds = %17
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !9
  %25 = getelementptr inbounds %struct.ADC_TypeDef, ptr %24, i32 0, i32 2
  %26 = load volatile i32, ptr %25, align 4, !tbaa !16
  %27 = zext i32 %26 to i64
  %28 = and i64 %27, 13
  %29 = icmp eq i64 %28, 1
  br i1 %29, label %30, label %38

30:                                               ; preds = %21
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %31, i32 0, i32 0
  %33 = load ptr, ptr %32, align 8, !tbaa !9
  call void @LL_ADC_Disable(ptr noundef %33)
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !9
  %37 = getelementptr inbounds %struct.ADC_TypeDef, ptr %36, i32 0, i32 0
  store volatile i32 3, ptr %37, align 4, !tbaa !18
  br label %49

38:                                               ; preds = %21
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 4
  %41 = load volatile i32, ptr %40, align 4, !tbaa !19
  %42 = zext i32 %41 to i64
  %43 = or i64 %42, 16
  %44 = trunc i64 %43 to i32
  store volatile i32 %44, ptr %40, align 4, !tbaa !19
  %45 = load ptr, ptr %3, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %45, i32 0, i32 5
  %47 = load volatile i32, ptr %46, align 8, !tbaa !20
  %48 = or i32 %47, 1
  store volatile i32 %48, ptr %46, align 8, !tbaa !20
  store i32 1, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

49:                                               ; preds = %30
  %50 = call i32 @HAL_GetTick()
  store i32 %50, ptr %4, align 4, !tbaa !15
  br label %51

51:                                               ; preds = %87, %49
  %52 = load ptr, ptr %3, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !9
  %55 = getelementptr inbounds %struct.ADC_TypeDef, ptr %54, i32 0, i32 2
  %56 = load volatile i32, ptr %55, align 4, !tbaa !16
  %57 = zext i32 %56 to i64
  %58 = and i64 %57, 1
  %59 = icmp ne i64 %58, 0
  br i1 %59, label %60, label %88

60:                                               ; preds = %51
  %61 = call i32 @HAL_GetTick()
  %62 = load i32, ptr %4, align 4, !tbaa !15
  %63 = sub i32 %61, %62
  %64 = zext i32 %63 to i64
  %65 = icmp ugt i64 %64, 2
  br i1 %65, label %66, label %87

66:                                               ; preds = %60
  %67 = load ptr, ptr %3, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !9
  %70 = getelementptr inbounds %struct.ADC_TypeDef, ptr %69, i32 0, i32 2
  %71 = load volatile i32, ptr %70, align 4, !tbaa !16
  %72 = zext i32 %71 to i64
  %73 = and i64 %72, 1
  %74 = icmp ne i64 %73, 0
  br i1 %74, label %75, label %86

75:                                               ; preds = %66
  %76 = load ptr, ptr %3, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %76, i32 0, i32 4
  %78 = load volatile i32, ptr %77, align 4, !tbaa !19
  %79 = zext i32 %78 to i64
  %80 = or i64 %79, 16
  %81 = trunc i64 %80 to i32
  store volatile i32 %81, ptr %77, align 4, !tbaa !19
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %82, i32 0, i32 5
  %84 = load volatile i32, ptr %83, align 8, !tbaa !20
  %85 = or i32 %84, 1
  store volatile i32 %85, ptr %83, align 8, !tbaa !20
  store i32 1, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

86:                                               ; preds = %66
  br label %87

87:                                               ; preds = %86, %60
  br label %51, !llvm.loop !21

88:                                               ; preds = %51
  br label %89

89:                                               ; preds = %88, %17, %1
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %90

90:                                               ; preds = %89, %75, %38
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %91 = load i32, ptr %2, align 4
  ret i32 %91
}

declare i32 @HAL_GetTick() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDisableOngoing(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_Disable(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"", !6, i64 0, !11, i64 8, !6, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !14, i64 108}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !13, i64 60}
!12 = !{!"int", !7, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!14 = !{!"", !12, i64 0, !12, i64 4}
!15 = !{!12, !12, i64 0}
!16 = !{!17, !12, i64 8}
!17 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !7, i64 112, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !7, i64 144, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200}
!18 = !{!17, !12, i64 0}
!19 = !{!10, !12, i64 100}
!20 = !{!10, !12, i64 104}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @ADC_Disable(ptr noundef %0) local_unnamed_addr #1 {
  %2 = load ptr, ptr %0, align 8, !tbaa !5
  %3 = tail call i32 @LL_ADC_IsDisableOngoing(ptr noundef %2)
  %4 = load ptr, ptr %0, align 8, !tbaa !5
  %5 = tail call i32 @LL_ADC_IsEnabled(ptr noundef %4)
  %6 = icmp ne i32 %5, 0
  %7 = icmp eq i32 %3, 0
  %or.cond = select i1 %6, i1 %7, i1 false
  br i1 %or.cond, label %8, label %.loopexit

8:                                                ; preds = %1
  %9 = load ptr, ptr %0, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %9, i64 8
  %11 = load volatile i32, ptr %10, align 4, !tbaa !14
  %12 = and i32 %11, 13
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %14, label %.loopexit.sink.split

14:                                               ; preds = %8
  tail call void @LL_ADC_Disable(ptr noundef nonnull %9)
  %15 = load ptr, ptr %0, align 8, !tbaa !5
  store volatile i32 3, ptr %15, align 4, !tbaa !16
  %16 = tail call i32 @HAL_GetTick() #3
  %17 = load ptr, ptr %0, align 8, !tbaa !5
  %18 = getelementptr inbounds i8, ptr %17, i64 8
  %19 = load volatile i32, ptr %18, align 4, !tbaa !14
  %20 = and i32 %19, 1
  %.not16 = icmp eq i32 %20, 0
  br i1 %.not16, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %14, %28
  %21 = tail call i32 @HAL_GetTick() #3
  %22 = sub i32 %21, %16
  %23 = icmp ugt i32 %22, 2
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  br i1 %23, label %24, label %28

24:                                               ; preds = %.lr.ph
  %25 = getelementptr inbounds i8, ptr %.pre, i64 8
  %26 = load volatile i32, ptr %25, align 4, !tbaa !14
  %27 = and i32 %26, 1
  %.not15 = icmp eq i32 %27, 0
  br i1 %.not15, label %28, label %.loopexit.sink.split

28:                                               ; preds = %24, %.lr.ph
  %29 = getelementptr inbounds i8, ptr %.pre, i64 8
  %30 = load volatile i32, ptr %29, align 4, !tbaa !14
  %31 = and i32 %30, 1
  %.not = icmp eq i32 %31, 0
  br i1 %.not, label %.loopexit, label %.lr.ph, !llvm.loop !17

.loopexit.sink.split:                             ; preds = %24, %8
  %32 = getelementptr inbounds i8, ptr %0, i64 100
  %33 = load volatile i32, ptr %32, align 4, !tbaa !19
  %34 = or i32 %33, 16
  store volatile i32 %34, ptr %32, align 4, !tbaa !19
  %35 = getelementptr inbounds i8, ptr %0, i64 104
  %36 = load volatile i32, ptr %35, align 8, !tbaa !20
  %37 = or i32 %36, 1
  store volatile i32 %37, ptr %35, align 8, !tbaa !20
  br label %.loopexit

.loopexit:                                        ; preds = %28, %.loopexit.sink.split, %14, %1
  %.0 = phi i32 [ 0, %1 ], [ 0, %14 ], [ 1, %.loopexit.sink.split ], [ 0, %28 ]
  ret i32 %.0
}

declare i32 @HAL_GetTick() local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDisableOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_Disable(ptr noundef) local_unnamed_addr #0

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!15, !11, i64 8}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!16 = !{!15, !11, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!6, !11, i64 100}
!20 = !{!6, !11, i64 104}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass