; LLVM IR from trabucayre/openFPGALoader :: src/lattice.ll (ZN7Lattice13readStatusRegEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Device = type <{ ptr, ptr, %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", i32, i8, i8, i8, i8 }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_ZN7Lattice13readStatusRegEv(ptr noundef nonnull align 8 dereferenceable(152) %0) #2 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i64, align 8
  %4 = alloca [8 x i8], align 1
  %5 = alloca [8 x i8], align 1
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %7 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  %8 = call noundef i32 @_ZN7Lattice18get_statusreg_sizeEv(ptr noundef nonnull align 8 dereferenceable(152) %7)
  %9 = sdiv i32 %8, 8
  store i32 %9, ptr %6, align 4, !tbaa !9
  %10 = getelementptr inbounds [8 x i8], ptr %5, i64 0, i64 0
  call void @llvm.memset.p0.i64(ptr align 1 %10, i8 0, i64 8, i1 false)
  %11 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 0
  call void @llvm.memset.p0.i64(ptr align 1 %11, i8 0, i64 8, i1 false)
  %12 = getelementptr inbounds [8 x i8], ptr %5, i64 0, i64 0
  %13 = load i32, ptr %6, align 4, !tbaa !9
  %14 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 0
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = call noundef zeroext i1 @_ZN7Lattice5wr_rdEhPhiS0_ib(ptr noundef nonnull align 8 dereferenceable(152) %7, i8 noundef zeroext 60, ptr noundef %12, i32 noundef %13, ptr noundef %14, i32 noundef %15, i1 noundef zeroext false)
  %17 = getelementptr inbounds %class.Device, ptr %7, i32 0, i32 1
  %18 = load ptr, ptr %17, align 8, !tbaa !11
  call void @_ZN4Jtag9set_stateENS_10tapState_tEh(ptr noundef nonnull align 8 dereferenceable(193) %18, i32 noundef 1, i8 noundef zeroext 1)
  %19 = getelementptr inbounds %class.Device, ptr %7, i32 0, i32 1
  %20 = load ptr, ptr %19, align 8, !tbaa !11
  call void @_ZN4Jtag9toggleClkEi(ptr noundef nonnull align 8 dereferenceable(193) %20, i32 noundef 1000)
  %21 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 7
  %22 = load i8, ptr %21, align 1, !tbaa !18
  %23 = zext i8 %22 to i64
  %24 = shl i64 %23, 56
  %25 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 6
  %26 = load i8, ptr %25, align 1, !tbaa !18
  %27 = zext i8 %26 to i64
  %28 = shl i64 %27, 48
  %29 = or i64 %24, %28
  %30 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 5
  %31 = load i8, ptr %30, align 1, !tbaa !18
  %32 = zext i8 %31 to i64
  %33 = shl i64 %32, 40
  %34 = or i64 %29, %33
  %35 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 4
  %36 = load i8, ptr %35, align 1, !tbaa !18
  %37 = zext i8 %36 to i64
  %38 = shl i64 %37, 32
  %39 = or i64 %34, %38
  %40 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 3
  %41 = load i8, ptr %40, align 1, !tbaa !18
  %42 = zext i8 %41 to i32
  %43 = shl i32 %42, 24
  %44 = sext i32 %43 to i64
  %45 = or i64 %39, %44
  %46 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 2
  %47 = load i8, ptr %46, align 1, !tbaa !18
  %48 = zext i8 %47 to i32
  %49 = shl i32 %48, 16
  %50 = sext i32 %49 to i64
  %51 = or i64 %45, %50
  %52 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 1
  %53 = load i8, ptr %52, align 1, !tbaa !18
  %54 = zext i8 %53 to i32
  %55 = shl i32 %54, 8
  %56 = sext i32 %55 to i64
  %57 = or i64 %51, %56
  %58 = getelementptr inbounds [8 x i8], ptr %4, i64 0, i64 0
  %59 = load i8, ptr %58, align 1, !tbaa !18
  %60 = zext i8 %59 to i64
  %61 = or i64 %57, %60
  store i64 %61, ptr %3, align 8, !tbaa !19
  %62 = load i64, ptr %3, align 8, !tbaa !19
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
  ret i64 %62
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN7Lattice5wr_rdEhPhiS0_ib(ptr noundef nonnull align 8 dereferenceable(152), i8 noundef zeroext, ptr noundef, i32 noundef, ptr noundef, i32 noundef, i1 noundef zeroext) #2 align 2

declare void @_ZN4Jtag9set_stateENS_10tapState_tEh(ptr noundef nonnull align 8 dereferenceable(193), i32 noundef, i8 noundef zeroext) #3

declare void @_ZN4Jtag9toggleClkEi(ptr noundef nonnull align 8 dereferenceable(193), i32 noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN7Lattice18get_statusreg_sizeEv(ptr noundef nonnull align 8 dereferenceable(152)) #4 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 8}
!12 = !{!"_ZTS6Device", !6, i64 8, !13, i64 16, !13, i64 48, !16, i64 80, !17, i64 84, !17, i64 85, !17, i64 86}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"_ZTSN6Device9prog_modeE", !7, i64 0}
!17 = !{!"bool", !7, i64 0}
!18 = !{!7, !7, i64 0}
!19 = !{!15, !15, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_ZN7Lattice13readStatusRegEv(ptr noundef nonnull align 8 dereferenceable(152) %0) local_unnamed_addr #1 align 2 {
  %2 = alloca [8 x i8], align 8
  %3 = alloca [8 x i8], align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #4
  %4 = tail call noundef i32 @_ZN7Lattice18get_statusreg_sizeEv(ptr noundef nonnull align 8 dereferenceable(152) %0)
  %5 = sdiv i32 %4, 8
  store i64 0, ptr %3, align 8
  store i64 0, ptr %2, align 8
  %6 = call noundef zeroext i1 @_ZN7Lattice5wr_rdEhPhiS0_ib(ptr noundef nonnull align 8 dereferenceable(152) %0, i8 noundef zeroext 60, ptr noundef nonnull %3, i32 noundef %5, ptr noundef nonnull %2, i32 noundef %5, i1 noundef zeroext false)
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = load ptr, ptr %7, align 8, !tbaa !5
  call void @_ZN4Jtag9set_stateENS_10tapState_tEh(ptr noundef nonnull align 8 dereferenceable(193) %8, i32 noundef 1, i8 noundef zeroext 1)
  %9 = load ptr, ptr %7, align 8, !tbaa !5
  call void @_ZN4Jtag9toggleClkEi(ptr noundef nonnull align 8 dereferenceable(193) %9, i32 noundef 1000)
  %10 = getelementptr inbounds i8, ptr %2, i64 4
  %11 = load i32, ptr %10, align 4
  %12 = zext i32 %11 to i64
  %13 = shl nuw i64 %12, 32
  %14 = getelementptr inbounds i8, ptr %2, i64 3
  %15 = load i8, ptr %14, align 1, !tbaa !15
  %16 = zext i8 %15 to i32
  %17 = shl nuw i32 %16, 24
  %18 = sext i32 %17 to i64
  %19 = or i64 %13, %18
  %20 = getelementptr inbounds i8, ptr %2, i64 2
  %21 = load i8, ptr %20, align 2, !tbaa !15
  %22 = zext i8 %21 to i64
  %23 = shl nuw nsw i64 %22, 16
  %24 = or disjoint i64 %19, %23
  %25 = getelementptr inbounds i8, ptr %2, i64 1
  %26 = load i8, ptr %25, align 1, !tbaa !15
  %27 = zext i8 %26 to i64
  %28 = shl nuw nsw i64 %27, 8
  %29 = or disjoint i64 %24, %28
  %30 = load i8, ptr %2, align 8, !tbaa !15
  %31 = zext i8 %30 to i64
  %32 = or disjoint i64 %29, %31
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #4
  ret i64 %32
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN7Lattice5wr_rdEhPhiS0_ib(ptr noundef nonnull align 8 dereferenceable(152), i8 noundef zeroext, ptr noundef, i32 noundef, ptr noundef, i32 noundef, i1 noundef zeroext) local_unnamed_addr #1 align 2

declare void @_ZN4Jtag9set_stateENS_10tapState_tEh(ptr noundef nonnull align 8 dereferenceable(193), i32 noundef, i8 noundef zeroext) local_unnamed_addr #2

declare void @_ZN4Jtag9toggleClkEi(ptr noundef nonnull align 8 dereferenceable(193), i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN7Lattice18get_statusreg_sizeEv(ptr noundef nonnull align 8 dereferenceable(152)) local_unnamed_addr #3 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTS6Device", !7, i64 8, !10, i64 16, !10, i64 48, !13, i64 80, !14, i64 84, !14, i64 85, !14, i64 86}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !11, i64 0, !12, i64 8, !8, i64 16}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !7, i64 0}
!12 = !{!"long", !8, i64 0}
!13 = !{!"_ZTSN6Device9prog_modeE", !8, i64 0}
!14 = !{!"bool", !8, i64 0}
!15 = !{!8, !8, i64 0}


; Effective O3 passes: AggressiveInstCombinePass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass