; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (GetTxEvent)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FDCAN_HandleTypeDef = type { ptr, ptr, %struct.FDCAN_InitTypeDef, %struct.FDCAN_MsgRamAddressTypeDef, i32, i32, i32, i32 }
%struct.FDCAN_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FDCAN_MsgRamAddressTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FDCAN_GlobalTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, [8 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32 }
%struct.FDCAN_TxEventFifoTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_FDCAN_GetTxEvent(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %10, i32 0, i32 5
  %12 = load volatile i32, ptr %11, align 8, !tbaa !9
  store i32 %12, ptr %8, align 4, !tbaa !14
  %13 = load i32, ptr %8, align 4, !tbaa !14
  %14 = icmp eq i32 %13, 2
  br i1 %14, label %15, label %134

15:                                               ; preds = %2
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %16, i32 0, i32 0
  %18 = load ptr, ptr %17, align 8, !tbaa !15
  %19 = getelementptr inbounds %struct.FDCAN_GlobalTypeDef, ptr %18, i32 0, i32 49
  %20 = load volatile i32, ptr %19, align 4, !tbaa !16
  %21 = zext i32 %20 to i64
  %22 = and i64 %21, 4128768
  %23 = icmp eq i64 %22, 0
  br i1 %23, label %24, label %29

24:                                               ; preds = %15
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %25, i32 0, i32 7
  %27 = load volatile i32, ptr %26, align 8, !tbaa !18
  %28 = or i32 %27, 32
  store volatile i32 %28, ptr %26, align 8, !tbaa !18
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %139

29:                                               ; preds = %15
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %30, i32 0, i32 0
  %32 = load ptr, ptr %31, align 8, !tbaa !15
  %33 = getelementptr inbounds %struct.FDCAN_GlobalTypeDef, ptr %32, i32 0, i32 50
  %34 = load volatile i32, ptr %33, align 4, !tbaa !19
  %35 = zext i32 %34 to i64
  %36 = and i64 %35, 63
  %37 = icmp eq i64 %36, 0
  br i1 %37, label %38, label %43

38:                                               ; preds = %29
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %39, i32 0, i32 7
  %41 = load volatile i32, ptr %40, align 8, !tbaa !18
  %42 = or i32 %41, 256
  store volatile i32 %42, ptr %40, align 8, !tbaa !18
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %139

43:                                               ; preds = %29
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !15
  %47 = getelementptr inbounds %struct.FDCAN_GlobalTypeDef, ptr %46, i32 0, i32 50
  %48 = load volatile i32, ptr %47, align 4, !tbaa !19
  %49 = zext i32 %48 to i64
  %50 = and i64 %49, 7936
  %51 = lshr i64 %50, 8
  %52 = trunc i64 %51 to i32
  store i32 %52, ptr %7, align 4, !tbaa !14
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %53, i32 0, i32 3
  %55 = getelementptr inbounds %struct.FDCAN_MsgRamAddressTypeDef, ptr %54, i32 0, i32 5
  %56 = load i32, ptr %55, align 4, !tbaa !20
  %57 = load i32, ptr %7, align 4, !tbaa !14
  %58 = mul i32 %57, 2
  %59 = mul i32 %58, 4
  %60 = add i32 %56, %59
  %61 = zext i32 %60 to i64
  %62 = inttoptr i64 %61 to ptr
  store ptr %62, ptr %6, align 8, !tbaa !5
  %63 = load ptr, ptr %6, align 8, !tbaa !5
  %64 = load i32, ptr %63, align 4, !tbaa !14
  %65 = and i32 %64, 1073741824
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %66, i32 0, i32 1
  store i32 %65, ptr %67, align 4, !tbaa !21
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %68, i32 0, i32 1
  %70 = load i32, ptr %69, align 4, !tbaa !21
  %71 = icmp eq i32 %70, 0
  br i1 %71, label %72, label %79

72:                                               ; preds = %43
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  %74 = load i32, ptr %73, align 4, !tbaa !14
  %75 = and i32 %74, 536608768
  %76 = lshr i32 %75, 18
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %77, i32 0, i32 0
  store i32 %76, ptr %78, align 4, !tbaa !22
  br label %85

79:                                               ; preds = %43
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = load i32, ptr %80, align 4, !tbaa !14
  %82 = and i32 %81, 536870911
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %83, i32 0, i32 0
  store i32 %82, ptr %84, align 4, !tbaa !22
  br label %85

85:                                               ; preds = %79, %72
  %86 = load ptr, ptr %6, align 8, !tbaa !5
  %87 = load i32, ptr %86, align 4, !tbaa !14
  %88 = and i32 %87, 536870912
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %89, i32 0, i32 2
  store i32 %88, ptr %90, align 4, !tbaa !23
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = load i32, ptr %91, align 4, !tbaa !14
  %93 = and i32 %92, -2147483648
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %94, i32 0, i32 4
  store i32 %93, ptr %95, align 4, !tbaa !24
  %96 = load ptr, ptr %6, align 8, !tbaa !5
  %97 = getelementptr inbounds i32, ptr %96, i32 1
  store ptr %97, ptr %6, align 8, !tbaa !5
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  %99 = load i32, ptr %98, align 4, !tbaa !14
  %100 = and i32 %99, 65535
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %101, i32 0, i32 7
  store i32 %100, ptr %102, align 4, !tbaa !25
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = load i32, ptr %103, align 4, !tbaa !14
  %105 = and i32 %104, 983040
  %106 = load ptr, ptr %5, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %106, i32 0, i32 3
  store i32 %105, ptr %107, align 4, !tbaa !26
  %108 = load ptr, ptr %6, align 8, !tbaa !5
  %109 = load i32, ptr %108, align 4, !tbaa !14
  %110 = and i32 %109, 1048576
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %111, i32 0, i32 5
  store i32 %110, ptr %112, align 4, !tbaa !27
  %113 = load ptr, ptr %6, align 8, !tbaa !5
  %114 = load i32, ptr %113, align 4, !tbaa !14
  %115 = and i32 %114, 2097152
  %116 = load ptr, ptr %5, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %116, i32 0, i32 6
  store i32 %115, ptr %117, align 4, !tbaa !28
  %118 = load ptr, ptr %6, align 8, !tbaa !5
  %119 = load i32, ptr %118, align 4, !tbaa !14
  %120 = and i32 %119, 12582912
  %121 = load ptr, ptr %5, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %121, i32 0, i32 9
  store i32 %120, ptr %122, align 4, !tbaa !29
  %123 = load ptr, ptr %6, align 8, !tbaa !5
  %124 = load i32, ptr %123, align 4, !tbaa !14
  %125 = and i32 %124, -16777216
  %126 = lshr i32 %125, 24
  %127 = load ptr, ptr %5, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.FDCAN_TxEventFifoTypeDef, ptr %127, i32 0, i32 8
  store i32 %126, ptr %128, align 4, !tbaa !30
  %129 = load i32, ptr %7, align 4, !tbaa !14
  %130 = load ptr, ptr %4, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %130, i32 0, i32 0
  %132 = load ptr, ptr %131, align 8, !tbaa !15
  %133 = getelementptr inbounds %struct.FDCAN_GlobalTypeDef, ptr %132, i32 0, i32 51
  store volatile i32 %129, ptr %133, align 4, !tbaa !31
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %139

134:                                              ; preds = %2
  %135 = load ptr, ptr %4, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.FDCAN_HandleTypeDef, ptr %135, i32 0, i32 7
  %137 = load volatile i32, ptr %136, align 8, !tbaa !18
  %138 = or i32 %137, 8
  store volatile i32 %138, ptr %136, align 8, !tbaa !18
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %139

139:                                              ; preds = %134, %85, %38, %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  %140 = load i32, ptr %3, align 4
  ret i32 %140
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 168}
!10 = !{!"", !6, i64 0, !6, i64 8, !11, i64 16, !13, i64 124, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!12 = !{!"int", !7, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36}
!14 = !{!12, !12, i64 0}
!15 = !{!10, !6, i64 0}
!16 = !{!17, !12, i64 240}
!17 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !7, i64 48, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !7, i64 96, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !12, i64 144, !12, i64 148, !12, i64 152, !12, i64 156, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200, !12, i64 204, !12, i64 208, !12, i64 212, !12, i64 216, !12, i64 220, !12, i64 224, !12, i64 228, !7, i64 232, !12, i64 240, !12, i64 244, !12, i64 248, !12, i64 252}
!18 = !{!10, !12, i64 176}
!19 = !{!17, !12, i64 244}
!20 = !{!10, !12, i64 144}
!21 = !{!13, !12, i64 4}
!22 = !{!13, !12, i64 0}
!23 = !{!13, !12, i64 8}
!24 = !{!13, !12, i64 16}
!25 = !{!13, !12, i64 28}
!26 = !{!13, !12, i64 12}
!27 = !{!13, !12, i64 20}
!28 = !{!13, !12, i64 24}
!29 = !{!13, !12, i64 36}
!30 = !{!13, !12, i64 32}
!31 = !{!17, !12, i64 248}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_FDCAN_GetTxEvent(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 168
  %4 = load volatile i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 2
  br i1 %5, label %6, label %69

6:                                                ; preds = %2
  %7 = load ptr, ptr %0, align 8, !tbaa !13
  %8 = getelementptr inbounds i8, ptr %7, i64 240
  %9 = load volatile i32, ptr %8, align 4, !tbaa !14
  %10 = and i32 %9, 4128768
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %16

12:                                               ; preds = %6
  %13 = getelementptr inbounds i8, ptr %0, i64 176
  %14 = load volatile i32, ptr %13, align 8, !tbaa !16
  %15 = or i32 %14, 32
  store volatile i32 %15, ptr %13, align 8, !tbaa !16
  br label %73

16:                                               ; preds = %6
  %17 = getelementptr inbounds i8, ptr %7, i64 244
  %18 = load volatile i32, ptr %17, align 4, !tbaa !17
  %19 = and i32 %18, 63
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %25

21:                                               ; preds = %16
  %22 = getelementptr inbounds i8, ptr %0, i64 176
  %23 = load volatile i32, ptr %22, align 8, !tbaa !16
  %24 = or i32 %23, 256
  store volatile i32 %24, ptr %22, align 8, !tbaa !16
  br label %73

25:                                               ; preds = %16
  %26 = load volatile i32, ptr %17, align 4, !tbaa !17
  %27 = lshr i32 %26, 8
  %28 = and i32 %27, 31
  %29 = getelementptr inbounds i8, ptr %0, i64 144
  %30 = load i32, ptr %29, align 4, !tbaa !18
  %31 = shl nuw nsw i32 %28, 3
  %32 = add i32 %31, %30
  %33 = zext i32 %32 to i64
  %34 = inttoptr i64 %33 to ptr
  %35 = load i32, ptr %34, align 4, !tbaa !19
  %36 = and i32 %35, 1073741824
  %37 = getelementptr inbounds i8, ptr %1, i64 4
  store i32 %36, ptr %37, align 4, !tbaa !20
  %38 = icmp eq i32 %36, 0
  %39 = load i32, ptr %34, align 4, !tbaa !19
  %40 = and i32 %39, 536870911
  %41 = lshr i32 %39, 18
  %42 = and i32 %41, 2047
  %storemerge = select i1 %38, i32 %42, i32 %40
  store i32 %storemerge, ptr %1, align 4, !tbaa !21
  %43 = load i32, ptr %34, align 4, !tbaa !19
  %44 = and i32 %43, 536870912
  %45 = getelementptr inbounds i8, ptr %1, i64 8
  store i32 %44, ptr %45, align 4, !tbaa !22
  %46 = load i32, ptr %34, align 4, !tbaa !19
  %47 = and i32 %46, -2147483648
  %48 = getelementptr inbounds i8, ptr %1, i64 16
  store i32 %47, ptr %48, align 4, !tbaa !23
  %49 = getelementptr inbounds i8, ptr %34, i64 4
  %50 = load i32, ptr %49, align 4, !tbaa !19
  %51 = and i32 %50, 65535
  %52 = getelementptr inbounds i8, ptr %1, i64 28
  store i32 %51, ptr %52, align 4, !tbaa !24
  %53 = load i32, ptr %49, align 4, !tbaa !19
  %54 = and i32 %53, 983040
  %55 = getelementptr inbounds i8, ptr %1, i64 12
  store i32 %54, ptr %55, align 4, !tbaa !25
  %56 = load i32, ptr %49, align 4, !tbaa !19
  %57 = and i32 %56, 1048576
  %58 = getelementptr inbounds i8, ptr %1, i64 20
  store i32 %57, ptr %58, align 4, !tbaa !26
  %59 = load i32, ptr %49, align 4, !tbaa !19
  %60 = and i32 %59, 2097152
  %61 = getelementptr inbounds i8, ptr %1, i64 24
  store i32 %60, ptr %61, align 4, !tbaa !27
  %62 = load i32, ptr %49, align 4, !tbaa !19
  %63 = and i32 %62, 12582912
  %64 = getelementptr inbounds i8, ptr %1, i64 36
  store i32 %63, ptr %64, align 4, !tbaa !28
  %65 = load i32, ptr %49, align 4, !tbaa !19
  %66 = lshr i32 %65, 24
  %67 = getelementptr inbounds i8, ptr %1, i64 32
  store i32 %66, ptr %67, align 4, !tbaa !29
  %68 = getelementptr inbounds i8, ptr %7, i64 248
  store volatile i32 %28, ptr %68, align 4, !tbaa !30
  br label %73

69:                                               ; preds = %2
  %70 = getelementptr inbounds i8, ptr %0, i64 176
  %71 = load volatile i32, ptr %70, align 8, !tbaa !16
  %72 = or i32 %71, 8
  store volatile i32 %72, ptr %70, align 8, !tbaa !16
  br label %73

73:                                               ; preds = %69, %25, %21, %12
  %.0 = phi i32 [ 1, %12 ], [ 1, %21 ], [ 0, %25 ], [ 1, %69 ]
  ret i32 %.0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 168}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !12, i64 124, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 240}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !8, i64 48, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !8, i64 96, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !11, i64 144, !11, i64 148, !11, i64 152, !11, i64 156, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200, !11, i64 204, !11, i64 208, !11, i64 212, !11, i64 216, !11, i64 220, !11, i64 224, !11, i64 228, !8, i64 232, !11, i64 240, !11, i64 244, !11, i64 248, !11, i64 252}
!16 = !{!6, !11, i64 176}
!17 = !{!15, !11, i64 244}
!18 = !{!6, !11, i64 144}
!19 = !{!11, !11, i64 0}
!20 = !{!12, !11, i64 4}
!21 = !{!12, !11, i64 0}
!22 = !{!12, !11, i64 8}
!23 = !{!12, !11, i64 16}
!24 = !{!12, !11, i64 28}
!25 = !{!12, !11, i64 12}
!26 = !{!12, !11, i64 20}
!27 = !{!12, !11, i64 24}
!28 = !{!12, !11, i64 36}
!29 = !{!12, !11, i64 32}
!30 = !{!15, !11, i64 248}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass