; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.RTC_HandleTypeDef = type { ptr, %struct.RTC_InitTypeDef, i32, i32 }
%struct.RTC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.RTC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.RTC_TamperTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_RTCEx_SetTamper_IT(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  br label %8

8:                                                ; preds = %2
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %9, i32 0, i32 2
  %11 = load i32, ptr %10, align 4, !tbaa !9
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %241

14:                                               ; preds = %8
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %15, i32 0, i32 2
  store i32 1, ptr %16, align 4, !tbaa !9
  br label %17

17:                                               ; preds = %14
  br label %18

18:                                               ; preds = %17
  br label %19

19:                                               ; preds = %18
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %20, i32 0, i32 3
  store volatile i32 2, ptr %21, align 8, !tbaa !13
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !14
  %25 = getelementptr inbounds %struct.RTC_TypeDef, ptr %24, i32 0, i32 16
  %26 = load volatile i32, ptr %25, align 4, !tbaa !15
  store i32 %26, ptr %6, align 4, !tbaa !17
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 4, !tbaa !18
  %30 = load i32, ptr %6, align 4, !tbaa !17
  %31 = or i32 %30, %29
  store i32 %31, ptr %6, align 4, !tbaa !17
  %32 = load ptr, ptr %5, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %32, i32 0, i32 2
  %34 = load i32, ptr %33, align 4, !tbaa !20
  %35 = icmp eq i32 %34, 8
  br i1 %35, label %41, label %36

36:                                               ; preds = %19
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %37, i32 0, i32 2
  %39 = load i32, ptr %38, align 4, !tbaa !20
  %40 = icmp eq i32 %39, 2
  br i1 %40, label %41, label %48

41:                                               ; preds = %36, %19
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %42, i32 0, i32 0
  %44 = load i32, ptr %43, align 4, !tbaa !18
  %45 = shl i32 %44, 1
  %46 = load i32, ptr %6, align 4, !tbaa !17
  %47 = or i32 %46, %45
  store i32 %47, ptr %6, align 4, !tbaa !17
  br label %56

48:                                               ; preds = %36
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %49, i32 0, i32 0
  %51 = load i32, ptr %50, align 4, !tbaa !18
  %52 = shl i32 %51, 1
  %53 = xor i32 %52, -1
  %54 = load i32, ptr %6, align 4, !tbaa !17
  %55 = and i32 %54, %53
  store i32 %55, ptr %6, align 4, !tbaa !17
  br label %56

56:                                               ; preds = %48, %41
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %57, i32 0, i32 3
  %59 = load i32, ptr %58, align 4, !tbaa !21
  %60 = icmp ne i32 %59, 0
  br i1 %60, label %61, label %92

61:                                               ; preds = %56
  %62 = load ptr, ptr %5, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %62, i32 0, i32 0
  %64 = load i32, ptr %63, align 4, !tbaa !18
  %65 = zext i32 %64 to i64
  %66 = and i64 %65, 1
  %67 = icmp ne i64 %66, 0
  br i1 %67, label %68, label %71

68:                                               ; preds = %61
  %69 = load i32, ptr %6, align 4, !tbaa !17
  %70 = or i32 %69, 131072
  store i32 %70, ptr %6, align 4, !tbaa !17
  br label %71

71:                                               ; preds = %68, %61
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %72, i32 0, i32 0
  %74 = load i32, ptr %73, align 4, !tbaa !18
  %75 = zext i32 %74 to i64
  %76 = and i64 %75, 8
  %77 = icmp ne i64 %76, 0
  br i1 %77, label %78, label %81

78:                                               ; preds = %71
  %79 = load i32, ptr %6, align 4, !tbaa !17
  %80 = or i32 %79, 1048576
  store i32 %80, ptr %6, align 4, !tbaa !17
  br label %81

81:                                               ; preds = %78, %71
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %82, i32 0, i32 0
  %84 = load i32, ptr %83, align 4, !tbaa !18
  %85 = zext i32 %84 to i64
  %86 = and i64 %85, 32
  %87 = icmp ne i64 %86, 0
  br i1 %87, label %88, label %91

88:                                               ; preds = %81
  %89 = load i32, ptr %6, align 4, !tbaa !17
  %90 = or i32 %89, 8388608
  store i32 %90, ptr %6, align 4, !tbaa !17
  br label %91

91:                                               ; preds = %88, %81
  br label %123

92:                                               ; preds = %56
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %93, i32 0, i32 0
  %95 = load i32, ptr %94, align 4, !tbaa !18
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, 1
  %98 = icmp ne i64 %97, 0
  br i1 %98, label %99, label %102

99:                                               ; preds = %92
  %100 = load i32, ptr %6, align 4, !tbaa !17
  %101 = and i32 %100, -131073
  store i32 %101, ptr %6, align 4, !tbaa !17
  br label %102

102:                                              ; preds = %99, %92
  %103 = load ptr, ptr %5, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %103, i32 0, i32 0
  %105 = load i32, ptr %104, align 4, !tbaa !18
  %106 = zext i32 %105 to i64
  %107 = and i64 %106, 8
  %108 = icmp ne i64 %107, 0
  br i1 %108, label %109, label %112

109:                                              ; preds = %102
  %110 = load i32, ptr %6, align 4, !tbaa !17
  %111 = and i32 %110, -1048577
  store i32 %111, ptr %6, align 4, !tbaa !17
  br label %112

112:                                              ; preds = %109, %102
  %113 = load ptr, ptr %5, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %113, i32 0, i32 0
  %115 = load i32, ptr %114, align 4, !tbaa !18
  %116 = zext i32 %115 to i64
  %117 = and i64 %116, 32
  %118 = icmp ne i64 %117, 0
  br i1 %118, label %119, label %122

119:                                              ; preds = %112
  %120 = load i32, ptr %6, align 4, !tbaa !17
  %121 = and i32 %120, -8388609
  store i32 %121, ptr %6, align 4, !tbaa !17
  br label %122

122:                                              ; preds = %119, %112
  br label %123

123:                                              ; preds = %122, %91
  %124 = load ptr, ptr %5, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %124, i32 0, i32 4
  %126 = load i32, ptr %125, align 4, !tbaa !22
  %127 = icmp ne i32 %126, 0
  br i1 %127, label %128, label %159

128:                                              ; preds = %123
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %129, i32 0, i32 0
  %131 = load i32, ptr %130, align 4, !tbaa !18
  %132 = zext i32 %131 to i64
  %133 = and i64 %132, 1
  %134 = icmp ne i64 %133, 0
  br i1 %134, label %135, label %138

135:                                              ; preds = %128
  %136 = load i32, ptr %6, align 4, !tbaa !17
  %137 = or i32 %136, 262144
  store i32 %137, ptr %6, align 4, !tbaa !17
  br label %138

138:                                              ; preds = %135, %128
  %139 = load ptr, ptr %5, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %139, i32 0, i32 0
  %141 = load i32, ptr %140, align 4, !tbaa !18
  %142 = zext i32 %141 to i64
  %143 = and i64 %142, 8
  %144 = icmp ne i64 %143, 0
  br i1 %144, label %145, label %148

145:                                              ; preds = %138
  %146 = load i32, ptr %6, align 4, !tbaa !17
  %147 = or i32 %146, 2097152
  store i32 %147, ptr %6, align 4, !tbaa !17
  br label %148

148:                                              ; preds = %145, %138
  %149 = load ptr, ptr %5, align 8, !tbaa !5
  %150 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %149, i32 0, i32 0
  %151 = load i32, ptr %150, align 4, !tbaa !18
  %152 = zext i32 %151 to i64
  %153 = and i64 %152, 32
  %154 = icmp ne i64 %153, 0
  br i1 %154, label %155, label %158

155:                                              ; preds = %148
  %156 = load i32, ptr %6, align 4, !tbaa !17
  %157 = or i32 %156, 16777216
  store i32 %157, ptr %6, align 4, !tbaa !17
  br label %158

158:                                              ; preds = %155, %148
  br label %190

159:                                              ; preds = %123
  %160 = load ptr, ptr %5, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %160, i32 0, i32 0
  %162 = load i32, ptr %161, align 4, !tbaa !18
  %163 = zext i32 %162 to i64
  %164 = and i64 %163, 1
  %165 = icmp ne i64 %164, 0
  br i1 %165, label %166, label %169

166:                                              ; preds = %159
  %167 = load i32, ptr %6, align 4, !tbaa !17
  %168 = and i32 %167, -262145
  store i32 %168, ptr %6, align 4, !tbaa !17
  br label %169

169:                                              ; preds = %166, %159
  %170 = load ptr, ptr %5, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %170, i32 0, i32 0
  %172 = load i32, ptr %171, align 4, !tbaa !18
  %173 = zext i32 %172 to i64
  %174 = and i64 %173, 8
  %175 = icmp ne i64 %174, 0
  br i1 %175, label %176, label %179

176:                                              ; preds = %169
  %177 = load i32, ptr %6, align 4, !tbaa !17
  %178 = and i32 %177, -2097153
  store i32 %178, ptr %6, align 4, !tbaa !17
  br label %179

179:                                              ; preds = %176, %169
  %180 = load ptr, ptr %5, align 8, !tbaa !5
  %181 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %180, i32 0, i32 0
  %182 = load i32, ptr %181, align 4, !tbaa !18
  %183 = zext i32 %182 to i64
  %184 = and i64 %183, 32
  %185 = icmp ne i64 %184, 0
  br i1 %185, label %186, label %189

186:                                              ; preds = %179
  %187 = load i32, ptr %6, align 4, !tbaa !17
  %188 = and i32 %187, -16777217
  store i32 %188, ptr %6, align 4, !tbaa !17
  br label %189

189:                                              ; preds = %186, %179
  br label %190

190:                                              ; preds = %189, %158
  %191 = load i32, ptr %6, align 4, !tbaa !17
  %192 = zext i32 %191 to i64
  %193 = and i64 %192, -65409
  %194 = trunc i64 %193 to i32
  store i32 %194, ptr %6, align 4, !tbaa !17
  %195 = load ptr, ptr %5, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %195, i32 0, i32 5
  %197 = load i32, ptr %196, align 4, !tbaa !23
  %198 = load ptr, ptr %5, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %198, i32 0, i32 6
  %200 = load i32, ptr %199, align 4, !tbaa !24
  %201 = or i32 %197, %200
  %202 = load ptr, ptr %5, align 8, !tbaa !5
  %203 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %202, i32 0, i32 7
  %204 = load i32, ptr %203, align 4, !tbaa !25
  %205 = or i32 %201, %204
  %206 = load ptr, ptr %5, align 8, !tbaa !5
  %207 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %206, i32 0, i32 8
  %208 = load i32, ptr %207, align 4, !tbaa !26
  %209 = or i32 %205, %208
  %210 = load ptr, ptr %5, align 8, !tbaa !5
  %211 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %210, i32 0, i32 9
  %212 = load i32, ptr %211, align 4, !tbaa !27
  %213 = or i32 %209, %212
  %214 = load i32, ptr %6, align 4, !tbaa !17
  %215 = or i32 %214, %213
  store i32 %215, ptr %6, align 4, !tbaa !17
  %216 = load ptr, ptr %5, align 8, !tbaa !5
  %217 = getelementptr inbounds %struct.RTC_TamperTypeDef, ptr %216, i32 0, i32 1
  %218 = load i32, ptr %217, align 4, !tbaa !28
  %219 = load i32, ptr %6, align 4, !tbaa !17
  %220 = or i32 %219, %218
  store i32 %220, ptr %6, align 4, !tbaa !17
  %221 = load i32, ptr %6, align 4, !tbaa !17
  %222 = load ptr, ptr %4, align 8, !tbaa !5
  %223 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %222, i32 0, i32 0
  %224 = load ptr, ptr %223, align 8, !tbaa !14
  %225 = getelementptr inbounds %struct.RTC_TypeDef, ptr %224, i32 0, i32 16
  store volatile i32 %221, ptr %225, align 4, !tbaa !15
  %226 = load volatile i32, ptr inttoptr (i64 1476395136 to ptr), align 4, !tbaa !29
  %227 = zext i32 %226 to i64
  %228 = or i64 %227, 262144
  %229 = trunc i64 %228 to i32
  store volatile i32 %229, ptr inttoptr (i64 1476395136 to ptr), align 4, !tbaa !29
  %230 = load volatile i32, ptr inttoptr (i64 1476395008 to ptr), align 4, !tbaa !31
  %231 = zext i32 %230 to i64
  %232 = or i64 %231, 262144
  %233 = trunc i64 %232 to i32
  store volatile i32 %233, ptr inttoptr (i64 1476395008 to ptr), align 4, !tbaa !31
  %234 = load ptr, ptr %4, align 8, !tbaa !5
  %235 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %234, i32 0, i32 3
  store volatile i32 1, ptr %235, align 8, !tbaa !13
  br label %236

236:                                              ; preds = %190
  %237 = load ptr, ptr %4, align 8, !tbaa !5
  %238 = getelementptr inbounds %struct.RTC_HandleTypeDef, ptr %237, i32 0, i32 2
  store i32 0, ptr %238, align 4, !tbaa !9
  br label %239

239:                                              ; preds = %236
  br label %240

240:                                              ; preds = %239
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %241

241:                                              ; preds = %240, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %242 = load i32, ptr %3, align 4
  ret i32 %242
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 36}
!10 = !{!"", !6, i64 0, !11, i64 8, !12, i64 36, !12, i64 40}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 40}
!14 = !{!10, !6, i64 0}
!15 = !{!16, !12, i64 64}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !12, i64 112, !12, i64 116, !12, i64 120, !12, i64 124, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !12, i64 144, !12, i64 148, !12, i64 152, !12, i64 156, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200, !12, i64 204}
!17 = !{!12, !12, i64 0}
!18 = !{!19, !12, i64 0}
!19 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36}
!20 = !{!19, !12, i64 8}
!21 = !{!19, !12, i64 12}
!22 = !{!19, !12, i64 16}
!23 = !{!19, !12, i64 20}
!24 = !{!19, !12, i64 24}
!25 = !{!19, !12, i64 28}
!26 = !{!19, !12, i64 32}
!27 = !{!19, !12, i64 36}
!28 = !{!19, !12, i64 4}
!29 = !{!30, !12, i64 0}
!30 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40}
!31 = !{!32, !12, i64 0}
!32 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !7, i64 24, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !7, i64 56, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !7, i64 88, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !12, i64 144, !12, i64 148, !12, i64 152, !12, i64 156, !12, i64 160, !12, i64 164, !12, i64 168}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_RTCEx_SetTamper_IT(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 36
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %67, label %6

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 40
  store volatile i32 2, ptr %7, align 8, !tbaa !12
  %8 = load ptr, ptr %0, align 8, !tbaa !13
  %9 = getelementptr inbounds i8, ptr %8, i64 64
  %10 = load volatile i32, ptr %9, align 4, !tbaa !14
  %11 = load i32, ptr %1, align 4, !tbaa !16
  %12 = or i32 %11, %10
  %13 = getelementptr inbounds i8, ptr %1, i64 8
  %14 = load i32, ptr %13, align 4, !tbaa !18
  switch i32 %14, label %18 [
    i32 8, label %15
    i32 2, label %15
  ]

15:                                               ; preds = %6, %6
  %16 = shl i32 %11, 1
  %17 = or i32 %12, %16
  br label %22

18:                                               ; preds = %6
  %19 = shl i32 %11, 1
  %20 = xor i32 %19, -1
  %21 = and i32 %12, %20
  br label %22

22:                                               ; preds = %18, %15
  %.0 = phi i32 [ %17, %15 ], [ %21, %18 ]
  %23 = getelementptr inbounds i8, ptr %1, i64 12
  %24 = load i32, ptr %23, align 4, !tbaa !19
  %.not = icmp eq i32 %24, 0
  br i1 %.not, label %31, label %25

25:                                               ; preds = %22
  %26 = shl i32 %11, 17
  %27 = and i32 %26, 1179648
  %28 = shl i32 %11, 18
  %29 = and i32 %28, 8388608
  %30 = or disjoint i32 %27, %29
  %spec.select69 = or i32 %30, %.0
  br label %38

31:                                               ; preds = %22
  %32 = and i32 %11, 1
  %.not53 = icmp eq i32 %32, 0
  %33 = and i32 %.0, -131073
  %spec.select66 = select i1 %.not53, i32 %.0, i32 %33
  %34 = and i32 %11, 8
  %.not54 = icmp eq i32 %34, 0
  %35 = and i32 %spec.select66, -1048577
  %.4 = select i1 %.not54, i32 %spec.select66, i32 %35
  %36 = and i32 %11, 32
  %.not55 = icmp eq i32 %36, 0
  %37 = and i32 %.4, -8388609
  %spec.select70 = select i1 %.not55, i32 %.4, i32 %37
  br label %38

38:                                               ; preds = %31, %25
  %.5 = phi i32 [ %spec.select69, %25 ], [ %spec.select70, %31 ]
  %39 = getelementptr inbounds i8, ptr %1, i64 16
  %40 = load i32, ptr %39, align 4, !tbaa !20
  %.not59 = icmp eq i32 %40, 0
  br i1 %.not59, label %47, label %41

41:                                               ; preds = %38
  %42 = shl i32 %11, 18
  %43 = and i32 %42, 2359296
  %44 = shl i32 %11, 19
  %45 = and i32 %44, 16777216
  %46 = or disjoint i32 %43, %45
  %spec.select71 = or i32 %46, %.5
  br label %54

47:                                               ; preds = %38
  %48 = and i32 %11, 1
  %.not60 = icmp eq i32 %48, 0
  %49 = and i32 %.5, -262145
  %spec.select68 = select i1 %.not60, i32 %.5, i32 %49
  %50 = and i32 %11, 8
  %.not61 = icmp eq i32 %50, 0
  %51 = and i32 %spec.select68, -2097153
  %.9 = select i1 %.not61, i32 %spec.select68, i32 %51
  %52 = and i32 %11, 32
  %.not62 = icmp eq i32 %52, 0
  %53 = and i32 %.9, -16777217
  %spec.select72 = select i1 %.not62, i32 %.9, i32 %53
  br label %54

54:                                               ; preds = %47, %41
  %.10 = phi i32 [ %spec.select71, %41 ], [ %spec.select72, %47 ]
  %55 = and i32 %.10, -65409
  %56 = getelementptr inbounds i8, ptr %1, i64 20
  %57 = load <4 x i32>, ptr %56, align 4, !tbaa !21
  %58 = getelementptr inbounds i8, ptr %1, i64 36
  %59 = load i32, ptr %58, align 4, !tbaa !22
  %60 = getelementptr inbounds i8, ptr %1, i64 4
  %61 = load i32, ptr %60, align 4, !tbaa !23
  %62 = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %57)
  %op.rdx = or i32 %62, %59
  %op.rdx73 = or i32 %61, %55
  %op.rdx74 = or i32 %op.rdx, %op.rdx73
  store volatile i32 %op.rdx74, ptr %9, align 4, !tbaa !14
  %63 = load volatile i32, ptr inttoptr (i64 1476395136 to ptr), align 128, !tbaa !24
  %64 = or i32 %63, 262144
  store volatile i32 %64, ptr inttoptr (i64 1476395136 to ptr), align 128, !tbaa !24
  %65 = load volatile i32, ptr inttoptr (i64 1476395008 to ptr), align 134217728, !tbaa !26
  %66 = or i32 %65, 262144
  store volatile i32 %66, ptr inttoptr (i64 1476395008 to ptr), align 134217728, !tbaa !26
  store volatile i32 1, ptr %7, align 8, !tbaa !12
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %67

67:                                               ; preds = %2, %54
  %.051 = phi i32 [ 0, %54 ], [ 2, %2 ]
  ret i32 %.051
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>) #1

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 36}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 40}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 64}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !11, i64 112, !11, i64 116, !11, i64 120, !11, i64 124, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !11, i64 144, !11, i64 148, !11, i64 152, !11, i64 156, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200, !11, i64 204}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!18 = !{!17, !11, i64 8}
!19 = !{!17, !11, i64 12}
!20 = !{!17, !11, i64 16}
!21 = !{!11, !11, i64 0}
!22 = !{!17, !11, i64 36}
!23 = !{!17, !11, i64 4}
!24 = !{!25, !11, i64 0}
!25 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40}
!26 = !{!27, !11, i64 0}
!27 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !8, i64 24, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !8, i64 56, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !8, i64 88, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !11, i64 144, !11, i64 148, !11, i64 152, !11, i64 156, !11, i64 160, !11, i64 164, !11, i64 168}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass