; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src (DSwitch)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Config = type { i32, %class.DSNetworkConfig, %class.DSwitchConfig, %class.MSNetworkConfig, %class.MSwitchConfig, %class.ASNetworkConfig, %class.ASwitchConfig, %class.LookUpTableConfig, %class.SDMemoryConfig }
%class.DSNetworkConfig = type { i32 }
%class.DSwitchConfig = type { i32, i32, i32, i32 }
%class.MSNetworkConfig = type { i32, i32, i32, i32 }
%class.MSwitchConfig = type { i32, i32, i32, i32, i32, i32 }
%class.ASNetworkConfig = type { i32, i32 }
%class.ASwitchConfig = type { i32, i32, i32, i32, i32, i32 }
%class.LookUpTableConfig = type { i32, i32 }
%class.SDMemoryConfig = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%class.DSwitch = type { %class.Unit, i32, i32, i32, i8, i32, i32, i32, %"class.std::vector", i32, ptr, ptr, ptr, i32, i64, %class.DSwitchStats }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.DSwitchStats = type <{ %class.Stats, i32, i32, i32, i32, i32, [4 x i8] }>
%class.Stats = type { ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6Configj(ptr noundef nonnull align 8 dereferenceable(184), i32 noundef, ptr noundef, i32 noundef, i32 noundef, ptr noundef byval(%class.Config) align 8, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6ConfigjP10ConnectionS8_S8_(ptr noundef nonnull align 8 dereferenceable(184) %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4, ptr noundef byval(%class.Config) align 8 %5, i32 noundef %6, ptr noundef %7, ptr noundef %8, ptr noundef %9) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca %"class.std::__cxx11::basic_string", align 8
  %21 = alloca %class.Config, align 8
  %22 = alloca ptr, align 8
  %23 = alloca i32, align 4
  store ptr %0, ptr %11, align 8, !tbaa !5
  store i32 %1, ptr %12, align 4, !tbaa !9
  store ptr %2, ptr %13, align 8, !tbaa !5
  store i32 %3, ptr %14, align 4, !tbaa !9
  store i32 %4, ptr %15, align 4, !tbaa !9
  store i32 %6, ptr %16, align 4, !tbaa !9
  store ptr %7, ptr %17, align 8, !tbaa !5
  store ptr %8, ptr %18, align 8, !tbaa !5
  store ptr %9, ptr %19, align 8, !tbaa !5
  %24 = load ptr, ptr %11, align 8
  %25 = load i32, ptr %12, align 4, !tbaa !9
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_(ptr noundef nonnull align 8 dereferenceable(32) %20, ptr noundef nonnull align 8 dereferenceable(32) %2)
  %26 = load i32, ptr %14, align 4, !tbaa !9
  %27 = load i32, ptr %15, align 4, !tbaa !9
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %21, ptr align 8 %5, i64 160, i1 false), !tbaa.struct !11
  %28 = load i32, ptr %16, align 4, !tbaa !9
  invoke void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6Configj(ptr noundef nonnull align 8 dereferenceable(184) %24, i32 noundef %25, ptr noundef %20, i32 noundef %26, i32 noundef %27, ptr noundef byval(%class.Config) align 8 %21, i32 noundef %28)
          to label %29 unwind label %38

29:                                               ; preds = %10
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %20) #4
  %30 = getelementptr inbounds %class.DSwitch, ptr %24, i32 0, i32 9
  store i32 0, ptr %30, align 8, !tbaa !20
  %31 = getelementptr inbounds %class.DSwitch, ptr %24, i32 0, i32 4
  store i8 0, ptr %31, align 4, !tbaa !33
  %32 = load ptr, ptr %17, align 8, !tbaa !5
  invoke void @_ZN7DSwitch17setLeftConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %24, ptr noundef %32)
          to label %33 unwind label %42

33:                                               ; preds = %29
  %34 = load ptr, ptr %18, align 8, !tbaa !5
  invoke void @_ZN7DSwitch18setRightConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %24, ptr noundef %34)
          to label %35 unwind label %42

35:                                               ; preds = %33
  %36 = load ptr, ptr %19, align 8, !tbaa !5
  invoke void @_ZN7DSwitch18setInputConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %24, ptr noundef %36)
          to label %37 unwind label %42

37:                                               ; preds = %35
  ret void

38:                                               ; preds = %10
  %39 = landingpad { ptr, i32 }
          cleanup
  %40 = extractvalue { ptr, i32 } %39, 0
  store ptr %40, ptr %22, align 8
  %41 = extractvalue { ptr, i32 } %39, 1
  store i32 %41, ptr %23, align 4
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %20) #4
  br label %46

42:                                               ; preds = %35, %33, %29
  %43 = landingpad { ptr, i32 }
          cleanup
  %44 = extractvalue { ptr, i32 } %43, 0
  store ptr %44, ptr %22, align 8
  %45 = extractvalue { ptr, i32 } %43, 1
  store i32 %45, ptr %23, align 4
  call void @_ZN7DSwitchD2Ev(ptr noundef nonnull align 8 dereferenceable(184) %24) #4
  br label %46

46:                                               ; preds = %42, %38
  %47 = load ptr, ptr %22, align 8
  %48 = load i32, ptr %23, align 4
  %49 = insertvalue { ptr, i32 } poison, ptr %47, 0
  %50 = insertvalue { ptr, i32 } %49, i32 %48, 1
  resume { ptr, i32 } %50
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch17setLeftConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch18setRightConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch18setInputConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitchD2Ev(ptr noundef nonnull align 8 dereferenceable(184)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{i64 0, i64 4, !9, i64 4, i64 4, !9, i64 8, i64 4, !9, i64 12, i64 4, !9, i64 16, i64 4, !9, i64 20, i64 4, !9, i64 24, i64 4, !12, i64 28, i64 4, !9, i64 32, i64 4, !9, i64 36, i64 4, !9, i64 40, i64 4, !9, i64 44, i64 4, !9, i64 48, i64 4, !9, i64 52, i64 4, !9, i64 56, i64 4, !9, i64 60, i64 4, !9, i64 64, i64 4, !14, i64 68, i64 4, !9, i64 72, i64 4, !9, i64 76, i64 4, !9, i64 80, i64 4, !9, i64 84, i64 4, !9, i64 88, i64 4, !9, i64 92, i64 4, !9, i64 96, i64 4, !9, i64 100, i64 4, !9, i64 104, i64 4, !16, i64 108, i64 4, !9, i64 112, i64 4, !9, i64 116, i64 4, !9, i64 120, i64 4, !9, i64 124, i64 4, !9, i64 128, i64 4, !9, i64 132, i64 4, !18, i64 136, i64 4, !9, i64 140, i64 4, !9, i64 144, i64 4, !9, i64 148, i64 4, !9, i64 152, i64 4, !9, i64 156, i64 4, !9}
!12 = !{!13, !13, i64 0}
!13 = !{!"_ZTS19MultiplierNetwork_t", !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS15ReduceNetwork_t", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"_ZTS18MemoryController_t", !7, i64 0}
!18 = !{!19, !19, i64 0}
!19 = !{!"_ZTS17MemoryHierarchy_t", !7, i64 0}
!20 = !{!21, !10, i64 104}
!21 = !{!"_ZTS7DSwitch", !22, i64 0, !10, i64 48, !10, i64 52, !10, i64 56, !26, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !27, i64 80, !10, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !10, i64 136, !25, i64 144, !31, i64 152}
!22 = !{!"_ZTS4Unit", !10, i64 8, !23, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"long", !7, i64 0}
!26 = !{!"bool", !7, i64 0}
!27 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!31 = !{!"_ZTS12DSwitchStats", !32, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!32 = !{!"_ZTS5Stats"}
!33 = !{!21, !26, i64 60}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Config = type { i32, %class.DSNetworkConfig, %class.DSwitchConfig, %class.MSNetworkConfig, %class.MSwitchConfig, %class.ASNetworkConfig, %class.ASwitchConfig, %class.LookUpTableConfig, %class.SDMemoryConfig }
%class.DSNetworkConfig = type { i32 }
%class.DSwitchConfig = type { i32, i32, i32, i32 }
%class.MSNetworkConfig = type { i32, i32, i32, i32 }
%class.MSwitchConfig = type { i32, i32, i32, i32, i32, i32 }
%class.ASNetworkConfig = type { i32, i32 }
%class.ASwitchConfig = type { i32, i32, i32, i32, i32, i32 }
%class.LookUpTableConfig = type { i32, i32 }
%class.SDMemoryConfig = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6Configj(ptr noundef nonnull align 8 dereferenceable(184), i32 noundef, ptr noundef, i32 noundef, i32 noundef, ptr noundef byval(%class.Config) align 8, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6ConfigjP10ConnectionS8_S8_(ptr noundef nonnull align 8 dereferenceable(184) %0, i32 noundef %1, ptr noundef nonnull %2, i32 noundef %3, i32 noundef %4, ptr nocapture noundef readonly byval(%class.Config) align 8 %5, i32 noundef %6, ptr noundef %7, ptr noundef %8, ptr noundef %9) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %11 = alloca %"class.std::__cxx11::basic_string", align 8
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_(ptr noundef nonnull align 8 dereferenceable(32) %11, ptr noundef nonnull align 8 dereferenceable(32) %2)
  invoke void @_ZN7DSwitchC2EjNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEjj6Configj(ptr noundef nonnull align 8 dereferenceable(184) %0, i32 noundef %1, ptr noundef nonnull %11, i32 noundef %3, i32 noundef %4, ptr noundef nonnull byval(%class.Config) align 8 %5, i32 noundef %6)
          to label %12 unwind label %15

12:                                               ; preds = %10
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %11) #2
  %13 = getelementptr inbounds i8, ptr %0, i64 104
  store i32 0, ptr %13, align 8, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %0, i64 60
  store i8 0, ptr %14, align 4, !tbaa !22
  call void @_ZN7DSwitch17setLeftConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef %7)
  call void @_ZN7DSwitch18setRightConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef %8)
  call void @_ZN7DSwitch18setInputConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184) %0, ptr noundef %9)
  ret void

15:                                               ; preds = %10
  %16 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %11) #2
  resume { ptr, i32 } %16
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch17setLeftConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch18setRightConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7DSwitch18setInputConnectionEP10Connection(ptr noundef nonnull align 8 dereferenceable(184), ptr noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 104}
!6 = !{!"_ZTS7DSwitch", !7, i64 0, !8, i64 48, !8, i64 52, !8, i64 56, !15, i64 60, !8, i64 64, !8, i64 68, !8, i64 72, !16, i64 80, !8, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !8, i64 136, !14, i64 144, !20, i64 152}
!7 = !{!"_ZTS4Unit", !8, i64 8, !11, i64 16}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !14, i64 8, !9, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!13 = !{!"any pointer", !9, i64 0}
!14 = !{!"long", !9, i64 0}
!15 = !{!"bool", !9, i64 0}
!16 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!20 = !{!"_ZTS12DSwitchStats", !21, i64 0, !8, i64 8, !8, i64 12, !8, i64 16, !8, i64 20, !8, i64 24}
!21 = !{!"_ZTS5Stats"}
!22 = !{!6, !15, i64 60}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass