; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x (s8)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_nn_mat_mul_core_1x_s8(i32 noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !9
  store ptr %4, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  store i32 0, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  store i32 0, ptr %13, align 4, !tbaa !5
  br label %14

14:                                               ; preds = %43, %5
  %15 = load i32, ptr %13, align 4, !tbaa !5
  %16 = load i32, ptr %6, align 4, !tbaa !5
  %17 = icmp slt i32 %15, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  br label %46

19:                                               ; preds = %14
  %20 = load ptr, ptr %8, align 8, !tbaa !9
  %21 = load i32, ptr %13, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds i8, ptr %20, i64 %22
  %24 = load i8, ptr %23, align 1, !tbaa !11
  %25 = sext i8 %24 to i32
  %26 = load i32, ptr %12, align 4, !tbaa !5
  %27 = add nsw i32 %26, %25
  store i32 %27, ptr %12, align 4, !tbaa !5
  %28 = load ptr, ptr %7, align 8, !tbaa !9
  %29 = load i32, ptr %13, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds i8, ptr %28, i64 %30
  %32 = load i8, ptr %31, align 1, !tbaa !11
  %33 = sext i8 %32 to i32
  %34 = load ptr, ptr %8, align 8, !tbaa !9
  %35 = load i32, ptr %13, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds i8, ptr %34, i64 %36
  %38 = load i8, ptr %37, align 1, !tbaa !11
  %39 = sext i8 %38 to i32
  %40 = mul nsw i32 %33, %39
  %41 = load i32, ptr %11, align 4, !tbaa !5
  %42 = add nsw i32 %41, %40
  store i32 %42, ptr %11, align 4, !tbaa !5
  br label %43

43:                                               ; preds = %19
  %44 = load i32, ptr %13, align 4, !tbaa !5
  %45 = add nsw i32 %44, 1
  store i32 %45, ptr %13, align 4, !tbaa !5
  br label %14, !llvm.loop !12

46:                                               ; preds = %18
  %47 = load i32, ptr %12, align 4, !tbaa !5
  %48 = load ptr, ptr %9, align 8, !tbaa !9
  store i32 %47, ptr %48, align 4, !tbaa !5
  %49 = load i32, ptr %11, align 4, !tbaa !5
  %50 = load ptr, ptr %10, align 8, !tbaa !9
  store i32 %49, ptr %50, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable
define dso_local noundef i32 @arm_nn_mat_mul_core_1x_s8(i32 noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, ptr nocapture noundef writeonly %3, ptr nocapture noundef writeonly %4) local_unnamed_addr #0 {
  %6 = icmp sgt i32 %0, 0
  br i1 %6, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %5
  %wide.trip.count = zext nneg i32 %0 to i64
  %min.iters.check = icmp ult i32 %0, 8
  br i1 %min.iters.check, label %.lr.ph.preheader32, label %vector.ph

.lr.ph.preheader32:                               ; preds = %middle.block, %.lr.ph.preheader
  %indvars.iv.ph = phi i64 [ 0, %.lr.ph.preheader ], [ %n.vec, %middle.block ]
  %.01417.ph = phi i32 [ 0, %.lr.ph.preheader ], [ %22, %middle.block ]
  %.01516.ph = phi i32 [ 0, %.lr.ph.preheader ], [ %23, %middle.block ]
  br label %.lr.ph

vector.ph:                                        ; preds = %.lr.ph.preheader
  %n.vec = and i64 %wide.trip.count, 2147483640
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %11, %vector.body ]
  %vec.phi24 = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
  %vec.phi25 = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %19, %vector.body ]
  %vec.phi26 = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %20, %vector.body ]
  %7 = getelementptr inbounds i8, ptr %2, i64 %index
  %8 = getelementptr inbounds i8, ptr %7, i64 4
  %wide.load = load <4 x i8>, ptr %7, align 1, !tbaa !5
  %wide.load27 = load <4 x i8>, ptr %8, align 1, !tbaa !5
  %9 = sext <4 x i8> %wide.load to <4 x i32>
  %10 = sext <4 x i8> %wide.load27 to <4 x i32>
  %11 = add <4 x i32> %vec.phi, %9
  %12 = add <4 x i32> %vec.phi24, %10
  %13 = getelementptr inbounds i8, ptr %1, i64 %index
  %14 = getelementptr inbounds i8, ptr %13, i64 4
  %wide.load28 = load <4 x i8>, ptr %13, align 1, !tbaa !5
  %wide.load29 = load <4 x i8>, ptr %14, align 1, !tbaa !5
  %15 = sext <4 x i8> %wide.load28 to <4 x i32>
  %16 = sext <4 x i8> %wide.load29 to <4 x i32>
  %17 = mul nsw <4 x i32> %15, %9
  %18 = mul nsw <4 x i32> %16, %10
  %19 = add <4 x i32> %17, %vec.phi25
  %20 = add <4 x i32> %18, %vec.phi26
  %index.next = add nuw i64 %index, 8
  %21 = icmp eq i64 %index.next, %n.vec
  br i1 %21, label %middle.block, label %vector.body, !llvm.loop !8

middle.block:                                     ; preds = %vector.body
  %bin.rdx = add <4 x i32> %12, %11
  %22 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
  %bin.rdx30 = add <4 x i32> %20, %19
  %23 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx30)
  %cmp.n = icmp eq i64 %n.vec, %wide.trip.count
  br i1 %cmp.n, label %._crit_edge, label %.lr.ph.preheader32

._crit_edge:                                      ; preds = %.lr.ph, %middle.block, %5
  %.015.lcssa = phi i32 [ 0, %5 ], [ %23, %middle.block ], [ %32, %.lr.ph ]
  %.014.lcssa = phi i32 [ 0, %5 ], [ %22, %middle.block ], [ %27, %.lr.ph ]
  store i32 %.014.lcssa, ptr %3, align 4, !tbaa !12
  store i32 %.015.lcssa, ptr %4, align 4, !tbaa !12
  ret i32 0

.lr.ph:                                           ; preds = %.lr.ph.preheader32, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %indvars.iv.ph, %.lr.ph.preheader32 ]
  %.01417 = phi i32 [ %27, %.lr.ph ], [ %.01417.ph, %.lr.ph.preheader32 ]
  %.01516 = phi i32 [ %32, %.lr.ph ], [ %.01516.ph, %.lr.ph.preheader32 ]
  %24 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv
  %25 = load i8, ptr %24, align 1, !tbaa !5
  %26 = sext i8 %25 to i32
  %27 = add nsw i32 %.01417, %26
  %28 = getelementptr inbounds i8, ptr %1, i64 %indvars.iv
  %29 = load i8, ptr %28, align 1, !tbaa !5
  %30 = sext i8 %29 to i32
  %31 = mul nsw i32 %30, %26
  %32 = add nsw i32 %31, %.01516
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !14
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #1

attributes #0 = { nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9, !10, !11}
!9 = !{!"llvm.loop.mustprogress"}
!10 = !{!"llvm.loop.isvectorized", i32 1}
!11 = !{!"llvm.loop.unroll.runtime.disable"}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !6, i64 0}
!14 = distinct !{!14, !9, !11, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass