; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_PWM_Start_IT(ptr noundef %0, i32 noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %6 = load i32, ptr %4, align 4, !tbaa !9
  switch i32 %6, label %43 [
    i32 0, label %7
    i32 4, label %16
    i32 8, label %25
    i32 12, label %34
  ]

7:                                                ; preds = %2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !11
  %11 = getelementptr inbounds %struct.TIM_TypeDef, ptr %10, i32 0, i32 3
  %12 = load volatile i32, ptr %11, align 4, !tbaa !14
  %13 = zext i32 %12 to i64
  %14 = or i64 %13, 2
  %15 = trunc i64 %14 to i32
  store volatile i32 %15, ptr %11, align 4, !tbaa !14
  br label %44

16:                                               ; preds = %2
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 0
  %19 = load ptr, ptr %18, align 8, !tbaa !11
  %20 = getelementptr inbounds %struct.TIM_TypeDef, ptr %19, i32 0, i32 3
  %21 = load volatile i32, ptr %20, align 4, !tbaa !14
  %22 = zext i32 %21 to i64
  %23 = or i64 %22, 4
  %24 = trunc i64 %23 to i32
  store volatile i32 %24, ptr %20, align 4, !tbaa !14
  br label %44

25:                                               ; preds = %2
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %26, i32 0, i32 0
  %28 = load ptr, ptr %27, align 8, !tbaa !11
  %29 = getelementptr inbounds %struct.TIM_TypeDef, ptr %28, i32 0, i32 3
  %30 = load volatile i32, ptr %29, align 4, !tbaa !14
  %31 = zext i32 %30 to i64
  %32 = or i64 %31, 8
  %33 = trunc i64 %32 to i32
  store volatile i32 %33, ptr %29, align 4, !tbaa !14
  br label %44

34:                                               ; preds = %2
  %35 = load ptr, ptr %3, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %35, i32 0, i32 0
  %37 = load ptr, ptr %36, align 8, !tbaa !11
  %38 = getelementptr inbounds %struct.TIM_TypeDef, ptr %37, i32 0, i32 3
  %39 = load volatile i32, ptr %38, align 4, !tbaa !14
  %40 = zext i32 %39 to i64
  %41 = or i64 %40, 16
  %42 = trunc i64 %41 to i32
  store volatile i32 %42, ptr %38, align 4, !tbaa !14
  br label %44

43:                                               ; preds = %2
  br label %44

44:                                               ; preds = %43, %34, %25, %16, %7
  %45 = load ptr, ptr %3, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %45, i32 0, i32 0
  %47 = load ptr, ptr %46, align 8, !tbaa !11
  %48 = load i32, ptr %4, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %47, i32 noundef %48, i32 noundef 1)
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !11
  %52 = icmp eq ptr %51, inttoptr (i64 1073807360 to ptr)
  br i1 %52, label %73, label %53

53:                                               ; preds = %44
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !11
  %57 = icmp eq ptr %56, inttoptr (i64 1073808384 to ptr)
  br i1 %57, label %73, label %58

58:                                               ; preds = %53
  %59 = load ptr, ptr %3, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !11
  %62 = icmp eq ptr %61, inttoptr (i64 1073823744 to ptr)
  br i1 %62, label %73, label %63

63:                                               ; preds = %58
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %64, i32 0, i32 0
  %66 = load ptr, ptr %65, align 8, !tbaa !11
  %67 = icmp eq ptr %66, inttoptr (i64 1073824768 to ptr)
  br i1 %67, label %73, label %68

68:                                               ; preds = %63
  %69 = load ptr, ptr %3, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %69, i32 0, i32 0
  %71 = load ptr, ptr %70, align 8, !tbaa !11
  %72 = icmp eq ptr %71, inttoptr (i64 1073825792 to ptr)
  br label %73

73:                                               ; preds = %68, %63, %58, %53, %44
  %74 = phi i1 [ true, %63 ], [ true, %58 ], [ true, %53 ], [ true, %44 ], [ %72, %68 ]
  %75 = zext i1 %74 to i32
  %76 = icmp ne i32 %75, 0
  br i1 %76, label %77, label %86

77:                                               ; preds = %73
  %78 = load ptr, ptr %3, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %78, i32 0, i32 0
  %80 = load ptr, ptr %79, align 8, !tbaa !11
  %81 = getelementptr inbounds %struct.TIM_TypeDef, ptr %80, i32 0, i32 17
  %82 = load volatile i32, ptr %81, align 4, !tbaa !16
  %83 = zext i32 %82 to i64
  %84 = or i64 %83, 32768
  %85 = trunc i64 %84 to i32
  store volatile i32 %85, ptr %81, align 4, !tbaa !16
  br label %86

86:                                               ; preds = %77, %73
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !11
  %90 = getelementptr inbounds %struct.TIM_TypeDef, ptr %89, i32 0, i32 2
  %91 = load volatile i32, ptr %90, align 4, !tbaa !17
  %92 = zext i32 %91 to i64
  %93 = and i64 %92, 65543
  %94 = trunc i64 %93 to i32
  store i32 %94, ptr %5, align 4, !tbaa !9
  %95 = load i32, ptr %5, align 4, !tbaa !9
  %96 = zext i32 %95 to i64
  %97 = icmp eq i64 %96, 6
  br i1 %97, label %111, label %98

98:                                               ; preds = %86
  %99 = load i32, ptr %5, align 4, !tbaa !9
  %100 = zext i32 %99 to i64
  %101 = icmp eq i64 %100, 65536
  br i1 %101, label %111, label %102

102:                                              ; preds = %98
  %103 = load ptr, ptr %3, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %103, i32 0, i32 0
  %105 = load ptr, ptr %104, align 8, !tbaa !11
  %106 = getelementptr inbounds %struct.TIM_TypeDef, ptr %105, i32 0, i32 0
  %107 = load volatile i32, ptr %106, align 4, !tbaa !18
  %108 = zext i32 %107 to i64
  %109 = or i64 %108, 1
  %110 = trunc i64 %109 to i32
  store volatile i32 %110, ptr %106, align 4, !tbaa !18
  br label %111

111:                                              ; preds = %102, %98, %86
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 0
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 68}
!17 = !{!15, !10, i64 8}
!18 = !{!15, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.HAL_TIM_PWM_Start_IT = private unnamed_addr constant [4 x i32] [i32 2, i32 4, i32 8, i32 16], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @HAL_TIM_PWM_Start_IT(ptr nocapture noundef readonly %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  %4 = icmp ult i32 %3, 4
  br i1 %4, label %switch.lookup, label %._crit_edge

switch.lookup:                                    ; preds = %2
  %5 = zext nneg i32 %3 to i64
  %switch.gep = getelementptr inbounds [4 x i32], ptr @switch.table.HAL_TIM_PWM_Start_IT, i64 0, i64 %5
  %switch.load = load i32, ptr %switch.gep, align 4
  %6 = getelementptr inbounds i8, ptr %.pre, i64 12
  %7 = load volatile i32, ptr %6, align 4, !tbaa !12
  %8 = or i32 %7, %switch.load
  store volatile i32 %8, ptr %6, align 4, !tbaa !12
  br label %._crit_edge

._crit_edge:                                      ; preds = %2, %switch.lookup
  tail call void @TIM_CCxChannelCmd(ptr noundef %.pre, i32 noundef %1, i32 noundef 1)
  %9 = load ptr, ptr %0, align 8, !tbaa !5
  %magicptr19 = ptrtoint ptr %9 to i64
  switch i64 %magicptr19, label %13 [
    i64 1073807360, label %.critedge
    i64 1073808384, label %.critedge
    i64 1073823744, label %.critedge
    i64 1073824768, label %.critedge
    i64 1073825792, label %.critedge
  ]

.critedge:                                        ; preds = %._crit_edge, %._crit_edge, %._crit_edge, %._crit_edge, %._crit_edge
  %10 = getelementptr inbounds i8, ptr %9, i64 68
  %11 = load volatile i32, ptr %10, align 4, !tbaa !14
  %12 = or i32 %11, 32768
  store volatile i32 %12, ptr %10, align 4, !tbaa !14
  br label %13

13:                                               ; preds = %._crit_edge, %.critedge
  %14 = getelementptr inbounds i8, ptr %9, i64 8
  %15 = load volatile i32, ptr %14, align 4, !tbaa !15
  %16 = and i32 %15, 65543
  switch i32 %16, label %17 [
    i32 65536, label %20
    i32 6, label %20
  ]

17:                                               ; preds = %13
  %18 = load volatile i32, ptr %9, align 4, !tbaa !16
  %19 = or i32 %18, 1
  store volatile i32 %19, ptr %9, align 4, !tbaa !16
  br label %20

20:                                               ; preds = %13, %13, %17
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!14 = !{!13, !11, i64 68}
!15 = !{!13, !11, i64 8}
!16 = !{!13, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass