; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IRQHandler)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.CRS_TypeDef = type { i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @HAL_RCCEx_CRS_IRQHandler() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  store i32 0, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  %4 = load volatile i32, ptr getelementptr inbounds (%struct.CRS_TypeDef, ptr inttoptr (i64 1073775616 to ptr), i32 0, i32 2), align 4, !tbaa !9
  store i32 %4, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  %5 = load volatile i32, ptr inttoptr (i64 1073775616 to ptr), align 4, !tbaa !11
  store i32 %5, ptr %3, align 4, !tbaa !5
  %6 = load i32, ptr %2, align 4, !tbaa !5
  %7 = zext i32 %6 to i64
  %8 = and i64 %7, 1
  %9 = icmp ne i64 %8, 0
  br i1 %9, label %10, label %16

10:                                               ; preds = %0
  %11 = load i32, ptr %3, align 4, !tbaa !5
  %12 = zext i32 %11 to i64
  %13 = and i64 %12, 1
  %14 = icmp ne i64 %13, 0
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store volatile i32 1, ptr getelementptr inbounds (%struct.CRS_TypeDef, ptr inttoptr (i64 1073775616 to ptr), i32 0, i32 3), align 4, !tbaa !12
  call void @HAL_RCCEx_CRS_SyncOkCallback()
  br label %77

16:                                               ; preds = %10, %0
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = zext i32 %17 to i64
  %19 = and i64 %18, 2
  %20 = icmp ne i64 %19, 0
  br i1 %20, label %21, label %27

21:                                               ; preds = %16
  %22 = load i32, ptr %3, align 4, !tbaa !5
  %23 = zext i32 %22 to i64
  %24 = and i64 %23, 2
  %25 = icmp ne i64 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store volatile i32 2, ptr getelementptr inbounds (%struct.CRS_TypeDef, ptr inttoptr (i64 1073775616 to ptr), i32 0, i32 3), align 4, !tbaa !12
  call void @HAL_RCCEx_CRS_SyncWarnCallback()
  br label %76

27:                                               ; preds = %21, %16
  %28 = load i32, ptr %2, align 4, !tbaa !5
  %29 = zext i32 %28 to i64
  %30 = and i64 %29, 8
  %31 = icmp ne i64 %30, 0
  br i1 %31, label %32, label %38

32:                                               ; preds = %27
  %33 = load i32, ptr %3, align 4, !tbaa !5
  %34 = zext i32 %33 to i64
  %35 = and i64 %34, 8
  %36 = icmp ne i64 %35, 0
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store volatile i32 8, ptr getelementptr inbounds (%struct.CRS_TypeDef, ptr inttoptr (i64 1073775616 to ptr), i32 0, i32 3), align 4, !tbaa !12
  call void @HAL_RCCEx_CRS_ExpectedSyncCallback()
  br label %75

38:                                               ; preds = %32, %27
  %39 = load i32, ptr %2, align 4, !tbaa !5
  %40 = zext i32 %39 to i64
  %41 = and i64 %40, 4
  %42 = icmp ne i64 %41, 0
  br i1 %42, label %43, label %74

43:                                               ; preds = %38
  %44 = load i32, ptr %3, align 4, !tbaa !5
  %45 = zext i32 %44 to i64
  %46 = and i64 %45, 4
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %48, label %74

48:                                               ; preds = %43
  %49 = load i32, ptr %2, align 4, !tbaa !5
  %50 = zext i32 %49 to i64
  %51 = and i64 %50, 256
  %52 = icmp ne i64 %51, 0
  br i1 %52, label %53, label %56

53:                                               ; preds = %48
  %54 = load i32, ptr %1, align 4, !tbaa !5
  %55 = or i32 %54, 8
  store i32 %55, ptr %1, align 4, !tbaa !5
  br label %56

56:                                               ; preds = %53, %48
  %57 = load i32, ptr %2, align 4, !tbaa !5
  %58 = zext i32 %57 to i64
  %59 = and i64 %58, 512
  %60 = icmp ne i64 %59, 0
  br i1 %60, label %61, label %64

61:                                               ; preds = %56
  %62 = load i32, ptr %1, align 4, !tbaa !5
  %63 = or i32 %62, 16
  store i32 %63, ptr %1, align 4, !tbaa !5
  br label %64

64:                                               ; preds = %61, %56
  %65 = load i32, ptr %2, align 4, !tbaa !5
  %66 = zext i32 %65 to i64
  %67 = and i64 %66, 1024
  %68 = icmp ne i64 %67, 0
  br i1 %68, label %69, label %72

69:                                               ; preds = %64
  %70 = load i32, ptr %1, align 4, !tbaa !5
  %71 = or i32 %70, 32
  store i32 %71, ptr %1, align 4, !tbaa !5
  br label %72

72:                                               ; preds = %69, %64
  store volatile i32 4, ptr getelementptr inbounds (%struct.CRS_TypeDef, ptr inttoptr (i64 1073775616 to ptr), i32 0, i32 3), align 4, !tbaa !12
  %73 = load i32, ptr %1, align 4, !tbaa !5
  call void @HAL_RCCEx_CRS_ErrorCallback(i32 noundef %73)
  br label %74

74:                                               ; preds = %72, %43, %38
  br label %75

75:                                               ; preds = %74, %37
  br label %76

76:                                               ; preds = %75, %26
  br label %77

77:                                               ; preds = %76, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_SyncOkCallback() #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_SyncWarnCallback() #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_ExpectedSyncCallback() #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_ErrorCallback(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12}
!11 = !{!10, !6, i64 0}
!12 = !{!10, !6, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @HAL_RCCEx_CRS_IRQHandler() local_unnamed_addr #0 {
  %1 = load volatile i32, ptr inttoptr (i64 1073775624 to ptr), align 8, !tbaa !5
  %2 = load volatile i32, ptr inttoptr (i64 1073775616 to ptr), align 1024, !tbaa !10
  %3 = zext i32 %1 to i64
  %4 = and i64 %3, 1
  %.not = icmp eq i64 %4, 0
  %5 = and i32 %2, 1
  %.not15 = icmp eq i32 %5, 0
  %or.cond = select i1 %.not, i1 true, i1 %.not15
  br i1 %or.cond, label %7, label %6

6:                                                ; preds = %0
  store volatile i32 1, ptr inttoptr (i64 1073775628 to ptr), align 4, !tbaa !11
  tail call void @HAL_RCCEx_CRS_SyncOkCallback()
  br label %20

7:                                                ; preds = %0
  %8 = and i64 %3, 2
  %.not16 = icmp eq i64 %8, 0
  %9 = and i32 %2, 2
  %.not17 = icmp eq i32 %9, 0
  %or.cond25 = select i1 %.not16, i1 true, i1 %.not17
  br i1 %or.cond25, label %11, label %10

10:                                               ; preds = %7
  store volatile i32 2, ptr inttoptr (i64 1073775628 to ptr), align 4, !tbaa !11
  tail call void @HAL_RCCEx_CRS_SyncWarnCallback()
  br label %20

11:                                               ; preds = %7
  %12 = and i64 %3, 8
  %.not18 = icmp eq i64 %12, 0
  %13 = and i32 %2, 8
  %.not19 = icmp eq i32 %13, 0
  %or.cond26 = select i1 %.not18, i1 true, i1 %.not19
  br i1 %or.cond26, label %15, label %14

14:                                               ; preds = %11
  store volatile i32 8, ptr inttoptr (i64 1073775628 to ptr), align 4, !tbaa !11
  tail call void @HAL_RCCEx_CRS_ExpectedSyncCallback()
  br label %20

15:                                               ; preds = %11
  %16 = and i64 %3, 4
  %.not20 = icmp eq i64 %16, 0
  %17 = and i32 %2, 4
  %.not21 = icmp eq i32 %17, 0
  %or.cond27 = select i1 %.not20, i1 true, i1 %.not21
  br i1 %or.cond27, label %20, label %18

18:                                               ; preds = %15
  %19 = lshr i32 %1, 5
  %.2 = and i32 %19, 56
  store volatile i32 4, ptr inttoptr (i64 1073775628 to ptr), align 4, !tbaa !11
  tail call void @HAL_RCCEx_CRS_ErrorCallback(i32 noundef %.2)
  br label %20

20:                                               ; preds = %10, %15, %18, %14, %6
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_SyncOkCallback() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_SyncWarnCallback() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_ExpectedSyncCallback() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_RCCEx_CRS_ErrorCallback(i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = !{!6, !7, i64 12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass