; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Init)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SRAM_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32, ptr }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FMC_Bank1_TypeDef = type { [8 x i32] }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SRAM_Init(ptr noundef %0, ptr noundef %1, ptr noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  %8 = load ptr, ptr %5, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %3
  store i32 1, ptr %4, align 4
  br label %69

11:                                               ; preds = %3
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %12, i32 0, i32 4
  %14 = load volatile i32, ptr %13, align 8, !tbaa !9
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %16, label %20

16:                                               ; preds = %11
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %17, i32 0, i32 3
  store i32 0, ptr %18, align 4, !tbaa !13
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  call void @HAL_SRAM_MspInit(ptr noundef %19)
  br label %20

20:                                               ; preds = %16, %11
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %21, i32 0, i32 0
  %23 = load ptr, ptr %22, align 8, !tbaa !14
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %24, i32 0, i32 2
  %26 = call i32 @FMC_NORSRAM_Init(ptr noundef %23, ptr noundef %25)
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %27, i32 0, i32 0
  %29 = load ptr, ptr %28, align 8, !tbaa !14
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %31, i32 0, i32 2
  %33 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %32, i32 0, i32 0
  %34 = load i32, ptr %33, align 8, !tbaa !15
  %35 = call i32 @FMC_NORSRAM_Timing_Init(ptr noundef %29, ptr noundef %30, i32 noundef %34)
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %36, i32 0, i32 1
  %38 = load ptr, ptr %37, align 8, !tbaa !16
  %39 = load ptr, ptr %7, align 8, !tbaa !5
  %40 = load ptr, ptr %5, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %40, i32 0, i32 2
  %42 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %41, i32 0, i32 0
  %43 = load i32, ptr %42, align 8, !tbaa !15
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %44, i32 0, i32 2
  %46 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %45, i32 0, i32 9
  %47 = load i32, ptr %46, align 4, !tbaa !17
  %48 = call i32 @FMC_NORSRAM_Extended_Timing_Init(ptr noundef %38, ptr noundef %39, i32 noundef %43, i32 noundef %47)
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !14
  %52 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %51, i32 0, i32 0
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %53, i32 0, i32 2
  %55 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %54, i32 0, i32 0
  %56 = load i32, ptr %55, align 8, !tbaa !15
  %57 = zext i32 %56 to i64
  %58 = getelementptr inbounds [8 x i32], ptr %52, i64 0, i64 %57
  %59 = load volatile i32, ptr %58, align 4, !tbaa !18
  %60 = zext i32 %59 to i64
  %61 = or i64 %60, 1
  %62 = trunc i64 %61 to i32
  store volatile i32 %62, ptr %58, align 4, !tbaa !18
  %63 = load volatile i32, ptr inttoptr (i64 1375748096 to ptr), align 4, !tbaa !18
  %64 = zext i32 %63 to i64
  %65 = or i64 %64, 2147483648
  %66 = trunc i64 %65 to i32
  store volatile i32 %66, ptr inttoptr (i64 1375748096 to ptr), align 4, !tbaa !18
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %67, i32 0, i32 4
  store volatile i32 1, ptr %68, align 8, !tbaa !9
  store i32 0, ptr %4, align 4
  br label %69

69:                                               ; preds = %20, %10
  %70 = load i32, ptr %4, align 4
  ret i32 %70
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_SRAM_MspInit(ptr noundef) #0

declare i32 @FMC_NORSRAM_Init(ptr noundef, ptr noundef) #1

declare i32 @FMC_NORSRAM_Timing_Init(ptr noundef, ptr noundef, i32 noundef) #1

declare i32 @FMC_NORSRAM_Extended_Timing_Init(ptr noundef, ptr noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 80}
!10 = !{!"", !6, i64 0, !6, i64 8, !11, i64 16, !12, i64 76, !12, i64 80, !6, i64 88}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 76}
!14 = !{!10, !6, i64 0}
!15 = !{!10, !12, i64 16}
!16 = !{!10, !6, i64 8}
!17 = !{!10, !12, i64 52}
!18 = !{!12, !12, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_SRAM_Init(ptr noundef %0, ptr noundef %1, ptr noundef %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %0, null
  br i1 %4, label %32, label %5

5:                                                ; preds = %3
  %6 = getelementptr inbounds i8, ptr %0, i64 80
  %7 = load volatile i32, ptr %6, align 8, !tbaa !5
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %11

9:                                                ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 76
  store i32 0, ptr %10, align 4, !tbaa !12
  tail call void @HAL_SRAM_MspInit(ptr noundef nonnull %0)
  br label %11

11:                                               ; preds = %9, %5
  %12 = load ptr, ptr %0, align 8, !tbaa !13
  %13 = getelementptr inbounds i8, ptr %0, i64 16
  %14 = tail call i32 @FMC_NORSRAM_Init(ptr noundef %12, ptr noundef nonnull %13) #2
  %15 = load ptr, ptr %0, align 8, !tbaa !13
  %16 = load i32, ptr %13, align 8, !tbaa !14
  %17 = tail call i32 @FMC_NORSRAM_Timing_Init(ptr noundef %15, ptr noundef %1, i32 noundef %16) #2
  %18 = getelementptr inbounds i8, ptr %0, i64 8
  %19 = load ptr, ptr %18, align 8, !tbaa !15
  %20 = load i32, ptr %13, align 8, !tbaa !14
  %21 = getelementptr inbounds i8, ptr %0, i64 52
  %22 = load i32, ptr %21, align 4, !tbaa !16
  %23 = tail call i32 @FMC_NORSRAM_Extended_Timing_Init(ptr noundef %19, ptr noundef %2, i32 noundef %20, i32 noundef %22) #2
  %24 = load ptr, ptr %0, align 8, !tbaa !13
  %25 = load i32, ptr %13, align 8, !tbaa !14
  %26 = zext i32 %25 to i64
  %27 = getelementptr inbounds [8 x i32], ptr %24, i64 0, i64 %26
  %28 = load volatile i32, ptr %27, align 4, !tbaa !17
  %29 = or i32 %28, 1
  store volatile i32 %29, ptr %27, align 4, !tbaa !17
  %30 = load volatile i32, ptr inttoptr (i64 1375748096 to ptr), align 16384, !tbaa !17
  %31 = or i32 %30, -2147483648
  store volatile i32 %31, ptr inttoptr (i64 1375748096 to ptr), align 16384, !tbaa !17
  store volatile i32 1, ptr %6, align 8, !tbaa !5
  br label %32

32:                                               ; preds = %3, %11
  %.0 = phi i32 [ 0, %11 ], [ 1, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_SRAM_MspInit(ptr noundef) local_unnamed_addr #0

declare i32 @FMC_NORSRAM_Init(ptr noundef, ptr noundef) local_unnamed_addr #1

declare i32 @FMC_NORSRAM_Timing_Init(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

declare i32 @FMC_NORSRAM_Extended_Timing_Init(ptr noundef, ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80, !7, i64 88}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !7, i64 0}
!14 = !{!6, !11, i64 16}
!15 = !{!6, !7, i64 8}
!16 = !{!6, !11, i64 52}
!17 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass