; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Program)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NOR_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32 }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@uwNORMemoryDataWidth = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NOR_Program(ptr noundef %0, ptr noundef %1, ptr noundef %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %10, i32 0, i32 4
  %12 = load volatile i32, ptr %11, align 8, !tbaa !9
  %13 = icmp eq i32 %12, 2
  br i1 %13, label %14, label %15

14:                                               ; preds = %3
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %123

15:                                               ; preds = %3
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %16, i32 0, i32 4
  %18 = load volatile i32, ptr %17, align 8, !tbaa !9
  %19 = icmp eq i32 %18, 1
  br i1 %19, label %20, label %120

20:                                               ; preds = %15
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %22, i32 0, i32 3
  %24 = load i32, ptr %23, align 4, !tbaa !13
  %25 = icmp eq i32 %24, 1
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %123

27:                                               ; preds = %21
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %28, i32 0, i32 3
  store i32 1, ptr %29, align 4, !tbaa !13
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %33, i32 0, i32 4
  store volatile i32 2, ptr %34, align 8, !tbaa !9
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %35, i32 0, i32 2
  %37 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %36, i32 0, i32 0
  %38 = load i32, ptr %37, align 8, !tbaa !14
  %39 = icmp eq i32 %38, 0
  br i1 %39, label %40, label %41

40:                                               ; preds = %32
  store i32 1610612736, ptr %8, align 4, !tbaa !15
  br label %58

41:                                               ; preds = %32
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %42, i32 0, i32 2
  %44 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %43, i32 0, i32 0
  %45 = load i32, ptr %44, align 8, !tbaa !14
  %46 = icmp eq i32 %45, 2
  br i1 %46, label %47, label %48

47:                                               ; preds = %41
  store i32 1677721600, ptr %8, align 4, !tbaa !15
  br label %57

48:                                               ; preds = %41
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %49, i32 0, i32 2
  %51 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %50, i32 0, i32 0
  %52 = load i32, ptr %51, align 8, !tbaa !14
  %53 = icmp eq i32 %52, 4
  br i1 %53, label %54, label %55

54:                                               ; preds = %48
  store i32 1744830464, ptr %8, align 4, !tbaa !15
  br label %56

55:                                               ; preds = %48
  store i32 1811939328, ptr %8, align 4, !tbaa !15
  br label %56

56:                                               ; preds = %55, %54
  br label %57

57:                                               ; preds = %56, %47
  br label %58

58:                                               ; preds = %57, %40
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !15
  %61 = icmp eq i32 %60, 1
  br i1 %61, label %62, label %65

62:                                               ; preds = %59
  %63 = load i32, ptr %8, align 4, !tbaa !15
  %64 = add i32 %63, 2730
  br label %68

65:                                               ; preds = %59
  %66 = load i32, ptr %8, align 4, !tbaa !15
  %67 = add i32 %66, 1365
  br label %68

68:                                               ; preds = %65, %62
  %69 = phi i32 [ %64, %62 ], [ %67, %65 ]
  %70 = zext i32 %69 to i64
  %71 = inttoptr i64 %70 to ptr
  store volatile i16 170, ptr %71, align 2, !tbaa !16
  call void @__DSB()
  br label %72

72:                                               ; preds = %68
  br label %73

73:                                               ; preds = %72
  br label %74

74:                                               ; preds = %73
  %75 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !15
  %76 = icmp eq i32 %75, 1
  br i1 %76, label %77, label %80

77:                                               ; preds = %74
  %78 = load i32, ptr %8, align 4, !tbaa !15
  %79 = add i32 %78, 1364
  br label %83

80:                                               ; preds = %74
  %81 = load i32, ptr %8, align 4, !tbaa !15
  %82 = add i32 %81, 682
  br label %83

83:                                               ; preds = %80, %77
  %84 = phi i32 [ %79, %77 ], [ %82, %80 ]
  %85 = zext i32 %84 to i64
  %86 = inttoptr i64 %85 to ptr
  store volatile i16 85, ptr %86, align 2, !tbaa !16
  call void @__DSB()
  br label %87

87:                                               ; preds = %83
  br label %88

88:                                               ; preds = %87
  br label %89

89:                                               ; preds = %88
  %90 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !15
  %91 = icmp eq i32 %90, 1
  br i1 %91, label %92, label %95

92:                                               ; preds = %89
  %93 = load i32, ptr %8, align 4, !tbaa !15
  %94 = add i32 %93, 2730
  br label %98

95:                                               ; preds = %89
  %96 = load i32, ptr %8, align 4, !tbaa !15
  %97 = add i32 %96, 1365
  br label %98

98:                                               ; preds = %95, %92
  %99 = phi i32 [ %94, %92 ], [ %97, %95 ]
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  store volatile i16 160, ptr %101, align 2, !tbaa !16
  call void @__DSB()
  br label %102

102:                                              ; preds = %98
  br label %103

103:                                              ; preds = %102
  br label %104

104:                                              ; preds = %103
  %105 = load ptr, ptr %7, align 8, !tbaa !5
  %106 = load i16, ptr %105, align 2, !tbaa !16
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = ptrtoint ptr %107 to i32
  %109 = zext i32 %108 to i64
  %110 = inttoptr i64 %109 to ptr
  store volatile i16 %106, ptr %110, align 2, !tbaa !16
  call void @__DSB()
  br label %111

111:                                              ; preds = %104
  br label %112

112:                                              ; preds = %111
  %113 = load ptr, ptr %5, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %113, i32 0, i32 4
  store volatile i32 1, ptr %114, align 8, !tbaa !9
  br label %115

115:                                              ; preds = %112
  %116 = load ptr, ptr %5, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %116, i32 0, i32 3
  store i32 0, ptr %117, align 4, !tbaa !13
  br label %118

118:                                              ; preds = %115
  br label %119

119:                                              ; preds = %118
  br label %121

120:                                              ; preds = %15
  store i32 1, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %123

121:                                              ; preds = %119
  br label %122

122:                                              ; preds = %121
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %123

123:                                              ; preds = %122, %120, %26, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %124 = load i32, ptr %4, align 4
  ret i32 %124
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 80}
!10 = !{!"", !6, i64 0, !6, i64 8, !11, i64 16, !12, i64 76, !12, i64 80}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 76}
!14 = !{!10, !12, i64 16}
!15 = !{!12, !12, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@uwNORMemoryDataWidth = external hidden local_unnamed_addr global i32, align 4
@switch.table.HAL_NOR_Program = private unnamed_addr constant [5 x i32] [i32 1610612736, i32 1811939328, i32 1677721600, i32 1811939328, i32 1744830464], align 4

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_NOR_Program(ptr noundef %0, ptr noundef %1, ptr nocapture noundef readonly %2) local_unnamed_addr #1 {
  %4 = getelementptr inbounds i8, ptr %0, i64 80
  %5 = load volatile i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 2
  br i1 %6, label %41, label %7

7:                                                ; preds = %3
  %8 = load volatile i32, ptr %4, align 8, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %10, label %41

10:                                               ; preds = %7
  %11 = getelementptr inbounds i8, ptr %0, i64 76
  %12 = load i32, ptr %11, align 4, !tbaa !12
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %41, label %14

14:                                               ; preds = %10
  store i32 1, ptr %11, align 4, !tbaa !12
  store volatile i32 2, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %0, i64 16
  %16 = load i32, ptr %15, align 8, !tbaa !13
  %17 = icmp ult i32 %16, 5
  br i1 %17, label %switch.lookup, label %19

switch.lookup:                                    ; preds = %14
  %18 = zext nneg i32 %16 to i64
  %switch.gep = getelementptr inbounds [5 x i32], ptr @switch.table.HAL_NOR_Program, i64 0, i64 %18
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %19

19:                                               ; preds = %14, %switch.lookup
  %.0 = phi i32 [ %switch.load, %switch.lookup ], [ 1811939328, %14 ]
  %20 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %21 = icmp eq i32 %20, 1
  %22 = or disjoint i32 %.0, 2730
  %23 = or disjoint i32 %.0, 1365
  %24 = select i1 %21, i32 %22, i32 %23
  %25 = zext nneg i32 %24 to i64
  %26 = inttoptr i64 %25 to ptr
  store volatile i16 170, ptr %26, align 2, !tbaa !15
  tail call void @__DSB()
  %27 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %28 = icmp eq i32 %27, 1
  %.v = select i1 %28, i32 1364, i32 682
  %29 = or disjoint i32 %.v, %.0
  %30 = zext nneg i32 %29 to i64
  %31 = inttoptr i64 %30 to ptr
  store volatile i16 85, ptr %31, align 2, !tbaa !15
  tail call void @__DSB()
  %32 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %33 = icmp eq i32 %32, 1
  %34 = select i1 %33, i32 %22, i32 %23
  %35 = zext nneg i32 %34 to i64
  %36 = inttoptr i64 %35 to ptr
  store volatile i16 160, ptr %36, align 2, !tbaa !15
  tail call void @__DSB()
  %37 = load i16, ptr %2, align 2, !tbaa !15
  %38 = ptrtoint ptr %1 to i64
  %39 = and i64 %38, 4294967295
  %40 = inttoptr i64 %39 to ptr
  store volatile i16 %37, ptr %40, align 2, !tbaa !15
  tail call void @__DSB()
  store volatile i32 1, ptr %4, align 8, !tbaa !5
  store i32 0, ptr %11, align 4, !tbaa !12
  br label %41

41:                                               ; preds = %7, %10, %3, %19
  %.018 = phi i32 [ 0, %19 ], [ 2, %3 ], [ 2, %10 ], [ 1, %7 ]
  ret i32 %.018
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !11, i64 16}
!14 = !{!11, !11, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"short", !8, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass