; LLVM IR from plainNet/plainNet :: src/IntelHexParser.ll (ZN4kvpr5proto14IntelHexParser5parseEPhj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.kvpr::proto::IntelHexParser" = type { ptr, %"class.std::vector", %"class.std::vector", i8, i32, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4kvpr5proto14IntelHexParser13handleIHexRowEv(ptr noundef nonnull align 8 dereferenceable(72)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIhSaIhEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4kvpr5proto14IntelHexParser5parseEPhj(ptr noundef nonnull align 8 dereferenceable(72) %0, ptr noundef %1, i32 noundef %2) #0 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %8 = load ptr, ptr %4, align 8
  br label %9

9:                                                ; preds = %85, %3
  %10 = load i32, ptr %6, align 4, !tbaa !9
  %11 = add i32 %10, -1
  store i32 %11, ptr %6, align 4, !tbaa !9
  %12 = icmp ugt i32 %10, 0
  br i1 %12, label %13, label %86

13:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %14, i32 1
  store ptr %15, ptr %5, align 8, !tbaa !5
  %16 = load i8, ptr %14, align 1, !tbaa !11
  store i8 %16, ptr %7, align 1, !tbaa !11
  %17 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 3
  %18 = load i8, ptr %17, align 8, !tbaa !12, !range !19, !noundef !20
  %19 = trunc i8 %18 to i1
  br i1 %19, label %20, label %28

20:                                               ; preds = %13
  %21 = load i8, ptr %7, align 1, !tbaa !11
  %22 = zext i8 %21 to i32
  %23 = icmp eq i32 %22, 58
  br i1 %23, label %24, label %27

24:                                               ; preds = %20
  %25 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 1
  call void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %25) #3
  %26 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 3
  store i8 0, ptr %26, align 8, !tbaa !12
  br label %27

27:                                               ; preds = %24, %20
  br label %85

28:                                               ; preds = %13
  %29 = load i8, ptr %7, align 1, !tbaa !11
  %30 = zext i8 %29 to i32
  %31 = icmp eq i32 %30, 13
  br i1 %31, label %36, label %32

32:                                               ; preds = %28
  %33 = load i8, ptr %7, align 1, !tbaa !11
  %34 = zext i8 %33 to i32
  %35 = icmp eq i32 %34, 10
  br i1 %35, label %36, label %44

36:                                               ; preds = %32, %28
  %37 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 1
  %38 = call noundef i64 @_ZNKSt6vectorIhSaIhEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %37) #3
  %39 = icmp ne i64 %38, 0
  br i1 %39, label %40, label %41

40:                                               ; preds = %36
  call void @_ZN4kvpr5proto14IntelHexParser13handleIHexRowEv(ptr noundef nonnull align 8 dereferenceable(72) %8)
  br label %41

41:                                               ; preds = %40, %36
  %42 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 1
  call void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %42) #3
  %43 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 3
  store i8 1, ptr %43, align 8, !tbaa !12
  br label %84

44:                                               ; preds = %32
  %45 = load i8, ptr %7, align 1, !tbaa !11
  %46 = zext i8 %45 to i32
  %47 = icmp sge i32 %46, 48
  br i1 %47, label %48, label %52

48:                                               ; preds = %44
  %49 = load i8, ptr %7, align 1, !tbaa !11
  %50 = zext i8 %49 to i32
  %51 = icmp sle i32 %50, 57
  br i1 %51, label %68, label %52

52:                                               ; preds = %48, %44
  %53 = load i8, ptr %7, align 1, !tbaa !11
  %54 = zext i8 %53 to i32
  %55 = icmp sge i32 %54, 65
  br i1 %55, label %56, label %60

56:                                               ; preds = %52
  %57 = load i8, ptr %7, align 1, !tbaa !11
  %58 = zext i8 %57 to i32
  %59 = icmp sle i32 %58, 70
  br i1 %59, label %68, label %60

60:                                               ; preds = %56, %52
  %61 = load i8, ptr %7, align 1, !tbaa !11
  %62 = zext i8 %61 to i32
  %63 = icmp sge i32 %62, 97
  br i1 %63, label %64, label %70

64:                                               ; preds = %60
  %65 = load i8, ptr %7, align 1, !tbaa !11
  %66 = zext i8 %65 to i32
  %67 = icmp sle i32 %66, 102
  br i1 %67, label %68, label %70

68:                                               ; preds = %64, %56, %48
  %69 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 1
  call void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24) %69, ptr noundef nonnull align 1 dereferenceable(1) %7)
  br label %83

70:                                               ; preds = %64, %60
  %71 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 5
  %72 = load ptr, ptr %71, align 8, !tbaa !21
  %73 = icmp ne ptr %72, null
  br i1 %73, label %74, label %82

74:                                               ; preds = %70
  %75 = getelementptr inbounds %"class.kvpr::proto::IntelHexParser", ptr %8, i32 0, i32 5
  %76 = load ptr, ptr %75, align 8, !tbaa !21
  %77 = load i8, ptr %7, align 1, !tbaa !11
  %78 = zext i8 %77 to i32
  %79 = load ptr, ptr %76, align 8, !tbaa !22
  %80 = getelementptr inbounds ptr, ptr %79, i64 3
  %81 = load ptr, ptr %80, align 8
  call void %81(ptr noundef nonnull align 8 dereferenceable(8) %76, i32 noundef -1, i32 noundef %78)
  br label %82

82:                                               ; preds = %74, %70
  br label %83

83:                                               ; preds = %82, %68
  br label %84

84:                                               ; preds = %83, %41
  br label %85

85:                                               ; preds = %84, %27
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  br label %9, !llvm.loop !24

86:                                               ; preds = %9
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !18, i64 56}
!13 = !{!"_ZTSN4kvpr5proto14IntelHexParserE", !14, i64 8, !14, i64 32, !18, i64 56, !10, i64 60, !6, i64 64}
!14 = !{!"_ZTSSt6vectorIhSaIhEE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIhSaIhEE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"bool", !7, i64 0}
!19 = !{i8 0, i8 2}
!20 = !{}
!21 = !{!13, !6, i64 64}
!22 = !{!23, !23, i64 0}
!23 = !{!"vtable pointer", !8, i64 0}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4kvpr5proto14IntelHexParser13handleIHexRowEv(ptr noundef nonnull align 8 dereferenceable(72)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIhSaIhEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4kvpr5proto14IntelHexParser5parseEPhj(ptr noundef nonnull align 8 dereferenceable(72) %0, ptr nocapture noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 align 2 {
  %4 = alloca i8, align 1
  %.not19 = icmp eq i32 %2, 0
  br i1 %.not19, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %3
  %5 = getelementptr inbounds i8, ptr %0, i64 56
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = getelementptr inbounds i8, ptr %0, i64 64
  br label %8

8:                                                ; preds = %.lr.ph, %32
  %.in = phi i32 [ %2, %.lr.ph ], [ %9, %32 ]
  %.01320 = phi ptr [ %1, %.lr.ph ], [ %10, %32 ]
  %9 = add i32 %.in, -1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  %10 = getelementptr inbounds i8, ptr %.01320, i64 1
  %11 = load i8, ptr %.01320, align 1, !tbaa !5
  store i8 %11, ptr %4, align 1, !tbaa !5
  %12 = load i8, ptr %5, align 8, !tbaa !8, !range !17, !noundef !18
  %13 = trunc nuw i8 %12 to i1
  br i1 %13, label %14, label %17

14:                                               ; preds = %8
  %15 = icmp eq i8 %11, 58
  br i1 %15, label %16, label %32

16:                                               ; preds = %14
  call void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  store i8 0, ptr %5, align 8, !tbaa !8
  br label %32

17:                                               ; preds = %8
  %18 = zext i8 %11 to i32
  switch i8 %11, label %23 [
    i8 13, label %19
    i8 10, label %19
  ]

19:                                               ; preds = %17, %17
  %20 = call noundef i64 @_ZNKSt6vectorIhSaIhEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %.not17 = icmp eq i64 %20, 0
  br i1 %.not17, label %22, label %21

21:                                               ; preds = %19
  call void @_ZN4kvpr5proto14IntelHexParser13handleIHexRowEv(ptr noundef nonnull align 8 dereferenceable(72) %0)
  br label %22

22:                                               ; preds = %21, %19
  call void @_ZNSt6vectorIhSaIhEE5clearEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  store i8 1, ptr %5, align 8, !tbaa !8
  br label %32

23:                                               ; preds = %17
  %24 = add i8 %11, -48
  %or.cond5 = icmp ult i8 %24, 10
  br i1 %or.cond5, label %25, label %switch.early.test

switch.early.test:                                ; preds = %23
  switch i8 %11, label %26 [
    i8 102, label %25
    i8 101, label %25
    i8 100, label %25
    i8 99, label %25
    i8 98, label %25
    i8 97, label %25
    i8 70, label %25
    i8 69, label %25
    i8 68, label %25
    i8 67, label %25
    i8 66, label %25
    i8 65, label %25
  ]

25:                                               ; preds = %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %switch.early.test, %23
  call void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 1 dereferenceable(1) %4)
  br label %32

26:                                               ; preds = %switch.early.test
  %27 = load ptr, ptr %7, align 8, !tbaa !19
  %.not16 = icmp eq ptr %27, null
  br i1 %.not16, label %32, label %28

28:                                               ; preds = %26
  %29 = load ptr, ptr %27, align 8, !tbaa !20
  %30 = getelementptr inbounds i8, ptr %29, i64 24
  %31 = load ptr, ptr %30, align 8
  call void %31(ptr noundef nonnull align 8 dereferenceable(8) %27, i32 noundef -1, i32 noundef %18)
  br label %32

32:                                               ; preds = %22, %26, %28, %25, %14, %16
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  %.not = icmp eq i32 %9, 0
  br i1 %.not, label %._crit_edge, label %8, !llvm.loop !22

._crit_edge:                                      ; preds = %32, %3
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !15, i64 56}
!9 = !{!"_ZTSN4kvpr5proto14IntelHexParserE", !10, i64 8, !10, i64 32, !15, i64 56, !16, i64 60, !14, i64 64}
!10 = !{!"_ZTSSt6vectorIhSaIhEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIhSaIhEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !6, i64 0}
!15 = !{!"bool", !6, i64 0}
!16 = !{!"int", !6, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = !{!9, !14, i64 64}
!20 = !{!21, !21, i64 0}
!21 = !{!"vtable pointer", !7, i64 0}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass