; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (8b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Write_SpareArea_8b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #4
  %19 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %19, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %20, ptr %17, align 8, !tbaa !5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load volatile i32, ptr %22, align 8, !tbaa !11
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %26

25:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %302

26:                                               ; preds = %4
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %27, i32 0, i32 3
  %29 = load volatile i32, ptr %28, align 8, !tbaa !11
  %30 = icmp eq i32 %29, 1
  br i1 %30, label %31, label %299

31:                                               ; preds = %26
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %33, i32 0, i32 2
  %35 = load i32, ptr %34, align 4, !tbaa !14
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %302

38:                                               ; preds = %32
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %39, i32 0, i32 2
  store i32 1, ptr %40, align 4, !tbaa !14
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %44, i32 0, i32 3
  store volatile i32 2, ptr %45, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %46 = load ptr, ptr %7, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %46, i32 0, i32 0
  %48 = load i16, ptr %47, align 2, !tbaa !15
  %49 = zext i16 %48 to i32
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %50, i32 0, i32 2
  %52 = load i16, ptr %51, align 2, !tbaa !18
  %53 = zext i16 %52 to i32
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %54, i32 0, i32 1
  %56 = load i16, ptr %55, align 2, !tbaa !19
  %57 = zext i16 %56 to i32
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %58, i32 0, i32 4
  %60 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %59, i32 0, i32 5
  %61 = load i32, ptr %60, align 4, !tbaa !20
  %62 = mul i32 %57, %61
  %63 = add i32 %53, %62
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %64, i32 0, i32 4
  %66 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %65, i32 0, i32 2
  %67 = load i32, ptr %66, align 4, !tbaa !21
  %68 = mul i32 %63, %67
  %69 = add i32 %49, %68
  store i32 %69, ptr %14, align 4, !tbaa !9
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %70, i32 0, i32 4
  %72 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 4, !tbaa !22
  store i32 %73, ptr %15, align 4, !tbaa !9
  br label %74

74:                                               ; preds = %284, %43
  %75 = load i32, ptr %16, align 4, !tbaa !9
  %76 = icmp ne i32 %75, 0
  br i1 %76, label %77, label %89

77:                                               ; preds = %74
  %78 = load i32, ptr %14, align 4, !tbaa !9
  %79 = load ptr, ptr %6, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %79, i32 0, i32 4
  %81 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %80, i32 0, i32 2
  %82 = load i32, ptr %81, align 4, !tbaa !21
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %83, i32 0, i32 4
  %85 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %84, i32 0, i32 3
  %86 = load i32, ptr %85, align 4, !tbaa !23
  %87 = mul i32 %82, %86
  %88 = icmp ult i32 %78, %87
  br label %89

89:                                               ; preds = %77, %74
  %90 = phi i1 [ false, %74 ], [ %88, %77 ]
  br i1 %90, label %91, label %291

91:                                               ; preds = %89
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %92, i32 0, i32 4
  %94 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %93, i32 0, i32 0
  %95 = load i32, ptr %94, align 4, !tbaa !22
  %96 = icmp ule i32 %95, 512
  br i1 %96, label %97, label %160

97:                                               ; preds = %91
  %98 = load i32, ptr %12, align 4, !tbaa !9
  %99 = or i32 %98, 65536
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  store volatile i8 80, ptr %101, align 1, !tbaa !24
  call void @__DSB()
  %102 = load i32, ptr %12, align 4, !tbaa !9
  %103 = or i32 %102, 65536
  %104 = zext i32 %103 to i64
  %105 = inttoptr i64 %104 to ptr
  store volatile i8 -128, ptr %105, align 1, !tbaa !24
  call void @__DSB()
  %106 = load ptr, ptr %6, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %106, i32 0, i32 4
  %108 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %107, i32 0, i32 2
  %109 = load i32, ptr %108, align 4, !tbaa !21
  %110 = load ptr, ptr %6, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %110, i32 0, i32 4
  %112 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %111, i32 0, i32 3
  %113 = load i32, ptr %112, align 4, !tbaa !23
  %114 = mul i32 %109, %113
  %115 = icmp ule i32 %114, 65535
  br i1 %115, label %116, label %134

116:                                              ; preds = %97
  %117 = load i32, ptr %12, align 4, !tbaa !9
  %118 = or i32 %117, 131072
  %119 = zext i32 %118 to i64
  %120 = inttoptr i64 %119 to ptr
  store volatile i8 0, ptr %120, align 1, !tbaa !24
  call void @__DSB()
  %121 = load i32, ptr %14, align 4, !tbaa !9
  %122 = trunc i32 %121 to i8
  %123 = load i32, ptr %12, align 4, !tbaa !9
  %124 = or i32 %123, 131072
  %125 = zext i32 %124 to i64
  %126 = inttoptr i64 %125 to ptr
  store volatile i8 %122, ptr %126, align 1, !tbaa !24
  call void @__DSB()
  %127 = load i32, ptr %14, align 4, !tbaa !9
  %128 = lshr i32 %127, 8
  %129 = trunc i32 %128 to i8
  %130 = load i32, ptr %12, align 4, !tbaa !9
  %131 = or i32 %130, 131072
  %132 = zext i32 %131 to i64
  %133 = inttoptr i64 %132 to ptr
  store volatile i8 %129, ptr %133, align 1, !tbaa !24
  call void @__DSB()
  br label %159

134:                                              ; preds = %97
  %135 = load i32, ptr %12, align 4, !tbaa !9
  %136 = or i32 %135, 131072
  %137 = zext i32 %136 to i64
  %138 = inttoptr i64 %137 to ptr
  store volatile i8 0, ptr %138, align 1, !tbaa !24
  call void @__DSB()
  %139 = load i32, ptr %14, align 4, !tbaa !9
  %140 = trunc i32 %139 to i8
  %141 = load i32, ptr %12, align 4, !tbaa !9
  %142 = or i32 %141, 131072
  %143 = zext i32 %142 to i64
  %144 = inttoptr i64 %143 to ptr
  store volatile i8 %140, ptr %144, align 1, !tbaa !24
  call void @__DSB()
  %145 = load i32, ptr %14, align 4, !tbaa !9
  %146 = lshr i32 %145, 8
  %147 = trunc i32 %146 to i8
  %148 = load i32, ptr %12, align 4, !tbaa !9
  %149 = or i32 %148, 131072
  %150 = zext i32 %149 to i64
  %151 = inttoptr i64 %150 to ptr
  store volatile i8 %147, ptr %151, align 1, !tbaa !24
  call void @__DSB()
  %152 = load i32, ptr %14, align 4, !tbaa !9
  %153 = lshr i32 %152, 16
  %154 = trunc i32 %153 to i8
  %155 = load i32, ptr %12, align 4, !tbaa !9
  %156 = or i32 %155, 131072
  %157 = zext i32 %156 to i64
  %158 = inttoptr i64 %157 to ptr
  store volatile i8 %154, ptr %158, align 1, !tbaa !24
  call void @__DSB()
  br label %159

159:                                              ; preds = %134, %116
  br label %241

160:                                              ; preds = %91
  %161 = load i32, ptr %12, align 4, !tbaa !9
  %162 = or i32 %161, 65536
  %163 = zext i32 %162 to i64
  %164 = inttoptr i64 %163 to ptr
  store volatile i8 0, ptr %164, align 1, !tbaa !24
  call void @__DSB()
  %165 = load i32, ptr %12, align 4, !tbaa !9
  %166 = or i32 %165, 65536
  %167 = zext i32 %166 to i64
  %168 = inttoptr i64 %167 to ptr
  store volatile i8 -128, ptr %168, align 1, !tbaa !24
  call void @__DSB()
  %169 = load ptr, ptr %6, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %169, i32 0, i32 4
  %171 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %170, i32 0, i32 2
  %172 = load i32, ptr %171, align 4, !tbaa !21
  %173 = load ptr, ptr %6, align 8, !tbaa !5
  %174 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %173, i32 0, i32 4
  %175 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %174, i32 0, i32 3
  %176 = load i32, ptr %175, align 4, !tbaa !23
  %177 = mul i32 %172, %176
  %178 = icmp ule i32 %177, 65535
  br i1 %178, label %179, label %206

179:                                              ; preds = %160
  %180 = load i32, ptr %15, align 4, !tbaa !9
  %181 = trunc i32 %180 to i8
  %182 = load i32, ptr %12, align 4, !tbaa !9
  %183 = or i32 %182, 131072
  %184 = zext i32 %183 to i64
  %185 = inttoptr i64 %184 to ptr
  store volatile i8 %181, ptr %185, align 1, !tbaa !24
  call void @__DSB()
  %186 = load i32, ptr %15, align 4, !tbaa !9
  %187 = lshr i32 %186, 8
  %188 = trunc i32 %187 to i8
  %189 = load i32, ptr %12, align 4, !tbaa !9
  %190 = or i32 %189, 131072
  %191 = zext i32 %190 to i64
  %192 = inttoptr i64 %191 to ptr
  store volatile i8 %188, ptr %192, align 1, !tbaa !24
  call void @__DSB()
  %193 = load i32, ptr %14, align 4, !tbaa !9
  %194 = trunc i32 %193 to i8
  %195 = load i32, ptr %12, align 4, !tbaa !9
  %196 = or i32 %195, 131072
  %197 = zext i32 %196 to i64
  %198 = inttoptr i64 %197 to ptr
  store volatile i8 %194, ptr %198, align 1, !tbaa !24
  call void @__DSB()
  %199 = load i32, ptr %14, align 4, !tbaa !9
  %200 = lshr i32 %199, 8
  %201 = trunc i32 %200 to i8
  %202 = load i32, ptr %12, align 4, !tbaa !9
  %203 = or i32 %202, 131072
  %204 = zext i32 %203 to i64
  %205 = inttoptr i64 %204 to ptr
  store volatile i8 %201, ptr %205, align 1, !tbaa !24
  call void @__DSB()
  br label %240

206:                                              ; preds = %160
  %207 = load i32, ptr %15, align 4, !tbaa !9
  %208 = trunc i32 %207 to i8
  %209 = load i32, ptr %12, align 4, !tbaa !9
  %210 = or i32 %209, 131072
  %211 = zext i32 %210 to i64
  %212 = inttoptr i64 %211 to ptr
  store volatile i8 %208, ptr %212, align 1, !tbaa !24
  call void @__DSB()
  %213 = load i32, ptr %15, align 4, !tbaa !9
  %214 = lshr i32 %213, 8
  %215 = trunc i32 %214 to i8
  %216 = load i32, ptr %12, align 4, !tbaa !9
  %217 = or i32 %216, 131072
  %218 = zext i32 %217 to i64
  %219 = inttoptr i64 %218 to ptr
  store volatile i8 %215, ptr %219, align 1, !tbaa !24
  call void @__DSB()
  %220 = load i32, ptr %14, align 4, !tbaa !9
  %221 = trunc i32 %220 to i8
  %222 = load i32, ptr %12, align 4, !tbaa !9
  %223 = or i32 %222, 131072
  %224 = zext i32 %223 to i64
  %225 = inttoptr i64 %224 to ptr
  store volatile i8 %221, ptr %225, align 1, !tbaa !24
  call void @__DSB()
  %226 = load i32, ptr %14, align 4, !tbaa !9
  %227 = lshr i32 %226, 8
  %228 = trunc i32 %227 to i8
  %229 = load i32, ptr %12, align 4, !tbaa !9
  %230 = or i32 %229, 131072
  %231 = zext i32 %230 to i64
  %232 = inttoptr i64 %231 to ptr
  store volatile i8 %228, ptr %232, align 1, !tbaa !24
  call void @__DSB()
  %233 = load i32, ptr %14, align 4, !tbaa !9
  %234 = lshr i32 %233, 16
  %235 = trunc i32 %234 to i8
  %236 = load i32, ptr %12, align 4, !tbaa !9
  %237 = or i32 %236, 131072
  %238 = zext i32 %237 to i64
  %239 = inttoptr i64 %238 to ptr
  store volatile i8 %235, ptr %239, align 1, !tbaa !24
  call void @__DSB()
  br label %240

240:                                              ; preds = %206, %179
  br label %241

241:                                              ; preds = %240, %159
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %242

242:                                              ; preds = %257, %241
  %243 = load i32, ptr %10, align 4, !tbaa !9
  %244 = load ptr, ptr %6, align 8, !tbaa !5
  %245 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %244, i32 0, i32 4
  %246 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %245, i32 0, i32 1
  %247 = load i32, ptr %246, align 4, !tbaa !25
  %248 = icmp ult i32 %243, %247
  br i1 %248, label %249, label %260

249:                                              ; preds = %242
  %250 = load ptr, ptr %17, align 8, !tbaa !5
  %251 = load i8, ptr %250, align 1, !tbaa !24
  %252 = load i32, ptr %12, align 4, !tbaa !9
  %253 = zext i32 %252 to i64
  %254 = inttoptr i64 %253 to ptr
  store volatile i8 %251, ptr %254, align 1, !tbaa !24
  %255 = load ptr, ptr %17, align 8, !tbaa !5
  %256 = getelementptr inbounds i8, ptr %255, i32 1
  store ptr %256, ptr %17, align 8, !tbaa !5
  call void @__DSB()
  br label %257

257:                                              ; preds = %249
  %258 = load i32, ptr %10, align 4, !tbaa !9
  %259 = add i32 %258, 1
  store i32 %259, ptr %10, align 4, !tbaa !9
  br label %242, !llvm.loop !26

260:                                              ; preds = %242
  %261 = load i32, ptr %12, align 4, !tbaa !9
  %262 = or i32 %261, 65536
  %263 = zext i32 %262 to i64
  %264 = inttoptr i64 %263 to ptr
  store volatile i8 16, ptr %264, align 1, !tbaa !24
  call void @__DSB()
  %265 = call i32 @HAL_GetTick()
  store i32 %265, ptr %11, align 4, !tbaa !9
  br label %266

266:                                              ; preds = %283, %260
  %267 = load ptr, ptr %6, align 8, !tbaa !5
  %268 = call i32 @HAL_NAND_Read_Status(ptr noundef %267)
  %269 = icmp ne i32 %268, 64
  br i1 %269, label %270, label %284

270:                                              ; preds = %266
  %271 = call i32 @HAL_GetTick()
  %272 = load i32, ptr %11, align 4, !tbaa !9
  %273 = sub i32 %271, %272
  %274 = icmp ugt i32 %273, 16777216
  br i1 %274, label %275, label %283

275:                                              ; preds = %270
  %276 = load ptr, ptr %6, align 8, !tbaa !5
  %277 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %276, i32 0, i32 3
  store volatile i32 3, ptr %277, align 8, !tbaa !11
  br label %278

278:                                              ; preds = %275
  %279 = load ptr, ptr %6, align 8, !tbaa !5
  %280 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %279, i32 0, i32 2
  store i32 0, ptr %280, align 4, !tbaa !14
  br label %281

281:                                              ; preds = %278
  br label %282

282:                                              ; preds = %281
  store i32 3, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %302

283:                                              ; preds = %270
  br label %266, !llvm.loop !28

284:                                              ; preds = %266
  %285 = load i32, ptr %13, align 4, !tbaa !9
  %286 = add i32 %285, 1
  store i32 %286, ptr %13, align 4, !tbaa !9
  %287 = load i32, ptr %16, align 4, !tbaa !9
  %288 = add i32 %287, -1
  store i32 %288, ptr %16, align 4, !tbaa !9
  %289 = load i32, ptr %14, align 4, !tbaa !9
  %290 = add i32 %289, 1
  store i32 %290, ptr %14, align 4, !tbaa !9
  br label %74, !llvm.loop !29

291:                                              ; preds = %89
  %292 = load ptr, ptr %6, align 8, !tbaa !5
  %293 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %292, i32 0, i32 3
  store volatile i32 1, ptr %293, align 8, !tbaa !11
  br label %294

294:                                              ; preds = %291
  %295 = load ptr, ptr %6, align 8, !tbaa !5
  %296 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %295, i32 0, i32 2
  store i32 0, ptr %296, align 4, !tbaa !14
  br label %297

297:                                              ; preds = %294
  br label %298

298:                                              ; preds = %297
  br label %300

299:                                              ; preds = %26
  store i32 1, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %302

300:                                              ; preds = %298
  br label %301

301:                                              ; preds = %300
  store i32 0, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %302

302:                                              ; preds = %301, %299, %282, %37, %25
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %303 = load i32, ptr %5, align 4
  ret i32 %303
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 44}
!23 = !{!12, !10, i64 56}
!24 = !{!7, !7, i64 0}
!25 = !{!12, !10, i64 48}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = distinct !{!28, !27}
!29 = distinct !{!29, !27}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Write_SpareArea_8b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %82, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %82

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %82, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not80 = icmp eq i32 %3, 0
  br i1 %.not80, label %.sink.split89, label %.lr.ph85

.lr.ph85:                                         ; preds = %15
  %18 = load i32, ptr %16, align 4, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %0, i64 64
  %20 = load i32, ptr %19, align 4, !tbaa !14
  %21 = getelementptr inbounds i8, ptr %1, i64 2
  %22 = load i16, ptr %21, align 2, !tbaa !15
  %23 = zext i16 %22 to i32
  %24 = mul i32 %20, %23
  %25 = getelementptr inbounds i8, ptr %1, i64 4
  %26 = load i16, ptr %25, align 2, !tbaa !18
  %27 = zext i16 %26 to i32
  %28 = add i32 %24, %27
  %29 = load i32, ptr %17, align 4, !tbaa !19
  %30 = mul i32 %28, %29
  %31 = load i16, ptr %1, align 2, !tbaa !20
  %32 = zext i16 %31 to i32
  %33 = add i32 %30, %32
  %34 = getelementptr inbounds i8, ptr %0, i64 56
  %35 = trunc i32 %18 to i8
  %36 = lshr i32 %18, 8
  %37 = trunc i32 %36 to i8
  %38 = getelementptr inbounds i8, ptr %0, i64 48
  br label %39

39:                                               ; preds = %.lr.ph85, %79
  %.083 = phi ptr [ %2, %.lr.ph85 ], [ %.1.lcssa, %79 ]
  %.07282 = phi i32 [ %3, %.lr.ph85 ], [ %80, %79 ]
  %.07481 = phi i32 [ %33, %.lr.ph85 ], [ %81, %79 ]
  %40 = load i32, ptr %17, align 4, !tbaa !19
  %41 = load i32, ptr %34, align 4, !tbaa !21
  %42 = mul i32 %41, %40
  %43 = icmp ult i32 %.07481, %42
  br i1 %43, label %44, label %.sink.split89

44:                                               ; preds = %39
  %45 = load i32, ptr %16, align 4, !tbaa !13
  %46 = icmp ult i32 %45, 513
  br i1 %46, label %47, label %55

47:                                               ; preds = %44
  store volatile i8 80, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  store volatile i8 -128, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %48 = load i32, ptr %17, align 4, !tbaa !19
  %49 = load i32, ptr %34, align 4, !tbaa !21
  %50 = mul i32 %49, %48
  %51 = icmp ult i32 %50, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %52 = trunc i32 %.07481 to i8
  store volatile i8 %52, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %53 = lshr i32 %.07481, 8
  %54 = trunc i32 %53 to i8
  store volatile i8 %54, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %51, label %65, label %.sink.split

55:                                               ; preds = %44
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  store volatile i8 -128, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %56 = load i32, ptr %17, align 4, !tbaa !19
  %57 = load i32, ptr %34, align 4, !tbaa !21
  %58 = mul i32 %57, %56
  %59 = icmp ult i32 %58, 65536
  store volatile i8 %35, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  store volatile i8 %37, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %60 = trunc i32 %.07481 to i8
  store volatile i8 %60, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %61 = lshr i32 %.07481, 8
  %62 = trunc i32 %61 to i8
  store volatile i8 %62, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %59, label %65, label %.sink.split

.sink.split:                                      ; preds = %55, %47
  %63 = lshr i32 %.07481, 16
  %64 = trunc i32 %63 to i8
  store volatile i8 %64, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br label %65

65:                                               ; preds = %.sink.split, %55, %47
  %66 = load i32, ptr %38, align 4, !tbaa !23
  %.not87 = icmp eq i32 %66, 0
  br i1 %.not87, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %65, %.lr.ph
  %.179 = phi ptr [ %68, %.lr.ph ], [ %.083, %65 ]
  %.07678 = phi i32 [ %69, %.lr.ph ], [ 0, %65 ]
  %67 = load i8, ptr %.179, align 1, !tbaa !22
  store volatile i8 %67, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !22
  %68 = getelementptr inbounds i8, ptr %.179, i64 1
  tail call void @__DSB()
  %69 = add nuw i32 %.07678, 1
  %70 = load i32, ptr %38, align 4, !tbaa !23
  %71 = icmp ult i32 %69, %70
  br i1 %71, label %.lr.ph, label %._crit_edge, !llvm.loop !24

._crit_edge:                                      ; preds = %.lr.ph, %65
  %.1.lcssa = phi ptr [ %.083, %65 ], [ %68, %.lr.ph ]
  store volatile i8 16, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %72 = tail call i32 @HAL_GetTick() #3
  br label %73

73:                                               ; preds = %75, %._crit_edge
  %74 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not77 = icmp eq i32 %74, 64
  br i1 %.not77, label %79, label %75

75:                                               ; preds = %73
  %76 = tail call i32 @HAL_GetTick() #3
  %77 = sub i32 %76, %72
  %78 = icmp ugt i32 %77, 16777216
  br i1 %78, label %.sink.split89, label %73, !llvm.loop !26

79:                                               ; preds = %73
  %80 = add i32 %.07282, -1
  %81 = add i32 %.07481, 1
  %.not = icmp eq i32 %80, 0
  br i1 %.not, label %.sink.split89, label %39, !llvm.loop !27

.sink.split89:                                    ; preds = %79, %39, %75, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %75 ], [ 1, %39 ], [ 1, %79 ]
  %.073.ph = phi i32 [ 0, %15 ], [ 3, %75 ], [ 0, %39 ], [ 0, %79 ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %82

82:                                               ; preds = %.sink.split89, %8, %11, %4
  %.073 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.073.ph, %.sink.split89 ]
  ret i32 %.073
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 44}
!14 = !{!6, !11, i64 64}
!15 = !{!16, !17, i64 2}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !8, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!6, !11, i64 52}
!20 = !{!16, !17, i64 0}
!21 = !{!6, !11, i64 56}
!22 = !{!8, !8, i64 0}
!23 = !{!6, !11, i64 48}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = distinct !{!26, !25}
!27 = distinct !{!27, !25}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass