; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Init)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@SystemCoreClock = external global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Init(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store volatile i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = icmp eq ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %1
  store i32 1, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %467

14:                                               ; preds = %1
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %15, i32 0, i32 1
  %17 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %16, i32 0, i32 2
  %18 = load i32, ptr %17, align 8, !tbaa !11
  %19 = zext i32 %18 to i64
  %20 = icmp ne i64 %19, 0
  br i1 %20, label %21, label %29

21:                                               ; preds = %14
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %22, i32 0, i32 1
  %24 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %23, i32 0, i32 7
  %25 = load i32, ptr %24, align 4, !tbaa !16
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %21
  br label %28

28:                                               ; preds = %27, %21
  br label %29

29:                                               ; preds = %28, %14
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 4
  %32 = load volatile i32, ptr %31, align 4, !tbaa !17
  %33 = zext i32 %32 to i64
  %34 = icmp eq i64 %33, 0
  br i1 %34, label %35, label %41

35:                                               ; preds = %29
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  call void @HAL_ADC_MspInit(ptr noundef %36)
  %37 = load ptr, ptr %3, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %37, i32 0, i32 5
  store volatile i32 0, ptr %38, align 8, !tbaa !18
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 3
  store i32 0, ptr %40, align 8, !tbaa !19
  br label %41

41:                                               ; preds = %35, %29
  %42 = load ptr, ptr %3, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %42, i32 0, i32 0
  %44 = load ptr, ptr %43, align 8, !tbaa !20
  %45 = call i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef %44)
  %46 = zext i32 %45 to i64
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %48, label %52

48:                                               ; preds = %41
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !20
  call void @LL_ADC_DisableDeepPowerDown(ptr noundef %51)
  br label %52

52:                                               ; preds = %48, %41
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %53, i32 0, i32 0
  %55 = load ptr, ptr %54, align 8, !tbaa !20
  %56 = call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %55)
  %57 = zext i32 %56 to i64
  %58 = icmp eq i64 %57, 0
  br i1 %58, label %59, label %76

59:                                               ; preds = %52
  %60 = load ptr, ptr %3, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %60, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8, !tbaa !20
  call void @LL_ADC_EnableInternalRegulator(ptr noundef %62)
  %63 = load i32, ptr @SystemCoreClock, align 4, !tbaa !9
  %64 = zext i32 %63 to i64
  %65 = udiv i64 %64, 200000
  %66 = mul i64 1, %65
  %67 = trunc i64 %66 to i32
  store volatile i32 %67, ptr %7, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %72, %59
  %69 = load volatile i32, ptr %7, align 4, !tbaa !9
  %70 = zext i32 %69 to i64
  %71 = icmp ne i64 %70, 0
  br i1 %71, label %72, label %75

72:                                               ; preds = %68
  %73 = load volatile i32, ptr %7, align 4, !tbaa !9
  %74 = add i32 %73, -1
  store volatile i32 %74, ptr %7, align 4, !tbaa !9
  br label %68, !llvm.loop !21

75:                                               ; preds = %68
  br label %76

76:                                               ; preds = %75, %52
  %77 = load ptr, ptr %3, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !20
  %80 = call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %79)
  %81 = zext i32 %80 to i64
  %82 = icmp eq i64 %81, 0
  br i1 %82, label %83, label %94

83:                                               ; preds = %76
  %84 = load ptr, ptr %3, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %84, i32 0, i32 4
  %86 = load volatile i32, ptr %85, align 4, !tbaa !17
  %87 = zext i32 %86 to i64
  %88 = or i64 %87, 16
  %89 = trunc i64 %88 to i32
  store volatile i32 %89, ptr %85, align 4, !tbaa !17
  %90 = load ptr, ptr %3, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %90, i32 0, i32 5
  %92 = load volatile i32, ptr %91, align 8, !tbaa !18
  %93 = or i32 %92, 1
  store volatile i32 %93, ptr %91, align 8, !tbaa !18
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %94

94:                                               ; preds = %83, %76
  %95 = load ptr, ptr %3, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %95, i32 0, i32 0
  %97 = load ptr, ptr %96, align 8, !tbaa !20
  %98 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %97)
  store i32 %98, ptr %6, align 4, !tbaa !9
  %99 = load ptr, ptr %3, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %99, i32 0, i32 4
  %101 = load volatile i32, ptr %100, align 4, !tbaa !17
  %102 = zext i32 %101 to i64
  %103 = and i64 %102, 16
  %104 = icmp eq i64 %103, 0
  br i1 %104, label %105, label %458

105:                                              ; preds = %94
  %106 = load i32, ptr %6, align 4, !tbaa !9
  %107 = zext i32 %106 to i64
  %108 = icmp eq i64 %107, 0
  br i1 %108, label %109, label %458

109:                                              ; preds = %105
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %110, i32 0, i32 4
  %112 = load volatile i32, ptr %111, align 4, !tbaa !17
  %113 = zext i32 %112 to i64
  %114 = and i64 %113, -257
  %115 = or i64 %114, 2
  %116 = trunc i64 %115 to i32
  %117 = load ptr, ptr %3, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %117, i32 0, i32 4
  store volatile i32 %116, ptr %118, align 4, !tbaa !17
  %119 = load ptr, ptr %3, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !20
  %122 = call i32 @LL_ADC_IsEnabled(ptr noundef %121)
  %123 = zext i32 %122 to i64
  %124 = icmp eq i64 %123, 0
  br i1 %124, label %125, label %169

125:                                              ; preds = %109
  %126 = load ptr, ptr %3, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %126, i32 0, i32 0
  %128 = load ptr, ptr %127, align 8, !tbaa !20
  %129 = icmp eq ptr %128, inttoptr (i64 1073881088 to ptr)
  br i1 %129, label %135, label %130

130:                                              ; preds = %125
  %131 = load ptr, ptr %3, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %131, i32 0, i32 0
  %133 = load ptr, ptr %132, align 8, !tbaa !20
  %134 = icmp eq ptr %133, inttoptr (i64 1073881344 to ptr)
  br label %135

135:                                              ; preds = %130, %125
  %136 = phi i1 [ true, %125 ], [ %134, %130 ]
  %137 = zext i1 %136 to i64
  %138 = select i1 %136, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %139 = icmp eq ptr %138, inttoptr (i64 1073881856 to ptr)
  br i1 %139, label %140, label %144

140:                                              ; preds = %135
  %141 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %142 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %143 = or i32 %141, %142
  br label %146

144:                                              ; preds = %135
  %145 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %146

146:                                              ; preds = %144, %140
  %147 = phi i32 [ %143, %140 ], [ %145, %144 ]
  %148 = zext i32 %147 to i64
  %149 = icmp eq i64 %148, 0
  br i1 %149, label %150, label %168

150:                                              ; preds = %146
  %151 = load ptr, ptr %3, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %151, i32 0, i32 0
  %153 = load ptr, ptr %152, align 8, !tbaa !20
  %154 = icmp eq ptr %153, inttoptr (i64 1073881088 to ptr)
  br i1 %154, label %160, label %155

155:                                              ; preds = %150
  %156 = load ptr, ptr %3, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %156, i32 0, i32 0
  %158 = load ptr, ptr %157, align 8, !tbaa !20
  %159 = icmp eq ptr %158, inttoptr (i64 1073881344 to ptr)
  br label %160

160:                                              ; preds = %155, %150
  %161 = phi i1 [ true, %150 ], [ %159, %155 ]
  %162 = zext i1 %161 to i64
  %163 = select i1 %161, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %164 = load ptr, ptr %3, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %164, i32 0, i32 1
  %166 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %165, i32 0, i32 0
  %167 = load i32, ptr %166, align 8, !tbaa !23
  call void @LL_ADC_SetCommonClock(ptr noundef %163, i32 noundef %167)
  br label %168

168:                                              ; preds = %160, %146
  br label %169

169:                                              ; preds = %168, %109
  %170 = call i32 @HAL_GetREVID()
  %171 = icmp ugt i32 %170, 4099
  br i1 %171, label %172, label %205

172:                                              ; preds = %169
  %173 = load ptr, ptr %3, align 8, !tbaa !5
  %174 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %173, i32 0, i32 1
  %175 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %174, i32 0, i32 1
  %176 = load i32, ptr %175, align 4, !tbaa !24
  %177 = zext i32 %176 to i64
  %178 = icmp eq i64 16, %177
  br i1 %178, label %179, label %205

179:                                              ; preds = %172
  %180 = load ptr, ptr %3, align 8, !tbaa !5
  %181 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %180, i32 0, i32 1
  %182 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %181, i32 0, i32 5
  %183 = load i32, ptr %182, align 4, !tbaa !25
  %184 = shl i32 %183, 13
  %185 = load ptr, ptr %3, align 8, !tbaa !5
  %186 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %185, i32 0, i32 1
  %187 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %186, i32 0, i32 12
  %188 = load i32, ptr %187, align 8, !tbaa !26
  %189 = or i32 %184, %188
  %190 = load ptr, ptr %3, align 8, !tbaa !5
  %191 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %190, i32 0, i32 1
  %192 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %191, i32 0, i32 1
  %193 = load i32, ptr %192, align 4, !tbaa !24
  %194 = or i32 %189, %193
  %195 = zext i32 %194 to i64
  %196 = or i64 %195, 12
  %197 = load ptr, ptr %3, align 8, !tbaa !5
  %198 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %197, i32 0, i32 1
  %199 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %198, i32 0, i32 7
  %200 = load i32, ptr %199, align 4, !tbaa !16
  %201 = shl i32 %200, 16
  %202 = zext i32 %201 to i64
  %203 = or i64 %196, %202
  %204 = trunc i64 %203 to i32
  store i32 %204, ptr %5, align 4, !tbaa !9
  br label %227

205:                                              ; preds = %172, %169
  %206 = load ptr, ptr %3, align 8, !tbaa !5
  %207 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %206, i32 0, i32 1
  %208 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %207, i32 0, i32 5
  %209 = load i32, ptr %208, align 4, !tbaa !25
  %210 = shl i32 %209, 13
  %211 = load ptr, ptr %3, align 8, !tbaa !5
  %212 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %211, i32 0, i32 1
  %213 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %212, i32 0, i32 12
  %214 = load i32, ptr %213, align 8, !tbaa !26
  %215 = or i32 %210, %214
  %216 = load ptr, ptr %3, align 8, !tbaa !5
  %217 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %216, i32 0, i32 1
  %218 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %217, i32 0, i32 1
  %219 = load i32, ptr %218, align 4, !tbaa !24
  %220 = or i32 %215, %219
  %221 = load ptr, ptr %3, align 8, !tbaa !5
  %222 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %221, i32 0, i32 1
  %223 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %222, i32 0, i32 7
  %224 = load i32, ptr %223, align 4, !tbaa !16
  %225 = shl i32 %224, 16
  %226 = or i32 %220, %225
  store i32 %226, ptr %5, align 4, !tbaa !9
  br label %227

227:                                              ; preds = %205, %179
  %228 = load ptr, ptr %3, align 8, !tbaa !5
  %229 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %228, i32 0, i32 1
  %230 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %229, i32 0, i32 7
  %231 = load i32, ptr %230, align 4, !tbaa !16
  %232 = icmp eq i32 %231, 1
  br i1 %232, label %233, label %245

233:                                              ; preds = %227
  %234 = load ptr, ptr %3, align 8, !tbaa !5
  %235 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %234, i32 0, i32 1
  %236 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %235, i32 0, i32 8
  %237 = load i32, ptr %236, align 8, !tbaa !27
  %238 = zext i32 %237 to i64
  %239 = sub i64 %238, 1
  %240 = shl i64 %239, 17
  %241 = load i32, ptr %5, align 4, !tbaa !9
  %242 = zext i32 %241 to i64
  %243 = or i64 %242, %240
  %244 = trunc i64 %243 to i32
  store i32 %244, ptr %5, align 4, !tbaa !9
  br label %245

245:                                              ; preds = %233, %227
  %246 = load ptr, ptr %3, align 8, !tbaa !5
  %247 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %246, i32 0, i32 1
  %248 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %247, i32 0, i32 9
  %249 = load i32, ptr %248, align 4, !tbaa !28
  %250 = zext i32 %249 to i64
  %251 = icmp ne i64 %250, 0
  br i1 %251, label %252, label %269

252:                                              ; preds = %245
  %253 = load ptr, ptr %3, align 8, !tbaa !5
  %254 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %253, i32 0, i32 1
  %255 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %254, i32 0, i32 9
  %256 = load i32, ptr %255, align 4, !tbaa !28
  %257 = zext i32 %256 to i64
  %258 = and i64 %257, 992
  %259 = load ptr, ptr %3, align 8, !tbaa !5
  %260 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %259, i32 0, i32 1
  %261 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %260, i32 0, i32 10
  %262 = load i32, ptr %261, align 8, !tbaa !29
  %263 = zext i32 %262 to i64
  %264 = or i64 %258, %263
  %265 = load i32, ptr %5, align 4, !tbaa !9
  %266 = zext i32 %265 to i64
  %267 = or i64 %266, %264
  %268 = trunc i64 %267 to i32
  store i32 %268, ptr %5, align 4, !tbaa !9
  br label %269

269:                                              ; preds = %252, %245
  %270 = load ptr, ptr %3, align 8, !tbaa !5
  %271 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %270, i32 0, i32 0
  %272 = load ptr, ptr %271, align 8, !tbaa !20
  %273 = getelementptr inbounds %struct.ADC_TypeDef, ptr %272, i32 0, i32 3
  %274 = load volatile i32, ptr %273, align 4, !tbaa !30
  %275 = and i32 %274, -999421
  %276 = load i32, ptr %5, align 4, !tbaa !9
  %277 = or i32 %275, %276
  %278 = load ptr, ptr %3, align 8, !tbaa !5
  %279 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %278, i32 0, i32 0
  %280 = load ptr, ptr %279, align 8, !tbaa !20
  %281 = getelementptr inbounds %struct.ADC_TypeDef, ptr %280, i32 0, i32 3
  store volatile i32 %277, ptr %281, align 4, !tbaa !30
  %282 = load ptr, ptr %3, align 8, !tbaa !5
  %283 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %282, i32 0, i32 0
  %284 = load ptr, ptr %283, align 8, !tbaa !20
  %285 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %284)
  store i32 %285, ptr %8, align 4, !tbaa !9
  %286 = load ptr, ptr %3, align 8, !tbaa !5
  %287 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %286, i32 0, i32 0
  %288 = load ptr, ptr %287, align 8, !tbaa !20
  %289 = call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %288)
  store i32 %289, ptr %9, align 4, !tbaa !9
  %290 = load i32, ptr %8, align 4, !tbaa !9
  %291 = zext i32 %290 to i64
  %292 = icmp eq i64 %291, 0
  br i1 %292, label %293, label %412

293:                                              ; preds = %269
  %294 = load i32, ptr %9, align 4, !tbaa !9
  %295 = zext i32 %294 to i64
  %296 = icmp eq i64 %295, 0
  br i1 %296, label %297, label %412

297:                                              ; preds = %293
  %298 = load ptr, ptr %3, align 8, !tbaa !5
  %299 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %298, i32 0, i32 1
  %300 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %299, i32 0, i32 4
  %301 = load i32, ptr %300, align 8, !tbaa !32
  %302 = shl i32 %301, 14
  %303 = load ptr, ptr %3, align 8, !tbaa !5
  %304 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %303, i32 0, i32 1
  %305 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %304, i32 0, i32 11
  %306 = load i32, ptr %305, align 4, !tbaa !33
  %307 = or i32 %302, %306
  store i32 %307, ptr %5, align 4, !tbaa !9
  %308 = load ptr, ptr %3, align 8, !tbaa !5
  %309 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %308, i32 0, i32 0
  %310 = load ptr, ptr %309, align 8, !tbaa !20
  %311 = getelementptr inbounds %struct.ADC_TypeDef, ptr %310, i32 0, i32 3
  %312 = load volatile i32, ptr %311, align 4, !tbaa !30
  %313 = and i32 %312, -16388
  %314 = load i32, ptr %5, align 4, !tbaa !9
  %315 = or i32 %313, %314
  %316 = load ptr, ptr %3, align 8, !tbaa !5
  %317 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %316, i32 0, i32 0
  %318 = load ptr, ptr %317, align 8, !tbaa !20
  %319 = getelementptr inbounds %struct.ADC_TypeDef, ptr %318, i32 0, i32 3
  store volatile i32 %315, ptr %319, align 4, !tbaa !30
  %320 = load ptr, ptr %3, align 8, !tbaa !5
  %321 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %320, i32 0, i32 1
  %322 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %321, i32 0, i32 14
  %323 = load i32, ptr %322, align 8, !tbaa !34
  %324 = icmp eq i32 %323, 1
  br i1 %324, label %325, label %383

325:                                              ; preds = %297
  %326 = load ptr, ptr %3, align 8, !tbaa !5
  %327 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %326, i32 0, i32 1
  %328 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %327, i32 0, i32 9
  %329 = load i32, ptr %328, align 4, !tbaa !28
  %330 = zext i32 %329 to i64
  %331 = icmp eq i64 %330, 0
  br i1 %331, label %339, label %332

332:                                              ; preds = %325
  %333 = load ptr, ptr %3, align 8, !tbaa !5
  %334 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %333, i32 0, i32 1
  %335 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %334, i32 0, i32 10
  %336 = load i32, ptr %335, align 8, !tbaa !29
  %337 = zext i32 %336 to i64
  %338 = icmp eq i64 %337, 0
  br i1 %338, label %339, label %340

339:                                              ; preds = %332, %325
  br label %340

340:                                              ; preds = %339, %332
  %341 = load ptr, ptr %3, align 8, !tbaa !5
  %342 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %341, i32 0, i32 0
  %343 = load ptr, ptr %342, align 8, !tbaa !20
  %344 = getelementptr inbounds %struct.ADC_TypeDef, ptr %343, i32 0, i32 4
  %345 = load volatile i32, ptr %344, align 4, !tbaa !35
  %346 = and i32 %345, -67045346
  %347 = zext i32 %346 to i64
  %348 = load ptr, ptr %3, align 8, !tbaa !5
  %349 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %348, i32 0, i32 1
  %350 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %349, i32 0, i32 15
  %351 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %350, i32 0, i32 0
  %352 = load i32, ptr %351, align 4, !tbaa !36
  %353 = shl i32 %352, 16
  %354 = zext i32 %353 to i64
  %355 = or i64 1, %354
  %356 = load ptr, ptr %3, align 8, !tbaa !5
  %357 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %356, i32 0, i32 1
  %358 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %357, i32 0, i32 15
  %359 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %358, i32 0, i32 1
  %360 = load i32, ptr %359, align 4, !tbaa !37
  %361 = zext i32 %360 to i64
  %362 = or i64 %355, %361
  %363 = load ptr, ptr %3, align 8, !tbaa !5
  %364 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %363, i32 0, i32 1
  %365 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %364, i32 0, i32 15
  %366 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %365, i32 0, i32 2
  %367 = load i32, ptr %366, align 4, !tbaa !38
  %368 = zext i32 %367 to i64
  %369 = or i64 %362, %368
  %370 = load ptr, ptr %3, align 8, !tbaa !5
  %371 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %370, i32 0, i32 1
  %372 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %371, i32 0, i32 15
  %373 = getelementptr inbounds %struct.ADC_OversamplingTypeDef, ptr %372, i32 0, i32 3
  %374 = load i32, ptr %373, align 4, !tbaa !39
  %375 = zext i32 %374 to i64
  %376 = or i64 %369, %375
  %377 = or i64 %347, %376
  %378 = trunc i64 %377 to i32
  %379 = load ptr, ptr %3, align 8, !tbaa !5
  %380 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %379, i32 0, i32 0
  %381 = load ptr, ptr %380, align 8, !tbaa !20
  %382 = getelementptr inbounds %struct.ADC_TypeDef, ptr %381, i32 0, i32 4
  store volatile i32 %378, ptr %382, align 4, !tbaa !35
  br label %392

383:                                              ; preds = %297
  %384 = load ptr, ptr %3, align 8, !tbaa !5
  %385 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %384, i32 0, i32 0
  %386 = load ptr, ptr %385, align 8, !tbaa !20
  %387 = getelementptr inbounds %struct.ADC_TypeDef, ptr %386, i32 0, i32 4
  %388 = load volatile i32, ptr %387, align 4, !tbaa !35
  %389 = zext i32 %388 to i64
  %390 = and i64 %389, -2
  %391 = trunc i64 %390 to i32
  store volatile i32 %391, ptr %387, align 4, !tbaa !35
  br label %392

392:                                              ; preds = %383, %340
  %393 = load ptr, ptr %3, align 8, !tbaa !5
  %394 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %393, i32 0, i32 0
  %395 = load ptr, ptr %394, align 8, !tbaa !20
  %396 = getelementptr inbounds %struct.ADC_TypeDef, ptr %395, i32 0, i32 4
  %397 = load volatile i32, ptr %396, align 4, !tbaa !35
  %398 = zext i32 %397 to i64
  %399 = and i64 %398, -4026531841
  %400 = load ptr, ptr %3, align 8, !tbaa !5
  %401 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %400, i32 0, i32 1
  %402 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %401, i32 0, i32 13
  %403 = load i32, ptr %402, align 4, !tbaa !40
  %404 = zext i32 %403 to i64
  %405 = or i64 %399, %404
  %406 = trunc i64 %405 to i32
  %407 = load ptr, ptr %3, align 8, !tbaa !5
  %408 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %407, i32 0, i32 0
  %409 = load ptr, ptr %408, align 8, !tbaa !20
  %410 = getelementptr inbounds %struct.ADC_TypeDef, ptr %409, i32 0, i32 4
  store volatile i32 %406, ptr %410, align 4, !tbaa !35
  %411 = load ptr, ptr %3, align 8, !tbaa !5
  call void @ADC_ConfigureBoostMode(ptr noundef %411)
  br label %412

412:                                              ; preds = %392, %293, %269
  %413 = load ptr, ptr %3, align 8, !tbaa !5
  %414 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %413, i32 0, i32 1
  %415 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %414, i32 0, i32 2
  %416 = load i32, ptr %415, align 8, !tbaa !11
  %417 = zext i32 %416 to i64
  %418 = icmp eq i64 %417, 1
  br i1 %418, label %419, label %439

419:                                              ; preds = %412
  %420 = load ptr, ptr %3, align 8, !tbaa !5
  %421 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %420, i32 0, i32 0
  %422 = load ptr, ptr %421, align 8, !tbaa !20
  %423 = getelementptr inbounds %struct.ADC_TypeDef, ptr %422, i32 0, i32 12
  %424 = load volatile i32, ptr %423, align 4, !tbaa !41
  %425 = zext i32 %424 to i64
  %426 = and i64 %425, -16
  %427 = load ptr, ptr %3, align 8, !tbaa !5
  %428 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %427, i32 0, i32 1
  %429 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %428, i32 0, i32 6
  %430 = load i32, ptr %429, align 8, !tbaa !42
  %431 = sub i32 %430, 1
  %432 = zext i32 %431 to i64
  %433 = or i64 %426, %432
  %434 = trunc i64 %433 to i32
  %435 = load ptr, ptr %3, align 8, !tbaa !5
  %436 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %435, i32 0, i32 0
  %437 = load ptr, ptr %436, align 8, !tbaa !20
  %438 = getelementptr inbounds %struct.ADC_TypeDef, ptr %437, i32 0, i32 12
  store volatile i32 %434, ptr %438, align 4, !tbaa !41
  br label %448

439:                                              ; preds = %412
  %440 = load ptr, ptr %3, align 8, !tbaa !5
  %441 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %440, i32 0, i32 0
  %442 = load ptr, ptr %441, align 8, !tbaa !20
  %443 = getelementptr inbounds %struct.ADC_TypeDef, ptr %442, i32 0, i32 12
  %444 = load volatile i32, ptr %443, align 4, !tbaa !41
  %445 = zext i32 %444 to i64
  %446 = and i64 %445, -16
  %447 = trunc i64 %446 to i32
  store volatile i32 %447, ptr %443, align 4, !tbaa !41
  br label %448

448:                                              ; preds = %439, %419
  %449 = load ptr, ptr %3, align 8, !tbaa !5
  %450 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %449, i32 0, i32 4
  %451 = load volatile i32, ptr %450, align 4, !tbaa !17
  %452 = zext i32 %451 to i64
  %453 = and i64 %452, -3
  %454 = or i64 %453, 1
  %455 = trunc i64 %454 to i32
  %456 = load ptr, ptr %3, align 8, !tbaa !5
  %457 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %456, i32 0, i32 4
  store volatile i32 %455, ptr %457, align 4, !tbaa !17
  br label %465

458:                                              ; preds = %105, %94
  %459 = load ptr, ptr %3, align 8, !tbaa !5
  %460 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %459, i32 0, i32 4
  %461 = load volatile i32, ptr %460, align 4, !tbaa !17
  %462 = zext i32 %461 to i64
  %463 = or i64 %462, 16
  %464 = trunc i64 %463 to i32
  store volatile i32 %464, ptr %460, align 4, !tbaa !17
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %465

465:                                              ; preds = %458, %448
  %466 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %466, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %467

467:                                              ; preds = %465, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %468 = load i32, ptr %2, align 4
  ret i32 %468
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_MspInit(ptr noundef) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_DisableDeepPowerDown(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_EnableInternalRegulator(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_SetCommonClock(ptr noundef, i32 noundef) #2

declare i32 @HAL_GetREVID() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_ConfigureBoostMode(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 36}
!17 = !{!12, !10, i64 100}
!18 = !{!12, !10, i64 104}
!19 = !{!12, !10, i64 96}
!20 = !{!12, !6, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!12, !10, i64 8}
!24 = !{!12, !10, i64 12}
!25 = !{!12, !10, i64 28}
!26 = !{!12, !10, i64 56}
!27 = !{!12, !10, i64 40}
!28 = !{!12, !10, i64 44}
!29 = !{!12, !10, i64 48}
!30 = !{!31, !10, i64 12}
!31 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!32 = !{!12, !10, i64 24}
!33 = !{!12, !10, i64 52}
!34 = !{!12, !10, i64 64}
!35 = !{!31, !10, i64 16}
!36 = !{!12, !10, i64 68}
!37 = !{!12, !10, i64 72}
!38 = !{!12, !10, i64 76}
!39 = !{!12, !10, i64 80}
!40 = !{!12, !10, i64 60}
!41 = !{!31, !10, i64 48}
!42 = !{!12, !10, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_ADC_Init(ptr noundef %0) local_unnamed_addr #0 {
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
  store volatile i32 0, ptr %2, align 4, !tbaa !5
  %3 = icmp eq ptr %0, null
  br i1 %3, label %171, label %4

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = getelementptr inbounds i8, ptr %0, i64 16
  %7 = getelementptr inbounds i8, ptr %0, i64 100
  %8 = load volatile i32, ptr %7, align 4, !tbaa !9
  %9 = icmp eq i32 %8, 0
  br i1 %9, label %10, label %13

10:                                               ; preds = %4
  tail call void @HAL_ADC_MspInit(ptr noundef nonnull %0)
  %11 = getelementptr inbounds i8, ptr %0, i64 104
  store volatile i32 0, ptr %11, align 8, !tbaa !15
  %12 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 0, ptr %12, align 8, !tbaa !16
  br label %13

13:                                               ; preds = %10, %4
  %14 = load ptr, ptr %0, align 8, !tbaa !17
  %15 = tail call i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef %14)
  %.not89 = icmp eq i32 %15, 0
  br i1 %.not89, label %18, label %16

16:                                               ; preds = %13
  %17 = load ptr, ptr %0, align 8, !tbaa !17
  tail call void @LL_ADC_DisableDeepPowerDown(ptr noundef %17)
  br label %18

18:                                               ; preds = %16, %13
  %19 = load ptr, ptr %0, align 8, !tbaa !17
  %20 = tail call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %19)
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %.loopexit

22:                                               ; preds = %18
  %23 = load ptr, ptr %0, align 8, !tbaa !17
  tail call void @LL_ADC_EnableInternalRegulator(ptr noundef %23)
  %24 = load i32, ptr @SystemCoreClock, align 4, !tbaa !5
  %25 = udiv i32 %24, 200000
  store volatile i32 %25, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.93 = load volatile i32, ptr %2, align 4, !tbaa !5
  %.not9094 = icmp eq i32 %.0..0..0..0.93, 0
  br i1 %.not9094, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %22, %.lr.ph
  %.0..0..0..0.7 = load volatile i32, ptr %2, align 4, !tbaa !5
  %26 = add i32 %.0..0..0..0.7, -1
  store volatile i32 %26, ptr %2, align 4, !tbaa !5
  %.0..0..0..0. = load volatile i32, ptr %2, align 4, !tbaa !5
  %.not90 = icmp eq i32 %.0..0..0..0., 0
  br i1 %.not90, label %.loopexit, label %.lr.ph, !llvm.loop !18

.loopexit:                                        ; preds = %.lr.ph, %22, %18
  %27 = load ptr, ptr %0, align 8, !tbaa !17
  %28 = tail call i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef %27)
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %36

30:                                               ; preds = %.loopexit
  %31 = load volatile i32, ptr %7, align 4, !tbaa !9
  %32 = or i32 %31, 16
  store volatile i32 %32, ptr %7, align 4, !tbaa !9
  %33 = getelementptr inbounds i8, ptr %0, i64 104
  %34 = load volatile i32, ptr %33, align 8, !tbaa !15
  %35 = or i32 %34, 1
  store volatile i32 %35, ptr %33, align 8, !tbaa !15
  br label %36

36:                                               ; preds = %30, %.loopexit
  %.082 = phi i32 [ 1, %30 ], [ 0, %.loopexit ]
  %37 = load ptr, ptr %0, align 8, !tbaa !17
  %38 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %37)
  %39 = load volatile i32, ptr %7, align 4, !tbaa !9
  %40 = and i32 %39, 16
  %41 = icmp eq i32 %40, 0
  %42 = icmp eq i32 %38, 0
  %or.cond = select i1 %41, i1 %42, i1 false
  %43 = load volatile i32, ptr %7, align 4, !tbaa !9
  br i1 %or.cond, label %44, label %169

44:                                               ; preds = %36
  %45 = and i32 %43, -259
  %46 = or disjoint i32 %45, 2
  store volatile i32 %46, ptr %7, align 4, !tbaa !9
  %47 = load ptr, ptr %0, align 8, !tbaa !17
  %48 = tail call i32 @LL_ADC_IsEnabled(ptr noundef %47)
  %49 = icmp eq i32 %48, 0
  br i1 %49, label %50, label %67

50:                                               ; preds = %44
  %51 = load ptr, ptr %0, align 8, !tbaa !17
  %magicptr = ptrtoint ptr %51 to i64
  switch i64 %magicptr, label %56 [
    i64 1073881344, label %52
    i64 1073881088, label %52
  ]

52:                                               ; preds = %50, %50
  %53 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %54 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %55 = or i32 %54, %53
  br label %58

56:                                               ; preds = %50
  %57 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %58

58:                                               ; preds = %56, %52
  %59 = phi i32 [ %55, %52 ], [ %57, %56 ]
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %67

61:                                               ; preds = %58
  %62 = load ptr, ptr %0, align 8, !tbaa !17
  %63 = icmp eq ptr %62, inttoptr (i64 1073881088 to ptr)
  %64 = icmp eq ptr %62, inttoptr (i64 1073881344 to ptr)
  %spec.select92 = or i1 %63, %64
  %65 = select i1 %spec.select92, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %66 = load i32, ptr %5, align 8, !tbaa !20
  tail call void @LL_ADC_SetCommonClock(ptr noundef nonnull %65, i32 noundef %66)
  br label %67

67:                                               ; preds = %58, %61, %44
  %68 = tail call i32 @HAL_GetREVID() #4
  %69 = icmp ugt i32 %68, 4099
  %70 = getelementptr inbounds i8, ptr %0, i64 12
  %71 = load i32, ptr %70, align 4, !tbaa !21
  %72 = icmp eq i32 %71, 16
  %or.cond95 = select i1 %69, i1 %72, i1 false
  %73 = getelementptr inbounds i8, ptr %0, i64 28
  %74 = load i32, ptr %73, align 4, !tbaa !22
  %75 = shl i32 %74, 13
  %76 = getelementptr inbounds i8, ptr %0, i64 56
  %77 = load i32, ptr %76, align 8, !tbaa !23
  %78 = getelementptr inbounds i8, ptr %0, i64 36
  %79 = load i32, ptr %78, align 4, !tbaa !24
  %80 = shl i32 %79, 16
  %. = select i1 %or.cond95, i32 %75, i32 %77
  %.103 = select i1 %or.cond95, i32 %77, i32 %75
  %.104 = select i1 %or.cond95, i32 28, i32 %71
  %81 = or i32 %., %80
  %82 = or i32 %81, %.103
  %83 = or i32 %82, %.104
  %84 = icmp eq i32 %79, 1
  br i1 %84, label %85, label %91

85:                                               ; preds = %67
  %86 = getelementptr inbounds i8, ptr %0, i64 40
  %87 = load i32, ptr %86, align 8, !tbaa !25
  %88 = shl i32 %87, 17
  %89 = add i32 %88, -131072
  %90 = or i32 %89, %83
  br label %91

91:                                               ; preds = %85, %67
  %.184 = phi i32 [ %90, %85 ], [ %83, %67 ]
  %92 = getelementptr inbounds i8, ptr %0, i64 44
  %93 = load i32, ptr %92, align 4, !tbaa !26
  %.not91 = icmp eq i32 %93, 0
  br i1 %.not91, label %100, label %94

94:                                               ; preds = %91
  %95 = and i32 %93, 992
  %96 = getelementptr inbounds i8, ptr %0, i64 48
  %97 = load i32, ptr %96, align 8, !tbaa !27
  %98 = or i32 %95, %97
  %99 = or i32 %98, %.184
  br label %100

100:                                              ; preds = %94, %91
  %.2 = phi i32 [ %99, %94 ], [ %.184, %91 ]
  %101 = load ptr, ptr %0, align 8, !tbaa !17
  %102 = getelementptr inbounds i8, ptr %101, i64 12
  %103 = load volatile i32, ptr %102, align 4, !tbaa !28
  %104 = and i32 %103, -999421
  %105 = or i32 %104, %.2
  store volatile i32 %105, ptr %102, align 4, !tbaa !28
  %106 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %101)
  %107 = load ptr, ptr %0, align 8, !tbaa !17
  %108 = tail call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %107)
  %109 = icmp eq i32 %106, 0
  %110 = icmp eq i32 %108, 0
  %or.cond5 = select i1 %109, i1 %110, i1 false
  br i1 %or.cond5, label %111, label %153

111:                                              ; preds = %100
  %112 = getelementptr inbounds i8, ptr %0, i64 24
  %113 = load i32, ptr %112, align 8, !tbaa !30
  %114 = shl i32 %113, 14
  %115 = getelementptr inbounds i8, ptr %0, i64 52
  %116 = load i32, ptr %115, align 4, !tbaa !31
  %117 = or i32 %114, %116
  %118 = load ptr, ptr %0, align 8, !tbaa !17
  %119 = getelementptr inbounds i8, ptr %118, i64 12
  %120 = load volatile i32, ptr %119, align 4, !tbaa !28
  %121 = and i32 %120, -16388
  %122 = or i32 %117, %121
  store volatile i32 %122, ptr %119, align 4, !tbaa !28
  %123 = getelementptr inbounds i8, ptr %0, i64 64
  %124 = load i32, ptr %123, align 8, !tbaa !32
  %125 = icmp eq i32 %124, 1
  %126 = getelementptr inbounds i8, ptr %118, i64 16
  %127 = load volatile i32, ptr %126, align 4, !tbaa !33
  br i1 %125, label %128, label %144

128:                                              ; preds = %111
  %129 = and i32 %127, -67045346
  %130 = getelementptr inbounds i8, ptr %0, i64 68
  %131 = load i32, ptr %130, align 4, !tbaa !34
  %132 = shl i32 %131, 16
  %133 = getelementptr inbounds i8, ptr %0, i64 72
  %134 = load i32, ptr %133, align 4, !tbaa !35
  %135 = getelementptr inbounds i8, ptr %0, i64 76
  %136 = load i32, ptr %135, align 4, !tbaa !36
  %137 = getelementptr inbounds i8, ptr %0, i64 80
  %138 = load i32, ptr %137, align 4, !tbaa !37
  %139 = or i32 %129, %134
  %140 = or i32 %139, %132
  %141 = or i32 %140, %136
  %142 = or i32 %141, %138
  %143 = or i32 %142, 1
  br label %146

144:                                              ; preds = %111
  %145 = and i32 %127, -2
  br label %146

146:                                              ; preds = %144, %128
  %.sink = phi i32 [ %145, %144 ], [ %143, %128 ]
  store volatile i32 %.sink, ptr %126, align 4, !tbaa !33
  %147 = getelementptr inbounds i8, ptr %118, i64 16
  %148 = load volatile i32, ptr %147, align 4, !tbaa !33
  %149 = and i32 %148, 268435455
  %150 = getelementptr inbounds i8, ptr %0, i64 60
  %151 = load i32, ptr %150, align 4, !tbaa !38
  %152 = or i32 %149, %151
  store volatile i32 %152, ptr %147, align 4, !tbaa !33
  tail call void @ADC_ConfigureBoostMode(ptr noundef nonnull %0)
  br label %153

153:                                              ; preds = %146, %100
  %154 = load i32, ptr %6, align 8, !tbaa !39
  %155 = icmp eq i32 %154, 1
  %156 = load ptr, ptr %0, align 8, !tbaa !17
  %157 = getelementptr inbounds i8, ptr %156, i64 48
  %158 = load volatile i32, ptr %157, align 4, !tbaa !40
  %159 = and i32 %158, -16
  br i1 %155, label %160, label %165

160:                                              ; preds = %153
  %161 = getelementptr inbounds i8, ptr %0, i64 32
  %162 = load i32, ptr %161, align 8, !tbaa !41
  %163 = add i32 %162, -1
  %164 = or i32 %163, %159
  br label %165

165:                                              ; preds = %153, %160
  %.sink96 = phi i32 [ %164, %160 ], [ %159, %153 ]
  store volatile i32 %.sink96, ptr %157, align 4, !tbaa !40
  %166 = load volatile i32, ptr %7, align 4, !tbaa !9
  %167 = and i32 %166, -4
  %168 = or disjoint i32 %167, 1
  br label %.sink.split

169:                                              ; preds = %36
  %170 = or i32 %43, 16
  br label %.sink.split

.sink.split:                                      ; preds = %169, %165
  %.sink97 = phi i32 [ %168, %165 ], [ %170, %169 ]
  %.0.ph = phi i32 [ %.082, %165 ], [ 1, %169 ]
  store volatile i32 %.sink97, ptr %7, align 4, !tbaa !9
  br label %171

171:                                              ; preds = %.sink.split, %1
  %.0 = phi i32 [ 1, %1 ], [ %.0.ph, %.sink.split ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
  ret i32 %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_MspInit(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDeepPowerDownEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_DisableDeepPowerDown(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsInternalRegulatorEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_EnableInternalRegulator(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_SetCommonClock(ptr noundef, i32 noundef) local_unnamed_addr #2

declare i32 @HAL_GetREVID() local_unnamed_addr #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_ConfigureBoostMode(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 100}
!10 = !{!"", !11, i64 0, !12, i64 8, !11, i64 88, !6, i64 96, !6, i64 100, !6, i64 104, !14, i64 108}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !13, i64 60}
!13 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12}
!14 = !{!"", !6, i64 0, !6, i64 4}
!15 = !{!10, !6, i64 104}
!16 = !{!10, !6, i64 96}
!17 = !{!10, !11, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!10, !6, i64 8}
!21 = !{!10, !6, i64 12}
!22 = !{!10, !6, i64 28}
!23 = !{!10, !6, i64 56}
!24 = !{!10, !6, i64 36}
!25 = !{!10, !6, i64 40}
!26 = !{!10, !6, i64 44}
!27 = !{!10, !6, i64 48}
!28 = !{!29, !6, i64 12}
!29 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !7, i64 80, !6, i64 96, !6, i64 100, !6, i64 104, !6, i64 108, !7, i64 112, !6, i64 128, !6, i64 132, !6, i64 136, !6, i64 140, !7, i64 144, !6, i64 160, !6, i64 164, !6, i64 168, !6, i64 172, !6, i64 176, !6, i64 180, !6, i64 184, !6, i64 188, !6, i64 192, !6, i64 196, !6, i64 200}
!30 = !{!10, !6, i64 24}
!31 = !{!10, !6, i64 52}
!32 = !{!10, !6, i64 64}
!33 = !{!29, !6, i64 16}
!34 = !{!10, !6, i64 68}
!35 = !{!10, !6, i64 72}
!36 = !{!10, !6, i64 76}
!37 = !{!10, !6, i64 80}
!38 = !{!10, !6, i64 60}
!39 = !{!10, !6, i64 16}
!40 = !{!29, !6, i64 48}
!41 = !{!10, !6, i64 32}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass