; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SWPMI_HandleTypeDef = type { ptr, %struct.SWPMI_InitTypeDef, ptr, i32, i32, ptr, i32, i32, ptr, ptr, i32, i32, i32 }
%struct.SWPMI_InitTypeDef = type { i32, i32, i32, i32 }
%struct.SWPMI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SWPMI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  %12 = icmp eq ptr %11, null
  br i1 %12, label %17, label %13

13:                                               ; preds = %3
  %14 = load i16, ptr %7, align 2, !tbaa !9
  %15 = zext i16 %14 to i32
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %13, %3
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %135

18:                                               ; preds = %13
  br label %19

19:                                               ; preds = %18
  %20 = load ptr, ptr %5, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %20, i32 0, i32 10
  %22 = load i32, ptr %21, align 8, !tbaa !13
  %23 = icmp eq i32 %22, 1
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  store i32 2, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %137

25:                                               ; preds = %19
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %26, i32 0, i32 10
  store i32 1, ptr %27, align 8, !tbaa !13
  br label %28

28:                                               ; preds = %25
  br label %29

29:                                               ; preds = %28
  br label %30

30:                                               ; preds = %29
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %31, i32 0, i32 11
  %33 = load volatile i32, ptr %32, align 4, !tbaa !16
  store i32 %33, ptr %9, align 4, !tbaa !11
  %34 = load i32, ptr %9, align 4, !tbaa !11
  %35 = icmp eq i32 %34, 1
  br i1 %35, label %39, label %36

36:                                               ; preds = %30
  %37 = load i32, ptr %9, align 4, !tbaa !11
  %38 = icmp eq i32 %37, 18
  br i1 %38, label %39, label %128

39:                                               ; preds = %36, %30
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %41, i32 0, i32 5
  store ptr %40, ptr %42, align 8, !tbaa !17
  %43 = load i16, ptr %7, align 2, !tbaa !9
  %44 = zext i16 %43 to i32
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %45, i32 0, i32 6
  store i32 %44, ptr %46, align 8, !tbaa !18
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %47, i32 0, i32 12
  store volatile i32 0, ptr %48, align 8, !tbaa !19
  %49 = load i32, ptr %9, align 4, !tbaa !11
  %50 = icmp eq i32 %49, 1
  br i1 %50, label %51, label %62

51:                                               ; preds = %39
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %52, i32 0, i32 11
  store volatile i32 34, ptr %53, align 4, !tbaa !16
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !20
  %57 = getelementptr inbounds %struct.SWPMI_TypeDef, ptr %56, i32 0, i32 0
  %58 = load volatile i32, ptr %57, align 4, !tbaa !21
  %59 = zext i32 %58 to i64
  %60 = or i64 %59, 32
  %61 = trunc i64 %60 to i32
  store volatile i32 %61, ptr %57, align 4, !tbaa !21
  br label %65

62:                                               ; preds = %39
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %63, i32 0, i32 11
  store volatile i32 50, ptr %64, align 4, !tbaa !16
  br label %65

65:                                               ; preds = %62, %51
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %66, i32 0, i32 9
  %68 = load ptr, ptr %67, align 8, !tbaa !23
  %69 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %68, i32 0, i32 5
  store ptr @SWPMI_DMAReceiveCplt, ptr %69, align 8, !tbaa !24
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %70, i32 0, i32 9
  %72 = load ptr, ptr %71, align 8, !tbaa !23
  %73 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %72, i32 0, i32 6
  store ptr @SWPMI_DMARxHalfCplt, ptr %73, align 8, !tbaa !27
  %74 = load ptr, ptr %5, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %74, i32 0, i32 9
  %76 = load ptr, ptr %75, align 8, !tbaa !23
  %77 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %76, i32 0, i32 9
  store ptr @SWPMI_DMAError, ptr %77, align 8, !tbaa !28
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %78, i32 0, i32 9
  %80 = load ptr, ptr %79, align 8, !tbaa !23
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !20
  %84 = getelementptr inbounds %struct.SWPMI_TypeDef, ptr %83, i32 0, i32 8
  %85 = ptrtoint ptr %84 to i32
  %86 = load ptr, ptr %5, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %86, i32 0, i32 5
  %88 = load ptr, ptr %87, align 8, !tbaa !17
  %89 = ptrtoint ptr %88 to i32
  %90 = load i16, ptr %7, align 2, !tbaa !9
  %91 = zext i16 %90 to i32
  %92 = call i32 @HAL_DMA_Start_IT(ptr noundef %80, i32 noundef %85, i32 noundef %89, i32 noundef %91)
  %93 = icmp ne i32 %92, 0
  br i1 %93, label %94, label %105

94:                                               ; preds = %65
  %95 = load i32, ptr %9, align 4, !tbaa !11
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %96, i32 0, i32 11
  store volatile i32 %95, ptr %97, align 4, !tbaa !16
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %98, i32 0, i32 12
  store volatile i32 16, ptr %99, align 8, !tbaa !19
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %100

100:                                              ; preds = %94
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %101, i32 0, i32 10
  store i32 0, ptr %102, align 8, !tbaa !13
  br label %103

103:                                              ; preds = %100
  br label %104

104:                                              ; preds = %103
  br label %127

105:                                              ; preds = %65
  br label %106

106:                                              ; preds = %105
  %107 = load ptr, ptr %5, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %107, i32 0, i32 10
  store i32 0, ptr %108, align 8, !tbaa !13
  br label %109

109:                                              ; preds = %106
  br label %110

110:                                              ; preds = %109
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %111, i32 0, i32 0
  %113 = load ptr, ptr %112, align 8, !tbaa !20
  %114 = getelementptr inbounds %struct.SWPMI_TypeDef, ptr %113, i32 0, i32 5
  %115 = load volatile i32, ptr %114, align 4, !tbaa !29
  %116 = zext i32 %115 to i64
  %117 = or i64 %116, 12
  %118 = trunc i64 %117 to i32
  store volatile i32 %118, ptr %114, align 4, !tbaa !29
  %119 = load ptr, ptr %5, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !20
  %122 = getelementptr inbounds %struct.SWPMI_TypeDef, ptr %121, i32 0, i32 0
  %123 = load volatile i32, ptr %122, align 4, !tbaa !21
  %124 = zext i32 %123 to i64
  %125 = or i64 %124, 1
  %126 = trunc i64 %125 to i32
  store volatile i32 %126, ptr %122, align 4, !tbaa !21
  br label %127

127:                                              ; preds = %110, %104
  br label %134

128:                                              ; preds = %36
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %129

129:                                              ; preds = %128
  %130 = load ptr, ptr %5, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.SWPMI_HandleTypeDef, ptr %130, i32 0, i32 10
  store i32 0, ptr %131, align 8, !tbaa !13
  br label %132

132:                                              ; preds = %129
  br label %133

133:                                              ; preds = %132
  br label %134

134:                                              ; preds = %133, %127
  br label %135

135:                                              ; preds = %134, %17
  %136 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %136, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %137

137:                                              ; preds = %135, %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %138 = load i32, ptr %4, align 4
  ret i32 %138
}

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMAReceiveCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMARxHalfCplt(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 72}
!14 = !{!"", !6, i64 0, !15, i64 8, !6, i64 24, !12, i64 32, !12, i64 36, !6, i64 40, !12, i64 48, !12, i64 52, !6, i64 56, !6, i64 64, !12, i64 72, !12, i64 76, !12, i64 80}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!16 = !{!14, !12, i64 76}
!17 = !{!14, !6, i64 40}
!18 = !{!14, !12, i64 48}
!19 = !{!14, !12, i64 80}
!20 = !{!14, !6, i64 0}
!21 = !{!22, !12, i64 0}
!22 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36}
!23 = !{!14, !6, i64 64}
!24 = !{!25, !6, i64 72}
!25 = !{!"__DMA_HandleTypeDef", !6, i64 0, !26, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!26 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!27 = !{!25, !6, i64 80}
!28 = !{!25, !6, i64 104}
!29 = !{!22, !12, i64 20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SWPMI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %1, null
  %5 = zext i16 %2 to i32
  %6 = icmp eq i16 %2, 0
  %or.cond = or i1 %4, %6
  br i1 %or.cond, label %46, label %7

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 72
  %9 = load i32, ptr %8, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %46, label %11

11:                                               ; preds = %7
  store i32 1, ptr %8, align 8, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %0, i64 76
  %13 = load volatile i32, ptr %12, align 4, !tbaa !12
  switch i32 %13, label %45 [
    i32 18, label %14
    i32 1, label %14
  ]

14:                                               ; preds = %11, %11
  %15 = icmp eq i32 %13, 1
  %16 = getelementptr inbounds i8, ptr %0, i64 40
  store ptr %1, ptr %16, align 8, !tbaa !13
  %17 = getelementptr inbounds i8, ptr %0, i64 48
  store i32 %5, ptr %17, align 8, !tbaa !14
  %18 = getelementptr inbounds i8, ptr %0, i64 80
  store volatile i32 0, ptr %18, align 8, !tbaa !15
  br i1 %15, label %19, label %23

19:                                               ; preds = %14
  store volatile i32 34, ptr %12, align 4, !tbaa !12
  %20 = load ptr, ptr %0, align 8, !tbaa !16
  %21 = load volatile i32, ptr %20, align 4, !tbaa !17
  %22 = or i32 %21, 32
  store volatile i32 %22, ptr %20, align 4, !tbaa !17
  br label %24

23:                                               ; preds = %14
  store volatile i32 50, ptr %12, align 4, !tbaa !12
  %.pre = load ptr, ptr %0, align 8, !tbaa !16
  br label %24

24:                                               ; preds = %23, %19
  %25 = phi ptr [ %.pre, %23 ], [ %20, %19 ]
  %26 = getelementptr inbounds i8, ptr %0, i64 64
  %27 = load ptr, ptr %26, align 8, !tbaa !19
  %28 = getelementptr inbounds i8, ptr %27, i64 72
  store ptr @SWPMI_DMAReceiveCplt, ptr %28, align 8, !tbaa !20
  %29 = getelementptr inbounds i8, ptr %27, i64 80
  store ptr @SWPMI_DMARxHalfCplt, ptr %29, align 8, !tbaa !23
  %30 = getelementptr inbounds i8, ptr %27, i64 104
  store ptr @SWPMI_DMAError, ptr %30, align 8, !tbaa !24
  %31 = getelementptr inbounds i8, ptr %25, i64 32
  %32 = ptrtoint ptr %31 to i64
  %33 = trunc i64 %32 to i32
  %34 = ptrtoint ptr %1 to i64
  %35 = trunc i64 %34 to i32
  %36 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %27, i32 noundef %33, i32 noundef %35, i32 noundef %5) #2
  %.not = icmp eq i32 %36, 0
  br i1 %.not, label %38, label %37

37:                                               ; preds = %24
  store volatile i32 %13, ptr %12, align 4, !tbaa !12
  store volatile i32 16, ptr %18, align 8, !tbaa !15
  store i32 0, ptr %8, align 8, !tbaa !5
  br label %46

38:                                               ; preds = %24
  store i32 0, ptr %8, align 8, !tbaa !5
  %39 = load ptr, ptr %0, align 8, !tbaa !16
  %40 = getelementptr inbounds i8, ptr %39, i64 20
  %41 = load volatile i32, ptr %40, align 4, !tbaa !25
  %42 = or i32 %41, 12
  store volatile i32 %42, ptr %40, align 4, !tbaa !25
  %43 = load volatile i32, ptr %39, align 4, !tbaa !17
  %44 = or i32 %43, 1
  store volatile i32 %44, ptr %39, align 4, !tbaa !17
  br label %46

45:                                               ; preds = %11
  store i32 0, ptr %8, align 8, !tbaa !5
  br label %46

46:                                               ; preds = %37, %38, %45, %3, %7
  %.0 = phi i32 [ 2, %7 ], [ 1, %37 ], [ 0, %38 ], [ 2, %45 ], [ 1, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMAReceiveCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SWPMI_DMARxHalfCplt(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 72}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 24, !11, i64 32, !11, i64 36, !7, i64 40, !11, i64 48, !11, i64 52, !7, i64 56, !7, i64 64, !11, i64 72, !11, i64 76, !11, i64 80}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !7, i64 40}
!14 = !{!6, !11, i64 48}
!15 = !{!6, !11, i64 80}
!16 = !{!6, !7, i64 0}
!17 = !{!18, !11, i64 0}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!19 = !{!6, !7, i64 64}
!20 = !{!21, !7, i64 72}
!21 = !{!"__DMA_HandleTypeDef", !7, i64 0, !22, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!22 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!23 = !{!21, !7, i64 80}
!24 = !{!21, !7, i64 104}
!25 = !{!18, !11, i64 20}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass