; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ProgramLineEvent)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.LTDC_HandleTypeDef = type { ptr, %struct.LTDC_InitTypeDef, [2 x %struct.LTDC_LayerCfgTypeDef], i32, i32, i32 }
%struct.LTDC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.LTDC_ColorTypeDef }
%struct.LTDC_ColorTypeDef = type { i8, i8, i8, i8 }
%struct.LTDC_LayerCfgTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.LTDC_ColorTypeDef }
%struct.LTDC_TypeDef = type { [2 x i32], i32, i32, i32, i32, i32, [2 x i32], i32, [1 x i32], i32, [1 x i32], i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_LTDC_ProgramLineEvent(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  br label %6

6:                                                ; preds = %2
  %7 = load ptr, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %7, i32 0, i32 3
  %9 = load i32, ptr %8, align 4, !tbaa !11
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %12

11:                                               ; preds = %6
  store i32 2, ptr %3, align 4
  br label %42

12:                                               ; preds = %6
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %13, i32 0, i32 3
  store i32 1, ptr %14, align 4, !tbaa !11
  br label %15

15:                                               ; preds = %12
  br label %16

16:                                               ; preds = %15
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %17, i32 0, i32 4
  store volatile i32 2, ptr %18, align 8, !tbaa !15
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %19, i32 0, i32 0
  %21 = load ptr, ptr %20, align 8, !tbaa !16
  %22 = getelementptr inbounds %struct.LTDC_TypeDef, ptr %21, i32 0, i32 11
  %23 = load volatile i32, ptr %22, align 4, !tbaa !17
  %24 = zext i32 %23 to i64
  %25 = and i64 %24, -2
  %26 = trunc i64 %25 to i32
  store volatile i32 %26, ptr %22, align 4, !tbaa !17
  %27 = load i32, ptr %5, align 4, !tbaa !9
  store volatile i32 %27, ptr getelementptr inbounds (%struct.LTDC_TypeDef, ptr inttoptr (i64 1342181376 to ptr), i32 0, i32 14), align 4, !tbaa !19
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %28, i32 0, i32 0
  %30 = load ptr, ptr %29, align 8, !tbaa !16
  %31 = getelementptr inbounds %struct.LTDC_TypeDef, ptr %30, i32 0, i32 11
  %32 = load volatile i32, ptr %31, align 4, !tbaa !17
  %33 = zext i32 %32 to i64
  %34 = or i64 %33, 1
  %35 = trunc i64 %34 to i32
  store volatile i32 %35, ptr %31, align 4, !tbaa !17
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %36, i32 0, i32 4
  store volatile i32 1, ptr %37, align 8, !tbaa !15
  br label %38

38:                                               ; preds = %16
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %39, i32 0, i32 3
  store i32 0, ptr %40, align 4, !tbaa !11
  br label %41

41:                                               ; preds = %38
  store i32 0, ptr %3, align 4
  br label %42

42:                                               ; preds = %41, %11
  %43 = load i32, ptr %3, align 4
  ret i32 %43
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 164}
!12 = !{!"", !6, i64 0, !13, i64 8, !7, i64 60, !10, i64 164, !10, i64 168, !10, i64 172}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !14, i64 48}
!14 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!15 = !{!12, !10, i64 168}
!16 = !{!12, !6, i64 0}
!17 = !{!18, !10, i64 52}
!18 = !{!"", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !7, i64 28, !10, i64 36, !7, i64 40, !10, i64 44, !7, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72}
!19 = !{!18, !10, i64 64}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_LTDC_ProgramLineEvent(ptr noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 164
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %14, label %6

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 2, ptr %7, align 8, !tbaa !13
  %8 = load ptr, ptr %0, align 8, !tbaa !14
  %9 = getelementptr inbounds i8, ptr %8, i64 52
  %10 = load volatile i32, ptr %9, align 4, !tbaa !15
  %11 = and i32 %10, -2
  store volatile i32 %11, ptr %9, align 4, !tbaa !15
  store volatile i32 %1, ptr inttoptr (i64 1342181440 to ptr), align 64, !tbaa !17
  %12 = load volatile i32, ptr %9, align 4, !tbaa !15
  %13 = or i32 %12, 1
  store volatile i32 %13, ptr %9, align 4, !tbaa !15
  store volatile i32 1, ptr %7, align 8, !tbaa !13
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %14

14:                                               ; preds = %2, %6
  %.0 = phi i32 [ 0, %6 ], [ 2, %2 ]
  ret i32 %.0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 164}
!6 = !{!"", !7, i64 0, !10, i64 8, !8, i64 60, !11, i64 164, !11, i64 168, !11, i64 172}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !12, i64 48}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !8, i64 0, !8, i64 1, !8, i64 2, !8, i64 3}
!13 = !{!6, !11, i64 168}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !11, i64 52}
!16 = !{!"", !8, i64 0, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !8, i64 28, !11, i64 36, !8, i64 40, !11, i64 44, !8, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72}
!17 = !{!16, !11, i64 64}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass