; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (InjectedPollForConversion)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_InjectedPollForConversion(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %14, i32 0, i32 0
  %16 = load ptr, ptr %15, align 8, !tbaa !11
  %17 = icmp eq ptr %16, inttoptr (i64 1073881088 to ptr)
  br i1 %17, label %23, label %18

18:                                               ; preds = %2
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %19, i32 0, i32 0
  %21 = load ptr, ptr %20, align 8, !tbaa !11
  %22 = icmp eq ptr %21, inttoptr (i64 1073881344 to ptr)
  br label %23

23:                                               ; preds = %18, %2
  %24 = phi i1 [ true, %2 ], [ %22, %18 ]
  %25 = zext i1 %24 to i64
  %26 = select i1 %24, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %27 = call i32 @LL_ADC_GetMultimode(ptr noundef %26)
  store i32 %27, ptr %12, align 4, !tbaa !9
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %28, i32 0, i32 1
  %30 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %29, i32 0, i32 3
  %31 = load i32, ptr %30, align 4, !tbaa !16
  %32 = zext i32 %31 to i64
  %33 = icmp eq i64 %32, 8
  br i1 %33, label %34, label %35

34:                                               ; preds = %23
  store i32 64, ptr %7, align 4, !tbaa !9
  br label %36

35:                                               ; preds = %23
  store i32 32, ptr %7, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %35, %34
  %37 = call i32 @HAL_GetTick()
  store i32 %37, ptr %6, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %74, %36
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 0
  %41 = load ptr, ptr %40, align 8, !tbaa !11
  %42 = getelementptr inbounds %struct.ADC_TypeDef, ptr %41, i32 0, i32 0
  %43 = load volatile i32, ptr %42, align 4, !tbaa !17
  %44 = load i32, ptr %7, align 4, !tbaa !9
  %45 = and i32 %43, %44
  %46 = zext i32 %45 to i64
  %47 = icmp eq i64 %46, 0
  br i1 %47, label %48, label %75

48:                                               ; preds = %38
  %49 = load i32, ptr %5, align 4, !tbaa !9
  %50 = icmp ne i32 %49, -1
  br i1 %50, label %51, label %74

51:                                               ; preds = %48
  %52 = call i32 @HAL_GetTick()
  %53 = load i32, ptr %6, align 4, !tbaa !9
  %54 = sub i32 %52, %53
  %55 = load i32, ptr %5, align 4, !tbaa !9
  %56 = icmp ugt i32 %54, %55
  br i1 %56, label %61, label %57

57:                                               ; preds = %51
  %58 = load i32, ptr %5, align 4, !tbaa !9
  %59 = zext i32 %58 to i64
  %60 = icmp eq i64 %59, 0
  br i1 %60, label %61, label %73

61:                                               ; preds = %57, %51
  %62 = load ptr, ptr %4, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %62, i32 0, i32 4
  %64 = load volatile i32, ptr %63, align 4, !tbaa !19
  %65 = zext i32 %64 to i64
  %66 = or i64 %65, 4
  %67 = trunc i64 %66 to i32
  store volatile i32 %67, ptr %63, align 4, !tbaa !19
  br label %68

68:                                               ; preds = %61
  %69 = load ptr, ptr %4, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %69, i32 0, i32 3
  store i32 0, ptr %70, align 8, !tbaa !20
  br label %71

71:                                               ; preds = %68
  br label %72

72:                                               ; preds = %71
  store i32 3, ptr %3, align 4
  store i32 1, ptr %13, align 4
  br label %214

73:                                               ; preds = %57
  br label %74

74:                                               ; preds = %73, %48
  br label %38, !llvm.loop !21

75:                                               ; preds = %38
  %76 = load ptr, ptr %4, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %76, i32 0, i32 0
  %78 = load ptr, ptr %77, align 8, !tbaa !11
  %79 = call i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef %78)
  store i32 %79, ptr %8, align 4, !tbaa !9
  %80 = load ptr, ptr %4, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %80, i32 0, i32 0
  %82 = load ptr, ptr %81, align 8, !tbaa !11
  %83 = call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef %82)
  store i32 %83, ptr %9, align 4, !tbaa !9
  %84 = load ptr, ptr %4, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %84, i32 0, i32 0
  %86 = load ptr, ptr %85, align 8, !tbaa !11
  %87 = icmp eq ptr %86, inttoptr (i64 1073881344 to ptr)
  br i1 %87, label %88, label %89

88:                                               ; preds = %75
  br label %93

89:                                               ; preds = %75
  %90 = load ptr, ptr %4, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %90, i32 0, i32 0
  %92 = load ptr, ptr %91, align 8, !tbaa !11
  br label %93

93:                                               ; preds = %89, %88
  %94 = phi ptr [ inttoptr (i64 1073881088 to ptr), %88 ], [ %92, %89 ]
  %95 = load ptr, ptr %4, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %95, i32 0, i32 0
  %97 = load ptr, ptr %96, align 8, !tbaa !11
  %98 = icmp eq ptr %94, %97
  br i1 %98, label %111, label %99

99:                                               ; preds = %93
  %100 = load i32, ptr %12, align 4, !tbaa !9
  %101 = zext i32 %100 to i64
  %102 = icmp eq i64 %101, 0
  br i1 %102, label %111, label %103

103:                                              ; preds = %99
  %104 = load i32, ptr %12, align 4, !tbaa !9
  %105 = zext i32 %104 to i64
  %106 = icmp eq i64 %105, 6
  br i1 %106, label %111, label %107

107:                                              ; preds = %103
  %108 = load i32, ptr %12, align 4, !tbaa !9
  %109 = zext i32 %108 to i64
  %110 = icmp eq i64 %109, 7
  br i1 %110, label %111, label %117

111:                                              ; preds = %107, %103, %99, %93
  %112 = load ptr, ptr %4, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %112, i32 0, i32 0
  %114 = load ptr, ptr %113, align 8, !tbaa !11
  %115 = getelementptr inbounds %struct.ADC_TypeDef, ptr %114, i32 0, i32 3
  %116 = load volatile i32, ptr %115, align 4, !tbaa !23
  store i32 %116, ptr %10, align 4, !tbaa !9
  br label %132

117:                                              ; preds = %107
  %118 = load ptr, ptr %4, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %118, i32 0, i32 0
  %120 = load ptr, ptr %119, align 8, !tbaa !11
  %121 = icmp eq ptr %120, inttoptr (i64 1073881344 to ptr)
  br i1 %121, label %122, label %123

122:                                              ; preds = %117
  br label %127

123:                                              ; preds = %117
  %124 = load ptr, ptr %4, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !11
  br label %127

127:                                              ; preds = %123, %122
  %128 = phi ptr [ inttoptr (i64 1073881088 to ptr), %122 ], [ %126, %123 ]
  store ptr %128, ptr %11, align 8, !tbaa !5
  %129 = load ptr, ptr %11, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ADC_TypeDef, ptr %129, i32 0, i32 3
  %131 = load volatile i32, ptr %130, align 4, !tbaa !23
  store i32 %131, ptr %10, align 4, !tbaa !9
  br label %132

132:                                              ; preds = %127, %111
  %133 = load ptr, ptr %4, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %133, i32 0, i32 4
  %135 = load volatile i32, ptr %134, align 4, !tbaa !19
  %136 = zext i32 %135 to i64
  %137 = or i64 %136, 8192
  %138 = trunc i64 %137 to i32
  store volatile i32 %138, ptr %134, align 4, !tbaa !19
  %139 = load i32, ptr %8, align 4, !tbaa !9
  %140 = zext i32 %139 to i64
  %141 = icmp ne i64 %140, 0
  br i1 %141, label %156, label %142

142:                                              ; preds = %132
  %143 = load i32, ptr %10, align 4, !tbaa !9
  %144 = zext i32 %143 to i64
  %145 = and i64 %144, 33554432
  %146 = icmp eq i64 %145, 0
  br i1 %146, label %147, label %193

147:                                              ; preds = %142
  %148 = load i32, ptr %9, align 4, !tbaa !9
  %149 = zext i32 %148 to i64
  %150 = icmp ne i64 %149, 0
  br i1 %150, label %151, label %193

151:                                              ; preds = %147
  %152 = load i32, ptr %10, align 4, !tbaa !9
  %153 = zext i32 %152 to i64
  %154 = and i64 %153, 8192
  %155 = icmp eq i64 %154, 0
  br i1 %155, label %156, label %193

156:                                              ; preds = %151, %132
  %157 = load ptr, ptr %4, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %157, i32 0, i32 0
  %159 = load ptr, ptr %158, align 8, !tbaa !11
  %160 = getelementptr inbounds %struct.ADC_TypeDef, ptr %159, i32 0, i32 0
  %161 = load volatile i32, ptr %160, align 4, !tbaa !17
  %162 = zext i32 %161 to i64
  %163 = and i64 %162, 64
  %164 = icmp eq i64 %163, 64
  br i1 %164, label %165, label %192

165:                                              ; preds = %156
  %166 = load i32, ptr %10, align 4, !tbaa !9
  %167 = zext i32 %166 to i64
  %168 = and i64 %167, 2097152
  %169 = icmp eq i64 %168, 0
  br i1 %169, label %170, label %191

170:                                              ; preds = %165
  %171 = load ptr, ptr %4, align 8, !tbaa !5
  %172 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %171, i32 0, i32 4
  %173 = load volatile i32, ptr %172, align 4, !tbaa !19
  %174 = zext i32 %173 to i64
  %175 = and i64 %174, -4097
  %176 = trunc i64 %175 to i32
  store volatile i32 %176, ptr %172, align 4, !tbaa !19
  %177 = load ptr, ptr %4, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %177, i32 0, i32 4
  %179 = load volatile i32, ptr %178, align 4, !tbaa !19
  %180 = zext i32 %179 to i64
  %181 = and i64 %180, 256
  %182 = icmp eq i64 %181, 0
  br i1 %182, label %183, label %190

183:                                              ; preds = %170
  %184 = load ptr, ptr %4, align 8, !tbaa !5
  %185 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %184, i32 0, i32 4
  %186 = load volatile i32, ptr %185, align 4, !tbaa !19
  %187 = zext i32 %186 to i64
  %188 = or i64 %187, 1
  %189 = trunc i64 %188 to i32
  store volatile i32 %189, ptr %185, align 4, !tbaa !19
  br label %190

190:                                              ; preds = %183, %170
  br label %191

191:                                              ; preds = %190, %165
  br label %192

192:                                              ; preds = %191, %156
  br label %193

193:                                              ; preds = %192, %151, %147, %142
  %194 = load i32, ptr %7, align 4, !tbaa !9
  %195 = zext i32 %194 to i64
  %196 = icmp eq i64 %195, 64
  br i1 %196, label %197, label %208

197:                                              ; preds = %193
  %198 = load i32, ptr %10, align 4, !tbaa !9
  %199 = zext i32 %198 to i64
  %200 = and i64 %199, 16384
  %201 = icmp eq i64 %200, 0
  br i1 %201, label %202, label %207

202:                                              ; preds = %197
  %203 = load ptr, ptr %4, align 8, !tbaa !5
  %204 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %203, i32 0, i32 0
  %205 = load ptr, ptr %204, align 8, !tbaa !11
  %206 = getelementptr inbounds %struct.ADC_TypeDef, ptr %205, i32 0, i32 0
  store volatile i32 96, ptr %206, align 4, !tbaa !17
  br label %207

207:                                              ; preds = %202, %197
  br label %213

208:                                              ; preds = %193
  %209 = load ptr, ptr %4, align 8, !tbaa !5
  %210 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %209, i32 0, i32 0
  %211 = load ptr, ptr %210, align 8, !tbaa !11
  %212 = getelementptr inbounds %struct.ADC_TypeDef, ptr %211, i32 0, i32 0
  store volatile i32 32, ptr %212, align 4, !tbaa !17
  br label %213

213:                                              ; preds = %208, %207
  store i32 0, ptr %3, align 4
  store i32 1, ptr %13, align 4
  br label %214

214:                                              ; preds = %213, %72
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %215 = load i32, ptr %3, align 4
  ret i32 %215
}

declare i32 @HAL_GetTick() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 20}
!17 = !{!18, !10, i64 0}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!19 = !{!12, !10, i64 100}
!20 = !{!12, !10, i64 96}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!18, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_ADCEx_InjectedPollForConversion(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = icmp eq ptr %3, inttoptr (i64 1073881088 to ptr)
  %5 = icmp eq ptr %3, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %4, %5
  %6 = select i1 %spec.select, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %7 = tail call i32 @LL_ADC_GetMultimode(ptr noundef nonnull %6)
  %8 = getelementptr inbounds i8, ptr %0, i64 20
  %9 = load i32, ptr %8, align 4, !tbaa !14
  %10 = icmp eq i32 %9, 8
  %.051 = select i1 %10, i32 64, i32 32
  %11 = tail call i32 @HAL_GetTick() #3
  %12 = load ptr, ptr %0, align 8, !tbaa !5
  %13 = load volatile i32, ptr %12, align 4, !tbaa !15
  %14 = and i32 %13, %.051
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %2
  switch i32 %1, label %.lr.ph.split.split [
    i32 -1, label %.lr.ph.split.us
    i32 0, label %.lr.ph.split.split.us
  ]

.lr.ph.split.us:                                  ; preds = %.lr.ph, %.lr.ph.split.us
  %16 = load volatile i32, ptr %12, align 4, !tbaa !15
  %17 = and i32 %16, %.051
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %.lr.ph.split.us, label %._crit_edge, !llvm.loop !17

.lr.ph.split.split.us:                            ; preds = %.lr.ph
  %19 = tail call i32 @HAL_GetTick() #3
  br label %.split

.lr.ph.split.split:                               ; preds = %.lr.ph, %27
  %20 = tail call i32 @HAL_GetTick() #3
  %21 = sub i32 %20, %11
  %22 = icmp ugt i32 %21, %1
  br i1 %22, label %.split, label %27

.split:                                           ; preds = %.lr.ph.split.split, %.lr.ph.split.split.us
  %23 = getelementptr inbounds i8, ptr %0, i64 100
  %24 = load volatile i32, ptr %23, align 4, !tbaa !19
  %25 = or i32 %24, 4
  store volatile i32 %25, ptr %23, align 4, !tbaa !19
  %26 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 0, ptr %26, align 8, !tbaa !20
  br label %69

27:                                               ; preds = %.lr.ph.split.split
  %28 = load ptr, ptr %0, align 8, !tbaa !5
  %29 = load volatile i32, ptr %28, align 4, !tbaa !15
  %30 = and i32 %29, %.051
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %.lr.ph.split.split, label %._crit_edge, !llvm.loop !17

._crit_edge:                                      ; preds = %.lr.ph.split.us, %27, %2
  %.lcssa = phi ptr [ %12, %2 ], [ %28, %27 ], [ %12, %.lr.ph.split.us ]
  %32 = tail call i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef nonnull %.lcssa)
  %33 = load ptr, ptr %0, align 8, !tbaa !5
  %34 = tail call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef %33)
  %35 = load ptr, ptr %0, align 8, !tbaa !5
  %36 = icmp eq ptr %35, inttoptr (i64 1073881344 to ptr)
  %spec.select59 = select i1 %36, ptr inttoptr (i64 1073881088 to ptr), ptr %35
  %37 = icmp eq ptr %spec.select59, %35
  %38 = icmp eq i32 %7, 0
  %39 = and i32 %7, -2
  %40 = icmp eq i32 %39, 6
  %41 = or i1 %38, %40
  %or.cond11 = select i1 %37, i1 true, i1 %41
  %.pn = select i1 %or.cond11, ptr %35, ptr %spec.select59
  %.052.in = getelementptr inbounds i8, ptr %.pn, i64 12
  %.052 = load volatile i32, ptr %.052.in, align 4, !tbaa !21
  %42 = getelementptr inbounds i8, ptr %0, i64 100
  %43 = load volatile i32, ptr %42, align 4, !tbaa !19
  %44 = or i32 %43, 8192
  store volatile i32 %44, ptr %42, align 4, !tbaa !19
  %.not = icmp eq i32 %32, 0
  br i1 %.not, label %45, label %49

45:                                               ; preds = %._crit_edge
  %46 = icmp ne i32 %34, 0
  %47 = and i32 %.052, 33562624
  %48 = icmp eq i32 %47, 0
  %or.cond62 = select i1 %48, i1 %46, i1 false
  br i1 %or.cond62, label %49, label %63

49:                                               ; preds = %45, %._crit_edge
  %50 = load volatile i32, ptr %35, align 4, !tbaa !15
  %51 = and i32 %50, 64
  %.not57 = icmp ne i32 %51, 0
  %52 = and i32 %.052, 2097152
  %53 = icmp eq i32 %52, 0
  %or.cond64 = select i1 %.not57, i1 %53, i1 false
  br i1 %or.cond64, label %54, label %63

54:                                               ; preds = %49
  %55 = load volatile i32, ptr %42, align 4, !tbaa !19
  %56 = and i32 %55, -4097
  store volatile i32 %56, ptr %42, align 4, !tbaa !19
  %57 = load volatile i32, ptr %42, align 4, !tbaa !19
  %58 = and i32 %57, 256
  %59 = icmp eq i32 %58, 0
  br i1 %59, label %60, label %63

60:                                               ; preds = %54
  %61 = load volatile i32, ptr %42, align 4, !tbaa !19
  %62 = or i32 %61, 1
  store volatile i32 %62, ptr %42, align 4, !tbaa !19
  br label %63

63:                                               ; preds = %49, %54, %60, %45
  br i1 %10, label %64, label %68

64:                                               ; preds = %63
  %65 = and i32 %.052, 16384
  %66 = icmp eq i32 %65, 0
  br i1 %66, label %67, label %69

67:                                               ; preds = %64
  store volatile i32 96, ptr %35, align 4, !tbaa !15
  br label %69

68:                                               ; preds = %63
  store volatile i32 32, ptr %35, align 4, !tbaa !15
  br label %69

69:                                               ; preds = %68, %67, %64, %.split
  %.0 = phi i32 [ 3, %.split ], [ 0, %64 ], [ 0, %67 ], [ 0, %68 ]
  ret i32 %.0
}

declare i32 @HAL_GetTick() local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsTriggerSourceSWStart(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) local_unnamed_addr #0

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 20}
!15 = !{!16, !11, i64 0}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!6, !11, i64 100}
!20 = !{!6, !11, i64 96}
!21 = !{!16, !11, i64 12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass