; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (usb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.USB_OTG_HostChannelTypeDef = type { i32, i32, i32, i32, i32, i32, [2 x i32] }
%struct.USB_OTG_HostTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.USB_OTG_GlobalTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [39 x i32], i32, [15 x i32] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_EnableGlobalInt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_DisableGlobalInt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_FlushTxFifo(ptr noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_FlushRxFifo(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @USB_StopHost(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  %7 = load ptr, ptr %2, align 8, !tbaa !5
  %8 = ptrtoint ptr %7 to i32
  store i32 %8, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store volatile i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %9 = load ptr, ptr %2, align 8, !tbaa !5
  %10 = call i32 @USB_DisableGlobalInt(ptr noundef %9)
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = call i32 @USB_FlushTxFifo(ptr noundef %11, i32 noundef 16)
  %13 = load ptr, ptr %2, align 8, !tbaa !5
  %14 = call i32 @USB_FlushRxFifo(ptr noundef %13)
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %15

15:                                               ; preds = %51, %1
  %16 = load i32, ptr %6, align 4, !tbaa !9
  %17 = icmp ule i32 %16, 15
  br i1 %17, label %18, label %54

18:                                               ; preds = %15
  %19 = load i32, ptr %3, align 4, !tbaa !9
  %20 = zext i32 %19 to i64
  %21 = add i64 %20, 1280
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = zext i32 %22 to i64
  %24 = mul i64 %23, 32
  %25 = add i64 %21, %24
  %26 = inttoptr i64 %25 to ptr
  %27 = getelementptr inbounds %struct.USB_OTG_HostChannelTypeDef, ptr %26, i32 0, i32 0
  %28 = load volatile i32, ptr %27, align 4, !tbaa !11
  store volatile i32 %28, ptr %5, align 4, !tbaa !9
  %29 = load volatile i32, ptr %5, align 4, !tbaa !9
  %30 = zext i32 %29 to i64
  %31 = or i64 %30, 1073741824
  %32 = trunc i64 %31 to i32
  store volatile i32 %32, ptr %5, align 4, !tbaa !9
  %33 = load volatile i32, ptr %5, align 4, !tbaa !9
  %34 = zext i32 %33 to i64
  %35 = and i64 %34, -2147483649
  %36 = trunc i64 %35 to i32
  store volatile i32 %36, ptr %5, align 4, !tbaa !9
  %37 = load volatile i32, ptr %5, align 4, !tbaa !9
  %38 = zext i32 %37 to i64
  %39 = and i64 %38, -32769
  %40 = trunc i64 %39 to i32
  store volatile i32 %40, ptr %5, align 4, !tbaa !9
  %41 = load volatile i32, ptr %5, align 4, !tbaa !9
  %42 = load i32, ptr %3, align 4, !tbaa !9
  %43 = zext i32 %42 to i64
  %44 = add i64 %43, 1280
  %45 = load i32, ptr %6, align 4, !tbaa !9
  %46 = zext i32 %45 to i64
  %47 = mul i64 %46, 32
  %48 = add i64 %44, %47
  %49 = inttoptr i64 %48 to ptr
  %50 = getelementptr inbounds %struct.USB_OTG_HostChannelTypeDef, ptr %49, i32 0, i32 0
  store volatile i32 %41, ptr %50, align 4, !tbaa !11
  br label %51

51:                                               ; preds = %18
  %52 = load i32, ptr %6, align 4, !tbaa !9
  %53 = add i32 %52, 1
  store i32 %53, ptr %6, align 4, !tbaa !9
  br label %15, !llvm.loop !13

54:                                               ; preds = %15
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %112, %54
  %56 = load i32, ptr %6, align 4, !tbaa !9
  %57 = icmp ule i32 %56, 15
  br i1 %57, label %58, label %115

58:                                               ; preds = %55
  %59 = load i32, ptr %3, align 4, !tbaa !9
  %60 = zext i32 %59 to i64
  %61 = add i64 %60, 1280
  %62 = load i32, ptr %6, align 4, !tbaa !9
  %63 = zext i32 %62 to i64
  %64 = mul i64 %63, 32
  %65 = add i64 %61, %64
  %66 = inttoptr i64 %65 to ptr
  %67 = getelementptr inbounds %struct.USB_OTG_HostChannelTypeDef, ptr %66, i32 0, i32 0
  %68 = load volatile i32, ptr %67, align 4, !tbaa !11
  store volatile i32 %68, ptr %5, align 4, !tbaa !9
  %69 = load volatile i32, ptr %5, align 4, !tbaa !9
  %70 = zext i32 %69 to i64
  %71 = or i64 %70, 1073741824
  %72 = trunc i64 %71 to i32
  store volatile i32 %72, ptr %5, align 4, !tbaa !9
  %73 = load volatile i32, ptr %5, align 4, !tbaa !9
  %74 = zext i32 %73 to i64
  %75 = or i64 %74, 2147483648
  %76 = trunc i64 %75 to i32
  store volatile i32 %76, ptr %5, align 4, !tbaa !9
  %77 = load volatile i32, ptr %5, align 4, !tbaa !9
  %78 = zext i32 %77 to i64
  %79 = and i64 %78, -32769
  %80 = trunc i64 %79 to i32
  store volatile i32 %80, ptr %5, align 4, !tbaa !9
  %81 = load volatile i32, ptr %5, align 4, !tbaa !9
  %82 = load i32, ptr %3, align 4, !tbaa !9
  %83 = zext i32 %82 to i64
  %84 = add i64 %83, 1280
  %85 = load i32, ptr %6, align 4, !tbaa !9
  %86 = zext i32 %85 to i64
  %87 = mul i64 %86, 32
  %88 = add i64 %84, %87
  %89 = inttoptr i64 %88 to ptr
  %90 = getelementptr inbounds %struct.USB_OTG_HostChannelTypeDef, ptr %89, i32 0, i32 0
  store volatile i32 %81, ptr %90, align 4, !tbaa !11
  br label %91

91:                                               ; preds = %97, %58
  %92 = load volatile i32, ptr %4, align 4, !tbaa !9
  %93 = add i32 %92, 1
  store volatile i32 %93, ptr %4, align 4, !tbaa !9
  %94 = icmp ugt i32 %93, 1000
  br i1 %94, label %95, label %96

95:                                               ; preds = %91
  br label %111

96:                                               ; preds = %91
  br label %97

97:                                               ; preds = %96
  %98 = load i32, ptr %3, align 4, !tbaa !9
  %99 = zext i32 %98 to i64
  %100 = add i64 %99, 1280
  %101 = load i32, ptr %6, align 4, !tbaa !9
  %102 = zext i32 %101 to i64
  %103 = mul i64 %102, 32
  %104 = add i64 %100, %103
  %105 = inttoptr i64 %104 to ptr
  %106 = getelementptr inbounds %struct.USB_OTG_HostChannelTypeDef, ptr %105, i32 0, i32 0
  %107 = load volatile i32, ptr %106, align 4, !tbaa !11
  %108 = zext i32 %107 to i64
  %109 = and i64 %108, 2147483648
  %110 = icmp eq i64 %109, 2147483648
  br i1 %110, label %91, label %111, !llvm.loop !15

111:                                              ; preds = %97, %95
  br label %112

112:                                              ; preds = %111
  %113 = load i32, ptr %6, align 4, !tbaa !9
  %114 = add i32 %113, 1
  store i32 %114, ptr %6, align 4, !tbaa !9
  br label %55, !llvm.loop !16

115:                                              ; preds = %55
  %116 = load i32, ptr %3, align 4, !tbaa !9
  %117 = zext i32 %116 to i64
  %118 = add i64 %117, 1024
  %119 = inttoptr i64 %118 to ptr
  %120 = getelementptr inbounds %struct.USB_OTG_HostTypeDef, ptr %119, i32 0, i32 5
  store volatile i32 -1, ptr %120, align 4, !tbaa !17
  %121 = load ptr, ptr %2, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.USB_OTG_GlobalTypeDef, ptr %121, i32 0, i32 5
  store volatile i32 -1, ptr %122, align 4, !tbaa !19
  %123 = load ptr, ptr %2, align 8, !tbaa !5
  %124 = call i32 @USB_EnableGlobalInt(ptr noundef %123)
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret i32 0
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !7, i64 24}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = !{!18, !10, i64 20}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!19 = !{!20, !10, i64 20}
!20 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !7, i64 48, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !7, i64 100, !10, i64 256, !7, i64 260}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_EnableGlobalInt(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_DisableGlobalInt(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_FlushTxFifo(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @USB_FlushRxFifo(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @USB_StopHost(ptr noundef %0) local_unnamed_addr #1 {
.preheader:
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = ptrtoint ptr %0 to i64
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1)
  store volatile i32 0, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
  %4 = tail call i32 @USB_DisableGlobalInt(ptr noundef %0)
  %5 = tail call i32 @USB_FlushTxFifo(ptr noundef %0, i32 noundef 16)
  %6 = tail call i32 @USB_FlushRxFifo(ptr noundef %0)
  %7 = and i64 %3, 4294967295
  %8 = add nuw nsw i64 %7, 1280
  %9 = inttoptr i64 %8 to ptr
  %10 = load volatile i32, ptr %9, align 4, !tbaa !9
  store volatile i32 %10, ptr %2, align 4, !tbaa !5
  %.0..0..0..0. = load volatile i32, ptr %2, align 4, !tbaa !5
  %11 = or i32 %.0..0..0..0., 1073741824
  store volatile i32 %11, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9 = load volatile i32, ptr %2, align 4, !tbaa !5
  %12 = and i32 %.0..0..0..0.9, 2147483647
  store volatile i32 %12, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10 = load volatile i32, ptr %2, align 4, !tbaa !5
  %13 = and i32 %.0..0..0..0.10, -32769
  store volatile i32 %13, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11, ptr %9, align 4, !tbaa !9
  %14 = add nuw nsw i64 %7, 1312
  %15 = inttoptr i64 %14 to ptr
  %16 = load volatile i32, ptr %15, align 4, !tbaa !9
  store volatile i32 %16, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..1 = load volatile i32, ptr %2, align 4, !tbaa !5
  %17 = or i32 %.0..0..0..0..1, 1073741824
  store volatile i32 %17, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.1 = load volatile i32, ptr %2, align 4, !tbaa !5
  %18 = and i32 %.0..0..0..0.9.1, 2147483647
  store volatile i32 %18, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.1 = load volatile i32, ptr %2, align 4, !tbaa !5
  %19 = and i32 %.0..0..0..0.10.1, -32769
  store volatile i32 %19, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.1 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.1, ptr %15, align 4, !tbaa !9
  %20 = add nuw nsw i64 %7, 1344
  %21 = inttoptr i64 %20 to ptr
  %22 = load volatile i32, ptr %21, align 4, !tbaa !9
  store volatile i32 %22, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..2 = load volatile i32, ptr %2, align 4, !tbaa !5
  %23 = or i32 %.0..0..0..0..2, 1073741824
  store volatile i32 %23, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.2 = load volatile i32, ptr %2, align 4, !tbaa !5
  %24 = and i32 %.0..0..0..0.9.2, 2147483647
  store volatile i32 %24, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.2 = load volatile i32, ptr %2, align 4, !tbaa !5
  %25 = and i32 %.0..0..0..0.10.2, -32769
  store volatile i32 %25, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.2 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.2, ptr %21, align 4, !tbaa !9
  %26 = add nuw nsw i64 %7, 1376
  %27 = inttoptr i64 %26 to ptr
  %28 = load volatile i32, ptr %27, align 4, !tbaa !9
  store volatile i32 %28, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..3 = load volatile i32, ptr %2, align 4, !tbaa !5
  %29 = or i32 %.0..0..0..0..3, 1073741824
  store volatile i32 %29, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.3 = load volatile i32, ptr %2, align 4, !tbaa !5
  %30 = and i32 %.0..0..0..0.9.3, 2147483647
  store volatile i32 %30, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.3 = load volatile i32, ptr %2, align 4, !tbaa !5
  %31 = and i32 %.0..0..0..0.10.3, -32769
  store volatile i32 %31, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.3 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.3, ptr %27, align 4, !tbaa !9
  %32 = add nuw nsw i64 %7, 1408
  %33 = inttoptr i64 %32 to ptr
  %34 = load volatile i32, ptr %33, align 4, !tbaa !9
  store volatile i32 %34, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..4 = load volatile i32, ptr %2, align 4, !tbaa !5
  %35 = or i32 %.0..0..0..0..4, 1073741824
  store volatile i32 %35, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.4 = load volatile i32, ptr %2, align 4, !tbaa !5
  %36 = and i32 %.0..0..0..0.9.4, 2147483647
  store volatile i32 %36, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.4 = load volatile i32, ptr %2, align 4, !tbaa !5
  %37 = and i32 %.0..0..0..0.10.4, -32769
  store volatile i32 %37, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.4 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.4, ptr %33, align 4, !tbaa !9
  %38 = add nuw nsw i64 %7, 1440
  %39 = inttoptr i64 %38 to ptr
  %40 = load volatile i32, ptr %39, align 4, !tbaa !9
  store volatile i32 %40, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..5 = load volatile i32, ptr %2, align 4, !tbaa !5
  %41 = or i32 %.0..0..0..0..5, 1073741824
  store volatile i32 %41, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.5 = load volatile i32, ptr %2, align 4, !tbaa !5
  %42 = and i32 %.0..0..0..0.9.5, 2147483647
  store volatile i32 %42, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.5 = load volatile i32, ptr %2, align 4, !tbaa !5
  %43 = and i32 %.0..0..0..0.10.5, -32769
  store volatile i32 %43, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.5 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.5, ptr %39, align 4, !tbaa !9
  %44 = add nuw nsw i64 %7, 1472
  %45 = inttoptr i64 %44 to ptr
  %46 = load volatile i32, ptr %45, align 4, !tbaa !9
  store volatile i32 %46, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..6 = load volatile i32, ptr %2, align 4, !tbaa !5
  %47 = or i32 %.0..0..0..0..6, 1073741824
  store volatile i32 %47, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.6 = load volatile i32, ptr %2, align 4, !tbaa !5
  %48 = and i32 %.0..0..0..0.9.6, 2147483647
  store volatile i32 %48, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.6 = load volatile i32, ptr %2, align 4, !tbaa !5
  %49 = and i32 %.0..0..0..0.10.6, -32769
  store volatile i32 %49, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.6 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.6, ptr %45, align 4, !tbaa !9
  %50 = add nuw nsw i64 %7, 1504
  %51 = inttoptr i64 %50 to ptr
  %52 = load volatile i32, ptr %51, align 4, !tbaa !9
  store volatile i32 %52, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..7 = load volatile i32, ptr %2, align 4, !tbaa !5
  %53 = or i32 %.0..0..0..0..7, 1073741824
  store volatile i32 %53, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.7 = load volatile i32, ptr %2, align 4, !tbaa !5
  %54 = and i32 %.0..0..0..0.9.7, 2147483647
  store volatile i32 %54, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.7 = load volatile i32, ptr %2, align 4, !tbaa !5
  %55 = and i32 %.0..0..0..0.10.7, -32769
  store volatile i32 %55, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.7 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.7, ptr %51, align 4, !tbaa !9
  %56 = add nuw nsw i64 %7, 1536
  %57 = inttoptr i64 %56 to ptr
  %58 = load volatile i32, ptr %57, align 4, !tbaa !9
  store volatile i32 %58, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..8 = load volatile i32, ptr %2, align 4, !tbaa !5
  %59 = or i32 %.0..0..0..0..8, 1073741824
  store volatile i32 %59, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.8 = load volatile i32, ptr %2, align 4, !tbaa !5
  %60 = and i32 %.0..0..0..0.9.8, 2147483647
  store volatile i32 %60, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.8 = load volatile i32, ptr %2, align 4, !tbaa !5
  %61 = and i32 %.0..0..0..0.10.8, -32769
  store volatile i32 %61, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.8 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.8, ptr %57, align 4, !tbaa !9
  %62 = add nuw nsw i64 %7, 1568
  %63 = inttoptr i64 %62 to ptr
  %64 = load volatile i32, ptr %63, align 4, !tbaa !9
  store volatile i32 %64, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..9 = load volatile i32, ptr %2, align 4, !tbaa !5
  %65 = or i32 %.0..0..0..0..9, 1073741824
  store volatile i32 %65, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.9 = load volatile i32, ptr %2, align 4, !tbaa !5
  %66 = and i32 %.0..0..0..0.9.9, 2147483647
  store volatile i32 %66, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.9 = load volatile i32, ptr %2, align 4, !tbaa !5
  %67 = and i32 %.0..0..0..0.10.9, -32769
  store volatile i32 %67, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.9 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.9, ptr %63, align 4, !tbaa !9
  %68 = add nuw nsw i64 %7, 1600
  %69 = inttoptr i64 %68 to ptr
  %70 = load volatile i32, ptr %69, align 4, !tbaa !9
  store volatile i32 %70, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..10 = load volatile i32, ptr %2, align 4, !tbaa !5
  %71 = or i32 %.0..0..0..0..10, 1073741824
  store volatile i32 %71, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.10 = load volatile i32, ptr %2, align 4, !tbaa !5
  %72 = and i32 %.0..0..0..0.9.10, 2147483647
  store volatile i32 %72, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.10 = load volatile i32, ptr %2, align 4, !tbaa !5
  %73 = and i32 %.0..0..0..0.10.10, -32769
  store volatile i32 %73, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.10 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.10, ptr %69, align 4, !tbaa !9
  %74 = add nuw nsw i64 %7, 1632
  %75 = inttoptr i64 %74 to ptr
  %76 = load volatile i32, ptr %75, align 4, !tbaa !9
  store volatile i32 %76, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..11 = load volatile i32, ptr %2, align 4, !tbaa !5
  %77 = or i32 %.0..0..0..0..11, 1073741824
  store volatile i32 %77, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.11 = load volatile i32, ptr %2, align 4, !tbaa !5
  %78 = and i32 %.0..0..0..0.9.11, 2147483647
  store volatile i32 %78, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.11 = load volatile i32, ptr %2, align 4, !tbaa !5
  %79 = and i32 %.0..0..0..0.10.11, -32769
  store volatile i32 %79, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.11 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.11, ptr %75, align 4, !tbaa !9
  %80 = add nuw nsw i64 %7, 1664
  %81 = inttoptr i64 %80 to ptr
  %82 = load volatile i32, ptr %81, align 4, !tbaa !9
  store volatile i32 %82, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..12 = load volatile i32, ptr %2, align 4, !tbaa !5
  %83 = or i32 %.0..0..0..0..12, 1073741824
  store volatile i32 %83, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.12 = load volatile i32, ptr %2, align 4, !tbaa !5
  %84 = and i32 %.0..0..0..0.9.12, 2147483647
  store volatile i32 %84, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.12 = load volatile i32, ptr %2, align 4, !tbaa !5
  %85 = and i32 %.0..0..0..0.10.12, -32769
  store volatile i32 %85, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.12 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.12, ptr %81, align 4, !tbaa !9
  %86 = add nuw nsw i64 %7, 1696
  %87 = inttoptr i64 %86 to ptr
  %88 = load volatile i32, ptr %87, align 4, !tbaa !9
  store volatile i32 %88, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..13 = load volatile i32, ptr %2, align 4, !tbaa !5
  %89 = or i32 %.0..0..0..0..13, 1073741824
  store volatile i32 %89, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.13 = load volatile i32, ptr %2, align 4, !tbaa !5
  %90 = and i32 %.0..0..0..0.9.13, 2147483647
  store volatile i32 %90, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.13 = load volatile i32, ptr %2, align 4, !tbaa !5
  %91 = and i32 %.0..0..0..0.10.13, -32769
  store volatile i32 %91, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.13 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.13, ptr %87, align 4, !tbaa !9
  %92 = add nuw nsw i64 %7, 1728
  %93 = inttoptr i64 %92 to ptr
  %94 = load volatile i32, ptr %93, align 4, !tbaa !9
  store volatile i32 %94, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..14 = load volatile i32, ptr %2, align 4, !tbaa !5
  %95 = or i32 %.0..0..0..0..14, 1073741824
  store volatile i32 %95, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.14 = load volatile i32, ptr %2, align 4, !tbaa !5
  %96 = and i32 %.0..0..0..0.9.14, 2147483647
  store volatile i32 %96, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.14 = load volatile i32, ptr %2, align 4, !tbaa !5
  %97 = and i32 %.0..0..0..0.10.14, -32769
  store volatile i32 %97, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.14 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.14, ptr %93, align 4, !tbaa !9
  %98 = add nuw nsw i64 %7, 1760
  %99 = inttoptr i64 %98 to ptr
  %100 = load volatile i32, ptr %99, align 4, !tbaa !9
  store volatile i32 %100, ptr %2, align 4, !tbaa !5
  %.0..0..0..0..15 = load volatile i32, ptr %2, align 4, !tbaa !5
  %101 = or i32 %.0..0..0..0..15, 1073741824
  store volatile i32 %101, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.9.15 = load volatile i32, ptr %2, align 4, !tbaa !5
  %102 = and i32 %.0..0..0..0.9.15, 2147483647
  store volatile i32 %102, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.10.15 = load volatile i32, ptr %2, align 4, !tbaa !5
  %103 = and i32 %.0..0..0..0.10.15, -32769
  store volatile i32 %103, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.11.15 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.11.15, ptr %99, align 4, !tbaa !9
  br label %104

104:                                              ; preds = %.preheader, %117
  %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %117 ]
  %105 = shl nuw nsw i64 %indvars.iv, 5
  %106 = add nuw nsw i64 %8, %105
  %107 = inttoptr i64 %106 to ptr
  %108 = load volatile i32, ptr %107, align 4, !tbaa !9
  store volatile i32 %108, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.12 = load volatile i32, ptr %2, align 4, !tbaa !5
  %109 = or i32 %.0..0..0..0.12, 1073741824
  store volatile i32 %109, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.13 = load volatile i32, ptr %2, align 4, !tbaa !5
  %110 = or i32 %.0..0..0..0.13, -2147483648
  store volatile i32 %110, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.14 = load volatile i32, ptr %2, align 4, !tbaa !5
  %111 = and i32 %.0..0..0..0.14, -32769
  store volatile i32 %111, ptr %2, align 4, !tbaa !5
  %.0..0..0..0.15 = load volatile i32, ptr %2, align 4, !tbaa !5
  store volatile i32 %.0..0..0..0.15, ptr %107, align 4, !tbaa !9
  br label %112

112:                                              ; preds = %115, %104
  %.0..0..0..0.16 = load volatile i32, ptr %1, align 4, !tbaa !5
  %113 = add i32 %.0..0..0..0.16, 1
  store volatile i32 %113, ptr %1, align 4, !tbaa !5
  %114 = icmp ugt i32 %113, 1000
  br i1 %114, label %117, label %115

115:                                              ; preds = %112
  %116 = load volatile i32, ptr %107, align 4, !tbaa !9
  %.not = icmp sgt i32 %116, -1
  br i1 %.not, label %117, label %112, !llvm.loop !11

117:                                              ; preds = %115, %112
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 16
  br i1 %exitcond.not, label %118, label %104, !llvm.loop !13

118:                                              ; preds = %117
  %119 = add nuw nsw i64 %7, 1024
  %120 = inttoptr i64 %119 to ptr
  %121 = getelementptr inbounds i8, ptr %120, i64 20
  store volatile i32 -1, ptr %121, align 4, !tbaa !14
  %122 = getelementptr inbounds i8, ptr %0, i64 20
  store volatile i32 -1, ptr %122, align 4, !tbaa !16
  %123 = tail call i32 @USB_EnableGlobalInt(ptr noundef %0)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1)
  ret i32 0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !7, i64 24}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = !{!15, !6, i64 20}
!15 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24}
!16 = !{!17, !6, i64 20}
!17 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !7, i64 48, !6, i64 56, !6, i64 60, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92, !6, i64 96, !7, i64 100, !6, i64 256, !7, i64 260}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass