; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (CFI)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NOR_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32 }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.NOR_CFITypeDef = type { i16, i16, i16, i16 }

@uwNORMemoryDataWidth = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NOR_Read_CFI(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %9, i32 0, i32 4
  %11 = load volatile i32, ptr %10, align 8, !tbaa !9
  store i32 %11, ptr %7, align 4, !tbaa !13
  %12 = load i32, ptr %7, align 4, !tbaa !13
  %13 = icmp eq i32 %12, 2
  br i1 %13, label %14, label %15

14:                                               ; preds = %2
  store i32 2, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %146

15:                                               ; preds = %2
  %16 = load i32, ptr %7, align 4, !tbaa !13
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %21, label %18

18:                                               ; preds = %15
  %19 = load i32, ptr %7, align 4, !tbaa !13
  %20 = icmp eq i32 %19, 4
  br i1 %20, label %21, label %143

21:                                               ; preds = %18, %15
  br label %22

22:                                               ; preds = %21
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %23, i32 0, i32 3
  %25 = load i32, ptr %24, align 4, !tbaa !14
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %22
  store i32 2, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %146

28:                                               ; preds = %22
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %29, i32 0, i32 3
  store i32 1, ptr %30, align 4, !tbaa !14
  br label %31

31:                                               ; preds = %28
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %34, i32 0, i32 4
  store volatile i32 2, ptr %35, align 8, !tbaa !9
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %36, i32 0, i32 2
  %38 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %37, i32 0, i32 0
  %39 = load i32, ptr %38, align 8, !tbaa !15
  %40 = icmp eq i32 %39, 0
  br i1 %40, label %41, label %42

41:                                               ; preds = %33
  store i32 1610612736, ptr %6, align 4, !tbaa !13
  br label %59

42:                                               ; preds = %33
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %43, i32 0, i32 2
  %45 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %44, i32 0, i32 0
  %46 = load i32, ptr %45, align 8, !tbaa !15
  %47 = icmp eq i32 %46, 2
  br i1 %47, label %48, label %49

48:                                               ; preds = %42
  store i32 1677721600, ptr %6, align 4, !tbaa !13
  br label %58

49:                                               ; preds = %42
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %50, i32 0, i32 2
  %52 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %51, i32 0, i32 0
  %53 = load i32, ptr %52, align 8, !tbaa !15
  %54 = icmp eq i32 %53, 4
  br i1 %54, label %55, label %56

55:                                               ; preds = %49
  store i32 1744830464, ptr %6, align 4, !tbaa !13
  br label %57

56:                                               ; preds = %49
  store i32 1811939328, ptr %6, align 4, !tbaa !13
  br label %57

57:                                               ; preds = %56, %55
  br label %58

58:                                               ; preds = %57, %48
  br label %59

59:                                               ; preds = %58, %41
  br label %60

60:                                               ; preds = %59
  %61 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !13
  %62 = icmp eq i32 %61, 1
  br i1 %62, label %63, label %66

63:                                               ; preds = %60
  %64 = load i32, ptr %6, align 4, !tbaa !13
  %65 = add i32 %64, 170
  br label %69

66:                                               ; preds = %60
  %67 = load i32, ptr %6, align 4, !tbaa !13
  %68 = add i32 %67, 85
  br label %69

69:                                               ; preds = %66, %63
  %70 = phi i32 [ %65, %63 ], [ %68, %66 ]
  %71 = zext i32 %70 to i64
  %72 = inttoptr i64 %71 to ptr
  store volatile i16 152, ptr %72, align 2, !tbaa !16
  call void @__DSB()
  br label %73

73:                                               ; preds = %69
  br label %74

74:                                               ; preds = %73
  %75 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !13
  %76 = icmp eq i32 %75, 1
  br i1 %76, label %77, label %80

77:                                               ; preds = %74
  %78 = load i32, ptr %6, align 4, !tbaa !13
  %79 = add i32 %78, 194
  br label %83

80:                                               ; preds = %74
  %81 = load i32, ptr %6, align 4, !tbaa !13
  %82 = add i32 %81, 97
  br label %83

83:                                               ; preds = %80, %77
  %84 = phi i32 [ %79, %77 ], [ %82, %80 ]
  %85 = zext i32 %84 to i64
  %86 = inttoptr i64 %85 to ptr
  %87 = load volatile i16, ptr %86, align 2, !tbaa !16
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.NOR_CFITypeDef, ptr %88, i32 0, i32 0
  store i16 %87, ptr %89, align 2, !tbaa !18
  %90 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !13
  %91 = icmp eq i32 %90, 1
  br i1 %91, label %92, label %95

92:                                               ; preds = %83
  %93 = load i32, ptr %6, align 4, !tbaa !13
  %94 = add i32 %93, 196
  br label %98

95:                                               ; preds = %83
  %96 = load i32, ptr %6, align 4, !tbaa !13
  %97 = add i32 %96, 98
  br label %98

98:                                               ; preds = %95, %92
  %99 = phi i32 [ %94, %92 ], [ %97, %95 ]
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  %102 = load volatile i16, ptr %101, align 2, !tbaa !16
  %103 = load ptr, ptr %5, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.NOR_CFITypeDef, ptr %103, i32 0, i32 1
  store i16 %102, ptr %104, align 2, !tbaa !20
  %105 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !13
  %106 = icmp eq i32 %105, 1
  br i1 %106, label %107, label %110

107:                                              ; preds = %98
  %108 = load i32, ptr %6, align 4, !tbaa !13
  %109 = add i32 %108, 198
  br label %113

110:                                              ; preds = %98
  %111 = load i32, ptr %6, align 4, !tbaa !13
  %112 = add i32 %111, 99
  br label %113

113:                                              ; preds = %110, %107
  %114 = phi i32 [ %109, %107 ], [ %112, %110 ]
  %115 = zext i32 %114 to i64
  %116 = inttoptr i64 %115 to ptr
  %117 = load volatile i16, ptr %116, align 2, !tbaa !16
  %118 = load ptr, ptr %5, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.NOR_CFITypeDef, ptr %118, i32 0, i32 2
  store i16 %117, ptr %119, align 2, !tbaa !21
  %120 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !13
  %121 = icmp eq i32 %120, 1
  br i1 %121, label %122, label %125

122:                                              ; preds = %113
  %123 = load i32, ptr %6, align 4, !tbaa !13
  %124 = add i32 %123, 200
  br label %128

125:                                              ; preds = %113
  %126 = load i32, ptr %6, align 4, !tbaa !13
  %127 = add i32 %126, 100
  br label %128

128:                                              ; preds = %125, %122
  %129 = phi i32 [ %124, %122 ], [ %127, %125 ]
  %130 = zext i32 %129 to i64
  %131 = inttoptr i64 %130 to ptr
  %132 = load volatile i16, ptr %131, align 2, !tbaa !16
  %133 = load ptr, ptr %5, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.NOR_CFITypeDef, ptr %133, i32 0, i32 3
  store i16 %132, ptr %134, align 2, !tbaa !22
  %135 = load i32, ptr %7, align 4, !tbaa !13
  %136 = load ptr, ptr %4, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %136, i32 0, i32 4
  store volatile i32 %135, ptr %137, align 8, !tbaa !9
  br label %138

138:                                              ; preds = %128
  %139 = load ptr, ptr %4, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %139, i32 0, i32 3
  store i32 0, ptr %140, align 4, !tbaa !14
  br label %141

141:                                              ; preds = %138
  br label %142

142:                                              ; preds = %141
  br label %144

143:                                              ; preds = %18
  store i32 1, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %146

144:                                              ; preds = %142
  br label %145

145:                                              ; preds = %144
  store i32 0, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %146

146:                                              ; preds = %145, %143, %27, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %147 = load i32, ptr %3, align 4
  ret i32 %147
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 80}
!10 = !{!"", !6, i64 0, !6, i64 8, !11, i64 16, !12, i64 76, !12, i64 80}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56}
!12 = !{!"int", !7, i64 0}
!13 = !{!12, !12, i64 0}
!14 = !{!10, !12, i64 76}
!15 = !{!10, !12, i64 16}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !7, i64 0}
!18 = !{!19, !17, i64 0}
!19 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4, !17, i64 6}
!20 = !{!19, !17, i64 2}
!21 = !{!19, !17, i64 4}
!22 = !{!19, !17, i64 6}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@uwNORMemoryDataWidth = external hidden local_unnamed_addr global i32, align 4
@switch.table.HAL_NOR_Read_CFI = private unnamed_addr constant [5 x i32] [i32 1610612736, i32 1811939328, i32 1677721600, i32 1811939328, i32 1744830464], align 4

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_NOR_Read_CFI(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 80
  %4 = load volatile i32, ptr %3, align 8, !tbaa !5
  switch i32 %4, label %.fold.split [
    i32 2, label %41
    i32 4, label %5
    i32 1, label %5
  ]

5:                                                ; preds = %2, %2
  %6 = getelementptr inbounds i8, ptr %0, i64 76
  %7 = load i32, ptr %6, align 4, !tbaa !12
  %8 = icmp eq i32 %7, 1
  br i1 %8, label %41, label %9

9:                                                ; preds = %5
  store i32 1, ptr %6, align 4, !tbaa !12
  store volatile i32 2, ptr %3, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %0, i64 16
  %11 = load i32, ptr %10, align 8, !tbaa !13
  %12 = icmp ult i32 %11, 5
  br i1 %12, label %switch.lookup, label %14

switch.lookup:                                    ; preds = %9
  %13 = zext nneg i32 %11 to i64
  %switch.gep = getelementptr inbounds [5 x i32], ptr @switch.table.HAL_NOR_Read_CFI, i64 0, i64 %13
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %14

14:                                               ; preds = %9, %switch.lookup
  %.028 = phi i32 [ %switch.load, %switch.lookup ], [ 1811939328, %9 ]
  %15 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %16 = icmp eq i32 %15, 1
  %.v = select i1 %16, i32 170, i32 85
  %17 = or disjoint i32 %.v, %.028
  %18 = zext nneg i32 %17 to i64
  %19 = inttoptr i64 %18 to ptr
  store volatile i16 152, ptr %19, align 2, !tbaa !15
  tail call void @__DSB()
  %20 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %21 = icmp eq i32 %20, 1
  %.v31 = select i1 %21, i32 194, i32 97
  %22 = or disjoint i32 %.v31, %.028
  %23 = zext nneg i32 %22 to i64
  %24 = inttoptr i64 %23 to ptr
  %25 = load volatile i16, ptr %24, align 2, !tbaa !15
  store i16 %25, ptr %1, align 2, !tbaa !17
  %.v32 = select i1 %21, i32 196, i32 98
  %26 = or disjoint i32 %.v32, %.028
  %27 = zext nneg i32 %26 to i64
  %28 = inttoptr i64 %27 to ptr
  %29 = load volatile i16, ptr %28, align 2, !tbaa !15
  %30 = getelementptr inbounds i8, ptr %1, i64 2
  store i16 %29, ptr %30, align 2, !tbaa !19
  %.v33 = select i1 %21, i32 198, i32 99
  %31 = or disjoint i32 %.v33, %.028
  %32 = zext nneg i32 %31 to i64
  %33 = inttoptr i64 %32 to ptr
  %34 = load volatile i16, ptr %33, align 2, !tbaa !15
  %35 = getelementptr inbounds i8, ptr %1, i64 4
  store i16 %34, ptr %35, align 2, !tbaa !20
  %.v34 = select i1 %21, i32 200, i32 100
  %36 = or disjoint i32 %.v34, %.028
  %37 = zext nneg i32 %36 to i64
  %38 = inttoptr i64 %37 to ptr
  %39 = load volatile i16, ptr %38, align 4, !tbaa !15
  %40 = getelementptr inbounds i8, ptr %1, i64 6
  store i16 %39, ptr %40, align 2, !tbaa !21
  store volatile i32 %4, ptr %3, align 8, !tbaa !5
  store i32 0, ptr %6, align 4, !tbaa !12
  br label %41

.fold.split:                                      ; preds = %2
  br label %41

41:                                               ; preds = %2, %.fold.split, %5, %14
  %.0 = phi i32 [ 0, %14 ], [ %4, %2 ], [ 2, %5 ], [ 1, %.fold.split ]
  ret i32 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !11, i64 16}
!14 = !{!11, !11, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"short", !8, i64 0}
!17 = !{!18, !16, i64 0}
!18 = !{!"", !16, i64 0, !16, i64 2, !16, i64 4, !16, i64 6}
!19 = !{!18, !16, i64 2}
!20 = !{!18, !16, i64 4}
!21 = !{!18, !16, i64 6}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass