; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.DAC_HandleTypeDef = type { ptr, i32, i32, ptr, ptr, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.DAC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DAC_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store ptr %2, ptr %9, align 8, !tbaa !5
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i32 %4, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %15

15:                                               ; preds = %5
  %16 = load ptr, ptr %7, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %16, i32 0, i32 2
  %18 = load i32, ptr %17, align 4, !tbaa !11
  %19 = icmp eq i32 %18, 1
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  store i32 2, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %180

21:                                               ; preds = %15
  %22 = load ptr, ptr %7, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %22, i32 0, i32 2
  store i32 1, ptr %23, align 4, !tbaa !11
  br label %24

24:                                               ; preds = %21
  br label %25

25:                                               ; preds = %24
  br label %26

26:                                               ; preds = %25
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %27, i32 0, i32 1
  store volatile i32 2, ptr %28, align 8, !tbaa !13
  %29 = load i32, ptr %8, align 4, !tbaa !9
  %30 = icmp eq i32 %29, 0
  br i1 %30, label %31, label %73

31:                                               ; preds = %26
  %32 = load ptr, ptr %7, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %32, i32 0, i32 3
  %34 = load ptr, ptr %33, align 8, !tbaa !14
  %35 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %34, i32 0, i32 5
  store ptr @DAC_DMAConvCpltCh1, ptr %35, align 8, !tbaa !15
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %36, i32 0, i32 3
  %38 = load ptr, ptr %37, align 8, !tbaa !14
  %39 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %38, i32 0, i32 6
  store ptr @DAC_DMAHalfConvCpltCh1, ptr %39, align 8, !tbaa !18
  %40 = load ptr, ptr %7, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %40, i32 0, i32 3
  %42 = load ptr, ptr %41, align 8, !tbaa !14
  %43 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %42, i32 0, i32 9
  store ptr @DAC_DMAErrorCh1, ptr %43, align 8, !tbaa !19
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !20
  %47 = getelementptr inbounds %struct.DAC_TypeDef, ptr %46, i32 0, i32 0
  %48 = load volatile i32, ptr %47, align 4, !tbaa !21
  %49 = zext i32 %48 to i64
  %50 = or i64 %49, 4096
  %51 = trunc i64 %50 to i32
  store volatile i32 %51, ptr %47, align 4, !tbaa !21
  %52 = load i32, ptr %11, align 4, !tbaa !9
  switch i32 %52, label %71 [
    i32 0, label %53
    i32 4, label %59
    i32 8, label %65
  ]

53:                                               ; preds = %31
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %54, i32 0, i32 0
  %56 = load ptr, ptr %55, align 8, !tbaa !20
  %57 = getelementptr inbounds %struct.DAC_TypeDef, ptr %56, i32 0, i32 2
  %58 = ptrtoint ptr %57 to i32
  store i32 %58, ptr %13, align 4, !tbaa !9
  br label %72

59:                                               ; preds = %31
  %60 = load ptr, ptr %7, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %60, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8, !tbaa !20
  %63 = getelementptr inbounds %struct.DAC_TypeDef, ptr %62, i32 0, i32 3
  %64 = ptrtoint ptr %63 to i32
  store i32 %64, ptr %13, align 4, !tbaa !9
  br label %72

65:                                               ; preds = %31
  %66 = load ptr, ptr %7, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %66, i32 0, i32 0
  %68 = load ptr, ptr %67, align 8, !tbaa !20
  %69 = getelementptr inbounds %struct.DAC_TypeDef, ptr %68, i32 0, i32 4
  %70 = ptrtoint ptr %69 to i32
  store i32 %70, ptr %13, align 4, !tbaa !9
  br label %72

71:                                               ; preds = %31
  br label %72

72:                                               ; preds = %71, %65, %59, %53
  br label %115

73:                                               ; preds = %26
  %74 = load ptr, ptr %7, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %74, i32 0, i32 4
  %76 = load ptr, ptr %75, align 8, !tbaa !23
  %77 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %76, i32 0, i32 5
  store ptr @DAC_DMAConvCpltCh2, ptr %77, align 8, !tbaa !15
  %78 = load ptr, ptr %7, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %78, i32 0, i32 4
  %80 = load ptr, ptr %79, align 8, !tbaa !23
  %81 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %80, i32 0, i32 6
  store ptr @DAC_DMAHalfConvCpltCh2, ptr %81, align 8, !tbaa !18
  %82 = load ptr, ptr %7, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %82, i32 0, i32 4
  %84 = load ptr, ptr %83, align 8, !tbaa !23
  %85 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %84, i32 0, i32 9
  store ptr @DAC_DMAErrorCh2, ptr %85, align 8, !tbaa !19
  %86 = load ptr, ptr %7, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %86, i32 0, i32 0
  %88 = load ptr, ptr %87, align 8, !tbaa !20
  %89 = getelementptr inbounds %struct.DAC_TypeDef, ptr %88, i32 0, i32 0
  %90 = load volatile i32, ptr %89, align 4, !tbaa !21
  %91 = zext i32 %90 to i64
  %92 = or i64 %91, 268435456
  %93 = trunc i64 %92 to i32
  store volatile i32 %93, ptr %89, align 4, !tbaa !21
  %94 = load i32, ptr %11, align 4, !tbaa !9
  switch i32 %94, label %113 [
    i32 0, label %95
    i32 4, label %101
    i32 8, label %107
  ]

95:                                               ; preds = %73
  %96 = load ptr, ptr %7, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %96, i32 0, i32 0
  %98 = load ptr, ptr %97, align 8, !tbaa !20
  %99 = getelementptr inbounds %struct.DAC_TypeDef, ptr %98, i32 0, i32 5
  %100 = ptrtoint ptr %99 to i32
  store i32 %100, ptr %13, align 4, !tbaa !9
  br label %114

101:                                              ; preds = %73
  %102 = load ptr, ptr %7, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !20
  %105 = getelementptr inbounds %struct.DAC_TypeDef, ptr %104, i32 0, i32 6
  %106 = ptrtoint ptr %105 to i32
  store i32 %106, ptr %13, align 4, !tbaa !9
  br label %114

107:                                              ; preds = %73
  %108 = load ptr, ptr %7, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %108, i32 0, i32 0
  %110 = load ptr, ptr %109, align 8, !tbaa !20
  %111 = getelementptr inbounds %struct.DAC_TypeDef, ptr %110, i32 0, i32 7
  %112 = ptrtoint ptr %111 to i32
  store i32 %112, ptr %13, align 4, !tbaa !9
  br label %114

113:                                              ; preds = %73
  br label %114

114:                                              ; preds = %113, %107, %101, %95
  br label %115

115:                                              ; preds = %114, %72
  %116 = load i32, ptr %8, align 4, !tbaa !9
  %117 = icmp eq i32 %116, 0
  br i1 %117, label %118, label %135

118:                                              ; preds = %115
  %119 = load ptr, ptr %7, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !20
  %122 = getelementptr inbounds %struct.DAC_TypeDef, ptr %121, i32 0, i32 0
  %123 = load volatile i32, ptr %122, align 4, !tbaa !21
  %124 = zext i32 %123 to i64
  %125 = or i64 %124, 8192
  %126 = trunc i64 %125 to i32
  store volatile i32 %126, ptr %122, align 4, !tbaa !21
  %127 = load ptr, ptr %7, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %127, i32 0, i32 3
  %129 = load ptr, ptr %128, align 8, !tbaa !14
  %130 = load ptr, ptr %9, align 8, !tbaa !5
  %131 = ptrtoint ptr %130 to i32
  %132 = load i32, ptr %13, align 4, !tbaa !9
  %133 = load i32, ptr %10, align 4, !tbaa !9
  %134 = call i32 @HAL_DMA_Start_IT(ptr noundef %129, i32 noundef %131, i32 noundef %132, i32 noundef %133)
  store i32 %134, ptr %12, align 4, !tbaa !9
  br label %152

135:                                              ; preds = %115
  %136 = load ptr, ptr %7, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %136, i32 0, i32 0
  %138 = load ptr, ptr %137, align 8, !tbaa !20
  %139 = getelementptr inbounds %struct.DAC_TypeDef, ptr %138, i32 0, i32 0
  %140 = load volatile i32, ptr %139, align 4, !tbaa !21
  %141 = zext i32 %140 to i64
  %142 = or i64 %141, 536870912
  %143 = trunc i64 %142 to i32
  store volatile i32 %143, ptr %139, align 4, !tbaa !21
  %144 = load ptr, ptr %7, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %144, i32 0, i32 4
  %146 = load ptr, ptr %145, align 8, !tbaa !23
  %147 = load ptr, ptr %9, align 8, !tbaa !5
  %148 = ptrtoint ptr %147 to i32
  %149 = load i32, ptr %13, align 4, !tbaa !9
  %150 = load i32, ptr %10, align 4, !tbaa !9
  %151 = call i32 @HAL_DMA_Start_IT(ptr noundef %146, i32 noundef %148, i32 noundef %149, i32 noundef %150)
  store i32 %151, ptr %12, align 4, !tbaa !9
  br label %152

152:                                              ; preds = %135, %118
  br label %153

153:                                              ; preds = %152
  %154 = load ptr, ptr %7, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %154, i32 0, i32 2
  store i32 0, ptr %155, align 4, !tbaa !11
  br label %156

156:                                              ; preds = %153
  br label %157

157:                                              ; preds = %156
  %158 = load i32, ptr %12, align 4, !tbaa !9
  %159 = icmp eq i32 %158, 0
  br i1 %159, label %160, label %173

160:                                              ; preds = %157
  %161 = load i32, ptr %8, align 4, !tbaa !9
  %162 = zext i32 %161 to i64
  %163 = and i64 %162, 16
  %164 = shl i64 1, %163
  %165 = load ptr, ptr %7, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %165, i32 0, i32 0
  %167 = load ptr, ptr %166, align 8, !tbaa !20
  %168 = getelementptr inbounds %struct.DAC_TypeDef, ptr %167, i32 0, i32 0
  %169 = load volatile i32, ptr %168, align 4, !tbaa !21
  %170 = zext i32 %169 to i64
  %171 = or i64 %170, %164
  %172 = trunc i64 %171 to i32
  store volatile i32 %172, ptr %168, align 4, !tbaa !21
  br label %178

173:                                              ; preds = %157
  %174 = load ptr, ptr %7, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.DAC_HandleTypeDef, ptr %174, i32 0, i32 5
  %176 = load volatile i32, ptr %175, align 8, !tbaa !24
  %177 = or i32 %176, 4
  store volatile i32 %177, ptr %175, align 8, !tbaa !24
  br label %178

178:                                              ; preds = %173, %160
  %179 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %179, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %180

180:                                              ; preds = %178, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  %181 = load i32, ptr %6, align 4
  ret i32 %181
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAConvCpltCh1(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAHalfConvCpltCh1(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAErrorCh1(ptr noundef) #0

declare void @DAC_DMAConvCpltCh2(ptr noundef) #2

declare void @DAC_DMAHalfConvCpltCh2(ptr noundef) #2

declare void @DAC_DMAErrorCh2(ptr noundef) #2

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 12}
!12 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12, !6, i64 16, !6, i64 24, !10, i64 32}
!13 = !{!12, !10, i64 8}
!14 = !{!12, !6, i64 16}
!15 = !{!16, !6, i64 72}
!16 = !{!"__DMA_HandleTypeDef", !6, i64 0, !17, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!18 = !{!16, !6, i64 80}
!19 = !{!16, !6, i64 104}
!20 = !{!12, !6, i64 0}
!21 = !{!22, !10, i64 0}
!22 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76}
!23 = !{!12, !6, i64 24}
!24 = !{!12, !10, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DAC_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = getelementptr inbounds i8, ptr %0, i64 12
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = icmp eq i32 %7, 1
  br i1 %8, label %78, label %9

9:                                                ; preds = %5
  store i32 1, ptr %6, align 4, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %0, i64 8
  store volatile i32 2, ptr %10, align 8, !tbaa !11
  %11 = icmp eq i32 %1, 0
  br i1 %11, label %12, label %33

12:                                               ; preds = %9
  %13 = getelementptr inbounds i8, ptr %0, i64 16
  %14 = load ptr, ptr %13, align 8, !tbaa !12
  %15 = getelementptr inbounds i8, ptr %14, i64 72
  store ptr @DAC_DMAConvCpltCh1, ptr %15, align 8, !tbaa !13
  %16 = getelementptr inbounds i8, ptr %14, i64 80
  store ptr @DAC_DMAHalfConvCpltCh1, ptr %16, align 8, !tbaa !16
  %17 = getelementptr inbounds i8, ptr %14, i64 104
  store ptr @DAC_DMAErrorCh1, ptr %17, align 8, !tbaa !17
  %18 = load ptr, ptr %0, align 8, !tbaa !18
  %19 = load volatile i32, ptr %18, align 4, !tbaa !19
  %20 = or i32 %19, 4096
  store volatile i32 %20, ptr %18, align 4, !tbaa !19
  switch i32 %4, label %54 [
    i32 0, label %21
    i32 4, label %25
    i32 8, label %29
  ]

21:                                               ; preds = %12
  %22 = getelementptr inbounds i8, ptr %18, i64 8
  %23 = ptrtoint ptr %22 to i64
  %24 = trunc i64 %23 to i32
  br label %54

25:                                               ; preds = %12
  %26 = getelementptr inbounds i8, ptr %18, i64 12
  %27 = ptrtoint ptr %26 to i64
  %28 = trunc i64 %27 to i32
  br label %54

29:                                               ; preds = %12
  %30 = getelementptr inbounds i8, ptr %18, i64 16
  %31 = ptrtoint ptr %30 to i64
  %32 = trunc i64 %31 to i32
  br label %54

33:                                               ; preds = %9
  %34 = getelementptr inbounds i8, ptr %0, i64 24
  %35 = load ptr, ptr %34, align 8, !tbaa !21
  %36 = getelementptr inbounds i8, ptr %35, i64 72
  store ptr @DAC_DMAConvCpltCh2, ptr %36, align 8, !tbaa !13
  %37 = getelementptr inbounds i8, ptr %35, i64 80
  store ptr @DAC_DMAHalfConvCpltCh2, ptr %37, align 8, !tbaa !16
  %38 = getelementptr inbounds i8, ptr %35, i64 104
  store ptr @DAC_DMAErrorCh2, ptr %38, align 8, !tbaa !17
  %39 = load ptr, ptr %0, align 8, !tbaa !18
  %40 = load volatile i32, ptr %39, align 4, !tbaa !19
  %41 = or i32 %40, 268435456
  store volatile i32 %41, ptr %39, align 4, !tbaa !19
  switch i32 %4, label %60 [
    i32 0, label %42
    i32 4, label %46
    i32 8, label %50
  ]

42:                                               ; preds = %33
  %43 = getelementptr inbounds i8, ptr %39, i64 20
  %44 = ptrtoint ptr %43 to i64
  %45 = trunc i64 %44 to i32
  br label %60

46:                                               ; preds = %33
  %47 = getelementptr inbounds i8, ptr %39, i64 24
  %48 = ptrtoint ptr %47 to i64
  %49 = trunc i64 %48 to i32
  br label %60

50:                                               ; preds = %33
  %51 = getelementptr inbounds i8, ptr %39, i64 28
  %52 = ptrtoint ptr %51 to i64
  %53 = trunc i64 %52 to i32
  br label %60

54:                                               ; preds = %21, %25, %29, %12
  %.0.ph = phi i32 [ %24, %21 ], [ %28, %25 ], [ %32, %29 ], [ 0, %12 ]
  %55 = load volatile i32, ptr %18, align 4, !tbaa !19
  %56 = or i32 %55, 8192
  store volatile i32 %56, ptr %18, align 4, !tbaa !19
  %57 = ptrtoint ptr %2 to i64
  %58 = trunc i64 %57 to i32
  %59 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %14, i32 noundef %58, i32 noundef %.0.ph, i32 noundef %3) #2
  br label %66

60:                                               ; preds = %33, %50, %46, %42
  %.0 = phi i32 [ 0, %33 ], [ %53, %50 ], [ %49, %46 ], [ %45, %42 ]
  %61 = load volatile i32, ptr %39, align 4, !tbaa !19
  %62 = or i32 %61, 536870912
  store volatile i32 %62, ptr %39, align 4, !tbaa !19
  %63 = ptrtoint ptr %2 to i64
  %64 = trunc i64 %63 to i32
  %65 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %35, i32 noundef %64, i32 noundef %.0, i32 noundef %3) #2
  br label %66

66:                                               ; preds = %54, %60
  %.037 = phi i32 [ %59, %54 ], [ %65, %60 ]
  store i32 0, ptr %6, align 4, !tbaa !5
  %67 = icmp eq i32 %.037, 0
  br i1 %67, label %68, label %74

68:                                               ; preds = %66
  %69 = and i32 %1, 16
  %70 = shl nuw nsw i32 1, %69
  %71 = load ptr, ptr %0, align 8, !tbaa !18
  %72 = load volatile i32, ptr %71, align 4, !tbaa !19
  %73 = or i32 %72, %70
  store volatile i32 %73, ptr %71, align 4, !tbaa !19
  br label %78

74:                                               ; preds = %66
  %75 = getelementptr inbounds i8, ptr %0, i64 32
  %76 = load volatile i32, ptr %75, align 8, !tbaa !22
  %77 = or i32 %76, 4
  store volatile i32 %77, ptr %75, align 8, !tbaa !22
  br label %78

78:                                               ; preds = %68, %74, %5
  %.038 = phi i32 [ 2, %5 ], [ %.037, %74 ], [ 0, %68 ]
  ret i32 %.038
}

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAConvCpltCh1(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAHalfConvCpltCh1(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DAC_DMAErrorCh1(ptr noundef) #0

declare void @DAC_DMAConvCpltCh2(ptr noundef) #1

declare void @DAC_DMAHalfConvCpltCh2(ptr noundef) #1

declare void @DAC_DMAErrorCh2(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 12}
!6 = !{!"", !7, i64 0, !10, i64 8, !10, i64 12, !7, i64 16, !7, i64 24, !10, i64 32}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!6, !10, i64 8}
!12 = !{!6, !7, i64 16}
!13 = !{!14, !7, i64 72}
!14 = !{!"__DMA_HandleTypeDef", !7, i64 0, !15, i64 8, !10, i64 56, !10, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !7, i64 136, !7, i64 144, !10, i64 152, !7, i64 160, !7, i64 168, !10, i64 176}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!16 = !{!14, !7, i64 80}
!17 = !{!14, !7, i64 104}
!18 = !{!6, !7, i64 0}
!19 = !{!20, !10, i64 0}
!20 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76}
!21 = !{!6, !7, i64 24}
!22 = !{!6, !10, i64 32}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass