; LLVM IR from simbody/simbody :: SimTKcommon/src/ParallelWorkQueue.ll (ZNK5SimTK21ParallelWorkQueueImpl5cloneEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.SimTK::ParallelWorkQueueImpl" = type { %"class.SimTK::PIMPLImplementation.base", i32, i32, i8, %"class.std::queue", %"class.std::mutex", %"class.std::condition_variable", %"class.std::condition_variable", %"class.SimTK::Array_" }
%"class.SimTK::PIMPLImplementation.base" = type <{ ptr, i32 }>
%"class.std::queue" = type { %"class.std::deque" }
%"class.std::deque" = type { %"class.std::_Deque_base" }
%"class.std::_Deque_base" = type { %"struct.std::_Deque_base<SimTK::ParallelWorkQueue::Task *, std::allocator<SimTK::ParallelWorkQueue::Task *>>::_Deque_impl" }
%"struct.std::_Deque_base<SimTK::ParallelWorkQueue::Task *, std::allocator<SimTK::ParallelWorkQueue::Task *>>::_Deque_impl" = type { %"struct.std::_Deque_base<SimTK::ParallelWorkQueue::Task *, std::allocator<SimTK::ParallelWorkQueue::Task *>>::_Deque_impl_data" }
%"struct.std::_Deque_base<SimTK::ParallelWorkQueue::Task *, std::allocator<SimTK::ParallelWorkQueue::Task *>>::_Deque_impl_data" = type { ptr, i64, %"struct.std::_Deque_iterator", %"struct.std::_Deque_iterator" }
%"struct.std::_Deque_iterator" = type { ptr, ptr, ptr, ptr }
%"class.std::mutex" = type { %"class.std::__mutex_base" }
%"class.std::__mutex_base" = type { %union.pthread_mutex_t }
%union.pthread_mutex_t = type { %struct.__pthread_mutex_s }
%struct.__pthread_mutex_s = type { i32, i32, i32, i32, i32, i16, i16, %struct.__pthread_internal_list }
%struct.__pthread_internal_list = type { ptr, ptr }
%"class.std::condition_variable" = type { %"class.std::__condvar" }
%"class.std::__condvar" = type { %union.pthread_cond_t }
%union.pthread_cond_t = type { %struct.__pthread_cond_s }
%struct.__pthread_cond_s = type { %union.__atomic_wide_counter, %union.__atomic_wide_counter, [2 x i32], [2 x i32], i32, i32, [2 x i32] }
%union.__atomic_wide_counter = type { i64 }
%"class.SimTK::Array_" = type { %"class.SimTK::ArrayView_" }
%"class.SimTK::ArrayView_" = type { %"class.SimTK::ArrayViewConst_" }
%"class.SimTK::ArrayViewConst_" = type { ptr, i32, i32 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5SimTK6Array_ISt6threadjE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16)) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZNK5SimTK21ParallelWorkQueueImpl5cloneEv(ptr noundef nonnull align 8 dereferenceable(256) %0) #1 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  %6 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 256) #4
  %7 = getelementptr inbounds %"class.SimTK::ParallelWorkQueueImpl", ptr %5, i32 0, i32 1
  %8 = load i32, ptr %7, align 4, !tbaa !9
  %9 = getelementptr inbounds %"class.SimTK::ParallelWorkQueueImpl", ptr %5, i32 0, i32 8
  %10 = invoke noundef i32 @_ZNK5SimTK6Array_ISt6threadjE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %9)
          to label %11 unwind label %13

11:                                               ; preds = %1
  invoke void @_ZN5SimTK21ParallelWorkQueueImplC1Eii(ptr noundef nonnull align 8 dereferenceable(256) %6, i32 noundef %8, i32 noundef %10)
          to label %12 unwind label %13

12:                                               ; preds = %11
  ret ptr %6

13:                                               ; preds = %11, %1
  %14 = landingpad { ptr, i32 }
          cleanup
  %15 = extractvalue { ptr, i32 } %14, 0
  store ptr %15, ptr %3, align 8
  %16 = extractvalue { ptr, i32 } %14, 1
  store i32 %16, ptr %4, align 4
  call void @_ZdlPvm(ptr noundef %6, i64 noundef 256) #5
  br label %17

17:                                               ; preds = %13
  %18 = load ptr, ptr %3, align 8
  %19 = load i32, ptr %4, align 4
  %20 = insertvalue { ptr, i32 } poison, ptr %18, 0
  %21 = insertvalue { ptr, i32 } %20, i32 %19, 1
  resume { ptr, i32 } %21
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #3

declare void @_ZN5SimTK21ParallelWorkQueueImplC1Eii(ptr, i32, i32)

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 12}
!10 = !{!"_ZTSN5SimTK21ParallelWorkQueueImplE", !11, i64 0, !12, i64 12, !12, i64 16, !13, i64 20, !14, i64 24, !21, i64 104, !23, i64 144, !23, i64 192, !25, i64 240}
!11 = !{!"_ZTSN5SimTK19PIMPLImplementationINS_17ParallelWorkQueueENS_21ParallelWorkQueueImplEEE", !6, i64 0, !12, i64 8}
!12 = !{!"int", !7, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{!"_ZTSSt5queueIPN5SimTK17ParallelWorkQueue4TaskESt5dequeIS3_SaIS3_EEE", !15, i64 0}
!15 = !{!"_ZTSSt5dequeIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE", !16, i64 0}
!16 = !{!"_ZTSSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE", !17, i64 0}
!17 = !{!"_ZTSNSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE11_Deque_implE", !18, i64 0}
!18 = !{!"_ZTSNSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE16_Deque_impl_dataE", !6, i64 0, !19, i64 8, !20, i64 16, !20, i64 48}
!19 = !{!"long", !7, i64 0}
!20 = !{!"_ZTSSt15_Deque_iteratorIPN5SimTK17ParallelWorkQueue4TaskERS3_PS3_E", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!21 = !{!"_ZTSSt5mutex", !22, i64 0}
!22 = !{!"_ZTSSt12__mutex_base", !7, i64 0}
!23 = !{!"_ZTSSt18condition_variable", !24, i64 0}
!24 = !{!"_ZTSSt9__condvar", !7, i64 0}
!25 = !{!"_ZTSN5SimTK6Array_ISt6threadjEE", !26, i64 0}
!26 = !{!"_ZTSN5SimTK10ArrayView_ISt6threadjEE", !27, i64 0}
!27 = !{!"_ZTSN5SimTK15ArrayViewConst_ISt6threadjEE", !6, i64 0, !12, i64 8, !12, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK5SimTK6Array_ISt6threadjE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef nonnull ptr @_ZNK5SimTK21ParallelWorkQueueImpl5cloneEv(ptr noundef nonnull align 8 dereferenceable(256) %0) local_unnamed_addr #1 align 2 personality ptr @__gxx_personality_v0 {
  %2 = tail call noalias noundef nonnull dereferenceable(256) ptr @_Znwm(i64 noundef 256) #4
  %3 = getelementptr inbounds i8, ptr %0, i64 12
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 240
  %6 = tail call noundef i32 @_ZNK5SimTK6Array_ISt6threadjE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %5)
  invoke void @_ZN5SimTK21ParallelWorkQueueImplC1Eii(ptr noundef nonnull align 8 dereferenceable(256) %2, i32 noundef %4, i32 noundef %6)
          to label %7 unwind label %8

7:                                                ; preds = %1
  ret ptr %2

8:                                                ; preds = %1
  %9 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZdlPvm(ptr noundef nonnull %2, i64 noundef 256) #5
  resume { ptr, i32 } %9
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #2

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #3

declare void @_ZN5SimTK21ParallelWorkQueueImplC1Eii(ptr, i32, i32) local_unnamed_addr

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 12}
!6 = !{!"_ZTSN5SimTK21ParallelWorkQueueImplE", !7, i64 0, !11, i64 12, !11, i64 16, !12, i64 20, !13, i64 24, !20, i64 104, !22, i64 144, !22, i64 192, !24, i64 240}
!7 = !{!"_ZTSN5SimTK19PIMPLImplementationINS_17ParallelWorkQueueENS_21ParallelWorkQueueImplEEE", !8, i64 0, !11, i64 8}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"bool", !9, i64 0}
!13 = !{!"_ZTSSt5queueIPN5SimTK17ParallelWorkQueue4TaskESt5dequeIS3_SaIS3_EEE", !14, i64 0}
!14 = !{!"_ZTSSt5dequeIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE", !15, i64 0}
!15 = !{!"_ZTSSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE", !16, i64 0}
!16 = !{!"_ZTSNSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE11_Deque_implE", !17, i64 0}
!17 = !{!"_ZTSNSt11_Deque_baseIPN5SimTK17ParallelWorkQueue4TaskESaIS3_EE16_Deque_impl_dataE", !8, i64 0, !18, i64 8, !19, i64 16, !19, i64 48}
!18 = !{!"long", !9, i64 0}
!19 = !{!"_ZTSSt15_Deque_iteratorIPN5SimTK17ParallelWorkQueue4TaskERS3_PS3_E", !8, i64 0, !8, i64 8, !8, i64 16, !8, i64 24}
!20 = !{!"_ZTSSt5mutex", !21, i64 0}
!21 = !{!"_ZTSSt12__mutex_base", !9, i64 0}
!22 = !{!"_ZTSSt18condition_variable", !23, i64 0}
!23 = !{!"_ZTSSt9__condvar", !9, i64 0}
!24 = !{!"_ZTSN5SimTK6Array_ISt6threadjEE", !25, i64 0}
!25 = !{!"_ZTSN5SimTK10ArrayView_ISt6threadjEE", !26, i64 0}
!26 = !{!"_ZTSN5SimTK15ArrayViewConst_ISt6threadjEE", !8, i64 0, !11, i64 8, !11, i64 12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass