; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src/ASwitch.ll (ZN7ASwitch14receive_fwlinkEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.ASwitch = type { %class.Unit, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, %"class.std::vector", i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, i32, i32, i8, i8, i8, i32, [4 x i8], %class.ASwitchStats }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%class.ASwitchStats = type <{ %class.Stats, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
%class.Stats = type { ptr }

@.str.1 = external hidden unnamed_addr constant [90 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [29 x i8], align 1
@__PRETTY_FUNCTION__._ZN7ASwitch14receive_fwlinkEv = external hidden unnamed_addr constant [31 x i8], align 1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64)) #3

declare void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector") align 8, ptr noundef nonnull align 8 dereferenceable(64)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

declare void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7ASwitch14receive_fwlinkEv(ptr noundef nonnull align 8 dereferenceable(288) %0) #4 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca %"class.std::vector", align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %7 = load ptr, ptr %2, align 8
  %8 = getelementptr inbounds %class.ASwitch, ptr %7, i32 0, i32 26
  %9 = load i8, ptr %8, align 8, !tbaa !9, !range !26, !noundef !27
  %10 = trunc i8 %9 to i1
  br i1 %10, label %11, label %51

11:                                               ; preds = %1
  %12 = getelementptr inbounds %class.ASwitch, ptr %7, i32 0, i32 25
  %13 = load i32, ptr %12, align 4, !tbaa !28
  %14 = icmp eq i32 %13, 0
  br i1 %14, label %15, label %51

15:                                               ; preds = %11
  %16 = getelementptr inbounds %class.ASwitch, ptr %7, i32 0, i32 23
  %17 = load ptr, ptr %16, align 8, !tbaa !29
  %18 = call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %17)
  br i1 %18, label %19, label %50

19:                                               ; preds = %15
  call void @llvm.lifetime.start.p0(i64 24, ptr %3) #5
  %20 = getelementptr inbounds %class.ASwitch, ptr %7, i32 0, i32 23
  %21 = load ptr, ptr %20, align 8, !tbaa !29
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector") align 8 %3, ptr noundef nonnull align 8 dereferenceable(64) %21)
  %22 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  %23 = icmp eq i64 %22, 1
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  br label %27

25:                                               ; preds = %19
  call void @__assert_fail(ptr noundef @.str.3, ptr noundef @.str.1, i32 noundef 290, ptr noundef @__PRETTY_FUNCTION__._ZN7ASwitch14receive_fwlinkEv) #6
  unreachable

26:                                               ; No predecessors!
  br label %27

27:                                               ; preds = %26, %24
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  store i32 0, ptr %4, align 4, !tbaa !30
  br label %28

28:                                               ; preds = %42, %27
  %29 = load i32, ptr %4, align 4, !tbaa !30
  %30 = sext i32 %29 to i64
  %31 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  %32 = icmp ult i64 %30, %31
  br i1 %32, label %34, label %33

33:                                               ; preds = %28
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  br label %49

34:                                               ; preds = %28
  %35 = getelementptr inbounds %class.ASwitch, ptr %7, i32 0, i32 14
  %36 = load ptr, ptr %35, align 8, !tbaa !31
  %37 = load i32, ptr %4, align 4, !tbaa !30
  %38 = sext i32 %37 to i64
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %38) #5
  %40 = load ptr, ptr %39, align 8, !tbaa !5
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %36, ptr noundef %40)
          to label %41 unwind label %45

41:                                               ; preds = %34
  br label %42

42:                                               ; preds = %41
  %43 = load i32, ptr %4, align 4, !tbaa !30
  %44 = add nsw i32 %43, 1
  store i32 %44, ptr %4, align 4, !tbaa !30
  br label %28, !llvm.loop !32

45:                                               ; preds = %34
  %46 = landingpad { ptr, i32 }
          cleanup
  %47 = extractvalue { ptr, i32 } %46, 0
  store ptr %47, ptr %5, align 8
  %48 = extractvalue { ptr, i32 } %46, 1
  store i32 %48, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr %3) #5
  br label %52

49:                                               ; preds = %33
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr %3) #5
  br label %50

50:                                               ; preds = %49, %15
  br label %51

51:                                               ; preds = %50, %11, %1
  ret void

52:                                               ; preds = %45
  %53 = load ptr, ptr %5, align 8
  %54 = load i32, ptr %6, align 4
  %55 = insertvalue { ptr, i32 } poison, ptr %53, 0
  %56 = insertvalue { ptr, i32 } %55, i32 %54, 1
  resume { ptr, i32 } %56
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !21, i64 216}
!10 = !{!"_ZTS7ASwitch", !11, i64 0, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !16, i64 136, !12, i64 160, !6, i64 168, !6, i64 176, !6, i64 184, !6, i64 192, !6, i64 200, !12, i64 208, !20, i64 212, !21, i64 216, !22, i64 220, !23, i64 224, !21, i64 228, !21, i64 229, !21, i64 230, !12, i64 232, !24, i64 240}
!11 = !{!"_ZTS4Unit", !12, i64 8, !13, i64 16}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTS4fl_t", !7, i64 0}
!21 = !{!"bool", !7, i64 0}
!22 = !{!"_ZTS13adderconfig_t", !7, i64 0}
!23 = !{!"_ZTS16adderoperation_t", !7, i64 0}
!24 = !{!"_ZTS12ASwitchStats", !25, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40}
!25 = !{!"_ZTS5Stats"}
!26 = !{i8 0, i8 2}
!27 = !{}
!28 = !{!10, !20, i64 212}
!29 = !{!10, !6, i64 200}
!30 = !{!12, !12, i64 0}
!31 = !{!10, !6, i64 112}
!32 = distinct !{!32, !33}
!33 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.1 = external hidden unnamed_addr constant [90 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [29 x i8], align 1
@__PRETTY_FUNCTION__._ZN7ASwitch14receive_fwlinkEv = external hidden unnamed_addr constant [31 x i8], align 1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #3

declare void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector") align 8, ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

declare void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7ASwitch14receive_fwlinkEv(ptr nocapture noundef nonnull readonly align 8 dereferenceable(288) %0) local_unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"class.std::vector", align 8
  %3 = getelementptr inbounds i8, ptr %0, i64 216
  %4 = load i8, ptr %3, align 8, !tbaa !5, !range !25, !noundef !26
  %5 = trunc nuw i8 %4 to i1
  %6 = getelementptr inbounds i8, ptr %0, i64 212
  %7 = load i32, ptr %6, align 4
  %8 = icmp eq i32 %7, 0
  %or.cond = select i1 %5, i1 %8, i1 false
  br i1 %or.cond, label %9, label %29

9:                                                ; preds = %1
  %10 = getelementptr inbounds i8, ptr %0, i64 200
  %11 = load ptr, ptr %10, align 8, !tbaa !27
  %12 = tail call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %11)
  br i1 %12, label %13, label %29

13:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %2) #5
  %14 = load ptr, ptr %10, align 8, !tbaa !27
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind nonnull writable sret(%"class.std::vector") align 8 %2, ptr noundef nonnull align 8 dereferenceable(64) %14)
  %15 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  %16 = icmp eq i64 %15, 1
  br i1 %16, label %.preheader, label %19

.preheader:                                       ; preds = %13
  %17 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  %.not = icmp eq i64 %17, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader
  %18 = getelementptr inbounds i8, ptr %0, i64 112
  br label %20

19:                                               ; preds = %13
  call void @__assert_fail(ptr noundef nonnull @.str.3, ptr noundef nonnull @.str.1, i32 noundef 290, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN7ASwitch14receive_fwlinkEv) #6
  unreachable

._crit_edge:                                      ; preds = %24, %.preheader
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #5
  br label %29

20:                                               ; preds = %.lr.ph, %24
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %24 ]
  %21 = load ptr, ptr %18, align 8, !tbaa !28
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #5
  %23 = load ptr, ptr %22, align 8, !tbaa !29
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %21, ptr noundef %23)
          to label %24 unwind label %27

24:                                               ; preds = %20
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %25 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  %26 = icmp ugt i64 %25, %indvars.iv.next
  br i1 %26, label %20, label %._crit_edge, !llvm.loop !30

27:                                               ; preds = %20
  %28 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #5
  resume { ptr, i32 } %28

29:                                               ; preds = %9, %._crit_edge, %1
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !20, i64 216}
!6 = !{!"_ZTS7ASwitch", !7, i64 0, !8, i64 48, !8, i64 52, !8, i64 56, !8, i64 60, !8, i64 64, !8, i64 68, !8, i64 72, !8, i64 76, !8, i64 80, !8, i64 84, !8, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !15, i64 136, !8, i64 160, !13, i64 168, !13, i64 176, !13, i64 184, !13, i64 192, !13, i64 200, !8, i64 208, !19, i64 212, !20, i64 216, !21, i64 220, !22, i64 224, !20, i64 228, !20, i64 229, !20, i64 230, !8, i64 232, !23, i64 240}
!7 = !{!"_ZTS4Unit", !8, i64 8, !11, i64 16}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !14, i64 8, !9, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!13 = !{!"any pointer", !9, i64 0}
!14 = !{!"long", !9, i64 0}
!15 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!19 = !{!"_ZTS4fl_t", !9, i64 0}
!20 = !{!"bool", !9, i64 0}
!21 = !{!"_ZTS13adderconfig_t", !9, i64 0}
!22 = !{!"_ZTS16adderoperation_t", !9, i64 0}
!23 = !{!"_ZTS12ASwitchStats", !24, i64 0, !8, i64 8, !8, i64 12, !8, i64 16, !8, i64 20, !8, i64 24, !8, i64 28, !8, i64 32, !8, i64 36, !8, i64 40}
!24 = !{!"_ZTS5Stats"}
!25 = !{i8 0, i8 2}
!26 = !{}
!27 = !{!6, !13, i64 200}
!28 = !{!6, !13, i64 112}
!29 = !{!13, !13, i64 0}
!30 = distinct !{!30, !31}
!31 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass