; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Block)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Erase_Block(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %8, i32 0, i32 3
  %10 = load volatile i32, ptr %9, align 8, !tbaa !9
  %11 = icmp eq i32 %10, 2
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %140

13:                                               ; preds = %2
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %14, i32 0, i32 3
  %16 = load volatile i32, ptr %15, align 8, !tbaa !9
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %18, label %137

18:                                               ; preds = %13
  br label %19

19:                                               ; preds = %18
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %20, i32 0, i32 2
  %22 = load i32, ptr %21, align 4, !tbaa !13
  %23 = icmp eq i32 %22, 1
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %140

25:                                               ; preds = %19
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %26, i32 0, i32 2
  store i32 1, ptr %27, align 4, !tbaa !13
  br label %28

28:                                               ; preds = %25
  br label %29

29:                                               ; preds = %28
  br label %30

30:                                               ; preds = %29
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %31, i32 0, i32 3
  store volatile i32 2, ptr %32, align 8, !tbaa !9
  store i32 -2147483648, ptr %6, align 4, !tbaa !14
  %33 = load i32, ptr %6, align 4, !tbaa !14
  %34 = or i32 %33, 65536
  %35 = zext i32 %34 to i64
  %36 = inttoptr i64 %35 to ptr
  store volatile i8 96, ptr %36, align 1, !tbaa !15
  call void @__DSB()
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %37, i32 0, i32 0
  %39 = load i16, ptr %38, align 2, !tbaa !16
  %40 = zext i16 %39 to i32
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %41, i32 0, i32 2
  %43 = load i16, ptr %42, align 2, !tbaa !19
  %44 = zext i16 %43 to i32
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %45, i32 0, i32 1
  %47 = load i16, ptr %46, align 2, !tbaa !20
  %48 = zext i16 %47 to i32
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %49, i32 0, i32 4
  %51 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %50, i32 0, i32 5
  %52 = load i32, ptr %51, align 4, !tbaa !21
  %53 = mul i32 %48, %52
  %54 = add i32 %44, %53
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %55, i32 0, i32 4
  %57 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %56, i32 0, i32 2
  %58 = load i32, ptr %57, align 4, !tbaa !22
  %59 = mul i32 %54, %58
  %60 = add i32 %40, %59
  %61 = trunc i32 %60 to i8
  %62 = load i32, ptr %6, align 4, !tbaa !14
  %63 = or i32 %62, 131072
  %64 = zext i32 %63 to i64
  %65 = inttoptr i64 %64 to ptr
  store volatile i8 %61, ptr %65, align 1, !tbaa !15
  call void @__DSB()
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %66, i32 0, i32 0
  %68 = load i16, ptr %67, align 2, !tbaa !16
  %69 = zext i16 %68 to i32
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %70, i32 0, i32 2
  %72 = load i16, ptr %71, align 2, !tbaa !19
  %73 = zext i16 %72 to i32
  %74 = load ptr, ptr %5, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %74, i32 0, i32 1
  %76 = load i16, ptr %75, align 2, !tbaa !20
  %77 = zext i16 %76 to i32
  %78 = load ptr, ptr %4, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %78, i32 0, i32 4
  %80 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %79, i32 0, i32 5
  %81 = load i32, ptr %80, align 4, !tbaa !21
  %82 = mul i32 %77, %81
  %83 = add i32 %73, %82
  %84 = load ptr, ptr %4, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %84, i32 0, i32 4
  %86 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %85, i32 0, i32 2
  %87 = load i32, ptr %86, align 4, !tbaa !22
  %88 = mul i32 %83, %87
  %89 = add i32 %69, %88
  %90 = lshr i32 %89, 8
  %91 = trunc i32 %90 to i8
  %92 = load i32, ptr %6, align 4, !tbaa !14
  %93 = or i32 %92, 131072
  %94 = zext i32 %93 to i64
  %95 = inttoptr i64 %94 to ptr
  store volatile i8 %91, ptr %95, align 1, !tbaa !15
  call void @__DSB()
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %96, i32 0, i32 0
  %98 = load i16, ptr %97, align 2, !tbaa !16
  %99 = zext i16 %98 to i32
  %100 = load ptr, ptr %5, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %100, i32 0, i32 2
  %102 = load i16, ptr %101, align 2, !tbaa !19
  %103 = zext i16 %102 to i32
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %104, i32 0, i32 1
  %106 = load i16, ptr %105, align 2, !tbaa !20
  %107 = zext i16 %106 to i32
  %108 = load ptr, ptr %4, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %108, i32 0, i32 4
  %110 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %109, i32 0, i32 5
  %111 = load i32, ptr %110, align 4, !tbaa !21
  %112 = mul i32 %107, %111
  %113 = add i32 %103, %112
  %114 = load ptr, ptr %4, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %114, i32 0, i32 4
  %116 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %115, i32 0, i32 2
  %117 = load i32, ptr %116, align 4, !tbaa !22
  %118 = mul i32 %113, %117
  %119 = add i32 %99, %118
  %120 = lshr i32 %119, 16
  %121 = trunc i32 %120 to i8
  %122 = load i32, ptr %6, align 4, !tbaa !14
  %123 = or i32 %122, 131072
  %124 = zext i32 %123 to i64
  %125 = inttoptr i64 %124 to ptr
  store volatile i8 %121, ptr %125, align 1, !tbaa !15
  call void @__DSB()
  %126 = load i32, ptr %6, align 4, !tbaa !14
  %127 = or i32 %126, 65536
  %128 = zext i32 %127 to i64
  %129 = inttoptr i64 %128 to ptr
  store volatile i8 -48, ptr %129, align 1, !tbaa !15
  call void @__DSB()
  %130 = load ptr, ptr %4, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %130, i32 0, i32 3
  store volatile i32 1, ptr %131, align 8, !tbaa !9
  br label %132

132:                                              ; preds = %30
  %133 = load ptr, ptr %4, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %133, i32 0, i32 2
  store i32 0, ptr %134, align 4, !tbaa !13
  br label %135

135:                                              ; preds = %132
  br label %136

136:                                              ; preds = %135
  br label %138

137:                                              ; preds = %13
  store i32 1, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %140

138:                                              ; preds = %136
  br label %139

139:                                              ; preds = %138
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %140

140:                                              ; preds = %139, %137, %24, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %141 = load i32, ptr %3, align 4
  ret i32 %141
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 40}
!10 = !{!"", !6, i64 0, !11, i64 8, !12, i64 36, !12, i64 40, !11, i64 44}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 36}
!14 = !{!12, !12, i64 0}
!15 = !{!7, !7, i64 0}
!16 = !{!17, !18, i64 0}
!17 = !{!"", !18, i64 0, !18, i64 2, !18, i64 4}
!18 = !{!"short", !7, i64 0}
!19 = !{!17, !18, i64 4}
!20 = !{!17, !18, i64 2}
!21 = !{!10, !12, i64 64}
!22 = !{!10, !12, i64 52}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_NAND_Erase_Block(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 40
  %4 = load volatile i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 2
  br i1 %5, label %59, label %6

6:                                                ; preds = %2
  %7 = load volatile i32, ptr %3, align 8, !tbaa !5
  %8 = icmp eq i32 %7, 1
  br i1 %8, label %9, label %59

9:                                                ; preds = %6
  %10 = getelementptr inbounds i8, ptr %0, i64 36
  %11 = load i32, ptr %10, align 4, !tbaa !12
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %59, label %13

13:                                               ; preds = %9
  store i32 1, ptr %10, align 4, !tbaa !12
  store volatile i32 2, ptr %3, align 8, !tbaa !5
  store volatile i8 96, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !13
  tail call void @__DSB()
  %14 = load i16, ptr %1, align 2, !tbaa !14
  %15 = zext i16 %14 to i32
  %16 = getelementptr inbounds i8, ptr %1, i64 4
  %17 = load i16, ptr %16, align 2, !tbaa !17
  %18 = zext i16 %17 to i32
  %19 = getelementptr inbounds i8, ptr %1, i64 2
  %20 = load i16, ptr %19, align 2, !tbaa !18
  %21 = zext i16 %20 to i32
  %22 = getelementptr inbounds i8, ptr %0, i64 64
  %23 = load i32, ptr %22, align 4, !tbaa !19
  %24 = mul i32 %23, %21
  %25 = add i32 %24, %18
  %26 = getelementptr inbounds i8, ptr %0, i64 52
  %27 = load i32, ptr %26, align 4, !tbaa !20
  %28 = mul i32 %25, %27
  %29 = add i32 %28, %15
  %30 = trunc i32 %29 to i8
  store volatile i8 %30, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !13
  tail call void @__DSB()
  %31 = load i16, ptr %1, align 2, !tbaa !14
  %32 = zext i16 %31 to i32
  %33 = load i16, ptr %16, align 2, !tbaa !17
  %34 = zext i16 %33 to i32
  %35 = load i16, ptr %19, align 2, !tbaa !18
  %36 = zext i16 %35 to i32
  %37 = load i32, ptr %22, align 4, !tbaa !19
  %38 = mul i32 %37, %36
  %39 = add i32 %38, %34
  %40 = load i32, ptr %26, align 4, !tbaa !20
  %41 = mul i32 %39, %40
  %42 = add i32 %41, %32
  %43 = lshr i32 %42, 8
  %44 = trunc i32 %43 to i8
  store volatile i8 %44, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !13
  tail call void @__DSB()
  %45 = load i16, ptr %1, align 2, !tbaa !14
  %46 = zext i16 %45 to i32
  %47 = load i16, ptr %16, align 2, !tbaa !17
  %48 = zext i16 %47 to i32
  %49 = load i16, ptr %19, align 2, !tbaa !18
  %50 = zext i16 %49 to i32
  %51 = load i32, ptr %22, align 4, !tbaa !19
  %52 = mul i32 %51, %50
  %53 = add i32 %52, %48
  %54 = load i32, ptr %26, align 4, !tbaa !20
  %55 = mul i32 %53, %54
  %56 = add i32 %55, %46
  %57 = lshr i32 %56, 16
  %58 = trunc i32 %57 to i8
  store volatile i8 %58, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !13
  tail call void @__DSB()
  store volatile i8 -48, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !13
  tail call void @__DSB()
  store volatile i32 1, ptr %3, align 8, !tbaa !5
  store i32 0, ptr %10, align 4, !tbaa !12
  br label %59

59:                                               ; preds = %6, %9, %2, %13
  %.0 = phi i32 [ 0, %13 ], [ 2, %2 ], [ 2, %9 ], [ 1, %6 ]
  ret i32 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!8, !8, i64 0}
!14 = !{!15, !16, i64 0}
!15 = !{!"", !16, i64 0, !16, i64 2, !16, i64 4}
!16 = !{!"short", !8, i64 0}
!17 = !{!15, !16, i64 4}
!18 = !{!15, !16, i64 2}
!19 = !{!6, !11, i64 64}
!20 = !{!6, !11, i64 52}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass