; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SRAM_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32, ptr }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SRAM_Write_16b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i8, align 1
  %14 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  store ptr %15, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #2
  %16 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %16, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #2
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %17, i32 0, i32 4
  %19 = load volatile i32, ptr %18, align 8, !tbaa !11
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %91

21:                                               ; preds = %4
  br label %22

22:                                               ; preds = %21
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %23, i32 0, i32 3
  %25 = load i32, ptr %24, align 4, !tbaa !14
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %22
  store i32 2, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %93

28:                                               ; preds = %22
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %29, i32 0, i32 3
  store i32 1, ptr %30, align 4, !tbaa !14
  br label %31

31:                                               ; preds = %28
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %34, i32 0, i32 4
  store volatile i32 2, ptr %35, align 8, !tbaa !11
  %36 = load i32, ptr %9, align 4, !tbaa !9
  %37 = urem i32 %36, 2
  %38 = icmp ne i32 %37, 0
  %39 = zext i1 %38 to i64
  %40 = select i1 %38, i32 1, i32 0
  %41 = trunc i32 %40 to i8
  store i8 %41, ptr %13, align 1, !tbaa !15
  %42 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %42, ptr %10, align 4, !tbaa !9
  br label %43

43:                                               ; preds = %66, %33
  %44 = load i32, ptr %10, align 4, !tbaa !9
  %45 = load i8, ptr %13, align 1, !tbaa !15
  %46 = zext i8 %45 to i32
  %47 = icmp ne i32 %44, %46
  br i1 %47, label %48, label %69

48:                                               ; preds = %43
  %49 = load ptr, ptr %12, align 8, !tbaa !5
  %50 = load i16, ptr %49, align 2, !tbaa !16
  %51 = zext i16 %50 to i32
  %52 = load ptr, ptr %11, align 8, !tbaa !5
  store volatile i32 %51, ptr %52, align 4, !tbaa !9
  %53 = load ptr, ptr %12, align 8, !tbaa !5
  %54 = getelementptr inbounds i16, ptr %53, i32 1
  store ptr %54, ptr %12, align 8, !tbaa !5
  %55 = load ptr, ptr %12, align 8, !tbaa !5
  %56 = load i16, ptr %55, align 2, !tbaa !16
  %57 = zext i16 %56 to i32
  %58 = shl i32 %57, 16
  %59 = load ptr, ptr %11, align 8, !tbaa !5
  %60 = load volatile i32, ptr %59, align 4, !tbaa !9
  %61 = or i32 %60, %58
  store volatile i32 %61, ptr %59, align 4, !tbaa !9
  %62 = load ptr, ptr %12, align 8, !tbaa !5
  %63 = getelementptr inbounds i16, ptr %62, i32 1
  store ptr %63, ptr %12, align 8, !tbaa !5
  %64 = load ptr, ptr %11, align 8, !tbaa !5
  %65 = getelementptr inbounds i32, ptr %64, i32 1
  store ptr %65, ptr %11, align 8, !tbaa !5
  br label %66

66:                                               ; preds = %48
  %67 = load i32, ptr %10, align 4, !tbaa !9
  %68 = sub i32 %67, 2
  store i32 %68, ptr %10, align 4, !tbaa !9
  br label %43, !llvm.loop !18

69:                                               ; preds = %43
  %70 = load i8, ptr %13, align 1, !tbaa !15
  %71 = zext i8 %70 to i32
  %72 = icmp ne i32 %71, 0
  br i1 %72, label %73, label %83

73:                                               ; preds = %69
  %74 = load ptr, ptr %12, align 8, !tbaa !5
  %75 = load i16, ptr %74, align 2, !tbaa !16
  %76 = zext i16 %75 to i32
  %77 = and i32 %76, 65535
  %78 = load ptr, ptr %11, align 8, !tbaa !5
  %79 = load volatile i32, ptr %78, align 4, !tbaa !9
  %80 = and i32 %79, -65536
  %81 = or i32 %77, %80
  %82 = load ptr, ptr %11, align 8, !tbaa !5
  store volatile i32 %81, ptr %82, align 4, !tbaa !9
  br label %83

83:                                               ; preds = %73, %69
  %84 = load ptr, ptr %6, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %84, i32 0, i32 4
  store volatile i32 1, ptr %85, align 8, !tbaa !11
  br label %86

86:                                               ; preds = %83
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %87, i32 0, i32 3
  store i32 0, ptr %88, align 4, !tbaa !14
  br label %89

89:                                               ; preds = %86
  br label %90

90:                                               ; preds = %89
  br label %92

91:                                               ; preds = %4
  store i32 1, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %93

92:                                               ; preds = %90
  store i32 0, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %93

93:                                               ; preds = %92, %91, %27
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %94 = load i32, ptr %5, align 4
  ret i32 %94
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 80}
!12 = !{!"", !6, i64 0, !6, i64 8, !13, i64 16, !10, i64 76, !10, i64 80, !6, i64 88}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!14 = !{!12, !10, i64 76}
!15 = !{!7, !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !7, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SRAM_Write_16b(ptr noundef %0, ptr noundef %1, ptr nocapture noundef readonly %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 80
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 1
  br i1 %7, label %8, label %32

8:                                                ; preds = %4
  %9 = getelementptr inbounds i8, ptr %0, i64 76
  %10 = load i32, ptr %9, align 4, !tbaa !12
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %32, label %12

12:                                               ; preds = %8
  store i32 1, ptr %9, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %13 = and i32 %3, 1
  %.not29 = icmp ult i32 %3, 2
  br i1 %.not29, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %12, %.lr.ph
  %.02432 = phi ptr [ %22, %.lr.ph ], [ %2, %12 ]
  %.02531 = phi ptr [ %23, %.lr.ph ], [ %1, %12 ]
  %.02630 = phi i32 [ %24, %.lr.ph ], [ %3, %12 ]
  %14 = load i16, ptr %.02432, align 2, !tbaa !13
  %15 = zext i16 %14 to i32
  store volatile i32 %15, ptr %.02531, align 4, !tbaa !15
  %16 = getelementptr inbounds i8, ptr %.02432, i64 2
  %17 = load i16, ptr %16, align 2, !tbaa !13
  %18 = zext i16 %17 to i32
  %19 = shl nuw i32 %18, 16
  %20 = load volatile i32, ptr %.02531, align 4, !tbaa !15
  %21 = or i32 %19, %20
  store volatile i32 %21, ptr %.02531, align 4, !tbaa !15
  %22 = getelementptr inbounds i8, ptr %.02432, i64 4
  %23 = getelementptr inbounds i8, ptr %.02531, i64 4
  %24 = add i32 %.02630, -2
  %.not = icmp eq i32 %24, %13
  br i1 %.not, label %._crit_edge, label %.lr.ph, !llvm.loop !16

._crit_edge:                                      ; preds = %.lr.ph, %12
  %.025.lcssa = phi ptr [ %1, %12 ], [ %23, %.lr.ph ]
  %.024.lcssa = phi ptr [ %2, %12 ], [ %22, %.lr.ph ]
  %.not28 = icmp eq i32 %13, 0
  br i1 %.not28, label %31, label %25

25:                                               ; preds = %._crit_edge
  %26 = load i16, ptr %.024.lcssa, align 2, !tbaa !13
  %27 = zext i16 %26 to i32
  %28 = load volatile i32, ptr %.025.lcssa, align 4, !tbaa !15
  %29 = and i32 %28, -65536
  %30 = or disjoint i32 %29, %27
  store volatile i32 %30, ptr %.025.lcssa, align 4, !tbaa !15
  br label %31

31:                                               ; preds = %25, %._crit_edge
  store volatile i32 1, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %9, align 4, !tbaa !12
  br label %32

32:                                               ; preds = %4, %8, %31
  %.0 = phi i32 [ 0, %31 ], [ 2, %8 ], [ 1, %4 ]
  ret i32 %.0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80, !7, i64 88}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!14, !14, i64 0}
!14 = !{!"short", !8, i64 0}
!15 = !{!11, !11, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass