; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (SetPitch)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.LTDC_HandleTypeDef = type { ptr, %struct.LTDC_InitTypeDef, [2 x %struct.LTDC_LayerCfgTypeDef], i32, i32, i32 }
%struct.LTDC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.LTDC_ColorTypeDef }
%struct.LTDC_ColorTypeDef = type { i8, i8, i8, i8 }
%struct.LTDC_LayerCfgTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.LTDC_ColorTypeDef }
%struct.LTDC_Layer_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, [3 x i32], i32 }
%struct.LTDC_TypeDef = type { [2 x i32], i32, i32, i32, i32, i32, [2 x i32], i32, [1 x i32], i32, [1 x i32], i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_LTDC_SetPitch(ptr noundef %0, i32 noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  br label %12

12:                                               ; preds = %3
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %13, i32 0, i32 3
  %15 = load i32, ptr %14, align 4, !tbaa !11
  %16 = icmp eq i32 %15, 1
  br i1 %16, label %17, label %18

17:                                               ; preds = %12
  store i32 2, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %105

18:                                               ; preds = %12
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %19, i32 0, i32 3
  store i32 1, ptr %20, align 4, !tbaa !11
  br label %21

21:                                               ; preds = %18
  br label %22

22:                                               ; preds = %21
  br label %23

23:                                               ; preds = %22
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %24, i32 0, i32 4
  store volatile i32 2, ptr %25, align 8, !tbaa !15
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %26, i32 0, i32 2
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = zext i32 %28 to i64
  %30 = getelementptr inbounds [2 x %struct.LTDC_LayerCfgTypeDef], ptr %27, i64 0, i64 %29
  %31 = getelementptr inbounds %struct.LTDC_LayerCfgTypeDef, ptr %30, i32 0, i32 4
  %32 = load i32, ptr %31, align 4, !tbaa !16
  store i32 %32, ptr %10, align 4, !tbaa !9
  %33 = load i32, ptr %10, align 4, !tbaa !9
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %35, label %36

35:                                               ; preds = %23
  store i32 4, ptr %8, align 4, !tbaa !9
  br label %56

36:                                               ; preds = %23
  %37 = load i32, ptr %10, align 4, !tbaa !9
  %38 = icmp eq i32 %37, 1
  br i1 %38, label %39, label %40

39:                                               ; preds = %36
  store i32 3, ptr %8, align 4, !tbaa !9
  br label %55

40:                                               ; preds = %36
  %41 = load i32, ptr %10, align 4, !tbaa !9
  %42 = icmp eq i32 %41, 4
  br i1 %42, label %52, label %43

43:                                               ; preds = %40
  %44 = load i32, ptr %10, align 4, !tbaa !9
  %45 = icmp eq i32 %44, 2
  br i1 %45, label %52, label %46

46:                                               ; preds = %43
  %47 = load i32, ptr %10, align 4, !tbaa !9
  %48 = icmp eq i32 %47, 3
  br i1 %48, label %52, label %49

49:                                               ; preds = %46
  %50 = load i32, ptr %10, align 4, !tbaa !9
  %51 = icmp eq i32 %50, 7
  br i1 %51, label %52, label %53

52:                                               ; preds = %49, %46, %43, %40
  store i32 2, ptr %8, align 4, !tbaa !9
  br label %54

53:                                               ; preds = %49
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %54

54:                                               ; preds = %53, %52
  br label %55

55:                                               ; preds = %54, %39
  br label %56

56:                                               ; preds = %55, %35
  %57 = load i32, ptr %6, align 4, !tbaa !9
  %58 = load i32, ptr %8, align 4, !tbaa !9
  %59 = mul i32 %57, %58
  %60 = shl i32 %59, 16
  store i32 %60, ptr %9, align 4, !tbaa !9
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !17
  %64 = ptrtoint ptr %63 to i32
  %65 = add i32 %64, 132
  %66 = load i32, ptr %7, align 4, !tbaa !9
  %67 = mul i32 128, %66
  %68 = add i32 %65, %67
  %69 = zext i32 %68 to i64
  %70 = inttoptr i64 %69 to ptr
  %71 = getelementptr inbounds %struct.LTDC_Layer_TypeDef, ptr %70, i32 0, i32 10
  %72 = load volatile i32, ptr %71, align 4, !tbaa !18
  %73 = zext i32 %72 to i64
  %74 = and i64 %73, -536805377
  %75 = trunc i64 %74 to i32
  store volatile i32 %75, ptr %71, align 4, !tbaa !18
  %76 = load volatile i32, ptr getelementptr inbounds (%struct.LTDC_TypeDef, ptr inttoptr (i64 1342181376 to ptr), i32 0, i32 7), align 4, !tbaa !20
  %77 = zext i32 %76 to i64
  %78 = or i64 %77, 1
  %79 = trunc i64 %78 to i32
  store volatile i32 %79, ptr getelementptr inbounds (%struct.LTDC_TypeDef, ptr inttoptr (i64 1342181376 to ptr), i32 0, i32 7), align 4, !tbaa !20
  %80 = load i32, ptr %9, align 4, !tbaa !9
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !17
  %84 = ptrtoint ptr %83 to i32
  %85 = add i32 %84, 132
  %86 = load i32, ptr %7, align 4, !tbaa !9
  %87 = mul i32 128, %86
  %88 = add i32 %85, %87
  %89 = zext i32 %88 to i64
  %90 = inttoptr i64 %89 to ptr
  %91 = getelementptr inbounds %struct.LTDC_Layer_TypeDef, ptr %90, i32 0, i32 10
  %92 = load volatile i32, ptr %91, align 4, !tbaa !18
  %93 = or i32 %92, %80
  store volatile i32 %93, ptr %91, align 4, !tbaa !18
  %94 = load volatile i32, ptr getelementptr inbounds (%struct.LTDC_TypeDef, ptr inttoptr (i64 1342181376 to ptr), i32 0, i32 7), align 4, !tbaa !20
  %95 = zext i32 %94 to i64
  %96 = or i64 %95, 1
  %97 = trunc i64 %96 to i32
  store volatile i32 %97, ptr getelementptr inbounds (%struct.LTDC_TypeDef, ptr inttoptr (i64 1342181376 to ptr), i32 0, i32 7), align 4, !tbaa !20
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %98, i32 0, i32 4
  store volatile i32 1, ptr %99, align 8, !tbaa !15
  br label %100

100:                                              ; preds = %56
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.LTDC_HandleTypeDef, ptr %101, i32 0, i32 3
  store i32 0, ptr %102, align 4, !tbaa !11
  br label %103

103:                                              ; preds = %100
  br label %104

104:                                              ; preds = %103
  store i32 0, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %105

105:                                              ; preds = %104, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %106 = load i32, ptr %4, align 4
  ret i32 %106
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 164}
!12 = !{!"", !6, i64 0, !13, i64 8, !7, i64 60, !10, i64 164, !10, i64 168, !10, i64 172}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !14, i64 48}
!14 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!15 = !{!12, !10, i64 168}
!16 = !{!13, !10, i64 16}
!17 = !{!12, !6, i64 0}
!18 = !{!19, !10, i64 44}
!19 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !10, i64 64}
!20 = !{!21, !10, i64 36}
!21 = !{!"", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !7, i64 28, !10, i64 36, !7, i64 40, !10, i64 44, !7, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.LTDC_LayerCfgTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.LTDC_ColorTypeDef }
%struct.LTDC_ColorTypeDef = type { i8, i8, i8, i8 }

@switch.table.HAL_LTDC_SetPitch = private unnamed_addr constant [8 x i32] [i32 4, i32 3, i32 2, i32 2, i32 2, i32 1, i32 1, i32 2], align 4

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_LTDC_SetPitch(ptr noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 164
  %5 = load i32, ptr %4, align 4, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %35, label %7

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 2, ptr %8, align 8, !tbaa !13
  %9 = getelementptr inbounds i8, ptr %0, i64 60
  %10 = zext i32 %2 to i64
  %11 = getelementptr inbounds [2 x %struct.LTDC_LayerCfgTypeDef], ptr %9, i64 0, i64 %10, i32 4
  %12 = load i32, ptr %11, align 4, !tbaa !14
  %13 = icmp ult i32 %12, 8
  br i1 %13, label %switch.lookup, label %15

switch.lookup:                                    ; preds = %7
  %14 = zext nneg i32 %12 to i64
  %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.HAL_LTDC_SetPitch, i64 0, i64 %14
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %15

15:                                               ; preds = %7, %switch.lookup
  %.025 = phi i32 [ %switch.load, %switch.lookup ], [ 1, %7 ]
  %16 = shl i32 %1, 16
  %17 = mul i32 %16, %.025
  %18 = load ptr, ptr %0, align 8, !tbaa !15
  %19 = ptrtoint ptr %18 to i64
  %20 = trunc i64 %19 to i32
  %21 = shl i32 %2, 7
  %22 = add i32 %21, 132
  %23 = add i32 %22, %20
  %24 = zext i32 %23 to i64
  %25 = inttoptr i64 %24 to ptr
  %26 = getelementptr inbounds i8, ptr %25, i64 44
  %27 = load volatile i32, ptr %26, align 4, !tbaa !16
  %28 = and i32 %27, -536805377
  store volatile i32 %28, ptr %26, align 4, !tbaa !16
  %29 = load volatile i32, ptr inttoptr (i64 1342181412 to ptr), align 4, !tbaa !18
  %30 = or i32 %29, 1
  store volatile i32 %30, ptr inttoptr (i64 1342181412 to ptr), align 4, !tbaa !18
  %31 = load volatile i32, ptr %26, align 4, !tbaa !16
  %32 = or i32 %31, %17
  store volatile i32 %32, ptr %26, align 4, !tbaa !16
  %33 = load volatile i32, ptr inttoptr (i64 1342181412 to ptr), align 4, !tbaa !18
  %34 = or i32 %33, 1
  store volatile i32 %34, ptr inttoptr (i64 1342181412 to ptr), align 4, !tbaa !18
  store volatile i32 1, ptr %8, align 8, !tbaa !13
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %3, %15
  %.0 = phi i32 [ 0, %15 ], [ 2, %3 ]
  ret i32 %.0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 164}
!6 = !{!"", !7, i64 0, !10, i64 8, !8, i64 60, !11, i64 164, !11, i64 168, !11, i64 172}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !12, i64 48}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !8, i64 0, !8, i64 1, !8, i64 2, !8, i64 3}
!13 = !{!6, !11, i64 168}
!14 = !{!10, !11, i64 16}
!15 = !{!6, !7, i64 0}
!16 = !{!17, !11, i64 44}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !8, i64 32, !11, i64 40, !11, i64 44, !11, i64 48, !8, i64 52, !11, i64 64}
!18 = !{!19, !11, i64 36}
!19 = !{!"", !8, i64 0, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !8, i64 28, !11, i64 36, !8, i64 40, !11, i64 44, !8, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass