; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src/OSMeshSDMemory.ll (ZN14OSMeshSDMemory7receiveEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.21" = type { %"struct.std::_Vector_base.22" }
%"struct.std::_Vector_base.22" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.OSMeshSDMemory = type { %class.MemoryController, ptr, ptr, ptr, i32, i32, i32, i32, i32, ptr, i32, %"class.std::vector", %"class.std::vector.3", %"class.std::vector.8", i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, %"class.std::vector.13", %"class.std::vector.13", ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, %"class.std::vector.8", i32, %class.SDMemoryStats }
%class.MemoryController = type { %class.Unit }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl" }
%"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl" = type { %"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.SDMemoryStats = type { %class.Stats, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3" }
%class.Stats = type { ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14OSMeshSDMemory7receiveEv(ptr noundef nonnull align 8 dereferenceable(552) %0) #2 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca %"class.std::vector.21", align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca %"class.std::vector.21", align 8
  %10 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %11 = load ptr, ptr %2, align 8
  %12 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 9
  %13 = load ptr, ptr %12, align 8, !tbaa !9
  %14 = call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %13)
  br i1 %14, label %15, label %40

15:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 24, ptr %3) #4
  %16 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 9
  %17 = load ptr, ptr %16, align 8, !tbaa !9
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector.21") align 8 %3, ptr noundef nonnull align 8 dereferenceable(64) %17)
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !38
  br label %18

18:                                               ; preds = %32, %15
  %19 = load i32, ptr %4, align 4, !tbaa !38
  %20 = sext i32 %19 to i64
  %21 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %22 = icmp ult i64 %20, %21
  br i1 %22, label %24, label %23

23:                                               ; preds = %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  br label %39

24:                                               ; preds = %18
  %25 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 23
  %26 = load ptr, ptr %25, align 8, !tbaa !39
  %27 = load i32, ptr %4, align 4, !tbaa !38
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %28) #4
  %30 = load ptr, ptr %29, align 8, !tbaa !5
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %26, ptr noundef %30)
          to label %31 unwind label %35

31:                                               ; preds = %24
  br label %32

32:                                               ; preds = %31
  %33 = load i32, ptr %4, align 4, !tbaa !38
  %34 = add nsw i32 %33, 1
  store i32 %34, ptr %4, align 4, !tbaa !38
  br label %18, !llvm.loop !40

35:                                               ; preds = %24
  %36 = landingpad { ptr, i32 }
          cleanup
  %37 = extractvalue { ptr, i32 } %36, 0
  store ptr %37, ptr %5, align 8
  %38 = extractvalue { ptr, i32 } %36, 1
  store i32 %38, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr %3) #4
  br label %88

39:                                               ; preds = %23
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr %3) #4
  br label %40

40:                                               ; preds = %39, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !38
  br label %41

41:                                               ; preds = %84, %40
  %42 = load i32, ptr %7, align 4, !tbaa !38
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 48
  %45 = call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %44) #4
  %46 = icmp ult i64 %43, %45
  br i1 %46, label %48, label %47

47:                                               ; preds = %41
  store i32 5, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %87

48:                                               ; preds = %41
  %49 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 48
  %50 = load i32, ptr %7, align 4, !tbaa !38
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %51) #4
  %53 = load ptr, ptr %52, align 8, !tbaa !5
  %54 = call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %53)
  br i1 %54, label %55, label %83

55:                                               ; preds = %48
  call void @llvm.lifetime.start.p0(i64 24, ptr %9) #4
  %56 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 48
  %57 = load i32, ptr %7, align 4, !tbaa !38
  %58 = sext i32 %57 to i64
  %59 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %56, i64 noundef %58) #4
  %60 = load ptr, ptr %59, align 8, !tbaa !5
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector.21") align 8 %9, ptr noundef nonnull align 8 dereferenceable(64) %60)
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  store i32 0, ptr %10, align 4, !tbaa !38
  br label %61

61:                                               ; preds = %75, %55
  %62 = load i32, ptr %10, align 4, !tbaa !38
  %63 = sext i32 %62 to i64
  %64 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  %65 = icmp ult i64 %63, %64
  br i1 %65, label %67, label %66

66:                                               ; preds = %61
  store i32 8, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  br label %82

67:                                               ; preds = %61
  %68 = getelementptr inbounds %class.OSMeshSDMemory, ptr %11, i32 0, i32 23
  %69 = load ptr, ptr %68, align 8, !tbaa !39
  %70 = load i32, ptr %10, align 4, !tbaa !38
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %71) #4
  %73 = load ptr, ptr %72, align 8, !tbaa !5
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %69, ptr noundef %73)
          to label %74 unwind label %78

74:                                               ; preds = %67
  br label %75

75:                                               ; preds = %74
  %76 = load i32, ptr %10, align 4, !tbaa !38
  %77 = add nsw i32 %76, 1
  store i32 %77, ptr %10, align 4, !tbaa !38
  br label %61, !llvm.loop !42

78:                                               ; preds = %67
  %79 = landingpad { ptr, i32 }
          cleanup
  %80 = extractvalue { ptr, i32 } %79, 0
  store ptr %80, ptr %5, align 8
  %81 = extractvalue { ptr, i32 } %79, 1
  store i32 %81, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %88

82:                                               ; preds = %66
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr %9) #4
  br label %83

83:                                               ; preds = %82, %48
  br label %84

84:                                               ; preds = %83
  %85 = load i32, ptr %7, align 4, !tbaa !38
  %86 = add nsw i32 %85, 1
  store i32 %86, ptr %7, align 4, !tbaa !38
  br label %41, !llvm.loop !43

87:                                               ; preds = %47
  ret void

88:                                               ; preds = %78, %35
  %89 = load ptr, ptr %5, align 8
  %90 = load i32, ptr %6, align 4
  %91 = insertvalue { ptr, i32 } poison, ptr %89, 0
  %92 = insertvalue { ptr, i32 } %91, i32 %90, 1
  resume { ptr, i32 } %92
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

declare noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64)) #3

declare void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector.21") align 8, ptr noundef nonnull align 8 dereferenceable(64)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 96}
!10 = !{!"_ZTS14OSMeshSDMemory", !11, i64 0, !6, i64 48, !6, i64 56, !6, i64 64, !13, i64 72, !13, i64 76, !13, i64 80, !13, i64 84, !13, i64 88, !6, i64 96, !17, i64 104, !18, i64 112, !22, i64 136, !26, i64 160, !13, i64 184, !13, i64 188, !13, i64 192, !13, i64 196, !13, i64 200, !13, i64 204, !13, i64 208, !13, i64 212, !13, i64 216, !6, i64 224, !30, i64 232, !30, i64 256, !6, i64 280, !6, i64 288, !6, i64 296, !13, i64 304, !13, i64 308, !13, i64 312, !13, i64 316, !13, i64 320, !13, i64 324, !13, i64 328, !13, i64 332, !13, i64 336, !34, i64 340, !34, i64 341, !34, i64 342, !34, i64 343, !34, i64 344, !13, i64 348, !13, i64 352, !13, i64 356, !13, i64 360, !13, i64 364, !26, i64 368, !13, i64 392, !35, i64 400}
!11 = !{!"_ZTS16MemoryController", !12, i64 0}
!12 = !{!"_ZTS4Unit", !13, i64 8, !14, i64 16}
!13 = !{!"int", !7, i64 0}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !15, i64 0, !16, i64 8, !7, i64 16}
!15 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!"_ZTS21OSMeshControllerState", !7, i64 0}
!18 = !{!"_ZTSSt6vectorI8SparseVNSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseI8SparseVNSaIS0_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIjSaIjEE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"bool", !7, i64 0}
!35 = !{!"_ZTS13SDMemoryStats", !36, i64 0, !13, i64 8, !13, i64 12, !13, i64 16, !13, i64 20, !13, i64 24, !13, i64 28, !13, i64 32, !13, i64 36, !13, i64 40, !13, i64 44, !37, i64 48, !22, i64 56, !22, i64 80, !22, i64 104, !22, i64 128}
!36 = !{!"_ZTS5Stats"}
!37 = !{!"_ZTS8Dataflow", !7, i64 0}
!38 = !{!13, !13, i64 0}
!39 = !{!10, !6, i64 224}
!40 = distinct !{!40, !41}
!41 = !{!"llvm.loop.mustprogress"}
!42 = distinct !{!42, !41}
!43 = distinct !{!43, !41}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.21" = type { %"struct.std::_Vector_base.22" }
%"struct.std::_Vector_base.22" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14OSMeshSDMemory7receiveEv(ptr noundef nonnull align 8 dereferenceable(552) %0) local_unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"class.std::vector.21", align 8
  %3 = alloca %"class.std::vector.21", align 8
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load ptr, ptr %4, align 8, !tbaa !5
  %6 = tail call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %5)
  br i1 %6, label %7, label %20

7:                                                ; preds = %1
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %2) #4
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind nonnull writable sret(%"class.std::vector.21") align 8 %2, ptr noundef nonnull align 8 dereferenceable(64) %8)
  %9 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %.not = icmp eq i64 %9, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 224
  br label %11

._crit_edge:                                      ; preds = %15, %7
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #4
  br label %20

11:                                               ; preds = %.lr.ph, %15
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %15 ]
  %12 = load ptr, ptr %10, align 8, !tbaa !37
  %13 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #4
  %14 = load ptr, ptr %13, align 8, !tbaa !38
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %12, ptr noundef %14)
          to label %15 unwind label %18

15:                                               ; preds = %11
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %16 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %17 = icmp ugt i64 %16, %indvars.iv.next
  br i1 %17, label %11, label %._crit_edge, !llvm.loop !39

18:                                               ; preds = %11
  %19 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #4
  br label %43

20:                                               ; preds = %._crit_edge, %1
  %21 = getelementptr inbounds i8, ptr %0, i64 368
  %22 = call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #4
  %.not29 = icmp eq i64 %22, 0
  br i1 %.not29, label %._crit_edge28, label %.lr.ph27

.lr.ph27:                                         ; preds = %20
  %23 = getelementptr inbounds i8, ptr %0, i64 224
  br label %24

._crit_edge28:                                    ; preds = %40, %20
  ret void

24:                                               ; preds = %.lr.ph27, %40
  %indvars.iv35 = phi i64 [ 0, %.lr.ph27 ], [ %indvars.iv.next36, %40 ]
  %25 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %indvars.iv35) #4
  %26 = load ptr, ptr %25, align 8, !tbaa !38
  %27 = call noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64) %26)
  br i1 %27, label %28, label %40

28:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %3) #4
  %29 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %indvars.iv35) #4
  %30 = load ptr, ptr %29, align 8, !tbaa !38
  call void @_ZN10Connection7receiveEv(ptr dead_on_unwind nonnull writable sret(%"class.std::vector.21") align 8 %3, ptr noundef nonnull align 8 dereferenceable(64) %30)
  %31 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %.not30 = icmp eq i64 %31, 0
  br i1 %.not30, label %._crit_edge24, label %.lr.ph23

._crit_edge24:                                    ; preds = %35, %28
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #4
  br label %40

.lr.ph23:                                         ; preds = %28, %35
  %indvars.iv32 = phi i64 [ %indvars.iv.next33, %35 ], [ 0, %28 ]
  %32 = load ptr, ptr %23, align 8, !tbaa !37
  %33 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %indvars.iv32) #4
  %34 = load ptr, ptr %33, align 8, !tbaa !38
  invoke void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120) %32, ptr noundef %34)
          to label %35 unwind label %38

35:                                               ; preds = %.lr.ph23
  %indvars.iv.next33 = add nuw nsw i64 %indvars.iv32, 1
  %36 = call noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %37 = icmp ugt i64 %36, %indvars.iv.next33
  br i1 %37, label %.lr.ph23, label %._crit_edge24, !llvm.loop !41

38:                                               ; preds = %.lr.ph23
  %39 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #4
  br label %43

40:                                               ; preds = %24, %._crit_edge24
  %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
  %41 = call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #4
  %42 = icmp ugt i64 %41, %indvars.iv.next36
  br i1 %42, label %24, label %._crit_edge28, !llvm.loop !42

43:                                               ; preds = %38, %18
  %.pn = phi { ptr, i32 } [ %19, %18 ], [ %39, %38 ]
  resume { ptr, i32 } %.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN4Fifo4pushEP11DataPackage(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

declare noundef zeroext i1 @_ZN10Connection16existPendingDataEv(ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #3

declare void @_ZN10Connection7receiveEv(ptr dead_on_unwind writable sret(%"class.std::vector.21") align 8, ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11DataPackageSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP11DataPackageSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 96}
!6 = !{!"_ZTS14OSMeshSDMemory", !7, i64 0, !14, i64 48, !14, i64 56, !14, i64 64, !9, i64 72, !9, i64 76, !9, i64 80, !9, i64 84, !9, i64 88, !14, i64 96, !16, i64 104, !17, i64 112, !21, i64 136, !25, i64 160, !9, i64 184, !9, i64 188, !9, i64 192, !9, i64 196, !9, i64 200, !9, i64 204, !9, i64 208, !9, i64 212, !9, i64 216, !14, i64 224, !29, i64 232, !29, i64 256, !14, i64 280, !14, i64 288, !14, i64 296, !9, i64 304, !9, i64 308, !9, i64 312, !9, i64 316, !9, i64 320, !9, i64 324, !9, i64 328, !9, i64 332, !9, i64 336, !33, i64 340, !33, i64 341, !33, i64 342, !33, i64 343, !33, i64 344, !9, i64 348, !9, i64 352, !9, i64 356, !9, i64 360, !9, i64 364, !25, i64 368, !9, i64 392, !34, i64 400}
!7 = !{!"_ZTS16MemoryController", !8, i64 0}
!8 = !{!"_ZTS4Unit", !9, i64 8, !12, i64 16}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !13, i64 0, !15, i64 8, !10, i64 16}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !14, i64 0}
!14 = !{!"any pointer", !10, i64 0}
!15 = !{!"long", !10, i64 0}
!16 = !{!"_ZTS21OSMeshControllerState", !10, i64 0}
!17 = !{!"_ZTSSt6vectorI8SparseVNSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseI8SparseVNSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!21 = !{!"_ZTSSt6vectorIjSaIjEE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!25 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!29 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!33 = !{!"bool", !10, i64 0}
!34 = !{!"_ZTS13SDMemoryStats", !35, i64 0, !9, i64 8, !9, i64 12, !9, i64 16, !9, i64 20, !9, i64 24, !9, i64 28, !9, i64 32, !9, i64 36, !9, i64 40, !9, i64 44, !36, i64 48, !21, i64 56, !21, i64 80, !21, i64 104, !21, i64 128}
!35 = !{!"_ZTS5Stats"}
!36 = !{!"_ZTS8Dataflow", !10, i64 0}
!37 = !{!6, !14, i64 224}
!38 = !{!14, !14, i64 0}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}
!41 = distinct !{!41, !40}
!42 = distinct !{!42, !40}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass