; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @TIM_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_CCxNChannelCmd(ptr noundef, i32 noundef, i32 noundef) #2

declare void @TIM_DMADelayPulseCplt(ptr noundef) #1

declare void @TIM_DMADelayPulseHalfCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_PWMN_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i16 noundef zeroext %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 5
  %14 = load volatile i32, ptr %13, align 4, !tbaa !13
  %15 = icmp eq i32 %14, 2
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

17:                                               ; preds = %4
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %18, i32 0, i32 5
  %20 = load volatile i32, ptr %19, align 4, !tbaa !13
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %22, label %35

22:                                               ; preds = %17
  %23 = load ptr, ptr %8, align 8, !tbaa !5
  %24 = ptrtoint ptr %23 to i32
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %31

26:                                               ; preds = %22
  %27 = load i16, ptr %9, align 2, !tbaa !11
  %28 = zext i16 %27 to i32
  %29 = icmp ugt i32 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %26
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

31:                                               ; preds = %26, %22
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %32, i32 0, i32 5
  store volatile i32 2, ptr %33, align 4, !tbaa !13
  br label %34

34:                                               ; preds = %31
  br label %36

35:                                               ; preds = %17
  br label %36

36:                                               ; preds = %35, %34
  br label %37

37:                                               ; preds = %36
  %38 = load i32, ptr %7, align 4, !tbaa !9
  switch i32 %38, label %162 [
    i32 0, label %39
    i32 4, label %80
    i32 8, label %121
  ]

39:                                               ; preds = %37
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %40, i32 0, i32 3
  %42 = getelementptr inbounds [7 x ptr], ptr %41, i64 0, i64 1
  %43 = load ptr, ptr %42, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %43, i32 0, i32 5
  store ptr @TIM_DMADelayPulseCplt, ptr %44, align 8, !tbaa !16
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %45, i32 0, i32 3
  %47 = getelementptr inbounds [7 x ptr], ptr %46, i64 0, i64 1
  %48 = load ptr, ptr %47, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %48, i32 0, i32 6
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %49, align 8, !tbaa !19
  %50 = load ptr, ptr %6, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %50, i32 0, i32 3
  %52 = getelementptr inbounds [7 x ptr], ptr %51, i64 0, i64 1
  %53 = load ptr, ptr %52, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %53, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %54, align 8, !tbaa !20
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %55, i32 0, i32 3
  %57 = getelementptr inbounds [7 x ptr], ptr %56, i64 0, i64 1
  %58 = load ptr, ptr %57, align 8, !tbaa !5
  %59 = load ptr, ptr %8, align 8, !tbaa !5
  %60 = ptrtoint ptr %59 to i32
  %61 = load ptr, ptr %6, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !21
  %64 = getelementptr inbounds %struct.TIM_TypeDef, ptr %63, i32 0, i32 13
  %65 = ptrtoint ptr %64 to i32
  %66 = load i16, ptr %9, align 2, !tbaa !11
  %67 = zext i16 %66 to i32
  %68 = call i32 @HAL_DMA_Start_IT(ptr noundef %58, i32 noundef %60, i32 noundef %65, i32 noundef %67)
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %70, label %71

70:                                               ; preds = %39
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

71:                                               ; preds = %39
  %72 = load ptr, ptr %6, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !21
  %75 = getelementptr inbounds %struct.TIM_TypeDef, ptr %74, i32 0, i32 3
  %76 = load volatile i32, ptr %75, align 4, !tbaa !22
  %77 = zext i32 %76 to i64
  %78 = or i64 %77, 512
  %79 = trunc i64 %78 to i32
  store volatile i32 %79, ptr %75, align 4, !tbaa !22
  br label %163

80:                                               ; preds = %37
  %81 = load ptr, ptr %6, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %81, i32 0, i32 3
  %83 = getelementptr inbounds [7 x ptr], ptr %82, i64 0, i64 2
  %84 = load ptr, ptr %83, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %84, i32 0, i32 5
  store ptr @TIM_DMADelayPulseCplt, ptr %85, align 8, !tbaa !16
  %86 = load ptr, ptr %6, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %86, i32 0, i32 3
  %88 = getelementptr inbounds [7 x ptr], ptr %87, i64 0, i64 2
  %89 = load ptr, ptr %88, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %89, i32 0, i32 6
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %90, align 8, !tbaa !19
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %91, i32 0, i32 3
  %93 = getelementptr inbounds [7 x ptr], ptr %92, i64 0, i64 2
  %94 = load ptr, ptr %93, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %94, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %95, align 8, !tbaa !20
  %96 = load ptr, ptr %6, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %96, i32 0, i32 3
  %98 = getelementptr inbounds [7 x ptr], ptr %97, i64 0, i64 2
  %99 = load ptr, ptr %98, align 8, !tbaa !5
  %100 = load ptr, ptr %8, align 8, !tbaa !5
  %101 = ptrtoint ptr %100 to i32
  %102 = load ptr, ptr %6, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !21
  %105 = getelementptr inbounds %struct.TIM_TypeDef, ptr %104, i32 0, i32 14
  %106 = ptrtoint ptr %105 to i32
  %107 = load i16, ptr %9, align 2, !tbaa !11
  %108 = zext i16 %107 to i32
  %109 = call i32 @HAL_DMA_Start_IT(ptr noundef %99, i32 noundef %101, i32 noundef %106, i32 noundef %108)
  %110 = icmp ne i32 %109, 0
  br i1 %110, label %111, label %112

111:                                              ; preds = %80
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

112:                                              ; preds = %80
  %113 = load ptr, ptr %6, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %113, i32 0, i32 0
  %115 = load ptr, ptr %114, align 8, !tbaa !21
  %116 = getelementptr inbounds %struct.TIM_TypeDef, ptr %115, i32 0, i32 3
  %117 = load volatile i32, ptr %116, align 4, !tbaa !22
  %118 = zext i32 %117 to i64
  %119 = or i64 %118, 1024
  %120 = trunc i64 %119 to i32
  store volatile i32 %120, ptr %116, align 4, !tbaa !22
  br label %163

121:                                              ; preds = %37
  %122 = load ptr, ptr %6, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %122, i32 0, i32 3
  %124 = getelementptr inbounds [7 x ptr], ptr %123, i64 0, i64 3
  %125 = load ptr, ptr %124, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %125, i32 0, i32 5
  store ptr @TIM_DMADelayPulseCplt, ptr %126, align 8, !tbaa !16
  %127 = load ptr, ptr %6, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %127, i32 0, i32 3
  %129 = getelementptr inbounds [7 x ptr], ptr %128, i64 0, i64 3
  %130 = load ptr, ptr %129, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %130, i32 0, i32 6
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %131, align 8, !tbaa !19
  %132 = load ptr, ptr %6, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %132, i32 0, i32 3
  %134 = getelementptr inbounds [7 x ptr], ptr %133, i64 0, i64 3
  %135 = load ptr, ptr %134, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %135, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %136, align 8, !tbaa !20
  %137 = load ptr, ptr %6, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %137, i32 0, i32 3
  %139 = getelementptr inbounds [7 x ptr], ptr %138, i64 0, i64 3
  %140 = load ptr, ptr %139, align 8, !tbaa !5
  %141 = load ptr, ptr %8, align 8, !tbaa !5
  %142 = ptrtoint ptr %141 to i32
  %143 = load ptr, ptr %6, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %143, i32 0, i32 0
  %145 = load ptr, ptr %144, align 8, !tbaa !21
  %146 = getelementptr inbounds %struct.TIM_TypeDef, ptr %145, i32 0, i32 15
  %147 = ptrtoint ptr %146 to i32
  %148 = load i16, ptr %9, align 2, !tbaa !11
  %149 = zext i16 %148 to i32
  %150 = call i32 @HAL_DMA_Start_IT(ptr noundef %140, i32 noundef %142, i32 noundef %147, i32 noundef %149)
  %151 = icmp ne i32 %150, 0
  br i1 %151, label %152, label %153

152:                                              ; preds = %121
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

153:                                              ; preds = %121
  %154 = load ptr, ptr %6, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %154, i32 0, i32 0
  %156 = load ptr, ptr %155, align 8, !tbaa !21
  %157 = getelementptr inbounds %struct.TIM_TypeDef, ptr %156, i32 0, i32 3
  %158 = load volatile i32, ptr %157, align 4, !tbaa !22
  %159 = zext i32 %158 to i64
  %160 = or i64 %159, 2048
  %161 = trunc i64 %160 to i32
  store volatile i32 %161, ptr %157, align 4, !tbaa !22
  br label %163

162:                                              ; preds = %37
  br label %163

163:                                              ; preds = %162, %153, %112, %71
  %164 = load ptr, ptr %6, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %164, i32 0, i32 0
  %166 = load ptr, ptr %165, align 8, !tbaa !21
  %167 = load i32, ptr %7, align 4, !tbaa !9
  call void @TIM_CCxNChannelCmd(ptr noundef %166, i32 noundef %167, i32 noundef 4)
  %168 = load ptr, ptr %6, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %168, i32 0, i32 0
  %170 = load ptr, ptr %169, align 8, !tbaa !21
  %171 = getelementptr inbounds %struct.TIM_TypeDef, ptr %170, i32 0, i32 17
  %172 = load volatile i32, ptr %171, align 4, !tbaa !24
  %173 = zext i32 %172 to i64
  %174 = or i64 %173, 32768
  %175 = trunc i64 %174 to i32
  store volatile i32 %175, ptr %171, align 4, !tbaa !24
  %176 = load ptr, ptr %6, align 8, !tbaa !5
  %177 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %176, i32 0, i32 0
  %178 = load ptr, ptr %177, align 8, !tbaa !21
  %179 = getelementptr inbounds %struct.TIM_TypeDef, ptr %178, i32 0, i32 2
  %180 = load volatile i32, ptr %179, align 4, !tbaa !25
  %181 = zext i32 %180 to i64
  %182 = and i64 %181, 65543
  %183 = trunc i64 %182 to i32
  store i32 %183, ptr %10, align 4, !tbaa !9
  %184 = load i32, ptr %10, align 4, !tbaa !9
  %185 = zext i32 %184 to i64
  %186 = icmp eq i64 %185, 6
  br i1 %186, label %200, label %187

187:                                              ; preds = %163
  %188 = load i32, ptr %10, align 4, !tbaa !9
  %189 = zext i32 %188 to i64
  %190 = icmp eq i64 %189, 65536
  br i1 %190, label %200, label %191

191:                                              ; preds = %187
  %192 = load ptr, ptr %6, align 8, !tbaa !5
  %193 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %192, i32 0, i32 0
  %194 = load ptr, ptr %193, align 8, !tbaa !21
  %195 = getelementptr inbounds %struct.TIM_TypeDef, ptr %194, i32 0, i32 0
  %196 = load volatile i32, ptr %195, align 4, !tbaa !26
  %197 = zext i32 %196 to i64
  %198 = or i64 %197, 1
  %199 = trunc i64 %198 to i32
  store volatile i32 %199, ptr %195, align 4, !tbaa !26
  br label %200

200:                                              ; preds = %191, %187, %163
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %201

201:                                              ; preds = %200, %152, %111, %70, %30, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %202 = load i32, ptr %5, align 4
  ret i32 %202
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !10, i64 100}
!14 = !{!"", !6, i64 0, !15, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!16 = !{!17, !6, i64 72}
!17 = !{!"__DMA_HandleTypeDef", !6, i64 0, !18, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!19 = !{!17, !6, i64 80}
!20 = !{!17, !6, i64 104}
!21 = !{!14, !6, i64 0}
!22 = !{!23, !10, i64 12}
!23 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!24 = !{!23, !10, i64 68}
!25 = !{!23, !10, i64 8}
!26 = !{!23, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @TIM_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_CCxNChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @TIM_DMADelayPulseCplt(ptr noundef) #0

declare void @TIM_DMADelayPulseHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIMEx_PWMN_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i16 noundef zeroext %3) local_unnamed_addr #1 {
  %5 = getelementptr inbounds i8, ptr %0, i64 100
  %6 = load volatile i32, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %96, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 4, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %17

11:                                               ; preds = %8
  %12 = ptrtoint ptr %2 to i64
  %13 = and i64 %12, 4294967295
  %14 = icmp eq i64 %13, 0
  %15 = icmp ne i16 %3, 0
  %or.cond = and i1 %15, %14
  br i1 %or.cond, label %96, label %16

16:                                               ; preds = %11
  store volatile i32 2, ptr %5, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %16, %8
  switch i32 %1, label %._crit_edge [
    i32 0, label %18
    i32 4, label %40
    i32 8, label %62
  ]

._crit_edge:                                      ; preds = %17
  %.pre = load ptr, ptr %0, align 8, !tbaa !12
  br label %84

18:                                               ; preds = %17
  %19 = getelementptr inbounds i8, ptr %0, i64 48
  %20 = load ptr, ptr %19, align 8, !tbaa !13
  %21 = getelementptr inbounds i8, ptr %20, i64 72
  store ptr @TIM_DMADelayPulseCplt, ptr %21, align 8, !tbaa !14
  %22 = load ptr, ptr %19, align 8, !tbaa !13
  %23 = getelementptr inbounds i8, ptr %22, i64 80
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %23, align 8, !tbaa !17
  %24 = load ptr, ptr %19, align 8, !tbaa !13
  %25 = getelementptr inbounds i8, ptr %24, i64 104
  store ptr @TIM_DMAError, ptr %25, align 8, !tbaa !18
  %26 = load ptr, ptr %19, align 8, !tbaa !13
  %27 = ptrtoint ptr %2 to i64
  %28 = trunc i64 %27 to i32
  %29 = load ptr, ptr %0, align 8, !tbaa !12
  %30 = getelementptr inbounds i8, ptr %29, i64 52
  %31 = ptrtoint ptr %30 to i64
  %32 = trunc i64 %31 to i32
  %33 = zext i16 %3 to i32
  %34 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %26, i32 noundef %28, i32 noundef %32, i32 noundef %33) #2
  %.not43 = icmp eq i32 %34, 0
  br i1 %.not43, label %35, label %96

35:                                               ; preds = %18
  %36 = load ptr, ptr %0, align 8, !tbaa !12
  %37 = getelementptr inbounds i8, ptr %36, i64 12
  %38 = load volatile i32, ptr %37, align 4, !tbaa !19
  %39 = or i32 %38, 512
  store volatile i32 %39, ptr %37, align 4, !tbaa !19
  br label %84

40:                                               ; preds = %17
  %41 = getelementptr inbounds i8, ptr %0, i64 56
  %42 = load ptr, ptr %41, align 8, !tbaa !13
  %43 = getelementptr inbounds i8, ptr %42, i64 72
  store ptr @TIM_DMADelayPulseCplt, ptr %43, align 8, !tbaa !14
  %44 = load ptr, ptr %41, align 8, !tbaa !13
  %45 = getelementptr inbounds i8, ptr %44, i64 80
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %45, align 8, !tbaa !17
  %46 = load ptr, ptr %41, align 8, !tbaa !13
  %47 = getelementptr inbounds i8, ptr %46, i64 104
  store ptr @TIM_DMAError, ptr %47, align 8, !tbaa !18
  %48 = load ptr, ptr %41, align 8, !tbaa !13
  %49 = ptrtoint ptr %2 to i64
  %50 = trunc i64 %49 to i32
  %51 = load ptr, ptr %0, align 8, !tbaa !12
  %52 = getelementptr inbounds i8, ptr %51, i64 56
  %53 = ptrtoint ptr %52 to i64
  %54 = trunc i64 %53 to i32
  %55 = zext i16 %3 to i32
  %56 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %48, i32 noundef %50, i32 noundef %54, i32 noundef %55) #2
  %.not42 = icmp eq i32 %56, 0
  br i1 %.not42, label %57, label %96

57:                                               ; preds = %40
  %58 = load ptr, ptr %0, align 8, !tbaa !12
  %59 = getelementptr inbounds i8, ptr %58, i64 12
  %60 = load volatile i32, ptr %59, align 4, !tbaa !19
  %61 = or i32 %60, 1024
  store volatile i32 %61, ptr %59, align 4, !tbaa !19
  br label %84

62:                                               ; preds = %17
  %63 = getelementptr inbounds i8, ptr %0, i64 64
  %64 = load ptr, ptr %63, align 8, !tbaa !13
  %65 = getelementptr inbounds i8, ptr %64, i64 72
  store ptr @TIM_DMADelayPulseCplt, ptr %65, align 8, !tbaa !14
  %66 = load ptr, ptr %63, align 8, !tbaa !13
  %67 = getelementptr inbounds i8, ptr %66, i64 80
  store ptr @TIM_DMADelayPulseHalfCplt, ptr %67, align 8, !tbaa !17
  %68 = load ptr, ptr %63, align 8, !tbaa !13
  %69 = getelementptr inbounds i8, ptr %68, i64 104
  store ptr @TIM_DMAError, ptr %69, align 8, !tbaa !18
  %70 = load ptr, ptr %63, align 8, !tbaa !13
  %71 = ptrtoint ptr %2 to i64
  %72 = trunc i64 %71 to i32
  %73 = load ptr, ptr %0, align 8, !tbaa !12
  %74 = getelementptr inbounds i8, ptr %73, i64 60
  %75 = ptrtoint ptr %74 to i64
  %76 = trunc i64 %75 to i32
  %77 = zext i16 %3 to i32
  %78 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %70, i32 noundef %72, i32 noundef %76, i32 noundef %77) #2
  %.not = icmp eq i32 %78, 0
  br i1 %.not, label %79, label %96

79:                                               ; preds = %62
  %80 = load ptr, ptr %0, align 8, !tbaa !12
  %81 = getelementptr inbounds i8, ptr %80, i64 12
  %82 = load volatile i32, ptr %81, align 4, !tbaa !19
  %83 = or i32 %82, 2048
  store volatile i32 %83, ptr %81, align 4, !tbaa !19
  br label %84

84:                                               ; preds = %._crit_edge, %79, %57, %35
  %85 = phi ptr [ %.pre, %._crit_edge ], [ %80, %79 ], [ %58, %57 ], [ %36, %35 ]
  tail call void @TIM_CCxNChannelCmd(ptr noundef %85, i32 noundef %1, i32 noundef 4)
  %86 = load ptr, ptr %0, align 8, !tbaa !12
  %87 = getelementptr inbounds i8, ptr %86, i64 68
  %88 = load volatile i32, ptr %87, align 4, !tbaa !21
  %89 = or i32 %88, 32768
  store volatile i32 %89, ptr %87, align 4, !tbaa !21
  %90 = getelementptr inbounds i8, ptr %86, i64 8
  %91 = load volatile i32, ptr %90, align 4, !tbaa !22
  %92 = and i32 %91, 65543
  switch i32 %92, label %93 [
    i32 65536, label %96
    i32 6, label %96
  ]

93:                                               ; preds = %84
  %94 = load volatile i32, ptr %86, align 4, !tbaa !23
  %95 = or i32 %94, 1
  store volatile i32 %95, ptr %86, align 4, !tbaa !23
  br label %96

96:                                               ; preds = %93, %84, %84, %62, %40, %18, %11, %4
  %.0 = phi i32 [ 2, %4 ], [ 1, %11 ], [ 1, %18 ], [ 1, %40 ], [ 1, %62 ], [ 0, %84 ], [ 0, %84 ], [ 0, %93 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 100}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !7, i64 72}
!15 = !{!"__DMA_HandleTypeDef", !7, i64 0, !16, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!17 = !{!15, !7, i64 80}
!18 = !{!15, !7, i64 104}
!19 = !{!20, !11, i64 12}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!21 = !{!20, !11, i64 68}
!22 = !{!20, !11, i64 8}
!23 = !{!20, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass