; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Chip)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NOR_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32 }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

@uwNORMemoryDataWidth = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NOR_Erase_Chip(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %8 = load i32, ptr %5, align 4, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %9, i32 0, i32 4
  %11 = load volatile i32, ptr %10, align 8, !tbaa !11
  %12 = icmp eq i32 %11, 2
  br i1 %12, label %13, label %14

13:                                               ; preds = %2
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %158

14:                                               ; preds = %2
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %15, i32 0, i32 4
  %17 = load volatile i32, ptr %16, align 8, !tbaa !11
  %18 = icmp eq i32 %17, 1
  br i1 %18, label %19, label %155

19:                                               ; preds = %14
  br label %20

20:                                               ; preds = %19
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load i32, ptr %22, align 4, !tbaa !14
  %24 = icmp eq i32 %23, 1
  br i1 %24, label %25, label %26

25:                                               ; preds = %20
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %158

26:                                               ; preds = %20
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %27, i32 0, i32 3
  store i32 1, ptr %28, align 4, !tbaa !14
  br label %29

29:                                               ; preds = %26
  br label %30

30:                                               ; preds = %29
  br label %31

31:                                               ; preds = %30
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %32, i32 0, i32 4
  store volatile i32 2, ptr %33, align 8, !tbaa !11
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %34, i32 0, i32 2
  %36 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %35, i32 0, i32 0
  %37 = load i32, ptr %36, align 8, !tbaa !15
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %39, label %40

39:                                               ; preds = %31
  store i32 1610612736, ptr %6, align 4, !tbaa !9
  br label %57

40:                                               ; preds = %31
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %41, i32 0, i32 2
  %43 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %42, i32 0, i32 0
  %44 = load i32, ptr %43, align 8, !tbaa !15
  %45 = icmp eq i32 %44, 2
  br i1 %45, label %46, label %47

46:                                               ; preds = %40
  store i32 1677721600, ptr %6, align 4, !tbaa !9
  br label %56

47:                                               ; preds = %40
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %48, i32 0, i32 2
  %50 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %49, i32 0, i32 0
  %51 = load i32, ptr %50, align 8, !tbaa !15
  %52 = icmp eq i32 %51, 4
  br i1 %52, label %53, label %54

53:                                               ; preds = %47
  store i32 1744830464, ptr %6, align 4, !tbaa !9
  br label %55

54:                                               ; preds = %47
  store i32 1811939328, ptr %6, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %54, %53
  br label %56

56:                                               ; preds = %55, %46
  br label %57

57:                                               ; preds = %56, %39
  br label %58

58:                                               ; preds = %57
  %59 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %60 = icmp eq i32 %59, 1
  br i1 %60, label %61, label %64

61:                                               ; preds = %58
  %62 = load i32, ptr %6, align 4, !tbaa !9
  %63 = add i32 %62, 2730
  br label %67

64:                                               ; preds = %58
  %65 = load i32, ptr %6, align 4, !tbaa !9
  %66 = add i32 %65, 1365
  br label %67

67:                                               ; preds = %64, %61
  %68 = phi i32 [ %63, %61 ], [ %66, %64 ]
  %69 = zext i32 %68 to i64
  %70 = inttoptr i64 %69 to ptr
  store volatile i16 170, ptr %70, align 2, !tbaa !16
  call void @__DSB()
  br label %71

71:                                               ; preds = %67
  br label %72

72:                                               ; preds = %71
  br label %73

73:                                               ; preds = %72
  %74 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %75 = icmp eq i32 %74, 1
  br i1 %75, label %76, label %79

76:                                               ; preds = %73
  %77 = load i32, ptr %6, align 4, !tbaa !9
  %78 = add i32 %77, 1364
  br label %82

79:                                               ; preds = %73
  %80 = load i32, ptr %6, align 4, !tbaa !9
  %81 = add i32 %80, 682
  br label %82

82:                                               ; preds = %79, %76
  %83 = phi i32 [ %78, %76 ], [ %81, %79 ]
  %84 = zext i32 %83 to i64
  %85 = inttoptr i64 %84 to ptr
  store volatile i16 85, ptr %85, align 2, !tbaa !16
  call void @__DSB()
  br label %86

86:                                               ; preds = %82
  br label %87

87:                                               ; preds = %86
  br label %88

88:                                               ; preds = %87
  %89 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %90 = icmp eq i32 %89, 1
  br i1 %90, label %91, label %94

91:                                               ; preds = %88
  %92 = load i32, ptr %6, align 4, !tbaa !9
  %93 = add i32 %92, 2730
  br label %97

94:                                               ; preds = %88
  %95 = load i32, ptr %6, align 4, !tbaa !9
  %96 = add i32 %95, 1365
  br label %97

97:                                               ; preds = %94, %91
  %98 = phi i32 [ %93, %91 ], [ %96, %94 ]
  %99 = zext i32 %98 to i64
  %100 = inttoptr i64 %99 to ptr
  store volatile i16 128, ptr %100, align 2, !tbaa !16
  call void @__DSB()
  br label %101

101:                                              ; preds = %97
  br label %102

102:                                              ; preds = %101
  br label %103

103:                                              ; preds = %102
  %104 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %105 = icmp eq i32 %104, 1
  br i1 %105, label %106, label %109

106:                                              ; preds = %103
  %107 = load i32, ptr %6, align 4, !tbaa !9
  %108 = add i32 %107, 2730
  br label %112

109:                                              ; preds = %103
  %110 = load i32, ptr %6, align 4, !tbaa !9
  %111 = add i32 %110, 1365
  br label %112

112:                                              ; preds = %109, %106
  %113 = phi i32 [ %108, %106 ], [ %111, %109 ]
  %114 = zext i32 %113 to i64
  %115 = inttoptr i64 %114 to ptr
  store volatile i16 170, ptr %115, align 2, !tbaa !16
  call void @__DSB()
  br label %116

116:                                              ; preds = %112
  br label %117

117:                                              ; preds = %116
  br label %118

118:                                              ; preds = %117
  %119 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %120 = icmp eq i32 %119, 1
  br i1 %120, label %121, label %124

121:                                              ; preds = %118
  %122 = load i32, ptr %6, align 4, !tbaa !9
  %123 = add i32 %122, 1364
  br label %127

124:                                              ; preds = %118
  %125 = load i32, ptr %6, align 4, !tbaa !9
  %126 = add i32 %125, 682
  br label %127

127:                                              ; preds = %124, %121
  %128 = phi i32 [ %123, %121 ], [ %126, %124 ]
  %129 = zext i32 %128 to i64
  %130 = inttoptr i64 %129 to ptr
  store volatile i16 85, ptr %130, align 2, !tbaa !16
  call void @__DSB()
  br label %131

131:                                              ; preds = %127
  br label %132

132:                                              ; preds = %131
  br label %133

133:                                              ; preds = %132
  %134 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !9
  %135 = icmp eq i32 %134, 1
  br i1 %135, label %136, label %139

136:                                              ; preds = %133
  %137 = load i32, ptr %6, align 4, !tbaa !9
  %138 = add i32 %137, 2730
  br label %142

139:                                              ; preds = %133
  %140 = load i32, ptr %6, align 4, !tbaa !9
  %141 = add i32 %140, 1365
  br label %142

142:                                              ; preds = %139, %136
  %143 = phi i32 [ %138, %136 ], [ %141, %139 ]
  %144 = zext i32 %143 to i64
  %145 = inttoptr i64 %144 to ptr
  store volatile i16 16, ptr %145, align 2, !tbaa !16
  call void @__DSB()
  br label %146

146:                                              ; preds = %142
  br label %147

147:                                              ; preds = %146
  %148 = load ptr, ptr %4, align 8, !tbaa !5
  %149 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %148, i32 0, i32 4
  store volatile i32 1, ptr %149, align 8, !tbaa !11
  br label %150

150:                                              ; preds = %147
  %151 = load ptr, ptr %4, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.NOR_HandleTypeDef, ptr %151, i32 0, i32 3
  store i32 0, ptr %152, align 4, !tbaa !14
  br label %153

153:                                              ; preds = %150
  br label %154

154:                                              ; preds = %153
  br label %156

155:                                              ; preds = %14
  store i32 1, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %158

156:                                              ; preds = %154
  br label %157

157:                                              ; preds = %156
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %158

158:                                              ; preds = %157, %155, %25, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %159 = load i32, ptr %3, align 4
  ret i32 %159
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 80}
!12 = !{!"", !6, i64 0, !6, i64 8, !13, i64 16, !10, i64 76, !10, i64 80}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!14 = !{!12, !10, i64 76}
!15 = !{!12, !10, i64 16}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@uwNORMemoryDataWidth = external hidden local_unnamed_addr global i32, align 4
@switch.table.HAL_NOR_Erase_Chip = private unnamed_addr constant [5 x i32] [i32 1610612736, i32 1811939328, i32 1677721600, i32 1811939328, i32 1744830464], align 4

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_NOR_Erase_Chip(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 80
  %4 = load volatile i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 2
  br i1 %5, label %53, label %6

6:                                                ; preds = %2
  %7 = load volatile i32, ptr %3, align 8, !tbaa !5
  %8 = icmp eq i32 %7, 1
  br i1 %8, label %9, label %53

9:                                                ; preds = %6
  %10 = getelementptr inbounds i8, ptr %0, i64 76
  %11 = load i32, ptr %10, align 4, !tbaa !12
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %53, label %13

13:                                               ; preds = %9
  store i32 1, ptr %10, align 4, !tbaa !12
  store volatile i32 2, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %0, i64 16
  %15 = load i32, ptr %14, align 8, !tbaa !13
  %16 = icmp ult i32 %15, 5
  br i1 %16, label %switch.lookup, label %18

switch.lookup:                                    ; preds = %13
  %17 = zext nneg i32 %15 to i64
  %switch.gep = getelementptr inbounds [5 x i32], ptr @switch.table.HAL_NOR_Erase_Chip, i64 0, i64 %17
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %18

18:                                               ; preds = %13, %switch.lookup
  %.0 = phi i32 [ %switch.load, %switch.lookup ], [ 1811939328, %13 ]
  %19 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %20 = icmp eq i32 %19, 1
  %21 = or disjoint i32 %.0, 2730
  %22 = or disjoint i32 %.0, 1365
  %23 = select i1 %20, i32 %21, i32 %22
  %24 = zext nneg i32 %23 to i64
  %25 = inttoptr i64 %24 to ptr
  store volatile i16 170, ptr %25, align 2, !tbaa !15
  tail call void @__DSB()
  %26 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %27 = icmp eq i32 %26, 1
  %28 = or disjoint i32 %.0, 1364
  %29 = or disjoint i32 %.0, 682
  %30 = select i1 %27, i32 %28, i32 %29
  %31 = zext nneg i32 %30 to i64
  %32 = inttoptr i64 %31 to ptr
  store volatile i16 85, ptr %32, align 2, !tbaa !15
  tail call void @__DSB()
  %33 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %34 = icmp eq i32 %33, 1
  %35 = select i1 %34, i32 %21, i32 %22
  %36 = zext nneg i32 %35 to i64
  %37 = inttoptr i64 %36 to ptr
  store volatile i16 128, ptr %37, align 2, !tbaa !15
  tail call void @__DSB()
  %38 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %39 = icmp eq i32 %38, 1
  %40 = select i1 %39, i32 %21, i32 %22
  %41 = zext nneg i32 %40 to i64
  %42 = inttoptr i64 %41 to ptr
  store volatile i16 170, ptr %42, align 2, !tbaa !15
  tail call void @__DSB()
  %43 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %44 = icmp eq i32 %43, 1
  %45 = select i1 %44, i32 %28, i32 %29
  %46 = zext nneg i32 %45 to i64
  %47 = inttoptr i64 %46 to ptr
  store volatile i16 85, ptr %47, align 2, !tbaa !15
  tail call void @__DSB()
  %48 = load i32, ptr @uwNORMemoryDataWidth, align 4, !tbaa !14
  %49 = icmp eq i32 %48, 1
  %50 = select i1 %49, i32 %21, i32 %22
  %51 = zext nneg i32 %50 to i64
  %52 = inttoptr i64 %51 to ptr
  store volatile i16 16, ptr %52, align 2, !tbaa !15
  tail call void @__DSB()
  store volatile i32 1, ptr %3, align 8, !tbaa !5
  store i32 0, ptr %10, align 4, !tbaa !12
  br label %53

53:                                               ; preds = %6, %9, %2, %18
  %.023 = phi i32 [ 0, %18 ], [ 2, %2 ], [ 2, %9 ], [ 1, %6 ]
  ret i32 %.023
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !11, i64 16}
!14 = !{!11, !11, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"short", !8, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass