; LLVM IR from RichtersFinger/ChainSimulation :: Chain.ll (ZN5ChainC2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Chain = type { double, double, double, double, double, %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<ChainElement *, std::allocator<ChainElement *>>::_Vector_impl" }
%"struct.std::_Vector_base<ChainElement *, std::allocator<ChainElement *>>::_Vector_impl" = type { %"struct.std::_Vector_base<ChainElement *, std::allocator<ChainElement *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<ChainElement *, std::allocator<ChainElement *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN5ChainC2Ev(ptr noundef nonnull align 8 dereferenceable(64) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  %4 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 5
  call void @_ZNSt6vectorIP12ChainElementSaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #2
  %5 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 0
  store double 4.000000e+04, ptr %5, align 8, !tbaa !9
  %6 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 3
  store double 2.000000e+04, ptr %6, align 8, !tbaa !16
  %7 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 0
  %8 = load double, ptr %7, align 8, !tbaa !9
  %9 = call double @sqrt(double noundef %8) #2
  %10 = fmul double 5.000000e-04, %9
  %11 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 1
  store double %10, ptr %11, align 8, !tbaa !17
  %12 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 3
  %13 = load double, ptr %12, align 8, !tbaa !16
  %14 = call double @sqrt(double noundef %13) #2
  %15 = fmul double 5.000000e-03, %14
  %16 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 4
  store double %15, ptr %16, align 8, !tbaa !18
  %17 = getelementptr inbounds %class.Chain, ptr %3, i32 0, i32 2
  store double 1.000000e-03, ptr %17, align 8, !tbaa !19
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP12ChainElementSaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: nounwind
declare double @sqrt(double noundef) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS5Chain", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !12, i64 40}
!11 = !{!"double", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIP12ChainElementSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIP12ChainElementSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP12ChainElementSaIS1_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP12ChainElementSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!10, !11, i64 24}
!17 = !{!10, !11, i64 8}
!18 = !{!10, !11, i64 32}
!19 = !{!10, !11, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN5ChainC2Ev(ptr noundef nonnull align 8 dereferenceable(64) %0) unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 40
  tail call void @_ZNSt6vectorIP12ChainElementSaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #1
  store <2 x double> <double 4.000000e+04, double 1.000000e-01>, ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 32
  store double 0x3FE6A09E667F3BCD, ptr %3, align 8, !tbaa !9
  %4 = getelementptr inbounds i8, ptr %0, i64 16
  store <2 x double> <double 1.000000e-03, double 2.000000e+04>, ptr %4, align 8, !tbaa !5
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP12ChainElementSaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 32}
!10 = !{!"_ZTS5Chain", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !11, i64 40}
!11 = !{!"_ZTSSt6vectorIP12ChainElementSaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIP12ChainElementSaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIP12ChainElementSaIS1_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIP12ChainElementSaIS1_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!15 = !{!"any pointer", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SLPVectorizerPass,SROAPass,TailCallElimPass