; LLVM IR from artfulbytes/bots2d :: src/controllers/components (Microcontroller)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Microcontroller = type <{ %class.ControllerComponent, %"struct.std::array", %"class.std::thread", %"struct.std::atomic", i8, i8, [5 x i8], %"class.std::mutex", [16 x float], %"class.std::condition_variable", i32, i32, %"class.std::mutex", float, [4 x i8] }>
%class.ControllerComponent = type { %class.Component }
%class.Component = type { ptr }
%"struct.std::array" = type { [16 x %"struct.Microcontroller::VoltageLine"] }
%"struct.Microcontroller::VoltageLine" = type { i32, ptr }
%"class.std::thread" = type { %"class.std::thread::id" }
%"class.std::thread::id" = type { i64 }
%"struct.std::atomic" = type { %"struct.std::__atomic_base" }
%"struct.std::__atomic_base" = type { i8 }
%"class.std::condition_variable" = type { %"class.std::__condvar" }
%"class.std::__condvar" = type { %union.pthread_cond_t }
%union.pthread_cond_t = type { %struct.__pthread_cond_s }
%struct.__pthread_cond_s = type { %union.__atomic_wide_counter, %union.__atomic_wide_counter, [2 x i32], [2 x i32], i32, i32, [2 x i32] }
%union.__atomic_wide_counter = type { i64 }
%"class.std::mutex" = type { %"class.std::__mutex_base" }
%"class.std::__mutex_base" = type { %union.pthread_mutex_t }
%union.pthread_mutex_t = type { %struct.__pthread_mutex_s }
%struct.__pthread_mutex_s = type { i32, i32, i32, i32, i32, i16, i16, %struct.__pthread_internal_list }
%struct.__pthread_internal_list = type { ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15Microcontroller21transferVoltageLevelsEv(ptr noundef nonnull align 8 dereferenceable(484) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  %5 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 7
  call void @_ZNSt5mutex4lockEv(ptr noundef nonnull align 8 dereferenceable(40) %5)
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %6

6:                                                ; preds = %52, %1
  %7 = load i32, ptr %3, align 4, !tbaa !9
  %8 = icmp slt i32 %7, 16
  br i1 %8, label %10, label %9

9:                                                ; preds = %6
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %55

10:                                               ; preds = %6
  %11 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 1
  %12 = load i32, ptr %3, align 4, !tbaa !9
  %13 = sext i32 %12 to i64
  %14 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %11, i64 noundef %13) #3
  %15 = getelementptr inbounds %"struct.Microcontroller::VoltageLine", ptr %14, i32 0, i32 1
  %16 = load ptr, ptr %15, align 8, !tbaa !11
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %10
  br label %52

19:                                               ; preds = %10
  %20 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 1
  %21 = load i32, ptr %3, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %20, i64 noundef %22) #3
  %24 = getelementptr inbounds %"struct.Microcontroller::VoltageLine", ptr %23, i32 0, i32 0
  %25 = load i32, ptr %24, align 8, !tbaa !14
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %39

27:                                               ; preds = %19
  %28 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 8
  %29 = load i32, ptr %3, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds [16 x float], ptr %28, i64 0, i64 %30
  %32 = load float, ptr %31, align 4, !tbaa !15
  %33 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 1
  %34 = load i32, ptr %3, align 4, !tbaa !9
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %33, i64 noundef %35) #3
  %37 = getelementptr inbounds %"struct.Microcontroller::VoltageLine", ptr %36, i32 0, i32 1
  %38 = load ptr, ptr %37, align 8, !tbaa !11
  store float %32, ptr %38, align 4, !tbaa !15
  br label %51

39:                                               ; preds = %19
  %40 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 1
  %41 = load i32, ptr %3, align 4, !tbaa !9
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %40, i64 noundef %42) #3
  %44 = getelementptr inbounds %"struct.Microcontroller::VoltageLine", ptr %43, i32 0, i32 1
  %45 = load ptr, ptr %44, align 8, !tbaa !11
  %46 = load float, ptr %45, align 4, !tbaa !15
  %47 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 8
  %48 = load i32, ptr %3, align 4, !tbaa !9
  %49 = sext i32 %48 to i64
  %50 = getelementptr inbounds [16 x float], ptr %47, i64 0, i64 %49
  store float %46, ptr %50, align 4, !tbaa !15
  br label %51

51:                                               ; preds = %39, %27
  br label %52

52:                                               ; preds = %51, %18
  %53 = load i32, ptr %3, align 4, !tbaa !9
  %54 = add nsw i32 %53, 1
  store i32 %54, ptr %3, align 4, !tbaa !9
  br label %6, !llvm.loop !17

55:                                               ; preds = %9
  %56 = getelementptr inbounds %class.Microcontroller, ptr %4, i32 0, i32 7
  call void @_ZNSt5mutex6unlockEv(ptr noundef nonnull align 8 dereferenceable(40) %56)
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5mutex4lockEv(ptr noundef nonnull align 8 dereferenceable(40)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5mutex6unlockEv(ptr noundef nonnull align 8 dereferenceable(40)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 8}
!12 = !{!"_ZTSN15Microcontroller11VoltageLineE", !13, i64 0, !6, i64 8}
!13 = !{!"_ZTSN15Microcontroller11VoltageLine4TypeE", !7, i64 0}
!14 = !{!12, !13, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"float", !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN15Microcontroller21transferVoltageLevelsEv(ptr noundef nonnull align 8 dereferenceable(484) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 280
  tail call void @_ZNSt5mutex4lockEv(ptr noundef nonnull align 8 dereferenceable(40) %2)
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = getelementptr inbounds i8, ptr %0, i64 320
  br label %6

5:                                                ; preds = %27
  tail call void @_ZNSt5mutex6unlockEv(ptr noundef nonnull align 8 dereferenceable(40) %2)
  ret void

6:                                                ; preds = %1, %27
  %indvars.iv = phi i64 [ 0, %1 ], [ %indvars.iv.next, %27 ]
  %7 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %3, i64 noundef %indvars.iv) #2
  %8 = getelementptr inbounds i8, ptr %7, i64 8
  %9 = load ptr, ptr %8, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %27, label %11

11:                                               ; preds = %6
  %12 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %3, i64 noundef %indvars.iv) #2
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %15, label %21

15:                                               ; preds = %11
  %16 = getelementptr inbounds [16 x float], ptr %4, i64 0, i64 %indvars.iv
  %17 = load float, ptr %16, align 4, !tbaa !12
  %18 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %3, i64 noundef %indvars.iv) #2
  %19 = getelementptr inbounds i8, ptr %18, i64 8
  %20 = load ptr, ptr %19, align 8, !tbaa !5
  store float %17, ptr %20, align 4, !tbaa !12
  br label %27

21:                                               ; preds = %11
  %22 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256) %3, i64 noundef %indvars.iv) #2
  %23 = getelementptr inbounds i8, ptr %22, i64 8
  %24 = load ptr, ptr %23, align 8, !tbaa !5
  %25 = load float, ptr %24, align 4, !tbaa !12
  %26 = getelementptr inbounds [16 x float], ptr %4, i64 0, i64 %indvars.iv
  store float %25, ptr %26, align 4, !tbaa !12
  br label %27

27:                                               ; preds = %15, %21, %6
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 16
  br i1 %exitcond.not, label %5, label %6, !llvm.loop !14
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5mutex4lockEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(16) ptr @_ZNSt5arrayIN15Microcontroller11VoltageLineELm16EEixEm(ptr noundef nonnull align 8 dereferenceable(256), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5mutex6unlockEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"_ZTSN15Microcontroller11VoltageLineE", !7, i64 0, !10, i64 8}
!7 = !{!"_ZTSN15Microcontroller11VoltageLine4TypeE", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"float", !8, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass