; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__UART_HandleTypeDef = type { ptr, %struct.UART_InitTypeDef, %struct.UART_AdvFeatureInitTypeDef, ptr, i16, i16, ptr, i16, i16, i16, i32, i16, i16, ptr, ptr, ptr, ptr, i32, i32, i32, i32 }
%struct.UART_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.UART_AdvFeatureInitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.USART_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_UART_Transmit_IT(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  %8 = load ptr, ptr %5, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %8, i32 0, i32 18
  %10 = load volatile i32, ptr %9, align 4, !tbaa !11
  %11 = icmp eq i32 %10, 32
  br i1 %11, label %12, label %117

12:                                               ; preds = %3
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = icmp eq ptr %13, null
  br i1 %14, label %19, label %15

15:                                               ; preds = %12
  %16 = load i16, ptr %7, align 2, !tbaa !9
  %17 = zext i16 %16 to i32
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %20

19:                                               ; preds = %15, %12
  store i32 1, ptr %4, align 4
  br label %118

20:                                               ; preds = %15
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %22, i32 0, i32 17
  %24 = load i32, ptr %23, align 8, !tbaa !16
  %25 = icmp eq i32 %24, 1
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 2, ptr %4, align 4
  br label %118

27:                                               ; preds = %21
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %28, i32 0, i32 17
  store i32 1, ptr %29, align 8, !tbaa !16
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %33, i32 0, i32 3
  store ptr %32, ptr %34, align 8, !tbaa !17
  %35 = load i16, ptr %7, align 2, !tbaa !9
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %36, i32 0, i32 4
  store i16 %35, ptr %37, align 8, !tbaa !18
  %38 = load i16, ptr %7, align 2, !tbaa !9
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %39, i32 0, i32 5
  store volatile i16 %38, ptr %40, align 2, !tbaa !19
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %41, i32 0, i32 14
  store ptr null, ptr %42, align 8, !tbaa !20
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %43, i32 0, i32 20
  store volatile i32 0, ptr %44, align 4, !tbaa !21
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %45, i32 0, i32 18
  store volatile i32 33, ptr %46, align 4, !tbaa !11
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %47, i32 0, i32 10
  %49 = load i32, ptr %48, align 8, !tbaa !22
  %50 = zext i32 %49 to i64
  %51 = icmp eq i64 %50, 536870912
  br i1 %51, label %52, label %84

52:                                               ; preds = %31
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %53, i32 0, i32 1
  %55 = getelementptr inbounds %struct.UART_InitTypeDef, ptr %54, i32 0, i32 1
  %56 = load i32, ptr %55, align 4, !tbaa !23
  %57 = zext i32 %56 to i64
  %58 = icmp eq i64 %57, 4096
  br i1 %58, label %59, label %68

59:                                               ; preds = %52
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %60, i32 0, i32 1
  %62 = getelementptr inbounds %struct.UART_InitTypeDef, ptr %61, i32 0, i32 3
  %63 = load i32, ptr %62, align 4, !tbaa !24
  %64 = icmp eq i32 %63, 0
  br i1 %64, label %65, label %68

65:                                               ; preds = %59
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %66, i32 0, i32 14
  store ptr @UART_TxISR_16BIT_FIFOEN, ptr %67, align 8, !tbaa !20
  br label %71

68:                                               ; preds = %59, %52
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %69, i32 0, i32 14
  store ptr @UART_TxISR_8BIT_FIFOEN, ptr %70, align 8, !tbaa !20
  br label %71

71:                                               ; preds = %68, %65
  br label %72

72:                                               ; preds = %71
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %73, i32 0, i32 17
  store i32 0, ptr %74, align 8, !tbaa !16
  br label %75

75:                                               ; preds = %72
  %76 = load ptr, ptr %5, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %76, i32 0, i32 0
  %78 = load ptr, ptr %77, align 8, !tbaa !25
  %79 = getelementptr inbounds %struct.USART_TypeDef, ptr %78, i32 0, i32 2
  %80 = load volatile i32, ptr %79, align 4, !tbaa !26
  %81 = zext i32 %80 to i64
  %82 = or i64 %81, 8388608
  %83 = trunc i64 %82 to i32
  store volatile i32 %83, ptr %79, align 4, !tbaa !26
  br label %116

84:                                               ; preds = %31
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %85, i32 0, i32 1
  %87 = getelementptr inbounds %struct.UART_InitTypeDef, ptr %86, i32 0, i32 1
  %88 = load i32, ptr %87, align 4, !tbaa !23
  %89 = zext i32 %88 to i64
  %90 = icmp eq i64 %89, 4096
  br i1 %90, label %91, label %100

91:                                               ; preds = %84
  %92 = load ptr, ptr %5, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %92, i32 0, i32 1
  %94 = getelementptr inbounds %struct.UART_InitTypeDef, ptr %93, i32 0, i32 3
  %95 = load i32, ptr %94, align 4, !tbaa !24
  %96 = icmp eq i32 %95, 0
  br i1 %96, label %97, label %100

97:                                               ; preds = %91
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %98, i32 0, i32 14
  store ptr @UART_TxISR_16BIT, ptr %99, align 8, !tbaa !20
  br label %103

100:                                              ; preds = %91, %84
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %101, i32 0, i32 14
  store ptr @UART_TxISR_8BIT, ptr %102, align 8, !tbaa !20
  br label %103

103:                                              ; preds = %100, %97
  br label %104

104:                                              ; preds = %103
  %105 = load ptr, ptr %5, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %105, i32 0, i32 17
  store i32 0, ptr %106, align 8, !tbaa !16
  br label %107

107:                                              ; preds = %104
  %108 = load ptr, ptr %5, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %108, i32 0, i32 0
  %110 = load ptr, ptr %109, align 8, !tbaa !25
  %111 = getelementptr inbounds %struct.USART_TypeDef, ptr %110, i32 0, i32 0
  %112 = load volatile i32, ptr %111, align 4, !tbaa !28
  %113 = zext i32 %112 to i64
  %114 = or i64 %113, 128
  %115 = trunc i64 %114 to i32
  store volatile i32 %115, ptr %111, align 4, !tbaa !28
  br label %116

116:                                              ; preds = %107, %75
  store i32 0, ptr %4, align 4
  br label %118

117:                                              ; preds = %3
  store i32 2, ptr %4, align 4
  br label %118

118:                                              ; preds = %117, %116, %26, %19
  %119 = load i32, ptr %4, align 4
  ret i32 %119
}

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_16BIT_FIFOEN(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_8BIT_FIFOEN(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_16BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_8BIT(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 164}
!12 = !{!"__UART_HandleTypeDef", !6, i64 0, !13, i64 8, !15, i64 44, !6, i64 88, !10, i64 96, !10, i64 98, !6, i64 104, !10, i64 112, !10, i64 114, !10, i64 116, !14, i64 120, !10, i64 124, !10, i64 126, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !14, i64 160, !14, i64 164, !14, i64 168, !14, i64 172}
!13 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32}
!14 = !{!"int", !7, i64 0}
!15 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36}
!16 = !{!12, !14, i64 160}
!17 = !{!12, !6, i64 88}
!18 = !{!12, !10, i64 96}
!19 = !{!12, !10, i64 98}
!20 = !{!12, !6, i64 136}
!21 = !{!12, !14, i64 172}
!22 = !{!12, !14, i64 120}
!23 = !{!12, !14, i64 12}
!24 = !{!12, !14, i64 20}
!25 = !{!12, !6, i64 0}
!26 = !{!27, !14, i64 8}
!27 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44}
!28 = !{!27, !14, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_UART_Transmit_IT(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 164
  %5 = load volatile i32, ptr %4, align 4, !tbaa !5
  %6 = icmp eq i32 %5, 32
  br i1 %6, label %7, label %45

7:                                                ; preds = %3
  %8 = icmp eq ptr %1, null
  %9 = icmp eq i16 %2, 0
  %or.cond = or i1 %8, %9
  br i1 %or.cond, label %45, label %10

10:                                               ; preds = %7
  %11 = getelementptr inbounds i8, ptr %0, i64 160
  %12 = load i32, ptr %11, align 8, !tbaa !14
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %45, label %14

14:                                               ; preds = %10
  %15 = getelementptr inbounds i8, ptr %0, i64 88
  store ptr %1, ptr %15, align 8, !tbaa !15
  %16 = getelementptr inbounds i8, ptr %0, i64 96
  store i16 %2, ptr %16, align 8, !tbaa !16
  %17 = getelementptr inbounds i8, ptr %0, i64 98
  store volatile i16 %2, ptr %17, align 2, !tbaa !17
  %18 = getelementptr inbounds i8, ptr %0, i64 136
  %19 = getelementptr inbounds i8, ptr %0, i64 172
  store volatile i32 0, ptr %19, align 4, !tbaa !18
  store volatile i32 33, ptr %4, align 4, !tbaa !5
  %20 = getelementptr inbounds i8, ptr %0, i64 120
  %21 = load i32, ptr %20, align 8, !tbaa !19
  %22 = icmp eq i32 %21, 536870912
  %23 = getelementptr inbounds i8, ptr %0, i64 12
  %24 = load i32, ptr %23, align 4, !tbaa !20
  %25 = icmp eq i32 %24, 4096
  br i1 %22, label %26, label %35

26:                                               ; preds = %14
  br i1 %25, label %27, label %31

27:                                               ; preds = %26
  %28 = getelementptr inbounds i8, ptr %0, i64 20
  %29 = load i32, ptr %28, align 4, !tbaa !21
  %30 = icmp eq i32 %29, 0
  br i1 %30, label %32, label %31

31:                                               ; preds = %27, %26
  br label %32

32:                                               ; preds = %27, %31
  %storemerge30 = phi ptr [ @UART_TxISR_8BIT_FIFOEN, %31 ], [ @UART_TxISR_16BIT_FIFOEN, %27 ]
  store ptr %storemerge30, ptr %18, align 8, !tbaa !22
  store i32 0, ptr %11, align 8, !tbaa !14
  %33 = load ptr, ptr %0, align 8, !tbaa !23
  %34 = getelementptr inbounds i8, ptr %33, i64 8
  br label %.sink.split

35:                                               ; preds = %14
  br i1 %25, label %36, label %40

36:                                               ; preds = %35
  %37 = getelementptr inbounds i8, ptr %0, i64 20
  %38 = load i32, ptr %37, align 4, !tbaa !21
  %39 = icmp eq i32 %38, 0
  br i1 %39, label %41, label %40

40:                                               ; preds = %36, %35
  br label %41

41:                                               ; preds = %36, %40
  %storemerge = phi ptr [ @UART_TxISR_8BIT, %40 ], [ @UART_TxISR_16BIT, %36 ]
  store ptr %storemerge, ptr %18, align 8, !tbaa !22
  store i32 0, ptr %11, align 8, !tbaa !14
  %42 = load ptr, ptr %0, align 8, !tbaa !23
  br label %.sink.split

.sink.split:                                      ; preds = %41, %32
  %.sink = phi ptr [ %34, %32 ], [ %42, %41 ]
  %.sink33 = phi i32 [ 8388608, %32 ], [ 128, %41 ]
  %43 = load volatile i32, ptr %.sink, align 4, !tbaa !24
  %44 = or i32 %43, %.sink33
  store volatile i32 %44, ptr %.sink, align 4, !tbaa !24
  br label %45

45:                                               ; preds = %.sink.split, %3, %10, %7
  %.0 = phi i32 [ 1, %7 ], [ 2, %10 ], [ 2, %3 ], [ 0, %.sink.split ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_16BIT_FIFOEN(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_8BIT_FIFOEN(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_16BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @UART_TxISR_8BIT(ptr noundef) #1

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 164}
!6 = !{!"__UART_HandleTypeDef", !7, i64 0, !10, i64 8, !12, i64 44, !7, i64 88, !13, i64 96, !13, i64 98, !7, i64 104, !13, i64 112, !13, i64 114, !13, i64 116, !11, i64 120, !13, i64 124, !13, i64 126, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!13 = !{!"short", !8, i64 0}
!14 = !{!6, !11, i64 160}
!15 = !{!6, !7, i64 88}
!16 = !{!6, !13, i64 96}
!17 = !{!6, !13, i64 98}
!18 = !{!6, !11, i64 172}
!19 = !{!6, !11, i64 120}
!20 = !{!6, !11, i64 12}
!21 = !{!6, !11, i64 20}
!22 = !{!6, !7, i64 136}
!23 = !{!6, !7, i64 0}
!24 = !{!11, !11, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass