; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__USART_HandleTypeDef = type { ptr, %struct.USART_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i16, i16, i16, i32, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.USART_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.USART_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMATransmitCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMATxHalfCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMAReceiveCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMARxHalfCplt(ptr noundef) #1

declare i32 @HAL_DMA_Abort(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_USART_TransmitReceive_DMA(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %13, i32 0, i32 18
  %15 = load volatile i32, ptr %14, align 4, !tbaa !11
  %16 = icmp eq i32 %15, 1
  br i1 %16, label %17, label %188

17:                                               ; preds = %4
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  %19 = icmp eq ptr %18, null
  br i1 %19, label %27, label %20

20:                                               ; preds = %17
  %21 = load ptr, ptr %8, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %27, label %23

23:                                               ; preds = %20
  %24 = load i16, ptr %9, align 2, !tbaa !9
  %25 = zext i16 %24 to i32
  %26 = icmp eq i32 %25, 0
  br i1 %26, label %27, label %28

27:                                               ; preds = %23, %20, %17
  store i32 1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %189

28:                                               ; preds = %23
  br label %29

29:                                               ; preds = %28
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %30, i32 0, i32 17
  %32 = load i32, ptr %31, align 8, !tbaa !15
  %33 = icmp eq i32 %32, 1
  br i1 %33, label %34, label %35

34:                                               ; preds = %29
  store i32 2, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %189

35:                                               ; preds = %29
  %36 = load ptr, ptr %6, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %36, i32 0, i32 17
  store i32 1, ptr %37, align 8, !tbaa !15
  br label %38

38:                                               ; preds = %35
  br label %39

39:                                               ; preds = %38
  br label %40

40:                                               ; preds = %39
  %41 = load ptr, ptr %8, align 8, !tbaa !5
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %42, i32 0, i32 5
  store ptr %41, ptr %43, align 8, !tbaa !16
  %44 = load i16, ptr %9, align 2, !tbaa !9
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %45, i32 0, i32 6
  store i16 %44, ptr %46, align 8, !tbaa !17
  %47 = load ptr, ptr %7, align 8, !tbaa !5
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %48, i32 0, i32 2
  store ptr %47, ptr %49, align 8, !tbaa !18
  %50 = load i16, ptr %9, align 2, !tbaa !9
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %51, i32 0, i32 3
  store i16 %50, ptr %52, align 8, !tbaa !19
  %53 = load ptr, ptr %6, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %53, i32 0, i32 19
  store volatile i32 0, ptr %54, align 8, !tbaa !20
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %55, i32 0, i32 18
  store volatile i32 50, ptr %56, align 4, !tbaa !11
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %57, i32 0, i32 16
  %59 = load ptr, ptr %58, align 8, !tbaa !21
  %60 = icmp ne ptr %59, null
  br i1 %60, label %61, label %121

61:                                               ; preds = %40
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %62, i32 0, i32 15
  %64 = load ptr, ptr %63, align 8, !tbaa !22
  %65 = icmp ne ptr %64, null
  br i1 %65, label %66, label %121

66:                                               ; preds = %61
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %67, i32 0, i32 16
  %69 = load ptr, ptr %68, align 8, !tbaa !21
  %70 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %69, i32 0, i32 5
  store ptr @USART_DMAReceiveCplt, ptr %70, align 8, !tbaa !23
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %71, i32 0, i32 16
  %73 = load ptr, ptr %72, align 8, !tbaa !21
  %74 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %73, i32 0, i32 6
  store ptr @USART_DMARxHalfCplt, ptr %74, align 8, !tbaa !26
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %75, i32 0, i32 15
  %77 = load ptr, ptr %76, align 8, !tbaa !22
  %78 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %77, i32 0, i32 5
  store ptr @USART_DMATransmitCplt, ptr %78, align 8, !tbaa !23
  %79 = load ptr, ptr %6, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %79, i32 0, i32 15
  %81 = load ptr, ptr %80, align 8, !tbaa !22
  %82 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %81, i32 0, i32 6
  store ptr @USART_DMATxHalfCplt, ptr %82, align 8, !tbaa !26
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %83, i32 0, i32 15
  %85 = load ptr, ptr %84, align 8, !tbaa !22
  %86 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %85, i32 0, i32 9
  store ptr @USART_DMAError, ptr %86, align 8, !tbaa !27
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %87, i32 0, i32 16
  %89 = load ptr, ptr %88, align 8, !tbaa !21
  %90 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %89, i32 0, i32 9
  store ptr @USART_DMAError, ptr %90, align 8, !tbaa !27
  store ptr %8, ptr %11, align 8, !tbaa !5
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %91, i32 0, i32 16
  %93 = load ptr, ptr %92, align 8, !tbaa !21
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !28
  %97 = getelementptr inbounds %struct.USART_TypeDef, ptr %96, i32 0, i32 9
  %98 = ptrtoint ptr %97 to i32
  %99 = load ptr, ptr %11, align 8, !tbaa !5
  %100 = load i32, ptr %99, align 4, !tbaa !29
  %101 = load i16, ptr %9, align 2, !tbaa !9
  %102 = zext i16 %101 to i32
  %103 = call i32 @HAL_DMA_Start_IT(ptr noundef %93, i32 noundef %98, i32 noundef %100, i32 noundef %102)
  store i32 %103, ptr %10, align 4, !tbaa !29
  %104 = load i32, ptr %10, align 4, !tbaa !29
  %105 = icmp eq i32 %104, 0
  br i1 %105, label %106, label %120

106:                                              ; preds = %66
  store ptr %7, ptr %11, align 8, !tbaa !5
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %107, i32 0, i32 15
  %109 = load ptr, ptr %108, align 8, !tbaa !22
  %110 = load ptr, ptr %11, align 8, !tbaa !5
  %111 = load i32, ptr %110, align 4, !tbaa !29
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %112, i32 0, i32 0
  %114 = load ptr, ptr %113, align 8, !tbaa !28
  %115 = getelementptr inbounds %struct.USART_TypeDef, ptr %114, i32 0, i32 10
  %116 = ptrtoint ptr %115 to i32
  %117 = load i16, ptr %9, align 2, !tbaa !9
  %118 = zext i16 %117 to i32
  %119 = call i32 @HAL_DMA_Start_IT(ptr noundef %109, i32 noundef %111, i32 noundef %116, i32 noundef %118)
  store i32 %119, ptr %10, align 4, !tbaa !29
  br label %120

120:                                              ; preds = %106, %66
  br label %122

121:                                              ; preds = %61, %40
  store i32 1, ptr %10, align 4, !tbaa !29
  br label %122

122:                                              ; preds = %121, %120
  %123 = load i32, ptr %10, align 4, !tbaa !29
  %124 = icmp eq i32 %123, 0
  br i1 %124, label %125, label %167

125:                                              ; preds = %122
  br label %126

126:                                              ; preds = %125
  %127 = load ptr, ptr %6, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %127, i32 0, i32 17
  store i32 0, ptr %128, align 8, !tbaa !15
  br label %129

129:                                              ; preds = %126
  br label %130

130:                                              ; preds = %129
  %131 = load ptr, ptr %6, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %131, i32 0, i32 0
  %133 = load ptr, ptr %132, align 8, !tbaa !28
  %134 = getelementptr inbounds %struct.USART_TypeDef, ptr %133, i32 0, i32 0
  %135 = load volatile i32, ptr %134, align 4, !tbaa !30
  %136 = zext i32 %135 to i64
  %137 = or i64 %136, 256
  %138 = trunc i64 %137 to i32
  store volatile i32 %138, ptr %134, align 4, !tbaa !30
  %139 = load ptr, ptr %6, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %139, i32 0, i32 0
  %141 = load ptr, ptr %140, align 8, !tbaa !28
  %142 = getelementptr inbounds %struct.USART_TypeDef, ptr %141, i32 0, i32 2
  %143 = load volatile i32, ptr %142, align 4, !tbaa !31
  %144 = zext i32 %143 to i64
  %145 = or i64 %144, 1
  %146 = trunc i64 %145 to i32
  store volatile i32 %146, ptr %142, align 4, !tbaa !31
  %147 = load ptr, ptr %6, align 8, !tbaa !5
  %148 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %147, i32 0, i32 0
  %149 = load ptr, ptr %148, align 8, !tbaa !28
  %150 = getelementptr inbounds %struct.USART_TypeDef, ptr %149, i32 0, i32 8
  store volatile i32 64, ptr %150, align 4, !tbaa !32
  %151 = load ptr, ptr %6, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %151, i32 0, i32 0
  %153 = load ptr, ptr %152, align 8, !tbaa !28
  %154 = getelementptr inbounds %struct.USART_TypeDef, ptr %153, i32 0, i32 2
  %155 = load volatile i32, ptr %154, align 4, !tbaa !31
  %156 = zext i32 %155 to i64
  %157 = or i64 %156, 64
  %158 = trunc i64 %157 to i32
  store volatile i32 %158, ptr %154, align 4, !tbaa !31
  %159 = load ptr, ptr %6, align 8, !tbaa !5
  %160 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %159, i32 0, i32 0
  %161 = load ptr, ptr %160, align 8, !tbaa !28
  %162 = getelementptr inbounds %struct.USART_TypeDef, ptr %161, i32 0, i32 2
  %163 = load volatile i32, ptr %162, align 4, !tbaa !31
  %164 = zext i32 %163 to i64
  %165 = or i64 %164, 128
  %166 = trunc i64 %165 to i32
  store volatile i32 %166, ptr %162, align 4, !tbaa !31
  store i32 0, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %189

167:                                              ; preds = %122
  %168 = load ptr, ptr %6, align 8, !tbaa !5
  %169 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %168, i32 0, i32 16
  %170 = load ptr, ptr %169, align 8, !tbaa !21
  %171 = icmp ne ptr %170, null
  br i1 %171, label %172, label %177

172:                                              ; preds = %167
  %173 = load ptr, ptr %6, align 8, !tbaa !5
  %174 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %173, i32 0, i32 16
  %175 = load ptr, ptr %174, align 8, !tbaa !21
  %176 = call i32 @HAL_DMA_Abort(ptr noundef %175)
  store i32 %176, ptr %10, align 4, !tbaa !29
  br label %177

177:                                              ; preds = %172, %167
  %178 = load i32, ptr %10, align 4, !tbaa !29
  %179 = load ptr, ptr %6, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %179, i32 0, i32 19
  store volatile i32 16, ptr %180, align 8, !tbaa !20
  br label %181

181:                                              ; preds = %177
  %182 = load ptr, ptr %6, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %182, i32 0, i32 17
  store i32 0, ptr %183, align 8, !tbaa !15
  br label %184

184:                                              ; preds = %181
  br label %185

185:                                              ; preds = %184
  %186 = load ptr, ptr %6, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.__USART_HandleTypeDef, ptr %186, i32 0, i32 18
  store volatile i32 1, ptr %187, align 4, !tbaa !11
  store i32 1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %189

188:                                              ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %189

189:                                              ; preds = %188, %185, %130, %34, %27
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %190 = load i32, ptr %5, align 4
  ret i32 %190
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 132}
!12 = !{!"__USART_HandleTypeDef", !6, i64 0, !13, i64 8, !6, i64 48, !10, i64 56, !10, i64 58, !6, i64 64, !10, i64 72, !10, i64 74, !10, i64 76, !10, i64 78, !10, i64 80, !14, i64 84, !14, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !14, i64 128, !14, i64 132, !14, i64 136}
!13 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32}
!14 = !{!"int", !7, i64 0}
!15 = !{!12, !14, i64 128}
!16 = !{!12, !6, i64 64}
!17 = !{!12, !10, i64 72}
!18 = !{!12, !6, i64 48}
!19 = !{!12, !10, i64 56}
!20 = !{!12, !14, i64 136}
!21 = !{!12, !6, i64 120}
!22 = !{!12, !6, i64 112}
!23 = !{!24, !6, i64 72}
!24 = !{!"__DMA_HandleTypeDef", !6, i64 0, !25, i64 8, !14, i64 56, !14, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !6, i64 136, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !14, i64 176}
!25 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44}
!26 = !{!24, !6, i64 80}
!27 = !{!24, !6, i64 104}
!28 = !{!12, !6, i64 0}
!29 = !{!14, !14, i64 0}
!30 = !{!25, !14, i64 0}
!31 = !{!25, !14, i64 8}
!32 = !{!25, !14, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMATransmitCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMATxHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMAReceiveCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @USART_DMARxHalfCplt(ptr noundef) #0

declare i32 @HAL_DMA_Abort(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_USART_TransmitReceive_DMA(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 132
  %6 = load volatile i32, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i32 %6, 1
  br i1 %7, label %8, label %65

8:                                                ; preds = %4
  %9 = icmp eq ptr %1, null
  %10 = icmp eq ptr %2, null
  %or.cond = or i1 %9, %10
  %11 = zext i16 %3 to i32
  %12 = icmp eq i16 %3, 0
  %or.cond4 = or i1 %or.cond, %12
  br i1 %or.cond4, label %65, label %13

13:                                               ; preds = %8
  %14 = getelementptr inbounds i8, ptr %0, i64 128
  %15 = load i32, ptr %14, align 8, !tbaa !13
  %16 = icmp eq i32 %15, 1
  br i1 %16, label %65, label %17

17:                                               ; preds = %13
  store i32 1, ptr %14, align 8, !tbaa !13
  %18 = getelementptr inbounds i8, ptr %0, i64 64
  store ptr %2, ptr %18, align 8, !tbaa !14
  %19 = getelementptr inbounds i8, ptr %0, i64 72
  store i16 %3, ptr %19, align 8, !tbaa !15
  %20 = getelementptr inbounds i8, ptr %0, i64 48
  store ptr %1, ptr %20, align 8, !tbaa !16
  %21 = getelementptr inbounds i8, ptr %0, i64 56
  store i16 %3, ptr %21, align 8, !tbaa !17
  %22 = getelementptr inbounds i8, ptr %0, i64 136
  store volatile i32 0, ptr %22, align 8, !tbaa !18
  store volatile i32 50, ptr %5, align 4, !tbaa !5
  %23 = getelementptr inbounds i8, ptr %0, i64 120
  %24 = load ptr, ptr %23, align 8, !tbaa !19
  %.not = icmp eq ptr %24, null
  br i1 %.not, label %.critedge.thread, label %25

25:                                               ; preds = %17
  %26 = getelementptr inbounds i8, ptr %0, i64 112
  %27 = load ptr, ptr %26, align 8, !tbaa !20
  %.not58 = icmp eq ptr %27, null
  br i1 %.not58, label %.critedge, label %28

28:                                               ; preds = %25
  %29 = getelementptr inbounds i8, ptr %24, i64 72
  store ptr @USART_DMAReceiveCplt, ptr %29, align 8, !tbaa !21
  %30 = getelementptr inbounds i8, ptr %24, i64 80
  store ptr @USART_DMARxHalfCplt, ptr %30, align 8, !tbaa !24
  %31 = getelementptr inbounds i8, ptr %27, i64 72
  store ptr @USART_DMATransmitCplt, ptr %31, align 8, !tbaa !21
  %32 = getelementptr inbounds i8, ptr %27, i64 80
  store ptr @USART_DMATxHalfCplt, ptr %32, align 8, !tbaa !24
  %33 = getelementptr inbounds i8, ptr %27, i64 104
  store ptr @USART_DMAError, ptr %33, align 8, !tbaa !25
  %34 = getelementptr inbounds i8, ptr %24, i64 104
  store ptr @USART_DMAError, ptr %34, align 8, !tbaa !25
  %35 = load ptr, ptr %0, align 8, !tbaa !26
  %36 = getelementptr inbounds i8, ptr %35, i64 36
  %37 = ptrtoint ptr %36 to i64
  %38 = trunc i64 %37 to i32
  %39 = ptrtoint ptr %2 to i64
  %.0.extract.trunc51 = trunc i64 %39 to i32
  %40 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %24, i32 noundef %38, i32 noundef %.0.extract.trunc51, i32 noundef %11) #2
  %41 = icmp eq i32 %40, 0
  br i1 %41, label %42, label %.critedge

42:                                               ; preds = %28
  %43 = load ptr, ptr %26, align 8, !tbaa !20
  %44 = ptrtoint ptr %1 to i64
  %.0.extract.trunc = trunc i64 %44 to i32
  %45 = load ptr, ptr %0, align 8, !tbaa !26
  %46 = getelementptr inbounds i8, ptr %45, i64 40
  %47 = ptrtoint ptr %46 to i64
  %48 = trunc i64 %47 to i32
  %49 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %43, i32 noundef %.0.extract.trunc, i32 noundef %48, i32 noundef %11) #2
  %50 = icmp eq i32 %49, 0
  br i1 %50, label %51, label %.critedge

51:                                               ; preds = %42
  store i32 0, ptr %14, align 8, !tbaa !13
  %52 = load ptr, ptr %0, align 8, !tbaa !26
  %53 = load volatile i32, ptr %52, align 4, !tbaa !27
  %54 = or i32 %53, 256
  store volatile i32 %54, ptr %52, align 4, !tbaa !27
  %55 = getelementptr inbounds i8, ptr %52, i64 8
  %56 = load volatile i32, ptr %55, align 4, !tbaa !28
  %57 = or i32 %56, 1
  store volatile i32 %57, ptr %55, align 4, !tbaa !28
  %58 = getelementptr inbounds i8, ptr %52, i64 32
  store volatile i32 64, ptr %58, align 4, !tbaa !29
  %59 = load volatile i32, ptr %55, align 4, !tbaa !28
  %60 = or i32 %59, 64
  store volatile i32 %60, ptr %55, align 4, !tbaa !28
  %61 = load volatile i32, ptr %55, align 4, !tbaa !28
  %62 = or i32 %61, 128
  store volatile i32 %62, ptr %55, align 4, !tbaa !28
  br label %65

.critedge:                                        ; preds = %28, %25, %42
  %.pr = load ptr, ptr %23, align 8, !tbaa !19
  %.not59 = icmp eq ptr %.pr, null
  br i1 %.not59, label %.critedge.thread, label %63

63:                                               ; preds = %.critedge
  %64 = tail call i32 @HAL_DMA_Abort(ptr noundef nonnull %.pr) #2
  br label %.critedge.thread

.critedge.thread:                                 ; preds = %17, %63, %.critedge
  store volatile i32 16, ptr %22, align 8, !tbaa !18
  store i32 0, ptr %14, align 8, !tbaa !13
  store volatile i32 1, ptr %5, align 4, !tbaa !5
  br label %65

65:                                               ; preds = %4, %13, %8, %.critedge.thread, %51
  %.046 = phi i32 [ 0, %51 ], [ 1, %.critedge.thread ], [ 1, %8 ], [ 2, %13 ], [ 2, %4 ]
  ret i32 %.046
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 132}
!6 = !{!"__USART_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 48, !12, i64 56, !12, i64 58, !7, i64 64, !12, i64 72, !12, i64 74, !12, i64 76, !12, i64 78, !12, i64 80, !11, i64 84, !11, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !11, i64 128, !11, i64 132, !11, i64 136}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 128}
!14 = !{!6, !7, i64 64}
!15 = !{!6, !12, i64 72}
!16 = !{!6, !7, i64 48}
!17 = !{!6, !12, i64 56}
!18 = !{!6, !11, i64 136}
!19 = !{!6, !7, i64 120}
!20 = !{!6, !7, i64 112}
!21 = !{!22, !7, i64 72}
!22 = !{!"__DMA_HandleTypeDef", !7, i64 0, !23, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!23 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!24 = !{!22, !7, i64 80}
!25 = !{!22, !7, i64 104}
!26 = !{!6, !7, i64 0}
!27 = !{!23, !11, i64 0}
!28 = !{!23, !11, i64 8}
!29 = !{!23, !11, i64 32}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass