; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source (SystemCoreClockUpdate)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.RCC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32] }

@SystemCoreClock = external dso_local global i32, align 4
@SystemD2Clock = external dso_local global i32, align 4
@D1CorePrescTable = external dso_local constant [16 x i8], align 16

; Function Attrs: nounwind uwtable
define dso_local void @SystemCoreClockUpdate() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca float, align 4
  %8 = alloca float, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %9 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 4), align 4, !tbaa !5
  %10 = zext i32 %9 to i64
  %11 = and i64 %10, 56
  switch i64 %11, label %127 [
    i64 0, label %12
    i64 8, label %19
    i64 16, label %20
    i64 24, label %21
  ]

12:                                               ; preds = %0
  %13 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %14 = zext i32 %13 to i64
  %15 = and i64 %14, 24
  %16 = lshr i64 %15, 3
  %17 = trunc i64 %16 to i32
  %18 = lshr i32 64000000, %17
  store i32 %18, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %128

19:                                               ; preds = %0
  store i32 4000000, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %128

20:                                               ; preds = %0
  store i32 25000000, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %128

21:                                               ; preds = %0
  %22 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 10), align 4, !tbaa !12
  %23 = zext i32 %22 to i64
  %24 = and i64 %23, 3
  %25 = trunc i64 %24 to i32
  store i32 %25, ptr %2, align 4, !tbaa !11
  %26 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 10), align 4, !tbaa !12
  %27 = zext i32 %26 to i64
  %28 = and i64 %27, 1008
  %29 = lshr i64 %28, 4
  %30 = trunc i64 %29 to i32
  store i32 %30, ptr %3, align 4, !tbaa !11
  %31 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 11), align 4, !tbaa !13
  %32 = zext i32 %31 to i64
  %33 = and i64 %32, 1
  %34 = lshr i64 %33, 0
  %35 = trunc i64 %34 to i32
  store i32 %35, ptr %4, align 4, !tbaa !11
  %36 = load i32, ptr %4, align 4, !tbaa !11
  %37 = zext i32 %36 to i64
  %38 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 13), align 4, !tbaa !14
  %39 = zext i32 %38 to i64
  %40 = and i64 %39, 65528
  %41 = lshr i64 %40, 3
  %42 = mul i64 %37, %41
  %43 = trunc i64 %42 to i32
  %44 = uitofp i32 %43 to float
  store float %44, ptr %7, align 4, !tbaa !15
  %45 = load i32, ptr %3, align 4, !tbaa !11
  %46 = icmp ne i32 %45, 0
  br i1 %46, label %47, label %125

47:                                               ; preds = %21
  %48 = load i32, ptr %2, align 4, !tbaa !11
  switch i32 %48, label %99 [
    i32 0, label %49
    i32 1, label %71
    i32 2, label %85
  ]

49:                                               ; preds = %47
  %50 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 4, !tbaa !10
  %51 = zext i32 %50 to i64
  %52 = and i64 %51, 24
  %53 = lshr i64 %52, 3
  %54 = trunc i64 %53 to i32
  %55 = lshr i32 64000000, %54
  store i32 %55, ptr %5, align 4, !tbaa !11
  %56 = load i32, ptr %5, align 4, !tbaa !11
  %57 = uitofp i32 %56 to float
  %58 = load i32, ptr %3, align 4, !tbaa !11
  %59 = uitofp i32 %58 to float
  %60 = fdiv float %57, %59
  %61 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %62 = zext i32 %61 to i64
  %63 = and i64 %62, 511
  %64 = trunc i64 %63 to i32
  %65 = uitofp i32 %64 to float
  %66 = load float, ptr %7, align 4, !tbaa !15
  %67 = fdiv float %66, 8.192000e+03
  %68 = fadd float %65, %67
  %69 = fadd float %68, 1.000000e+00
  %70 = fmul float %60, %69
  store float %70, ptr %8, align 4, !tbaa !15
  br label %113

71:                                               ; preds = %47
  %72 = load i32, ptr %3, align 4, !tbaa !11
  %73 = uitofp i32 %72 to float
  %74 = fdiv float 4.000000e+06, %73
  %75 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %76 = zext i32 %75 to i64
  %77 = and i64 %76, 511
  %78 = trunc i64 %77 to i32
  %79 = uitofp i32 %78 to float
  %80 = load float, ptr %7, align 4, !tbaa !15
  %81 = fdiv float %80, 8.192000e+03
  %82 = fadd float %79, %81
  %83 = fadd float %82, 1.000000e+00
  %84 = fmul float %74, %83
  store float %84, ptr %8, align 4, !tbaa !15
  br label %113

85:                                               ; preds = %47
  %86 = load i32, ptr %3, align 4, !tbaa !11
  %87 = uitofp i32 %86 to float
  %88 = fdiv float 2.500000e+07, %87
  %89 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %90 = zext i32 %89 to i64
  %91 = and i64 %90, 511
  %92 = trunc i64 %91 to i32
  %93 = uitofp i32 %92 to float
  %94 = load float, ptr %7, align 4, !tbaa !15
  %95 = fdiv float %94, 8.192000e+03
  %96 = fadd float %93, %95
  %97 = fadd float %96, 1.000000e+00
  %98 = fmul float %88, %97
  store float %98, ptr %8, align 4, !tbaa !15
  br label %113

99:                                               ; preds = %47
  %100 = load i32, ptr %3, align 4, !tbaa !11
  %101 = uitofp i32 %100 to float
  %102 = fdiv float 4.000000e+06, %101
  %103 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %104 = zext i32 %103 to i64
  %105 = and i64 %104, 511
  %106 = trunc i64 %105 to i32
  %107 = uitofp i32 %106 to float
  %108 = load float, ptr %7, align 4, !tbaa !15
  %109 = fdiv float %108, 8.192000e+03
  %110 = fadd float %107, %109
  %111 = fadd float %110, 1.000000e+00
  %112 = fmul float %102, %111
  store float %112, ptr %8, align 4, !tbaa !15
  br label %113

113:                                              ; preds = %99, %85, %71, %49
  %114 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 12), align 4, !tbaa !17
  %115 = zext i32 %114 to i64
  %116 = and i64 %115, 65024
  %117 = lshr i64 %116, 9
  %118 = add i64 %117, 1
  %119 = trunc i64 %118 to i32
  store i32 %119, ptr %1, align 4, !tbaa !11
  %120 = load float, ptr %8, align 4, !tbaa !15
  %121 = load i32, ptr %1, align 4, !tbaa !11
  %122 = uitofp i32 %121 to float
  %123 = fdiv float %120, %122
  %124 = fptoui float %123 to i32
  store i32 %124, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %126

125:                                              ; preds = %21
  store i32 0, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %126

126:                                              ; preds = %125, %113
  br label %128

127:                                              ; preds = %0
  store i32 4000000, ptr @SystemCoreClock, align 4, !tbaa !11
  br label %128

128:                                              ; preds = %127, %126, %20, %19, %12
  %129 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 6), align 4, !tbaa !18
  %130 = zext i32 %129 to i64
  %131 = and i64 %130, 3840
  %132 = lshr i64 %131, 8
  %133 = getelementptr inbounds [16 x i8], ptr @D1CorePrescTable, i64 0, i64 %132
  %134 = load i8, ptr %133, align 1, !tbaa !19
  %135 = zext i8 %134 to i32
  store i32 %135, ptr %6, align 4, !tbaa !11
  %136 = load i32, ptr %6, align 4, !tbaa !11
  %137 = load i32, ptr @SystemCoreClock, align 4, !tbaa !11
  %138 = lshr i32 %137, %136
  store i32 %138, ptr @SystemCoreClock, align 4, !tbaa !11
  %139 = load i32, ptr @SystemCoreClock, align 4, !tbaa !11
  %140 = load volatile i32, ptr getelementptr inbounds (%struct.RCC_TypeDef, ptr inttoptr (i64 1476543488 to ptr), i32 0, i32 6), align 4, !tbaa !18
  %141 = zext i32 %140 to i64
  %142 = and i64 %141, 15
  %143 = lshr i64 %142, 0
  %144 = getelementptr inbounds [16 x i8], ptr @D1CorePrescTable, i64 0, i64 %143
  %145 = load i8, ptr %144, align 1, !tbaa !19
  %146 = zext i8 %145 to i32
  %147 = and i32 %146, 31
  %148 = lshr i32 %139, %147
  store i32 %148, ptr @SystemD2Clock, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 16}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !7, i64 88, !7, i64 92, !7, i64 96, !7, i64 100, !7, i64 104, !7, i64 108, !7, i64 112, !7, i64 116, !7, i64 120, !7, i64 124, !7, i64 128, !7, i64 132, !7, i64 136, !7, i64 140, !7, i64 144, !7, i64 148, !7, i64 152, !7, i64 156, !7, i64 160, !7, i64 164, !7, i64 168, !8, i64 172, !7, i64 208, !7, i64 212, !7, i64 216, !7, i64 220, !7, i64 224, !7, i64 228, !7, i64 232, !7, i64 236, !7, i64 240, !7, i64 244, !7, i64 248, !7, i64 252, !7, i64 256, !7, i64 260, !7, i64 264, !7, i64 268, !7, i64 272, !7, i64 276, !7, i64 280, !7, i64 284, !8, i64 288}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !7, i64 40}
!13 = !{!6, !7, i64 44}
!14 = !{!6, !7, i64 52}
!15 = !{!16, !16, i64 0}
!16 = !{!"float", !8, i64 0}
!17 = !{!6, !7, i64 48}
!18 = !{!6, !7, i64 24}
!19 = !{!8, !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@SystemCoreClock = external dso_local local_unnamed_addr global i32, align 4
@SystemD2Clock = external dso_local local_unnamed_addr global i32, align 4
@D1CorePrescTable = external dso_local local_unnamed_addr constant [16 x i8], align 16

; Function Attrs: mustprogress nofree norecurse nounwind willreturn uwtable
define dso_local void @SystemCoreClockUpdate() local_unnamed_addr #0 {
  %1 = load volatile i32, ptr inttoptr (i64 1476543504 to ptr), align 16, !tbaa !5
  %2 = lshr i32 %1, 3
  %3 = and i32 %2, 7
  switch i32 %3, label %47 [
    i32 0, label %4
    i32 3, label %10
    i32 2, label %9
  ]

4:                                                ; preds = %0
  %5 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %6 = lshr i32 %5, 3
  %7 = and i32 %6, 3
  %8 = lshr exact i32 64000000, %7
  br label %47

9:                                                ; preds = %0
  br label %47

10:                                               ; preds = %0
  %11 = load volatile i32, ptr inttoptr (i64 1476543528 to ptr), align 8, !tbaa !11
  %12 = load volatile i32, ptr inttoptr (i64 1476543528 to ptr), align 8, !tbaa !11
  %13 = lshr i32 %12, 4
  %14 = and i32 %13, 63
  %15 = load volatile i32, ptr inttoptr (i64 1476543532 to ptr), align 4, !tbaa !12
  %16 = load volatile i32, ptr inttoptr (i64 1476543540 to ptr), align 4, !tbaa !13
  %17 = lshr i32 %16, 3
  %18 = and i32 %17, 8191
  %19 = trunc i32 %15 to i1
  %20 = uitofp nneg i32 %18 to float
  %21 = fmul float %20, 0x3F20000000000000
  %.not = icmp eq i32 %14, 0
  br i1 %.not, label %47, label %22

22:                                               ; preds = %10
  %23 = and i32 %11, 3
  switch i32 %23, label %default.unreachable [
    i32 0, label %24
    i32 1, label %31
    i32 2, label %30
    i32 3, label %31
  ]

24:                                               ; preds = %22
  %25 = load volatile i32, ptr inttoptr (i64 1476543488 to ptr), align 1024, !tbaa !10
  %26 = lshr i32 %25, 3
  %27 = and i32 %26, 3
  %28 = lshr exact i32 64000000, %27
  %29 = uitofp nneg i32 %28 to float
  br label %31

30:                                               ; preds = %22
  br label %31

default.unreachable:                              ; preds = %22
  unreachable

31:                                               ; preds = %22, %22, %30, %24
  %.sink21 = phi float [ 2.500000e+07, %30 ], [ %29, %24 ], [ 4.000000e+06, %22 ], [ 4.000000e+06, %22 ]
  %32 = uitofp nneg i32 %14 to float
  %33 = fdiv float %.sink21, %32
  %34 = load volatile i32, ptr inttoptr (i64 1476543536 to ptr), align 16, !tbaa !14
  %35 = and i32 %34, 511
  %36 = uitofp nneg i32 %35 to float
  %37 = select i1 %19, float %21, float 0.000000e+00
  %38 = fadd float %37, %36
  %39 = fadd float %38, 1.000000e+00
  %40 = fmul float %33, %39
  %41 = load volatile i32, ptr inttoptr (i64 1476543536 to ptr), align 16, !tbaa !14
  %42 = lshr i32 %41, 9
  %43 = and i32 %42, 127
  %narrow = add nuw nsw i32 %43, 1
  %44 = uitofp nneg i32 %narrow to float
  %45 = fdiv float %40, %44
  %46 = fptoui float %45 to i32
  br label %47

47:                                               ; preds = %0, %10, %31, %9, %4
  %.sink = phi i32 [ %46, %31 ], [ 25000000, %9 ], [ %8, %4 ], [ 0, %10 ], [ 4000000, %0 ]
  store i32 %.sink, ptr @SystemCoreClock, align 4, !tbaa !15
  %48 = load volatile i32, ptr inttoptr (i64 1476543512 to ptr), align 8, !tbaa !16
  %49 = lshr i32 %48, 8
  %50 = and i32 %49, 15
  %51 = zext nneg i32 %50 to i64
  %52 = getelementptr inbounds [16 x i8], ptr @D1CorePrescTable, i64 0, i64 %51
  %53 = load i8, ptr %52, align 1, !tbaa !17
  %54 = zext nneg i8 %53 to i32
  %55 = lshr i32 %.sink, %54
  store i32 %55, ptr @SystemCoreClock, align 4, !tbaa !15
  %56 = load volatile i32, ptr inttoptr (i64 1476543512 to ptr), align 8, !tbaa !16
  %57 = and i32 %56, 15
  %58 = zext nneg i32 %57 to i64
  %59 = getelementptr inbounds [16 x i8], ptr @D1CorePrescTable, i64 0, i64 %58
  %60 = load i8, ptr %59, align 1, !tbaa !17
  %61 = and i8 %60, 31
  %62 = zext nneg i8 %61 to i32
  %63 = lshr i32 %55, %62
  store i32 %63, ptr @SystemD2Clock, align 4, !tbaa !15
  ret void
}

attributes #0 = { mustprogress nofree norecurse nounwind willreturn uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 16}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !7, i64 88, !7, i64 92, !7, i64 96, !7, i64 100, !7, i64 104, !7, i64 108, !7, i64 112, !7, i64 116, !7, i64 120, !7, i64 124, !7, i64 128, !7, i64 132, !7, i64 136, !7, i64 140, !7, i64 144, !7, i64 148, !7, i64 152, !7, i64 156, !7, i64 160, !7, i64 164, !7, i64 168, !8, i64 172, !7, i64 208, !7, i64 212, !7, i64 216, !7, i64 220, !7, i64 224, !7, i64 228, !7, i64 232, !7, i64 236, !7, i64 240, !7, i64 244, !7, i64 248, !7, i64 252, !7, i64 256, !7, i64 260, !7, i64 264, !7, i64 268, !7, i64 272, !7, i64 276, !7, i64 280, !7, i64 284, !8, i64 288}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = !{!6, !7, i64 40}
!12 = !{!6, !7, i64 44}
!13 = !{!6, !7, i64 52}
!14 = !{!6, !7, i64 48}
!15 = !{!7, !7, i64 0}
!16 = !{!6, !7, i64 24}
!17 = !{!8, !8, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass