; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions (q15)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_nn_accumulate_q7_to_q15(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %16, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %17, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %18 = load i32, ptr %6, align 4, !tbaa !9
  %19 = lshr i32 %18, 2
  store i32 %19, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  br label %20

20:                                               ; preds = %24, %3
  %21 = load i32, ptr %13, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = icmp sgt i64 %22, 0
  br i1 %23, label %24, label %57

24:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %25 = call i32 @arm_nn_read_q7x4_ia(ptr noundef %8)
  store i32 %25, ptr %15, align 4, !tbaa !9
  %26 = load i32, ptr %15, align 4, !tbaa !9
  %27 = call i32 @__ROR(i32 noundef %26, i32 noundef 8)
  %28 = call i32 @__SXTB16(i32 noundef %27)
  store i32 %28, ptr %9, align 4, !tbaa !9
  %29 = load i32, ptr %15, align 4, !tbaa !9
  %30 = call i32 @__SXTB16(i32 noundef %29)
  store i32 %30, ptr %10, align 4, !tbaa !9
  %31 = load i32, ptr %9, align 4, !tbaa !9
  %32 = shl i32 %31, 0
  %33 = and i32 %32, -65536
  %34 = load i32, ptr %10, align 4, !tbaa !9
  %35 = ashr i32 %34, 16
  %36 = and i32 %35, 65535
  %37 = or i32 %33, %36
  store i32 %37, ptr %12, align 4, !tbaa !9
  %38 = load i32, ptr %10, align 4, !tbaa !9
  %39 = shl i32 %38, 0
  %40 = and i32 %39, 65535
  %41 = load i32, ptr %9, align 4, !tbaa !9
  %42 = shl i32 %41, 16
  %43 = and i32 %42, -65536
  %44 = or i32 %40, %43
  store i32 %44, ptr %11, align 4, !tbaa !9
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = call i32 @arm_nn_read_q15x2(ptr noundef %45)
  store i32 %46, ptr %14, align 4, !tbaa !9
  %47 = load i32, ptr %11, align 4, !tbaa !9
  %48 = load i32, ptr %14, align 4, !tbaa !9
  %49 = call i32 @__QADD16(i32 noundef %47, i32 noundef %48)
  call void @write_q15x2_ia(ptr noundef %7, i32 noundef %49)
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = call i32 @arm_nn_read_q15x2(ptr noundef %50)
  store i32 %51, ptr %14, align 4, !tbaa !9
  %52 = load i32, ptr %12, align 4, !tbaa !9
  %53 = load i32, ptr %14, align 4, !tbaa !9
  %54 = call i32 @__QADD16(i32 noundef %52, i32 noundef %53)
  call void @write_q15x2_ia(ptr noundef %7, i32 noundef %54)
  %55 = load i32, ptr %13, align 4, !tbaa !9
  %56 = add nsw i32 %55, -1
  store i32 %56, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  br label %20, !llvm.loop !11

57:                                               ; preds = %20
  %58 = load i32, ptr %6, align 4, !tbaa !9
  %59 = and i32 %58, 3
  store i32 %59, ptr %13, align 4, !tbaa !9
  br label %60

60:                                               ; preds = %64, %57
  %61 = load i32, ptr %13, align 4, !tbaa !9
  %62 = sext i32 %61 to i64
  %63 = icmp sgt i64 %62, 0
  br i1 %63, label %64, label %77

64:                                               ; preds = %60
  %65 = load ptr, ptr %8, align 8, !tbaa !5
  %66 = getelementptr inbounds i8, ptr %65, i32 1
  store ptr %66, ptr %8, align 8, !tbaa !5
  %67 = load i8, ptr %65, align 1, !tbaa !13
  %68 = sext i8 %67 to i32
  %69 = load ptr, ptr %7, align 8, !tbaa !5
  %70 = getelementptr inbounds i16, ptr %69, i32 1
  store ptr %70, ptr %7, align 8, !tbaa !5
  %71 = load i16, ptr %69, align 2, !tbaa !14
  %72 = sext i16 %71 to i32
  %73 = add nsw i32 %72, %68
  %74 = trunc i32 %73 to i16
  store i16 %74, ptr %69, align 2, !tbaa !14
  %75 = load i32, ptr %13, align 4, !tbaa !9
  %76 = add nsw i32 %75, -1
  store i32 %76, ptr %13, align 4, !tbaa !9
  br label %60, !llvm.loop !16

77:                                               ; preds = %60
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q7x4_ia(ptr noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SXTB16(i32 noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__ROR(i32 noundef, i32 noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q15x2(ptr noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @write_q15x2_ia(ptr noundef, i32 noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__QADD16(i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"short", !7, i64 0}
!16 = distinct !{!16, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_nn_accumulate_q7_to_q15(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #3
  store ptr %0, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #3
  store ptr %1, ptr %5, align 8, !tbaa !5
  %.not = icmp ult i32 %2, 4
  br i1 %.not, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %3
  %6 = lshr i32 %2, 2
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %.017 = phi i32 [ %23, %.lr.ph ], [ %6, %.lr.ph.preheader ]
  %7 = call i32 @arm_nn_read_q7x4_ia(ptr noundef nonnull %5)
  %8 = call i32 @__ROR(i32 noundef %7, i32 noundef 8)
  %9 = call i32 @__SXTB16(i32 noundef %8)
  %10 = call i32 @__SXTB16(i32 noundef %7)
  %11 = and i32 %9, -65536
  %12 = lshr i32 %10, 16
  %13 = or disjoint i32 %12, %11
  %14 = and i32 %10, 65535
  %15 = shl i32 %9, 16
  %16 = or disjoint i32 %14, %15
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = call i32 @arm_nn_read_q15x2(ptr noundef %17)
  %19 = call i32 @__QADD16(i32 noundef %16, i32 noundef %18)
  call void @write_q15x2_ia(ptr noundef nonnull %4, i32 noundef %19)
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = call i32 @arm_nn_read_q15x2(ptr noundef %20)
  %22 = call i32 @__QADD16(i32 noundef %13, i32 noundef %21)
  call void @write_q15x2_ia(ptr noundef nonnull %4, i32 noundef %22)
  %23 = add nsw i32 %.017, -1
  %24 = icmp ugt i32 %.017, 1
  br i1 %24, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !9

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %.promoted.pre = load ptr, ptr %5, align 8, !tbaa !5
  %.promoted18.pre = load ptr, ptr %4, align 8, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %3
  %.promoted18 = phi ptr [ %.promoted18.pre, %._crit_edge.loopexit ], [ %0, %3 ]
  %.promoted = phi ptr [ %.promoted.pre, %._crit_edge.loopexit ], [ %1, %3 ]
  %25 = and i32 %2, 3
  %.not23 = icmp eq i32 %25, 0
  br i1 %.not23, label %._crit_edge22, label %.lr.ph21

.lr.ph21:                                         ; preds = %._crit_edge
  %26 = getelementptr inbounds i8, ptr %.promoted, i64 1
  store ptr %26, ptr %5, align 8, !tbaa !5
  %27 = load i8, ptr %.promoted, align 1, !tbaa !11
  %28 = sext i8 %27 to i16
  %29 = getelementptr inbounds i8, ptr %.promoted18, i64 2
  store ptr %29, ptr %4, align 8, !tbaa !5
  %30 = load i16, ptr %.promoted18, align 2, !tbaa !12
  %31 = add i16 %30, %28
  store i16 %31, ptr %.promoted18, align 2, !tbaa !12
  %.not26 = icmp eq i32 %25, 1
  br i1 %.not26, label %._crit_edge22, label %.lr.ph21.1, !llvm.loop !14

.lr.ph21.1:                                       ; preds = %.lr.ph21
  %32 = getelementptr inbounds i8, ptr %.promoted, i64 2
  store ptr %32, ptr %5, align 8, !tbaa !5
  %33 = load i8, ptr %26, align 1, !tbaa !11
  %34 = sext i8 %33 to i16
  %35 = getelementptr inbounds i8, ptr %.promoted18, i64 4
  store ptr %35, ptr %4, align 8, !tbaa !5
  %36 = load i16, ptr %29, align 2, !tbaa !12
  %37 = add i16 %36, %34
  store i16 %37, ptr %29, align 2, !tbaa !12
  %38 = add nsw i32 %25, -3
  %39 = icmp ult i32 %38, -2
  br i1 %39, label %.lr.ph21.2, label %._crit_edge22, !llvm.loop !14

.lr.ph21.2:                                       ; preds = %.lr.ph21.1
  %40 = getelementptr inbounds i8, ptr %.promoted, i64 3
  store ptr %40, ptr %5, align 8, !tbaa !5
  %41 = load i8, ptr %32, align 1, !tbaa !11
  %42 = sext i8 %41 to i16
  %43 = getelementptr inbounds i8, ptr %.promoted18, i64 6
  store ptr %43, ptr %4, align 8, !tbaa !5
  %44 = load i16, ptr %35, align 2, !tbaa !12
  %45 = add i16 %44, %42
  store i16 %45, ptr %35, align 2, !tbaa !12
  br label %._crit_edge22

._crit_edge22:                                    ; preds = %.lr.ph21, %.lr.ph21.1, %.lr.ph21.2, %._crit_edge
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q7x4_ia(ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SXTB16(i32 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__ROR(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q15x2(ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @write_q15x2_ia(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__QADD16(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"short", !7, i64 0}
!14 = distinct !{!14, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass