; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions (arm_nn_mult_q15)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_nn_mult_q15(ptr noundef %0, ptr noundef %1, ptr noundef %2, i16 noundef zeroext %3, i32 noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %12 = load i32, ptr %10, align 4, !tbaa !11
  store i32 %12, ptr %11, align 4, !tbaa !11
  br label %13

13:                                               ; preds = %16, %5
  %14 = load i32, ptr %11, align 4, !tbaa !11
  %15 = icmp ugt i32 %14, 0
  br i1 %15, label %16, label %40

16:                                               ; preds = %13
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = getelementptr inbounds i16, ptr %17, i32 1
  store ptr %18, ptr %6, align 8, !tbaa !5
  %19 = load i16, ptr %17, align 2, !tbaa !9
  %20 = sext i16 %19 to i32
  %21 = load ptr, ptr %7, align 8, !tbaa !5
  %22 = getelementptr inbounds i16, ptr %21, i32 1
  store ptr %22, ptr %7, align 8, !tbaa !5
  %23 = load i16, ptr %21, align 2, !tbaa !9
  %24 = sext i16 %23 to i32
  %25 = mul nsw i32 %20, %24
  %26 = load i16, ptr %9, align 2, !tbaa !9
  %27 = zext i16 %26 to i32
  %28 = shl i32 1, %27
  %29 = lshr i32 %28, 1
  %30 = add i32 %25, %29
  %31 = load i16, ptr %9, align 2, !tbaa !9
  %32 = zext i16 %31 to i32
  %33 = ashr i32 %30, %32
  %34 = call i32 @__SSAT(i32 noundef %33, i32 noundef 16)
  %35 = trunc i32 %34 to i16
  %36 = load ptr, ptr %8, align 8, !tbaa !5
  %37 = getelementptr inbounds i16, ptr %36, i32 1
  store ptr %37, ptr %8, align 8, !tbaa !5
  store i16 %35, ptr %36, align 2, !tbaa !9
  %38 = load i32, ptr %11, align 4, !tbaa !11
  %39 = add i32 %38, -1
  store i32 %39, ptr %11, align 4, !tbaa !11
  br label %13, !llvm.loop !13

40:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SSAT(i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_nn_mult_q15(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2, i16 noundef zeroext %3, i32 noundef %4) local_unnamed_addr #0 {
  %.not10 = icmp eq i32 %4, 0
  br i1 %.not10, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %5
  %6 = zext i16 %3 to i32
  %7 = shl nuw i32 1, %6
  %8 = lshr i32 %7, 1
  br label %9

9:                                                ; preds = %.lr.ph, %9
  %.014 = phi i32 [ %4, %.lr.ph ], [ %22, %9 ]
  %.0713 = phi ptr [ %0, %.lr.ph ], [ %10, %9 ]
  %.0812 = phi ptr [ %1, %.lr.ph ], [ %13, %9 ]
  %.0911 = phi ptr [ %2, %.lr.ph ], [ %21, %9 ]
  %10 = getelementptr inbounds i8, ptr %.0713, i64 2
  %11 = load i16, ptr %.0713, align 2, !tbaa !5
  %12 = sext i16 %11 to i32
  %13 = getelementptr inbounds i8, ptr %.0812, i64 2
  %14 = load i16, ptr %.0812, align 2, !tbaa !5
  %15 = sext i16 %14 to i32
  %16 = mul nsw i32 %15, %12
  %17 = add i32 %16, %8
  %18 = ashr i32 %17, %6
  %19 = tail call i32 @__SSAT(i32 noundef %18, i32 noundef 16)
  %20 = trunc i32 %19 to i16
  %21 = getelementptr inbounds i8, ptr %.0911, i64 2
  store i16 %20, ptr %.0911, align 2, !tbaa !5
  %22 = add i32 %.014, -1
  %.not = icmp eq i32 %22, 0
  br i1 %.not, label %._crit_edge, label %9, !llvm.loop !9

._crit_edge:                                      ; preds = %9, %5
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SSAT(i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass