; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMAConvCplt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @ADC_DMAConvCplt(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #3
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %4, i32 0, i32 4
  %6 = load ptr, ptr %5, align 8, !tbaa !9
  store ptr %6, ptr %3, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %7, i32 0, i32 4
  %9 = load volatile i32, ptr %8, align 4, !tbaa !13
  %10 = zext i32 %9 to i64
  %11 = and i64 %10, 80
  %12 = icmp eq i64 %11, 0
  br i1 %12, label %13, label %100

13:                                               ; preds = %1
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %14, i32 0, i32 4
  %16 = load volatile i32, ptr %15, align 4, !tbaa !13
  %17 = zext i32 %16 to i64
  %18 = or i64 %17, 512
  %19 = trunc i64 %18 to i32
  store volatile i32 %19, ptr %15, align 4, !tbaa !13
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %20, i32 0, i32 0
  %22 = load ptr, ptr %21, align 8, !tbaa !18
  %23 = getelementptr inbounds %struct.ADC_TypeDef, ptr %22, i32 0, i32 0
  %24 = load volatile i32, ptr %23, align 4, !tbaa !19
  %25 = zext i32 %24 to i64
  %26 = and i64 %25, 8
  %27 = icmp ne i64 %26, 0
  br i1 %27, label %28, label %67

28:                                               ; preds = %13
  %29 = load ptr, ptr %3, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %29, i32 0, i32 0
  %31 = load ptr, ptr %30, align 8, !tbaa !18
  %32 = call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef %31)
  %33 = zext i32 %32 to i64
  %34 = icmp ne i64 %33, 0
  br i1 %34, label %35, label %66

35:                                               ; preds = %28
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !18
  %39 = getelementptr inbounds %struct.ADC_TypeDef, ptr %38, i32 0, i32 3
  %40 = load volatile i32, ptr %39, align 4, !tbaa !21
  %41 = zext i32 %40 to i64
  %42 = and i64 %41, 8192
  %43 = icmp eq i64 %42, 0
  br i1 %43, label %44, label %65

44:                                               ; preds = %35
  %45 = load ptr, ptr %3, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %45, i32 0, i32 4
  %47 = load volatile i32, ptr %46, align 4, !tbaa !13
  %48 = zext i32 %47 to i64
  %49 = and i64 %48, -257
  %50 = trunc i64 %49 to i32
  store volatile i32 %50, ptr %46, align 4, !tbaa !13
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %51, i32 0, i32 4
  %53 = load volatile i32, ptr %52, align 4, !tbaa !13
  %54 = zext i32 %53 to i64
  %55 = and i64 %54, 4096
  %56 = icmp eq i64 %55, 0
  br i1 %56, label %57, label %64

57:                                               ; preds = %44
  %58 = load ptr, ptr %3, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %58, i32 0, i32 4
  %60 = load volatile i32, ptr %59, align 4, !tbaa !13
  %61 = zext i32 %60 to i64
  %62 = or i64 %61, 1
  %63 = trunc i64 %62 to i32
  store volatile i32 %63, ptr %59, align 4, !tbaa !13
  br label %64

64:                                               ; preds = %57, %44
  br label %65

65:                                               ; preds = %64, %35
  br label %66

66:                                               ; preds = %65, %28
  br label %98

67:                                               ; preds = %13
  %68 = load ptr, ptr %3, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %68, i32 0, i32 0
  %70 = load ptr, ptr %69, align 8, !tbaa !18
  %71 = getelementptr inbounds %struct.ADC_TypeDef, ptr %70, i32 0, i32 3
  %72 = load volatile i32, ptr %71, align 4, !tbaa !21
  %73 = zext i32 %72 to i64
  %74 = and i64 %73, 3
  %75 = icmp eq i64 %74, 0
  br i1 %75, label %76, label %97

76:                                               ; preds = %67
  %77 = load ptr, ptr %3, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %77, i32 0, i32 4
  %79 = load volatile i32, ptr %78, align 4, !tbaa !13
  %80 = zext i32 %79 to i64
  %81 = and i64 %80, -257
  %82 = trunc i64 %81 to i32
  store volatile i32 %82, ptr %78, align 4, !tbaa !13
  %83 = load ptr, ptr %3, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %83, i32 0, i32 4
  %85 = load volatile i32, ptr %84, align 4, !tbaa !13
  %86 = zext i32 %85 to i64
  %87 = and i64 %86, 4096
  %88 = icmp eq i64 %87, 0
  br i1 %88, label %89, label %96

89:                                               ; preds = %76
  %90 = load ptr, ptr %3, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %90, i32 0, i32 4
  %92 = load volatile i32, ptr %91, align 4, !tbaa !13
  %93 = zext i32 %92 to i64
  %94 = or i64 %93, 1
  %95 = trunc i64 %94 to i32
  store volatile i32 %95, ptr %91, align 4, !tbaa !13
  br label %96

96:                                               ; preds = %89, %76
  br label %97

97:                                               ; preds = %96, %67
  br label %98

98:                                               ; preds = %97, %66
  %99 = load ptr, ptr %3, align 8, !tbaa !5
  call void @HAL_ADC_ConvCpltCallback(ptr noundef %99)
  br label %117

100:                                              ; preds = %1
  %101 = load ptr, ptr %3, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %101, i32 0, i32 4
  %103 = load volatile i32, ptr %102, align 4, !tbaa !13
  %104 = zext i32 %103 to i64
  %105 = and i64 %104, 16
  %106 = icmp ne i64 %105, 0
  br i1 %106, label %107, label %109

107:                                              ; preds = %100
  %108 = load ptr, ptr %3, align 8, !tbaa !5
  call void @HAL_ADC_ErrorCallback(ptr noundef %108)
  br label %116

109:                                              ; preds = %100
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %110, i32 0, i32 2
  %112 = load ptr, ptr %111, align 8, !tbaa !22
  %113 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %112, i32 0, i32 9
  %114 = load ptr, ptr %113, align 8, !tbaa !23
  %115 = load ptr, ptr %2, align 8, !tbaa !5
  call void %114(ptr noundef %115)
  br label %116

116:                                              ; preds = %109, %107
  br label %117

117:                                              ; preds = %116, %98
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #3
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_ConvCpltCallback(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_ErrorCallback(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 64}
!10 = !{!"__DMA_HandleTypeDef", !6, i64 0, !11, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 100}
!14 = !{!"", !6, i64 0, !15, i64 8, !6, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !17, i64 108}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !16, i64 60}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!17 = !{!"", !12, i64 0, !12, i64 4}
!18 = !{!14, !6, i64 0}
!19 = !{!20, !12, i64 0}
!20 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !7, i64 112, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !7, i64 144, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200}
!21 = !{!20, !12, i64 12}
!22 = !{!14, !6, i64 88}
!23 = !{!10, !6, i64 104}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @ADC_DMAConvCplt(ptr noundef %0) local_unnamed_addr #1 {
  %2 = getelementptr inbounds i8, ptr %0, i64 64
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %3, i64 100
  %5 = load volatile i32, ptr %4, align 4, !tbaa !12
  %6 = and i32 %5, 80
  %7 = icmp eq i32 %6, 0
  %8 = load volatile i32, ptr %4, align 4, !tbaa !12
  br i1 %7, label %9, label %42

9:                                                ; preds = %1
  %10 = or i32 %8, 512
  store volatile i32 %10, ptr %4, align 4, !tbaa !12
  %11 = load ptr, ptr %3, align 8, !tbaa !17
  %12 = load volatile i32, ptr %11, align 4, !tbaa !18
  %13 = and i32 %12, 8
  %.not18 = icmp eq i32 %13, 0
  br i1 %.not18, label %28, label %14

14:                                               ; preds = %9
  %15 = tail call i32 @LL_ADC_REG_IsTriggerSourceSWStart(ptr noundef nonnull %11)
  %.not19 = icmp eq i32 %15, 0
  br i1 %.not19, label %41, label %16

16:                                               ; preds = %14
  %17 = load ptr, ptr %3, align 8, !tbaa !17
  %18 = getelementptr inbounds i8, ptr %17, i64 12
  %19 = load volatile i32, ptr %18, align 4, !tbaa !20
  %20 = and i32 %19, 8192
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %41

22:                                               ; preds = %16
  %23 = load volatile i32, ptr %4, align 4, !tbaa !12
  %24 = and i32 %23, -257
  store volatile i32 %24, ptr %4, align 4, !tbaa !12
  %25 = load volatile i32, ptr %4, align 4, !tbaa !12
  %26 = and i32 %25, 4096
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %.sink.split, label %41

28:                                               ; preds = %9
  %29 = getelementptr inbounds i8, ptr %11, i64 12
  %30 = load volatile i32, ptr %29, align 4, !tbaa !20
  %31 = and i32 %30, 3
  %32 = icmp eq i32 %31, 0
  br i1 %32, label %33, label %41

33:                                               ; preds = %28
  %34 = load volatile i32, ptr %4, align 4, !tbaa !12
  %35 = and i32 %34, -257
  store volatile i32 %35, ptr %4, align 4, !tbaa !12
  %36 = load volatile i32, ptr %4, align 4, !tbaa !12
  %37 = and i32 %36, 4096
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %.sink.split, label %41

.sink.split:                                      ; preds = %33, %22
  %39 = load volatile i32, ptr %4, align 4, !tbaa !12
  %40 = or i32 %39, 1
  store volatile i32 %40, ptr %4, align 4, !tbaa !12
  br label %41

41:                                               ; preds = %.sink.split, %28, %33, %14, %22, %16
  tail call void @HAL_ADC_ConvCpltCallback(ptr noundef nonnull %3)
  br label %50

42:                                               ; preds = %1
  %43 = and i32 %8, 16
  %.not = icmp eq i32 %43, 0
  br i1 %.not, label %45, label %44

44:                                               ; preds = %42
  tail call void @HAL_ADC_ErrorCallback(ptr noundef nonnull %3)
  br label %50

45:                                               ; preds = %42
  %46 = getelementptr inbounds i8, ptr %3, i64 88
  %47 = load ptr, ptr %46, align 8, !tbaa !21
  %48 = getelementptr inbounds i8, ptr %47, i64 104
  %49 = load ptr, ptr %48, align 8, !tbaa !22
  tail call void %49(ptr noundef nonnull %0) #2
  br label %50

50:                                               ; preds = %44, %45, %41
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_ConvCpltCallback(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_ADC_ErrorCallback(ptr noundef) local_unnamed_addr #1

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 64}
!6 = !{!"__DMA_HandleTypeDef", !7, i64 0, !10, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 100}
!13 = !{!"", !7, i64 0, !14, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !16, i64 108}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !15, i64 60}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!16 = !{!"", !11, i64 0, !11, i64 4}
!17 = !{!13, !7, i64 0}
!18 = !{!19, !11, i64 0}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!20 = !{!19, !11, i64 12}
!21 = !{!13, !7, i64 88}
!22 = !{!6, !7, i64 104}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass