; LLVM IR from Xingyu-Lin/softgym :: PyFlex/extensions (flexExtContainer)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NvFlexExtContainer = type <{ i32, [4 x i8], ptr, ptr, %struct.NvFlexVector, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %struct.NvFlexVector.10, %struct.NvFlexVector.10, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector.10, %struct.NvFlexVector, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.16, %struct.NvFlexVector.12, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.12, %struct.NvFlexVector.12, i8, i8, [6 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl" }
%"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl" = type { %"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl" }
%"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl" = type { %"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.NvFlexVector.10 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.16 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.14 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.12 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local i32 @NvFlexExtAllocParticles(ptr noundef %0, i32 noundef %1, ptr noundef %2) #1 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %9, i32 0, i32 5
  %11 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #5
  %12 = trunc i64 %11 to i32
  %13 = load i32, ptr %5, align 4, !tbaa !9
  %14 = call noundef i32 @_Z3MinIiET_S0_S0_(i32 noundef %12, i32 noundef %13)
  store i32 %14, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %15, i32 0, i32 5
  %17 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #5
  %18 = trunc i64 %17 to i32
  %19 = load i32, ptr %7, align 4, !tbaa !9
  %20 = sub nsw i32 %18, %19
  store i32 %20, ptr %8, align 4, !tbaa !9
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %37

23:                                               ; preds = %3
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %25, i32 0, i32 5
  %27 = load i32, ptr %8, align 4, !tbaa !9
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %28) #5
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = mul i64 %31, 4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %24, ptr align 4 %29, i64 %32, i1 false)
  %33 = load ptr, ptr %4, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %33, i32 0, i32 5
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  call void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36)
  br label %37

37:                                               ; preds = %23, %3
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %38, i32 0, i32 34
  store i8 1, ptr %39, align 1, !tbaa !11
  %40 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  ret i32 %40
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z3MinIiET_S0_S0_(i32 noundef, i32 noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !31, i64 1137}
!12 = !{!"_ZTS18NvFlexExtContainer", !10, i64 0, !6, i64 8, !6, i64 16, !13, i64 24, !15, i64 64, !19, i64 88, !23, i64 112, !27, i64 136, !27, i64 176, !28, i64 216, !13, i64 256, !27, i64 296, !13, i64 336, !13, i64 376, !29, i64 416, !29, i64 456, !29, i64 496, !30, i64 536, !28, i64 576, !28, i64 616, !13, i64 656, !29, i64 696, !29, i64 736, !13, i64 776, !28, i64 816, !13, i64 856, !13, i64 896, !29, i64 936, !29, i64 976, !29, i64 1016, !28, i64 1056, !28, i64 1096, !31, i64 1136, !31, i64 1137}
!13 = !{!"_ZTS12NvFlexVectorIiE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!14 = !{!"_ZTS16NvFlexBufferType", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIiSaIiEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIP17NvFlexExtInstanceSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIP18NvFlexExtSoftJointSaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTS12NvFlexVectorI8XVector4IfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!28 = !{!"_ZTS12NvFlexVectorI8XVector3IfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!29 = !{!"_ZTS12NvFlexVectorIfE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!30 = !{!"_ZTS12NvFlexVectorI5XQuatIfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!31 = !{!"bool", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @NvFlexExtAllocParticles(ptr noundef %0, i32 noundef %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 64
  %5 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  %6 = trunc i64 %5 to i32
  %7 = tail call noundef i32 @_Z3MinIiET_S0_S0_(i32 noundef %6, i32 noundef %1)
  %8 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  %.not = icmp eq i32 %7, 0
  br i1 %.not, label %16, label %9

9:                                                ; preds = %3
  %10 = trunc i64 %8 to i32
  %11 = sub nsw i32 %10, %7
  %12 = sext i32 %11 to i64
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %12) #4
  %14 = sext i32 %7 to i64
  %15 = shl nsw i64 %14, 2
  tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %2, ptr nonnull align 4 %13, i64 %15, i1 false)
  tail call void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %12)
  br label %16

16:                                               ; preds = %9, %3
  %17 = getelementptr inbounds i8, ptr %0, i64 1137
  store i8 1, ptr %17, align 1, !tbaa !5
  ret i32 %7
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z3MinIiET_S0_S0_(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !29, i64 1137}
!6 = !{!"_ZTS18NvFlexExtContainer", !7, i64 0, !10, i64 8, !10, i64 16, !11, i64 24, !13, i64 64, !17, i64 88, !21, i64 112, !25, i64 136, !25, i64 176, !26, i64 216, !11, i64 256, !25, i64 296, !11, i64 336, !11, i64 376, !27, i64 416, !27, i64 456, !27, i64 496, !28, i64 536, !26, i64 576, !26, i64 616, !11, i64 656, !27, i64 696, !27, i64 736, !11, i64 776, !26, i64 816, !11, i64 856, !11, i64 896, !27, i64 936, !27, i64 976, !27, i64 1016, !26, i64 1056, !26, i64 1096, !29, i64 1136, !29, i64 1137}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!"_ZTS12NvFlexVectorIiE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!12 = !{!"_ZTS16NvFlexBufferType", !8, i64 0}
!13 = !{!"_ZTSSt6vectorIiSaIiEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!17 = !{!"_ZTSSt6vectorIP17NvFlexExtInstanceSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!21 = !{!"_ZTSSt6vectorIP18NvFlexExtSoftJointSaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!25 = !{!"_ZTS12NvFlexVectorI8XVector4IfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!26 = !{!"_ZTS12NvFlexVectorI8XVector3IfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!27 = !{!"_ZTS12NvFlexVectorIfE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!28 = !{!"_ZTS12NvFlexVectorI5XQuatIfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!29 = !{!"bool", !8, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass