; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/QCBOR/src (ieee754)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.IEEE754_union = type { i8, i64 }

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @IEEE754_FloatToHalf(float noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @CopyFloatToUint32(float noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local { i8, i64 } @IEEE754_FloatToSmallest(float noundef %0) #0 {
  %2 = alloca %struct.IEEE754_union, align 8
  %3 = alloca float, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  store float %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  %8 = load float, ptr %3, align 4, !tbaa !5
  %9 = call i32 @CopyFloatToUint32(float noundef %8)
  store i32 %9, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %10 = load i32, ptr %4, align 4, !tbaa !9
  %11 = zext i32 %10 to i64
  %12 = and i64 %11, 2139095040
  %13 = lshr i64 %12, 23
  %14 = sub i64 %13, 127
  %15 = trunc i64 %14 to i32
  store i32 %15, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %16 = load i32, ptr %4, align 4, !tbaa !9
  %17 = zext i32 %16 to i64
  %18 = and i64 %17, 8388607
  %19 = trunc i64 %18 to i32
  store i32 %19, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store i64 8191, ptr %7, align 8, !tbaa !11
  %20 = load i32, ptr %4, align 4, !tbaa !9
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %28

22:                                               ; preds = %1
  %23 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 0
  store i8 2, ptr %23, align 8, !tbaa !13
  %24 = load float, ptr %3, align 4, !tbaa !5
  %25 = call zeroext i16 @IEEE754_FloatToHalf(float noundef %24)
  %26 = zext i16 %25 to i64
  %27 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 1
  store i64 %26, ptr %27, align 8, !tbaa !15
  br label %61

28:                                               ; preds = %1
  %29 = load i32, ptr %5, align 4, !tbaa !9
  %30 = icmp eq i32 %29, 128
  br i1 %30, label %31, label %37

31:                                               ; preds = %28
  %32 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 0
  store i8 2, ptr %32, align 8, !tbaa !13
  %33 = load float, ptr %3, align 4, !tbaa !5
  %34 = call zeroext i16 @IEEE754_FloatToHalf(float noundef %33)
  %35 = zext i16 %34 to i64
  %36 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 1
  store i64 %35, ptr %36, align 8, !tbaa !15
  br label %60

37:                                               ; preds = %28
  %38 = load i32, ptr %5, align 4, !tbaa !9
  %39 = icmp sge i32 %38, -14
  br i1 %39, label %40, label %54

40:                                               ; preds = %37
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = icmp sle i32 %41, 15
  br i1 %42, label %43, label %54

43:                                               ; preds = %40
  %44 = load i32, ptr %6, align 4, !tbaa !9
  %45 = zext i32 %44 to i64
  %46 = and i64 %45, 8191
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %54, label %48

48:                                               ; preds = %43
  %49 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 0
  store i8 2, ptr %49, align 8, !tbaa !13
  %50 = load float, ptr %3, align 4, !tbaa !5
  %51 = call zeroext i16 @IEEE754_FloatToHalf(float noundef %50)
  %52 = zext i16 %51 to i64
  %53 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 1
  store i64 %52, ptr %53, align 8, !tbaa !15
  br label %59

54:                                               ; preds = %43, %40, %37
  %55 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 0
  store i8 4, ptr %55, align 8, !tbaa !13
  %56 = load i32, ptr %4, align 4, !tbaa !9
  %57 = zext i32 %56 to i64
  %58 = getelementptr inbounds %struct.IEEE754_union, ptr %2, i32 0, i32 1
  store i64 %57, ptr %58, align 8, !tbaa !15
  br label %59

59:                                               ; preds = %54, %48
  br label %60

60:                                               ; preds = %59, %31
  br label %61

61:                                               ; preds = %60, %22
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %62 = load { i8, i64 }, ptr %2, align 8
  ret { i8, i64 } %62
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !7, i64 0}
!14 = !{!"", !7, i64 0, !12, i64 8}
!15 = !{!14, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @IEEE754_FloatToHalf(float noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @CopyFloatToUint32(float noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local { i8, i64 } @IEEE754_FloatToSmallest(float noundef %0) local_unnamed_addr #0 {
  %2 = tail call i32 @CopyFloatToUint32(float noundef %0)
  %3 = lshr i32 %2, 23
  %4 = and i32 %3, 255
  %5 = icmp eq i32 %2, 0
  %6 = icmp eq i32 %4, 255
  %or.cond13 = or i1 %5, %6
  br i1 %or.cond13, label %.sink.split, label %7

7:                                                ; preds = %1
  %8 = zext i32 %2 to i64
  %9 = add nsw i32 %4, -113
  %or.cond = icmp ult i32 %9, 30
  %10 = and i32 %2, 8191
  %.not = icmp eq i32 %10, 0
  %or.cond12 = and i1 %.not, %or.cond
  br i1 %or.cond12, label %.sink.split, label %13

.sink.split:                                      ; preds = %7, %1
  %11 = tail call zeroext i16 @IEEE754_FloatToHalf(float noundef %0)
  %12 = zext i16 %11 to i64
  br label %13

13:                                               ; preds = %.sink.split, %7
  %.sroa.0.0 = phi i8 [ 4, %7 ], [ 2, %.sink.split ]
  %.sroa.5.0 = phi i64 [ %8, %7 ], [ %12, %.sink.split ]
  %.fca.0.insert = insertvalue { i8, i64 } poison, i8 %.sroa.0.0, 0
  %.fca.1.insert = insertvalue { i8, i64 } %.fca.0.insert, i64 %.sroa.5.0, 1
  ret { i8, i64 } %.fca.1.insert
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass