; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConversionStop)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @ADC_ConversionStop(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %13 = load i32, ptr %5, align 4, !tbaa !9
  store i32 %13, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %14, i32 0, i32 0
  %16 = load ptr, ptr %15, align 8, !tbaa !11
  %17 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %16)
  store i32 %17, ptr %10, align 4, !tbaa !9
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %18, i32 0, i32 0
  %20 = load ptr, ptr %19, align 8, !tbaa !11
  %21 = call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %20)
  store i32 %21, ptr %11, align 4, !tbaa !9
  %22 = load i32, ptr %10, align 4, !tbaa !9
  %23 = zext i32 %22 to i64
  %24 = icmp ne i64 %23, 0
  br i1 %24, label %29, label %25

25:                                               ; preds = %2
  %26 = load i32, ptr %11, align 4, !tbaa !9
  %27 = zext i32 %26 to i64
  %28 = icmp ne i64 %27, 0
  br i1 %28, label %29, label %170

29:                                               ; preds = %25, %2
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 0
  %32 = load ptr, ptr %31, align 8, !tbaa !11
  %33 = getelementptr inbounds %struct.ADC_TypeDef, ptr %32, i32 0, i32 3
  %34 = load volatile i32, ptr %33, align 4, !tbaa !16
  %35 = zext i32 %34 to i64
  %36 = and i64 %35, 33554432
  %37 = icmp ne i64 %36, 0
  br i1 %37, label %38, label %86

38:                                               ; preds = %29
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 1
  %41 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %40, i32 0, i32 5
  %42 = load i32, ptr %41, align 4, !tbaa !18
  %43 = icmp eq i32 %42, 1
  br i1 %43, label %44, label %86

44:                                               ; preds = %38
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %45, i32 0, i32 1
  %47 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %46, i32 0, i32 4
  %48 = load i32, ptr %47, align 8, !tbaa !19
  %49 = icmp eq i32 %48, 1
  br i1 %49, label %50, label %86

50:                                               ; preds = %44
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %51

51:                                               ; preds = %78, %50
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !11
  %55 = getelementptr inbounds %struct.ADC_TypeDef, ptr %54, i32 0, i32 0
  %56 = load volatile i32, ptr %55, align 4, !tbaa !20
  %57 = zext i32 %56 to i64
  %58 = and i64 %57, 64
  %59 = icmp eq i64 %58, 64
  %60 = zext i1 %59 to i32
  %61 = sext i32 %60 to i64
  %62 = icmp eq i64 %61, 0
  br i1 %62, label %63, label %81

63:                                               ; preds = %51
  %64 = load i32, ptr %7, align 4, !tbaa !9
  %65 = zext i32 %64 to i64
  %66 = icmp uge i64 %65, 842752
  br i1 %66, label %67, label %78

67:                                               ; preds = %63
  %68 = load ptr, ptr %4, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %68, i32 0, i32 4
  %70 = load volatile i32, ptr %69, align 4, !tbaa !21
  %71 = zext i32 %70 to i64
  %72 = or i64 %71, 16
  %73 = trunc i64 %72 to i32
  store volatile i32 %73, ptr %69, align 4, !tbaa !21
  %74 = load ptr, ptr %4, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %74, i32 0, i32 5
  %76 = load volatile i32, ptr %75, align 8, !tbaa !22
  %77 = or i32 %76, 1
  store volatile i32 %77, ptr %75, align 8, !tbaa !22
  store i32 1, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %171

78:                                               ; preds = %63
  %79 = load i32, ptr %7, align 4, !tbaa !9
  %80 = add i32 %79, 1
  store i32 %80, ptr %7, align 4, !tbaa !9
  br label %51, !llvm.loop !23

81:                                               ; preds = %51
  %82 = load ptr, ptr %4, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !11
  %85 = getelementptr inbounds %struct.ADC_TypeDef, ptr %84, i32 0, i32 0
  store volatile i32 64, ptr %85, align 4, !tbaa !20
  br label %86

86:                                               ; preds = %81, %44, %38, %29
  %87 = load i32, ptr %8, align 4, !tbaa !9
  %88 = zext i32 %87 to i64
  %89 = icmp ne i64 %88, 2
  br i1 %89, label %90, label %110

90:                                               ; preds = %86
  %91 = load ptr, ptr %4, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !11
  %94 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %93)
  %95 = zext i32 %94 to i64
  %96 = icmp ne i64 %95, 0
  br i1 %96, label %97, label %109

97:                                               ; preds = %90
  %98 = load ptr, ptr %4, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %98, i32 0, i32 0
  %100 = load ptr, ptr %99, align 8, !tbaa !11
  %101 = call i32 @LL_ADC_IsDisableOngoing(ptr noundef %100)
  %102 = zext i32 %101 to i64
  %103 = icmp eq i64 %102, 0
  br i1 %103, label %104, label %108

104:                                              ; preds = %97
  %105 = load ptr, ptr %4, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %105, i32 0, i32 0
  %107 = load ptr, ptr %106, align 8, !tbaa !11
  call void @LL_ADC_REG_StopConversion(ptr noundef %107)
  br label %108

108:                                              ; preds = %104, %97
  br label %109

109:                                              ; preds = %108, %90
  br label %110

110:                                              ; preds = %109, %86
  %111 = load i32, ptr %8, align 4, !tbaa !9
  %112 = zext i32 %111 to i64
  %113 = icmp ne i64 %112, 1
  br i1 %113, label %114, label %134

114:                                              ; preds = %110
  %115 = load ptr, ptr %4, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !11
  %118 = call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %117)
  %119 = zext i32 %118 to i64
  %120 = icmp ne i64 %119, 0
  br i1 %120, label %121, label %133

121:                                              ; preds = %114
  %122 = load ptr, ptr %4, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %122, i32 0, i32 0
  %124 = load ptr, ptr %123, align 8, !tbaa !11
  %125 = call i32 @LL_ADC_IsDisableOngoing(ptr noundef %124)
  %126 = zext i32 %125 to i64
  %127 = icmp eq i64 %126, 0
  br i1 %127, label %128, label %132

128:                                              ; preds = %121
  %129 = load ptr, ptr %4, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %129, i32 0, i32 0
  %131 = load ptr, ptr %130, align 8, !tbaa !11
  call void @LL_ADC_INJ_StopConversion(ptr noundef %131)
  br label %132

132:                                              ; preds = %128, %121
  br label %133

133:                                              ; preds = %132, %114
  br label %134

134:                                              ; preds = %133, %110
  %135 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %135, label %138 [
    i32 3, label %136
    i32 2, label %137
  ]

136:                                              ; preds = %134
  store i32 12, ptr %9, align 4, !tbaa !9
  br label %139

137:                                              ; preds = %134
  store i32 8, ptr %9, align 4, !tbaa !9
  br label %139

138:                                              ; preds = %134
  store i32 4, ptr %9, align 4, !tbaa !9
  br label %139

139:                                              ; preds = %138, %137, %136
  %140 = call i32 @HAL_GetTick()
  store i32 %140, ptr %6, align 4, !tbaa !9
  br label %141

141:                                              ; preds = %168, %139
  %142 = load ptr, ptr %4, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %142, i32 0, i32 0
  %144 = load ptr, ptr %143, align 8, !tbaa !11
  %145 = getelementptr inbounds %struct.ADC_TypeDef, ptr %144, i32 0, i32 2
  %146 = load volatile i32, ptr %145, align 4, !tbaa !25
  %147 = load i32, ptr %9, align 4, !tbaa !9
  %148 = and i32 %146, %147
  %149 = zext i32 %148 to i64
  %150 = icmp ne i64 %149, 0
  br i1 %150, label %151, label %169

151:                                              ; preds = %141
  %152 = call i32 @HAL_GetTick()
  %153 = load i32, ptr %6, align 4, !tbaa !9
  %154 = sub i32 %152, %153
  %155 = zext i32 %154 to i64
  %156 = icmp ugt i64 %155, 5
  br i1 %156, label %157, label %168

157:                                              ; preds = %151
  %158 = load ptr, ptr %4, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %158, i32 0, i32 4
  %160 = load volatile i32, ptr %159, align 4, !tbaa !21
  %161 = zext i32 %160 to i64
  %162 = or i64 %161, 16
  %163 = trunc i64 %162 to i32
  store volatile i32 %163, ptr %159, align 4, !tbaa !21
  %164 = load ptr, ptr %4, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %164, i32 0, i32 5
  %166 = load volatile i32, ptr %165, align 8, !tbaa !22
  %167 = or i32 %166, 1
  store volatile i32 %167, ptr %165, align 8, !tbaa !22
  store i32 1, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %171

168:                                              ; preds = %151
  br label %141, !llvm.loop !26

169:                                              ; preds = %141
  br label %170

170:                                              ; preds = %169, %25
  store i32 0, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %171

171:                                              ; preds = %170, %157, %67
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %172 = load i32, ptr %3, align 4
  ret i32 %172
}

declare i32 @HAL_GetTick() #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDisableOngoing(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StopConversion(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_INJ_StopConversion(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!17, !10, i64 12}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!18 = !{!12, !10, i64 28}
!19 = !{!12, !10, i64 24}
!20 = !{!17, !10, i64 0}
!21 = !{!12, !10, i64 100}
!22 = !{!12, !10, i64 104}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = !{!17, !10, i64 8}
!26 = distinct !{!26, !24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @ADC_ConversionStop(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %3)
  %5 = load ptr, ptr %0, align 8, !tbaa !5
  %6 = tail call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %5)
  %7 = icmp ne i32 %4, 0
  %8 = icmp ne i32 %6, 0
  %or.cond = select i1 %7, i1 true, i1 %8
  br i1 %or.cond, label %9, label %.loopexit

9:                                                ; preds = %2
  %10 = load ptr, ptr %0, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %10, i64 12
  %12 = load volatile i32, ptr %11, align 4, !tbaa !14
  %13 = and i32 %12, 33554432
  %.not = icmp eq i32 %13, 0
  br i1 %.not, label %39, label %14

14:                                               ; preds = %9
  %15 = getelementptr inbounds i8, ptr %0, i64 28
  %16 = load i32, ptr %15, align 4, !tbaa !16
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %18, label %39

18:                                               ; preds = %14
  %19 = getelementptr inbounds i8, ptr %0, i64 24
  %20 = load i32, ptr %19, align 8, !tbaa !17
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %.preheader, label %39

.preheader:                                       ; preds = %18
  %22 = load volatile i32, ptr %10, align 4, !tbaa !18
  %23 = and i32 %22, 64
  %24 = icmp eq i32 %23, 0
  br i1 %24, label %.lr.ph, label %.thread

25:                                               ; preds = %.lr.ph
  %26 = load volatile i32, ptr %10, align 4, !tbaa !18
  %27 = and i32 %26, 64
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %.lr.ph.1, label %.thread, !llvm.loop !19

.lr.ph.1:                                         ; preds = %25
  %29 = load volatile i32, ptr %10, align 4, !tbaa !18
  %30 = and i32 %29, 64
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %.lr.ph.2, label %.thread, !llvm.loop !19

.lr.ph.2:                                         ; preds = %.lr.ph.1
  %32 = load volatile i32, ptr %10, align 4, !tbaa !18
  %33 = and i32 %32, 64
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %.lr.ph.3, label %.thread, !llvm.loop !19

.lr.ph.3:                                         ; preds = %.lr.ph.2
  %35 = add nuw nsw i32 %.03047, 4
  %36 = load volatile i32, ptr %10, align 4, !tbaa !18
  %37 = and i32 %36, 64
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %.lr.ph, label %.thread, !llvm.loop !19

.lr.ph:                                           ; preds = %.preheader, %.lr.ph.3
  %.03047 = phi i32 [ %35, %.lr.ph.3 ], [ 0, %.preheader ]
  %exitcond = icmp eq i32 %.03047, 842752
  br i1 %exitcond, label %.loopexit.sink.split, label %25

.thread:                                          ; preds = %25, %.lr.ph.1, %.lr.ph.2, %.lr.ph.3, %.preheader
  store volatile i32 64, ptr %10, align 4, !tbaa !18
  br label %40

39:                                               ; preds = %18, %14, %9
  %cond = icmp eq i32 %1, 2
  br i1 %cond, label %51, label %40

40:                                               ; preds = %.thread, %39
  %.03243 = phi i32 [ 1, %.thread ], [ %1, %39 ]
  %41 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef nonnull %10)
  %.not34 = icmp eq i32 %41, 0
  br i1 %.not34, label %48, label %42

42:                                               ; preds = %40
  %43 = load ptr, ptr %0, align 8, !tbaa !5
  %44 = tail call i32 @LL_ADC_IsDisableOngoing(ptr noundef %43)
  %45 = icmp eq i32 %44, 0
  br i1 %45, label %46, label %48

46:                                               ; preds = %42
  %47 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @LL_ADC_REG_StopConversion(ptr noundef %47)
  br label %48

48:                                               ; preds = %40, %46, %42
  %cond40 = icmp eq i32 %.03243, 1
  br i1 %cond40, label %60, label %._crit_edge

._crit_edge:                                      ; preds = %48
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  %49 = icmp eq i32 %.03243, 3
  %50 = select i1 %49, i32 12, i32 4
  br label %51

51:                                               ; preds = %._crit_edge, %39
  %52 = phi ptr [ %.pre, %._crit_edge ], [ %10, %39 ]
  %.03244 = phi i32 [ %50, %._crit_edge ], [ 8, %39 ]
  %53 = tail call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %52)
  %.not36 = icmp eq i32 %53, 0
  br i1 %.not36, label %60, label %54

54:                                               ; preds = %51
  %55 = load ptr, ptr %0, align 8, !tbaa !5
  %56 = tail call i32 @LL_ADC_IsDisableOngoing(ptr noundef %55)
  %57 = icmp eq i32 %56, 0
  br i1 %57, label %58, label %60

58:                                               ; preds = %54
  %59 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @LL_ADC_INJ_StopConversion(ptr noundef %59)
  br label %60

60:                                               ; preds = %54, %58, %51, %48
  %.031 = phi i32 [ 4, %48 ], [ %.03244, %51 ], [ %.03244, %58 ], [ %.03244, %54 ]
  %61 = tail call i32 @HAL_GetTick() #3
  br label %62

62:                                               ; preds = %67, %60
  %63 = load ptr, ptr %0, align 8, !tbaa !5
  %64 = getelementptr inbounds i8, ptr %63, i64 8
  %65 = load volatile i32, ptr %64, align 4, !tbaa !21
  %66 = and i32 %65, %.031
  %.not37 = icmp eq i32 %66, 0
  br i1 %.not37, label %.loopexit, label %67

67:                                               ; preds = %62
  %68 = tail call i32 @HAL_GetTick() #3
  %69 = sub i32 %68, %61
  %70 = icmp ugt i32 %69, 5
  br i1 %70, label %.loopexit.sink.split, label %62, !llvm.loop !22

.loopexit.sink.split:                             ; preds = %.lr.ph, %67
  %71 = getelementptr inbounds i8, ptr %0, i64 100
  %72 = load volatile i32, ptr %71, align 4, !tbaa !23
  %73 = or i32 %72, 16
  store volatile i32 %73, ptr %71, align 4, !tbaa !23
  %74 = getelementptr inbounds i8, ptr %0, i64 104
  %75 = load volatile i32, ptr %74, align 8, !tbaa !24
  %76 = or i32 %75, 1
  store volatile i32 %76, ptr %74, align 8, !tbaa !24
  br label %.loopexit

.loopexit:                                        ; preds = %62, %.loopexit.sink.split, %2
  %.0 = phi i32 [ 0, %2 ], [ 1, %.loopexit.sink.split ], [ 0, %62 ]
  ret i32 %.0
}

declare i32 @HAL_GetTick() local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsDisableOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StopConversion(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_INJ_StopConversion(ptr noundef) local_unnamed_addr #0

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!15, !11, i64 12}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!16 = !{!6, !11, i64 28}
!17 = !{!6, !11, i64 24}
!18 = !{!15, !11, i64 0}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = !{!15, !11, i64 8}
!22 = distinct !{!22, !20}
!23 = !{!6, !11, i64 100}
!24 = !{!6, !11, i64 104}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass