; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (fmc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FMC_SDRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FMC_Bank5_6_TypeDef = type { [2 x i32], [2 x i32], i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @FMC_SDRAM_Init(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %5, i32 0, i32 0
  %7 = load i32, ptr %6, align 4, !tbaa !9
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %54

9:                                                ; preds = %2
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %10, i32 0, i32 0
  %12 = getelementptr inbounds [2 x i32], ptr %11, i64 0, i64 0
  %13 = load volatile i32, ptr %12, align 4, !tbaa !12
  %14 = and i32 %13, -32768
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %15, i32 0, i32 1
  %17 = load i32, ptr %16, align 4, !tbaa !13
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %18, i32 0, i32 2
  %20 = load i32, ptr %19, align 4, !tbaa !14
  %21 = or i32 %17, %20
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %22, i32 0, i32 3
  %24 = load i32, ptr %23, align 4, !tbaa !15
  %25 = or i32 %21, %24
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %26, i32 0, i32 4
  %28 = load i32, ptr %27, align 4, !tbaa !16
  %29 = or i32 %25, %28
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %30, i32 0, i32 5
  %32 = load i32, ptr %31, align 4, !tbaa !17
  %33 = or i32 %29, %32
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %34, i32 0, i32 6
  %36 = load i32, ptr %35, align 4, !tbaa !18
  %37 = or i32 %33, %36
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %38, i32 0, i32 7
  %40 = load i32, ptr %39, align 4, !tbaa !19
  %41 = or i32 %37, %40
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %42, i32 0, i32 8
  %44 = load i32, ptr %43, align 4, !tbaa !20
  %45 = or i32 %41, %44
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %46, i32 0, i32 9
  %48 = load i32, ptr %47, align 4, !tbaa !21
  %49 = or i32 %45, %48
  %50 = or i32 %14, %49
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %51, i32 0, i32 0
  %53 = getelementptr inbounds [2 x i32], ptr %52, i64 0, i64 0
  store volatile i32 %50, ptr %53, align 4, !tbaa !12
  br label %110

54:                                               ; preds = %2
  %55 = load ptr, ptr %3, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %55, i32 0, i32 0
  %57 = getelementptr inbounds [2 x i32], ptr %56, i64 0, i64 0
  %58 = load volatile i32, ptr %57, align 4, !tbaa !12
  %59 = zext i32 %58 to i64
  %60 = and i64 %59, -31745
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %61, i32 0, i32 7
  %63 = load i32, ptr %62, align 4, !tbaa !19
  %64 = load ptr, ptr %4, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %64, i32 0, i32 8
  %66 = load i32, ptr %65, align 4, !tbaa !20
  %67 = or i32 %63, %66
  %68 = load ptr, ptr %4, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %68, i32 0, i32 9
  %70 = load i32, ptr %69, align 4, !tbaa !21
  %71 = or i32 %67, %70
  %72 = zext i32 %71 to i64
  %73 = or i64 %60, %72
  %74 = trunc i64 %73 to i32
  %75 = load ptr, ptr %3, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %75, i32 0, i32 0
  %77 = getelementptr inbounds [2 x i32], ptr %76, i64 0, i64 0
  store volatile i32 %74, ptr %77, align 4, !tbaa !12
  %78 = load ptr, ptr %3, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %78, i32 0, i32 0
  %80 = getelementptr inbounds [2 x i32], ptr %79, i64 0, i64 1
  %81 = load volatile i32, ptr %80, align 4, !tbaa !12
  %82 = and i32 %81, -32768
  %83 = load ptr, ptr %4, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %83, i32 0, i32 1
  %85 = load i32, ptr %84, align 4, !tbaa !13
  %86 = load ptr, ptr %4, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %86, i32 0, i32 2
  %88 = load i32, ptr %87, align 4, !tbaa !14
  %89 = or i32 %85, %88
  %90 = load ptr, ptr %4, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %90, i32 0, i32 3
  %92 = load i32, ptr %91, align 4, !tbaa !15
  %93 = or i32 %89, %92
  %94 = load ptr, ptr %4, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %94, i32 0, i32 4
  %96 = load i32, ptr %95, align 4, !tbaa !16
  %97 = or i32 %93, %96
  %98 = load ptr, ptr %4, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %98, i32 0, i32 5
  %100 = load i32, ptr %99, align 4, !tbaa !17
  %101 = or i32 %97, %100
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.FMC_SDRAM_InitTypeDef, ptr %102, i32 0, i32 6
  %104 = load i32, ptr %103, align 4, !tbaa !18
  %105 = or i32 %101, %104
  %106 = or i32 %82, %105
  %107 = load ptr, ptr %3, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.FMC_Bank5_6_TypeDef, ptr %107, i32 0, i32 0
  %109 = getelementptr inbounds [2 x i32], ptr %108, i64 0, i64 1
  store volatile i32 %106, ptr %109, align 4, !tbaa !12
  br label %110

110:                                              ; preds = %54, %9
  ret i32 0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!11 = !{!"int", !7, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!10, !11, i64 4}
!14 = !{!10, !11, i64 8}
!15 = !{!10, !11, i64 12}
!16 = !{!10, !11, i64 16}
!17 = !{!10, !11, i64 20}
!18 = !{!10, !11, i64 24}
!19 = !{!10, !11, i64 28}
!20 = !{!10, !11, i64 32}
!21 = !{!10, !11, i64 36}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable
define dso_local noundef i32 @FMC_SDRAM_Init(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = load i32, ptr %1, align 4, !tbaa !5
  %4 = icmp eq i32 %3, 0
  %5 = load volatile i32, ptr %0, align 4, !tbaa !10
  br i1 %4, label %6, label %13

6:                                                ; preds = %2
  %7 = and i32 %5, -32768
  %8 = getelementptr inbounds i8, ptr %1, i64 4
  %9 = load <8 x i32>, ptr %8, align 4, !tbaa !10
  %10 = getelementptr inbounds i8, ptr %1, i64 36
  %11 = load i32, ptr %10, align 4, !tbaa !11
  %12 = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %9)
  %op.rdx = or i32 %12, %11
  %op.rdx25 = or i32 %op.rdx, %7
  store volatile i32 %op.rdx25, ptr %0, align 4, !tbaa !10
  br label %34

13:                                               ; preds = %2
  %14 = and i32 %5, -31745
  %15 = getelementptr inbounds i8, ptr %1, i64 28
  %16 = load i32, ptr %15, align 4, !tbaa !12
  %17 = getelementptr inbounds i8, ptr %1, i64 32
  %18 = load i32, ptr %17, align 4, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %1, i64 36
  %20 = load i32, ptr %19, align 4, !tbaa !11
  %21 = or i32 %14, %16
  %22 = or i32 %21, %18
  %23 = or i32 %22, %20
  store volatile i32 %23, ptr %0, align 4, !tbaa !10
  %24 = getelementptr inbounds i8, ptr %0, i64 4
  %25 = load volatile i32, ptr %24, align 4, !tbaa !10
  %26 = and i32 %25, -32768
  %27 = getelementptr inbounds i8, ptr %1, i64 4
  %28 = load <4 x i32>, ptr %27, align 4, !tbaa !10
  %29 = getelementptr inbounds i8, ptr %1, i64 20
  %30 = load i32, ptr %29, align 4, !tbaa !14
  %31 = getelementptr inbounds i8, ptr %1, i64 24
  %32 = load i32, ptr %31, align 4, !tbaa !15
  %33 = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %28)
  %op.rdx26 = or i32 %33, %30
  %op.rdx27 = or i32 %32, %26
  %op.rdx28 = or i32 %op.rdx26, %op.rdx27
  store volatile i32 %op.rdx28, ptr %24, align 4, !tbaa !10
  br label %34

34:                                               ; preds = %13, %6
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>) #1

attributes #0 = { nofree norecurse nounwind memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!7, !7, i64 0}
!11 = !{!6, !7, i64 36}
!12 = !{!6, !7, i64 28}
!13 = !{!6, !7, i64 32}
!14 = !{!6, !7, i64 20}
!15 = !{!6, !7, i64 24}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass