; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

declare void @TIM_DMAError(ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIMEx_ConfigCommutEvent_DMA(ptr noundef %0, i32 noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  br label %8

8:                                                ; preds = %3
  %9 = load ptr, ptr %5, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %9, i32 0, i32 4
  %11 = load i32, ptr %10, align 8, !tbaa !11
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 2, ptr %4, align 4
  br label %108

14:                                               ; preds = %8
  %15 = load ptr, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %15, i32 0, i32 4
  store i32 1, ptr %16, align 8, !tbaa !11
  br label %17

17:                                               ; preds = %14
  br label %18

18:                                               ; preds = %17
  %19 = load i32, ptr %6, align 4, !tbaa !9
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %33, label %21

21:                                               ; preds = %18
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = zext i32 %22 to i64
  %24 = icmp eq i64 %23, 16
  br i1 %24, label %33, label %25

25:                                               ; preds = %21
  %26 = load i32, ptr %6, align 4, !tbaa !9
  %27 = zext i32 %26 to i64
  %28 = icmp eq i64 %27, 32
  br i1 %28, label %33, label %29

29:                                               ; preds = %25
  %30 = load i32, ptr %6, align 4, !tbaa !9
  %31 = zext i32 %30 to i64
  %32 = icmp eq i64 %31, 48
  br i1 %32, label %33, label %49

33:                                               ; preds = %29, %25, %21, %18
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !14
  %37 = getelementptr inbounds %struct.TIM_TypeDef, ptr %36, i32 0, i32 2
  %38 = load volatile i32, ptr %37, align 4, !tbaa !15
  %39 = zext i32 %38 to i64
  %40 = and i64 %39, -3145841
  %41 = trunc i64 %40 to i32
  store volatile i32 %41, ptr %37, align 4, !tbaa !15
  %42 = load i32, ptr %6, align 4, !tbaa !9
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %43, i32 0, i32 0
  %45 = load ptr, ptr %44, align 8, !tbaa !14
  %46 = getelementptr inbounds %struct.TIM_TypeDef, ptr %45, i32 0, i32 2
  %47 = load volatile i32, ptr %46, align 4, !tbaa !15
  %48 = or i32 %47, %42
  store volatile i32 %48, ptr %46, align 4, !tbaa !15
  br label %49

49:                                               ; preds = %33, %29
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %50, i32 0, i32 0
  %52 = load ptr, ptr %51, align 8, !tbaa !14
  %53 = getelementptr inbounds %struct.TIM_TypeDef, ptr %52, i32 0, i32 1
  %54 = load volatile i32, ptr %53, align 4, !tbaa !17
  %55 = zext i32 %54 to i64
  %56 = or i64 %55, 1
  %57 = trunc i64 %56 to i32
  store volatile i32 %57, ptr %53, align 4, !tbaa !17
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !14
  %61 = getelementptr inbounds %struct.TIM_TypeDef, ptr %60, i32 0, i32 1
  %62 = load volatile i32, ptr %61, align 4, !tbaa !17
  %63 = zext i32 %62 to i64
  %64 = and i64 %63, -5
  %65 = trunc i64 %64 to i32
  store volatile i32 %65, ptr %61, align 4, !tbaa !17
  %66 = load i32, ptr %7, align 4, !tbaa !9
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !14
  %70 = getelementptr inbounds %struct.TIM_TypeDef, ptr %69, i32 0, i32 1
  %71 = load volatile i32, ptr %70, align 4, !tbaa !17
  %72 = or i32 %71, %66
  store volatile i32 %72, ptr %70, align 4, !tbaa !17
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %73, i32 0, i32 3
  %75 = getelementptr inbounds [7 x ptr], ptr %74, i64 0, i64 5
  %76 = load ptr, ptr %75, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %76, i32 0, i32 5
  store ptr @TIMEx_DMACommutationCplt, ptr %77, align 8, !tbaa !18
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %78, i32 0, i32 3
  %80 = getelementptr inbounds [7 x ptr], ptr %79, i64 0, i64 5
  %81 = load ptr, ptr %80, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %81, i32 0, i32 6
  store ptr @TIMEx_DMACommutationHalfCplt, ptr %82, align 8, !tbaa !21
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %83, i32 0, i32 3
  %85 = getelementptr inbounds [7 x ptr], ptr %84, i64 0, i64 5
  %86 = load ptr, ptr %85, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %86, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %87, align 8, !tbaa !22
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %88, i32 0, i32 0
  %90 = load ptr, ptr %89, align 8, !tbaa !14
  %91 = getelementptr inbounds %struct.TIM_TypeDef, ptr %90, i32 0, i32 3
  %92 = load volatile i32, ptr %91, align 4, !tbaa !23
  %93 = zext i32 %92 to i64
  %94 = and i64 %93, -33
  %95 = trunc i64 %94 to i32
  store volatile i32 %95, ptr %91, align 4, !tbaa !23
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %96, i32 0, i32 0
  %98 = load ptr, ptr %97, align 8, !tbaa !14
  %99 = getelementptr inbounds %struct.TIM_TypeDef, ptr %98, i32 0, i32 3
  %100 = load volatile i32, ptr %99, align 4, !tbaa !23
  %101 = zext i32 %100 to i64
  %102 = or i64 %101, 8192
  %103 = trunc i64 %102 to i32
  store volatile i32 %103, ptr %99, align 4, !tbaa !23
  br label %104

104:                                              ; preds = %49
  %105 = load ptr, ptr %5, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %105, i32 0, i32 4
  store i32 0, ptr %106, align 8, !tbaa !11
  br label %107

107:                                              ; preds = %104
  store i32 0, ptr %4, align 4
  br label %108

108:                                              ; preds = %107, %13
  %109 = load i32, ptr %4, align 4
  ret i32 %109
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIMEx_DMACommutationCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIMEx_DMACommutationHalfCplt(ptr noundef) #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !6, i64 0}
!15 = !{!16, !10, i64 8}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!17 = !{!16, !10, i64 4}
!18 = !{!19, !6, i64 72}
!19 = !{!"__DMA_HandleTypeDef", !6, i64 0, !20, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!20 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!21 = !{!19, !6, i64 80}
!22 = !{!19, !6, i64 104}
!23 = !{!16, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @TIM_DMAError(ptr noundef) #0

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIMEx_ConfigCommutEvent_DMA(ptr nocapture noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #1 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %35, label %7

7:                                                ; preds = %3
  %8 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 28)
  %switch = icmp ult i32 %8, 4
  %.pre = load ptr, ptr %0, align 8, !tbaa !12
  br i1 %switch, label %9, label %15

9:                                                ; preds = %7
  %10 = getelementptr inbounds i8, ptr %.pre, i64 8
  %11 = load volatile i32, ptr %10, align 4, !tbaa !13
  %12 = and i32 %11, -3145841
  store volatile i32 %12, ptr %10, align 4, !tbaa !13
  %13 = load volatile i32, ptr %10, align 4, !tbaa !13
  %14 = or i32 %13, %1
  store volatile i32 %14, ptr %10, align 4, !tbaa !13
  br label %15

15:                                               ; preds = %7, %9
  %16 = getelementptr inbounds i8, ptr %.pre, i64 4
  %17 = load volatile i32, ptr %16, align 4, !tbaa !15
  %18 = or i32 %17, 1
  store volatile i32 %18, ptr %16, align 4, !tbaa !15
  %19 = load volatile i32, ptr %16, align 4, !tbaa !15
  %20 = and i32 %19, -5
  store volatile i32 %20, ptr %16, align 4, !tbaa !15
  %21 = load volatile i32, ptr %16, align 4, !tbaa !15
  %22 = or i32 %21, %2
  store volatile i32 %22, ptr %16, align 4, !tbaa !15
  %23 = getelementptr inbounds i8, ptr %0, i64 80
  %24 = load ptr, ptr %23, align 8, !tbaa !16
  %25 = getelementptr inbounds i8, ptr %24, i64 72
  store ptr @TIMEx_DMACommutationCplt, ptr %25, align 8, !tbaa !17
  %26 = load ptr, ptr %23, align 8, !tbaa !16
  %27 = getelementptr inbounds i8, ptr %26, i64 80
  store ptr @TIMEx_DMACommutationHalfCplt, ptr %27, align 8, !tbaa !20
  %28 = load ptr, ptr %23, align 8, !tbaa !16
  %29 = getelementptr inbounds i8, ptr %28, i64 104
  store ptr @TIM_DMAError, ptr %29, align 8, !tbaa !21
  %30 = getelementptr inbounds i8, ptr %.pre, i64 12
  %31 = load volatile i32, ptr %30, align 4, !tbaa !22
  %32 = and i32 %31, -33
  store volatile i32 %32, ptr %30, align 4, !tbaa !22
  %33 = load volatile i32, ptr %30, align 4, !tbaa !22
  %34 = or i32 %33, 8192
  store volatile i32 %34, ptr %30, align 4, !tbaa !22
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %35

35:                                               ; preds = %3, %15
  %.0 = phi i32 [ 0, %15 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIMEx_DMACommutationCplt(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @TIMEx_DMACommutationHalfCplt(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #3

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!14, !11, i64 8}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!15 = !{!14, !11, i64 4}
!16 = !{!7, !7, i64 0}
!17 = !{!18, !7, i64 72}
!18 = !{!"__DMA_HandleTypeDef", !7, i64 0, !19, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!20 = !{!18, !7, i64 80}
!21 = !{!18, !7, i64 104}
!22 = !{!14, !11, i64 12}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass