; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Write_SpareArea_16b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #4
  %19 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %19, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %20, ptr %17, align 8, !tbaa !5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load volatile i32, ptr %22, align 8, !tbaa !11
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %26

25:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %303

26:                                               ; preds = %4
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %27, i32 0, i32 3
  %29 = load volatile i32, ptr %28, align 8, !tbaa !11
  %30 = icmp eq i32 %29, 1
  br i1 %30, label %31, label %300

31:                                               ; preds = %26
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %33, i32 0, i32 2
  %35 = load i32, ptr %34, align 4, !tbaa !14
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %303

38:                                               ; preds = %32
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %39, i32 0, i32 2
  store i32 1, ptr %40, align 4, !tbaa !14
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %44, i32 0, i32 3
  store volatile i32 2, ptr %45, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %46 = load ptr, ptr %7, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %46, i32 0, i32 0
  %48 = load i16, ptr %47, align 2, !tbaa !15
  %49 = zext i16 %48 to i32
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %50, i32 0, i32 2
  %52 = load i16, ptr %51, align 2, !tbaa !18
  %53 = zext i16 %52 to i32
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %54, i32 0, i32 1
  %56 = load i16, ptr %55, align 2, !tbaa !19
  %57 = zext i16 %56 to i32
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %58, i32 0, i32 4
  %60 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %59, i32 0, i32 5
  %61 = load i32, ptr %60, align 4, !tbaa !20
  %62 = mul i32 %57, %61
  %63 = add i32 %53, %62
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %64, i32 0, i32 4
  %66 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %65, i32 0, i32 2
  %67 = load i32, ptr %66, align 4, !tbaa !21
  %68 = mul i32 %63, %67
  %69 = add i32 %49, %68
  store i32 %69, ptr %14, align 4, !tbaa !9
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %70, i32 0, i32 4
  %72 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 4, !tbaa !22
  %74 = mul i32 %73, 2
  store i32 %74, ptr %15, align 4, !tbaa !9
  br label %75

75:                                               ; preds = %285, %43
  %76 = load i32, ptr %16, align 4, !tbaa !9
  %77 = icmp ne i32 %76, 0
  br i1 %77, label %78, label %90

78:                                               ; preds = %75
  %79 = load i32, ptr %14, align 4, !tbaa !9
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %80, i32 0, i32 4
  %82 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %81, i32 0, i32 2
  %83 = load i32, ptr %82, align 4, !tbaa !21
  %84 = load ptr, ptr %6, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %84, i32 0, i32 4
  %86 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %85, i32 0, i32 3
  %87 = load i32, ptr %86, align 4, !tbaa !23
  %88 = mul i32 %83, %87
  %89 = icmp ult i32 %79, %88
  br label %90

90:                                               ; preds = %78, %75
  %91 = phi i1 [ false, %75 ], [ %89, %78 ]
  br i1 %91, label %92, label %292

92:                                               ; preds = %90
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %93, i32 0, i32 4
  %95 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %94, i32 0, i32 0
  %96 = load i32, ptr %95, align 4, !tbaa !22
  %97 = icmp ule i32 %96, 512
  br i1 %97, label %98, label %161

98:                                               ; preds = %92
  %99 = load i32, ptr %12, align 4, !tbaa !9
  %100 = or i32 %99, 65536
  %101 = zext i32 %100 to i64
  %102 = inttoptr i64 %101 to ptr
  store volatile i8 80, ptr %102, align 1, !tbaa !24
  call void @__DSB()
  %103 = load i32, ptr %12, align 4, !tbaa !9
  %104 = or i32 %103, 65536
  %105 = zext i32 %104 to i64
  %106 = inttoptr i64 %105 to ptr
  store volatile i8 -128, ptr %106, align 1, !tbaa !24
  call void @__DSB()
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %107, i32 0, i32 4
  %109 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %108, i32 0, i32 2
  %110 = load i32, ptr %109, align 4, !tbaa !21
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %111, i32 0, i32 4
  %113 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %112, i32 0, i32 3
  %114 = load i32, ptr %113, align 4, !tbaa !23
  %115 = mul i32 %110, %114
  %116 = icmp ule i32 %115, 65535
  br i1 %116, label %117, label %135

117:                                              ; preds = %98
  %118 = load i32, ptr %12, align 4, !tbaa !9
  %119 = or i32 %118, 131072
  %120 = zext i32 %119 to i64
  %121 = inttoptr i64 %120 to ptr
  store volatile i8 0, ptr %121, align 1, !tbaa !24
  call void @__DSB()
  %122 = load i32, ptr %14, align 4, !tbaa !9
  %123 = trunc i32 %122 to i8
  %124 = load i32, ptr %12, align 4, !tbaa !9
  %125 = or i32 %124, 131072
  %126 = zext i32 %125 to i64
  %127 = inttoptr i64 %126 to ptr
  store volatile i8 %123, ptr %127, align 1, !tbaa !24
  call void @__DSB()
  %128 = load i32, ptr %14, align 4, !tbaa !9
  %129 = lshr i32 %128, 8
  %130 = trunc i32 %129 to i8
  %131 = load i32, ptr %12, align 4, !tbaa !9
  %132 = or i32 %131, 131072
  %133 = zext i32 %132 to i64
  %134 = inttoptr i64 %133 to ptr
  store volatile i8 %130, ptr %134, align 1, !tbaa !24
  call void @__DSB()
  br label %160

135:                                              ; preds = %98
  %136 = load i32, ptr %12, align 4, !tbaa !9
  %137 = or i32 %136, 131072
  %138 = zext i32 %137 to i64
  %139 = inttoptr i64 %138 to ptr
  store volatile i8 0, ptr %139, align 1, !tbaa !24
  call void @__DSB()
  %140 = load i32, ptr %14, align 4, !tbaa !9
  %141 = trunc i32 %140 to i8
  %142 = load i32, ptr %12, align 4, !tbaa !9
  %143 = or i32 %142, 131072
  %144 = zext i32 %143 to i64
  %145 = inttoptr i64 %144 to ptr
  store volatile i8 %141, ptr %145, align 1, !tbaa !24
  call void @__DSB()
  %146 = load i32, ptr %14, align 4, !tbaa !9
  %147 = lshr i32 %146, 8
  %148 = trunc i32 %147 to i8
  %149 = load i32, ptr %12, align 4, !tbaa !9
  %150 = or i32 %149, 131072
  %151 = zext i32 %150 to i64
  %152 = inttoptr i64 %151 to ptr
  store volatile i8 %148, ptr %152, align 1, !tbaa !24
  call void @__DSB()
  %153 = load i32, ptr %14, align 4, !tbaa !9
  %154 = lshr i32 %153, 16
  %155 = trunc i32 %154 to i8
  %156 = load i32, ptr %12, align 4, !tbaa !9
  %157 = or i32 %156, 131072
  %158 = zext i32 %157 to i64
  %159 = inttoptr i64 %158 to ptr
  store volatile i8 %155, ptr %159, align 1, !tbaa !24
  call void @__DSB()
  br label %160

160:                                              ; preds = %135, %117
  br label %242

161:                                              ; preds = %92
  %162 = load i32, ptr %12, align 4, !tbaa !9
  %163 = or i32 %162, 65536
  %164 = zext i32 %163 to i64
  %165 = inttoptr i64 %164 to ptr
  store volatile i8 0, ptr %165, align 1, !tbaa !24
  call void @__DSB()
  %166 = load i32, ptr %12, align 4, !tbaa !9
  %167 = or i32 %166, 65536
  %168 = zext i32 %167 to i64
  %169 = inttoptr i64 %168 to ptr
  store volatile i8 -128, ptr %169, align 1, !tbaa !24
  call void @__DSB()
  %170 = load ptr, ptr %6, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %170, i32 0, i32 4
  %172 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %171, i32 0, i32 2
  %173 = load i32, ptr %172, align 4, !tbaa !21
  %174 = load ptr, ptr %6, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %174, i32 0, i32 4
  %176 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %175, i32 0, i32 3
  %177 = load i32, ptr %176, align 4, !tbaa !23
  %178 = mul i32 %173, %177
  %179 = icmp ule i32 %178, 65535
  br i1 %179, label %180, label %207

180:                                              ; preds = %161
  %181 = load i32, ptr %15, align 4, !tbaa !9
  %182 = trunc i32 %181 to i8
  %183 = load i32, ptr %12, align 4, !tbaa !9
  %184 = or i32 %183, 131072
  %185 = zext i32 %184 to i64
  %186 = inttoptr i64 %185 to ptr
  store volatile i8 %182, ptr %186, align 1, !tbaa !24
  call void @__DSB()
  %187 = load i32, ptr %15, align 4, !tbaa !9
  %188 = lshr i32 %187, 8
  %189 = trunc i32 %188 to i8
  %190 = load i32, ptr %12, align 4, !tbaa !9
  %191 = or i32 %190, 131072
  %192 = zext i32 %191 to i64
  %193 = inttoptr i64 %192 to ptr
  store volatile i8 %189, ptr %193, align 1, !tbaa !24
  call void @__DSB()
  %194 = load i32, ptr %14, align 4, !tbaa !9
  %195 = trunc i32 %194 to i8
  %196 = load i32, ptr %12, align 4, !tbaa !9
  %197 = or i32 %196, 131072
  %198 = zext i32 %197 to i64
  %199 = inttoptr i64 %198 to ptr
  store volatile i8 %195, ptr %199, align 1, !tbaa !24
  call void @__DSB()
  %200 = load i32, ptr %14, align 4, !tbaa !9
  %201 = lshr i32 %200, 8
  %202 = trunc i32 %201 to i8
  %203 = load i32, ptr %12, align 4, !tbaa !9
  %204 = or i32 %203, 131072
  %205 = zext i32 %204 to i64
  %206 = inttoptr i64 %205 to ptr
  store volatile i8 %202, ptr %206, align 1, !tbaa !24
  call void @__DSB()
  br label %241

207:                                              ; preds = %161
  %208 = load i32, ptr %15, align 4, !tbaa !9
  %209 = trunc i32 %208 to i8
  %210 = load i32, ptr %12, align 4, !tbaa !9
  %211 = or i32 %210, 131072
  %212 = zext i32 %211 to i64
  %213 = inttoptr i64 %212 to ptr
  store volatile i8 %209, ptr %213, align 1, !tbaa !24
  call void @__DSB()
  %214 = load i32, ptr %15, align 4, !tbaa !9
  %215 = lshr i32 %214, 8
  %216 = trunc i32 %215 to i8
  %217 = load i32, ptr %12, align 4, !tbaa !9
  %218 = or i32 %217, 131072
  %219 = zext i32 %218 to i64
  %220 = inttoptr i64 %219 to ptr
  store volatile i8 %216, ptr %220, align 1, !tbaa !24
  call void @__DSB()
  %221 = load i32, ptr %14, align 4, !tbaa !9
  %222 = trunc i32 %221 to i8
  %223 = load i32, ptr %12, align 4, !tbaa !9
  %224 = or i32 %223, 131072
  %225 = zext i32 %224 to i64
  %226 = inttoptr i64 %225 to ptr
  store volatile i8 %222, ptr %226, align 1, !tbaa !24
  call void @__DSB()
  %227 = load i32, ptr %14, align 4, !tbaa !9
  %228 = lshr i32 %227, 8
  %229 = trunc i32 %228 to i8
  %230 = load i32, ptr %12, align 4, !tbaa !9
  %231 = or i32 %230, 131072
  %232 = zext i32 %231 to i64
  %233 = inttoptr i64 %232 to ptr
  store volatile i8 %229, ptr %233, align 1, !tbaa !24
  call void @__DSB()
  %234 = load i32, ptr %14, align 4, !tbaa !9
  %235 = lshr i32 %234, 16
  %236 = trunc i32 %235 to i8
  %237 = load i32, ptr %12, align 4, !tbaa !9
  %238 = or i32 %237, 131072
  %239 = zext i32 %238 to i64
  %240 = inttoptr i64 %239 to ptr
  store volatile i8 %236, ptr %240, align 1, !tbaa !24
  call void @__DSB()
  br label %241

241:                                              ; preds = %207, %180
  br label %242

242:                                              ; preds = %241, %160
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %243

243:                                              ; preds = %258, %242
  %244 = load i32, ptr %10, align 4, !tbaa !9
  %245 = load ptr, ptr %6, align 8, !tbaa !5
  %246 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %245, i32 0, i32 4
  %247 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %246, i32 0, i32 1
  %248 = load i32, ptr %247, align 4, !tbaa !25
  %249 = icmp ult i32 %244, %248
  br i1 %249, label %250, label %261

250:                                              ; preds = %243
  %251 = load ptr, ptr %17, align 8, !tbaa !5
  %252 = load i16, ptr %251, align 2, !tbaa !26
  %253 = load i32, ptr %12, align 4, !tbaa !9
  %254 = zext i32 %253 to i64
  %255 = inttoptr i64 %254 to ptr
  store volatile i16 %252, ptr %255, align 2, !tbaa !26
  %256 = load ptr, ptr %17, align 8, !tbaa !5
  %257 = getelementptr inbounds i16, ptr %256, i32 1
  store ptr %257, ptr %17, align 8, !tbaa !5
  call void @__DSB()
  br label %258

258:                                              ; preds = %250
  %259 = load i32, ptr %10, align 4, !tbaa !9
  %260 = add i32 %259, 1
  store i32 %260, ptr %10, align 4, !tbaa !9
  br label %243, !llvm.loop !27

261:                                              ; preds = %243
  %262 = load i32, ptr %12, align 4, !tbaa !9
  %263 = or i32 %262, 65536
  %264 = zext i32 %263 to i64
  %265 = inttoptr i64 %264 to ptr
  store volatile i8 16, ptr %265, align 1, !tbaa !24
  call void @__DSB()
  %266 = call i32 @HAL_GetTick()
  store i32 %266, ptr %11, align 4, !tbaa !9
  br label %267

267:                                              ; preds = %284, %261
  %268 = load ptr, ptr %6, align 8, !tbaa !5
  %269 = call i32 @HAL_NAND_Read_Status(ptr noundef %268)
  %270 = icmp ne i32 %269, 64
  br i1 %270, label %271, label %285

271:                                              ; preds = %267
  %272 = call i32 @HAL_GetTick()
  %273 = load i32, ptr %11, align 4, !tbaa !9
  %274 = sub i32 %272, %273
  %275 = icmp ugt i32 %274, 16777216
  br i1 %275, label %276, label %284

276:                                              ; preds = %271
  %277 = load ptr, ptr %6, align 8, !tbaa !5
  %278 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %277, i32 0, i32 3
  store volatile i32 3, ptr %278, align 8, !tbaa !11
  br label %279

279:                                              ; preds = %276
  %280 = load ptr, ptr %6, align 8, !tbaa !5
  %281 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %280, i32 0, i32 2
  store i32 0, ptr %281, align 4, !tbaa !14
  br label %282

282:                                              ; preds = %279
  br label %283

283:                                              ; preds = %282
  store i32 3, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %303

284:                                              ; preds = %271
  br label %267, !llvm.loop !29

285:                                              ; preds = %267
  %286 = load i32, ptr %13, align 4, !tbaa !9
  %287 = add i32 %286, 1
  store i32 %287, ptr %13, align 4, !tbaa !9
  %288 = load i32, ptr %16, align 4, !tbaa !9
  %289 = add i32 %288, -1
  store i32 %289, ptr %16, align 4, !tbaa !9
  %290 = load i32, ptr %14, align 4, !tbaa !9
  %291 = add i32 %290, 1
  store i32 %291, ptr %14, align 4, !tbaa !9
  br label %75, !llvm.loop !30

292:                                              ; preds = %90
  %293 = load ptr, ptr %6, align 8, !tbaa !5
  %294 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %293, i32 0, i32 3
  store volatile i32 1, ptr %294, align 8, !tbaa !11
  br label %295

295:                                              ; preds = %292
  %296 = load ptr, ptr %6, align 8, !tbaa !5
  %297 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %296, i32 0, i32 2
  store i32 0, ptr %297, align 4, !tbaa !14
  br label %298

298:                                              ; preds = %295
  br label %299

299:                                              ; preds = %298
  br label %301

300:                                              ; preds = %26
  store i32 1, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %303

301:                                              ; preds = %299
  br label %302

302:                                              ; preds = %301
  store i32 0, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %303

303:                                              ; preds = %302, %300, %283, %37, %25
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %304 = load i32, ptr %5, align 4
  ret i32 %304
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 44}
!23 = !{!12, !10, i64 56}
!24 = !{!7, !7, i64 0}
!25 = !{!12, !10, i64 48}
!26 = !{!17, !17, i64 0}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = distinct !{!29, !28}
!30 = distinct !{!30, !28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Write_SpareArea_16b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %83, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %83

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %83, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not80 = icmp eq i32 %3, 0
  br i1 %.not80, label %.sink.split89, label %.lr.ph85

.lr.ph85:                                         ; preds = %15
  %18 = load i32, ptr %16, align 4, !tbaa !13
  %19 = shl i32 %18, 1
  %20 = getelementptr inbounds i8, ptr %0, i64 64
  %21 = load i32, ptr %20, align 4, !tbaa !14
  %22 = getelementptr inbounds i8, ptr %1, i64 2
  %23 = load i16, ptr %22, align 2, !tbaa !15
  %24 = zext i16 %23 to i32
  %25 = mul i32 %21, %24
  %26 = getelementptr inbounds i8, ptr %1, i64 4
  %27 = load i16, ptr %26, align 2, !tbaa !18
  %28 = zext i16 %27 to i32
  %29 = add i32 %25, %28
  %30 = load i32, ptr %17, align 4, !tbaa !19
  %31 = mul i32 %29, %30
  %32 = load i16, ptr %1, align 2, !tbaa !20
  %33 = zext i16 %32 to i32
  %34 = add i32 %31, %33
  %35 = getelementptr inbounds i8, ptr %0, i64 56
  %36 = trunc i32 %19 to i8
  %37 = lshr i32 %19, 8
  %38 = trunc i32 %37 to i8
  %39 = getelementptr inbounds i8, ptr %0, i64 48
  br label %40

40:                                               ; preds = %.lr.ph85, %80
  %.083 = phi ptr [ %2, %.lr.ph85 ], [ %.1.lcssa, %80 ]
  %.07282 = phi i32 [ %3, %.lr.ph85 ], [ %81, %80 ]
  %.07481 = phi i32 [ %34, %.lr.ph85 ], [ %82, %80 ]
  %41 = load i32, ptr %17, align 4, !tbaa !19
  %42 = load i32, ptr %35, align 4, !tbaa !21
  %43 = mul i32 %42, %41
  %44 = icmp ult i32 %.07481, %43
  br i1 %44, label %45, label %.sink.split89

45:                                               ; preds = %40
  %46 = load i32, ptr %16, align 4, !tbaa !13
  %47 = icmp ult i32 %46, 513
  br i1 %47, label %48, label %56

48:                                               ; preds = %45
  store volatile i8 80, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  store volatile i8 -128, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %49 = load i32, ptr %17, align 4, !tbaa !19
  %50 = load i32, ptr %35, align 4, !tbaa !21
  %51 = mul i32 %50, %49
  %52 = icmp ult i32 %51, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %53 = trunc i32 %.07481 to i8
  store volatile i8 %53, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %54 = lshr i32 %.07481, 8
  %55 = trunc i32 %54 to i8
  store volatile i8 %55, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %52, label %66, label %.sink.split

56:                                               ; preds = %45
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  store volatile i8 -128, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %57 = load i32, ptr %17, align 4, !tbaa !19
  %58 = load i32, ptr %35, align 4, !tbaa !21
  %59 = mul i32 %58, %57
  %60 = icmp ult i32 %59, 65536
  store volatile i8 %36, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  store volatile i8 %38, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %61 = trunc i32 %.07481 to i8
  store volatile i8 %61, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %62 = lshr i32 %.07481, 8
  %63 = trunc i32 %62 to i8
  store volatile i8 %63, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %60, label %66, label %.sink.split

.sink.split:                                      ; preds = %56, %48
  %64 = lshr i32 %.07481, 16
  %65 = trunc i32 %64 to i8
  store volatile i8 %65, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br label %66

66:                                               ; preds = %.sink.split, %56, %48
  %67 = load i32, ptr %39, align 4, !tbaa !23
  %.not87 = icmp eq i32 %67, 0
  br i1 %.not87, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %66, %.lr.ph
  %.179 = phi ptr [ %69, %.lr.ph ], [ %.083, %66 ]
  %.07678 = phi i32 [ %70, %.lr.ph ], [ 0, %66 ]
  %68 = load i16, ptr %.179, align 2, !tbaa !24
  store volatile i16 %68, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !24
  %69 = getelementptr inbounds i8, ptr %.179, i64 2
  tail call void @__DSB()
  %70 = add nuw i32 %.07678, 1
  %71 = load i32, ptr %39, align 4, !tbaa !23
  %72 = icmp ult i32 %70, %71
  br i1 %72, label %.lr.ph, label %._crit_edge, !llvm.loop !25

._crit_edge:                                      ; preds = %.lr.ph, %66
  %.1.lcssa = phi ptr [ %.083, %66 ], [ %69, %.lr.ph ]
  store volatile i8 16, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %73 = tail call i32 @HAL_GetTick() #3
  br label %74

74:                                               ; preds = %76, %._crit_edge
  %75 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not77 = icmp eq i32 %75, 64
  br i1 %.not77, label %80, label %76

76:                                               ; preds = %74
  %77 = tail call i32 @HAL_GetTick() #3
  %78 = sub i32 %77, %73
  %79 = icmp ugt i32 %78, 16777216
  br i1 %79, label %.sink.split89, label %74, !llvm.loop !27

80:                                               ; preds = %74
  %81 = add i32 %.07282, -1
  %82 = add i32 %.07481, 1
  %.not = icmp eq i32 %81, 0
  br i1 %.not, label %.sink.split89, label %40, !llvm.loop !28

.sink.split89:                                    ; preds = %80, %40, %76, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %76 ], [ 1, %40 ], [ 1, %80 ]
  %.073.ph = phi i32 [ 0, %15 ], [ 3, %76 ], [ 0, %40 ], [ 0, %80 ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %83

83:                                               ; preds = %.sink.split89, %8, %11, %4
  %.073 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.073.ph, %.sink.split89 ]
  ret i32 %.073
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 44}
!14 = !{!6, !11, i64 64}
!15 = !{!16, !17, i64 2}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !8, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!6, !11, i64 52}
!20 = !{!16, !17, i64 0}
!21 = !{!6, !11, i64 56}
!22 = !{!8, !8, i64 0}
!23 = !{!6, !11, i64 48}
!24 = !{!17, !17, i64 0}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = distinct !{!27, !26}
!28 = distinct !{!28, !26}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass