; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @ADC_Enable(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_GetTrigAuto(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_INJ_StartConversion(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_InjectedStart_IT(ptr noundef %0) #3 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !9
  %11 = icmp eq ptr %10, inttoptr (i64 1073881088 to ptr)
  br i1 %11, label %17, label %12

12:                                               ; preds = %1
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %13, i32 0, i32 0
  %15 = load ptr, ptr %14, align 8, !tbaa !9
  %16 = icmp eq ptr %15, inttoptr (i64 1073881344 to ptr)
  br label %17

17:                                               ; preds = %12, %1
  %18 = phi i1 [ true, %1 ], [ %16, %12 ]
  %19 = zext i1 %18 to i64
  %20 = select i1 %18, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %21 = call i32 @LL_ADC_GetMultimode(ptr noundef %20)
  store i32 %21, ptr %6, align 4, !tbaa !15
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !9
  %25 = call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %24)
  %26 = zext i32 %25 to i64
  %27 = icmp ne i64 %26, 0
  br i1 %27, label %28, label %29

28:                                               ; preds = %17
  store i32 2, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %247

29:                                               ; preds = %17
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 0
  %32 = load ptr, ptr %31, align 8, !tbaa !9
  %33 = getelementptr inbounds %struct.ADC_TypeDef, ptr %32, i32 0, i32 3
  %34 = load volatile i32, ptr %33, align 4, !tbaa !16
  %35 = zext i32 %34 to i64
  %36 = and i64 %35, 2147483648
  %37 = trunc i64 %36 to i32
  store i32 %37, ptr %5, align 4, !tbaa !15
  %38 = load ptr, ptr %3, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %38, i32 0, i32 0
  %40 = load ptr, ptr %39, align 8, !tbaa !9
  %41 = getelementptr inbounds %struct.ADC_TypeDef, ptr %40, i32 0, i32 19
  %42 = load volatile i32, ptr %41, align 4, !tbaa !18
  %43 = zext i32 %42 to i64
  %44 = and i64 %43, 384
  %45 = icmp eq i64 %44, 0
  br i1 %45, label %46, label %57

46:                                               ; preds = %29
  %47 = load i32, ptr %5, align 4, !tbaa !15
  %48 = zext i32 %47 to i64
  %49 = icmp eq i64 %48, 0
  br i1 %49, label %50, label %57

50:                                               ; preds = %46
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %51, i32 0, i32 4
  %53 = load volatile i32, ptr %52, align 4, !tbaa !19
  %54 = zext i32 %53 to i64
  %55 = or i64 %54, 32
  %56 = trunc i64 %55 to i32
  store volatile i32 %56, ptr %52, align 4, !tbaa !19
  store i32 1, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %247

57:                                               ; preds = %46, %29
  br label %58

58:                                               ; preds = %57
  %59 = load ptr, ptr %3, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %59, i32 0, i32 3
  %61 = load i32, ptr %60, align 8, !tbaa !20
  %62 = icmp eq i32 %61, 1
  br i1 %62, label %63, label %64

63:                                               ; preds = %58
  store i32 2, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %247

64:                                               ; preds = %58
  %65 = load ptr, ptr %3, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %65, i32 0, i32 3
  store i32 1, ptr %66, align 8, !tbaa !20
  br label %67

67:                                               ; preds = %64
  br label %68

68:                                               ; preds = %67
  br label %69

69:                                               ; preds = %68
  %70 = load ptr, ptr %3, align 8, !tbaa !5
  %71 = call i32 @ADC_Enable(ptr noundef %70)
  store i32 %71, ptr %4, align 4, !tbaa !15
  %72 = load i32, ptr %4, align 4, !tbaa !15
  %73 = icmp eq i32 %72, 0
  br i1 %73, label %74, label %239

74:                                               ; preds = %69
  %75 = load ptr, ptr %3, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %75, i32 0, i32 4
  %77 = load volatile i32, ptr %76, align 4, !tbaa !19
  %78 = zext i32 %77 to i64
  %79 = and i64 %78, 256
  %80 = icmp ne i64 %79, 0
  br i1 %80, label %81, label %86

81:                                               ; preds = %74
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %82, i32 0, i32 5
  %84 = load volatile i32, ptr %83, align 8, !tbaa !21
  %85 = and i32 %84, -9
  store volatile i32 %85, ptr %83, align 8, !tbaa !21
  br label %89

86:                                               ; preds = %74
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %87, i32 0, i32 5
  store volatile i32 0, ptr %88, align 8, !tbaa !21
  br label %89

89:                                               ; preds = %86, %81
  %90 = load ptr, ptr %3, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %90, i32 0, i32 4
  %92 = load volatile i32, ptr %91, align 4, !tbaa !19
  %93 = zext i32 %92 to i64
  %94 = and i64 %93, -8194
  %95 = or i64 %94, 4096
  %96 = trunc i64 %95 to i32
  %97 = load ptr, ptr %3, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %97, i32 0, i32 4
  store volatile i32 %96, ptr %98, align 4, !tbaa !19
  %99 = load ptr, ptr %3, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %99, i32 0, i32 0
  %101 = load ptr, ptr %100, align 8, !tbaa !9
  %102 = icmp eq ptr %101, inttoptr (i64 1073881344 to ptr)
  br i1 %102, label %103, label %104

103:                                              ; preds = %89
  br label %108

104:                                              ; preds = %89
  %105 = load ptr, ptr %3, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %105, i32 0, i32 0
  %107 = load ptr, ptr %106, align 8, !tbaa !9
  br label %108

108:                                              ; preds = %104, %103
  %109 = phi ptr [ inttoptr (i64 1073881088 to ptr), %103 ], [ %107, %104 ]
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %110, i32 0, i32 0
  %112 = load ptr, ptr %111, align 8, !tbaa !9
  %113 = icmp eq ptr %109, %112
  br i1 %113, label %118, label %114

114:                                              ; preds = %108
  %115 = load i32, ptr %6, align 4, !tbaa !15
  %116 = zext i32 %115 to i64
  %117 = icmp eq i64 %116, 0
  br i1 %117, label %118, label %125

118:                                              ; preds = %114, %108
  %119 = load ptr, ptr %3, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %119, i32 0, i32 4
  %121 = load volatile i32, ptr %120, align 4, !tbaa !19
  %122 = zext i32 %121 to i64
  %123 = and i64 %122, -1048577
  %124 = trunc i64 %123 to i32
  store volatile i32 %124, ptr %120, align 4, !tbaa !19
  br label %125

125:                                              ; preds = %118, %114
  %126 = load ptr, ptr %3, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %126, i32 0, i32 0
  %128 = load ptr, ptr %127, align 8, !tbaa !9
  %129 = getelementptr inbounds %struct.ADC_TypeDef, ptr %128, i32 0, i32 0
  store volatile i32 96, ptr %129, align 4, !tbaa !22
  br label %130

130:                                              ; preds = %125
  %131 = load ptr, ptr %3, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %131, i32 0, i32 3
  store i32 0, ptr %132, align 8, !tbaa !20
  br label %133

133:                                              ; preds = %130
  br label %134

134:                                              ; preds = %133
  %135 = load ptr, ptr %3, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %135, i32 0, i32 0
  %137 = load ptr, ptr %136, align 8, !tbaa !9
  %138 = getelementptr inbounds %struct.ADC_TypeDef, ptr %137, i32 0, i32 3
  %139 = load volatile i32, ptr %138, align 4, !tbaa !16
  %140 = zext i32 %139 to i64
  %141 = and i64 %140, 2097152
  %142 = icmp ne i64 %141, 0
  br i1 %142, label %143, label %152

143:                                              ; preds = %134
  %144 = load ptr, ptr %3, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %144, i32 0, i32 0
  %146 = load ptr, ptr %145, align 8, !tbaa !9
  %147 = getelementptr inbounds %struct.ADC_TypeDef, ptr %146, i32 0, i32 1
  %148 = load volatile i32, ptr %147, align 4, !tbaa !23
  %149 = zext i32 %148 to i64
  %150 = or i64 %149, 1024
  %151 = trunc i64 %150 to i32
  store volatile i32 %151, ptr %147, align 4, !tbaa !23
  br label %152

152:                                              ; preds = %143, %134
  %153 = load ptr, ptr %3, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %153, i32 0, i32 1
  %155 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %154, i32 0, i32 3
  %156 = load i32, ptr %155, align 4, !tbaa !24
  switch i32 %156, label %174 [
    i32 8, label %157
  ]

157:                                              ; preds = %152
  %158 = load ptr, ptr %3, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %158, i32 0, i32 0
  %160 = load ptr, ptr %159, align 8, !tbaa !9
  %161 = getelementptr inbounds %struct.ADC_TypeDef, ptr %160, i32 0, i32 1
  %162 = load volatile i32, ptr %161, align 4, !tbaa !23
  %163 = zext i32 %162 to i64
  %164 = and i64 %163, -33
  %165 = trunc i64 %164 to i32
  store volatile i32 %165, ptr %161, align 4, !tbaa !23
  %166 = load ptr, ptr %3, align 8, !tbaa !5
  %167 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %166, i32 0, i32 0
  %168 = load ptr, ptr %167, align 8, !tbaa !9
  %169 = getelementptr inbounds %struct.ADC_TypeDef, ptr %168, i32 0, i32 1
  %170 = load volatile i32, ptr %169, align 4, !tbaa !23
  %171 = zext i32 %170 to i64
  %172 = or i64 %171, 64
  %173 = trunc i64 %172 to i32
  store volatile i32 %173, ptr %169, align 4, !tbaa !23
  br label %191

174:                                              ; preds = %152
  %175 = load ptr, ptr %3, align 8, !tbaa !5
  %176 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %175, i32 0, i32 0
  %177 = load ptr, ptr %176, align 8, !tbaa !9
  %178 = getelementptr inbounds %struct.ADC_TypeDef, ptr %177, i32 0, i32 1
  %179 = load volatile i32, ptr %178, align 4, !tbaa !23
  %180 = zext i32 %179 to i64
  %181 = and i64 %180, -65
  %182 = trunc i64 %181 to i32
  store volatile i32 %182, ptr %178, align 4, !tbaa !23
  %183 = load ptr, ptr %3, align 8, !tbaa !5
  %184 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %183, i32 0, i32 0
  %185 = load ptr, ptr %184, align 8, !tbaa !9
  %186 = getelementptr inbounds %struct.ADC_TypeDef, ptr %185, i32 0, i32 1
  %187 = load volatile i32, ptr %186, align 4, !tbaa !23
  %188 = zext i32 %187 to i64
  %189 = or i64 %188, 32
  %190 = trunc i64 %189 to i32
  store volatile i32 %190, ptr %186, align 4, !tbaa !23
  br label %191

191:                                              ; preds = %174, %157
  %192 = load ptr, ptr %3, align 8, !tbaa !5
  %193 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %192, i32 0, i32 0
  %194 = load ptr, ptr %193, align 8, !tbaa !9
  %195 = icmp eq ptr %194, inttoptr (i64 1073881344 to ptr)
  br i1 %195, label %196, label %197

196:                                              ; preds = %191
  br label %201

197:                                              ; preds = %191
  %198 = load ptr, ptr %3, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %198, i32 0, i32 0
  %200 = load ptr, ptr %199, align 8, !tbaa !9
  br label %201

201:                                              ; preds = %197, %196
  %202 = phi ptr [ inttoptr (i64 1073881088 to ptr), %196 ], [ %200, %197 ]
  %203 = load ptr, ptr %3, align 8, !tbaa !5
  %204 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %203, i32 0, i32 0
  %205 = load ptr, ptr %204, align 8, !tbaa !9
  %206 = icmp eq ptr %202, %205
  br i1 %206, label %219, label %207

207:                                              ; preds = %201
  %208 = load i32, ptr %6, align 4, !tbaa !15
  %209 = zext i32 %208 to i64
  %210 = icmp eq i64 %209, 0
  br i1 %210, label %219, label %211

211:                                              ; preds = %207
  %212 = load i32, ptr %6, align 4, !tbaa !15
  %213 = zext i32 %212 to i64
  %214 = icmp eq i64 %213, 6
  br i1 %214, label %219, label %215

215:                                              ; preds = %211
  %216 = load i32, ptr %6, align 4, !tbaa !15
  %217 = zext i32 %216 to i64
  %218 = icmp eq i64 %217, 7
  br i1 %218, label %219, label %231

219:                                              ; preds = %215, %211, %207, %201
  %220 = load ptr, ptr %3, align 8, !tbaa !5
  %221 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %220, i32 0, i32 0
  %222 = load ptr, ptr %221, align 8, !tbaa !9
  %223 = call i32 @LL_ADC_INJ_GetTrigAuto(ptr noundef %222)
  %224 = zext i32 %223 to i64
  %225 = icmp eq i64 %224, 0
  br i1 %225, label %226, label %230

226:                                              ; preds = %219
  %227 = load ptr, ptr %3, align 8, !tbaa !5
  %228 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %227, i32 0, i32 0
  %229 = load ptr, ptr %228, align 8, !tbaa !9
  call void @LL_ADC_INJ_StartConversion(ptr noundef %229)
  br label %230

230:                                              ; preds = %226, %219
  br label %238

231:                                              ; preds = %215
  %232 = load ptr, ptr %3, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %232, i32 0, i32 4
  %234 = load volatile i32, ptr %233, align 4, !tbaa !19
  %235 = zext i32 %234 to i64
  %236 = or i64 %235, 1048576
  %237 = trunc i64 %236 to i32
  store volatile i32 %237, ptr %233, align 4, !tbaa !19
  br label %238

238:                                              ; preds = %231, %230
  br label %245

239:                                              ; preds = %69
  br label %240

240:                                              ; preds = %239
  %241 = load ptr, ptr %3, align 8, !tbaa !5
  %242 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %241, i32 0, i32 3
  store i32 0, ptr %242, align 8, !tbaa !20
  br label %243

243:                                              ; preds = %240
  br label %244

244:                                              ; preds = %243
  br label %245

245:                                              ; preds = %244, %238
  %246 = load i32, ptr %4, align 4, !tbaa !15
  store i32 %246, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %247

247:                                              ; preds = %245, %63, %50, %28
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %248 = load i32, ptr %2, align 4
  ret i32 %248
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"", !6, i64 0, !11, i64 8, !6, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !14, i64 108}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !13, i64 60}
!12 = !{!"int", !7, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!14 = !{!"", !12, i64 0, !12, i64 4}
!15 = !{!12, !12, i64 0}
!16 = !{!17, !12, i64 12}
!17 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !7, i64 112, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !7, i64 144, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200}
!18 = !{!17, !12, i64 76}
!19 = !{!10, !12, i64 100}
!20 = !{!10, !12, i64 96}
!21 = !{!10, !12, i64 104}
!22 = !{!17, !12, i64 0}
!23 = !{!17, !12, i64 4}
!24 = !{!10, !12, i64 20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @ADC_Enable(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_INJ_GetTrigAuto(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_INJ_StartConversion(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_InjectedStart_IT(ptr noundef %0) local_unnamed_addr #2 {
  %2 = load ptr, ptr %0, align 8, !tbaa !5
  %3 = icmp eq ptr %2, inttoptr (i64 1073881088 to ptr)
  %4 = icmp eq ptr %2, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %3, %4
  %5 = select i1 %spec.select, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %6 = tail call i32 @LL_ADC_GetMultimode(ptr noundef nonnull %5)
  %7 = load ptr, ptr %0, align 8, !tbaa !5
  %8 = tail call i32 @LL_ADC_INJ_IsConversionOngoing(ptr noundef %7)
  %.not = icmp eq i32 %8, 0
  br i1 %.not, label %9, label %72

9:                                                ; preds = %1
  %10 = load ptr, ptr %0, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %10, i64 12
  %12 = load volatile i32, ptr %11, align 4, !tbaa !14
  %13 = getelementptr inbounds i8, ptr %10, i64 76
  %14 = load volatile i32, ptr %13, align 4, !tbaa !16
  %15 = and i32 %14, 384
  %16 = icmp eq i32 %15, 0
  %17 = icmp sgt i32 %12, -1
  %or.cond = select i1 %16, i1 %17, i1 false
  br i1 %or.cond, label %18, label %22

18:                                               ; preds = %9
  %19 = getelementptr inbounds i8, ptr %0, i64 100
  %20 = load volatile i32, ptr %19, align 4, !tbaa !17
  %21 = or i32 %20, 32
  store volatile i32 %21, ptr %19, align 4, !tbaa !17
  br label %72

22:                                               ; preds = %9
  %23 = getelementptr inbounds i8, ptr %0, i64 96
  %24 = load i32, ptr %23, align 8, !tbaa !18
  %25 = icmp eq i32 %24, 1
  br i1 %25, label %72, label %26

26:                                               ; preds = %22
  store i32 1, ptr %23, align 8, !tbaa !18
  %27 = tail call i32 @ADC_Enable(ptr noundef nonnull %0) #3
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %29, label %71

29:                                               ; preds = %26
  %30 = getelementptr inbounds i8, ptr %0, i64 100
  %31 = load volatile i32, ptr %30, align 4, !tbaa !17
  %32 = and i32 %31, 256
  %.not58 = icmp eq i32 %32, 0
  %33 = getelementptr inbounds i8, ptr %0, i64 104
  br i1 %.not58, label %37, label %34

34:                                               ; preds = %29
  %35 = load volatile i32, ptr %33, align 8, !tbaa !19
  %36 = and i32 %35, -9
  br label %37

37:                                               ; preds = %29, %34
  %.sink = phi i32 [ %36, %34 ], [ 0, %29 ]
  store volatile i32 %.sink, ptr %33, align 8, !tbaa !19
  %38 = load volatile i32, ptr %30, align 4, !tbaa !17
  %39 = and i32 %38, -12290
  %40 = or disjoint i32 %39, 4096
  store volatile i32 %40, ptr %30, align 4, !tbaa !17
  %41 = load ptr, ptr %0, align 8, !tbaa !5
  %.fr = freeze ptr %41
  %42 = icmp ne ptr %.fr, inttoptr (i64 1073881344 to ptr)
  %43 = icmp eq i32 %6, 0
  %or.cond5 = select i1 %42, i1 true, i1 %43
  br i1 %or.cond5, label %44, label %47

44:                                               ; preds = %37
  %45 = load volatile i32, ptr %30, align 4, !tbaa !17
  %46 = and i32 %45, -1048577
  store volatile i32 %46, ptr %30, align 4, !tbaa !17
  br label %47

47:                                               ; preds = %37, %44
  store volatile i32 96, ptr %.fr, align 4, !tbaa !20
  store i32 0, ptr %23, align 8, !tbaa !18
  %48 = getelementptr inbounds i8, ptr %.fr, i64 12
  %49 = load volatile i32, ptr %48, align 4, !tbaa !14
  %50 = and i32 %49, 2097152
  %.not59 = icmp eq i32 %50, 0
  br i1 %.not59, label %55, label %51

51:                                               ; preds = %47
  %52 = getelementptr inbounds i8, ptr %.fr, i64 4
  %53 = load volatile i32, ptr %52, align 4, !tbaa !21
  %54 = or i32 %53, 1024
  store volatile i32 %54, ptr %52, align 4, !tbaa !21
  br label %55

55:                                               ; preds = %51, %47
  %56 = getelementptr inbounds i8, ptr %0, i64 20
  %57 = load i32, ptr %56, align 4, !tbaa !22
  %cond = icmp eq i32 %57, 8
  %58 = getelementptr inbounds i8, ptr %.fr, i64 4
  %59 = load volatile i32, ptr %58, align 4, !tbaa !21
  %. = select i1 %cond, i32 -33, i32 -65
  %.67 = select i1 %cond, i32 64, i32 32
  %60 = and i32 %59, %.
  store volatile i32 %60, ptr %58, align 4, !tbaa !21
  %61 = load volatile i32, ptr %58, align 4, !tbaa !21
  %62 = or i32 %61, %.67
  store volatile i32 %62, ptr %58, align 4, !tbaa !21
  br i1 %42, label %63, label %switch.early.test

switch.early.test:                                ; preds = %55
  switch i32 %6, label %68 [
    i32 7, label %63
    i32 6, label %63
    i32 0, label %63
  ]

63:                                               ; preds = %switch.early.test, %switch.early.test, %switch.early.test, %55
  %64 = tail call i32 @LL_ADC_INJ_GetTrigAuto(ptr noundef nonnull %.fr)
  %65 = icmp eq i32 %64, 0
  br i1 %65, label %66, label %72

66:                                               ; preds = %63
  %67 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @LL_ADC_INJ_StartConversion(ptr noundef %67)
  br label %72

68:                                               ; preds = %switch.early.test
  %69 = load volatile i32, ptr %30, align 4, !tbaa !17
  %70 = or i32 %69, 1048576
  store volatile i32 %70, ptr %30, align 4, !tbaa !17
  br label %72

71:                                               ; preds = %26
  store i32 0, ptr %23, align 8, !tbaa !18
  br label %72

72:                                               ; preds = %71, %63, %66, %68, %22, %1, %18
  %.0 = phi i32 [ 1, %18 ], [ 2, %1 ], [ 2, %22 ], [ 0, %68 ], [ 0, %66 ], [ 0, %63 ], [ %27, %71 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!15, !11, i64 12}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!16 = !{!15, !11, i64 76}
!17 = !{!6, !11, i64 100}
!18 = !{!6, !11, i64 96}
!19 = !{!6, !11, i64 104}
!20 = !{!15, !11, i64 0}
!21 = !{!15, !11, i64 4}
!22 = !{!6, !11, i64 20}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass