; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (EnableNotification)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__RAMECC_HandleTypeDef = type { ptr, i32, ptr }
%struct.RAMECC_TypeDef = type { i32 }
%struct.RAMECC_MonitorTypeDef = type { i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_RAMECC_EnableNotification(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %2
  store i32 1, ptr %3, align 4
  br label %80

11:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.__RAMECC_HandleTypeDef, ptr %12, i32 0, i32 1
  %14 = load volatile i32, ptr %13, align 8, !tbaa !11
  store i32 %14, ptr %6, align 4, !tbaa !9
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = icmp eq i32 %15, 1
  br i1 %16, label %20, label %17

17:                                               ; preds = %11
  %18 = load i32, ptr %6, align 4, !tbaa !9
  %19 = icmp eq i32 %18, 2
  br i1 %19, label %20, label %75

20:                                               ; preds = %17, %11
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = zext i32 %21 to i64
  %23 = and i64 %22, 268435457
  %24 = icmp eq i64 %23, 268435457
  br i1 %24, label %45, label %25

25:                                               ; preds = %20
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = zext i32 %26 to i64
  %28 = and i64 %27, 268435458
  %29 = icmp eq i64 %28, 268435458
  br i1 %29, label %45, label %30

30:                                               ; preds = %25
  %31 = load i32, ptr %5, align 4, !tbaa !9
  %32 = zext i32 %31 to i64
  %33 = and i64 %32, 268435460
  %34 = icmp eq i64 %33, 268435460
  br i1 %34, label %45, label %35

35:                                               ; preds = %30
  %36 = load i32, ptr %5, align 4, !tbaa !9
  %37 = zext i32 %36 to i64
  %38 = and i64 %37, 268435464
  %39 = icmp eq i64 %38, 268435464
  br i1 %39, label %45, label %40

40:                                               ; preds = %35
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = zext i32 %41 to i64
  %43 = and i64 %42, 268435471
  %44 = icmp eq i64 %43, 268435471
  br i1 %44, label %45, label %61

45:                                               ; preds = %40, %35, %30, %25, %20
  %46 = load i32, ptr %5, align 4, !tbaa !9
  %47 = zext i32 %46 to i64
  %48 = and i64 %47, -268435457
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.__RAMECC_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !13
  %52 = ptrtoint ptr %51 to i32
  %53 = and i32 %52, -256
  %54 = zext i32 %53 to i64
  %55 = inttoptr i64 %54 to ptr
  %56 = getelementptr inbounds %struct.RAMECC_TypeDef, ptr %55, i32 0, i32 0
  %57 = load volatile i32, ptr %56, align 4, !tbaa !14
  %58 = zext i32 %57 to i64
  %59 = or i64 %58, %48
  %60 = trunc i64 %59 to i32
  store volatile i32 %60, ptr %56, align 4, !tbaa !14
  br label %73

61:                                               ; preds = %40
  %62 = load i32, ptr %5, align 4, !tbaa !9
  %63 = zext i32 %62 to i64
  %64 = and i64 %63, -536870913
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.__RAMECC_HandleTypeDef, ptr %65, i32 0, i32 0
  %67 = load ptr, ptr %66, align 8, !tbaa !13
  %68 = getelementptr inbounds %struct.RAMECC_MonitorTypeDef, ptr %67, i32 0, i32 0
  %69 = load volatile i32, ptr %68, align 4, !tbaa !16
  %70 = zext i32 %69 to i64
  %71 = or i64 %70, %64
  %72 = trunc i64 %71 to i32
  store volatile i32 %72, ptr %68, align 4, !tbaa !16
  br label %73

73:                                               ; preds = %61, %45
  %74 = phi i32 [ %60, %45 ], [ %72, %61 ]
  br label %78

75:                                               ; preds = %17
  %76 = load ptr, ptr %4, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__RAMECC_HandleTypeDef, ptr %76, i32 0, i32 1
  store volatile i32 3, ptr %77, align 8, !tbaa !11
  store i32 1, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %79

78:                                               ; preds = %73
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %79

79:                                               ; preds = %78, %75
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %80

80:                                               ; preds = %79, %10
  %81 = load i32, ptr %3, align 4
  ret i32 %81
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"__RAMECC_HandleTypeDef", !6, i64 0, !10, i64 8, !6, i64 16}
!13 = !{!12, !6, i64 0}
!14 = !{!15, !10, i64 0}
!15 = !{!"", !10, i64 0}
!16 = !{!17, !10, i64 0}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_RAMECC_EnableNotification(ptr noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = icmp eq ptr %0, null
  br i1 %3, label %31, label %4

4:                                                ; preds = %2
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = add i32 %6, -1
  %or.cond = icmp ult i32 %7, 2
  br i1 %or.cond, label %8, label %30

8:                                                ; preds = %4
  %9 = zext i32 %1 to i64
  %10 = and i64 %9, 268435457
  %11 = icmp eq i64 %10, 268435457
  %12 = and i64 %9, 268435458
  %13 = icmp eq i64 %12, 268435458
  %or.cond17 = or i1 %11, %13
  %14 = and i64 %9, 268435460
  %15 = icmp eq i64 %14, 268435460
  %or.cond19 = or i1 %15, %or.cond17
  %16 = and i64 %9, 268435464
  %17 = icmp eq i64 %16, 268435464
  %or.cond23 = or i1 %17, %or.cond19
  %18 = load ptr, ptr %0, align 8, !tbaa !11
  br i1 %or.cond23, label %19, label %26

19:                                               ; preds = %8
  %20 = and i32 %1, -268435457
  %21 = ptrtoint ptr %18 to i64
  %22 = and i64 %21, 4294967040
  %23 = inttoptr i64 %22 to ptr
  %24 = load volatile i32, ptr %23, align 256, !tbaa !12
  %25 = or i32 %24, %20
  store volatile i32 %25, ptr %23, align 256, !tbaa !12
  br label %31

26:                                               ; preds = %8
  %27 = and i32 %1, -536870913
  %28 = load volatile i32, ptr %18, align 4, !tbaa !14
  %29 = or i32 %28, %27
  store volatile i32 %29, ptr %18, align 4, !tbaa !14
  br label %31

30:                                               ; preds = %4
  store volatile i32 3, ptr %5, align 8, !tbaa !5
  br label %31

31:                                               ; preds = %30, %19, %26, %2
  %.1 = phi i32 [ 1, %2 ], [ 1, %30 ], [ 0, %19 ], [ 0, %26 ]
  ret i32 %.1
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 8}
!6 = !{!"__RAMECC_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 16}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!6, !7, i64 0}
!12 = !{!13, !10, i64 0}
!13 = !{!"", !10, i64 0}
!14 = !{!15, !10, i64 0}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass