; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_Encoder_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, ptr noundef %3, i16 noundef zeroext %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i16, align 2
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store ptr %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store i16 %4, ptr %11, align 2, !tbaa !11
  %12 = load ptr, ptr %7, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 5
  %14 = load volatile i32, ptr %13, align 4, !tbaa !13
  %15 = icmp eq i32 %14, 2
  br i1 %15, label %16, label %17

16:                                               ; preds = %5
  store i32 2, ptr %6, align 4
  br label %242

17:                                               ; preds = %5
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %18, i32 0, i32 5
  %20 = load volatile i32, ptr %19, align 4, !tbaa !13
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %22, label %37

22:                                               ; preds = %17
  %23 = load ptr, ptr %9, align 8, !tbaa !5
  %24 = icmp eq ptr %23, null
  br i1 %24, label %28, label %25

25:                                               ; preds = %22
  %26 = load ptr, ptr %10, align 8, !tbaa !5
  %27 = icmp eq ptr %26, null
  br i1 %27, label %28, label %33

28:                                               ; preds = %25, %22
  %29 = load i16, ptr %11, align 2, !tbaa !11
  %30 = zext i16 %29 to i32
  %31 = icmp ugt i32 %30, 0
  br i1 %31, label %32, label %33

32:                                               ; preds = %28
  store i32 1, ptr %6, align 4
  br label %242

33:                                               ; preds = %28, %25
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %34, i32 0, i32 5
  store volatile i32 2, ptr %35, align 4, !tbaa !13
  br label %36

36:                                               ; preds = %33
  br label %38

37:                                               ; preds = %17
  br label %38

38:                                               ; preds = %37, %36
  br label %39

39:                                               ; preds = %38
  %40 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %40, label %240 [
    i32 0, label %41
    i32 4, label %93
    i32 60, label %145
  ]

41:                                               ; preds = %39
  %42 = load ptr, ptr %7, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %42, i32 0, i32 3
  %44 = getelementptr inbounds [7 x ptr], ptr %43, i64 0, i64 1
  %45 = load ptr, ptr %44, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %45, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %46, align 8, !tbaa !16
  %47 = load ptr, ptr %7, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %47, i32 0, i32 3
  %49 = getelementptr inbounds [7 x ptr], ptr %48, i64 0, i64 1
  %50 = load ptr, ptr %49, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %50, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %51, align 8, !tbaa !19
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %52, i32 0, i32 3
  %54 = getelementptr inbounds [7 x ptr], ptr %53, i64 0, i64 1
  %55 = load ptr, ptr %54, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %55, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %56, align 8, !tbaa !20
  %57 = load ptr, ptr %7, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %57, i32 0, i32 3
  %59 = getelementptr inbounds [7 x ptr], ptr %58, i64 0, i64 1
  %60 = load ptr, ptr %59, align 8, !tbaa !5
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !21
  %64 = getelementptr inbounds %struct.TIM_TypeDef, ptr %63, i32 0, i32 13
  %65 = ptrtoint ptr %64 to i32
  %66 = load ptr, ptr %9, align 8, !tbaa !5
  %67 = ptrtoint ptr %66 to i32
  %68 = load i16, ptr %11, align 2, !tbaa !11
  %69 = zext i16 %68 to i32
  %70 = call i32 @HAL_DMA_Start_IT(ptr noundef %60, i32 noundef %65, i32 noundef %67, i32 noundef %69)
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %73

72:                                               ; preds = %41
  store i32 1, ptr %6, align 4
  br label %242

73:                                               ; preds = %41
  %74 = load ptr, ptr %7, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %74, i32 0, i32 0
  %76 = load ptr, ptr %75, align 8, !tbaa !21
  %77 = getelementptr inbounds %struct.TIM_TypeDef, ptr %76, i32 0, i32 3
  %78 = load volatile i32, ptr %77, align 4, !tbaa !22
  %79 = zext i32 %78 to i64
  %80 = or i64 %79, 512
  %81 = trunc i64 %80 to i32
  store volatile i32 %81, ptr %77, align 4, !tbaa !22
  %82 = load ptr, ptr %7, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !21
  %85 = getelementptr inbounds %struct.TIM_TypeDef, ptr %84, i32 0, i32 0
  %86 = load volatile i32, ptr %85, align 4, !tbaa !24
  %87 = zext i32 %86 to i64
  %88 = or i64 %87, 1
  %89 = trunc i64 %88 to i32
  store volatile i32 %89, ptr %85, align 4, !tbaa !24
  %90 = load ptr, ptr %7, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %90, i32 0, i32 0
  %92 = load ptr, ptr %91, align 8, !tbaa !21
  call void @TIM_CCxChannelCmd(ptr noundef %92, i32 noundef 0, i32 noundef 1)
  br label %241

93:                                               ; preds = %39
  %94 = load ptr, ptr %7, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %94, i32 0, i32 3
  %96 = getelementptr inbounds [7 x ptr], ptr %95, i64 0, i64 2
  %97 = load ptr, ptr %96, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %97, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %98, align 8, !tbaa !16
  %99 = load ptr, ptr %7, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %99, i32 0, i32 3
  %101 = getelementptr inbounds [7 x ptr], ptr %100, i64 0, i64 2
  %102 = load ptr, ptr %101, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %102, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %103, align 8, !tbaa !19
  %104 = load ptr, ptr %7, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %104, i32 0, i32 3
  %106 = getelementptr inbounds [7 x ptr], ptr %105, i64 0, i64 2
  %107 = load ptr, ptr %106, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %107, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %108, align 8, !tbaa !20
  %109 = load ptr, ptr %7, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %109, i32 0, i32 3
  %111 = getelementptr inbounds [7 x ptr], ptr %110, i64 0, i64 2
  %112 = load ptr, ptr %111, align 8, !tbaa !5
  %113 = load ptr, ptr %7, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %113, i32 0, i32 0
  %115 = load ptr, ptr %114, align 8, !tbaa !21
  %116 = getelementptr inbounds %struct.TIM_TypeDef, ptr %115, i32 0, i32 14
  %117 = ptrtoint ptr %116 to i32
  %118 = load ptr, ptr %10, align 8, !tbaa !5
  %119 = ptrtoint ptr %118 to i32
  %120 = load i16, ptr %11, align 2, !tbaa !11
  %121 = zext i16 %120 to i32
  %122 = call i32 @HAL_DMA_Start_IT(ptr noundef %112, i32 noundef %117, i32 noundef %119, i32 noundef %121)
  %123 = icmp ne i32 %122, 0
  br i1 %123, label %124, label %125

124:                                              ; preds = %93
  store i32 1, ptr %6, align 4
  br label %242

125:                                              ; preds = %93
  %126 = load ptr, ptr %7, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %126, i32 0, i32 0
  %128 = load ptr, ptr %127, align 8, !tbaa !21
  %129 = getelementptr inbounds %struct.TIM_TypeDef, ptr %128, i32 0, i32 3
  %130 = load volatile i32, ptr %129, align 4, !tbaa !22
  %131 = zext i32 %130 to i64
  %132 = or i64 %131, 1024
  %133 = trunc i64 %132 to i32
  store volatile i32 %133, ptr %129, align 4, !tbaa !22
  %134 = load ptr, ptr %7, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %134, i32 0, i32 0
  %136 = load ptr, ptr %135, align 8, !tbaa !21
  %137 = getelementptr inbounds %struct.TIM_TypeDef, ptr %136, i32 0, i32 0
  %138 = load volatile i32, ptr %137, align 4, !tbaa !24
  %139 = zext i32 %138 to i64
  %140 = or i64 %139, 1
  %141 = trunc i64 %140 to i32
  store volatile i32 %141, ptr %137, align 4, !tbaa !24
  %142 = load ptr, ptr %7, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %142, i32 0, i32 0
  %144 = load ptr, ptr %143, align 8, !tbaa !21
  call void @TIM_CCxChannelCmd(ptr noundef %144, i32 noundef 4, i32 noundef 1)
  br label %241

145:                                              ; preds = %39
  %146 = load ptr, ptr %7, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %146, i32 0, i32 3
  %148 = getelementptr inbounds [7 x ptr], ptr %147, i64 0, i64 1
  %149 = load ptr, ptr %148, align 8, !tbaa !5
  %150 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %149, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %150, align 8, !tbaa !16
  %151 = load ptr, ptr %7, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %151, i32 0, i32 3
  %153 = getelementptr inbounds [7 x ptr], ptr %152, i64 0, i64 1
  %154 = load ptr, ptr %153, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %154, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %155, align 8, !tbaa !19
  %156 = load ptr, ptr %7, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %156, i32 0, i32 3
  %158 = getelementptr inbounds [7 x ptr], ptr %157, i64 0, i64 1
  %159 = load ptr, ptr %158, align 8, !tbaa !5
  %160 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %159, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %160, align 8, !tbaa !20
  %161 = load ptr, ptr %7, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %161, i32 0, i32 3
  %163 = getelementptr inbounds [7 x ptr], ptr %162, i64 0, i64 1
  %164 = load ptr, ptr %163, align 8, !tbaa !5
  %165 = load ptr, ptr %7, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %165, i32 0, i32 0
  %167 = load ptr, ptr %166, align 8, !tbaa !21
  %168 = getelementptr inbounds %struct.TIM_TypeDef, ptr %167, i32 0, i32 13
  %169 = ptrtoint ptr %168 to i32
  %170 = load ptr, ptr %9, align 8, !tbaa !5
  %171 = ptrtoint ptr %170 to i32
  %172 = load i16, ptr %11, align 2, !tbaa !11
  %173 = zext i16 %172 to i32
  %174 = call i32 @HAL_DMA_Start_IT(ptr noundef %164, i32 noundef %169, i32 noundef %171, i32 noundef %173)
  %175 = icmp ne i32 %174, 0
  br i1 %175, label %176, label %177

176:                                              ; preds = %145
  store i32 1, ptr %6, align 4
  br label %242

177:                                              ; preds = %145
  %178 = load ptr, ptr %7, align 8, !tbaa !5
  %179 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %178, i32 0, i32 3
  %180 = getelementptr inbounds [7 x ptr], ptr %179, i64 0, i64 2
  %181 = load ptr, ptr %180, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %181, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %182, align 8, !tbaa !16
  %183 = load ptr, ptr %7, align 8, !tbaa !5
  %184 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %183, i32 0, i32 3
  %185 = getelementptr inbounds [7 x ptr], ptr %184, i64 0, i64 2
  %186 = load ptr, ptr %185, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %186, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %187, align 8, !tbaa !19
  %188 = load ptr, ptr %7, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %188, i32 0, i32 3
  %190 = getelementptr inbounds [7 x ptr], ptr %189, i64 0, i64 2
  %191 = load ptr, ptr %190, align 8, !tbaa !5
  %192 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %191, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %192, align 8, !tbaa !20
  %193 = load ptr, ptr %7, align 8, !tbaa !5
  %194 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %193, i32 0, i32 3
  %195 = getelementptr inbounds [7 x ptr], ptr %194, i64 0, i64 2
  %196 = load ptr, ptr %195, align 8, !tbaa !5
  %197 = load ptr, ptr %7, align 8, !tbaa !5
  %198 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %197, i32 0, i32 0
  %199 = load ptr, ptr %198, align 8, !tbaa !21
  %200 = getelementptr inbounds %struct.TIM_TypeDef, ptr %199, i32 0, i32 14
  %201 = ptrtoint ptr %200 to i32
  %202 = load ptr, ptr %10, align 8, !tbaa !5
  %203 = ptrtoint ptr %202 to i32
  %204 = load i16, ptr %11, align 2, !tbaa !11
  %205 = zext i16 %204 to i32
  %206 = call i32 @HAL_DMA_Start_IT(ptr noundef %196, i32 noundef %201, i32 noundef %203, i32 noundef %205)
  %207 = icmp ne i32 %206, 0
  br i1 %207, label %208, label %209

208:                                              ; preds = %177
  store i32 1, ptr %6, align 4
  br label %242

209:                                              ; preds = %177
  %210 = load ptr, ptr %7, align 8, !tbaa !5
  %211 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %210, i32 0, i32 0
  %212 = load ptr, ptr %211, align 8, !tbaa !21
  %213 = getelementptr inbounds %struct.TIM_TypeDef, ptr %212, i32 0, i32 0
  %214 = load volatile i32, ptr %213, align 4, !tbaa !24
  %215 = zext i32 %214 to i64
  %216 = or i64 %215, 1
  %217 = trunc i64 %216 to i32
  store volatile i32 %217, ptr %213, align 4, !tbaa !24
  %218 = load ptr, ptr %7, align 8, !tbaa !5
  %219 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %218, i32 0, i32 0
  %220 = load ptr, ptr %219, align 8, !tbaa !21
  call void @TIM_CCxChannelCmd(ptr noundef %220, i32 noundef 0, i32 noundef 1)
  %221 = load ptr, ptr %7, align 8, !tbaa !5
  %222 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %221, i32 0, i32 0
  %223 = load ptr, ptr %222, align 8, !tbaa !21
  call void @TIM_CCxChannelCmd(ptr noundef %223, i32 noundef 4, i32 noundef 1)
  %224 = load ptr, ptr %7, align 8, !tbaa !5
  %225 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %224, i32 0, i32 0
  %226 = load ptr, ptr %225, align 8, !tbaa !21
  %227 = getelementptr inbounds %struct.TIM_TypeDef, ptr %226, i32 0, i32 3
  %228 = load volatile i32, ptr %227, align 4, !tbaa !22
  %229 = zext i32 %228 to i64
  %230 = or i64 %229, 512
  %231 = trunc i64 %230 to i32
  store volatile i32 %231, ptr %227, align 4, !tbaa !22
  %232 = load ptr, ptr %7, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %232, i32 0, i32 0
  %234 = load ptr, ptr %233, align 8, !tbaa !21
  %235 = getelementptr inbounds %struct.TIM_TypeDef, ptr %234, i32 0, i32 3
  %236 = load volatile i32, ptr %235, align 4, !tbaa !22
  %237 = zext i32 %236 to i64
  %238 = or i64 %237, 1024
  %239 = trunc i64 %238 to i32
  store volatile i32 %239, ptr %235, align 4, !tbaa !22
  br label %241

240:                                              ; preds = %39
  br label %241

241:                                              ; preds = %240, %209, %125, %73
  store i32 0, ptr %6, align 4
  br label %242

242:                                              ; preds = %241, %208, %176, %124, %72, %32, %16
  %243 = load i32, ptr %6, align 4
  ret i32 %243
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !10, i64 100}
!14 = !{!"", !6, i64 0, !15, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!16 = !{!17, !6, i64 72}
!17 = !{!"__DMA_HandleTypeDef", !6, i64 0, !18, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!19 = !{!17, !6, i64 80}
!20 = !{!17, !6, i64 104}
!21 = !{!14, !6, i64 0}
!22 = !{!23, !10, i64 12}
!23 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!24 = !{!23, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_Encoder_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, ptr noundef %3, i16 noundef zeroext %4) local_unnamed_addr #0 {
  %6 = getelementptr inbounds i8, ptr %0, i64 100
  %7 = load volatile i32, ptr %6, align 4, !tbaa !5
  %8 = icmp eq i32 %7, 2
  br i1 %8, label %110, label %9

9:                                                ; preds = %5
  %10 = load volatile i32, ptr %6, align 4, !tbaa !5
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %12, label %17

12:                                               ; preds = %9
  %13 = icmp eq ptr %2, null
  %14 = icmp eq ptr %3, null
  %or.cond = or i1 %13, %14
  %15 = icmp ne i16 %4, 0
  %or.cond4 = and i1 %or.cond, %15
  br i1 %or.cond4, label %110, label %16

16:                                               ; preds = %12
  store volatile i32 2, ptr %6, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %16, %9
  switch i32 %1, label %110 [
    i32 0, label %18
    i32 4, label %42
    i32 60, label %66
  ]

18:                                               ; preds = %17
  %19 = getelementptr inbounds i8, ptr %0, i64 48
  %20 = load ptr, ptr %19, align 8, !tbaa !12
  %21 = getelementptr inbounds i8, ptr %20, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %21, align 8, !tbaa !13
  %22 = load ptr, ptr %19, align 8, !tbaa !12
  %23 = getelementptr inbounds i8, ptr %22, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %23, align 8, !tbaa !16
  %24 = load ptr, ptr %19, align 8, !tbaa !12
  %25 = getelementptr inbounds i8, ptr %24, i64 104
  store ptr @TIM_DMAError, ptr %25, align 8, !tbaa !17
  %26 = load ptr, ptr %19, align 8, !tbaa !12
  %27 = load ptr, ptr %0, align 8, !tbaa !18
  %28 = getelementptr inbounds i8, ptr %27, i64 52
  %29 = ptrtoint ptr %28 to i64
  %30 = trunc i64 %29 to i32
  %31 = ptrtoint ptr %2 to i64
  %32 = trunc i64 %31 to i32
  %33 = zext i16 %4 to i32
  %34 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %26, i32 noundef %30, i32 noundef %32, i32 noundef %33) #2
  %.not52 = icmp eq i32 %34, 0
  br i1 %.not52, label %35, label %110

35:                                               ; preds = %18
  %36 = load ptr, ptr %0, align 8, !tbaa !18
  %37 = getelementptr inbounds i8, ptr %36, i64 12
  %38 = load volatile i32, ptr %37, align 4, !tbaa !19
  %39 = or i32 %38, 512
  store volatile i32 %39, ptr %37, align 4, !tbaa !19
  %40 = load volatile i32, ptr %36, align 4, !tbaa !21
  %41 = or i32 %40, 1
  store volatile i32 %41, ptr %36, align 4, !tbaa !21
  tail call void @TIM_CCxChannelCmd(ptr noundef nonnull %36, i32 noundef 0, i32 noundef 1)
  br label %110

42:                                               ; preds = %17
  %43 = getelementptr inbounds i8, ptr %0, i64 56
  %44 = load ptr, ptr %43, align 8, !tbaa !12
  %45 = getelementptr inbounds i8, ptr %44, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %45, align 8, !tbaa !13
  %46 = load ptr, ptr %43, align 8, !tbaa !12
  %47 = getelementptr inbounds i8, ptr %46, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %47, align 8, !tbaa !16
  %48 = load ptr, ptr %43, align 8, !tbaa !12
  %49 = getelementptr inbounds i8, ptr %48, i64 104
  store ptr @TIM_DMAError, ptr %49, align 8, !tbaa !17
  %50 = load ptr, ptr %43, align 8, !tbaa !12
  %51 = load ptr, ptr %0, align 8, !tbaa !18
  %52 = getelementptr inbounds i8, ptr %51, i64 56
  %53 = ptrtoint ptr %52 to i64
  %54 = trunc i64 %53 to i32
  %55 = ptrtoint ptr %3 to i64
  %56 = trunc i64 %55 to i32
  %57 = zext i16 %4 to i32
  %58 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %50, i32 noundef %54, i32 noundef %56, i32 noundef %57) #2
  %.not51 = icmp eq i32 %58, 0
  br i1 %.not51, label %59, label %110

59:                                               ; preds = %42
  %60 = load ptr, ptr %0, align 8, !tbaa !18
  %61 = getelementptr inbounds i8, ptr %60, i64 12
  %62 = load volatile i32, ptr %61, align 4, !tbaa !19
  %63 = or i32 %62, 1024
  store volatile i32 %63, ptr %61, align 4, !tbaa !19
  %64 = load volatile i32, ptr %60, align 4, !tbaa !21
  %65 = or i32 %64, 1
  store volatile i32 %65, ptr %60, align 4, !tbaa !21
  tail call void @TIM_CCxChannelCmd(ptr noundef nonnull %60, i32 noundef 4, i32 noundef 1)
  br label %110

66:                                               ; preds = %17
  %67 = getelementptr inbounds i8, ptr %0, i64 48
  %68 = load ptr, ptr %67, align 8, !tbaa !12
  %69 = getelementptr inbounds i8, ptr %68, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %69, align 8, !tbaa !13
  %70 = load ptr, ptr %67, align 8, !tbaa !12
  %71 = getelementptr inbounds i8, ptr %70, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %71, align 8, !tbaa !16
  %72 = load ptr, ptr %67, align 8, !tbaa !12
  %73 = getelementptr inbounds i8, ptr %72, i64 104
  store ptr @TIM_DMAError, ptr %73, align 8, !tbaa !17
  %74 = load ptr, ptr %67, align 8, !tbaa !12
  %75 = load ptr, ptr %0, align 8, !tbaa !18
  %76 = getelementptr inbounds i8, ptr %75, i64 52
  %77 = ptrtoint ptr %76 to i64
  %78 = trunc i64 %77 to i32
  %79 = ptrtoint ptr %2 to i64
  %80 = trunc i64 %79 to i32
  %81 = zext i16 %4 to i32
  %82 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %74, i32 noundef %78, i32 noundef %80, i32 noundef %81) #2
  %.not = icmp eq i32 %82, 0
  br i1 %.not, label %83, label %110

83:                                               ; preds = %66
  %84 = getelementptr inbounds i8, ptr %0, i64 56
  %85 = load ptr, ptr %84, align 8, !tbaa !12
  %86 = getelementptr inbounds i8, ptr %85, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %86, align 8, !tbaa !13
  %87 = load ptr, ptr %84, align 8, !tbaa !12
  %88 = getelementptr inbounds i8, ptr %87, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %88, align 8, !tbaa !16
  %89 = load ptr, ptr %84, align 8, !tbaa !12
  %90 = getelementptr inbounds i8, ptr %89, i64 104
  store ptr @TIM_DMAError, ptr %90, align 8, !tbaa !17
  %91 = load ptr, ptr %84, align 8, !tbaa !12
  %92 = load ptr, ptr %0, align 8, !tbaa !18
  %93 = getelementptr inbounds i8, ptr %92, i64 56
  %94 = ptrtoint ptr %93 to i64
  %95 = trunc i64 %94 to i32
  %96 = ptrtoint ptr %3 to i64
  %97 = trunc i64 %96 to i32
  %98 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %91, i32 noundef %95, i32 noundef %97, i32 noundef %81) #2
  %.not50 = icmp eq i32 %98, 0
  br i1 %.not50, label %99, label %110

99:                                               ; preds = %83
  %100 = load ptr, ptr %0, align 8, !tbaa !18
  %101 = load volatile i32, ptr %100, align 4, !tbaa !21
  %102 = or i32 %101, 1
  store volatile i32 %102, ptr %100, align 4, !tbaa !21
  tail call void @TIM_CCxChannelCmd(ptr noundef nonnull %100, i32 noundef 0, i32 noundef 1)
  %103 = load ptr, ptr %0, align 8, !tbaa !18
  tail call void @TIM_CCxChannelCmd(ptr noundef %103, i32 noundef 4, i32 noundef 1)
  %104 = load ptr, ptr %0, align 8, !tbaa !18
  %105 = getelementptr inbounds i8, ptr %104, i64 12
  %106 = load volatile i32, ptr %105, align 4, !tbaa !19
  %107 = or i32 %106, 512
  store volatile i32 %107, ptr %105, align 4, !tbaa !19
  %108 = load volatile i32, ptr %105, align 4, !tbaa !19
  %109 = or i32 %108, 1024
  store volatile i32 %109, ptr %105, align 4, !tbaa !19
  br label %110

110:                                              ; preds = %35, %59, %99, %17, %83, %66, %42, %18, %12, %5
  %.0 = phi i32 [ 2, %5 ], [ 1, %12 ], [ 1, %18 ], [ 1, %42 ], [ 1, %66 ], [ 1, %83 ], [ 0, %17 ], [ 0, %99 ], [ 0, %59 ], [ 0, %35 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 100}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!7, !7, i64 0}
!13 = !{!14, !7, i64 72}
!14 = !{!"__DMA_HandleTypeDef", !7, i64 0, !15, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!16 = !{!14, !7, i64 80}
!17 = !{!14, !7, i64 104}
!18 = !{!6, !7, i64 0}
!19 = !{!20, !11, i64 12}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!21 = !{!20, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass