; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (SendCommand)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SDRAM_HandleTypeDef = type { ptr, %struct.FMC_SDRAM_InitTypeDef, i32, i32, ptr }
%struct.FMC_SDRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.FMC_SDRAM_CommandTypeDef = type { i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SDRAM_SendCommand(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.SDRAM_HandleTypeDef, ptr %10, i32 0, i32 2
  %12 = load volatile i32, ptr %11, align 8, !tbaa !11
  store i32 %12, ptr %8, align 4, !tbaa !9
  %13 = load i32, ptr %8, align 4, !tbaa !9
  %14 = icmp eq i32 %13, 2
  br i1 %14, label %15, label %16

15:                                               ; preds = %3
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

16:                                               ; preds = %3
  %17 = load i32, ptr %8, align 4, !tbaa !9
  %18 = icmp eq i32 %17, 1
  br i1 %18, label %22, label %19

19:                                               ; preds = %16
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = icmp eq i32 %20, 5
  br i1 %21, label %22, label %42

22:                                               ; preds = %19, %16
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.SDRAM_HandleTypeDef, ptr %23, i32 0, i32 2
  store volatile i32 2, ptr %24, align 8, !tbaa !11
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.SDRAM_HandleTypeDef, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !14
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = load i32, ptr %7, align 4, !tbaa !9
  %30 = call i32 @FMC_SDRAM_SendCommand(ptr noundef %27, ptr noundef %28, i32 noundef %29)
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.FMC_SDRAM_CommandTypeDef, ptr %31, i32 0, i32 0
  %33 = load i32, ptr %32, align 4, !tbaa !15
  %34 = icmp eq i32 %33, 2
  br i1 %34, label %35, label %38

35:                                               ; preds = %22
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.SDRAM_HandleTypeDef, ptr %36, i32 0, i32 2
  store volatile i32 5, ptr %37, align 8, !tbaa !11
  br label %41

38:                                               ; preds = %22
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.SDRAM_HandleTypeDef, ptr %39, i32 0, i32 2
  store volatile i32 1, ptr %40, align 8, !tbaa !11
  br label %41

41:                                               ; preds = %38, %35
  br label %43

42:                                               ; preds = %19
  store i32 1, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

43:                                               ; preds = %41
  br label %44

44:                                               ; preds = %43
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

45:                                               ; preds = %44, %42, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %46 = load i32, ptr %4, align 4
  ret i32 %46
}

declare i32 @FMC_SDRAM_SendCommand(ptr noundef, ptr noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 48}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 48, !10, i64 52, !6, i64 56}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36}
!14 = !{!12, !6, i64 0}
!15 = !{!16, !10, i64 0}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SDRAM_SendCommand(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 48
  %5 = load volatile i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 2
  br i1 %6, label %13, label %7

7:                                                ; preds = %3
  %8 = and i32 %5, -5
  %or.cond = icmp eq i32 %8, 1
  br i1 %or.cond, label %.sink.split, label %13

.sink.split:                                      ; preds = %7
  store volatile i32 2, ptr %4, align 8, !tbaa !5
  %9 = load ptr, ptr %0, align 8, !tbaa !12
  %10 = tail call i32 @FMC_SDRAM_SendCommand(ptr noundef %9, ptr noundef %1, i32 noundef %2) #2
  %11 = load i32, ptr %1, align 4, !tbaa !13
  %12 = icmp eq i32 %11, 2
  %. = select i1 %12, i32 5, i32 1
  store volatile i32 %., ptr %4, align 8, !tbaa !5
  br label %13

13:                                               ; preds = %.sink.split, %7, %3
  %.0 = phi i32 [ 2, %3 ], [ 1, %7 ], [ 0, %.sink.split ]
  ret i32 %.0
}

declare i32 @FMC_SDRAM_SendCommand(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 48}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 48, !11, i64 52, !7, i64 56}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!14, !11, i64 0}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass