; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__I2S_HandleTypeDef = type { ptr, %struct.I2S_InitTypeDef, ptr, i16, i16, ptr, i16, i16, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.I2S_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_I2S_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  %8 = load ptr, ptr %6, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %14, label %10

10:                                               ; preds = %3
  %11 = load i16, ptr %7, align 2, !tbaa !9
  %12 = zext i16 %11 to i64
  %13 = icmp eq i64 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %10, %3
  store i32 1, ptr %4, align 4
  br label %148

15:                                               ; preds = %10
  br label %16

16:                                               ; preds = %15
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %17, i32 0, i32 12
  %19 = load volatile i32, ptr %18, align 8, !tbaa !11
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  store i32 2, ptr %4, align 4
  br label %148

22:                                               ; preds = %16
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %23, i32 0, i32 12
  store volatile i32 1, ptr %24, align 8, !tbaa !11
  br label %25

25:                                               ; preds = %22
  br label %26

26:                                               ; preds = %25
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %27, i32 0, i32 13
  %29 = load volatile i32, ptr %28, align 4, !tbaa !15
  %30 = icmp ne i32 %29, 1
  br i1 %30, label %31, label %36

31:                                               ; preds = %26
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %33, i32 0, i32 12
  store volatile i32 0, ptr %34, align 8, !tbaa !11
  br label %35

35:                                               ; preds = %32
  store i32 2, ptr %4, align 4
  br label %148

36:                                               ; preds = %26
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %37, i32 0, i32 13
  store volatile i32 3, ptr %38, align 4, !tbaa !15
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %39, i32 0, i32 14
  store volatile i32 0, ptr %40, align 8, !tbaa !16
  %41 = load ptr, ptr %6, align 8, !tbaa !5
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %42, i32 0, i32 2
  store ptr %41, ptr %43, align 8, !tbaa !17
  %44 = load i16, ptr %7, align 2, !tbaa !9
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %45, i32 0, i32 3
  store volatile i16 %44, ptr %46, align 8, !tbaa !18
  %47 = load i16, ptr %7, align 2, !tbaa !9
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %48, i32 0, i32 4
  store volatile i16 %47, ptr %49, align 2, !tbaa !19
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %50, i32 0, i32 5
  store ptr null, ptr %51, align 8, !tbaa !20
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %52, i32 0, i32 6
  store volatile i16 0, ptr %53, align 8, !tbaa !21
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %54, i32 0, i32 7
  store volatile i16 0, ptr %55, align 2, !tbaa !22
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %56, i32 0, i32 10
  %58 = load ptr, ptr %57, align 8, !tbaa !23
  %59 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %58, i32 0, i32 6
  store ptr @I2S_DMATxHalfCplt, ptr %59, align 8, !tbaa !24
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %60, i32 0, i32 10
  %62 = load ptr, ptr %61, align 8, !tbaa !23
  %63 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %62, i32 0, i32 5
  store ptr @I2S_DMATxCplt, ptr %63, align 8, !tbaa !27
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %64, i32 0, i32 10
  %66 = load ptr, ptr %65, align 8, !tbaa !23
  %67 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %66, i32 0, i32 9
  store ptr @I2S_DMAError, ptr %67, align 8, !tbaa !28
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %68, i32 0, i32 10
  %70 = load ptr, ptr %69, align 8, !tbaa !23
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %71, i32 0, i32 2
  %73 = load ptr, ptr %72, align 8, !tbaa !17
  %74 = ptrtoint ptr %73 to i32
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %75, i32 0, i32 0
  %77 = load ptr, ptr %76, align 8, !tbaa !29
  %78 = getelementptr inbounds %struct.SPI_TypeDef, ptr %77, i32 0, i32 8
  %79 = ptrtoint ptr %78 to i32
  %80 = load ptr, ptr %5, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %80, i32 0, i32 3
  %82 = load volatile i16, ptr %81, align 8, !tbaa !18
  %83 = zext i16 %82 to i32
  %84 = call i32 @HAL_DMA_Start_IT(ptr noundef %70, i32 noundef %74, i32 noundef %79, i32 noundef %83)
  %85 = icmp ne i32 0, %84
  br i1 %85, label %86, label %99

86:                                               ; preds = %36
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %87, i32 0, i32 14
  %89 = load volatile i32, ptr %88, align 8, !tbaa !16
  %90 = zext i32 %89 to i64
  %91 = or i64 %90, 8
  %92 = trunc i64 %91 to i32
  store volatile i32 %92, ptr %88, align 8, !tbaa !16
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %93, i32 0, i32 13
  store volatile i32 1, ptr %94, align 4, !tbaa !15
  br label %95

95:                                               ; preds = %86
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %96, i32 0, i32 12
  store volatile i32 0, ptr %97, align 8, !tbaa !11
  br label %98

98:                                               ; preds = %95
  store i32 1, ptr %4, align 4
  br label %148

99:                                               ; preds = %36
  %100 = load ptr, ptr %5, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %100, i32 0, i32 0
  %102 = load ptr, ptr %101, align 8, !tbaa !29
  %103 = getelementptr inbounds %struct.SPI_TypeDef, ptr %102, i32 0, i32 2
  %104 = load volatile i32, ptr %103, align 4, !tbaa !30
  %105 = zext i32 %104 to i64
  %106 = and i64 %105, 32768
  %107 = icmp eq i64 %106, 0
  br i1 %107, label %108, label %117

108:                                              ; preds = %99
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %109, i32 0, i32 0
  %111 = load ptr, ptr %110, align 8, !tbaa !29
  %112 = getelementptr inbounds %struct.SPI_TypeDef, ptr %111, i32 0, i32 2
  %113 = load volatile i32, ptr %112, align 4, !tbaa !30
  %114 = zext i32 %113 to i64
  %115 = or i64 %114, 32768
  %116 = trunc i64 %115 to i32
  store volatile i32 %116, ptr %112, align 4, !tbaa !30
  br label %117

117:                                              ; preds = %108, %99
  %118 = load ptr, ptr %5, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %118, i32 0, i32 0
  %120 = load ptr, ptr %119, align 8, !tbaa !29
  %121 = getelementptr inbounds %struct.SPI_TypeDef, ptr %120, i32 0, i32 0
  %122 = load volatile i32, ptr %121, align 4, !tbaa !32
  %123 = zext i32 %122 to i64
  %124 = and i64 %123, 1
  %125 = icmp eq i64 %124, 0
  br i1 %125, label %126, label %135

126:                                              ; preds = %117
  %127 = load ptr, ptr %5, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %127, i32 0, i32 0
  %129 = load ptr, ptr %128, align 8, !tbaa !29
  %130 = getelementptr inbounds %struct.SPI_TypeDef, ptr %129, i32 0, i32 0
  %131 = load volatile i32, ptr %130, align 4, !tbaa !32
  %132 = zext i32 %131 to i64
  %133 = or i64 %132, 1
  %134 = trunc i64 %133 to i32
  store volatile i32 %134, ptr %130, align 4, !tbaa !32
  br label %135

135:                                              ; preds = %126, %117
  %136 = load ptr, ptr %5, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %136, i32 0, i32 0
  %138 = load ptr, ptr %137, align 8, !tbaa !29
  %139 = getelementptr inbounds %struct.SPI_TypeDef, ptr %138, i32 0, i32 0
  %140 = load volatile i32, ptr %139, align 4, !tbaa !32
  %141 = zext i32 %140 to i64
  %142 = or i64 %141, 512
  %143 = trunc i64 %142 to i32
  store volatile i32 %143, ptr %139, align 4, !tbaa !32
  br label %144

144:                                              ; preds = %135
  %145 = load ptr, ptr %5, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.__I2S_HandleTypeDef, ptr %145, i32 0, i32 12
  store volatile i32 0, ptr %146, align 8, !tbaa !11
  br label %147

147:                                              ; preds = %144
  store i32 0, ptr %4, align 4
  br label %148

148:                                              ; preds = %147, %98, %35, %21, %14
  %149 = load i32, ptr %4, align 4
  ret i32 %149
}

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMATxHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMATxCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 112}
!12 = !{!"__I2S_HandleTypeDef", !6, i64 0, !13, i64 8, !6, i64 48, !10, i64 56, !10, i64 58, !6, i64 64, !10, i64 72, !10, i64 74, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !14, i64 112, !14, i64 116, !14, i64 120}
!13 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36}
!14 = !{!"int", !7, i64 0}
!15 = !{!12, !14, i64 116}
!16 = !{!12, !14, i64 120}
!17 = !{!12, !6, i64 48}
!18 = !{!12, !10, i64 56}
!19 = !{!12, !10, i64 58}
!20 = !{!12, !6, i64 64}
!21 = !{!12, !10, i64 72}
!22 = !{!12, !10, i64 74}
!23 = !{!12, !6, i64 96}
!24 = !{!25, !6, i64 80}
!25 = !{!"__DMA_HandleTypeDef", !6, i64 0, !26, i64 8, !14, i64 56, !14, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !6, i64 136, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !14, i64 176}
!26 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44}
!27 = !{!25, !6, i64 72}
!28 = !{!25, !6, i64 104}
!29 = !{!12, !6, i64 0}
!30 = !{!31, !14, i64 8}
!31 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !7, i64 36, !14, i64 48, !7, i64 52, !14, i64 64, !14, i64 68, !14, i64 72, !14, i64 76, !14, i64 80}
!32 = !{!31, !14, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_I2S_Transmit_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %1, null
  %5 = icmp eq i16 %2, 0
  %or.cond = or i1 %4, %5
  br i1 %or.cond, label %57, label %6

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 112
  %8 = load volatile i32, ptr %7, align 8, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %57, label %10

10:                                               ; preds = %6
  store volatile i32 1, ptr %7, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %0, i64 116
  %12 = load volatile i32, ptr %11, align 4, !tbaa !13
  %.not = icmp eq i32 %12, 1
  br i1 %.not, label %13, label %.sink.split

13:                                               ; preds = %10
  store volatile i32 3, ptr %11, align 4, !tbaa !13
  %14 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 0, ptr %14, align 8, !tbaa !14
  %15 = getelementptr inbounds i8, ptr %0, i64 48
  store ptr %1, ptr %15, align 8, !tbaa !15
  %16 = getelementptr inbounds i8, ptr %0, i64 56
  store volatile i16 %2, ptr %16, align 8, !tbaa !16
  %17 = getelementptr inbounds i8, ptr %0, i64 58
  store volatile i16 %2, ptr %17, align 2, !tbaa !17
  %18 = getelementptr inbounds i8, ptr %0, i64 64
  store ptr null, ptr %18, align 8, !tbaa !18
  %19 = getelementptr inbounds i8, ptr %0, i64 72
  store volatile i16 0, ptr %19, align 8, !tbaa !19
  %20 = getelementptr inbounds i8, ptr %0, i64 74
  store volatile i16 0, ptr %20, align 2, !tbaa !20
  %21 = getelementptr inbounds i8, ptr %0, i64 96
  %22 = load ptr, ptr %21, align 8, !tbaa !21
  %23 = getelementptr inbounds i8, ptr %22, i64 80
  store ptr @I2S_DMATxHalfCplt, ptr %23, align 8, !tbaa !22
  %24 = getelementptr inbounds i8, ptr %22, i64 72
  store ptr @I2S_DMATxCplt, ptr %24, align 8, !tbaa !25
  %25 = getelementptr inbounds i8, ptr %22, i64 104
  store ptr @I2S_DMAError, ptr %25, align 8, !tbaa !26
  %26 = ptrtoint ptr %1 to i64
  %27 = trunc i64 %26 to i32
  %28 = load ptr, ptr %0, align 8, !tbaa !27
  %29 = getelementptr inbounds i8, ptr %28, i64 32
  %30 = ptrtoint ptr %29 to i64
  %31 = trunc i64 %30 to i32
  %32 = load volatile i16, ptr %16, align 8, !tbaa !16
  %33 = zext i16 %32 to i32
  %34 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %22, i32 noundef %27, i32 noundef %31, i32 noundef %33) #2
  %.not36 = icmp eq i32 %34, 0
  br i1 %.not36, label %38, label %35

35:                                               ; preds = %13
  %36 = load volatile i32, ptr %14, align 8, !tbaa !14
  %37 = or i32 %36, 8
  store volatile i32 %37, ptr %14, align 8, !tbaa !14
  store volatile i32 1, ptr %11, align 4, !tbaa !13
  br label %.sink.split

38:                                               ; preds = %13
  %39 = load ptr, ptr %0, align 8, !tbaa !27
  %40 = getelementptr inbounds i8, ptr %39, i64 8
  %41 = load volatile i32, ptr %40, align 4, !tbaa !28
  %42 = and i32 %41, 32768
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %47

44:                                               ; preds = %38
  %45 = load volatile i32, ptr %40, align 4, !tbaa !28
  %46 = or i32 %45, 32768
  store volatile i32 %46, ptr %40, align 4, !tbaa !28
  br label %47

47:                                               ; preds = %44, %38
  %48 = load volatile i32, ptr %39, align 4, !tbaa !30
  %49 = and i32 %48, 1
  %50 = icmp eq i32 %49, 0
  br i1 %50, label %51, label %54

51:                                               ; preds = %47
  %52 = load volatile i32, ptr %39, align 4, !tbaa !30
  %53 = or i32 %52, 1
  store volatile i32 %53, ptr %39, align 4, !tbaa !30
  br label %54

54:                                               ; preds = %51, %47
  %55 = load volatile i32, ptr %39, align 4, !tbaa !30
  %56 = or i32 %55, 512
  store volatile i32 %56, ptr %39, align 4, !tbaa !30
  br label %.sink.split

.sink.split:                                      ; preds = %10, %35, %54
  %.0.ph = phi i32 [ 0, %54 ], [ 1, %35 ], [ 2, %10 ]
  store volatile i32 0, ptr %7, align 8, !tbaa !5
  br label %57

57:                                               ; preds = %.sink.split, %6, %3
  %.0 = phi i32 [ 1, %3 ], [ 2, %6 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMATxHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMATxCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @I2S_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 112}
!6 = !{!"__I2S_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 48, !12, i64 56, !12, i64 58, !7, i64 64, !12, i64 72, !12, i64 74, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !11, i64 112, !11, i64 116, !11, i64 120}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 116}
!14 = !{!6, !11, i64 120}
!15 = !{!6, !7, i64 48}
!16 = !{!6, !12, i64 56}
!17 = !{!6, !12, i64 58}
!18 = !{!6, !7, i64 64}
!19 = !{!6, !12, i64 72}
!20 = !{!6, !12, i64 74}
!21 = !{!6, !7, i64 96}
!22 = !{!23, !7, i64 80}
!23 = !{!"__DMA_HandleTypeDef", !7, i64 0, !24, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!25 = !{!23, !7, i64 72}
!26 = !{!23, !7, i64 104}
!27 = !{!6, !7, i64 0}
!28 = !{!29, !11, i64 8}
!29 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!30 = !{!29, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass