; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Read_SpareArea_16b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #4
  %19 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %19, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %20, ptr %17, align 8, !tbaa !5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load volatile i32, ptr %22, align 8, !tbaa !11
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %26

25:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %306

26:                                               ; preds = %4
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %27, i32 0, i32 3
  %29 = load volatile i32, ptr %28, align 8, !tbaa !11
  %30 = icmp eq i32 %29, 1
  br i1 %30, label %31, label %303

31:                                               ; preds = %26
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %33, i32 0, i32 2
  %35 = load i32, ptr %34, align 4, !tbaa !14
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %306

38:                                               ; preds = %32
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %39, i32 0, i32 2
  store i32 1, ptr %40, align 4, !tbaa !14
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %44, i32 0, i32 3
  store volatile i32 2, ptr %45, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %46 = load ptr, ptr %7, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %46, i32 0, i32 0
  %48 = load i16, ptr %47, align 2, !tbaa !15
  %49 = zext i16 %48 to i32
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %50, i32 0, i32 2
  %52 = load i16, ptr %51, align 2, !tbaa !18
  %53 = zext i16 %52 to i32
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %54, i32 0, i32 1
  %56 = load i16, ptr %55, align 2, !tbaa !19
  %57 = zext i16 %56 to i32
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %58, i32 0, i32 4
  %60 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %59, i32 0, i32 5
  %61 = load i32, ptr %60, align 4, !tbaa !20
  %62 = mul i32 %57, %61
  %63 = add i32 %53, %62
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %64, i32 0, i32 4
  %66 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %65, i32 0, i32 2
  %67 = load i32, ptr %66, align 4, !tbaa !21
  %68 = mul i32 %63, %67
  %69 = add i32 %49, %68
  store i32 %69, ptr %14, align 4, !tbaa !9
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %70, i32 0, i32 4
  %72 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 4, !tbaa !22
  %74 = mul i32 %73, 2
  store i32 %74, ptr %15, align 4, !tbaa !9
  br label %75

75:                                               ; preds = %288, %43
  %76 = load i32, ptr %16, align 4, !tbaa !9
  %77 = icmp ne i32 %76, 0
  br i1 %77, label %78, label %90

78:                                               ; preds = %75
  %79 = load i32, ptr %14, align 4, !tbaa !9
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %80, i32 0, i32 4
  %82 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %81, i32 0, i32 2
  %83 = load i32, ptr %82, align 4, !tbaa !21
  %84 = load ptr, ptr %6, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %84, i32 0, i32 4
  %86 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %85, i32 0, i32 3
  %87 = load i32, ptr %86, align 4, !tbaa !23
  %88 = mul i32 %83, %87
  %89 = icmp ult i32 %79, %88
  br label %90

90:                                               ; preds = %78, %75
  %91 = phi i1 [ false, %75 ], [ %89, %78 ]
  br i1 %91, label %92, label %295

92:                                               ; preds = %90
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %93, i32 0, i32 4
  %95 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %94, i32 0, i32 0
  %96 = load i32, ptr %95, align 4, !tbaa !22
  %97 = icmp ule i32 %96, 512
  br i1 %97, label %98, label %157

98:                                               ; preds = %92
  %99 = load i32, ptr %12, align 4, !tbaa !9
  %100 = or i32 %99, 65536
  %101 = zext i32 %100 to i64
  %102 = inttoptr i64 %101 to ptr
  store volatile i8 80, ptr %102, align 1, !tbaa !24
  call void @__DSB()
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %103, i32 0, i32 4
  %105 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %104, i32 0, i32 2
  %106 = load i32, ptr %105, align 4, !tbaa !21
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %107, i32 0, i32 4
  %109 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %108, i32 0, i32 3
  %110 = load i32, ptr %109, align 4, !tbaa !23
  %111 = mul i32 %106, %110
  %112 = icmp ule i32 %111, 65535
  br i1 %112, label %113, label %131

113:                                              ; preds = %98
  %114 = load i32, ptr %12, align 4, !tbaa !9
  %115 = or i32 %114, 131072
  %116 = zext i32 %115 to i64
  %117 = inttoptr i64 %116 to ptr
  store volatile i8 0, ptr %117, align 1, !tbaa !24
  call void @__DSB()
  %118 = load i32, ptr %14, align 4, !tbaa !9
  %119 = trunc i32 %118 to i8
  %120 = load i32, ptr %12, align 4, !tbaa !9
  %121 = or i32 %120, 131072
  %122 = zext i32 %121 to i64
  %123 = inttoptr i64 %122 to ptr
  store volatile i8 %119, ptr %123, align 1, !tbaa !24
  call void @__DSB()
  %124 = load i32, ptr %14, align 4, !tbaa !9
  %125 = lshr i32 %124, 8
  %126 = trunc i32 %125 to i8
  %127 = load i32, ptr %12, align 4, !tbaa !9
  %128 = or i32 %127, 131072
  %129 = zext i32 %128 to i64
  %130 = inttoptr i64 %129 to ptr
  store volatile i8 %126, ptr %130, align 1, !tbaa !24
  call void @__DSB()
  br label %156

131:                                              ; preds = %98
  %132 = load i32, ptr %12, align 4, !tbaa !9
  %133 = or i32 %132, 131072
  %134 = zext i32 %133 to i64
  %135 = inttoptr i64 %134 to ptr
  store volatile i8 0, ptr %135, align 1, !tbaa !24
  call void @__DSB()
  %136 = load i32, ptr %14, align 4, !tbaa !9
  %137 = trunc i32 %136 to i8
  %138 = load i32, ptr %12, align 4, !tbaa !9
  %139 = or i32 %138, 131072
  %140 = zext i32 %139 to i64
  %141 = inttoptr i64 %140 to ptr
  store volatile i8 %137, ptr %141, align 1, !tbaa !24
  call void @__DSB()
  %142 = load i32, ptr %14, align 4, !tbaa !9
  %143 = lshr i32 %142, 8
  %144 = trunc i32 %143 to i8
  %145 = load i32, ptr %12, align 4, !tbaa !9
  %146 = or i32 %145, 131072
  %147 = zext i32 %146 to i64
  %148 = inttoptr i64 %147 to ptr
  store volatile i8 %144, ptr %148, align 1, !tbaa !24
  call void @__DSB()
  %149 = load i32, ptr %14, align 4, !tbaa !9
  %150 = lshr i32 %149, 16
  %151 = trunc i32 %150 to i8
  %152 = load i32, ptr %12, align 4, !tbaa !9
  %153 = or i32 %152, 131072
  %154 = zext i32 %153 to i64
  %155 = inttoptr i64 %154 to ptr
  store volatile i8 %151, ptr %155, align 1, !tbaa !24
  call void @__DSB()
  br label %156

156:                                              ; preds = %131, %113
  br label %234

157:                                              ; preds = %92
  %158 = load i32, ptr %12, align 4, !tbaa !9
  %159 = or i32 %158, 65536
  %160 = zext i32 %159 to i64
  %161 = inttoptr i64 %160 to ptr
  store volatile i8 0, ptr %161, align 1, !tbaa !24
  call void @__DSB()
  %162 = load ptr, ptr %6, align 8, !tbaa !5
  %163 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %162, i32 0, i32 4
  %164 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %163, i32 0, i32 2
  %165 = load i32, ptr %164, align 4, !tbaa !21
  %166 = load ptr, ptr %6, align 8, !tbaa !5
  %167 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %166, i32 0, i32 4
  %168 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %167, i32 0, i32 3
  %169 = load i32, ptr %168, align 4, !tbaa !23
  %170 = mul i32 %165, %169
  %171 = icmp ule i32 %170, 65535
  br i1 %171, label %172, label %199

172:                                              ; preds = %157
  %173 = load i32, ptr %15, align 4, !tbaa !9
  %174 = trunc i32 %173 to i8
  %175 = load i32, ptr %12, align 4, !tbaa !9
  %176 = or i32 %175, 131072
  %177 = zext i32 %176 to i64
  %178 = inttoptr i64 %177 to ptr
  store volatile i8 %174, ptr %178, align 1, !tbaa !24
  call void @__DSB()
  %179 = load i32, ptr %15, align 4, !tbaa !9
  %180 = lshr i32 %179, 8
  %181 = trunc i32 %180 to i8
  %182 = load i32, ptr %12, align 4, !tbaa !9
  %183 = or i32 %182, 131072
  %184 = zext i32 %183 to i64
  %185 = inttoptr i64 %184 to ptr
  store volatile i8 %181, ptr %185, align 1, !tbaa !24
  call void @__DSB()
  %186 = load i32, ptr %14, align 4, !tbaa !9
  %187 = trunc i32 %186 to i8
  %188 = load i32, ptr %12, align 4, !tbaa !9
  %189 = or i32 %188, 131072
  %190 = zext i32 %189 to i64
  %191 = inttoptr i64 %190 to ptr
  store volatile i8 %187, ptr %191, align 1, !tbaa !24
  call void @__DSB()
  %192 = load i32, ptr %14, align 4, !tbaa !9
  %193 = lshr i32 %192, 8
  %194 = trunc i32 %193 to i8
  %195 = load i32, ptr %12, align 4, !tbaa !9
  %196 = or i32 %195, 131072
  %197 = zext i32 %196 to i64
  %198 = inttoptr i64 %197 to ptr
  store volatile i8 %194, ptr %198, align 1, !tbaa !24
  call void @__DSB()
  br label %233

199:                                              ; preds = %157
  %200 = load i32, ptr %15, align 4, !tbaa !9
  %201 = trunc i32 %200 to i8
  %202 = load i32, ptr %12, align 4, !tbaa !9
  %203 = or i32 %202, 131072
  %204 = zext i32 %203 to i64
  %205 = inttoptr i64 %204 to ptr
  store volatile i8 %201, ptr %205, align 1, !tbaa !24
  call void @__DSB()
  %206 = load i32, ptr %15, align 4, !tbaa !9
  %207 = lshr i32 %206, 8
  %208 = trunc i32 %207 to i8
  %209 = load i32, ptr %12, align 4, !tbaa !9
  %210 = or i32 %209, 131072
  %211 = zext i32 %210 to i64
  %212 = inttoptr i64 %211 to ptr
  store volatile i8 %208, ptr %212, align 1, !tbaa !24
  call void @__DSB()
  %213 = load i32, ptr %14, align 4, !tbaa !9
  %214 = trunc i32 %213 to i8
  %215 = load i32, ptr %12, align 4, !tbaa !9
  %216 = or i32 %215, 131072
  %217 = zext i32 %216 to i64
  %218 = inttoptr i64 %217 to ptr
  store volatile i8 %214, ptr %218, align 1, !tbaa !24
  call void @__DSB()
  %219 = load i32, ptr %14, align 4, !tbaa !9
  %220 = lshr i32 %219, 8
  %221 = trunc i32 %220 to i8
  %222 = load i32, ptr %12, align 4, !tbaa !9
  %223 = or i32 %222, 131072
  %224 = zext i32 %223 to i64
  %225 = inttoptr i64 %224 to ptr
  store volatile i8 %221, ptr %225, align 1, !tbaa !24
  call void @__DSB()
  %226 = load i32, ptr %14, align 4, !tbaa !9
  %227 = lshr i32 %226, 16
  %228 = trunc i32 %227 to i8
  %229 = load i32, ptr %12, align 4, !tbaa !9
  %230 = or i32 %229, 131072
  %231 = zext i32 %230 to i64
  %232 = inttoptr i64 %231 to ptr
  store volatile i8 %228, ptr %232, align 1, !tbaa !24
  call void @__DSB()
  br label %233

233:                                              ; preds = %199, %172
  br label %234

234:                                              ; preds = %233, %156
  %235 = load i32, ptr %12, align 4, !tbaa !9
  %236 = or i32 %235, 65536
  %237 = zext i32 %236 to i64
  %238 = inttoptr i64 %237 to ptr
  store volatile i8 48, ptr %238, align 1, !tbaa !24
  call void @__DSB()
  %239 = load ptr, ptr %6, align 8, !tbaa !5
  %240 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %239, i32 0, i32 4
  %241 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %240, i32 0, i32 6
  %242 = load i32, ptr %241, align 4, !tbaa !25
  %243 = icmp eq i32 %242, 1
  br i1 %243, label %244, label %269

244:                                              ; preds = %234
  %245 = call i32 @HAL_GetTick()
  store i32 %245, ptr %11, align 4, !tbaa !9
  br label %246

246:                                              ; preds = %263, %244
  %247 = load ptr, ptr %6, align 8, !tbaa !5
  %248 = call i32 @HAL_NAND_Read_Status(ptr noundef %247)
  %249 = icmp ne i32 %248, 64
  br i1 %249, label %250, label %264

250:                                              ; preds = %246
  %251 = call i32 @HAL_GetTick()
  %252 = load i32, ptr %11, align 4, !tbaa !9
  %253 = sub i32 %251, %252
  %254 = icmp ugt i32 %253, 16777216
  br i1 %254, label %255, label %263

255:                                              ; preds = %250
  %256 = load ptr, ptr %6, align 8, !tbaa !5
  %257 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %256, i32 0, i32 3
  store volatile i32 3, ptr %257, align 8, !tbaa !11
  br label %258

258:                                              ; preds = %255
  %259 = load ptr, ptr %6, align 8, !tbaa !5
  %260 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %259, i32 0, i32 2
  store i32 0, ptr %260, align 4, !tbaa !14
  br label %261

261:                                              ; preds = %258
  br label %262

262:                                              ; preds = %261
  store i32 3, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %306

263:                                              ; preds = %250
  br label %246, !llvm.loop !26

264:                                              ; preds = %246
  %265 = load i32, ptr %12, align 4, !tbaa !9
  %266 = or i32 %265, 65536
  %267 = zext i32 %266 to i64
  %268 = inttoptr i64 %267 to ptr
  store volatile i8 0, ptr %268, align 1, !tbaa !24
  call void @__DSB()
  br label %269

269:                                              ; preds = %264, %234
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %270

270:                                              ; preds = %285, %269
  %271 = load i32, ptr %10, align 4, !tbaa !9
  %272 = load ptr, ptr %6, align 8, !tbaa !5
  %273 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %272, i32 0, i32 4
  %274 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %273, i32 0, i32 1
  %275 = load i32, ptr %274, align 4, !tbaa !28
  %276 = icmp ult i32 %271, %275
  br i1 %276, label %277, label %288

277:                                              ; preds = %270
  %278 = load i32, ptr %12, align 4, !tbaa !9
  %279 = zext i32 %278 to i64
  %280 = inttoptr i64 %279 to ptr
  %281 = load i16, ptr %280, align 2, !tbaa !29
  %282 = load ptr, ptr %17, align 8, !tbaa !5
  store i16 %281, ptr %282, align 2, !tbaa !29
  %283 = load ptr, ptr %17, align 8, !tbaa !5
  %284 = getelementptr inbounds i16, ptr %283, i32 1
  store ptr %284, ptr %17, align 8, !tbaa !5
  br label %285

285:                                              ; preds = %277
  %286 = load i32, ptr %10, align 4, !tbaa !9
  %287 = add i32 %286, 1
  store i32 %287, ptr %10, align 4, !tbaa !9
  br label %270, !llvm.loop !30

288:                                              ; preds = %270
  %289 = load i32, ptr %13, align 4, !tbaa !9
  %290 = add i32 %289, 1
  store i32 %290, ptr %13, align 4, !tbaa !9
  %291 = load i32, ptr %16, align 4, !tbaa !9
  %292 = add i32 %291, -1
  store i32 %292, ptr %16, align 4, !tbaa !9
  %293 = load i32, ptr %14, align 4, !tbaa !9
  %294 = add i32 %293, 1
  store i32 %294, ptr %14, align 4, !tbaa !9
  br label %75, !llvm.loop !31

295:                                              ; preds = %90
  %296 = load ptr, ptr %6, align 8, !tbaa !5
  %297 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %296, i32 0, i32 3
  store volatile i32 1, ptr %297, align 8, !tbaa !11
  br label %298

298:                                              ; preds = %295
  %299 = load ptr, ptr %6, align 8, !tbaa !5
  %300 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %299, i32 0, i32 2
  store i32 0, ptr %300, align 4, !tbaa !14
  br label %301

301:                                              ; preds = %298
  br label %302

302:                                              ; preds = %301
  br label %304

303:                                              ; preds = %26
  store i32 1, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %306

304:                                              ; preds = %302
  br label %305

305:                                              ; preds = %304
  store i32 0, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %306

306:                                              ; preds = %305, %303, %262, %37, %25
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %307 = load i32, ptr %5, align 4
  ret i32 %307
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 44}
!23 = !{!12, !10, i64 56}
!24 = !{!7, !7, i64 0}
!25 = !{!12, !10, i64 68}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!12, !10, i64 48}
!29 = !{!17, !17, i64 0}
!30 = distinct !{!30, !27}
!31 = distinct !{!31, !27}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Read_SpareArea_16b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %89, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %89

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %89, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not80 = icmp eq i32 %3, 0
  br i1 %.not80, label %.sink.split89, label %.lr.ph85

.lr.ph85:                                         ; preds = %15
  %18 = load i32, ptr %16, align 4, !tbaa !13
  %19 = shl i32 %18, 1
  %20 = getelementptr inbounds i8, ptr %0, i64 64
  %21 = load i32, ptr %20, align 4, !tbaa !14
  %22 = getelementptr inbounds i8, ptr %1, i64 2
  %23 = load i16, ptr %22, align 2, !tbaa !15
  %24 = zext i16 %23 to i32
  %25 = mul i32 %21, %24
  %26 = getelementptr inbounds i8, ptr %1, i64 4
  %27 = load i16, ptr %26, align 2, !tbaa !18
  %28 = zext i16 %27 to i32
  %29 = add i32 %25, %28
  %30 = load i32, ptr %17, align 4, !tbaa !19
  %31 = mul i32 %29, %30
  %32 = load i16, ptr %1, align 2, !tbaa !20
  %33 = zext i16 %32 to i32
  %34 = add i32 %31, %33
  %35 = getelementptr inbounds i8, ptr %0, i64 56
  %36 = trunc i32 %19 to i8
  %37 = lshr i32 %19, 8
  %38 = trunc i32 %37 to i8
  %39 = getelementptr inbounds i8, ptr %0, i64 68
  %40 = getelementptr inbounds i8, ptr %0, i64 48
  br label %41

41:                                               ; preds = %.lr.ph85, %._crit_edge
  %.083 = phi ptr [ %2, %.lr.ph85 ], [ %.1.lcssa, %._crit_edge ]
  %.07282 = phi i32 [ %3, %.lr.ph85 ], [ %87, %._crit_edge ]
  %.07481 = phi i32 [ %34, %.lr.ph85 ], [ %88, %._crit_edge ]
  %42 = load i32, ptr %17, align 4, !tbaa !19
  %43 = load i32, ptr %35, align 4, !tbaa !21
  %44 = mul i32 %43, %42
  %45 = icmp ult i32 %.07481, %44
  br i1 %45, label %46, label %.sink.split89

46:                                               ; preds = %41
  %47 = load i32, ptr %16, align 4, !tbaa !13
  %48 = icmp ult i32 %47, 513
  br i1 %48, label %49, label %57

49:                                               ; preds = %46
  store volatile i8 80, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %50 = load i32, ptr %17, align 4, !tbaa !19
  %51 = load i32, ptr %35, align 4, !tbaa !21
  %52 = mul i32 %51, %50
  %53 = icmp ult i32 %52, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %54 = trunc i32 %.07481 to i8
  store volatile i8 %54, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %55 = lshr i32 %.07481, 8
  %56 = trunc i32 %55 to i8
  store volatile i8 %56, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %53, label %67, label %.sink.split

57:                                               ; preds = %46
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %58 = load i32, ptr %17, align 4, !tbaa !19
  %59 = load i32, ptr %35, align 4, !tbaa !21
  %60 = mul i32 %59, %58
  %61 = icmp ult i32 %60, 65536
  store volatile i8 %36, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  store volatile i8 %38, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %62 = trunc i32 %.07481 to i8
  store volatile i8 %62, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %63 = lshr i32 %.07481, 8
  %64 = trunc i32 %63 to i8
  store volatile i8 %64, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %61, label %67, label %.sink.split

.sink.split:                                      ; preds = %57, %49
  %65 = lshr i32 %.07481, 16
  %66 = trunc i32 %65 to i8
  store volatile i8 %66, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br label %67

67:                                               ; preds = %.sink.split, %57, %49
  store volatile i8 48, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %68 = load i32, ptr %39, align 4, !tbaa !23
  %69 = icmp eq i32 %68, 1
  br i1 %69, label %70, label %79

70:                                               ; preds = %67
  %71 = tail call i32 @HAL_GetTick() #3
  br label %72

72:                                               ; preds = %74, %70
  %73 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not77 = icmp eq i32 %73, 64
  br i1 %.not77, label %78, label %74

74:                                               ; preds = %72
  %75 = tail call i32 @HAL_GetTick() #3
  %76 = sub i32 %75, %71
  %77 = icmp ugt i32 %76, 16777216
  br i1 %77, label %.sink.split89, label %72, !llvm.loop !24

78:                                               ; preds = %72
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  br label %79

79:                                               ; preds = %78, %67
  %80 = load i32, ptr %40, align 4, !tbaa !26
  %.not87 = icmp eq i32 %80, 0
  br i1 %.not87, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %79
  %.pre = load i16, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !27
  %81 = zext i32 %80 to i64
  %min.iters.check = icmp ult i32 %80, 16
  br i1 %min.iters.check, label %.lr.ph.preheader94, label %vector.ph

vector.ph:                                        ; preds = %.lr.ph.preheader
  %n.vec = and i64 %81, 4294967280
  %82 = shl nuw nsw i64 %n.vec, 1
  %ind.end = getelementptr i8, ptr %.083, i64 %82
  %ind.end91 = trunc nuw i64 %n.vec to i32
  %broadcast.splatinsert = insertelement <8 x i16> poison, i16 %.pre, i64 0
  %broadcast.splat = shufflevector <8 x i16> %broadcast.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %offset.idx = shl i64 %index, 1
  %next.gep = getelementptr i8, ptr %.083, i64 %offset.idx
  %83 = getelementptr i8, ptr %next.gep, i64 16
  store <8 x i16> %broadcast.splat, ptr %next.gep, align 2, !tbaa !27
  store <8 x i16> %broadcast.splat, ptr %83, align 2, !tbaa !27
  %index.next = add nuw i64 %index, 16
  %84 = icmp eq i64 %index.next, %n.vec
  br i1 %84, label %middle.block, label %vector.body, !llvm.loop !28

middle.block:                                     ; preds = %vector.body
  %cmp.n = icmp eq i64 %n.vec, %81
  br i1 %cmp.n, label %._crit_edge, label %.lr.ph.preheader94

.lr.ph.preheader94:                               ; preds = %middle.block, %.lr.ph.preheader
  %.179.ph = phi ptr [ %.083, %.lr.ph.preheader ], [ %ind.end, %middle.block ]
  %.07678.ph = phi i32 [ 0, %.lr.ph.preheader ], [ %ind.end91, %middle.block ]
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader94, %.lr.ph
  %.179 = phi ptr [ %85, %.lr.ph ], [ %.179.ph, %.lr.ph.preheader94 ]
  %.07678 = phi i32 [ %86, %.lr.ph ], [ %.07678.ph, %.lr.ph.preheader94 ]
  store i16 %.pre, ptr %.179, align 2, !tbaa !27
  %85 = getelementptr inbounds i8, ptr %.179, i64 2
  %86 = add nuw i32 %.07678, 1
  %exitcond.not = icmp eq i32 %86, %80
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !31

._crit_edge:                                      ; preds = %.lr.ph, %middle.block, %79
  %.1.lcssa = phi ptr [ %.083, %79 ], [ %ind.end, %middle.block ], [ %85, %.lr.ph ]
  %87 = add i32 %.07282, -1
  %88 = add i32 %.07481, 1
  %.not = icmp eq i32 %87, 0
  br i1 %.not, label %.sink.split89, label %41, !llvm.loop !32

.sink.split89:                                    ; preds = %._crit_edge, %41, %74, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %74 ], [ 1, %41 ], [ 1, %._crit_edge ]
  %.073.ph = phi i32 [ 0, %15 ], [ 3, %74 ], [ 0, %41 ], [ 0, %._crit_edge ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %89

89:                                               ; preds = %.sink.split89, %8, %11, %4
  %.073 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.073.ph, %.sink.split89 ]
  ret i32 %.073
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 44}
!14 = !{!6, !11, i64 64}
!15 = !{!16, !17, i64 2}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !8, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!6, !11, i64 52}
!20 = !{!16, !17, i64 0}
!21 = !{!6, !11, i64 56}
!22 = !{!8, !8, i64 0}
!23 = !{!6, !11, i64 68}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!6, !11, i64 48}
!27 = !{!17, !17, i64 0}
!28 = distinct !{!28, !25, !29, !30}
!29 = !{!"llvm.loop.isvectorized", i32 1}
!30 = !{!"llvm.loop.unroll.runtime.disable"}
!31 = distinct !{!31, !25, !30, !29}
!32 = distinct !{!32, !25}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass