; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConfigRegion)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.MPU_Region_InitTypeDef = type { i8, i8, i32, i8, i8, i8, i8, i8, i8, i8, i8 }
%struct.MPU_Type = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local void @HAL_MPU_ConfigRegion(ptr noundef %0) #0 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %4 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %3, i32 0, i32 1
  %5 = load i8, ptr %4, align 1, !tbaa !9
  %6 = zext i8 %5 to i32
  store volatile i32 %6, ptr getelementptr inbounds (%struct.MPU_Type, ptr inttoptr (i64 3758157200 to ptr), i32 0, i32 2), align 4, !tbaa !12
  %7 = load ptr, ptr %2, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %7, i32 0, i32 0
  %9 = load i8, ptr %8, align 4, !tbaa !14
  %10 = zext i8 %9 to i64
  %11 = icmp ne i64 %10, 0
  br i1 %11, label %12, label %69

12:                                               ; preds = %1
  %13 = load ptr, ptr %2, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %13, i32 0, i32 2
  %15 = load i32, ptr %14, align 4, !tbaa !15
  store volatile i32 %15, ptr getelementptr inbounds (%struct.MPU_Type, ptr inttoptr (i64 3758157200 to ptr), i32 0, i32 3), align 4, !tbaa !16
  %16 = load ptr, ptr %2, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %16, i32 0, i32 7
  %18 = load i8, ptr %17, align 4, !tbaa !17
  %19 = zext i8 %18 to i32
  %20 = shl i32 %19, 28
  %21 = load ptr, ptr %2, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %21, i32 0, i32 6
  %23 = load i8, ptr %22, align 1, !tbaa !18
  %24 = zext i8 %23 to i32
  %25 = shl i32 %24, 24
  %26 = or i32 %20, %25
  %27 = load ptr, ptr %2, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %27, i32 0, i32 5
  %29 = load i8, ptr %28, align 2, !tbaa !19
  %30 = zext i8 %29 to i32
  %31 = shl i32 %30, 19
  %32 = or i32 %26, %31
  %33 = load ptr, ptr %2, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %33, i32 0, i32 8
  %35 = load i8, ptr %34, align 1, !tbaa !20
  %36 = zext i8 %35 to i32
  %37 = shl i32 %36, 18
  %38 = or i32 %32, %37
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %39, i32 0, i32 9
  %41 = load i8, ptr %40, align 2, !tbaa !21
  %42 = zext i8 %41 to i32
  %43 = shl i32 %42, 17
  %44 = or i32 %38, %43
  %45 = load ptr, ptr %2, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %45, i32 0, i32 10
  %47 = load i8, ptr %46, align 1, !tbaa !22
  %48 = zext i8 %47 to i32
  %49 = shl i32 %48, 16
  %50 = or i32 %44, %49
  %51 = load ptr, ptr %2, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %51, i32 0, i32 4
  %53 = load i8, ptr %52, align 1, !tbaa !23
  %54 = zext i8 %53 to i32
  %55 = shl i32 %54, 8
  %56 = or i32 %50, %55
  %57 = load ptr, ptr %2, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %57, i32 0, i32 3
  %59 = load i8, ptr %58, align 4, !tbaa !24
  %60 = zext i8 %59 to i32
  %61 = shl i32 %60, 1
  %62 = or i32 %56, %61
  %63 = load ptr, ptr %2, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.MPU_Region_InitTypeDef, ptr %63, i32 0, i32 0
  %65 = load i8, ptr %64, align 4, !tbaa !14
  %66 = zext i8 %65 to i32
  %67 = shl i32 %66, 0
  %68 = or i32 %62, %67
  store volatile i32 %68, ptr getelementptr inbounds (%struct.MPU_Type, ptr inttoptr (i64 3758157200 to ptr), i32 0, i32 4), align 4, !tbaa !25
  br label %70

69:                                               ; preds = %1
  store volatile i32 0, ptr getelementptr inbounds (%struct.MPU_Type, ptr inttoptr (i64 3758157200 to ptr), i32 0, i32 3), align 4, !tbaa !16
  store volatile i32 0, ptr getelementptr inbounds (%struct.MPU_Type, ptr inttoptr (i64 3758157200 to ptr), i32 0, i32 4), align 4, !tbaa !25
  br label %70

70:                                               ; preds = %69, %12
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !7, i64 1}
!10 = !{!"", !7, i64 0, !7, i64 1, !11, i64 4, !7, i64 8, !7, i64 9, !7, i64 10, !7, i64 11, !7, i64 12, !7, i64 13, !7, i64 14, !7, i64 15}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40}
!14 = !{!10, !7, i64 0}
!15 = !{!10, !11, i64 4}
!16 = !{!13, !11, i64 12}
!17 = !{!10, !7, i64 12}
!18 = !{!10, !7, i64 11}
!19 = !{!10, !7, i64 10}
!20 = !{!10, !7, i64 13}
!21 = !{!10, !7, i64 14}
!22 = !{!10, !7, i64 15}
!23 = !{!10, !7, i64 9}
!24 = !{!10, !7, i64 8}
!25 = !{!13, !11, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local void @HAL_MPU_ConfigRegion(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 1
  %3 = load i8, ptr %2, align 1, !tbaa !5
  %4 = zext i8 %3 to i32
  store volatile i32 %4, ptr inttoptr (i64 3758157208 to ptr), align 8, !tbaa !10
  %5 = load i8, ptr %0, align 4, !tbaa !12
  %.not = icmp eq i8 %5, 0
  br i1 %.not, label %50, label %6

6:                                                ; preds = %1
  %7 = getelementptr inbounds i8, ptr %0, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !13
  store volatile i32 %8, ptr inttoptr (i64 3758157212 to ptr), align 4, !tbaa !14
  %9 = getelementptr inbounds i8, ptr %0, i64 12
  %10 = load i8, ptr %9, align 4, !tbaa !15
  %11 = zext i8 %10 to i32
  %12 = shl i32 %11, 28
  %13 = getelementptr inbounds i8, ptr %0, i64 11
  %14 = load i8, ptr %13, align 1, !tbaa !16
  %15 = zext i8 %14 to i32
  %16 = shl nuw i32 %15, 24
  %17 = getelementptr inbounds i8, ptr %0, i64 10
  %18 = load i8, ptr %17, align 2, !tbaa !17
  %19 = zext i8 %18 to i32
  %20 = shl nuw nsw i32 %19, 19
  %21 = getelementptr inbounds i8, ptr %0, i64 13
  %22 = load i8, ptr %21, align 1, !tbaa !18
  %23 = zext i8 %22 to i32
  %24 = shl nuw nsw i32 %23, 18
  %25 = getelementptr inbounds i8, ptr %0, i64 14
  %26 = load i8, ptr %25, align 2, !tbaa !19
  %27 = zext i8 %26 to i32
  %28 = shl nuw nsw i32 %27, 17
  %29 = getelementptr inbounds i8, ptr %0, i64 15
  %30 = load i8, ptr %29, align 1, !tbaa !20
  %31 = zext i8 %30 to i32
  %32 = shl nuw nsw i32 %31, 16
  %33 = getelementptr inbounds i8, ptr %0, i64 9
  %34 = load i8, ptr %33, align 1, !tbaa !21
  %35 = zext i8 %34 to i32
  %36 = shl nuw nsw i32 %35, 8
  %37 = getelementptr inbounds i8, ptr %0, i64 8
  %38 = load i8, ptr %37, align 4, !tbaa !22
  %39 = zext i8 %38 to i32
  %40 = shl nuw nsw i32 %39, 1
  %41 = zext i8 %5 to i32
  %42 = or disjoint i32 %12, %41
  %43 = or i32 %42, %16
  %44 = or i32 %43, %20
  %45 = or i32 %44, %24
  %46 = or i32 %45, %28
  %47 = or i32 %46, %32
  %48 = or i32 %47, %36
  %49 = or i32 %48, %40
  br label %51

50:                                               ; preds = %1
  store volatile i32 0, ptr inttoptr (i64 3758157212 to ptr), align 4, !tbaa !14
  br label %51

51:                                               ; preds = %50, %6
  %.sink = phi i32 [ 0, %50 ], [ %49, %6 ]
  store volatile i32 %.sink, ptr inttoptr (i64 3758157216 to ptr), align 32, !tbaa !23
  ret void
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 1}
!6 = !{!"", !7, i64 0, !7, i64 1, !9, i64 4, !7, i64 8, !7, i64 9, !7, i64 10, !7, i64 11, !7, i64 12, !7, i64 13, !7, i64 14, !7, i64 15}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"int", !7, i64 0}
!10 = !{!11, !9, i64 8}
!11 = !{!"", !9, i64 0, !9, i64 4, !9, i64 8, !9, i64 12, !9, i64 16, !9, i64 20, !9, i64 24, !9, i64 28, !9, i64 32, !9, i64 36, !9, i64 40}
!12 = !{!6, !7, i64 0}
!13 = !{!6, !9, i64 4}
!14 = !{!11, !9, i64 12}
!15 = !{!6, !7, i64 12}
!16 = !{!6, !7, i64 11}
!17 = !{!6, !7, i64 10}
!18 = !{!6, !7, i64 13}
!19 = !{!6, !7, i64 14}
!20 = !{!6, !7, i64 15}
!21 = !{!6, !7, i64 9}
!22 = !{!6, !7, i64 8}
!23 = !{!11, !9, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass