; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions (opt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_depthwise_conv_s8_opt(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, ptr noundef %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i16 noundef zeroext %7, i16 noundef zeroext %8, i16 noundef zeroext %9, i16 noundef zeroext %10, i16 noundef zeroext %11, ptr noundef %12, ptr noundef %13, ptr noundef %14, ptr noundef %15, i16 noundef zeroext %16, i16 noundef zeroext %17, i32 noundef %18, i32 noundef %19, i32 noundef %20, i32 noundef %21, i16 noundef zeroext %22, i16 noundef zeroext %23, ptr noundef %24) #0 {
  %26 = alloca i32, align 4
  %27 = alloca ptr, align 8
  %28 = alloca i16, align 2
  %29 = alloca i16, align 2
  %30 = alloca i16, align 2
  %31 = alloca ptr, align 8
  %32 = alloca i16, align 2
  %33 = alloca i16, align 2
  %34 = alloca i16, align 2
  %35 = alloca i16, align 2
  %36 = alloca i16, align 2
  %37 = alloca i16, align 2
  %38 = alloca i16, align 2
  %39 = alloca ptr, align 8
  %40 = alloca ptr, align 8
  %41 = alloca ptr, align 8
  %42 = alloca ptr, align 8
  %43 = alloca i16, align 2
  %44 = alloca i16, align 2
  %45 = alloca i32, align 4
  %46 = alloca i32, align 4
  %47 = alloca i32, align 4
  %48 = alloca i32, align 4
  %49 = alloca i16, align 2
  %50 = alloca i16, align 2
  %51 = alloca ptr, align 8
  store ptr %0, ptr %27, align 8, !tbaa !5
  store i16 %1, ptr %28, align 2, !tbaa !9
  store i16 %2, ptr %29, align 2, !tbaa !9
  store i16 %3, ptr %30, align 2, !tbaa !9
  store ptr %4, ptr %31, align 8, !tbaa !5
  store i16 %5, ptr %32, align 2, !tbaa !9
  store i16 %6, ptr %33, align 2, !tbaa !9
  store i16 %7, ptr %34, align 2, !tbaa !9
  store i16 %8, ptr %35, align 2, !tbaa !9
  store i16 %9, ptr %36, align 2, !tbaa !9
  store i16 %10, ptr %37, align 2, !tbaa !9
  store i16 %11, ptr %38, align 2, !tbaa !9
  store ptr %12, ptr %39, align 8, !tbaa !5
  store ptr %13, ptr %40, align 8, !tbaa !5
  store ptr %14, ptr %41, align 8, !tbaa !5
  store ptr %15, ptr %42, align 8, !tbaa !5
  store i16 %16, ptr %43, align 2, !tbaa !9
  store i16 %17, ptr %44, align 2, !tbaa !9
  store i32 %18, ptr %45, align 4, !tbaa !11
  store i32 %19, ptr %46, align 4, !tbaa !11
  store i32 %20, ptr %47, align 4, !tbaa !11
  store i32 %21, ptr %48, align 4, !tbaa !11
  store i16 %22, ptr %49, align 2, !tbaa !9
  store i16 %23, ptr %50, align 2, !tbaa !9
  store ptr %24, ptr %51, align 8, !tbaa !5
  %52 = load i16, ptr %30, align 2, !tbaa !9
  %53 = zext i16 %52 to i32
  %54 = load i16, ptr %32, align 2, !tbaa !9
  %55 = zext i16 %54 to i32
  %56 = icmp ne i32 %53, %55
  br i1 %56, label %57, label %58

57:                                               ; preds = %25
  store i32 -3, ptr %26, align 4
  br label %85

58:                                               ; preds = %25
  %59 = load ptr, ptr %51, align 8, !tbaa !5
  %60 = load ptr, ptr %27, align 8, !tbaa !5
  %61 = load i16, ptr %28, align 2, !tbaa !9
  %62 = load i16, ptr %29, align 2, !tbaa !9
  %63 = load i16, ptr %30, align 2, !tbaa !9
  %64 = load ptr, ptr %31, align 8, !tbaa !5
  %65 = load i16, ptr %32, align 2, !tbaa !9
  %66 = load i16, ptr %33, align 2, !tbaa !9
  %67 = load i16, ptr %34, align 2, !tbaa !9
  %68 = load i16, ptr %35, align 2, !tbaa !9
  %69 = load i16, ptr %36, align 2, !tbaa !9
  %70 = load i16, ptr %37, align 2, !tbaa !9
  %71 = load i16, ptr %38, align 2, !tbaa !9
  %72 = load ptr, ptr %39, align 8, !tbaa !5
  %73 = load ptr, ptr %40, align 8, !tbaa !5
  %74 = load ptr, ptr %41, align 8, !tbaa !5
  %75 = load ptr, ptr %42, align 8, !tbaa !5
  %76 = load i16, ptr %43, align 2, !tbaa !9
  %77 = load i16, ptr %44, align 2, !tbaa !9
  %78 = load i32, ptr %45, align 4, !tbaa !11
  %79 = load i32, ptr %46, align 4, !tbaa !11
  %80 = load i32, ptr %47, align 4, !tbaa !11
  %81 = load i32, ptr %48, align 4, !tbaa !11
  %82 = load i16, ptr %49, align 2, !tbaa !9
  %83 = load i16, ptr %50, align 2, !tbaa !9
  %84 = call i32 @arm_depthwise_conv_s8(ptr noundef %60, i16 noundef zeroext %61, i16 noundef zeroext %62, i16 noundef zeroext %63, ptr noundef %64, i16 noundef zeroext %65, i16 noundef zeroext 1, i16 noundef zeroext %66, i16 noundef zeroext %67, i16 noundef zeroext %68, i16 noundef zeroext %69, i16 noundef zeroext %70, i16 noundef zeroext %71, ptr noundef %72, ptr noundef %73, ptr noundef %74, ptr noundef %75, i16 noundef zeroext %76, i16 noundef zeroext %77, i32 noundef %78, i32 noundef %79, i32 noundef %80, i32 noundef %81, i16 noundef zeroext %82, i16 noundef zeroext %83, ptr noundef null)
  store i32 %84, ptr %26, align 4
  br label %85

85:                                               ; preds = %58, %57
  %86 = load i32, ptr %26, align 4
  ret i32 %86
}

declare i32 @arm_depthwise_conv_s8(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i16 noundef zeroext, i16 noundef zeroext, ptr noundef) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @arm_depthwise_conv_s8_opt(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, ptr noundef %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i16 noundef zeroext %7, i16 noundef zeroext %8, i16 noundef zeroext %9, i16 noundef zeroext %10, i16 noundef zeroext %11, ptr noundef %12, ptr noundef %13, ptr noundef %14, ptr noundef %15, i16 noundef zeroext %16, i16 noundef zeroext %17, i32 noundef %18, i32 noundef %19, i32 noundef %20, i32 noundef %21, i16 noundef zeroext %22, i16 noundef zeroext %23, ptr nocapture noundef readnone %24) local_unnamed_addr #0 {
  %.not = icmp eq i16 %3, %5
  br i1 %.not, label %26, label %28

26:                                               ; preds = %25
  %27 = tail call i32 @arm_depthwise_conv_s8(ptr noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, ptr noundef %4, i16 noundef zeroext %3, i16 noundef zeroext 1, i16 noundef zeroext %6, i16 noundef zeroext %7, i16 noundef zeroext %8, i16 noundef zeroext %9, i16 noundef zeroext %10, i16 noundef zeroext %11, ptr noundef %12, ptr noundef %13, ptr noundef %14, ptr noundef %15, i16 noundef zeroext %16, i16 noundef zeroext %17, i32 noundef %18, i32 noundef %19, i32 noundef %20, i32 noundef %21, i16 noundef zeroext %22, i16 noundef zeroext %23, ptr noundef null) #2
  br label %28

28:                                               ; preds = %25, %26
  %.0 = phi i32 [ %27, %26 ], [ -3, %25 ]
  ret i32 %.0
}

declare i32 @arm_depthwise_conv_s8(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i16 noundef zeroext, i16 noundef zeroext, ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GVNPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass