; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Init)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__UART_HandleTypeDef = type { ptr, %struct.UART_InitTypeDef, %struct.UART_AdvFeatureInitTypeDef, ptr, i16, i16, ptr, i16, i16, i16, i32, i16, i16, ptr, ptr, ptr, ptr, i32, i32, i32, i32 }
%struct.UART_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.UART_AdvFeatureInitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.USART_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_UART_MspInit(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @UART_SetConfig(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @UART_AdvFeatureConfig(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @UART_CheckIdleState(ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_MultiProcessor_Init(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !10
  %8 = load ptr, ptr %5, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %3
  store i32 1, ptr %4, align 4
  br label %107

11:                                               ; preds = %3
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %12, i32 0, i32 18
  %14 = load volatile i32, ptr %13, align 4, !tbaa !12
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %16, label %20

16:                                               ; preds = %11
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %17, i32 0, i32 17
  store i32 0, ptr %18, align 8, !tbaa !17
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  call void @HAL_UART_MspInit(ptr noundef %19)
  br label %20

20:                                               ; preds = %16, %11
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %21, i32 0, i32 18
  store volatile i32 36, ptr %22, align 4, !tbaa !12
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %23, i32 0, i32 0
  %25 = load ptr, ptr %24, align 8, !tbaa !18
  %26 = getelementptr inbounds %struct.USART_TypeDef, ptr %25, i32 0, i32 0
  %27 = load volatile i32, ptr %26, align 4, !tbaa !19
  %28 = zext i32 %27 to i64
  %29 = and i64 %28, -2
  %30 = trunc i64 %29 to i32
  store volatile i32 %30, ptr %26, align 4, !tbaa !19
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = call i32 @UART_SetConfig(ptr noundef %31)
  %33 = icmp eq i32 %32, 1
  br i1 %33, label %34, label %35

34:                                               ; preds = %20
  store i32 1, ptr %4, align 4
  br label %107

35:                                               ; preds = %20
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %36, i32 0, i32 2
  %38 = getelementptr inbounds %struct.UART_AdvFeatureInitTypeDef, ptr %37, i32 0, i32 0
  %39 = load i32, ptr %38, align 4, !tbaa !21
  %40 = icmp ne i32 %39, 0
  br i1 %40, label %41, label %43

41:                                               ; preds = %35
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  call void @UART_AdvFeatureConfig(ptr noundef %42)
  br label %43

43:                                               ; preds = %41, %35
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !18
  %47 = getelementptr inbounds %struct.USART_TypeDef, ptr %46, i32 0, i32 1
  %48 = load volatile i32, ptr %47, align 4, !tbaa !22
  %49 = zext i32 %48 to i64
  %50 = and i64 %49, -18433
  %51 = trunc i64 %50 to i32
  store volatile i32 %51, ptr %47, align 4, !tbaa !22
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !18
  %55 = getelementptr inbounds %struct.USART_TypeDef, ptr %54, i32 0, i32 2
  %56 = load volatile i32, ptr %55, align 4, !tbaa !23
  %57 = zext i32 %56 to i64
  %58 = and i64 %57, -43
  %59 = trunc i64 %58 to i32
  store volatile i32 %59, ptr %55, align 4, !tbaa !23
  %60 = load i32, ptr %7, align 4, !tbaa !10
  %61 = zext i32 %60 to i64
  %62 = icmp eq i64 %61, 2048
  br i1 %62, label %63, label %81

63:                                               ; preds = %43
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %64, i32 0, i32 0
  %66 = load ptr, ptr %65, align 8, !tbaa !18
  %67 = getelementptr inbounds %struct.USART_TypeDef, ptr %66, i32 0, i32 1
  %68 = load volatile i32, ptr %67, align 4, !tbaa !22
  %69 = zext i32 %68 to i64
  %70 = and i64 %69, -4278190081
  %71 = load i8, ptr %6, align 1, !tbaa !9
  %72 = zext i8 %71 to i32
  %73 = shl i32 %72, 24
  %74 = zext i32 %73 to i64
  %75 = or i64 %70, %74
  %76 = trunc i64 %75 to i32
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !18
  %80 = getelementptr inbounds %struct.USART_TypeDef, ptr %79, i32 0, i32 1
  store volatile i32 %76, ptr %80, align 4, !tbaa !22
  br label %81

81:                                               ; preds = %63, %43
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !18
  %85 = getelementptr inbounds %struct.USART_TypeDef, ptr %84, i32 0, i32 0
  %86 = load volatile i32, ptr %85, align 4, !tbaa !19
  %87 = zext i32 %86 to i64
  %88 = and i64 %87, -2049
  %89 = load i32, ptr %7, align 4, !tbaa !10
  %90 = zext i32 %89 to i64
  %91 = or i64 %88, %90
  %92 = trunc i64 %91 to i32
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %93, i32 0, i32 0
  %95 = load ptr, ptr %94, align 8, !tbaa !18
  %96 = getelementptr inbounds %struct.USART_TypeDef, ptr %95, i32 0, i32 0
  store volatile i32 %92, ptr %96, align 4, !tbaa !19
  %97 = load ptr, ptr %5, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.__UART_HandleTypeDef, ptr %97, i32 0, i32 0
  %99 = load ptr, ptr %98, align 8, !tbaa !18
  %100 = getelementptr inbounds %struct.USART_TypeDef, ptr %99, i32 0, i32 0
  %101 = load volatile i32, ptr %100, align 4, !tbaa !19
  %102 = zext i32 %101 to i64
  %103 = or i64 %102, 1
  %104 = trunc i64 %103 to i32
  store volatile i32 %104, ptr %100, align 4, !tbaa !19
  %105 = load ptr, ptr %5, align 8, !tbaa !5
  %106 = call i32 @UART_CheckIdleState(ptr noundef %105)
  store i32 %106, ptr %4, align 4
  br label %107

107:                                              ; preds = %81, %34, %10
  %108 = load i32, ptr %4, align 4
  ret i32 %108
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 164}
!13 = !{!"__UART_HandleTypeDef", !6, i64 0, !14, i64 8, !15, i64 44, !6, i64 88, !16, i64 96, !16, i64 98, !6, i64 104, !16, i64 112, !16, i64 114, !16, i64 116, !11, i64 120, !16, i64 124, !16, i64 126, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!16 = !{!"short", !7, i64 0}
!17 = !{!13, !11, i64 160}
!18 = !{!13, !6, i64 0}
!19 = !{!20, !11, i64 0}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!21 = !{!13, !11, i64 44}
!22 = !{!20, !11, i64 4}
!23 = !{!20, !11, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_UART_MspInit(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @UART_SetConfig(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @UART_AdvFeatureConfig(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @UART_CheckIdleState(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_MultiProcessor_Init(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %0, null
  br i1 %4, label %43, label %5

5:                                                ; preds = %3
  %6 = getelementptr inbounds i8, ptr %0, i64 164
  %7 = load volatile i32, ptr %6, align 4, !tbaa !5
  %8 = icmp eq i32 %7, 0
  br i1 %8, label %9, label %11

9:                                                ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 160
  store i32 0, ptr %10, align 8, !tbaa !14
  tail call void @HAL_UART_MspInit(ptr noundef nonnull %0)
  br label %11

11:                                               ; preds = %9, %5
  store volatile i32 36, ptr %6, align 4, !tbaa !5
  %12 = load ptr, ptr %0, align 8, !tbaa !15
  %13 = load volatile i32, ptr %12, align 4, !tbaa !16
  %14 = and i32 %13, -2
  store volatile i32 %14, ptr %12, align 4, !tbaa !16
  %15 = tail call i32 @UART_SetConfig(ptr noundef nonnull %0)
  %16 = icmp eq i32 %15, 1
  br i1 %16, label %43, label %17

17:                                               ; preds = %11
  %18 = getelementptr inbounds i8, ptr %0, i64 44
  %19 = load i32, ptr %18, align 4, !tbaa !18
  %.not = icmp eq i32 %19, 0
  br i1 %.not, label %21, label %20

20:                                               ; preds = %17
  tail call void @UART_AdvFeatureConfig(ptr noundef nonnull %0)
  br label %21

21:                                               ; preds = %20, %17
  %22 = load ptr, ptr %0, align 8, !tbaa !15
  %23 = getelementptr inbounds i8, ptr %22, i64 4
  %24 = load volatile i32, ptr %23, align 4, !tbaa !19
  %25 = and i32 %24, -18433
  store volatile i32 %25, ptr %23, align 4, !tbaa !19
  %26 = getelementptr inbounds i8, ptr %22, i64 8
  %27 = load volatile i32, ptr %26, align 4, !tbaa !20
  %28 = and i32 %27, -43
  store volatile i32 %28, ptr %26, align 4, !tbaa !20
  %29 = icmp eq i32 %2, 2048
  br i1 %29, label %30, label %36

30:                                               ; preds = %21
  %31 = load volatile i32, ptr %23, align 4, !tbaa !19
  %32 = and i32 %31, 16777215
  %33 = zext i8 %1 to i32
  %34 = shl nuw i32 %33, 24
  %35 = or disjoint i32 %32, %34
  store volatile i32 %35, ptr %23, align 4, !tbaa !19
  br label %36

36:                                               ; preds = %30, %21
  %37 = load volatile i32, ptr %22, align 4, !tbaa !16
  %38 = and i32 %37, -2049
  %39 = or i32 %38, %2
  store volatile i32 %39, ptr %22, align 4, !tbaa !16
  %40 = load volatile i32, ptr %22, align 4, !tbaa !16
  %41 = or i32 %40, 1
  store volatile i32 %41, ptr %22, align 4, !tbaa !16
  %42 = tail call i32 @UART_CheckIdleState(ptr noundef nonnull %0)
  br label %43

43:                                               ; preds = %11, %3, %36
  %.0 = phi i32 [ %42, %36 ], [ 1, %3 ], [ 1, %11 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 164}
!6 = !{!"__UART_HandleTypeDef", !7, i64 0, !10, i64 8, !12, i64 44, !7, i64 88, !13, i64 96, !13, i64 98, !7, i64 104, !13, i64 112, !13, i64 114, !13, i64 116, !11, i64 120, !13, i64 124, !13, i64 126, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36}
!13 = !{!"short", !8, i64 0}
!14 = !{!6, !11, i64 160}
!15 = !{!6, !7, i64 0}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!18 = !{!6, !11, i64 44}
!19 = !{!17, !11, i64 4}
!20 = !{!17, !11, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass