; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.DFSDM_Filter_HandleTypeDef = type { ptr, %struct.DFSDM_Filter_InitTypeDef, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.DFSDM_Filter_InitTypeDef = type { %struct.DFSDM_Filter_RegularParamTypeDef, %struct.DFSDM_Filter_InjectedParamTypeDef, %struct.DFSDM_Filter_FilterParamTypeDef }
%struct.DFSDM_Filter_RegularParamTypeDef = type { i32, i32, i32 }
%struct.DFSDM_Filter_InjectedParamTypeDef = type { i32, i32, i32, i32, i32 }
%struct.DFSDM_Filter_FilterParamTypeDef = type { i32, i32, i32 }
%struct.DFSDM_Filter_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_RegConvStart(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMARegularConvCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMAError(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMARegularHalfConvCplt(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DFSDM_FilterRegularMsbStart_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  %8 = load ptr, ptr %5, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %13, label %10

10:                                               ; preds = %3
  %11 = load i32, ptr %6, align 4, !tbaa !9
  %12 = icmp eq i32 %11, 0
  br i1 %12, label %13, label %14

13:                                               ; preds = %10, %3
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %122

14:                                               ; preds = %10
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %15, i32 0, i32 0
  %17 = load ptr, ptr %16, align 8, !tbaa !11
  %18 = getelementptr inbounds %struct.DFSDM_Filter_TypeDef, ptr %17, i32 0, i32 0
  %19 = load volatile i32, ptr %18, align 4, !tbaa !16
  %20 = zext i32 %19 to i64
  %21 = and i64 %20, 2097152
  %22 = icmp ne i64 %21, 2097152
  br i1 %22, label %23, label %24

23:                                               ; preds = %14
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %121

24:                                               ; preds = %14
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %25, i32 0, i32 5
  %27 = load i32, ptr %26, align 4, !tbaa !18
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %29, label %46

29:                                               ; preds = %24
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %30, i32 0, i32 4
  %32 = load i32, ptr %31, align 8, !tbaa !19
  %33 = icmp eq i32 %32, 0
  br i1 %33, label %34, label %46

34:                                               ; preds = %29
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %35, i32 0, i32 2
  %37 = load ptr, ptr %36, align 8, !tbaa !20
  %38 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %37, i32 0, i32 1
  %39 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %38, i32 0, i32 6
  %40 = load i32, ptr %39, align 8, !tbaa !21
  %41 = icmp eq i32 %40, 0
  br i1 %41, label %42, label %46

42:                                               ; preds = %34
  %43 = load i32, ptr %6, align 4, !tbaa !9
  %44 = icmp ne i32 %43, 1
  br i1 %44, label %45, label %46

45:                                               ; preds = %42
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %120

46:                                               ; preds = %42, %34, %29, %24
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %47, i32 0, i32 5
  %49 = load i32, ptr %48, align 4, !tbaa !18
  %50 = icmp eq i32 %49, 0
  br i1 %50, label %51, label %65

51:                                               ; preds = %46
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %52, i32 0, i32 4
  %54 = load i32, ptr %53, align 8, !tbaa !19
  %55 = icmp eq i32 %54, 0
  br i1 %55, label %56, label %65

56:                                               ; preds = %51
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %57, i32 0, i32 2
  %59 = load ptr, ptr %58, align 8, !tbaa !20
  %60 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %59, i32 0, i32 1
  %61 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %60, i32 0, i32 6
  %62 = load i32, ptr %61, align 8, !tbaa !21
  %63 = icmp eq i32 %62, 256
  br i1 %63, label %64, label %65

64:                                               ; preds = %56
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %119

65:                                               ; preds = %56, %51, %46
  %66 = load ptr, ptr %4, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %66, i32 0, i32 11
  %68 = load i32, ptr %67, align 4, !tbaa !24
  %69 = icmp eq i32 %68, 1
  br i1 %69, label %75, label %70

70:                                               ; preds = %65
  %71 = load ptr, ptr %4, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %71, i32 0, i32 11
  %73 = load i32, ptr %72, align 4, !tbaa !24
  %74 = icmp eq i32 %73, 3
  br i1 %74, label %75, label %117

75:                                               ; preds = %70, %65
  %76 = load ptr, ptr %4, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %76, i32 0, i32 2
  %78 = load ptr, ptr %77, align 8, !tbaa !20
  %79 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %78, i32 0, i32 5
  store ptr @DFSDM_DMARegularConvCplt, ptr %79, align 8, !tbaa !25
  %80 = load ptr, ptr %4, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %80, i32 0, i32 2
  %82 = load ptr, ptr %81, align 8, !tbaa !20
  %83 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %82, i32 0, i32 9
  store ptr @DFSDM_DMAError, ptr %83, align 8, !tbaa !26
  %84 = load ptr, ptr %4, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %84, i32 0, i32 2
  %86 = load ptr, ptr %85, align 8, !tbaa !20
  %87 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %86, i32 0, i32 1
  %88 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %87, i32 0, i32 6
  %89 = load i32, ptr %88, align 8, !tbaa !21
  %90 = icmp eq i32 %89, 256
  %91 = zext i1 %90 to i64
  %92 = select i1 %90, ptr @DFSDM_DMARegularHalfConvCplt, ptr null
  %93 = load ptr, ptr %4, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %93, i32 0, i32 2
  %95 = load ptr, ptr %94, align 8, !tbaa !20
  %96 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %95, i32 0, i32 6
  store ptr %92, ptr %96, align 8, !tbaa !27
  %97 = load ptr, ptr %4, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %97, i32 0, i32 2
  %99 = load ptr, ptr %98, align 8, !tbaa !20
  %100 = load ptr, ptr %4, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %100, i32 0, i32 0
  %102 = load ptr, ptr %101, align 8, !tbaa !11
  %103 = getelementptr inbounds %struct.DFSDM_Filter_TypeDef, ptr %102, i32 0, i32 7
  %104 = ptrtoint ptr %103 to i32
  %105 = add i32 %104, 2
  %106 = load ptr, ptr %5, align 8, !tbaa !5
  %107 = ptrtoint ptr %106 to i32
  %108 = load i32, ptr %6, align 4, !tbaa !9
  %109 = call i32 @HAL_DMA_Start_IT(ptr noundef %99, i32 noundef %105, i32 noundef %107, i32 noundef %108)
  %110 = icmp ne i32 %109, 0
  br i1 %110, label %111, label %114

111:                                              ; preds = %75
  %112 = load ptr, ptr %4, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.DFSDM_Filter_HandleTypeDef, ptr %112, i32 0, i32 11
  store i32 255, ptr %113, align 4, !tbaa !24
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %116

114:                                              ; preds = %75
  %115 = load ptr, ptr %4, align 8, !tbaa !5
  call void @DFSDM_RegConvStart(ptr noundef %115)
  br label %116

116:                                              ; preds = %114, %111
  br label %118

117:                                              ; preds = %70
  store i32 1, ptr %7, align 4, !tbaa !9
  br label %118

118:                                              ; preds = %117, %116
  br label %119

119:                                              ; preds = %118, %64
  br label %120

120:                                              ; preds = %119, %45
  br label %121

121:                                              ; preds = %120, %23
  br label %122

122:                                              ; preds = %121, %13
  %123 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret i32 %123
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 56, !6, i64 64, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!13 = !{!"", !14, i64 0, !15, i64 12, !14, i64 32}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16}
!16 = !{!17, !10, i64 0}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!18 = !{!12, !10, i64 76}
!19 = !{!12, !10, i64 72}
!20 = !{!12, !6, i64 56}
!21 = !{!22, !10, i64 32}
!22 = !{!"__DMA_HandleTypeDef", !6, i64 0, !23, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!23 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!24 = !{!12, !10, i64 100}
!25 = !{!22, !6, i64 72}
!26 = !{!22, !6, i64 104}
!27 = !{!22, !6, i64 80}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_RegConvStart(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMARegularConvCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMAError(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DFSDM_DMARegularHalfConvCplt(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_DFSDM_FilterRegularMsbStart_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %1, null
  %5 = icmp eq i32 %2, 0
  %or.cond = or i1 %4, %5
  br i1 %or.cond, label %53, label %6

6:                                                ; preds = %3
  %7 = load ptr, ptr %0, align 8, !tbaa !5
  %8 = load volatile i32, ptr %7, align 4, !tbaa !14
  %9 = and i32 %8, 2097152
  %.not.not = icmp eq i32 %9, 0
  br i1 %.not.not, label %53, label %10

10:                                               ; preds = %6
  %11 = getelementptr inbounds i8, ptr %0, i64 76
  %12 = load i32, ptr %11, align 4, !tbaa !16
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %14, label %31

14:                                               ; preds = %10
  %15 = getelementptr inbounds i8, ptr %0, i64 72
  %16 = load i32, ptr %15, align 8, !tbaa !17
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %31

18:                                               ; preds = %14
  %19 = getelementptr inbounds i8, ptr %0, i64 56
  %20 = load ptr, ptr %19, align 8, !tbaa !18
  %21 = getelementptr inbounds i8, ptr %20, i64 32
  %22 = load i32, ptr %21, align 8, !tbaa !19
  %23 = icmp eq i32 %22, 0
  %24 = icmp ne i32 %2, 1
  %or.cond3 = and i1 %24, %23
  br i1 %or.cond3, label %53, label %25

25:                                               ; preds = %18
  %26 = getelementptr inbounds i8, ptr %0, i64 56
  %27 = load ptr, ptr %26, align 8, !tbaa !18
  %28 = getelementptr inbounds i8, ptr %27, i64 32
  %29 = load i32, ptr %28, align 8, !tbaa !19
  %30 = icmp eq i32 %29, 256
  br i1 %30, label %53, label %31

31:                                               ; preds = %14, %10, %25
  %32 = getelementptr inbounds i8, ptr %0, i64 100
  %33 = load i32, ptr %32, align 4, !tbaa !22
  switch i32 %33, label %53 [
    i32 1, label %34
    i32 3, label %34
  ]

34:                                               ; preds = %31, %31
  %35 = getelementptr inbounds i8, ptr %0, i64 56
  %36 = load ptr, ptr %35, align 8, !tbaa !18
  %37 = getelementptr inbounds i8, ptr %36, i64 72
  store ptr @DFSDM_DMARegularConvCplt, ptr %37, align 8, !tbaa !23
  %38 = getelementptr inbounds i8, ptr %36, i64 104
  store ptr @DFSDM_DMAError, ptr %38, align 8, !tbaa !24
  %39 = getelementptr inbounds i8, ptr %36, i64 32
  %40 = load i32, ptr %39, align 8, !tbaa !19
  %41 = icmp eq i32 %40, 256
  %42 = select i1 %41, ptr @DFSDM_DMARegularHalfConvCplt, ptr null
  %43 = getelementptr inbounds i8, ptr %36, i64 80
  store ptr %42, ptr %43, align 8, !tbaa !25
  %44 = getelementptr inbounds i8, ptr %7, i64 28
  %45 = ptrtoint ptr %44 to i64
  %46 = trunc i64 %45 to i32
  %47 = add i32 %46, 2
  %48 = ptrtoint ptr %1 to i64
  %49 = trunc i64 %48 to i32
  %50 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %36, i32 noundef %47, i32 noundef %49, i32 noundef %2) #2
  %.not = icmp eq i32 %50, 0
  br i1 %.not, label %52, label %51

51:                                               ; preds = %34
  store i32 255, ptr %32, align 4, !tbaa !22
  br label %53

52:                                               ; preds = %34
  tail call void @DFSDM_RegConvStart(ptr noundef nonnull %0)
  br label %53

53:                                               ; preds = %31, %25, %18, %6, %3, %51, %52
  %.0 = phi i32 [ 1, %51 ], [ 0, %52 ], [ 1, %3 ], [ 1, %6 ], [ 1, %18 ], [ 1, %25 ], [ 1, %31 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 56, !7, i64 64, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !13, i64 12, !11, i64 32}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8}
!12 = !{!"int", !8, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16}
!14 = !{!15, !12, i64 0}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56}
!16 = !{!6, !12, i64 76}
!17 = !{!6, !12, i64 72}
!18 = !{!6, !7, i64 56}
!19 = !{!20, !12, i64 32}
!20 = !{!"__DMA_HandleTypeDef", !7, i64 0, !21, i64 8, !12, i64 56, !12, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !7, i64 136, !7, i64 144, !12, i64 152, !7, i64 160, !7, i64 168, !12, i64 176}
!21 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!22 = !{!6, !12, i64 100}
!23 = !{!20, !7, i64 72}
!24 = !{!20, !7, i64 104}
!25 = !{!20, !7, i64 80}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass