; LLVM IR from Xingyu-Lin/softgym :: PyFlex/extensions (flexExtContainer)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Bitmap = type { %"class.std::vector.19" }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.NvFlexExtContainer = type <{ i32, [4 x i8], ptr, ptr, %struct.NvFlexVector, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %struct.NvFlexVector.10, %struct.NvFlexVector.10, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector.10, %struct.NvFlexVector, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.16, %struct.NvFlexVector.12, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector, %struct.NvFlexVector.12, %struct.NvFlexVector, %struct.NvFlexVector, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.14, %struct.NvFlexVector.12, %struct.NvFlexVector.12, i8, i8, [6 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl" }
%"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl" = type { %"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NvFlexExtInstance *, std::allocator<NvFlexExtInstance *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl" }
%"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl" = type { %"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<NvFlexExtSoftJoint *, std::allocator<NvFlexExtSoftJoint *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.NvFlexVector.10 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.16 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.14 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>
%struct.NvFlexVector.12 = type <{ ptr, ptr, ptr, i32, i32, i32, [4 x i8] }>

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [91 x i8], align 1
@__PRETTY_FUNCTION__.NvFlexExtGetActiveList = external hidden unnamed_addr constant [56 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local i32 @NvFlexExtGetActiveList(ptr noundef %0, ptr noundef %1) #2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca %class.Bitmap, align 8
  %7 = alloca i64, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 0, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 24, ptr %6) #5
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %11, i32 0, i32 0
  %13 = load i32, ptr %12, align 8, !tbaa !11
  call void @_ZN6BitmapC2Ei(ptr noundef nonnull align 8 dereferenceable(24) %6, i32 noundef %13)
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  store i64 0, ptr %7, align 8, !tbaa !32
  br label %14

14:                                               ; preds = %44, %2
  %15 = load i64, ptr %7, align 8, !tbaa !32
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %16, i32 0, i32 5
  %18 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #5
  %19 = icmp ult i64 %15, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %47

21:                                               ; preds = %14
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %22, i32 0, i32 5
  %24 = load i64, ptr %7, align 8, !tbaa !32
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %24) #5
  %26 = load i32, ptr %25, align 4, !tbaa !9
  %27 = invoke noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24) %6, i32 noundef %26)
          to label %28 unwind label %32

28:                                               ; preds = %21
  %29 = xor i1 %27, true
  br i1 %29, label %30, label %31

30:                                               ; preds = %28
  br label %37

31:                                               ; preds = %28
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 595, ptr noundef @__PRETTY_FUNCTION__.NvFlexExtGetActiveList) #6
  unreachable

32:                                               ; preds = %37, %21
  %33 = landingpad { ptr, i32 }
          cleanup
  %34 = extractvalue { ptr, i32 } %33, 0
  store ptr %34, ptr %8, align 8
  %35 = extractvalue { ptr, i32 } %33, 1
  store i32 %35, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %78

36:                                               ; No predecessors!
  br label %37

37:                                               ; preds = %36, %30
  %38 = load ptr, ptr %3, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %38, i32 0, i32 5
  %40 = load i64, ptr %7, align 8, !tbaa !32
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %40) #5
  %42 = load i32, ptr %41, align 4, !tbaa !9
  invoke void @_ZN6Bitmap3SetEi(ptr noundef nonnull align 8 dereferenceable(24) %6, i32 noundef %42)
          to label %43 unwind label %32

43:                                               ; preds = %37
  br label %44

44:                                               ; preds = %43
  %45 = load i64, ptr %7, align 8, !tbaa !32
  %46 = add i64 %45, 1
  store i64 %46, ptr %7, align 8, !tbaa !32
  br label %14, !llvm.loop !34

47:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %73, %47
  %49 = load i32, ptr %10, align 4, !tbaa !9
  %50 = load ptr, ptr %3, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NvFlexExtContainer, ptr %50, i32 0, i32 0
  %52 = load i32, ptr %51, align 8, !tbaa !11
  %53 = icmp slt i32 %49, %52
  br i1 %53, label %55, label %54

54:                                               ; preds = %48
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  br label %76

55:                                               ; preds = %48
  %56 = load i32, ptr %10, align 4, !tbaa !9
  %57 = invoke noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24) %6, i32 noundef %56)
          to label %58 unwind label %68

58:                                               ; preds = %55
  %59 = zext i1 %57 to i32
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %72

61:                                               ; preds = %58
  %62 = load i32, ptr %10, align 4, !tbaa !9
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  %64 = load i32, ptr %5, align 4, !tbaa !9
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %5, align 4, !tbaa !9
  %66 = sext i32 %64 to i64
  %67 = getelementptr inbounds i32, ptr %63, i64 %66
  store i32 %62, ptr %67, align 4, !tbaa !9
  br label %72

68:                                               ; preds = %55
  %69 = landingpad { ptr, i32 }
          cleanup
  %70 = extractvalue { ptr, i32 } %69, 0
  store ptr %70, ptr %8, align 8
  %71 = extractvalue { ptr, i32 } %69, 1
  store i32 %71, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  br label %78

72:                                               ; preds = %61, %58
  br label %73

73:                                               ; preds = %72
  %74 = load i32, ptr %10, align 4, !tbaa !9
  %75 = add nsw i32 %74, 1
  store i32 %75, ptr %10, align 4, !tbaa !9
  br label %48, !llvm.loop !36

76:                                               ; preds = %54
  %77 = load i32, ptr %5, align 4, !tbaa !9
  call void @_ZN6BitmapD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  ret i32 %77

78:                                               ; preds = %68, %32
  call void @_ZN6BitmapD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  br label %79

79:                                               ; preds = %78
  %80 = load ptr, ptr %8, align 8
  %81 = load i32, ptr %9, align 4
  %82 = insertvalue { ptr, i32 } poison, ptr %80, 0
  %83 = insertvalue { ptr, i32 } %82, i32 %81, 1
  resume { ptr, i32 } %83
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6BitmapC2Ei(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6Bitmap3SetEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6BitmapD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTS18NvFlexExtContainer", !10, i64 0, !6, i64 8, !6, i64 16, !13, i64 24, !15, i64 64, !19, i64 88, !23, i64 112, !27, i64 136, !27, i64 176, !28, i64 216, !13, i64 256, !27, i64 296, !13, i64 336, !13, i64 376, !29, i64 416, !29, i64 456, !29, i64 496, !30, i64 536, !28, i64 576, !28, i64 616, !13, i64 656, !29, i64 696, !29, i64 736, !13, i64 776, !28, i64 816, !13, i64 856, !13, i64 896, !29, i64 936, !29, i64 976, !29, i64 1016, !28, i64 1056, !28, i64 1096, !31, i64 1136, !31, i64 1137}
!13 = !{!"_ZTS12NvFlexVectorIiE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!14 = !{!"_ZTS16NvFlexBufferType", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIiSaIiEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIP17NvFlexExtInstanceSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIP18NvFlexExtSoftJointSaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!"_ZTS12NvFlexVectorI8XVector4IfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!28 = !{!"_ZTS12NvFlexVectorI8XVector3IfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!29 = !{!"_ZTS12NvFlexVectorIfE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!30 = !{!"_ZTS12NvFlexVectorI5XQuatIfEE", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !14, i64 32}
!31 = !{!"bool", !7, i64 0}
!32 = !{!33, !33, i64 0}
!33 = !{!"long", !7, i64 0}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}
!36 = distinct !{!36, !35}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Bitmap = type { %"class.std::vector.19" }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str = external hidden unnamed_addr constant [33 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [91 x i8], align 1
@__PRETTY_FUNCTION__.NvFlexExtGetActiveList = external hidden unnamed_addr constant [56 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local i32 @NvFlexExtGetActiveList(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #2 personality ptr @__gxx_personality_v0 {
  %3 = alloca %class.Bitmap, align 8
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %3) #5
  %4 = load i32, ptr %0, align 8, !tbaa !5
  call void @_ZN6BitmapC2Ei(ptr noundef nonnull align 8 dereferenceable(24) %3, i32 noundef %4)
  %5 = getelementptr inbounds i8, ptr %0, i64 64
  %6 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #5
  %.not = icmp eq i64 %6, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %13, %2
  %7 = load i32, ptr %0, align 8, !tbaa !5
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %.lr.ph20, label %._crit_edge

.lr.ph:                                           ; preds = %2, %13
  %.01517 = phi i64 [ %16, %13 ], [ 0, %2 ]
  %9 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %.01517) #5
  %10 = load i32, ptr %9, align 4, !tbaa !30
  %11 = call noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24) %3, i32 noundef %10)
  br i1 %11, label %12, label %13

12:                                               ; preds = %.lr.ph
  call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 595, ptr noundef nonnull @__PRETTY_FUNCTION__.NvFlexExtGetActiveList) #6
  unreachable

13:                                               ; preds = %.lr.ph
  %14 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %.01517) #5
  %15 = load i32, ptr %14, align 4, !tbaa !30
  call void @_ZN6Bitmap3SetEi(ptr noundef nonnull align 8 dereferenceable(24) %3, i32 noundef %15)
  %16 = add nuw i64 %.01517, 1
  %17 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #5
  %18 = icmp ult i64 %16, %17
  br i1 %18, label %.lr.ph, label %.preheader, !llvm.loop !31

._crit_edge:                                      ; preds = %24, %.preheader
  %.016.lcssa = phi i32 [ 0, %.preheader ], [ %.1, %24 ]
  call void @_ZN6BitmapD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #5
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %3) #5
  ret i32 %.016.lcssa

.lr.ph20:                                         ; preds = %.preheader, %24
  %.019 = phi i32 [ %25, %24 ], [ 0, %.preheader ]
  %.01618 = phi i32 [ %.1, %24 ], [ 0, %.preheader ]
  %19 = call noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24) %3, i32 noundef %.019)
  br i1 %19, label %24, label %20

20:                                               ; preds = %.lr.ph20
  %21 = add nsw i32 %.01618, 1
  %22 = sext i32 %.01618 to i64
  %23 = getelementptr inbounds i32, ptr %1, i64 %22
  store i32 %.019, ptr %23, align 4, !tbaa !30
  br label %24

24:                                               ; preds = %.lr.ph20, %20
  %.1 = phi i32 [ %21, %20 ], [ %.01618, %.lr.ph20 ]
  %25 = add nuw nsw i32 %.019, 1
  %26 = load i32, ptr %0, align 8, !tbaa !5
  %27 = icmp slt i32 %25, %26
  br i1 %27, label %.lr.ph20, label %._crit_edge, !llvm.loop !33
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6BitmapC2Ei(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6Bitmap5IsSetEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #3 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6Bitmap3SetEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN6BitmapD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS18NvFlexExtContainer", !7, i64 0, !10, i64 8, !10, i64 16, !11, i64 24, !13, i64 64, !17, i64 88, !21, i64 112, !25, i64 136, !25, i64 176, !26, i64 216, !11, i64 256, !25, i64 296, !11, i64 336, !11, i64 376, !27, i64 416, !27, i64 456, !27, i64 496, !28, i64 536, !26, i64 576, !26, i64 616, !11, i64 656, !27, i64 696, !27, i64 736, !11, i64 776, !26, i64 816, !11, i64 856, !11, i64 896, !27, i64 936, !27, i64 976, !27, i64 1016, !26, i64 1056, !26, i64 1096, !29, i64 1136, !29, i64 1137}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!"_ZTS12NvFlexVectorIiE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!12 = !{!"_ZTS16NvFlexBufferType", !8, i64 0}
!13 = !{!"_ZTSSt6vectorIiSaIiEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!17 = !{!"_ZTSSt6vectorIP17NvFlexExtInstanceSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP17NvFlexExtInstanceSaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!21 = !{!"_ZTSSt6vectorIP18NvFlexExtSoftJointSaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP18NvFlexExtSoftJointSaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!25 = !{!"_ZTS12NvFlexVectorI8XVector4IfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!26 = !{!"_ZTS12NvFlexVectorI8XVector3IfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!27 = !{!"_ZTS12NvFlexVectorIfE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!28 = !{!"_ZTS12NvFlexVectorI5XQuatIfEE", !10, i64 0, !10, i64 8, !10, i64 16, !7, i64 24, !7, i64 28, !12, i64 32}
!29 = !{!"bool", !8, i64 0}
!30 = !{!7, !7, i64 0}
!31 = distinct !{!31, !32}
!32 = !{!"llvm.loop.mustprogress"}
!33 = distinct !{!33, !32}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass