; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @ADC_Enable(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Start_IT(ptr noundef %0) #2 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !9
  %11 = icmp eq ptr %10, inttoptr (i64 1073881088 to ptr)
  br i1 %11, label %17, label %12

12:                                               ; preds = %1
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %13, i32 0, i32 0
  %15 = load ptr, ptr %14, align 8, !tbaa !9
  %16 = icmp eq ptr %15, inttoptr (i64 1073881344 to ptr)
  br label %17

17:                                               ; preds = %12, %1
  %18 = phi i1 [ true, %1 ], [ %16, %12 ]
  %19 = zext i1 %18 to i64
  %20 = select i1 %18, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %21 = call i32 @LL_ADC_GetMultimode(ptr noundef %20)
  store i32 %21, ptr %6, align 4, !tbaa !15
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !9
  %25 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %24)
  %26 = zext i32 %25 to i64
  %27 = icmp eq i64 %26, 0
  br i1 %27, label %28, label %324

28:                                               ; preds = %17
  br label %29

29:                                               ; preds = %28
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 3
  %32 = load i32, ptr %31, align 8, !tbaa !16
  %33 = icmp eq i32 %32, 1
  br i1 %33, label %34, label %35

34:                                               ; preds = %29
  store i32 2, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %327

35:                                               ; preds = %29
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %36, i32 0, i32 3
  store i32 1, ptr %37, align 8, !tbaa !16
  br label %38

38:                                               ; preds = %35
  br label %39

39:                                               ; preds = %38
  br label %40

40:                                               ; preds = %39
  %41 = load ptr, ptr %3, align 8, !tbaa !5
  %42 = call i32 @ADC_Enable(ptr noundef %41)
  store i32 %42, ptr %4, align 4, !tbaa !15
  %43 = load i32, ptr %4, align 4, !tbaa !15
  %44 = icmp eq i32 %43, 0
  br i1 %44, label %45, label %317

45:                                               ; preds = %40
  %46 = load ptr, ptr %3, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %46, i32 0, i32 4
  %48 = load volatile i32, ptr %47, align 4, !tbaa !17
  %49 = zext i32 %48 to i64
  %50 = and i64 %49, -3586
  %51 = or i64 %50, 256
  %52 = trunc i64 %51 to i32
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %53, i32 0, i32 4
  store volatile i32 %52, ptr %54, align 4, !tbaa !17
  %55 = load ptr, ptr %3, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %55, i32 0, i32 0
  %57 = load ptr, ptr %56, align 8, !tbaa !9
  %58 = icmp eq ptr %57, inttoptr (i64 1073881344 to ptr)
  br i1 %58, label %59, label %60

59:                                               ; preds = %45
  br label %64

60:                                               ; preds = %45
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !9
  br label %64

64:                                               ; preds = %60, %59
  %65 = phi ptr [ inttoptr (i64 1073881088 to ptr), %59 ], [ %63, %60 ]
  %66 = load ptr, ptr %3, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %66, i32 0, i32 0
  %68 = load ptr, ptr %67, align 8, !tbaa !9
  %69 = icmp eq ptr %65, %68
  br i1 %69, label %74, label %70

70:                                               ; preds = %64
  %71 = load i32, ptr %6, align 4, !tbaa !15
  %72 = zext i32 %71 to i64
  %73 = icmp eq i64 %72, 0
  br i1 %73, label %74, label %81

74:                                               ; preds = %70, %64
  %75 = load ptr, ptr %3, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %75, i32 0, i32 4
  %77 = load volatile i32, ptr %76, align 4, !tbaa !17
  %78 = zext i32 %77 to i64
  %79 = and i64 %78, -1048577
  %80 = trunc i64 %79 to i32
  store volatile i32 %80, ptr %76, align 4, !tbaa !17
  br label %81

81:                                               ; preds = %74, %70
  %82 = load ptr, ptr %3, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %82, i32 0, i32 4
  %84 = load volatile i32, ptr %83, align 4, !tbaa !17
  %85 = zext i32 %84 to i64
  %86 = and i64 %85, 4096
  %87 = icmp ne i64 %86, 0
  br i1 %87, label %88, label %93

88:                                               ; preds = %81
  %89 = load ptr, ptr %3, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %89, i32 0, i32 5
  %91 = load volatile i32, ptr %90, align 8, !tbaa !18
  %92 = and i32 %91, -7
  store volatile i32 %92, ptr %90, align 8, !tbaa !18
  br label %96

93:                                               ; preds = %81
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %94, i32 0, i32 5
  store volatile i32 0, ptr %95, align 8, !tbaa !18
  br label %96

96:                                               ; preds = %93, %88
  %97 = load ptr, ptr %3, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %97, i32 0, i32 0
  %99 = load ptr, ptr %98, align 8, !tbaa !9
  %100 = getelementptr inbounds %struct.ADC_TypeDef, ptr %99, i32 0, i32 0
  store volatile i32 28, ptr %100, align 4, !tbaa !19
  br label %101

101:                                              ; preds = %96
  %102 = load ptr, ptr %3, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %102, i32 0, i32 3
  store i32 0, ptr %103, align 8, !tbaa !16
  br label %104

104:                                              ; preds = %101
  br label %105

105:                                              ; preds = %104
  %106 = load ptr, ptr %3, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %106, i32 0, i32 0
  %108 = load ptr, ptr %107, align 8, !tbaa !9
  %109 = getelementptr inbounds %struct.ADC_TypeDef, ptr %108, i32 0, i32 1
  %110 = load volatile i32, ptr %109, align 4, !tbaa !21
  %111 = zext i32 %110 to i64
  %112 = and i64 %111, -29
  %113 = trunc i64 %112 to i32
  store volatile i32 %113, ptr %109, align 4, !tbaa !21
  %114 = load ptr, ptr %3, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %114, i32 0, i32 1
  %116 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %115, i32 0, i32 3
  %117 = load i32, ptr %116, align 4, !tbaa !22
  switch i32 %117, label %127 [
    i32 8, label %118
  ]

118:                                              ; preds = %105
  %119 = load ptr, ptr %3, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !9
  %122 = getelementptr inbounds %struct.ADC_TypeDef, ptr %121, i32 0, i32 1
  %123 = load volatile i32, ptr %122, align 4, !tbaa !21
  %124 = zext i32 %123 to i64
  %125 = or i64 %124, 8
  %126 = trunc i64 %125 to i32
  store volatile i32 %126, ptr %122, align 4, !tbaa !21
  br label %136

127:                                              ; preds = %105
  %128 = load ptr, ptr %3, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %128, i32 0, i32 0
  %130 = load ptr, ptr %129, align 8, !tbaa !9
  %131 = getelementptr inbounds %struct.ADC_TypeDef, ptr %130, i32 0, i32 1
  %132 = load volatile i32, ptr %131, align 4, !tbaa !21
  %133 = zext i32 %132 to i64
  %134 = or i64 %133, 4
  %135 = trunc i64 %134 to i32
  store volatile i32 %135, ptr %131, align 4, !tbaa !21
  br label %136

136:                                              ; preds = %127, %118
  %137 = load ptr, ptr %3, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %137, i32 0, i32 1
  %139 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %138, i32 0, i32 12
  %140 = load i32, ptr %139, align 8, !tbaa !23
  %141 = zext i32 %140 to i64
  %142 = icmp eq i64 %141, 0
  br i1 %142, label %143, label %152

143:                                              ; preds = %136
  %144 = load ptr, ptr %3, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %144, i32 0, i32 0
  %146 = load ptr, ptr %145, align 8, !tbaa !9
  %147 = getelementptr inbounds %struct.ADC_TypeDef, ptr %146, i32 0, i32 1
  %148 = load volatile i32, ptr %147, align 4, !tbaa !21
  %149 = zext i32 %148 to i64
  %150 = or i64 %149, 16
  %151 = trunc i64 %150 to i32
  store volatile i32 %151, ptr %147, align 4, !tbaa !21
  br label %152

152:                                              ; preds = %143, %136
  %153 = load ptr, ptr %3, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %153, i32 0, i32 0
  %155 = load ptr, ptr %154, align 8, !tbaa !9
  %156 = icmp eq ptr %155, inttoptr (i64 1073881344 to ptr)
  br i1 %156, label %157, label %158

157:                                              ; preds = %152
  br label %162

158:                                              ; preds = %152
  %159 = load ptr, ptr %3, align 8, !tbaa !5
  %160 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %159, i32 0, i32 0
  %161 = load ptr, ptr %160, align 8, !tbaa !9
  br label %162

162:                                              ; preds = %158, %157
  %163 = phi ptr [ inttoptr (i64 1073881088 to ptr), %157 ], [ %161, %158 ]
  %164 = load ptr, ptr %3, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %164, i32 0, i32 0
  %166 = load ptr, ptr %165, align 8, !tbaa !9
  %167 = icmp eq ptr %163, %166
  br i1 %167, label %180, label %168

168:                                              ; preds = %162
  %169 = load i32, ptr %6, align 4, !tbaa !15
  %170 = zext i32 %169 to i64
  %171 = icmp eq i64 %170, 0
  br i1 %171, label %180, label %172

172:                                              ; preds = %168
  %173 = load i32, ptr %6, align 4, !tbaa !15
  %174 = zext i32 %173 to i64
  %175 = icmp eq i64 %174, 5
  br i1 %175, label %180, label %176

176:                                              ; preds = %172
  %177 = load i32, ptr %6, align 4, !tbaa !15
  %178 = zext i32 %177 to i64
  %179 = icmp eq i64 %178, 9
  br i1 %179, label %180, label %242

180:                                              ; preds = %176, %172, %168, %162
  %181 = load ptr, ptr %3, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %181, i32 0, i32 0
  %183 = load ptr, ptr %182, align 8, !tbaa !9
  %184 = getelementptr inbounds %struct.ADC_TypeDef, ptr %183, i32 0, i32 3
  %185 = load volatile i32, ptr %184, align 4, !tbaa !24
  %186 = zext i32 %185 to i64
  %187 = and i64 %186, 33554432
  %188 = icmp ne i64 %187, 0
  br i1 %188, label %189, label %238

189:                                              ; preds = %180
  %190 = load ptr, ptr %3, align 8, !tbaa !5
  %191 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %190, i32 0, i32 4
  %192 = load volatile i32, ptr %191, align 4, !tbaa !17
  %193 = zext i32 %192 to i64
  %194 = and i64 %193, -8193
  %195 = or i64 %194, 4096
  %196 = trunc i64 %195 to i32
  %197 = load ptr, ptr %3, align 8, !tbaa !5
  %198 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %197, i32 0, i32 4
  store volatile i32 %196, ptr %198, align 4, !tbaa !17
  %199 = load ptr, ptr %3, align 8, !tbaa !5
  %200 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %199, i32 0, i32 1
  %201 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %200, i32 0, i32 3
  %202 = load i32, ptr %201, align 4, !tbaa !22
  switch i32 %202, label %220 [
    i32 8, label %203
  ]

203:                                              ; preds = %189
  %204 = load ptr, ptr %3, align 8, !tbaa !5
  %205 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %204, i32 0, i32 0
  %206 = load ptr, ptr %205, align 8, !tbaa !9
  %207 = getelementptr inbounds %struct.ADC_TypeDef, ptr %206, i32 0, i32 1
  %208 = load volatile i32, ptr %207, align 4, !tbaa !21
  %209 = zext i32 %208 to i64
  %210 = and i64 %209, -33
  %211 = trunc i64 %210 to i32
  store volatile i32 %211, ptr %207, align 4, !tbaa !21
  %212 = load ptr, ptr %3, align 8, !tbaa !5
  %213 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %212, i32 0, i32 0
  %214 = load ptr, ptr %213, align 8, !tbaa !9
  %215 = getelementptr inbounds %struct.ADC_TypeDef, ptr %214, i32 0, i32 1
  %216 = load volatile i32, ptr %215, align 4, !tbaa !21
  %217 = zext i32 %216 to i64
  %218 = or i64 %217, 64
  %219 = trunc i64 %218 to i32
  store volatile i32 %219, ptr %215, align 4, !tbaa !21
  br label %237

220:                                              ; preds = %189
  %221 = load ptr, ptr %3, align 8, !tbaa !5
  %222 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %221, i32 0, i32 0
  %223 = load ptr, ptr %222, align 8, !tbaa !9
  %224 = getelementptr inbounds %struct.ADC_TypeDef, ptr %223, i32 0, i32 1
  %225 = load volatile i32, ptr %224, align 4, !tbaa !21
  %226 = zext i32 %225 to i64
  %227 = and i64 %226, -65
  %228 = trunc i64 %227 to i32
  store volatile i32 %228, ptr %224, align 4, !tbaa !21
  %229 = load ptr, ptr %3, align 8, !tbaa !5
  %230 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %229, i32 0, i32 0
  %231 = load ptr, ptr %230, align 8, !tbaa !9
  %232 = getelementptr inbounds %struct.ADC_TypeDef, ptr %231, i32 0, i32 1
  %233 = load volatile i32, ptr %232, align 4, !tbaa !21
  %234 = zext i32 %233 to i64
  %235 = or i64 %234, 32
  %236 = trunc i64 %235 to i32
  store volatile i32 %236, ptr %232, align 4, !tbaa !21
  br label %237

237:                                              ; preds = %220, %203
  br label %238

238:                                              ; preds = %237, %180
  %239 = load ptr, ptr %3, align 8, !tbaa !5
  %240 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %239, i32 0, i32 0
  %241 = load ptr, ptr %240, align 8, !tbaa !9
  call void @LL_ADC_REG_StartConversion(ptr noundef %241)
  br label %316

242:                                              ; preds = %176
  %243 = load ptr, ptr %3, align 8, !tbaa !5
  %244 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %243, i32 0, i32 4
  %245 = load volatile i32, ptr %244, align 4, !tbaa !17
  %246 = zext i32 %245 to i64
  %247 = or i64 %246, 1048576
  %248 = trunc i64 %247 to i32
  store volatile i32 %248, ptr %244, align 4, !tbaa !17
  %249 = load ptr, ptr %3, align 8, !tbaa !5
  %250 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %249, i32 0, i32 0
  %251 = load ptr, ptr %250, align 8, !tbaa !9
  %252 = icmp eq ptr %251, inttoptr (i64 1073881344 to ptr)
  br i1 %252, label %253, label %254

253:                                              ; preds = %242
  br label %258

254:                                              ; preds = %242
  %255 = load ptr, ptr %3, align 8, !tbaa !5
  %256 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %255, i32 0, i32 0
  %257 = load ptr, ptr %256, align 8, !tbaa !9
  br label %258

258:                                              ; preds = %254, %253
  %259 = phi ptr [ inttoptr (i64 1073881088 to ptr), %253 ], [ %257, %254 ]
  store ptr %259, ptr %5, align 8, !tbaa !5
  %260 = load ptr, ptr %5, align 8, !tbaa !5
  %261 = getelementptr inbounds %struct.ADC_TypeDef, ptr %260, i32 0, i32 3
  %262 = load volatile i32, ptr %261, align 4, !tbaa !24
  %263 = zext i32 %262 to i64
  %264 = and i64 %263, 33554432
  %265 = icmp ne i64 %264, 0
  br i1 %265, label %266, label %315

266:                                              ; preds = %258
  %267 = load ptr, ptr %3, align 8, !tbaa !5
  %268 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %267, i32 0, i32 4
  %269 = load volatile i32, ptr %268, align 4, !tbaa !17
  %270 = zext i32 %269 to i64
  %271 = and i64 %270, -8193
  %272 = or i64 %271, 4096
  %273 = trunc i64 %272 to i32
  %274 = load ptr, ptr %3, align 8, !tbaa !5
  %275 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %274, i32 0, i32 4
  store volatile i32 %273, ptr %275, align 4, !tbaa !17
  %276 = load ptr, ptr %3, align 8, !tbaa !5
  %277 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %276, i32 0, i32 1
  %278 = getelementptr inbounds %struct.ADC_InitTypeDef, ptr %277, i32 0, i32 3
  %279 = load i32, ptr %278, align 4, !tbaa !22
  switch i32 %279, label %297 [
    i32 8, label %280
  ]

280:                                              ; preds = %266
  %281 = load ptr, ptr %3, align 8, !tbaa !5
  %282 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %281, i32 0, i32 0
  %283 = load ptr, ptr %282, align 8, !tbaa !9
  %284 = getelementptr inbounds %struct.ADC_TypeDef, ptr %283, i32 0, i32 1
  %285 = load volatile i32, ptr %284, align 4, !tbaa !21
  %286 = zext i32 %285 to i64
  %287 = and i64 %286, -33
  %288 = trunc i64 %287 to i32
  store volatile i32 %288, ptr %284, align 4, !tbaa !21
  %289 = load ptr, ptr %3, align 8, !tbaa !5
  %290 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %289, i32 0, i32 0
  %291 = load ptr, ptr %290, align 8, !tbaa !9
  %292 = getelementptr inbounds %struct.ADC_TypeDef, ptr %291, i32 0, i32 1
  %293 = load volatile i32, ptr %292, align 4, !tbaa !21
  %294 = zext i32 %293 to i64
  %295 = or i64 %294, 64
  %296 = trunc i64 %295 to i32
  store volatile i32 %296, ptr %292, align 4, !tbaa !21
  br label %314

297:                                              ; preds = %266
  %298 = load ptr, ptr %3, align 8, !tbaa !5
  %299 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %298, i32 0, i32 0
  %300 = load ptr, ptr %299, align 8, !tbaa !9
  %301 = getelementptr inbounds %struct.ADC_TypeDef, ptr %300, i32 0, i32 1
  %302 = load volatile i32, ptr %301, align 4, !tbaa !21
  %303 = zext i32 %302 to i64
  %304 = and i64 %303, -65
  %305 = trunc i64 %304 to i32
  store volatile i32 %305, ptr %301, align 4, !tbaa !21
  %306 = load ptr, ptr %3, align 8, !tbaa !5
  %307 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %306, i32 0, i32 0
  %308 = load ptr, ptr %307, align 8, !tbaa !9
  %309 = getelementptr inbounds %struct.ADC_TypeDef, ptr %308, i32 0, i32 1
  %310 = load volatile i32, ptr %309, align 4, !tbaa !21
  %311 = zext i32 %310 to i64
  %312 = or i64 %311, 32
  %313 = trunc i64 %312 to i32
  store volatile i32 %313, ptr %309, align 4, !tbaa !21
  br label %314

314:                                              ; preds = %297, %280
  br label %315

315:                                              ; preds = %314, %258
  br label %316

316:                                              ; preds = %315, %238
  br label %323

317:                                              ; preds = %40
  br label %318

318:                                              ; preds = %317
  %319 = load ptr, ptr %3, align 8, !tbaa !5
  %320 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %319, i32 0, i32 3
  store i32 0, ptr %320, align 8, !tbaa !16
  br label %321

321:                                              ; preds = %318
  br label %322

322:                                              ; preds = %321
  br label %323

323:                                              ; preds = %322, %316
  br label %325

324:                                              ; preds = %17
  store i32 2, ptr %4, align 4, !tbaa !15
  br label %325

325:                                              ; preds = %324, %323
  %326 = load i32, ptr %4, align 4, !tbaa !15
  store i32 %326, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %327

327:                                              ; preds = %325, %34
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %328 = load i32, ptr %2, align 4
  ret i32 %328
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"", !6, i64 0, !11, i64 8, !6, i64 88, !12, i64 96, !12, i64 100, !12, i64 104, !14, i64 108}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !13, i64 60}
!12 = !{!"int", !7, i64 0}
!13 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!14 = !{!"", !12, i64 0, !12, i64 4}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !12, i64 96}
!17 = !{!10, !12, i64 100}
!18 = !{!10, !12, i64 104}
!19 = !{!20, !12, i64 0}
!20 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !12, i64 96, !12, i64 100, !12, i64 104, !12, i64 108, !7, i64 112, !12, i64 128, !12, i64 132, !12, i64 136, !12, i64 140, !7, i64 144, !12, i64 160, !12, i64 164, !12, i64 168, !12, i64 172, !12, i64 176, !12, i64 180, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200}
!21 = !{!20, !12, i64 4}
!22 = !{!10, !12, i64 20}
!23 = !{!10, !12, i64 56}
!24 = !{!20, !12, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @ADC_Enable(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Start_IT(ptr noundef %0) local_unnamed_addr #1 {
  %2 = load ptr, ptr %0, align 8, !tbaa !5
  %3 = icmp eq ptr %2, inttoptr (i64 1073881088 to ptr)
  %4 = icmp eq ptr %2, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %3, %4
  %5 = select i1 %spec.select, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %6 = tail call i32 @LL_ADC_GetMultimode(ptr noundef nonnull %5)
  %7 = load ptr, ptr %0, align 8, !tbaa !5
  %8 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %7)
  %9 = icmp eq i32 %8, 0
  br i1 %9, label %10, label %84

10:                                               ; preds = %1
  %11 = getelementptr inbounds i8, ptr %0, i64 96
  %12 = load i32, ptr %11, align 8, !tbaa !14
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %84, label %14

14:                                               ; preds = %10
  store i32 1, ptr %11, align 8, !tbaa !14
  %15 = tail call i32 @ADC_Enable(ptr noundef nonnull %0)
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %83

17:                                               ; preds = %14
  %18 = getelementptr inbounds i8, ptr %0, i64 100
  %19 = load volatile i32, ptr %18, align 4, !tbaa !15
  %20 = and i32 %19, -3842
  %21 = or disjoint i32 %20, 256
  store volatile i32 %21, ptr %18, align 4, !tbaa !15
  %22 = load ptr, ptr %0, align 8, !tbaa !5
  %23 = icmp eq ptr %22, inttoptr (i64 1073881344 to ptr)
  %spec.select74 = select i1 %23, ptr inttoptr (i64 1073881088 to ptr), ptr %22
  %24 = icmp eq ptr %spec.select74, %22
  %25 = freeze i1 %24
  %26 = icmp eq i32 %6, 0
  %or.cond = select i1 %25, i1 true, i1 %26
  br i1 %or.cond, label %27, label %30

27:                                               ; preds = %17
  %28 = load volatile i32, ptr %18, align 4, !tbaa !15
  %29 = and i32 %28, -1048577
  store volatile i32 %29, ptr %18, align 4, !tbaa !15
  br label %30

30:                                               ; preds = %17, %27
  %31 = load volatile i32, ptr %18, align 4, !tbaa !15
  %32 = and i32 %31, 4096
  %.not = icmp eq i32 %32, 0
  %33 = getelementptr inbounds i8, ptr %0, i64 104
  br i1 %.not, label %37, label %34

34:                                               ; preds = %30
  %35 = load volatile i32, ptr %33, align 8, !tbaa !16
  %36 = and i32 %35, -7
  br label %37

37:                                               ; preds = %30, %34
  %.sink = phi i32 [ %36, %34 ], [ 0, %30 ]
  store volatile i32 %.sink, ptr %33, align 8, !tbaa !16
  store volatile i32 28, ptr %22, align 4, !tbaa !17
  store i32 0, ptr %11, align 8, !tbaa !14
  %38 = getelementptr inbounds i8, ptr %22, i64 4
  %39 = load volatile i32, ptr %38, align 4, !tbaa !19
  %40 = and i32 %39, -29
  store volatile i32 %40, ptr %38, align 4, !tbaa !19
  %41 = getelementptr inbounds i8, ptr %0, i64 20
  %42 = load i32, ptr %41, align 4, !tbaa !20
  %cond = icmp eq i32 %42, 8
  %. = select i1 %cond, i32 8, i32 4
  %43 = load volatile i32, ptr %38, align 4, !tbaa !19
  %44 = or i32 %43, %.
  store volatile i32 %44, ptr %38, align 4, !tbaa !19
  %45 = getelementptr inbounds i8, ptr %0, i64 56
  %46 = load i32, ptr %45, align 8, !tbaa !21
  %47 = icmp eq i32 %46, 0
  br i1 %47, label %48, label %51

48:                                               ; preds = %37
  %49 = load volatile i32, ptr %38, align 4, !tbaa !19
  %50 = or i32 %49, 16
  store volatile i32 %50, ptr %38, align 4, !tbaa !19
  br label %51

51:                                               ; preds = %48, %37
  br i1 %25, label %52, label %switch.early.test

switch.early.test:                                ; preds = %51
  switch i32 %6, label %64 [
    i32 9, label %52
    i32 5, label %52
    i32 0, label %52
  ]

52:                                               ; preds = %switch.early.test, %switch.early.test, %switch.early.test, %51
  %53 = getelementptr inbounds i8, ptr %22, i64 12
  %54 = load volatile i32, ptr %53, align 4, !tbaa !22
  %55 = and i32 %54, 33554432
  %.not73 = icmp eq i32 %55, 0
  br i1 %.not73, label %63, label %.sink.split

.sink.split:                                      ; preds = %52
  %56 = load volatile i32, ptr %18, align 4, !tbaa !15
  %57 = and i32 %56, -12289
  %58 = or disjoint i32 %57, 4096
  store volatile i32 %58, ptr %18, align 4, !tbaa !15
  %59 = load volatile i32, ptr %38, align 4, !tbaa !19
  %.85 = select i1 %cond, i32 -33, i32 -65
  %.86 = select i1 %cond, i32 64, i32 32
  %60 = and i32 %59, %.85
  store volatile i32 %60, ptr %38, align 4, !tbaa !19
  %61 = load volatile i32, ptr %38, align 4, !tbaa !19
  %62 = or i32 %61, %.86
  store volatile i32 %62, ptr %38, align 4, !tbaa !19
  br label %63

63:                                               ; preds = %.sink.split, %52
  tail call void @LL_ADC_REG_StartConversion(ptr noundef nonnull %22)
  br label %84

64:                                               ; preds = %switch.early.test
  %65 = load volatile i32, ptr %18, align 4, !tbaa !15
  %66 = or i32 %65, 1048576
  store volatile i32 %66, ptr %18, align 4, !tbaa !15
  %67 = getelementptr inbounds i8, ptr %spec.select74, i64 12
  %68 = load volatile i32, ptr %67, align 4, !tbaa !22
  %69 = and i32 %68, 33554432
  %.not72 = icmp eq i32 %69, 0
  br i1 %.not72, label %84, label %70

70:                                               ; preds = %64
  %71 = load volatile i32, ptr %18, align 4, !tbaa !15
  %72 = and i32 %71, -12289
  %73 = or disjoint i32 %72, 4096
  store volatile i32 %73, ptr %18, align 4, !tbaa !15
  %74 = load volatile i32, ptr %38, align 4, !tbaa !19
  br i1 %cond, label %75, label %79

75:                                               ; preds = %70
  %76 = and i32 %74, -33
  store volatile i32 %76, ptr %38, align 4, !tbaa !19
  %77 = load volatile i32, ptr %38, align 4, !tbaa !19
  %78 = or i32 %77, 64
  store volatile i32 %78, ptr %38, align 4, !tbaa !19
  br label %84

79:                                               ; preds = %70
  %80 = and i32 %74, -65
  store volatile i32 %80, ptr %38, align 4, !tbaa !19
  %81 = load volatile i32, ptr %38, align 4, !tbaa !19
  %82 = or i32 %81, 32
  store volatile i32 %82, ptr %38, align 4, !tbaa !19
  br label %84

83:                                               ; preds = %14
  store i32 0, ptr %11, align 8, !tbaa !14
  br label %84

84:                                               ; preds = %63, %75, %79, %64, %83, %1, %10
  %.0 = phi i32 [ 2, %10 ], [ 0, %63 ], [ 0, %75 ], [ 0, %79 ], [ 0, %64 ], [ %15, %83 ], [ 2, %1 ]
  ret i32 %.0
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 96}
!15 = !{!6, !11, i64 100}
!16 = !{!6, !11, i64 104}
!17 = !{!18, !11, i64 0}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!19 = !{!18, !11, i64 4}
!20 = !{!6, !11, i64 20}
!21 = !{!6, !11, i64 56}
!22 = !{!18, !11, i64 12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass