; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (MultiModeConfigChannel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.ADC_MultiModeTypeDef = type { i32, i32, i32 }
%struct.ADC_Common_TypeDef = type { i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADCEx_MultiModeConfigChannel(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca %struct.ADC_HandleTypeDef, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 120, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %11, i32 0, i32 0
  %13 = load i32, ptr %12, align 4, !tbaa !11
  %14 = zext i32 %13 to i64
  %15 = icmp ne i64 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %2
  br label %17

17:                                               ; preds = %16, %2
  br label %18

18:                                               ; preds = %17
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %19, i32 0, i32 3
  %21 = load i32, ptr %20, align 8, !tbaa !13
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 2, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %199

24:                                               ; preds = %18
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %25, i32 0, i32 3
  store i32 1, ptr %26, align 8, !tbaa !13
  br label %27

27:                                               ; preds = %24
  br label %28

28:                                               ; preds = %27
  br label %29

29:                                               ; preds = %28
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %30, i32 0, i32 0
  %32 = load ptr, ptr %31, align 8, !tbaa !18
  %33 = icmp eq ptr %32, inttoptr (i64 1073881088 to ptr)
  br i1 %33, label %34, label %36

34:                                               ; preds = %29
  %35 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  store ptr inttoptr (i64 1073881344 to ptr), ptr %35, align 8, !tbaa !18
  br label %38

36:                                               ; preds = %29
  %37 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  store ptr null, ptr %37, align 8, !tbaa !18
  br label %38

38:                                               ; preds = %36, %34
  %39 = phi ptr [ inttoptr (i64 1073881344 to ptr), %34 ], [ null, %36 ]
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %41 = load ptr, ptr %40, align 8, !tbaa !18
  %42 = icmp eq ptr %41, null
  br i1 %42, label %43, label %55

43:                                               ; preds = %38
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %44, i32 0, i32 4
  %46 = load volatile i32, ptr %45, align 4, !tbaa !19
  %47 = zext i32 %46 to i64
  %48 = or i64 %47, 32
  %49 = trunc i64 %48 to i32
  store volatile i32 %49, ptr %45, align 4, !tbaa !19
  br label %50

50:                                               ; preds = %43
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %51, i32 0, i32 3
  store i32 0, ptr %52, align 8, !tbaa !13
  br label %53

53:                                               ; preds = %50
  br label %54

54:                                               ; preds = %53
  store i32 1, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %199

55:                                               ; preds = %38
  %56 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %8, i32 0, i32 0
  %57 = load ptr, ptr %56, align 8, !tbaa !18
  %58 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %57)
  store i32 %58, ptr %9, align 4, !tbaa !9
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !18
  %62 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %61)
  %63 = zext i32 %62 to i64
  %64 = icmp eq i64 %63, 0
  br i1 %64, label %65, label %185

65:                                               ; preds = %55
  %66 = load i32, ptr %9, align 4, !tbaa !9
  %67 = zext i32 %66 to i64
  %68 = icmp eq i64 %67, 0
  br i1 %68, label %69, label %185

69:                                               ; preds = %65
  %70 = load ptr, ptr %4, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %70, i32 0, i32 0
  %72 = load ptr, ptr %71, align 8, !tbaa !18
  %73 = icmp eq ptr %72, inttoptr (i64 1073881088 to ptr)
  br i1 %73, label %79, label %74

74:                                               ; preds = %69
  %75 = load ptr, ptr %4, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %75, i32 0, i32 0
  %77 = load ptr, ptr %76, align 8, !tbaa !18
  %78 = icmp eq ptr %77, inttoptr (i64 1073881344 to ptr)
  br label %79

79:                                               ; preds = %74, %69
  %80 = phi i1 [ true, %69 ], [ %78, %74 ]
  %81 = zext i1 %80 to i64
  %82 = select i1 %80, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  store ptr %82, ptr %7, align 8, !tbaa !5
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %83, i32 0, i32 0
  %85 = load i32, ptr %84, align 4, !tbaa !11
  %86 = zext i32 %85 to i64
  %87 = icmp ne i64 %86, 0
  br i1 %87, label %88, label %145

88:                                               ; preds = %79
  %89 = load ptr, ptr %7, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %89, i32 0, i32 2
  %91 = load volatile i32, ptr %90, align 4, !tbaa !20
  %92 = zext i32 %91 to i64
  %93 = and i64 %92, -49153
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %94, i32 0, i32 1
  %96 = load i32, ptr %95, align 4, !tbaa !22
  %97 = zext i32 %96 to i64
  %98 = or i64 %93, %97
  %99 = trunc i64 %98 to i32
  %100 = load ptr, ptr %7, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %100, i32 0, i32 2
  store volatile i32 %99, ptr %101, align 4, !tbaa !20
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !18
  %105 = icmp eq ptr %104, inttoptr (i64 1073881088 to ptr)
  br i1 %105, label %111, label %106

106:                                              ; preds = %88
  %107 = load ptr, ptr %4, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %107, i32 0, i32 0
  %109 = load ptr, ptr %108, align 8, !tbaa !18
  %110 = icmp eq ptr %109, inttoptr (i64 1073881344 to ptr)
  br label %111

111:                                              ; preds = %106, %88
  %112 = phi i1 [ true, %88 ], [ %110, %106 ]
  %113 = zext i1 %112 to i64
  %114 = select i1 %112, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %115 = icmp eq ptr %114, inttoptr (i64 1073881856 to ptr)
  br i1 %115, label %116, label %120

116:                                              ; preds = %111
  %117 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %118 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %119 = or i32 %117, %118
  br label %122

120:                                              ; preds = %111
  %121 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %122

122:                                              ; preds = %120, %116
  %123 = phi i32 [ %119, %116 ], [ %121, %120 ]
  %124 = zext i32 %123 to i64
  %125 = icmp eq i64 %124, 0
  br i1 %125, label %126, label %144

126:                                              ; preds = %122
  %127 = load ptr, ptr %7, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %127, i32 0, i32 2
  %129 = load volatile i32, ptr %128, align 4, !tbaa !20
  %130 = zext i32 %129 to i64
  %131 = and i64 %130, -3872
  %132 = load ptr, ptr %5, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %132, i32 0, i32 0
  %134 = load i32, ptr %133, align 4, !tbaa !11
  %135 = load ptr, ptr %5, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.ADC_MultiModeTypeDef, ptr %135, i32 0, i32 2
  %137 = load i32, ptr %136, align 4, !tbaa !23
  %138 = or i32 %134, %137
  %139 = zext i32 %138 to i64
  %140 = or i64 %131, %139
  %141 = trunc i64 %140 to i32
  %142 = load ptr, ptr %7, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %142, i32 0, i32 2
  store volatile i32 %141, ptr %143, align 4, !tbaa !20
  br label %144

144:                                              ; preds = %126, %122
  br label %184

145:                                              ; preds = %79
  %146 = load ptr, ptr %7, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %146, i32 0, i32 2
  %148 = load volatile i32, ptr %147, align 4, !tbaa !20
  %149 = zext i32 %148 to i64
  %150 = and i64 %149, -49153
  %151 = trunc i64 %150 to i32
  store volatile i32 %151, ptr %147, align 4, !tbaa !20
  %152 = load ptr, ptr %4, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !18
  %155 = icmp eq ptr %154, inttoptr (i64 1073881088 to ptr)
  br i1 %155, label %161, label %156

156:                                              ; preds = %145
  %157 = load ptr, ptr %4, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %157, i32 0, i32 0
  %159 = load ptr, ptr %158, align 8, !tbaa !18
  %160 = icmp eq ptr %159, inttoptr (i64 1073881344 to ptr)
  br label %161

161:                                              ; preds = %156, %145
  %162 = phi i1 [ true, %145 ], [ %160, %156 ]
  %163 = zext i1 %162 to i64
  %164 = select i1 %162, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %165 = icmp eq ptr %164, inttoptr (i64 1073881856 to ptr)
  br i1 %165, label %166, label %170

166:                                              ; preds = %161
  %167 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881088 to ptr))
  %168 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1073881344 to ptr))
  %169 = or i32 %167, %168
  br label %172

170:                                              ; preds = %161
  %171 = call i32 @LL_ADC_IsEnabled(ptr noundef inttoptr (i64 1476550656 to ptr))
  br label %172

172:                                              ; preds = %170, %166
  %173 = phi i32 [ %169, %166 ], [ %171, %170 ]
  %174 = zext i32 %173 to i64
  %175 = icmp eq i64 %174, 0
  br i1 %175, label %176, label %183

176:                                              ; preds = %172
  %177 = load ptr, ptr %7, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.ADC_Common_TypeDef, ptr %177, i32 0, i32 2
  %179 = load volatile i32, ptr %178, align 4, !tbaa !20
  %180 = zext i32 %179 to i64
  %181 = and i64 %180, -3872
  %182 = trunc i64 %181 to i32
  store volatile i32 %182, ptr %178, align 4, !tbaa !20
  br label %183

183:                                              ; preds = %176, %172
  br label %184

184:                                              ; preds = %183, %144
  br label %192

185:                                              ; preds = %65, %55
  %186 = load ptr, ptr %4, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %186, i32 0, i32 4
  %188 = load volatile i32, ptr %187, align 4, !tbaa !19
  %189 = zext i32 %188 to i64
  %190 = or i64 %189, 32
  %191 = trunc i64 %190 to i32
  store volatile i32 %191, ptr %187, align 4, !tbaa !19
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %192

192:                                              ; preds = %185, %184
  br label %193

193:                                              ; preds = %192
  %194 = load ptr, ptr %4, align 8, !tbaa !5
  %195 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %194, i32 0, i32 3
  store i32 0, ptr %195, align 8, !tbaa !13
  br label %196

196:                                              ; preds = %193
  br label %197

197:                                              ; preds = %196
  %198 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %198, ptr %3, align 4
  store i32 1, ptr %10, align 4
  br label %199

199:                                              ; preds = %197, %54, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 120, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %200 = load i32, ptr %3, align 4
  ret i32 %200
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!13 = !{!14, !10, i64 96}
!14 = !{!"", !6, i64 0, !15, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !17, i64 108}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !16, i64 60}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!17 = !{!"", !10, i64 0, !10, i64 4}
!18 = !{!14, !6, i64 0}
!19 = !{!14, !10, i64 100}
!20 = !{!21, !10, i64 8}
!21 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16}
!22 = !{!12, !10, i64 4}
!23 = !{!12, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_IsEnabled(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_ADCEx_MultiModeConfigChannel(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #1 {
  %3 = getelementptr inbounds i8, ptr %0, i64 96
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %64, label %6

6:                                                ; preds = %2
  store i32 1, ptr %3, align 8, !tbaa !5
  %7 = load ptr, ptr %0, align 8, !tbaa !14
  %.not = icmp eq ptr %7, inttoptr (i64 1073881088 to ptr)
  br i1 %.not, label %12, label %8

8:                                                ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 100
  %10 = load volatile i32, ptr %9, align 4, !tbaa !15
  %11 = or i32 %10, 32
  store volatile i32 %11, ptr %9, align 4, !tbaa !15
  br label %.sink.split

12:                                               ; preds = %6
  %13 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %14 = load ptr, ptr %0, align 8, !tbaa !14
  %15 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %14)
  %16 = icmp eq i32 %15, 0
  %17 = icmp eq i32 %13, 0
  %or.cond = select i1 %16, i1 %17, i1 false
  br i1 %or.cond, label %18, label %60

18:                                               ; preds = %12
  %19 = load ptr, ptr %0, align 8, !tbaa !14
  %20 = icmp eq ptr %19, inttoptr (i64 1073881088 to ptr)
  %21 = icmp eq ptr %19, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %20, %21
  %22 = load i32, ptr %1, align 4, !tbaa !16
  %.not34 = icmp eq i32 %22, 0
  %23 = select i1 %spec.select, ptr inttoptr (i64 1073881864 to ptr), ptr inttoptr (i64 1476551432 to ptr)
  %24 = load volatile i32, ptr %23, align 8, !tbaa !18
  %25 = and i32 %24, -49153
  br i1 %.not34, label %47, label %26

26:                                               ; preds = %18
  %27 = getelementptr inbounds i8, ptr %1, i64 4
  %28 = load i32, ptr %27, align 4, !tbaa !20
  %29 = or i32 %25, %28
  store volatile i32 %29, ptr %23, align 8, !tbaa !18
  %magicptr = ptrtoint ptr %19 to i64
  switch i64 %magicptr, label %34 [
    i64 1073881344, label %30
    i64 1073881088, label %30
  ]

30:                                               ; preds = %26, %26
  %31 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %32 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %33 = or i32 %32, %31
  br label %36

34:                                               ; preds = %26
  %35 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %36

36:                                               ; preds = %34, %30
  %37 = phi i32 [ %33, %30 ], [ %35, %34 ]
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %39, label %.sink.split

39:                                               ; preds = %36
  %40 = load volatile i32, ptr %23, align 8, !tbaa !18
  %41 = and i32 %40, -3872
  %42 = load i32, ptr %1, align 4, !tbaa !16
  %43 = getelementptr inbounds i8, ptr %1, i64 8
  %44 = load i32, ptr %43, align 4, !tbaa !21
  %45 = or i32 %41, %42
  %46 = or i32 %45, %44
  store volatile i32 %46, ptr %23, align 8, !tbaa !18
  br label %.sink.split

47:                                               ; preds = %18
  store volatile i32 %25, ptr %23, align 8, !tbaa !18
  %magicptr37 = ptrtoint ptr %19 to i64
  switch i64 %magicptr37, label %52 [
    i64 1073881344, label %48
    i64 1073881088, label %48
  ]

48:                                               ; preds = %47, %47
  %49 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881088 to ptr))
  %50 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1073881344 to ptr))
  %51 = or i32 %50, %49
  br label %54

52:                                               ; preds = %47
  %53 = tail call i32 @LL_ADC_IsEnabled(ptr noundef nonnull inttoptr (i64 1476550656 to ptr))
  br label %54

54:                                               ; preds = %52, %48
  %55 = phi i32 [ %51, %48 ], [ %53, %52 ]
  %56 = icmp eq i32 %55, 0
  br i1 %56, label %57, label %.sink.split

57:                                               ; preds = %54
  %58 = load volatile i32, ptr %23, align 8, !tbaa !18
  %59 = and i32 %58, -3872
  store volatile i32 %59, ptr %23, align 8, !tbaa !18
  br label %.sink.split

60:                                               ; preds = %12
  %61 = getelementptr inbounds i8, ptr %0, i64 100
  %62 = load volatile i32, ptr %61, align 4, !tbaa !15
  %63 = or i32 %62, 32
  store volatile i32 %63, ptr %61, align 4, !tbaa !15
  br label %.sink.split

.sink.split:                                      ; preds = %39, %36, %57, %54, %60, %8
  %.0.ph = phi i32 [ 1, %8 ], [ 0, %39 ], [ 0, %36 ], [ 0, %57 ], [ 0, %54 ], [ 1, %60 ]
  store i32 0, ptr %3, align 8, !tbaa !5
  br label %64

64:                                               ; preds = %.sink.split, %2
  %.0 = phi i32 [ 2, %2 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !7, i64 0}
!15 = !{!6, !11, i64 100}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!18 = !{!19, !11, i64 8}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16}
!20 = !{!17, !11, i64 4}
!21 = !{!17, !11, i64 8}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass