; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %10, i32 0, i32 1
  %12 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 4, !tbaa !13
  %14 = zext i32 %13 to i64
  %15 = icmp eq i64 %14, 0
  br i1 %15, label %16, label %31

16:                                               ; preds = %3
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %17, i32 0, i32 1
  %19 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %18, i32 0, i32 0
  %20 = load i32, ptr %19, align 8, !tbaa !16
  %21 = zext i32 %20 to i64
  %22 = icmp eq i64 %21, 4194304
  br i1 %22, label %23, label %31

23:                                               ; preds = %16
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %24, i32 0, i32 14
  store volatile i32 4, ptr %25, align 4, !tbaa !17
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = load i16, ptr %7, align 2, !tbaa !9
  %30 = call i32 @HAL_SPI_TransmitReceive_DMA(ptr noundef %26, ptr noundef %27, ptr noundef %28, i16 noundef zeroext %29)
  store i32 %30, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

31:                                               ; preds = %16, %3
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %33, i32 0, i32 13
  %35 = load i32, ptr %34, align 8, !tbaa !18
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

38:                                               ; preds = %32
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %39, i32 0, i32 13
  store i32 1, ptr %40, align 8, !tbaa !18
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %44, i32 0, i32 14
  %46 = load volatile i32, ptr %45, align 4, !tbaa !17
  %47 = icmp ne i32 %46, 1
  br i1 %47, label %48, label %55

48:                                               ; preds = %43
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %49

49:                                               ; preds = %48
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %50, i32 0, i32 13
  store i32 0, ptr %51, align 8, !tbaa !18
  br label %52

52:                                               ; preds = %49
  br label %53

53:                                               ; preds = %52
  %54 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %54, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

55:                                               ; preds = %43
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = icmp eq ptr %56, null
  br i1 %57, label %62, label %58

58:                                               ; preds = %55
  %59 = load i16, ptr %7, align 2, !tbaa !9
  %60 = zext i16 %59 to i64
  %61 = icmp eq i64 %60, 0
  br i1 %61, label %62, label %69

62:                                               ; preds = %58, %55
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %63

63:                                               ; preds = %62
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %64, i32 0, i32 13
  store i32 0, ptr %65, align 8, !tbaa !18
  br label %66

66:                                               ; preds = %63
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %68, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

69:                                               ; preds = %58
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %70, i32 0, i32 14
  store volatile i32 4, ptr %71, align 4, !tbaa !17
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %72, i32 0, i32 15
  store volatile i32 0, ptr %73, align 8, !tbaa !19
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %75, i32 0, i32 5
  store ptr %74, ptr %76, align 8, !tbaa !20
  %77 = load i16, ptr %7, align 2, !tbaa !9
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %78, i32 0, i32 6
  store i16 %77, ptr %79, align 8, !tbaa !21
  %80 = load i16, ptr %7, align 2, !tbaa !9
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %81, i32 0, i32 7
  store volatile i16 %80, ptr %82, align 2, !tbaa !22
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %83, i32 0, i32 9
  store ptr null, ptr %84, align 8, !tbaa !23
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %85, i32 0, i32 10
  store ptr null, ptr %86, align 8, !tbaa !24
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %87, i32 0, i32 3
  store i16 0, ptr %88, align 8, !tbaa !25
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %89, i32 0, i32 4
  store volatile i16 0, ptr %90, align 2, !tbaa !26
  %91 = load ptr, ptr %5, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %91, i32 0, i32 1
  %93 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %92, i32 0, i32 1
  %94 = load i32, ptr %93, align 4, !tbaa !13
  %95 = zext i32 %94 to i64
  %96 = icmp eq i64 %95, 393216
  br i1 %96, label %97, label %106

97:                                               ; preds = %69
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %98, i32 0, i32 0
  %100 = load ptr, ptr %99, align 8, !tbaa !27
  %101 = getelementptr inbounds %struct.SPI_TypeDef, ptr %100, i32 0, i32 0
  %102 = load volatile i32, ptr %101, align 4, !tbaa !28
  %103 = zext i32 %102 to i64
  %104 = and i64 %103, -2049
  %105 = trunc i64 %104 to i32
  store volatile i32 %105, ptr %101, align 4, !tbaa !28
  br label %106

106:                                              ; preds = %97, %69
  %107 = load ptr, ptr %5, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %107, i32 0, i32 1
  %109 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %108, i32 0, i32 2
  %110 = load i32, ptr %109, align 8, !tbaa !30
  %111 = zext i32 %110 to i64
  %112 = icmp ugt i64 %111, 15
  br i1 %112, label %113, label %121

113:                                              ; preds = %106
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %114, i32 0, i32 12
  %116 = load ptr, ptr %115, align 8, !tbaa !31
  %117 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %116, i32 0, i32 1
  %118 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %117, i32 0, i32 5
  %119 = load i32, ptr %118, align 4, !tbaa !32
  %120 = icmp ne i32 %119, 16384
  br i1 %120, label %144, label %121

121:                                              ; preds = %113, %106
  %122 = load ptr, ptr %5, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %122, i32 0, i32 1
  %124 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %123, i32 0, i32 2
  %125 = load i32, ptr %124, align 8, !tbaa !30
  %126 = zext i32 %125 to i64
  %127 = icmp ugt i64 %126, 7
  br i1 %127, label %128, label %151

128:                                              ; preds = %121
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %129, i32 0, i32 12
  %131 = load ptr, ptr %130, align 8, !tbaa !31
  %132 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %131, i32 0, i32 1
  %133 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %132, i32 0, i32 5
  %134 = load i32, ptr %133, align 4, !tbaa !32
  %135 = icmp ne i32 %134, 8192
  br i1 %135, label %136, label %151

136:                                              ; preds = %128
  %137 = load ptr, ptr %5, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %137, i32 0, i32 12
  %139 = load ptr, ptr %138, align 8, !tbaa !31
  %140 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %139, i32 0, i32 1
  %141 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %140, i32 0, i32 5
  %142 = load i32, ptr %141, align 4, !tbaa !32
  %143 = icmp ne i32 %142, 16384
  br i1 %143, label %144, label %151

144:                                              ; preds = %136, %113
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %145

145:                                              ; preds = %144
  %146 = load ptr, ptr %5, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %146, i32 0, i32 13
  store i32 0, ptr %147, align 8, !tbaa !18
  br label %148

148:                                              ; preds = %145
  br label %149

149:                                              ; preds = %148
  %150 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %150, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

151:                                              ; preds = %136, %128, %121
  %152 = load ptr, ptr %5, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !27
  %155 = getelementptr inbounds %struct.SPI_TypeDef, ptr %154, i32 0, i32 2
  %156 = load volatile i32, ptr %155, align 4, !tbaa !35
  %157 = zext i32 %156 to i64
  %158 = and i64 %157, -16385
  %159 = trunc i64 %158 to i32
  store volatile i32 %159, ptr %155, align 4, !tbaa !35
  %160 = load ptr, ptr %5, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %160, i32 0, i32 1
  %162 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %161, i32 0, i32 2
  %163 = load i32, ptr %162, align 8, !tbaa !30
  %164 = zext i32 %163 to i64
  %165 = icmp ule i64 %164, 7
  br i1 %165, label %166, label %203

166:                                              ; preds = %151
  %167 = load ptr, ptr %5, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %167, i32 0, i32 12
  %169 = load ptr, ptr %168, align 8, !tbaa !31
  %170 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %169, i32 0, i32 1
  %171 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %170, i32 0, i32 5
  %172 = load i32, ptr %171, align 4, !tbaa !32
  %173 = icmp eq i32 %172, 8192
  br i1 %173, label %174, label %184

174:                                              ; preds = %166
  %175 = load ptr, ptr %5, align 8, !tbaa !5
  %176 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %175, i32 0, i32 7
  %177 = load volatile i16, ptr %176, align 2, !tbaa !22
  %178 = zext i16 %177 to i32
  %179 = add nsw i32 %178, 1
  %180 = ashr i32 %179, 1
  %181 = trunc i32 %180 to i16
  %182 = load ptr, ptr %5, align 8, !tbaa !5
  %183 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %182, i32 0, i32 7
  store volatile i16 %181, ptr %183, align 2, !tbaa !22
  br label %184

184:                                              ; preds = %174, %166
  %185 = load ptr, ptr %5, align 8, !tbaa !5
  %186 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %185, i32 0, i32 12
  %187 = load ptr, ptr %186, align 8, !tbaa !31
  %188 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %187, i32 0, i32 1
  %189 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %188, i32 0, i32 5
  %190 = load i32, ptr %189, align 4, !tbaa !32
  %191 = icmp eq i32 %190, 16384
  br i1 %191, label %192, label %202

192:                                              ; preds = %184
  %193 = load ptr, ptr %5, align 8, !tbaa !5
  %194 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %193, i32 0, i32 7
  %195 = load volatile i16, ptr %194, align 2, !tbaa !22
  %196 = zext i16 %195 to i32
  %197 = add nsw i32 %196, 3
  %198 = ashr i32 %197, 2
  %199 = trunc i32 %198 to i16
  %200 = load ptr, ptr %5, align 8, !tbaa !5
  %201 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %200, i32 0, i32 7
  store volatile i16 %199, ptr %201, align 2, !tbaa !22
  br label %202

202:                                              ; preds = %192, %184
  br label %231

203:                                              ; preds = %151
  %204 = load ptr, ptr %5, align 8, !tbaa !5
  %205 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %204, i32 0, i32 1
  %206 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %205, i32 0, i32 2
  %207 = load i32, ptr %206, align 8, !tbaa !30
  %208 = zext i32 %207 to i64
  %209 = icmp ule i64 %208, 15
  br i1 %209, label %210, label %229

210:                                              ; preds = %203
  %211 = load ptr, ptr %5, align 8, !tbaa !5
  %212 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %211, i32 0, i32 12
  %213 = load ptr, ptr %212, align 8, !tbaa !31
  %214 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %213, i32 0, i32 1
  %215 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %214, i32 0, i32 5
  %216 = load i32, ptr %215, align 4, !tbaa !32
  %217 = icmp eq i32 %216, 16384
  br i1 %217, label %218, label %228

218:                                              ; preds = %210
  %219 = load ptr, ptr %5, align 8, !tbaa !5
  %220 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %219, i32 0, i32 7
  %221 = load volatile i16, ptr %220, align 2, !tbaa !22
  %222 = zext i16 %221 to i32
  %223 = add nsw i32 %222, 1
  %224 = ashr i32 %223, 1
  %225 = trunc i32 %224 to i16
  %226 = load ptr, ptr %5, align 8, !tbaa !5
  %227 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %226, i32 0, i32 7
  store volatile i16 %225, ptr %227, align 2, !tbaa !22
  br label %228

228:                                              ; preds = %218, %210
  br label %230

229:                                              ; preds = %203
  br label %230

230:                                              ; preds = %229, %228
  br label %231

231:                                              ; preds = %230, %202
  %232 = load ptr, ptr %5, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %232, i32 0, i32 12
  %234 = load ptr, ptr %233, align 8, !tbaa !31
  %235 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %234, i32 0, i32 6
  store ptr @SPI_DMAHalfReceiveCplt, ptr %235, align 8, !tbaa !36
  %236 = load ptr, ptr %5, align 8, !tbaa !5
  %237 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %236, i32 0, i32 12
  %238 = load ptr, ptr %237, align 8, !tbaa !31
  %239 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %238, i32 0, i32 5
  store ptr @SPI_DMAReceiveCplt, ptr %239, align 8, !tbaa !37
  %240 = load ptr, ptr %5, align 8, !tbaa !5
  %241 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %240, i32 0, i32 12
  %242 = load ptr, ptr %241, align 8, !tbaa !31
  %243 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %242, i32 0, i32 9
  store ptr @SPI_DMAError, ptr %243, align 8, !tbaa !38
  %244 = load ptr, ptr %5, align 8, !tbaa !5
  %245 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %244, i32 0, i32 12
  %246 = load ptr, ptr %245, align 8, !tbaa !31
  %247 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %246, i32 0, i32 10
  store ptr null, ptr %247, align 8, !tbaa !39
  %248 = load ptr, ptr %5, align 8, !tbaa !5
  %249 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %248, i32 0, i32 12
  %250 = load ptr, ptr %249, align 8, !tbaa !31
  %251 = load ptr, ptr %5, align 8, !tbaa !5
  %252 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %251, i32 0, i32 0
  %253 = load ptr, ptr %252, align 8, !tbaa !27
  %254 = getelementptr inbounds %struct.SPI_TypeDef, ptr %253, i32 0, i32 10
  %255 = ptrtoint ptr %254 to i32
  %256 = load ptr, ptr %5, align 8, !tbaa !5
  %257 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %256, i32 0, i32 5
  %258 = load ptr, ptr %257, align 8, !tbaa !20
  %259 = ptrtoint ptr %258 to i32
  %260 = load ptr, ptr %5, align 8, !tbaa !5
  %261 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %260, i32 0, i32 7
  %262 = load volatile i16, ptr %261, align 2, !tbaa !22
  %263 = zext i16 %262 to i32
  %264 = call i32 @HAL_DMA_Start_IT(ptr noundef %250, i32 noundef %255, i32 noundef %259, i32 noundef %263)
  %265 = icmp ne i32 0, %264
  br i1 %265, label %266, label %276

266:                                              ; preds = %231
  %267 = load ptr, ptr %5, align 8, !tbaa !5
  %268 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %267, i32 0, i32 15
  %269 = load volatile i32, ptr %268, align 8, !tbaa !19
  %270 = zext i32 %269 to i64
  %271 = or i64 %270, 16
  %272 = trunc i64 %271 to i32
  store volatile i32 %272, ptr %268, align 8, !tbaa !19
  store i32 1, ptr %8, align 4, !tbaa !11
  %273 = load ptr, ptr %5, align 8, !tbaa !5
  %274 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %273, i32 0, i32 14
  store volatile i32 1, ptr %274, align 4, !tbaa !17
  %275 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %275, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

276:                                              ; preds = %231
  %277 = load ptr, ptr %5, align 8, !tbaa !5
  %278 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %277, i32 0, i32 12
  %279 = load ptr, ptr %278, align 8, !tbaa !31
  %280 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %279, i32 0, i32 1
  %281 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %280, i32 0, i32 6
  %282 = load i32, ptr %281, align 8, !tbaa !40
  %283 = icmp eq i32 %282, 256
  br i1 %283, label %284, label %298

284:                                              ; preds = %276
  %285 = load ptr, ptr %5, align 8, !tbaa !5
  %286 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %285, i32 0, i32 0
  %287 = load ptr, ptr %286, align 8, !tbaa !27
  %288 = getelementptr inbounds %struct.SPI_TypeDef, ptr %287, i32 0, i32 1
  %289 = load volatile i32, ptr %288, align 4, !tbaa !41
  %290 = zext i32 %289 to i64
  %291 = and i64 %290, -65536
  %292 = or i64 %291, 0
  %293 = trunc i64 %292 to i32
  %294 = load ptr, ptr %5, align 8, !tbaa !5
  %295 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %294, i32 0, i32 0
  %296 = load ptr, ptr %295, align 8, !tbaa !27
  %297 = getelementptr inbounds %struct.SPI_TypeDef, ptr %296, i32 0, i32 1
  store volatile i32 %293, ptr %297, align 4, !tbaa !41
  br label %314

298:                                              ; preds = %276
  %299 = load ptr, ptr %5, align 8, !tbaa !5
  %300 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %299, i32 0, i32 0
  %301 = load ptr, ptr %300, align 8, !tbaa !27
  %302 = getelementptr inbounds %struct.SPI_TypeDef, ptr %301, i32 0, i32 1
  %303 = load volatile i32, ptr %302, align 4, !tbaa !41
  %304 = zext i32 %303 to i64
  %305 = and i64 %304, -65536
  %306 = load i16, ptr %7, align 2, !tbaa !9
  %307 = zext i16 %306 to i64
  %308 = or i64 %305, %307
  %309 = trunc i64 %308 to i32
  %310 = load ptr, ptr %5, align 8, !tbaa !5
  %311 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %310, i32 0, i32 0
  %312 = load ptr, ptr %311, align 8, !tbaa !27
  %313 = getelementptr inbounds %struct.SPI_TypeDef, ptr %312, i32 0, i32 1
  store volatile i32 %309, ptr %313, align 4, !tbaa !41
  br label %314

314:                                              ; preds = %298, %284
  %315 = load ptr, ptr %5, align 8, !tbaa !5
  %316 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %315, i32 0, i32 0
  %317 = load ptr, ptr %316, align 8, !tbaa !27
  %318 = getelementptr inbounds %struct.SPI_TypeDef, ptr %317, i32 0, i32 2
  %319 = load volatile i32, ptr %318, align 4, !tbaa !35
  %320 = zext i32 %319 to i64
  %321 = or i64 %320, 16384
  %322 = trunc i64 %321 to i32
  store volatile i32 %322, ptr %318, align 4, !tbaa !35
  %323 = load ptr, ptr %5, align 8, !tbaa !5
  %324 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %323, i32 0, i32 0
  %325 = load ptr, ptr %324, align 8, !tbaa !27
  %326 = getelementptr inbounds %struct.SPI_TypeDef, ptr %325, i32 0, i32 4
  %327 = load volatile i32, ptr %326, align 4, !tbaa !42
  %328 = zext i32 %327 to i64
  %329 = or i64 %328, 832
  %330 = trunc i64 %329 to i32
  store volatile i32 %330, ptr %326, align 4, !tbaa !42
  %331 = load ptr, ptr %5, align 8, !tbaa !5
  %332 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %331, i32 0, i32 0
  %333 = load ptr, ptr %332, align 8, !tbaa !27
  %334 = getelementptr inbounds %struct.SPI_TypeDef, ptr %333, i32 0, i32 0
  %335 = load volatile i32, ptr %334, align 4, !tbaa !28
  %336 = zext i32 %335 to i64
  %337 = or i64 %336, 1
  %338 = trunc i64 %337 to i32
  store volatile i32 %338, ptr %334, align 4, !tbaa !28
  %339 = load ptr, ptr %5, align 8, !tbaa !5
  %340 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %339, i32 0, i32 1
  %341 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %340, i32 0, i32 0
  %342 = load i32, ptr %341, align 8, !tbaa !16
  %343 = zext i32 %342 to i64
  %344 = icmp eq i64 %343, 4194304
  br i1 %344, label %345, label %354

345:                                              ; preds = %314
  %346 = load ptr, ptr %5, align 8, !tbaa !5
  %347 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %346, i32 0, i32 0
  %348 = load ptr, ptr %347, align 8, !tbaa !27
  %349 = getelementptr inbounds %struct.SPI_TypeDef, ptr %348, i32 0, i32 0
  %350 = load volatile i32, ptr %349, align 4, !tbaa !28
  %351 = zext i32 %350 to i64
  %352 = or i64 %351, 512
  %353 = trunc i64 %352 to i32
  store volatile i32 %353, ptr %349, align 4, !tbaa !28
  br label %354

354:                                              ; preds = %345, %314
  br label %355

355:                                              ; preds = %354
  %356 = load ptr, ptr %5, align 8, !tbaa !5
  %357 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %356, i32 0, i32 13
  store i32 0, ptr %357, align 8, !tbaa !18
  br label %358

358:                                              ; preds = %355
  br label %359

359:                                              ; preds = %358
  %360 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %360, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %361

361:                                              ; preds = %359, %266, %149, %67, %53, %37, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %362 = load i32, ptr %4, align 4
  ret i32 %362
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_SPI_TransmitReceive_DMA(ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfReceiveCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAReceiveCplt(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 12}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 8}
!17 = !{!14, !12, i64 164}
!18 = !{!14, !12, i64 160}
!19 = !{!14, !12, i64 168}
!20 = !{!14, !6, i64 112}
!21 = !{!14, !10, i64 120}
!22 = !{!14, !10, i64 122}
!23 = !{!14, !6, i64 128}
!24 = !{!14, !6, i64 136}
!25 = !{!14, !10, i64 104}
!26 = !{!14, !10, i64 106}
!27 = !{!14, !6, i64 0}
!28 = !{!29, !12, i64 0}
!29 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!30 = !{!14, !12, i64 16}
!31 = !{!14, !6, i64 152}
!32 = !{!33, !12, i64 28}
!33 = !{!"__DMA_HandleTypeDef", !6, i64 0, !34, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!34 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!35 = !{!29, !12, i64 8}
!36 = !{!33, !6, i64 80}
!37 = !{!33, !6, i64 72}
!38 = !{!33, !6, i64 104}
!39 = !{!33, !6, i64 112}
!40 = !{!33, !12, i64 32}
!41 = !{!29, !12, i64 4}
!42 = !{!29, !12, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = getelementptr inbounds i8, ptr %0, i64 12
  %6 = load i32, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %8, label %14

8:                                                ; preds = %3
  %9 = load i32, ptr %4, align 8, !tbaa !13
  %10 = icmp eq i32 %9, 4194304
  br i1 %10, label %11, label %14

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 164
  store volatile i32 4, ptr %12, align 4, !tbaa !14
  %13 = tail call i32 @HAL_SPI_TransmitReceive_DMA(ptr noundef nonnull %0, ptr noundef %1, ptr noundef %1, i16 noundef zeroext %2)
  br label %132

14:                                               ; preds = %3, %8
  %15 = getelementptr inbounds i8, ptr %0, i64 160
  %16 = load i32, ptr %15, align 8, !tbaa !15
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %132, label %18

18:                                               ; preds = %14
  store i32 1, ptr %15, align 8, !tbaa !15
  %19 = getelementptr inbounds i8, ptr %0, i64 164
  %20 = load volatile i32, ptr %19, align 4, !tbaa !14
  %.not = icmp eq i32 %20, 1
  br i1 %.not, label %22, label %21

21:                                               ; preds = %18
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %132

22:                                               ; preds = %18
  %23 = icmp eq ptr %1, null
  %24 = icmp eq i16 %2, 0
  %or.cond = or i1 %23, %24
  br i1 %or.cond, label %25, label %26

25:                                               ; preds = %22
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %132

26:                                               ; preds = %22
  store volatile i32 4, ptr %19, align 4, !tbaa !14
  %27 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %27, align 8, !tbaa !16
  %28 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr %1, ptr %28, align 8, !tbaa !17
  %29 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 %2, ptr %29, align 8, !tbaa !18
  %30 = getelementptr inbounds i8, ptr %0, i64 122
  store volatile i16 %2, ptr %30, align 2, !tbaa !19
  %31 = getelementptr inbounds i8, ptr %0, i64 128
  %32 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 0, ptr %32, align 8, !tbaa !20
  %33 = getelementptr inbounds i8, ptr %0, i64 106
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %31, i8 0, i64 16, i1 false)
  store volatile i16 0, ptr %33, align 2, !tbaa !21
  %34 = icmp eq i32 %6, 393216
  br i1 %34, label %35, label %39

35:                                               ; preds = %26
  %36 = load ptr, ptr %0, align 8, !tbaa !22
  %37 = load volatile i32, ptr %36, align 4, !tbaa !23
  %38 = and i32 %37, -2049
  store volatile i32 %38, ptr %36, align 4, !tbaa !23
  br label %39

39:                                               ; preds = %35, %26
  %40 = getelementptr inbounds i8, ptr %0, i64 16
  %41 = load i32, ptr %40, align 8, !tbaa !25
  %42 = icmp ugt i32 %41, 15
  br i1 %42, label %43, label %48

43:                                               ; preds = %39
  %44 = getelementptr inbounds i8, ptr %0, i64 152
  %45 = load ptr, ptr %44, align 8, !tbaa !26
  %46 = getelementptr inbounds i8, ptr %45, i64 28
  %47 = load i32, ptr %46, align 4, !tbaa !27
  %.not79 = icmp eq i32 %47, 16384
  br i1 %.not79, label %71, label %50

48:                                               ; preds = %39
  %49 = icmp ugt i32 %41, 7
  br i1 %49, label %.thread, label %51

.thread:                                          ; preds = %48
  %.phi.trans.insert = getelementptr inbounds i8, ptr %0, i64 152
  %.pre = load ptr, ptr %.phi.trans.insert, align 8, !tbaa !26
  %.phi.trans.insert85 = getelementptr inbounds i8, ptr %.pre, i64 28
  %.pre86 = load i32, ptr %.phi.trans.insert85, align 4, !tbaa !27
  switch i32 %.pre86, label %50 [
    i32 8192, label %76
    i32 16384, label %76
  ]

50:                                               ; preds = %.thread, %43
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %132

51:                                               ; preds = %48
  %52 = load ptr, ptr %0, align 8, !tbaa !22
  %53 = getelementptr inbounds i8, ptr %52, i64 8
  %54 = load volatile i32, ptr %53, align 4, !tbaa !30
  %55 = and i32 %54, -16385
  store volatile i32 %55, ptr %53, align 4, !tbaa !30
  %56 = getelementptr inbounds i8, ptr %0, i64 152
  %57 = load ptr, ptr %56, align 8, !tbaa !26
  %58 = getelementptr inbounds i8, ptr %57, i64 28
  %59 = load i32, ptr %58, align 4, !tbaa !27
  switch i32 %59, label %88 [
    i32 8192, label %.thread84
    i32 16384, label %65
  ]

.thread84:                                        ; preds = %51
  %60 = load volatile i16, ptr %30, align 2, !tbaa !19
  %61 = zext i16 %60 to i32
  %62 = add nuw nsw i32 %61, 1
  %63 = lshr i32 %62, 1
  %64 = trunc nuw i32 %63 to i16
  store volatile i16 %64, ptr %30, align 2, !tbaa !19
  br label %88

65:                                               ; preds = %51
  %66 = load volatile i16, ptr %30, align 2, !tbaa !19
  %67 = zext i16 %66 to i32
  %68 = add nuw nsw i32 %67, 3
  %69 = lshr i32 %68, 2
  %70 = trunc nuw nsw i32 %69 to i16
  store volatile i16 %70, ptr %30, align 2, !tbaa !19
  br label %88

71:                                               ; preds = %43
  %72 = load ptr, ptr %0, align 8, !tbaa !22
  %73 = getelementptr inbounds i8, ptr %72, i64 8
  %74 = load volatile i32, ptr %73, align 4, !tbaa !30
  %75 = and i32 %74, -16385
  store volatile i32 %75, ptr %73, align 4, !tbaa !30
  br label %88

76:                                               ; preds = %.thread, %.thread
  %77 = load ptr, ptr %0, align 8, !tbaa !22
  %78 = getelementptr inbounds i8, ptr %77, i64 8
  %79 = load volatile i32, ptr %78, align 4, !tbaa !30
  %80 = and i32 %79, -16385
  store volatile i32 %80, ptr %78, align 4, !tbaa !30
  %81 = icmp eq i32 %.pre86, 16384
  br i1 %81, label %82, label %88

82:                                               ; preds = %76
  %83 = load volatile i16, ptr %30, align 2, !tbaa !19
  %84 = zext i16 %83 to i32
  %85 = add nuw nsw i32 %84, 1
  %86 = lshr i32 %85, 1
  %87 = trunc nuw i32 %86 to i16
  store volatile i16 %87, ptr %30, align 2, !tbaa !19
  br label %88

88:                                               ; preds = %71, %51, %.thread84, %82, %76, %65
  %89 = phi ptr [ %.pre, %82 ], [ %.pre, %76 ], [ %45, %71 ], [ %57, %65 ], [ %57, %.thread84 ], [ %57, %51 ]
  %90 = phi ptr [ %77, %82 ], [ %77, %76 ], [ %72, %71 ], [ %52, %65 ], [ %52, %.thread84 ], [ %52, %51 ]
  %91 = getelementptr inbounds i8, ptr %89, i64 80
  store ptr @SPI_DMAHalfReceiveCplt, ptr %91, align 8, !tbaa !31
  %92 = getelementptr inbounds i8, ptr %89, i64 72
  store ptr @SPI_DMAReceiveCplt, ptr %92, align 8, !tbaa !32
  %93 = getelementptr inbounds i8, ptr %89, i64 104
  store ptr @SPI_DMAError, ptr %93, align 8, !tbaa !33
  %94 = getelementptr inbounds i8, ptr %89, i64 112
  store ptr null, ptr %94, align 8, !tbaa !34
  %95 = getelementptr inbounds i8, ptr %90, i64 48
  %96 = ptrtoint ptr %95 to i64
  %97 = trunc i64 %96 to i32
  %98 = ptrtoint ptr %1 to i64
  %99 = trunc i64 %98 to i32
  %100 = load volatile i16, ptr %30, align 2, !tbaa !19
  %101 = zext i16 %100 to i32
  %102 = tail call i32 @HAL_DMA_Start_IT(ptr noundef nonnull %89, i32 noundef %97, i32 noundef %99, i32 noundef %101) #3
  %.not82 = icmp eq i32 %102, 0
  br i1 %.not82, label %106, label %103

103:                                              ; preds = %88
  %104 = load volatile i32, ptr %27, align 8, !tbaa !16
  %105 = or i32 %104, 16
  store volatile i32 %105, ptr %27, align 8, !tbaa !16
  store volatile i32 1, ptr %19, align 4, !tbaa !14
  br label %132

106:                                              ; preds = %88
  %107 = getelementptr inbounds i8, ptr %0, i64 152
  %108 = load ptr, ptr %107, align 8, !tbaa !26
  %109 = getelementptr inbounds i8, ptr %108, i64 32
  %110 = load i32, ptr %109, align 8, !tbaa !35
  %111 = icmp eq i32 %110, 256
  %112 = load ptr, ptr %0, align 8, !tbaa !22
  %113 = getelementptr inbounds i8, ptr %112, i64 4
  %114 = load volatile i32, ptr %113, align 4, !tbaa !36
  %115 = and i32 %114, -65536
  %116 = zext i16 %2 to i32
  %117 = select i1 %111, i32 0, i32 %116
  %.sink = or disjoint i32 %115, %117
  store volatile i32 %.sink, ptr %113, align 4, !tbaa !36
  %118 = getelementptr inbounds i8, ptr %112, i64 8
  %119 = load volatile i32, ptr %118, align 4, !tbaa !30
  %120 = or i32 %119, 16384
  store volatile i32 %120, ptr %118, align 4, !tbaa !30
  %121 = getelementptr inbounds i8, ptr %112, i64 16
  %122 = load volatile i32, ptr %121, align 4, !tbaa !37
  %123 = or i32 %122, 832
  store volatile i32 %123, ptr %121, align 4, !tbaa !37
  %124 = load volatile i32, ptr %112, align 4, !tbaa !23
  %125 = or i32 %124, 1
  store volatile i32 %125, ptr %112, align 4, !tbaa !23
  %126 = load i32, ptr %4, align 8, !tbaa !13
  %127 = icmp eq i32 %126, 4194304
  br i1 %127, label %128, label %131

128:                                              ; preds = %106
  %129 = load volatile i32, ptr %112, align 4, !tbaa !23
  %130 = or i32 %129, 512
  store volatile i32 %130, ptr %112, align 4, !tbaa !23
  br label %131

131:                                              ; preds = %106, %128
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %132

132:                                              ; preds = %14, %131, %103, %50, %25, %21, %11
  %.0 = phi i32 [ %13, %11 ], [ 2, %21 ], [ 1, %25 ], [ 1, %50 ], [ 1, %103 ], [ 0, %131 ], [ 2, %14 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_SPI_TransmitReceive_DMA(ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAHalfReceiveCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_DMAReceiveCplt(ptr noundef) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 12}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 8}
!14 = !{!6, !11, i64 164}
!15 = !{!6, !11, i64 160}
!16 = !{!6, !11, i64 168}
!17 = !{!6, !7, i64 112}
!18 = !{!6, !12, i64 120}
!19 = !{!6, !12, i64 122}
!20 = !{!6, !12, i64 104}
!21 = !{!6, !12, i64 106}
!22 = !{!6, !7, i64 0}
!23 = !{!24, !11, i64 0}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!25 = !{!6, !11, i64 16}
!26 = !{!6, !7, i64 152}
!27 = !{!28, !11, i64 28}
!28 = !{!"__DMA_HandleTypeDef", !7, i64 0, !29, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!29 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!30 = !{!24, !11, i64 8}
!31 = !{!28, !7, i64 80}
!32 = !{!28, !7, i64 72}
!33 = !{!28, !7, i64 104}
!34 = !{!28, !7, i64 112}
!35 = !{!28, !11, i64 32}
!36 = !{!24, !11, i64 4}
!37 = !{!24, !11, i64 16}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass