; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConfigMuxRequestGenerator)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.DMAMUX_RequestGen_TypeDef = type { i32 }
%struct.HAL_DMA_MuxRequestGeneratorConfigTypeDef = type { i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DMAEx_ConfigMuxRequestGenerator(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %9, i32 0, i32 3
  %11 = load volatile i32, ptr %10, align 4, !tbaa !9
  store i32 %11, ptr %7, align 4, !tbaa !13
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %12, i32 0, i32 0
  %14 = load ptr, ptr %13, align 8, !tbaa !14
  %15 = icmp eq ptr %14, inttoptr (i64 1073872912 to ptr)
  br i1 %15, label %91, label %16

16:                                               ; preds = %2
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %17, i32 0, i32 0
  %19 = load ptr, ptr %18, align 8, !tbaa !14
  %20 = icmp eq ptr %19, inttoptr (i64 1073872936 to ptr)
  br i1 %20, label %91, label %21

21:                                               ; preds = %16
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !14
  %25 = icmp eq ptr %24, inttoptr (i64 1073872960 to ptr)
  br i1 %25, label %91, label %26

26:                                               ; preds = %21
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %27, i32 0, i32 0
  %29 = load ptr, ptr %28, align 8, !tbaa !14
  %30 = icmp eq ptr %29, inttoptr (i64 1073872984 to ptr)
  br i1 %30, label %91, label %31

31:                                               ; preds = %26
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %32, i32 0, i32 0
  %34 = load ptr, ptr %33, align 8, !tbaa !14
  %35 = icmp eq ptr %34, inttoptr (i64 1073873008 to ptr)
  br i1 %35, label %91, label %36

36:                                               ; preds = %31
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !14
  %40 = icmp eq ptr %39, inttoptr (i64 1073873032 to ptr)
  br i1 %40, label %91, label %41

41:                                               ; preds = %36
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %42, i32 0, i32 0
  %44 = load ptr, ptr %43, align 8, !tbaa !14
  %45 = icmp eq ptr %44, inttoptr (i64 1073873056 to ptr)
  br i1 %45, label %91, label %46

46:                                               ; preds = %41
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %47, i32 0, i32 0
  %49 = load ptr, ptr %48, align 8, !tbaa !14
  %50 = icmp eq ptr %49, inttoptr (i64 1073873080 to ptr)
  br i1 %50, label %91, label %51

51:                                               ; preds = %46
  %52 = load ptr, ptr %4, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !14
  %55 = icmp eq ptr %54, inttoptr (i64 1073873936 to ptr)
  br i1 %55, label %91, label %56

56:                                               ; preds = %51
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !14
  %60 = icmp eq ptr %59, inttoptr (i64 1073873960 to ptr)
  br i1 %60, label %91, label %61

61:                                               ; preds = %56
  %62 = load ptr, ptr %4, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !14
  %65 = icmp eq ptr %64, inttoptr (i64 1073873984 to ptr)
  br i1 %65, label %91, label %66

66:                                               ; preds = %61
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !14
  %70 = icmp eq ptr %69, inttoptr (i64 1073874008 to ptr)
  br i1 %70, label %91, label %71

71:                                               ; preds = %66
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !14
  %75 = icmp eq ptr %74, inttoptr (i64 1073874032 to ptr)
  br i1 %75, label %91, label %76

76:                                               ; preds = %71
  %77 = load ptr, ptr %4, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !14
  %80 = icmp eq ptr %79, inttoptr (i64 1073874056 to ptr)
  br i1 %80, label %91, label %81

81:                                               ; preds = %76
  %82 = load ptr, ptr %4, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %82, i32 0, i32 0
  %84 = load ptr, ptr %83, align 8, !tbaa !14
  %85 = icmp eq ptr %84, inttoptr (i64 1073874080 to ptr)
  br i1 %85, label %91, label %86

86:                                               ; preds = %81
  %87 = load ptr, ptr %4, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !14
  %90 = icmp eq ptr %89, inttoptr (i64 1073874104 to ptr)
  br label %91

91:                                               ; preds = %86, %81, %76, %71, %66, %61, %56, %51, %46, %41, %36, %31, %26, %21, %16, %2
  %92 = phi i1 [ true, %81 ], [ true, %76 ], [ true, %71 ], [ true, %66 ], [ true, %61 ], [ true, %56 ], [ true, %51 ], [ true, %46 ], [ true, %41 ], [ true, %36 ], [ true, %31 ], [ true, %26 ], [ true, %21 ], [ true, %16 ], [ true, %2 ], [ %90, %86 ]
  %93 = zext i1 %92 to i32
  %94 = icmp ne i32 %93, 0
  br i1 %94, label %95, label %96

95:                                               ; preds = %91
  br label %97

96:                                               ; preds = %91
  br label %97

97:                                               ; preds = %96, %95
  %98 = load ptr, ptr %4, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %98, i32 0, i32 17
  %100 = load ptr, ptr %99, align 8, !tbaa !15
  %101 = icmp eq ptr %100, null
  br i1 %101, label %102, label %105

102:                                              ; preds = %97
  %103 = load ptr, ptr %4, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %103, i32 0, i32 11
  store volatile i32 64, ptr %104, align 8, !tbaa !16
  store i32 1, ptr %6, align 4, !tbaa !13
  br label %156

105:                                              ; preds = %97
  %106 = load ptr, ptr %4, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %106, i32 0, i32 17
  %108 = load ptr, ptr %107, align 8, !tbaa !15
  %109 = getelementptr inbounds %struct.DMAMUX_RequestGen_TypeDef, ptr %108, i32 0, i32 0
  %110 = load volatile i32, ptr %109, align 4, !tbaa !17
  %111 = zext i32 %110 to i64
  %112 = and i64 %111, 65536
  %113 = icmp eq i64 %112, 0
  br i1 %113, label %114, label %152

114:                                              ; preds = %105
  %115 = load i32, ptr %7, align 4, !tbaa !13
  %116 = icmp eq i32 %115, 1
  br i1 %116, label %117, label %152

117:                                              ; preds = %114
  br label %118

118:                                              ; preds = %117
  %119 = load ptr, ptr %4, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %119, i32 0, i32 2
  %121 = load i32, ptr %120, align 8, !tbaa !19
  %122 = icmp eq i32 %121, 1
  br i1 %122, label %123, label %124

123:                                              ; preds = %118
  store i32 2, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %158

124:                                              ; preds = %118
  %125 = load ptr, ptr %4, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %125, i32 0, i32 2
  store i32 1, ptr %126, align 8, !tbaa !19
  br label %127

127:                                              ; preds = %124
  br label %128

128:                                              ; preds = %127
  br label %129

129:                                              ; preds = %128
  %130 = load ptr, ptr %5, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.HAL_DMA_MuxRequestGeneratorConfigTypeDef, ptr %130, i32 0, i32 0
  %132 = load i32, ptr %131, align 4, !tbaa !20
  %133 = load ptr, ptr %5, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.HAL_DMA_MuxRequestGeneratorConfigTypeDef, ptr %133, i32 0, i32 2
  %135 = load i32, ptr %134, align 4, !tbaa !22
  %136 = sub i32 %135, 1
  %137 = shl i32 %136, 19
  %138 = or i32 %132, %137
  %139 = load ptr, ptr %5, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.HAL_DMA_MuxRequestGeneratorConfigTypeDef, ptr %139, i32 0, i32 1
  %141 = load i32, ptr %140, align 4, !tbaa !23
  %142 = or i32 %138, %141
  %143 = load ptr, ptr %4, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %143, i32 0, i32 17
  %145 = load ptr, ptr %144, align 8, !tbaa !15
  %146 = getelementptr inbounds %struct.DMAMUX_RequestGen_TypeDef, ptr %145, i32 0, i32 0
  store volatile i32 %142, ptr %146, align 4, !tbaa !17
  br label %147

147:                                              ; preds = %129
  %148 = load ptr, ptr %4, align 8, !tbaa !5
  %149 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %148, i32 0, i32 2
  store i32 0, ptr %149, align 8, !tbaa !19
  br label %150

150:                                              ; preds = %147
  br label %151

151:                                              ; preds = %150
  store i32 0, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %158

152:                                              ; preds = %114, %105
  %153 = load ptr, ptr %4, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %153, i32 0, i32 11
  store volatile i32 2048, ptr %154, align 8, !tbaa !16
  store i32 1, ptr %6, align 4, !tbaa !13
  br label %155

155:                                              ; preds = %152
  br label %156

156:                                              ; preds = %155, %102
  %157 = load i32, ptr %6, align 4, !tbaa !13
  store i32 %157, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %158

158:                                              ; preds = %156, %151, %123
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %159 = load i32, ptr %3, align 4
  ret i32 %159
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 60}
!10 = !{!"__DMA_HandleTypeDef", !6, i64 0, !11, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!12 = !{!"int", !7, i64 0}
!13 = !{!12, !12, i64 0}
!14 = !{!10, !6, i64 0}
!15 = !{!10, !6, i64 160}
!16 = !{!10, !12, i64 120}
!17 = !{!18, !12, i64 0}
!18 = !{!"", !12, i64 0}
!19 = !{!10, !12, i64 56}
!20 = !{!21, !12, i64 0}
!21 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8}
!22 = !{!21, !12, i64 8}
!23 = !{!21, !12, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_DMAEx_ConfigMuxRequestGenerator(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 60
  %4 = load volatile i32, ptr %3, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 160
  %6 = load ptr, ptr %5, align 8, !tbaa !12
  %7 = icmp eq ptr %6, null
  br i1 %7, label %8, label %10

8:                                                ; preds = %2
  %9 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 64, ptr %9, align 8, !tbaa !13
  br label %31

10:                                               ; preds = %2
  %11 = load volatile i32, ptr %6, align 4, !tbaa !14
  %12 = and i32 %11, 65536
  %13 = icmp eq i32 %12, 0
  %14 = icmp eq i32 %4, 1
  %or.cond = select i1 %13, i1 %14, i1 false
  br i1 %or.cond, label %15, label %29

15:                                               ; preds = %10
  %16 = getelementptr inbounds i8, ptr %0, i64 56
  %17 = load i32, ptr %16, align 8, !tbaa !16
  %18 = icmp eq i32 %17, 1
  br i1 %18, label %31, label %19

19:                                               ; preds = %15
  %20 = load i32, ptr %1, align 4, !tbaa !17
  %21 = getelementptr inbounds i8, ptr %1, i64 8
  %22 = load i32, ptr %21, align 4, !tbaa !19
  %23 = shl i32 %22, 19
  %24 = add i32 %23, -524288
  %25 = getelementptr inbounds i8, ptr %1, i64 4
  %26 = load i32, ptr %25, align 4, !tbaa !20
  %27 = or i32 %26, %20
  %28 = or i32 %27, %24
  store volatile i32 %28, ptr %6, align 4, !tbaa !14
  store i32 0, ptr %16, align 8, !tbaa !16
  br label %31

29:                                               ; preds = %10
  %30 = getelementptr inbounds i8, ptr %0, i64 120
  store volatile i32 2048, ptr %30, align 8, !tbaa !13
  br label %31

31:                                               ; preds = %8, %29, %15, %19
  %.0 = phi i32 [ 0, %19 ], [ 2, %15 ], [ 1, %29 ], [ 1, %8 ]
  ret i32 %.0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 60}
!6 = !{!"__DMA_HandleTypeDef", !7, i64 0, !10, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 160}
!13 = !{!6, !11, i64 120}
!14 = !{!15, !11, i64 0}
!15 = !{!"", !11, i64 0}
!16 = !{!6, !11, i64 56}
!17 = !{!18, !11, i64 0}
!18 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!19 = !{!18, !11, i64 8}
!20 = !{!18, !11, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass