; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DeInit)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.DMA_Stream_TypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.BDMA_Channel_TypeDef = type { i32, i32, i32, i32, i32 }
%struct.DMA_Base_Registers = type { i32, i32, i32 }
%struct.BDMA_Base_Registers = type { i32, i32 }
%struct.DMAMUX_Channel_TypeDef = type { i32 }
%struct.DMAMUX_ChannelStatus_TypeDef = type { i32, i32 }
%struct.DMAMUX_RequestGen_TypeDef = type { i32 }
%struct.DMAMUX_RequestGenStatus_TypeDef = type { i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @DMA_CalcBaseAndBitshift(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @DMA_CalcDMAMUXChannelBaseAndMask(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @DMA_CalcDMAMUXRequestGenBaseAndMask(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DMA_DeInit(ptr noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = icmp eq ptr %7, null
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i32 1, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %382

10:                                               ; preds = %1
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %11, i32 0, i32 0
  %13 = load ptr, ptr %12, align 8, !tbaa !9
  %14 = icmp eq ptr %13, inttoptr (i64 1073872912 to ptr)
  br i1 %14, label %90, label %15

15:                                               ; preds = %10
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %16, i32 0, i32 0
  %18 = load ptr, ptr %17, align 8, !tbaa !9
  %19 = icmp eq ptr %18, inttoptr (i64 1073872936 to ptr)
  br i1 %19, label %90, label %20

20:                                               ; preds = %15
  %21 = load ptr, ptr %3, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %21, i32 0, i32 0
  %23 = load ptr, ptr %22, align 8, !tbaa !9
  %24 = icmp eq ptr %23, inttoptr (i64 1073872960 to ptr)
  br i1 %24, label %90, label %25

25:                                               ; preds = %20
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %26, i32 0, i32 0
  %28 = load ptr, ptr %27, align 8, !tbaa !9
  %29 = icmp eq ptr %28, inttoptr (i64 1073872984 to ptr)
  br i1 %29, label %90, label %30

30:                                               ; preds = %25
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %31, i32 0, i32 0
  %33 = load ptr, ptr %32, align 8, !tbaa !9
  %34 = icmp eq ptr %33, inttoptr (i64 1073873008 to ptr)
  br i1 %34, label %90, label %35

35:                                               ; preds = %30
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !9
  %39 = icmp eq ptr %38, inttoptr (i64 1073873032 to ptr)
  br i1 %39, label %90, label %40

40:                                               ; preds = %35
  %41 = load ptr, ptr %3, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %41, i32 0, i32 0
  %43 = load ptr, ptr %42, align 8, !tbaa !9
  %44 = icmp eq ptr %43, inttoptr (i64 1073873056 to ptr)
  br i1 %44, label %90, label %45

45:                                               ; preds = %40
  %46 = load ptr, ptr %3, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %46, i32 0, i32 0
  %48 = load ptr, ptr %47, align 8, !tbaa !9
  %49 = icmp eq ptr %48, inttoptr (i64 1073873080 to ptr)
  br i1 %49, label %90, label %50

50:                                               ; preds = %45
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %51, i32 0, i32 0
  %53 = load ptr, ptr %52, align 8, !tbaa !9
  %54 = icmp eq ptr %53, inttoptr (i64 1073873936 to ptr)
  br i1 %54, label %90, label %55

55:                                               ; preds = %50
  %56 = load ptr, ptr %3, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %56, i32 0, i32 0
  %58 = load ptr, ptr %57, align 8, !tbaa !9
  %59 = icmp eq ptr %58, inttoptr (i64 1073873960 to ptr)
  br i1 %59, label %90, label %60

60:                                               ; preds = %55
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %61, i32 0, i32 0
  %63 = load ptr, ptr %62, align 8, !tbaa !9
  %64 = icmp eq ptr %63, inttoptr (i64 1073873984 to ptr)
  br i1 %64, label %90, label %65

65:                                               ; preds = %60
  %66 = load ptr, ptr %3, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %66, i32 0, i32 0
  %68 = load ptr, ptr %67, align 8, !tbaa !9
  %69 = icmp eq ptr %68, inttoptr (i64 1073874008 to ptr)
  br i1 %69, label %90, label %70

70:                                               ; preds = %65
  %71 = load ptr, ptr %3, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %71, i32 0, i32 0
  %73 = load ptr, ptr %72, align 8, !tbaa !9
  %74 = icmp eq ptr %73, inttoptr (i64 1073874032 to ptr)
  br i1 %74, label %90, label %75

75:                                               ; preds = %70
  %76 = load ptr, ptr %3, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %76, i32 0, i32 0
  %78 = load ptr, ptr %77, align 8, !tbaa !9
  %79 = icmp eq ptr %78, inttoptr (i64 1073874056 to ptr)
  br i1 %79, label %90, label %80

80:                                               ; preds = %75
  %81 = load ptr, ptr %3, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !9
  %84 = icmp eq ptr %83, inttoptr (i64 1073874080 to ptr)
  br i1 %84, label %90, label %85

85:                                               ; preds = %80
  %86 = load ptr, ptr %3, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %86, i32 0, i32 0
  %88 = load ptr, ptr %87, align 8, !tbaa !9
  %89 = icmp eq ptr %88, inttoptr (i64 1073874104 to ptr)
  br i1 %89, label %90, label %99

90:                                               ; preds = %85, %80, %75, %70, %65, %60, %55, %50, %45, %40, %35, %30, %25, %20, %15, %10
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !9
  %94 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %93, i32 0, i32 0
  %95 = load volatile i32, ptr %94, align 4, !tbaa !13
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, -2
  %98 = trunc i64 %97 to i32
  store volatile i32 %98, ptr %94, align 4, !tbaa !13
  br label %108

99:                                               ; preds = %85
  %100 = load ptr, ptr %3, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %100, i32 0, i32 0
  %102 = load ptr, ptr %101, align 8, !tbaa !9
  %103 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %102, i32 0, i32 0
  %104 = load volatile i32, ptr %103, align 4, !tbaa !15
  %105 = zext i32 %104 to i64
  %106 = and i64 %105, -2
  %107 = trunc i64 %106 to i32
  store volatile i32 %107, ptr %103, align 4, !tbaa !15
  br label %108

108:                                              ; preds = %99, %90
  %109 = phi i32 [ %98, %90 ], [ %107, %99 ]
  %110 = load ptr, ptr %3, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %110, i32 0, i32 0
  %112 = load ptr, ptr %111, align 8, !tbaa !9
  %113 = icmp eq ptr %112, inttoptr (i64 1073872912 to ptr)
  br i1 %113, label %189, label %114

114:                                              ; preds = %108
  %115 = load ptr, ptr %3, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !9
  %118 = icmp eq ptr %117, inttoptr (i64 1073872936 to ptr)
  br i1 %118, label %189, label %119

119:                                              ; preds = %114
  %120 = load ptr, ptr %3, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %120, i32 0, i32 0
  %122 = load ptr, ptr %121, align 8, !tbaa !9
  %123 = icmp eq ptr %122, inttoptr (i64 1073872960 to ptr)
  br i1 %123, label %189, label %124

124:                                              ; preds = %119
  %125 = load ptr, ptr %3, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %125, i32 0, i32 0
  %127 = load ptr, ptr %126, align 8, !tbaa !9
  %128 = icmp eq ptr %127, inttoptr (i64 1073872984 to ptr)
  br i1 %128, label %189, label %129

129:                                              ; preds = %124
  %130 = load ptr, ptr %3, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %130, i32 0, i32 0
  %132 = load ptr, ptr %131, align 8, !tbaa !9
  %133 = icmp eq ptr %132, inttoptr (i64 1073873008 to ptr)
  br i1 %133, label %189, label %134

134:                                              ; preds = %129
  %135 = load ptr, ptr %3, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %135, i32 0, i32 0
  %137 = load ptr, ptr %136, align 8, !tbaa !9
  %138 = icmp eq ptr %137, inttoptr (i64 1073873032 to ptr)
  br i1 %138, label %189, label %139

139:                                              ; preds = %134
  %140 = load ptr, ptr %3, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %140, i32 0, i32 0
  %142 = load ptr, ptr %141, align 8, !tbaa !9
  %143 = icmp eq ptr %142, inttoptr (i64 1073873056 to ptr)
  br i1 %143, label %189, label %144

144:                                              ; preds = %139
  %145 = load ptr, ptr %3, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %145, i32 0, i32 0
  %147 = load ptr, ptr %146, align 8, !tbaa !9
  %148 = icmp eq ptr %147, inttoptr (i64 1073873080 to ptr)
  br i1 %148, label %189, label %149

149:                                              ; preds = %144
  %150 = load ptr, ptr %3, align 8, !tbaa !5
  %151 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %150, i32 0, i32 0
  %152 = load ptr, ptr %151, align 8, !tbaa !9
  %153 = icmp eq ptr %152, inttoptr (i64 1073873936 to ptr)
  br i1 %153, label %189, label %154

154:                                              ; preds = %149
  %155 = load ptr, ptr %3, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %155, i32 0, i32 0
  %157 = load ptr, ptr %156, align 8, !tbaa !9
  %158 = icmp eq ptr %157, inttoptr (i64 1073873960 to ptr)
  br i1 %158, label %189, label %159

159:                                              ; preds = %154
  %160 = load ptr, ptr %3, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %160, i32 0, i32 0
  %162 = load ptr, ptr %161, align 8, !tbaa !9
  %163 = icmp eq ptr %162, inttoptr (i64 1073873984 to ptr)
  br i1 %163, label %189, label %164

164:                                              ; preds = %159
  %165 = load ptr, ptr %3, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %165, i32 0, i32 0
  %167 = load ptr, ptr %166, align 8, !tbaa !9
  %168 = icmp eq ptr %167, inttoptr (i64 1073874008 to ptr)
  br i1 %168, label %189, label %169

169:                                              ; preds = %164
  %170 = load ptr, ptr %3, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %170, i32 0, i32 0
  %172 = load ptr, ptr %171, align 8, !tbaa !9
  %173 = icmp eq ptr %172, inttoptr (i64 1073874032 to ptr)
  br i1 %173, label %189, label %174

174:                                              ; preds = %169
  %175 = load ptr, ptr %3, align 8, !tbaa !5
  %176 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %175, i32 0, i32 0
  %177 = load ptr, ptr %176, align 8, !tbaa !9
  %178 = icmp eq ptr %177, inttoptr (i64 1073874056 to ptr)
  br i1 %178, label %189, label %179

179:                                              ; preds = %174
  %180 = load ptr, ptr %3, align 8, !tbaa !5
  %181 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %180, i32 0, i32 0
  %182 = load ptr, ptr %181, align 8, !tbaa !9
  %183 = icmp eq ptr %182, inttoptr (i64 1073874080 to ptr)
  br i1 %183, label %189, label %184

184:                                              ; preds = %179
  %185 = load ptr, ptr %3, align 8, !tbaa !5
  %186 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %185, i32 0, i32 0
  %187 = load ptr, ptr %186, align 8, !tbaa !9
  %188 = icmp eq ptr %187, inttoptr (i64 1073874104 to ptr)
  br label %189

189:                                              ; preds = %184, %179, %174, %169, %164, %159, %154, %149, %144, %139, %134, %129, %124, %119, %114, %108
  %190 = phi i1 [ true, %179 ], [ true, %174 ], [ true, %169 ], [ true, %164 ], [ true, %159 ], [ true, %154 ], [ true, %149 ], [ true, %144 ], [ true, %139 ], [ true, %134 ], [ true, %129 ], [ true, %124 ], [ true, %119 ], [ true, %114 ], [ true, %108 ], [ %188, %184 ]
  %191 = zext i1 %190 to i32
  %192 = icmp ne i32 %191, 0
  br i1 %192, label %193, label %231

193:                                              ; preds = %189
  %194 = load ptr, ptr %3, align 8, !tbaa !5
  %195 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %194, i32 0, i32 0
  %196 = load ptr, ptr %195, align 8, !tbaa !9
  %197 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %196, i32 0, i32 0
  store volatile i32 0, ptr %197, align 4, !tbaa !13
  %198 = load ptr, ptr %3, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %198, i32 0, i32 0
  %200 = load ptr, ptr %199, align 8, !tbaa !9
  %201 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %200, i32 0, i32 1
  store volatile i32 0, ptr %201, align 4, !tbaa !17
  %202 = load ptr, ptr %3, align 8, !tbaa !5
  %203 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %202, i32 0, i32 0
  %204 = load ptr, ptr %203, align 8, !tbaa !9
  %205 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %204, i32 0, i32 2
  store volatile i32 0, ptr %205, align 4, !tbaa !18
  %206 = load ptr, ptr %3, align 8, !tbaa !5
  %207 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %206, i32 0, i32 0
  %208 = load ptr, ptr %207, align 8, !tbaa !9
  %209 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %208, i32 0, i32 3
  store volatile i32 0, ptr %209, align 4, !tbaa !19
  %210 = load ptr, ptr %3, align 8, !tbaa !5
  %211 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %210, i32 0, i32 0
  %212 = load ptr, ptr %211, align 8, !tbaa !9
  %213 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %212, i32 0, i32 4
  store volatile i32 0, ptr %213, align 4, !tbaa !20
  %214 = load ptr, ptr %3, align 8, !tbaa !5
  %215 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %214, i32 0, i32 0
  %216 = load ptr, ptr %215, align 8, !tbaa !9
  %217 = getelementptr inbounds %struct.DMA_Stream_TypeDef, ptr %216, i32 0, i32 5
  store volatile i32 33, ptr %217, align 4, !tbaa !21
  %218 = load ptr, ptr %3, align 8, !tbaa !5
  %219 = call i32 @DMA_CalcBaseAndBitshift(ptr noundef %218)
  %220 = zext i32 %219 to i64
  %221 = inttoptr i64 %220 to ptr
  store ptr %221, ptr %4, align 8, !tbaa !5
  %222 = load ptr, ptr %3, align 8, !tbaa !5
  %223 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %222, i32 0, i32 13
  %224 = load i32, ptr %223, align 8, !tbaa !22
  %225 = and i32 %224, 31
  %226 = zext i32 %225 to i64
  %227 = shl i64 63, %226
  %228 = trunc i64 %227 to i32
  %229 = load ptr, ptr %4, align 8, !tbaa !5
  %230 = getelementptr inbounds %struct.DMA_Base_Registers, ptr %229, i32 0, i32 2
  store volatile i32 %228, ptr %230, align 4, !tbaa !23
  br label %311

231:                                              ; preds = %189
  %232 = load ptr, ptr %3, align 8, !tbaa !5
  %233 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %232, i32 0, i32 0
  %234 = load ptr, ptr %233, align 8, !tbaa !9
  %235 = icmp eq ptr %234, inttoptr (i64 1476547592 to ptr)
  br i1 %235, label %271, label %236

236:                                              ; preds = %231
  %237 = load ptr, ptr %3, align 8, !tbaa !5
  %238 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %237, i32 0, i32 0
  %239 = load ptr, ptr %238, align 8, !tbaa !9
  %240 = icmp eq ptr %239, inttoptr (i64 1476547612 to ptr)
  br i1 %240, label %271, label %241

241:                                              ; preds = %236
  %242 = load ptr, ptr %3, align 8, !tbaa !5
  %243 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %242, i32 0, i32 0
  %244 = load ptr, ptr %243, align 8, !tbaa !9
  %245 = icmp eq ptr %244, inttoptr (i64 1476547632 to ptr)
  br i1 %245, label %271, label %246

246:                                              ; preds = %241
  %247 = load ptr, ptr %3, align 8, !tbaa !5
  %248 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %247, i32 0, i32 0
  %249 = load ptr, ptr %248, align 8, !tbaa !9
  %250 = icmp eq ptr %249, inttoptr (i64 1476547652 to ptr)
  br i1 %250, label %271, label %251

251:                                              ; preds = %246
  %252 = load ptr, ptr %3, align 8, !tbaa !5
  %253 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %252, i32 0, i32 0
  %254 = load ptr, ptr %253, align 8, !tbaa !9
  %255 = icmp eq ptr %254, inttoptr (i64 1476547672 to ptr)
  br i1 %255, label %271, label %256

256:                                              ; preds = %251
  %257 = load ptr, ptr %3, align 8, !tbaa !5
  %258 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %257, i32 0, i32 0
  %259 = load ptr, ptr %258, align 8, !tbaa !9
  %260 = icmp eq ptr %259, inttoptr (i64 1476547692 to ptr)
  br i1 %260, label %271, label %261

261:                                              ; preds = %256
  %262 = load ptr, ptr %3, align 8, !tbaa !5
  %263 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %262, i32 0, i32 0
  %264 = load ptr, ptr %263, align 8, !tbaa !9
  %265 = icmp eq ptr %264, inttoptr (i64 1476547712 to ptr)
  br i1 %265, label %271, label %266

266:                                              ; preds = %261
  %267 = load ptr, ptr %3, align 8, !tbaa !5
  %268 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %267, i32 0, i32 0
  %269 = load ptr, ptr %268, align 8, !tbaa !9
  %270 = icmp eq ptr %269, inttoptr (i64 1476547732 to ptr)
  br label %271

271:                                              ; preds = %266, %261, %256, %251, %246, %241, %236, %231
  %272 = phi i1 [ true, %261 ], [ true, %256 ], [ true, %251 ], [ true, %246 ], [ true, %241 ], [ true, %236 ], [ true, %231 ], [ %270, %266 ]
  %273 = zext i1 %272 to i32
  %274 = icmp ne i32 %273, 0
  br i1 %274, label %275, label %309

275:                                              ; preds = %271
  %276 = load ptr, ptr %3, align 8, !tbaa !5
  %277 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %276, i32 0, i32 0
  %278 = load ptr, ptr %277, align 8, !tbaa !9
  %279 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %278, i32 0, i32 0
  store volatile i32 0, ptr %279, align 4, !tbaa !15
  %280 = load ptr, ptr %3, align 8, !tbaa !5
  %281 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %280, i32 0, i32 0
  %282 = load ptr, ptr %281, align 8, !tbaa !9
  %283 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %282, i32 0, i32 1
  store volatile i32 0, ptr %283, align 4, !tbaa !25
  %284 = load ptr, ptr %3, align 8, !tbaa !5
  %285 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %284, i32 0, i32 0
  %286 = load ptr, ptr %285, align 8, !tbaa !9
  %287 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %286, i32 0, i32 2
  store volatile i32 0, ptr %287, align 4, !tbaa !26
  %288 = load ptr, ptr %3, align 8, !tbaa !5
  %289 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %288, i32 0, i32 0
  %290 = load ptr, ptr %289, align 8, !tbaa !9
  %291 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %290, i32 0, i32 3
  store volatile i32 0, ptr %291, align 4, !tbaa !27
  %292 = load ptr, ptr %3, align 8, !tbaa !5
  %293 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %292, i32 0, i32 0
  %294 = load ptr, ptr %293, align 8, !tbaa !9
  %295 = getelementptr inbounds %struct.BDMA_Channel_TypeDef, ptr %294, i32 0, i32 4
  store volatile i32 0, ptr %295, align 4, !tbaa !28
  %296 = load ptr, ptr %3, align 8, !tbaa !5
  %297 = call i32 @DMA_CalcBaseAndBitshift(ptr noundef %296)
  %298 = zext i32 %297 to i64
  %299 = inttoptr i64 %298 to ptr
  store ptr %299, ptr %5, align 8, !tbaa !5
  %300 = load ptr, ptr %3, align 8, !tbaa !5
  %301 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %300, i32 0, i32 13
  %302 = load i32, ptr %301, align 8, !tbaa !22
  %303 = and i32 %302, 31
  %304 = zext i32 %303 to i64
  %305 = shl i64 1, %304
  %306 = trunc i64 %305 to i32
  %307 = load ptr, ptr %5, align 8, !tbaa !5
  %308 = getelementptr inbounds %struct.BDMA_Base_Registers, ptr %307, i32 0, i32 1
  store volatile i32 %306, ptr %308, align 4, !tbaa !29
  br label %310

309:                                              ; preds = %271
  store i32 1, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %382

310:                                              ; preds = %275
  br label %311

311:                                              ; preds = %310, %193
  %312 = load ptr, ptr %3, align 8, !tbaa !5
  call void @DMA_CalcDMAMUXChannelBaseAndMask(ptr noundef %312)
  %313 = load ptr, ptr %3, align 8, !tbaa !5
  %314 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %313, i32 0, i32 14
  %315 = load ptr, ptr %314, align 8, !tbaa !31
  %316 = icmp ne ptr %315, null
  br i1 %316, label %317, label %329

317:                                              ; preds = %311
  %318 = load ptr, ptr %3, align 8, !tbaa !5
  %319 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %318, i32 0, i32 14
  %320 = load ptr, ptr %319, align 8, !tbaa !31
  %321 = getelementptr inbounds %struct.DMAMUX_Channel_TypeDef, ptr %320, i32 0, i32 0
  store volatile i32 0, ptr %321, align 4, !tbaa !32
  %322 = load ptr, ptr %3, align 8, !tbaa !5
  %323 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %322, i32 0, i32 16
  %324 = load i32, ptr %323, align 8, !tbaa !34
  %325 = load ptr, ptr %3, align 8, !tbaa !5
  %326 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %325, i32 0, i32 15
  %327 = load ptr, ptr %326, align 8, !tbaa !35
  %328 = getelementptr inbounds %struct.DMAMUX_ChannelStatus_TypeDef, ptr %327, i32 0, i32 1
  store volatile i32 %324, ptr %328, align 4, !tbaa !29
  br label %329

329:                                              ; preds = %317, %311
  %330 = load ptr, ptr %3, align 8, !tbaa !5
  %331 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %330, i32 0, i32 1
  %332 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %331, i32 0, i32 0
  %333 = load i32, ptr %332, align 8, !tbaa !36
  %334 = icmp uge i32 %333, 1
  br i1 %334, label %335, label %354

335:                                              ; preds = %329
  %336 = load ptr, ptr %3, align 8, !tbaa !5
  %337 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %336, i32 0, i32 1
  %338 = getelementptr inbounds %struct.DMA_InitTypeDef, ptr %337, i32 0, i32 0
  %339 = load i32, ptr %338, align 8, !tbaa !36
  %340 = icmp ule i32 %339, 8
  br i1 %340, label %341, label %354

341:                                              ; preds = %335
  %342 = load ptr, ptr %3, align 8, !tbaa !5
  call void @DMA_CalcDMAMUXRequestGenBaseAndMask(ptr noundef %342)
  %343 = load ptr, ptr %3, align 8, !tbaa !5
  %344 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %343, i32 0, i32 17
  %345 = load ptr, ptr %344, align 8, !tbaa !37
  %346 = getelementptr inbounds %struct.DMAMUX_RequestGen_TypeDef, ptr %345, i32 0, i32 0
  store volatile i32 0, ptr %346, align 4, !tbaa !32
  %347 = load ptr, ptr %3, align 8, !tbaa !5
  %348 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %347, i32 0, i32 19
  %349 = load i32, ptr %348, align 8, !tbaa !38
  %350 = load ptr, ptr %3, align 8, !tbaa !5
  %351 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %350, i32 0, i32 18
  %352 = load ptr, ptr %351, align 8, !tbaa !39
  %353 = getelementptr inbounds %struct.DMAMUX_RequestGenStatus_TypeDef, ptr %352, i32 0, i32 1
  store volatile i32 %349, ptr %353, align 4, !tbaa !29
  br label %354

354:                                              ; preds = %341, %335, %329
  %355 = load ptr, ptr %3, align 8, !tbaa !5
  %356 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %355, i32 0, i32 17
  store ptr null, ptr %356, align 8, !tbaa !37
  %357 = load ptr, ptr %3, align 8, !tbaa !5
  %358 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %357, i32 0, i32 18
  store ptr null, ptr %358, align 8, !tbaa !39
  %359 = load ptr, ptr %3, align 8, !tbaa !5
  %360 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %359, i32 0, i32 19
  store i32 0, ptr %360, align 8, !tbaa !38
  %361 = load ptr, ptr %3, align 8, !tbaa !5
  %362 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %361, i32 0, i32 5
  store ptr null, ptr %362, align 8, !tbaa !40
  %363 = load ptr, ptr %3, align 8, !tbaa !5
  %364 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %363, i32 0, i32 6
  store ptr null, ptr %364, align 8, !tbaa !41
  %365 = load ptr, ptr %3, align 8, !tbaa !5
  %366 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %365, i32 0, i32 7
  store ptr null, ptr %366, align 8, !tbaa !42
  %367 = load ptr, ptr %3, align 8, !tbaa !5
  %368 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %367, i32 0, i32 8
  store ptr null, ptr %368, align 8, !tbaa !43
  %369 = load ptr, ptr %3, align 8, !tbaa !5
  %370 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %369, i32 0, i32 9
  store ptr null, ptr %370, align 8, !tbaa !44
  %371 = load ptr, ptr %3, align 8, !tbaa !5
  %372 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %371, i32 0, i32 10
  store ptr null, ptr %372, align 8, !tbaa !45
  %373 = load ptr, ptr %3, align 8, !tbaa !5
  %374 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %373, i32 0, i32 11
  store volatile i32 0, ptr %374, align 8, !tbaa !46
  %375 = load ptr, ptr %3, align 8, !tbaa !5
  %376 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %375, i32 0, i32 3
  store volatile i32 0, ptr %376, align 4, !tbaa !47
  br label %377

377:                                              ; preds = %354
  %378 = load ptr, ptr %3, align 8, !tbaa !5
  %379 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %378, i32 0, i32 2
  store i32 0, ptr %379, align 8, !tbaa !48
  br label %380

380:                                              ; preds = %377
  br label %381

381:                                              ; preds = %380
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %382

382:                                              ; preds = %381, %309, %9
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #2
  %383 = load i32, ptr %2, align 4
  ret i32 %383
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"__DMA_HandleTypeDef", !6, i64 0, !11, i64 8, !12, i64 56, !12, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !12, i64 120, !12, i64 124, !12, i64 128, !6, i64 136, !6, i64 144, !12, i64 152, !6, i64 160, !6, i64 168, !12, i64 176}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 0}
!14 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20}
!15 = !{!16, !12, i64 0}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16}
!17 = !{!14, !12, i64 4}
!18 = !{!14, !12, i64 8}
!19 = !{!14, !12, i64 12}
!20 = !{!14, !12, i64 16}
!21 = !{!14, !12, i64 20}
!22 = !{!10, !12, i64 128}
!23 = !{!24, !12, i64 8}
!24 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8}
!25 = !{!16, !12, i64 4}
!26 = !{!16, !12, i64 8}
!27 = !{!16, !12, i64 12}
!28 = !{!16, !12, i64 16}
!29 = !{!30, !12, i64 4}
!30 = !{!"", !12, i64 0, !12, i64 4}
!31 = !{!10, !6, i64 136}
!32 = !{!33, !12, i64 0}
!33 = !{!"", !12, i64 0}
!34 = !{!10, !12, i64 152}
!35 = !{!10, !6, i64 144}
!36 = !{!10, !12, i64 8}
!37 = !{!10, !6, i64 160}
!38 = !{!10, !12, i64 176}
!39 = !{!10, !6, i64 168}
!40 = !{!10, !6, i64 72}
!41 = !{!10, !6, i64 80}
!42 = !{!10, !6, i64 88}
!43 = !{!10, !6, i64 96}
!44 = !{!10, !6, i64 104}
!45 = !{!10, !6, i64 112}
!46 = !{!10, !12, i64 120}
!47 = !{!10, !12, i64 60}
!48 = !{!10, !12, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden i32 @DMA_CalcBaseAndBitshift(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @DMA_CalcDMAMUXChannelBaseAndMask(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @DMA_CalcDMAMUXRequestGenBaseAndMask(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_DMA_DeInit(ptr noundef %0) local_unnamed_addr #0 {
  %2 = icmp eq ptr %0, null
  br i1 %2, label %46, label %3

3:                                                ; preds = %1
  %4 = load ptr, ptr %0, align 8, !tbaa !5
  %magicptr = ptrtoint ptr %4 to i64
  %5 = load volatile i32, ptr %4, align 4, !tbaa !12
  %6 = and i32 %5, -2
  store volatile i32 %6, ptr %4, align 4, !tbaa !12
  switch i64 %magicptr, label %46 [
    i64 1073872912, label %.critedge
    i64 1073872936, label %.critedge
    i64 1073872960, label %.critedge
    i64 1073872984, label %.critedge
    i64 1073873008, label %.critedge
    i64 1073873032, label %.critedge
    i64 1073873056, label %.critedge
    i64 1073873080, label %.critedge
    i64 1073873936, label %.critedge
    i64 1073873960, label %.critedge
    i64 1073873984, label %.critedge
    i64 1073874008, label %.critedge
    i64 1073874032, label %.critedge
    i64 1073874056, label %.critedge
    i64 1073874080, label %.critedge
    i64 1073874104, label %.critedge
    i64 1476547592, label %.critedge118
    i64 1476547612, label %.critedge118
    i64 1476547632, label %.critedge118
    i64 1476547652, label %.critedge118
    i64 1476547672, label %.critedge118
    i64 1476547692, label %.critedge118
    i64 1476547712, label %.critedge118
    i64 1476547732, label %.critedge118
  ]

.critedge:                                        ; preds = %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3, %3
  store volatile i32 0, ptr %4, align 4, !tbaa !13
  %7 = getelementptr inbounds i8, ptr %4, i64 4
  br label %.critedge118

.critedge118:                                     ; preds = %3, %3, %3, %3, %3, %3, %3, %3, %.critedge
  %.sink138 = phi ptr [ %7, %.critedge ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ], [ %4, %3 ]
  %.sink137 = phi i64 [ 8, %.critedge ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ], [ 4, %3 ]
  %.sink135 = phi i64 [ 12, %.critedge ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ], [ 8, %3 ]
  %.sink133 = phi i64 [ 16, %.critedge ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ], [ 12, %3 ]
  %.sink131 = phi i64 [ 20, %.critedge ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ], [ 16, %3 ]
  %.sink = phi i32 [ 33, %.critedge ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ], [ 0, %3 ]
  %.sink126 = phi i32 [ 63, %.critedge ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ], [ 1, %3 ]
  store volatile i32 0, ptr %.sink138, align 4, !tbaa !12
  %8 = getelementptr inbounds i8, ptr %4, i64 %.sink137
  store volatile i32 0, ptr %8, align 4, !tbaa !12
  %9 = getelementptr inbounds i8, ptr %4, i64 %.sink135
  store volatile i32 0, ptr %9, align 4, !tbaa !12
  %10 = getelementptr inbounds i8, ptr %4, i64 %.sink133
  store volatile i32 0, ptr %10, align 4, !tbaa !12
  %11 = getelementptr inbounds i8, ptr %4, i64 %.sink131
  store volatile i32 %.sink, ptr %11, align 4, !tbaa !12
  %12 = tail call i32 @DMA_CalcBaseAndBitshift(ptr noundef nonnull %0)
  %13 = zext i32 %12 to i64
  %14 = inttoptr i64 %13 to ptr
  %15 = getelementptr inbounds i8, ptr %0, i64 128
  %16 = load i32, ptr %15, align 8, !tbaa !15
  %17 = and i32 %16, 31
  %18 = shl i32 %.sink126, %17
  %19 = getelementptr inbounds i8, ptr %14, i64 %.sink137
  store volatile i32 %18, ptr %19, align 4, !tbaa !12
  tail call void @DMA_CalcDMAMUXChannelBaseAndMask(ptr noundef nonnull %0)
  %20 = getelementptr inbounds i8, ptr %0, i64 136
  %21 = load ptr, ptr %20, align 8, !tbaa !16
  %.not = icmp eq ptr %21, null
  br i1 %.not, label %28, label %22

22:                                               ; preds = %.critedge118
  store volatile i32 0, ptr %21, align 4, !tbaa !17
  %23 = getelementptr inbounds i8, ptr %0, i64 152
  %24 = load i32, ptr %23, align 8, !tbaa !19
  %25 = getelementptr inbounds i8, ptr %0, i64 144
  %26 = load ptr, ptr %25, align 8, !tbaa !20
  %27 = getelementptr inbounds i8, ptr %26, i64 4
  store volatile i32 %24, ptr %27, align 4, !tbaa !21
  br label %28

28:                                               ; preds = %22, %.critedge118
  %29 = getelementptr inbounds i8, ptr %0, i64 8
  %30 = load i32, ptr %29, align 8, !tbaa !23
  %31 = add i32 %30, -1
  %or.cond = icmp ult i32 %31, 8
  br i1 %or.cond, label %32, label %40

32:                                               ; preds = %28
  tail call void @DMA_CalcDMAMUXRequestGenBaseAndMask(ptr noundef nonnull %0)
  %33 = getelementptr inbounds i8, ptr %0, i64 160
  %34 = load ptr, ptr %33, align 8, !tbaa !24
  store volatile i32 0, ptr %34, align 4, !tbaa !17
  %35 = getelementptr inbounds i8, ptr %0, i64 176
  %36 = load i32, ptr %35, align 8, !tbaa !25
  %37 = getelementptr inbounds i8, ptr %0, i64 168
  %38 = load ptr, ptr %37, align 8, !tbaa !26
  %39 = getelementptr inbounds i8, ptr %38, i64 4
  store volatile i32 %36, ptr %39, align 4, !tbaa !21
  br label %40

40:                                               ; preds = %32, %28
  %41 = getelementptr inbounds i8, ptr %0, i64 160
  %42 = getelementptr inbounds i8, ptr %0, i64 72
  %43 = getelementptr inbounds i8, ptr %0, i64 120
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(48) %42, i8 0, i64 48, i1 false)
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(20) %41, i8 0, i64 20, i1 false)
  store volatile i32 0, ptr %43, align 8, !tbaa !27
  %44 = getelementptr inbounds i8, ptr %0, i64 60
  store volatile i32 0, ptr %44, align 4, !tbaa !28
  %45 = getelementptr inbounds i8, ptr %0, i64 56
  store i32 0, ptr %45, align 8, !tbaa !29
  br label %46

46:                                               ; preds = %3, %1, %40
  %.0 = phi i32 [ 0, %40 ], [ 1, %1 ], [ 1, %3 ]
  ret i32 %.0
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"__DMA_HandleTypeDef", !7, i64 0, !10, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!11 = !{!"int", !8, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!14, !11, i64 0}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!15 = !{!6, !11, i64 128}
!16 = !{!6, !7, i64 136}
!17 = !{!18, !11, i64 0}
!18 = !{!"", !11, i64 0}
!19 = !{!6, !11, i64 152}
!20 = !{!6, !7, i64 144}
!21 = !{!22, !11, i64 4}
!22 = !{!"", !11, i64 0, !11, i64 4}
!23 = !{!6, !11, i64 8}
!24 = !{!6, !7, i64 160}
!25 = !{!6, !11, i64 176}
!26 = !{!6, !7, i64 168}
!27 = !{!6, !11, i64 120}
!28 = !{!6, !11, i64 60}
!29 = !{!6, !11, i64 56}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass