; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Enable)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.DLYB_TypeDef = type { i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @DelayBlock_Enable(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 1, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %11, i32 0, i32 0
  store volatile i32 3, ptr %12, align 4, !tbaa !11
  br label %13

13:                                               ; preds = %49, %1
  %14 = load i32, ptr %7, align 4, !tbaa !9
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %19

16:                                               ; preds = %13
  %17 = load i32, ptr %4, align 4, !tbaa !9
  %18 = icmp ult i32 %17, 128
  br label %19

19:                                               ; preds = %16, %13
  %20 = phi i1 [ false, %13 ], [ %18, %16 ]
  br i1 %20, label %21, label %52

21:                                               ; preds = %19
  %22 = load i32, ptr %4, align 4, !tbaa !9
  %23 = shl i32 %22, 8
  %24 = or i32 12, %23
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %25, i32 0, i32 1
  store volatile i32 %24, ptr %26, align 4, !tbaa !13
  call void @HAL_Delay(i32 noundef 1)
  %27 = load ptr, ptr %3, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %27, i32 0, i32 1
  %29 = load volatile i32, ptr %28, align 4, !tbaa !13
  %30 = zext i32 %29 to i64
  %31 = and i64 %30, 2147483648
  %32 = trunc i64 %31 to i32
  store i32 %32, ptr %8, align 4, !tbaa !9
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %33, i32 0, i32 1
  %35 = load volatile i32, ptr %34, align 4, !tbaa !13
  %36 = zext i32 %35 to i64
  %37 = and i64 %36, 268369920
  %38 = trunc i64 %37 to i32
  store i32 %38, ptr %9, align 4, !tbaa !9
  %39 = load i32, ptr %8, align 4, !tbaa !9
  %40 = icmp ne i32 %39, 0
  br i1 %40, label %41, label %49

41:                                               ; preds = %21
  %42 = load i32, ptr %9, align 4, !tbaa !9
  %43 = icmp ne i32 %42, 0
  br i1 %43, label %44, label %49

44:                                               ; preds = %41
  %45 = load i32, ptr %9, align 4, !tbaa !9
  %46 = zext i32 %45 to i64
  %47 = icmp ne i64 %46, 201326592
  br i1 %47, label %48, label %49

48:                                               ; preds = %44
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %48, %44, %41, %21
  %50 = load i32, ptr %4, align 4, !tbaa !9
  %51 = add i32 %50, 1
  store i32 %51, ptr %4, align 4, !tbaa !9
  br label %13, !llvm.loop !14

52:                                               ; preds = %19
  %53 = load i32, ptr %4, align 4, !tbaa !9
  %54 = icmp ne i32 128, %53
  br i1 %54, label %55, label %96

55:                                               ; preds = %52
  %56 = load ptr, ptr %3, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %56, i32 0, i32 1
  %58 = load volatile i32, ptr %57, align 4, !tbaa !13
  %59 = zext i32 %58 to i64
  %60 = and i64 %59, 268369920
  %61 = lshr i64 %60, 16
  %62 = trunc i64 %61 to i32
  store i32 %62, ptr %6, align 4, !tbaa !9
  store i32 10, ptr %5, align 4, !tbaa !9
  br label %63

63:                                               ; preds = %73, %55
  %64 = load i32, ptr %5, align 4, !tbaa !9
  %65 = icmp ugt i32 %64, 0
  br i1 %65, label %66, label %71

66:                                               ; preds = %63
  %67 = load i32, ptr %6, align 4, !tbaa !9
  %68 = load i32, ptr %5, align 4, !tbaa !9
  %69 = lshr i32 %67, %68
  %70 = icmp eq i32 %69, 0
  br label %71

71:                                               ; preds = %66, %63
  %72 = phi i1 [ false, %63 ], [ %70, %66 ]
  br i1 %72, label %73, label %76

73:                                               ; preds = %71
  %74 = load i32, ptr %5, align 4, !tbaa !9
  %75 = add i32 %74, -1
  store i32 %75, ptr %5, align 4, !tbaa !9
  br label %63, !llvm.loop !16

76:                                               ; preds = %71
  %77 = load i32, ptr %5, align 4, !tbaa !9
  %78 = icmp ne i32 0, %77
  br i1 %78, label %79, label %95

79:                                               ; preds = %76
  %80 = load ptr, ptr %3, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %80, i32 0, i32 1
  %82 = load volatile i32, ptr %81, align 4, !tbaa !13
  %83 = zext i32 %82 to i64
  %84 = and i64 %83, -16
  %85 = load i32, ptr %5, align 4, !tbaa !9
  %86 = udiv i32 %85, 2
  %87 = add i32 %86, 1
  %88 = zext i32 %87 to i64
  %89 = or i64 %84, %88
  %90 = trunc i64 %89 to i32
  %91 = load ptr, ptr %3, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %91, i32 0, i32 1
  store volatile i32 %90, ptr %92, align 4, !tbaa !13
  %93 = load ptr, ptr %3, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.DLYB_TypeDef, ptr %93, i32 0, i32 0
  store volatile i32 1, ptr %94, align 4, !tbaa !11
  store i32 0, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %99

95:                                               ; preds = %76
  br label %96

96:                                               ; preds = %95, %52
  %97 = load ptr, ptr %3, align 8, !tbaa !5
  %98 = call i32 @DelayBlock_Disable(ptr noundef %97)
  store i32 1, ptr %2, align 4
  store i32 1, ptr %10, align 4
  br label %99

99:                                               ; preds = %96, %79
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %100 = load i32, ptr %2, align 4
  ret i32 %100
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @HAL_Delay(i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @DelayBlock_Disable(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"", !10, i64 0, !10, i64 4}
!13 = !{!12, !10, i64 4}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @DelayBlock_Enable(ptr noundef %0) local_unnamed_addr #0 {
  store volatile i32 3, ptr %0, align 4, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 4
  br label %3

3:                                                ; preds = %1, %3
  %.02731 = phi i32 [ 0, %1 ], [ %10, %3 ]
  %4 = shl nuw nsw i32 %.02731, 8
  %5 = or disjoint i32 %4, 12
  store volatile i32 %5, ptr %2, align 4, !tbaa !10
  tail call void @HAL_Delay(i32 noundef 1) #2
  %6 = load volatile i32, ptr %2, align 4, !tbaa !10
  %7 = load volatile i32, ptr %2, align 4, !tbaa !10
  %8 = and i32 %7, 268369920
  %.fr = freeze i32 %6
  %9 = icmp sgt i32 %.fr, -1
  %switch.selectcmp.case1 = icmp eq i32 %8, 201326592
  %switch.selectcmp.case2 = icmp eq i32 %8, 0
  %switch.selectcmp = or i1 %switch.selectcmp.case1, %switch.selectcmp.case2
  %narrow = select i1 %9, i1 true, i1 %switch.selectcmp
  %10 = add nuw nsw i32 %.02731, 1
  %11 = icmp ult i32 %.02731, 127
  %12 = select i1 %narrow, i1 %11, i1 false
  br i1 %12, label %3, label %13, !llvm.loop !11

13:                                               ; preds = %3
  %.not = icmp eq i32 %10, 128
  br i1 %.not, label %31, label %14

14:                                               ; preds = %13
  %15 = load volatile i32, ptr %2, align 4, !tbaa !10
  %16 = lshr i32 %15, 16
  %17 = and i32 %16, 4095
  br label %18

18:                                               ; preds = %18, %14
  %.029 = phi i32 [ 10, %14 ], [ %23, %18 ]
  %19 = icmp ne i32 %.029, 0
  %20 = lshr i32 %17, %.029
  %21 = icmp eq i32 %20, 0
  %22 = select i1 %19, i1 %21, i1 false
  %23 = add nsw i32 %.029, -1
  br i1 %22, label %18, label %24, !llvm.loop !13

24:                                               ; preds = %18
  %.not30 = icmp eq i32 %.029, 0
  br i1 %.not30, label %31, label %25

25:                                               ; preds = %24
  %26 = load volatile i32, ptr %2, align 4, !tbaa !10
  %27 = and i32 %26, -16
  %28 = lshr i32 %.029, 1
  %29 = add nuw i32 %28, 1
  %30 = or i32 %27, %29
  store volatile i32 %30, ptr %2, align 4, !tbaa !10
  store volatile i32 1, ptr %0, align 4, !tbaa !5
  br label %33

31:                                               ; preds = %24, %13
  %32 = tail call i32 @DelayBlock_Disable(ptr noundef nonnull %0)
  br label %33

33:                                               ; preds = %31, %25
  %.0 = phi i32 [ 0, %25 ], [ 1, %31 ]
  ret i32 %.0
}

declare void @HAL_Delay(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @DelayBlock_Disable(ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 4}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass