; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_IC_Stop_IT(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %5 = load i32, ptr %4, align 4, !tbaa !9
  switch i32 %5, label %42 [
    i32 0, label %6
    i32 4, label %15
    i32 8, label %24
    i32 12, label %33
  ]

6:                                                ; preds = %2
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %7, i32 0, i32 0
  %9 = load ptr, ptr %8, align 8, !tbaa !11
  %10 = getelementptr inbounds %struct.TIM_TypeDef, ptr %9, i32 0, i32 3
  %11 = load volatile i32, ptr %10, align 4, !tbaa !14
  %12 = zext i32 %11 to i64
  %13 = and i64 %12, -3
  %14 = trunc i64 %13 to i32
  store volatile i32 %14, ptr %10, align 4, !tbaa !14
  br label %43

15:                                               ; preds = %2
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %16, i32 0, i32 0
  %18 = load ptr, ptr %17, align 8, !tbaa !11
  %19 = getelementptr inbounds %struct.TIM_TypeDef, ptr %18, i32 0, i32 3
  %20 = load volatile i32, ptr %19, align 4, !tbaa !14
  %21 = zext i32 %20 to i64
  %22 = and i64 %21, -5
  %23 = trunc i64 %22 to i32
  store volatile i32 %23, ptr %19, align 4, !tbaa !14
  br label %43

24:                                               ; preds = %2
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !11
  %28 = getelementptr inbounds %struct.TIM_TypeDef, ptr %27, i32 0, i32 3
  %29 = load volatile i32, ptr %28, align 4, !tbaa !14
  %30 = zext i32 %29 to i64
  %31 = and i64 %30, -9
  %32 = trunc i64 %31 to i32
  store volatile i32 %32, ptr %28, align 4, !tbaa !14
  br label %43

33:                                               ; preds = %2
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !11
  %37 = getelementptr inbounds %struct.TIM_TypeDef, ptr %36, i32 0, i32 3
  %38 = load volatile i32, ptr %37, align 4, !tbaa !14
  %39 = zext i32 %38 to i64
  %40 = and i64 %39, -17
  %41 = trunc i64 %40 to i32
  store volatile i32 %41, ptr %37, align 4, !tbaa !14
  br label %43

42:                                               ; preds = %2
  br label %43

43:                                               ; preds = %42, %33, %24, %15, %6
  %44 = load ptr, ptr %3, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !11
  %47 = load i32, ptr %4, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %46, i32 noundef %47, i32 noundef 0)
  br label %48

48:                                               ; preds = %43
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !11
  %52 = getelementptr inbounds %struct.TIM_TypeDef, ptr %51, i32 0, i32 8
  %53 = load volatile i32, ptr %52, align 4, !tbaa !16
  %54 = and i32 %53, 4369
  %55 = zext i32 %54 to i64
  %56 = icmp eq i64 %55, 0
  br i1 %56, label %57, label %76

57:                                               ; preds = %48
  %58 = load ptr, ptr %3, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !11
  %61 = getelementptr inbounds %struct.TIM_TypeDef, ptr %60, i32 0, i32 8
  %62 = load volatile i32, ptr %61, align 4, !tbaa !16
  %63 = and i32 %62, 1092
  %64 = zext i32 %63 to i64
  %65 = icmp eq i64 %64, 0
  br i1 %65, label %66, label %75

66:                                               ; preds = %57
  %67 = load ptr, ptr %3, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !11
  %70 = getelementptr inbounds %struct.TIM_TypeDef, ptr %69, i32 0, i32 0
  %71 = load volatile i32, ptr %70, align 4, !tbaa !17
  %72 = zext i32 %71 to i64
  %73 = and i64 %72, -2
  %74 = trunc i64 %73 to i32
  store volatile i32 %74, ptr %70, align 4, !tbaa !17
  br label %75

75:                                               ; preds = %66, %57
  br label %76

76:                                               ; preds = %75, %48
  br label %77

77:                                               ; preds = %76
  ret i32 0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!15, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!16 = !{!15, !10, i64 32}
!17 = !{!15, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.HAL_TIM_IC_Stop_IT = private unnamed_addr constant [4 x i32] [i32 -3, i32 -5, i32 -9, i32 -17], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @HAL_TIM_IC_Stop_IT(ptr nocapture noundef readonly %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  %.pre = load ptr, ptr %0, align 8, !tbaa !5
  %4 = icmp ult i32 %3, 4
  br i1 %4, label %switch.lookup, label %._crit_edge

switch.lookup:                                    ; preds = %2
  %5 = zext nneg i32 %3 to i64
  %switch.gep = getelementptr inbounds [4 x i32], ptr @switch.table.HAL_TIM_IC_Stop_IT, i64 0, i64 %5
  %switch.load = load i32, ptr %switch.gep, align 4
  %6 = getelementptr inbounds i8, ptr %.pre, i64 12
  %7 = load volatile i32, ptr %6, align 4, !tbaa !12
  %8 = and i32 %7, %switch.load
  store volatile i32 %8, ptr %6, align 4, !tbaa !12
  br label %._crit_edge

._crit_edge:                                      ; preds = %2, %switch.lookup
  tail call void @TIM_CCxChannelCmd(ptr noundef %.pre, i32 noundef %1, i32 noundef 0)
  %9 = load ptr, ptr %0, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %9, i64 32
  %11 = load volatile i32, ptr %10, align 4, !tbaa !14
  %12 = and i32 %11, 4369
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %14, label %21

14:                                               ; preds = %._crit_edge
  %15 = load volatile i32, ptr %10, align 4, !tbaa !14
  %16 = and i32 %15, 1092
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %21

18:                                               ; preds = %14
  %19 = load volatile i32, ptr %9, align 4, !tbaa !15
  %20 = and i32 %19, -2
  store volatile i32 %20, ptr %9, align 4, !tbaa !15
  br label %21

21:                                               ; preds = %._crit_edge, %18, %14
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!13, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!14 = !{!13, !11, i64 32}
!15 = !{!13, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass