; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (8b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Read_SpareArea_8b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #4
  %19 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %19, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %20, ptr %17, align 8, !tbaa !5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %21, i32 0, i32 3
  %23 = load volatile i32, ptr %22, align 8, !tbaa !11
  %24 = icmp eq i32 %23, 2
  br i1 %24, label %25, label %26

25:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %305

26:                                               ; preds = %4
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %27, i32 0, i32 3
  %29 = load volatile i32, ptr %28, align 8, !tbaa !11
  %30 = icmp eq i32 %29, 1
  br i1 %30, label %31, label %302

31:                                               ; preds = %26
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %33, i32 0, i32 2
  %35 = load i32, ptr %34, align 4, !tbaa !14
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %305

38:                                               ; preds = %32
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %39, i32 0, i32 2
  store i32 1, ptr %40, align 4, !tbaa !14
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %44, i32 0, i32 3
  store volatile i32 2, ptr %45, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %46 = load ptr, ptr %7, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %46, i32 0, i32 0
  %48 = load i16, ptr %47, align 2, !tbaa !15
  %49 = zext i16 %48 to i32
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %50, i32 0, i32 2
  %52 = load i16, ptr %51, align 2, !tbaa !18
  %53 = zext i16 %52 to i32
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %54, i32 0, i32 1
  %56 = load i16, ptr %55, align 2, !tbaa !19
  %57 = zext i16 %56 to i32
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %58, i32 0, i32 4
  %60 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %59, i32 0, i32 5
  %61 = load i32, ptr %60, align 4, !tbaa !20
  %62 = mul i32 %57, %61
  %63 = add i32 %53, %62
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %64, i32 0, i32 4
  %66 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %65, i32 0, i32 2
  %67 = load i32, ptr %66, align 4, !tbaa !21
  %68 = mul i32 %63, %67
  %69 = add i32 %49, %68
  store i32 %69, ptr %14, align 4, !tbaa !9
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %70, i32 0, i32 4
  %72 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %71, i32 0, i32 0
  %73 = load i32, ptr %72, align 4, !tbaa !22
  store i32 %73, ptr %15, align 4, !tbaa !9
  br label %74

74:                                               ; preds = %287, %43
  %75 = load i32, ptr %16, align 4, !tbaa !9
  %76 = icmp ne i32 %75, 0
  br i1 %76, label %77, label %89

77:                                               ; preds = %74
  %78 = load i32, ptr %14, align 4, !tbaa !9
  %79 = load ptr, ptr %6, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %79, i32 0, i32 4
  %81 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %80, i32 0, i32 2
  %82 = load i32, ptr %81, align 4, !tbaa !21
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %83, i32 0, i32 4
  %85 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %84, i32 0, i32 3
  %86 = load i32, ptr %85, align 4, !tbaa !23
  %87 = mul i32 %82, %86
  %88 = icmp ult i32 %78, %87
  br label %89

89:                                               ; preds = %77, %74
  %90 = phi i1 [ false, %74 ], [ %88, %77 ]
  br i1 %90, label %91, label %294

91:                                               ; preds = %89
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %92, i32 0, i32 4
  %94 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %93, i32 0, i32 0
  %95 = load i32, ptr %94, align 4, !tbaa !22
  %96 = icmp ule i32 %95, 512
  br i1 %96, label %97, label %156

97:                                               ; preds = %91
  %98 = load i32, ptr %12, align 4, !tbaa !9
  %99 = or i32 %98, 65536
  %100 = zext i32 %99 to i64
  %101 = inttoptr i64 %100 to ptr
  store volatile i8 80, ptr %101, align 1, !tbaa !24
  call void @__DSB()
  %102 = load ptr, ptr %6, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %102, i32 0, i32 4
  %104 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %103, i32 0, i32 2
  %105 = load i32, ptr %104, align 4, !tbaa !21
  %106 = load ptr, ptr %6, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %106, i32 0, i32 4
  %108 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %107, i32 0, i32 3
  %109 = load i32, ptr %108, align 4, !tbaa !23
  %110 = mul i32 %105, %109
  %111 = icmp ule i32 %110, 65535
  br i1 %111, label %112, label %130

112:                                              ; preds = %97
  %113 = load i32, ptr %12, align 4, !tbaa !9
  %114 = or i32 %113, 131072
  %115 = zext i32 %114 to i64
  %116 = inttoptr i64 %115 to ptr
  store volatile i8 0, ptr %116, align 1, !tbaa !24
  call void @__DSB()
  %117 = load i32, ptr %14, align 4, !tbaa !9
  %118 = trunc i32 %117 to i8
  %119 = load i32, ptr %12, align 4, !tbaa !9
  %120 = or i32 %119, 131072
  %121 = zext i32 %120 to i64
  %122 = inttoptr i64 %121 to ptr
  store volatile i8 %118, ptr %122, align 1, !tbaa !24
  call void @__DSB()
  %123 = load i32, ptr %14, align 4, !tbaa !9
  %124 = lshr i32 %123, 8
  %125 = trunc i32 %124 to i8
  %126 = load i32, ptr %12, align 4, !tbaa !9
  %127 = or i32 %126, 131072
  %128 = zext i32 %127 to i64
  %129 = inttoptr i64 %128 to ptr
  store volatile i8 %125, ptr %129, align 1, !tbaa !24
  call void @__DSB()
  br label %155

130:                                              ; preds = %97
  %131 = load i32, ptr %12, align 4, !tbaa !9
  %132 = or i32 %131, 131072
  %133 = zext i32 %132 to i64
  %134 = inttoptr i64 %133 to ptr
  store volatile i8 0, ptr %134, align 1, !tbaa !24
  call void @__DSB()
  %135 = load i32, ptr %14, align 4, !tbaa !9
  %136 = trunc i32 %135 to i8
  %137 = load i32, ptr %12, align 4, !tbaa !9
  %138 = or i32 %137, 131072
  %139 = zext i32 %138 to i64
  %140 = inttoptr i64 %139 to ptr
  store volatile i8 %136, ptr %140, align 1, !tbaa !24
  call void @__DSB()
  %141 = load i32, ptr %14, align 4, !tbaa !9
  %142 = lshr i32 %141, 8
  %143 = trunc i32 %142 to i8
  %144 = load i32, ptr %12, align 4, !tbaa !9
  %145 = or i32 %144, 131072
  %146 = zext i32 %145 to i64
  %147 = inttoptr i64 %146 to ptr
  store volatile i8 %143, ptr %147, align 1, !tbaa !24
  call void @__DSB()
  %148 = load i32, ptr %14, align 4, !tbaa !9
  %149 = lshr i32 %148, 16
  %150 = trunc i32 %149 to i8
  %151 = load i32, ptr %12, align 4, !tbaa !9
  %152 = or i32 %151, 131072
  %153 = zext i32 %152 to i64
  %154 = inttoptr i64 %153 to ptr
  store volatile i8 %150, ptr %154, align 1, !tbaa !24
  call void @__DSB()
  br label %155

155:                                              ; preds = %130, %112
  br label %233

156:                                              ; preds = %91
  %157 = load i32, ptr %12, align 4, !tbaa !9
  %158 = or i32 %157, 65536
  %159 = zext i32 %158 to i64
  %160 = inttoptr i64 %159 to ptr
  store volatile i8 0, ptr %160, align 1, !tbaa !24
  call void @__DSB()
  %161 = load ptr, ptr %6, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %161, i32 0, i32 4
  %163 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %162, i32 0, i32 2
  %164 = load i32, ptr %163, align 4, !tbaa !21
  %165 = load ptr, ptr %6, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %165, i32 0, i32 4
  %167 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %166, i32 0, i32 3
  %168 = load i32, ptr %167, align 4, !tbaa !23
  %169 = mul i32 %164, %168
  %170 = icmp ule i32 %169, 65535
  br i1 %170, label %171, label %198

171:                                              ; preds = %156
  %172 = load i32, ptr %15, align 4, !tbaa !9
  %173 = trunc i32 %172 to i8
  %174 = load i32, ptr %12, align 4, !tbaa !9
  %175 = or i32 %174, 131072
  %176 = zext i32 %175 to i64
  %177 = inttoptr i64 %176 to ptr
  store volatile i8 %173, ptr %177, align 1, !tbaa !24
  call void @__DSB()
  %178 = load i32, ptr %15, align 4, !tbaa !9
  %179 = lshr i32 %178, 8
  %180 = trunc i32 %179 to i8
  %181 = load i32, ptr %12, align 4, !tbaa !9
  %182 = or i32 %181, 131072
  %183 = zext i32 %182 to i64
  %184 = inttoptr i64 %183 to ptr
  store volatile i8 %180, ptr %184, align 1, !tbaa !24
  call void @__DSB()
  %185 = load i32, ptr %14, align 4, !tbaa !9
  %186 = trunc i32 %185 to i8
  %187 = load i32, ptr %12, align 4, !tbaa !9
  %188 = or i32 %187, 131072
  %189 = zext i32 %188 to i64
  %190 = inttoptr i64 %189 to ptr
  store volatile i8 %186, ptr %190, align 1, !tbaa !24
  call void @__DSB()
  %191 = load i32, ptr %14, align 4, !tbaa !9
  %192 = lshr i32 %191, 8
  %193 = trunc i32 %192 to i8
  %194 = load i32, ptr %12, align 4, !tbaa !9
  %195 = or i32 %194, 131072
  %196 = zext i32 %195 to i64
  %197 = inttoptr i64 %196 to ptr
  store volatile i8 %193, ptr %197, align 1, !tbaa !24
  call void @__DSB()
  br label %232

198:                                              ; preds = %156
  %199 = load i32, ptr %15, align 4, !tbaa !9
  %200 = trunc i32 %199 to i8
  %201 = load i32, ptr %12, align 4, !tbaa !9
  %202 = or i32 %201, 131072
  %203 = zext i32 %202 to i64
  %204 = inttoptr i64 %203 to ptr
  store volatile i8 %200, ptr %204, align 1, !tbaa !24
  call void @__DSB()
  %205 = load i32, ptr %15, align 4, !tbaa !9
  %206 = lshr i32 %205, 8
  %207 = trunc i32 %206 to i8
  %208 = load i32, ptr %12, align 4, !tbaa !9
  %209 = or i32 %208, 131072
  %210 = zext i32 %209 to i64
  %211 = inttoptr i64 %210 to ptr
  store volatile i8 %207, ptr %211, align 1, !tbaa !24
  call void @__DSB()
  %212 = load i32, ptr %14, align 4, !tbaa !9
  %213 = trunc i32 %212 to i8
  %214 = load i32, ptr %12, align 4, !tbaa !9
  %215 = or i32 %214, 131072
  %216 = zext i32 %215 to i64
  %217 = inttoptr i64 %216 to ptr
  store volatile i8 %213, ptr %217, align 1, !tbaa !24
  call void @__DSB()
  %218 = load i32, ptr %14, align 4, !tbaa !9
  %219 = lshr i32 %218, 8
  %220 = trunc i32 %219 to i8
  %221 = load i32, ptr %12, align 4, !tbaa !9
  %222 = or i32 %221, 131072
  %223 = zext i32 %222 to i64
  %224 = inttoptr i64 %223 to ptr
  store volatile i8 %220, ptr %224, align 1, !tbaa !24
  call void @__DSB()
  %225 = load i32, ptr %14, align 4, !tbaa !9
  %226 = lshr i32 %225, 16
  %227 = trunc i32 %226 to i8
  %228 = load i32, ptr %12, align 4, !tbaa !9
  %229 = or i32 %228, 131072
  %230 = zext i32 %229 to i64
  %231 = inttoptr i64 %230 to ptr
  store volatile i8 %227, ptr %231, align 1, !tbaa !24
  call void @__DSB()
  br label %232

232:                                              ; preds = %198, %171
  br label %233

233:                                              ; preds = %232, %155
  %234 = load i32, ptr %12, align 4, !tbaa !9
  %235 = or i32 %234, 65536
  %236 = zext i32 %235 to i64
  %237 = inttoptr i64 %236 to ptr
  store volatile i8 48, ptr %237, align 1, !tbaa !24
  call void @__DSB()
  %238 = load ptr, ptr %6, align 8, !tbaa !5
  %239 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %238, i32 0, i32 4
  %240 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %239, i32 0, i32 6
  %241 = load i32, ptr %240, align 4, !tbaa !25
  %242 = icmp eq i32 %241, 1
  br i1 %242, label %243, label %268

243:                                              ; preds = %233
  %244 = call i32 @HAL_GetTick()
  store i32 %244, ptr %11, align 4, !tbaa !9
  br label %245

245:                                              ; preds = %262, %243
  %246 = load ptr, ptr %6, align 8, !tbaa !5
  %247 = call i32 @HAL_NAND_Read_Status(ptr noundef %246)
  %248 = icmp ne i32 %247, 64
  br i1 %248, label %249, label %263

249:                                              ; preds = %245
  %250 = call i32 @HAL_GetTick()
  %251 = load i32, ptr %11, align 4, !tbaa !9
  %252 = sub i32 %250, %251
  %253 = icmp ugt i32 %252, 16777216
  br i1 %253, label %254, label %262

254:                                              ; preds = %249
  %255 = load ptr, ptr %6, align 8, !tbaa !5
  %256 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %255, i32 0, i32 3
  store volatile i32 3, ptr %256, align 8, !tbaa !11
  br label %257

257:                                              ; preds = %254
  %258 = load ptr, ptr %6, align 8, !tbaa !5
  %259 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %258, i32 0, i32 2
  store i32 0, ptr %259, align 4, !tbaa !14
  br label %260

260:                                              ; preds = %257
  br label %261

261:                                              ; preds = %260
  store i32 3, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %305

262:                                              ; preds = %249
  br label %245, !llvm.loop !26

263:                                              ; preds = %245
  %264 = load i32, ptr %12, align 4, !tbaa !9
  %265 = or i32 %264, 65536
  %266 = zext i32 %265 to i64
  %267 = inttoptr i64 %266 to ptr
  store volatile i8 0, ptr %267, align 1, !tbaa !24
  call void @__DSB()
  br label %268

268:                                              ; preds = %263, %233
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %269

269:                                              ; preds = %284, %268
  %270 = load i32, ptr %10, align 4, !tbaa !9
  %271 = load ptr, ptr %6, align 8, !tbaa !5
  %272 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %271, i32 0, i32 4
  %273 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %272, i32 0, i32 1
  %274 = load i32, ptr %273, align 4, !tbaa !28
  %275 = icmp ult i32 %270, %274
  br i1 %275, label %276, label %287

276:                                              ; preds = %269
  %277 = load i32, ptr %12, align 4, !tbaa !9
  %278 = zext i32 %277 to i64
  %279 = inttoptr i64 %278 to ptr
  %280 = load i8, ptr %279, align 1, !tbaa !24
  %281 = load ptr, ptr %17, align 8, !tbaa !5
  store i8 %280, ptr %281, align 1, !tbaa !24
  %282 = load ptr, ptr %17, align 8, !tbaa !5
  %283 = getelementptr inbounds i8, ptr %282, i32 1
  store ptr %283, ptr %17, align 8, !tbaa !5
  br label %284

284:                                              ; preds = %276
  %285 = load i32, ptr %10, align 4, !tbaa !9
  %286 = add i32 %285, 1
  store i32 %286, ptr %10, align 4, !tbaa !9
  br label %269, !llvm.loop !29

287:                                              ; preds = %269
  %288 = load i32, ptr %13, align 4, !tbaa !9
  %289 = add i32 %288, 1
  store i32 %289, ptr %13, align 4, !tbaa !9
  %290 = load i32, ptr %16, align 4, !tbaa !9
  %291 = add i32 %290, -1
  store i32 %291, ptr %16, align 4, !tbaa !9
  %292 = load i32, ptr %14, align 4, !tbaa !9
  %293 = add i32 %292, 1
  store i32 %293, ptr %14, align 4, !tbaa !9
  br label %74, !llvm.loop !30

294:                                              ; preds = %89
  %295 = load ptr, ptr %6, align 8, !tbaa !5
  %296 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %295, i32 0, i32 3
  store volatile i32 1, ptr %296, align 8, !tbaa !11
  br label %297

297:                                              ; preds = %294
  %298 = load ptr, ptr %6, align 8, !tbaa !5
  %299 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %298, i32 0, i32 2
  store i32 0, ptr %299, align 4, !tbaa !14
  br label %300

300:                                              ; preds = %297
  br label %301

301:                                              ; preds = %300
  br label %303

302:                                              ; preds = %26
  store i32 1, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %305

303:                                              ; preds = %301
  br label %304

304:                                              ; preds = %303
  store i32 0, ptr %5, align 4
  store i32 1, ptr %18, align 4
  br label %305

305:                                              ; preds = %304, %302, %261, %37, %25
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %306 = load i32, ptr %5, align 4
  ret i32 %306
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 44}
!23 = !{!12, !10, i64 56}
!24 = !{!7, !7, i64 0}
!25 = !{!12, !10, i64 68}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!12, !10, i64 48}
!29 = distinct !{!29, !27}
!30 = distinct !{!30, !27}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Read_SpareArea_8b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %86, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %86

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %86, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not80 = icmp eq i32 %3, 0
  br i1 %.not80, label %.sink.split89, label %.lr.ph85

.lr.ph85:                                         ; preds = %15
  %18 = load i32, ptr %16, align 4, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %0, i64 64
  %20 = load i32, ptr %19, align 4, !tbaa !14
  %21 = getelementptr inbounds i8, ptr %1, i64 2
  %22 = load i16, ptr %21, align 2, !tbaa !15
  %23 = zext i16 %22 to i32
  %24 = mul i32 %20, %23
  %25 = getelementptr inbounds i8, ptr %1, i64 4
  %26 = load i16, ptr %25, align 2, !tbaa !18
  %27 = zext i16 %26 to i32
  %28 = add i32 %24, %27
  %29 = load i32, ptr %17, align 4, !tbaa !19
  %30 = mul i32 %28, %29
  %31 = load i16, ptr %1, align 2, !tbaa !20
  %32 = zext i16 %31 to i32
  %33 = add i32 %30, %32
  %34 = getelementptr inbounds i8, ptr %0, i64 56
  %35 = trunc i32 %18 to i8
  %36 = lshr i32 %18, 8
  %37 = trunc i32 %36 to i8
  %38 = getelementptr inbounds i8, ptr %0, i64 68
  %39 = getelementptr inbounds i8, ptr %0, i64 48
  br label %40

40:                                               ; preds = %.lr.ph85, %._crit_edge
  %.083 = phi ptr [ %2, %.lr.ph85 ], [ %.1.lcssa, %._crit_edge ]
  %.07282 = phi i32 [ %3, %.lr.ph85 ], [ %84, %._crit_edge ]
  %.07481 = phi i32 [ %33, %.lr.ph85 ], [ %85, %._crit_edge ]
  %41 = load i32, ptr %17, align 4, !tbaa !19
  %42 = load i32, ptr %34, align 4, !tbaa !21
  %43 = mul i32 %42, %41
  %44 = icmp ult i32 %.07481, %43
  br i1 %44, label %45, label %.sink.split89

45:                                               ; preds = %40
  %46 = load i32, ptr %16, align 4, !tbaa !13
  %47 = icmp ult i32 %46, 513
  br i1 %47, label %48, label %56

48:                                               ; preds = %45
  store volatile i8 80, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %49 = load i32, ptr %17, align 4, !tbaa !19
  %50 = load i32, ptr %34, align 4, !tbaa !21
  %51 = mul i32 %50, %49
  %52 = icmp ult i32 %51, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %53 = trunc i32 %.07481 to i8
  store volatile i8 %53, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %54 = lshr i32 %.07481, 8
  %55 = trunc i32 %54 to i8
  store volatile i8 %55, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %52, label %66, label %.sink.split

56:                                               ; preds = %45
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %57 = load i32, ptr %17, align 4, !tbaa !19
  %58 = load i32, ptr %34, align 4, !tbaa !21
  %59 = mul i32 %58, %57
  %60 = icmp ult i32 %59, 65536
  store volatile i8 %35, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  store volatile i8 %37, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %61 = trunc i32 %.07481 to i8
  store volatile i8 %61, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  %62 = lshr i32 %.07481, 8
  %63 = trunc i32 %62 to i8
  store volatile i8 %63, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br i1 %60, label %66, label %.sink.split

.sink.split:                                      ; preds = %56, %48
  %64 = lshr i32 %.07481, 16
  %65 = trunc i32 %64 to i8
  store volatile i8 %65, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !22
  tail call void @__DSB()
  br label %66

66:                                               ; preds = %.sink.split, %56, %48
  store volatile i8 48, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  %67 = load i32, ptr %38, align 4, !tbaa !23
  %68 = icmp eq i32 %67, 1
  br i1 %68, label %69, label %78

69:                                               ; preds = %66
  %70 = tail call i32 @HAL_GetTick() #3
  br label %71

71:                                               ; preds = %73, %69
  %72 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not77 = icmp eq i32 %72, 64
  br i1 %.not77, label %77, label %73

73:                                               ; preds = %71
  %74 = tail call i32 @HAL_GetTick() #3
  %75 = sub i32 %74, %70
  %76 = icmp ugt i32 %75, 16777216
  br i1 %76, label %.sink.split89, label %71, !llvm.loop !24

77:                                               ; preds = %71
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !22
  tail call void @__DSB()
  br label %78

78:                                               ; preds = %77, %66
  %79 = load i32, ptr %39, align 4, !tbaa !26
  %.not87 = icmp eq i32 %79, 0
  br i1 %.not87, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %78
  %.pre = load i8, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !22
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %.179 = phi ptr [ %80, %.lr.ph ], [ %.083, %.lr.ph.preheader ]
  %.07678 = phi i32 [ %81, %.lr.ph ], [ 0, %.lr.ph.preheader ]
  store i8 %.pre, ptr %.179, align 1, !tbaa !22
  %80 = getelementptr inbounds i8, ptr %.179, i64 1
  %81 = add nuw i32 %.07678, 1
  %82 = load i32, ptr %39, align 4, !tbaa !26
  %83 = icmp ult i32 %81, %82
  br i1 %83, label %.lr.ph, label %._crit_edge, !llvm.loop !27

._crit_edge:                                      ; preds = %.lr.ph, %78
  %.1.lcssa = phi ptr [ %.083, %78 ], [ %80, %.lr.ph ]
  %84 = add i32 %.07282, -1
  %85 = add i32 %.07481, 1
  %.not = icmp eq i32 %84, 0
  br i1 %.not, label %.sink.split89, label %40, !llvm.loop !28

.sink.split89:                                    ; preds = %._crit_edge, %40, %73, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %73 ], [ 1, %40 ], [ 1, %._crit_edge ]
  %.073.ph = phi i32 [ 0, %15 ], [ 3, %73 ], [ 0, %40 ], [ 0, %._crit_edge ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %86

86:                                               ; preds = %.sink.split89, %8, %11, %4
  %.073 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.073.ph, %.sink.split89 ]
  ret i32 %.073
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 44}
!14 = !{!6, !11, i64 64}
!15 = !{!16, !17, i64 2}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !8, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!6, !11, i64 52}
!20 = !{!16, !17, i64 0}
!21 = !{!6, !11, i64 56}
!22 = !{!8, !8, i64 0}
!23 = !{!6, !11, i64 68}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!6, !11, i64 48}
!27 = distinct !{!27, !25}
!28 = distinct !{!28, !25}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass