; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConfigClockSource)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_ClockConfigTypeDef = type { i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_ETR_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_ConfigClockSource(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  br label %8

8:                                                ; preds = %2
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %9, i32 0, i32 4
  %11 = load i32, ptr %10, align 8, !tbaa !9
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 2, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %147

14:                                               ; preds = %8
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %15, i32 0, i32 4
  store i32 1, ptr %16, align 8, !tbaa !9
  br label %17

17:                                               ; preds = %14
  br label %18

18:                                               ; preds = %17
  br label %19

19:                                               ; preds = %18
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %20, i32 0, i32 5
  store volatile i32 2, ptr %21, align 4, !tbaa !13
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %22, i32 0, i32 0
  %24 = load ptr, ptr %23, align 8, !tbaa !14
  %25 = getelementptr inbounds %struct.TIM_TypeDef, ptr %24, i32 0, i32 2
  %26 = load volatile i32, ptr %25, align 4, !tbaa !15
  store i32 %26, ptr %6, align 4, !tbaa !17
  %27 = load i32, ptr %6, align 4, !tbaa !17
  %28 = zext i32 %27 to i64
  %29 = and i64 %28, -3211384
  %30 = trunc i64 %29 to i32
  store i32 %30, ptr %6, align 4, !tbaa !17
  %31 = load i32, ptr %6, align 4, !tbaa !17
  %32 = zext i32 %31 to i64
  %33 = and i64 %32, -65281
  %34 = trunc i64 %33 to i32
  store i32 %34, ptr %6, align 4, !tbaa !17
  %35 = load i32, ptr %6, align 4, !tbaa !17
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !14
  %39 = getelementptr inbounds %struct.TIM_TypeDef, ptr %38, i32 0, i32 2
  store volatile i32 %35, ptr %39, align 4, !tbaa !15
  %40 = load ptr, ptr %5, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %40, i32 0, i32 0
  %42 = load i32, ptr %41, align 4, !tbaa !18
  switch i32 %42, label %138 [
    i32 4096, label %43
    i32 112, label %44
    i32 8192, label %71
    i32 80, label %92
    i32 96, label %105
    i32 64, label %118
    i32 0, label %131
    i32 16, label %131
    i32 32, label %131
    i32 48, label %131
    i32 1048576, label %131
    i32 1048592, label %131
    i32 1048608, label %131
    i32 1048624, label %131
    i32 1048640, label %131
  ]

43:                                               ; preds = %19
  br label %139

44:                                               ; preds = %19
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %45, i32 0, i32 0
  %47 = load ptr, ptr %46, align 8, !tbaa !14
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %48, i32 0, i32 2
  %50 = load i32, ptr %49, align 4, !tbaa !20
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %51, i32 0, i32 1
  %53 = load i32, ptr %52, align 4, !tbaa !21
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %54, i32 0, i32 3
  %56 = load i32, ptr %55, align 4, !tbaa !22
  call void @TIM_ETR_SetConfig(ptr noundef %47, i32 noundef %50, i32 noundef %53, i32 noundef %56)
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !14
  %60 = getelementptr inbounds %struct.TIM_TypeDef, ptr %59, i32 0, i32 2
  %61 = load volatile i32, ptr %60, align 4, !tbaa !15
  store i32 %61, ptr %6, align 4, !tbaa !17
  %62 = load i32, ptr %6, align 4, !tbaa !17
  %63 = zext i32 %62 to i64
  %64 = or i64 %63, 119
  %65 = trunc i64 %64 to i32
  store i32 %65, ptr %6, align 4, !tbaa !17
  %66 = load i32, ptr %6, align 4, !tbaa !17
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !14
  %70 = getelementptr inbounds %struct.TIM_TypeDef, ptr %69, i32 0, i32 2
  store volatile i32 %66, ptr %70, align 4, !tbaa !15
  br label %139

71:                                               ; preds = %19
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %72, i32 0, i32 0
  %74 = load ptr, ptr %73, align 8, !tbaa !14
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %75, i32 0, i32 2
  %77 = load i32, ptr %76, align 4, !tbaa !20
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %78, i32 0, i32 1
  %80 = load i32, ptr %79, align 4, !tbaa !21
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %81, i32 0, i32 3
  %83 = load i32, ptr %82, align 4, !tbaa !22
  call void @TIM_ETR_SetConfig(ptr noundef %74, i32 noundef %77, i32 noundef %80, i32 noundef %83)
  %84 = load ptr, ptr %4, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %84, i32 0, i32 0
  %86 = load ptr, ptr %85, align 8, !tbaa !14
  %87 = getelementptr inbounds %struct.TIM_TypeDef, ptr %86, i32 0, i32 2
  %88 = load volatile i32, ptr %87, align 4, !tbaa !15
  %89 = zext i32 %88 to i64
  %90 = or i64 %89, 16384
  %91 = trunc i64 %90 to i32
  store volatile i32 %91, ptr %87, align 4, !tbaa !15
  br label %139

92:                                               ; preds = %19
  %93 = load ptr, ptr %4, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %93, i32 0, i32 0
  %95 = load ptr, ptr %94, align 8, !tbaa !14
  %96 = load ptr, ptr %5, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %96, i32 0, i32 1
  %98 = load i32, ptr %97, align 4, !tbaa !21
  %99 = load ptr, ptr %5, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %99, i32 0, i32 3
  %101 = load i32, ptr %100, align 4, !tbaa !22
  call void @TIM_TI1_ConfigInputStage(ptr noundef %95, i32 noundef %98, i32 noundef %101)
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %102, i32 0, i32 0
  %104 = load ptr, ptr %103, align 8, !tbaa !14
  call void @TIM_ITRx_SetConfig(ptr noundef %104, i32 noundef 80)
  br label %139

105:                                              ; preds = %19
  %106 = load ptr, ptr %4, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %106, i32 0, i32 0
  %108 = load ptr, ptr %107, align 8, !tbaa !14
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %109, i32 0, i32 1
  %111 = load i32, ptr %110, align 4, !tbaa !21
  %112 = load ptr, ptr %5, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %112, i32 0, i32 3
  %114 = load i32, ptr %113, align 4, !tbaa !22
  call void @TIM_TI2_ConfigInputStage(ptr noundef %108, i32 noundef %111, i32 noundef %114)
  %115 = load ptr, ptr %4, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %115, i32 0, i32 0
  %117 = load ptr, ptr %116, align 8, !tbaa !14
  call void @TIM_ITRx_SetConfig(ptr noundef %117, i32 noundef 96)
  br label %139

118:                                              ; preds = %19
  %119 = load ptr, ptr %4, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %119, i32 0, i32 0
  %121 = load ptr, ptr %120, align 8, !tbaa !14
  %122 = load ptr, ptr %5, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %122, i32 0, i32 1
  %124 = load i32, ptr %123, align 4, !tbaa !21
  %125 = load ptr, ptr %5, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %125, i32 0, i32 3
  %127 = load i32, ptr %126, align 4, !tbaa !22
  call void @TIM_TI1_ConfigInputStage(ptr noundef %121, i32 noundef %124, i32 noundef %127)
  %128 = load ptr, ptr %4, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %128, i32 0, i32 0
  %130 = load ptr, ptr %129, align 8, !tbaa !14
  call void @TIM_ITRx_SetConfig(ptr noundef %130, i32 noundef 64)
  br label %139

131:                                              ; preds = %19, %19, %19, %19, %19, %19, %19, %19, %19
  %132 = load ptr, ptr %4, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %132, i32 0, i32 0
  %134 = load ptr, ptr %133, align 8, !tbaa !14
  %135 = load ptr, ptr %5, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.TIM_ClockConfigTypeDef, ptr %135, i32 0, i32 0
  %137 = load i32, ptr %136, align 4, !tbaa !18
  call void @TIM_ITRx_SetConfig(ptr noundef %134, i32 noundef %137)
  br label %139

138:                                              ; preds = %19
  br label %139

139:                                              ; preds = %138, %131, %118, %105, %92, %71, %44, %43
  %140 = load ptr, ptr %4, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %140, i32 0, i32 5
  store volatile i32 1, ptr %141, align 4, !tbaa !13
  br label %142

142:                                              ; preds = %139
  %143 = load ptr, ptr %4, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %143, i32 0, i32 4
  store i32 0, ptr %144, align 8, !tbaa !9
  br label %145

145:                                              ; preds = %142
  br label %146

146:                                              ; preds = %145
  store i32 0, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %147

147:                                              ; preds = %146, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %148 = load i32, ptr %3, align 4
  ret i32 %148
}

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI1_ConfigInputStage(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_ITRx_SetConfig(ptr noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_ConfigInputStage(ptr noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 96}
!10 = !{!"", !6, i64 0, !11, i64 8, !12, i64 32, !7, i64 40, !12, i64 96, !12, i64 100}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 100}
!14 = !{!10, !6, i64 0}
!15 = !{!16, !12, i64 8}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !12, i64 100, !12, i64 104}
!17 = !{!12, !12, i64 0}
!18 = !{!19, !12, i64 0}
!19 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12}
!20 = !{!19, !12, i64 8}
!21 = !{!19, !12, i64 4}
!22 = !{!19, !12, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_ETR_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_ConfigClockSource(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 96
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i32 %4, 1
  br i1 %5, label %55, label %6

6:                                                ; preds = %2
  store i32 1, ptr %3, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 100
  store volatile i32 2, ptr %7, align 4, !tbaa !12
  %8 = load ptr, ptr %0, align 8, !tbaa !13
  %9 = getelementptr inbounds i8, ptr %8, i64 8
  %10 = load volatile i32, ptr %9, align 4, !tbaa !14
  %11 = and i32 %10, -3276664
  store volatile i32 %11, ptr %9, align 4, !tbaa !14
  %12 = load i32, ptr %1, align 4, !tbaa !16
  switch i32 %12, label %54 [
    i32 1048640, label %53
    i32 112, label %13
    i32 8192, label %24
    i32 80, label %35
    i32 96, label %41
    i32 64, label %47
    i32 0, label %53
    i32 16, label %53
    i32 32, label %53
    i32 48, label %53
    i32 1048576, label %53
    i32 1048592, label %53
    i32 1048608, label %53
    i32 1048624, label %53
  ]

13:                                               ; preds = %6
  %14 = getelementptr inbounds i8, ptr %1, i64 8
  %15 = load i32, ptr %14, align 4, !tbaa !18
  %16 = getelementptr inbounds i8, ptr %1, i64 4
  %17 = load i32, ptr %16, align 4, !tbaa !19
  %18 = getelementptr inbounds i8, ptr %1, i64 12
  %19 = load i32, ptr %18, align 4, !tbaa !20
  tail call void @TIM_ETR_SetConfig(ptr noundef nonnull %8, i32 noundef %15, i32 noundef %17, i32 noundef %19)
  %20 = load ptr, ptr %0, align 8, !tbaa !13
  %21 = getelementptr inbounds i8, ptr %20, i64 8
  %22 = load volatile i32, ptr %21, align 4, !tbaa !14
  %23 = or i32 %22, 119
  store volatile i32 %23, ptr %21, align 4, !tbaa !14
  br label %54

24:                                               ; preds = %6
  %25 = getelementptr inbounds i8, ptr %1, i64 8
  %26 = load i32, ptr %25, align 4, !tbaa !18
  %27 = getelementptr inbounds i8, ptr %1, i64 4
  %28 = load i32, ptr %27, align 4, !tbaa !19
  %29 = getelementptr inbounds i8, ptr %1, i64 12
  %30 = load i32, ptr %29, align 4, !tbaa !20
  tail call void @TIM_ETR_SetConfig(ptr noundef nonnull %8, i32 noundef %26, i32 noundef %28, i32 noundef %30)
  %31 = load ptr, ptr %0, align 8, !tbaa !13
  %32 = getelementptr inbounds i8, ptr %31, i64 8
  %33 = load volatile i32, ptr %32, align 4, !tbaa !14
  %34 = or i32 %33, 16384
  store volatile i32 %34, ptr %32, align 4, !tbaa !14
  br label %54

35:                                               ; preds = %6
  %36 = getelementptr inbounds i8, ptr %1, i64 4
  %37 = load i32, ptr %36, align 4, !tbaa !19
  %38 = getelementptr inbounds i8, ptr %1, i64 12
  %39 = load i32, ptr %38, align 4, !tbaa !20
  tail call void @TIM_TI1_ConfigInputStage(ptr noundef nonnull %8, i32 noundef %37, i32 noundef %39)
  %40 = load ptr, ptr %0, align 8, !tbaa !13
  tail call void @TIM_ITRx_SetConfig(ptr noundef %40, i32 noundef 80)
  br label %54

41:                                               ; preds = %6
  %42 = getelementptr inbounds i8, ptr %1, i64 4
  %43 = load i32, ptr %42, align 4, !tbaa !19
  %44 = getelementptr inbounds i8, ptr %1, i64 12
  %45 = load i32, ptr %44, align 4, !tbaa !20
  tail call void @TIM_TI2_ConfigInputStage(ptr noundef nonnull %8, i32 noundef %43, i32 noundef %45)
  %46 = load ptr, ptr %0, align 8, !tbaa !13
  tail call void @TIM_ITRx_SetConfig(ptr noundef %46, i32 noundef 96)
  br label %54

47:                                               ; preds = %6
  %48 = getelementptr inbounds i8, ptr %1, i64 4
  %49 = load i32, ptr %48, align 4, !tbaa !19
  %50 = getelementptr inbounds i8, ptr %1, i64 12
  %51 = load i32, ptr %50, align 4, !tbaa !20
  tail call void @TIM_TI1_ConfigInputStage(ptr noundef nonnull %8, i32 noundef %49, i32 noundef %51)
  %52 = load ptr, ptr %0, align 8, !tbaa !13
  tail call void @TIM_ITRx_SetConfig(ptr noundef %52, i32 noundef 64)
  br label %54

53:                                               ; preds = %6, %6, %6, %6, %6, %6, %6, %6, %6
  tail call void @TIM_ITRx_SetConfig(ptr noundef nonnull %8, i32 noundef %12)
  br label %54

54:                                               ; preds = %6, %53, %47, %41, %35, %24, %13
  store volatile i32 1, ptr %7, align 4, !tbaa !12
  store i32 0, ptr %3, align 8, !tbaa !5
  br label %55

55:                                               ; preds = %2, %54
  %.0 = phi i32 [ 0, %54 ], [ 2, %2 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI1_ConfigInputStage(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_ITRx_SetConfig(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_ConfigInputStage(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 100}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 8}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!16 = !{!17, !11, i64 0}
!17 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!18 = !{!17, !11, i64 8}
!19 = !{!17, !11, i64 4}
!20 = !{!17, !11, i64 12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass