; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/src/per (spiMultislave)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.daisy::MultiSlaveSpiHandle" = type { %"struct.daisy::MultiSlaveSpiHandle::Config", %"class.daisy::SpiHandle", [4 x %struct.dsy_gpio], %"struct.daisy::MultiSlaveSpiHandle::DmaTransfer" }
%"struct.daisy::MultiSlaveSpiHandle::Config" = type { %struct.anon, i32, i32, i64, i32, i32, i32, i64 }
%struct.anon = type { %struct.dsy_gpio_pin, %struct.dsy_gpio_pin, %struct.dsy_gpio_pin, [4 x %struct.dsy_gpio_pin] }
%struct.dsy_gpio_pin = type { i32, i8 }
%"class.daisy::SpiHandle" = type { ptr }
%struct.dsy_gpio = type { %struct.dsy_gpio_pin, i32, i32 }
%"struct.daisy::MultiSlaveSpiHandle::DmaTransfer" = type { i8, ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5daisy19MultiSlaveSpiHandle11DmaTransfer7IsValidEv(ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5daisy19MultiSlaveSpiHandle16DmaStartCallbackEPv(ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5daisy19MultiSlaveSpiHandle14DmaEndCallbackEPvNS_9SpiHandle6ResultE(ptr noundef, i32 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN5daisy19MultiSlaveSpiHandle21DmaTransmitAndReceiveEmPhS1_mPFvPvEPFvS2_NS_9SpiHandle6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(200) %0, i64 noundef %1, ptr noundef %2, ptr noundef %3, i64 noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7) #1 align 2 {
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i64, align 8
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca ptr, align 8
  store ptr %0, ptr %10, align 8, !tbaa !5
  store i64 %1, ptr %11, align 8, !tbaa !9
  store ptr %2, ptr %12, align 8, !tbaa !5
  store ptr %3, ptr %13, align 8, !tbaa !5
  store i64 %4, ptr %14, align 8, !tbaa !9
  store ptr %5, ptr %15, align 8, !tbaa !5
  store ptr %6, ptr %16, align 8, !tbaa !5
  store ptr %7, ptr %17, align 8, !tbaa !5
  %18 = load ptr, ptr %10, align 8
  %19 = load i64, ptr %11, align 8, !tbaa !9
  %20 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 0
  %21 = getelementptr inbounds %"struct.daisy::MultiSlaveSpiHandle::Config", ptr %20, i32 0, i32 7
  %22 = load i64, ptr %21, align 8, !tbaa !11
  %23 = icmp uge i64 %19, %22
  br i1 %23, label %24, label %25

24:                                               ; preds = %8
  store i32 1, ptr %9, align 4
  br label %49

25:                                               ; preds = %8
  br label %26

26:                                               ; preds = %29, %25
  %27 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 3
  %28 = call noundef zeroext i1 @_ZNK5daisy19MultiSlaveSpiHandle11DmaTransfer7IsValidEv(ptr noundef nonnull align 8 dereferenceable(32) %27)
  br i1 %28, label %29, label %30

29:                                               ; preds = %26
  br label %26, !llvm.loop !24

30:                                               ; preds = %26
  %31 = load i64, ptr %11, align 8, !tbaa !9
  %32 = trunc i64 %31 to i8
  %33 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 3
  %34 = getelementptr inbounds %"struct.daisy::MultiSlaveSpiHandle::DmaTransfer", ptr %33, i32 0, i32 0
  store i8 %32, ptr %34, align 8, !tbaa !26
  %35 = load ptr, ptr %15, align 8, !tbaa !5
  %36 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 3
  %37 = getelementptr inbounds %"struct.daisy::MultiSlaveSpiHandle::DmaTransfer", ptr %36, i32 0, i32 1
  store ptr %35, ptr %37, align 8, !tbaa !27
  %38 = load ptr, ptr %16, align 8, !tbaa !5
  %39 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 3
  %40 = getelementptr inbounds %"struct.daisy::MultiSlaveSpiHandle::DmaTransfer", ptr %39, i32 0, i32 2
  store ptr %38, ptr %40, align 8, !tbaa !28
  %41 = load ptr, ptr %17, align 8, !tbaa !5
  %42 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 3
  %43 = getelementptr inbounds %"struct.daisy::MultiSlaveSpiHandle::DmaTransfer", ptr %42, i32 0, i32 3
  store ptr %41, ptr %43, align 8, !tbaa !29
  %44 = getelementptr inbounds %"class.daisy::MultiSlaveSpiHandle", ptr %18, i32 0, i32 1
  %45 = load ptr, ptr %12, align 8, !tbaa !5
  %46 = load ptr, ptr %13, align 8, !tbaa !5
  %47 = load i64, ptr %14, align 8, !tbaa !9
  %48 = call noundef i32 @_ZN5daisy9SpiHandle21DmaTransmitAndReceiveEPhS1_mPFvPvEPFvS2_NS0_6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(8) %44, ptr noundef %45, ptr noundef %46, i64 noundef %47, ptr noundef @_ZN5daisy19MultiSlaveSpiHandle16DmaStartCallbackEPv, ptr noundef @_ZN5daisy19MultiSlaveSpiHandle14DmaEndCallbackEPvNS_9SpiHandle6ResultE, ptr noundef %18)
  store i32 %48, ptr %9, align 4
  br label %49

49:                                               ; preds = %30, %24
  %50 = load i32, ptr %9, align 4
  ret i32 %50
}

declare noundef i32 @_ZN5daisy9SpiHandle21DmaTransmitAndReceiveEPhS1_mPFvPvEPFvS2_NS0_6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef, ptr noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 88}
!12 = !{!"_ZTSN5daisy19MultiSlaveSpiHandleE", !13, i64 0, !22, i64 96, !7, i64 104, !23, i64 168}
!13 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle6ConfigE", !14, i64 0, !17, i64 56, !18, i64 60, !10, i64 64, !19, i64 72, !20, i64 76, !21, i64 80, !10, i64 88}
!14 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle6ConfigUt_E", !15, i64 0, !15, i64 8, !15, i64 16, !7, i64 24}
!15 = !{!"_ZTS12dsy_gpio_pin", !16, i64 0, !7, i64 4}
!16 = !{!"_ZTS13dsy_gpio_port", !7, i64 0}
!17 = !{!"_ZTSN5daisy9SpiHandle6Config10PeripheralE", !7, i64 0}
!18 = !{!"_ZTSN5daisy9SpiHandle6Config9DirectionE", !7, i64 0}
!19 = !{!"_ZTSN5daisy9SpiHandle6Config13ClockPolarityE", !7, i64 0}
!20 = !{!"_ZTSN5daisy9SpiHandle6Config10ClockPhaseE", !7, i64 0}
!21 = !{!"_ZTSN5daisy9SpiHandle6Config13BaudPrescalerE", !7, i64 0}
!22 = !{!"_ZTSN5daisy9SpiHandleE", !6, i64 0}
!23 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle11DmaTransferE", !7, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!12, !7, i64 168}
!27 = !{!12, !6, i64 176}
!28 = !{!12, !6, i64 184}
!29 = !{!12, !6, i64 192}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK5daisy19MultiSlaveSpiHandle11DmaTransfer7IsValidEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5daisy19MultiSlaveSpiHandle16DmaStartCallbackEPv(ptr noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN5daisy19MultiSlaveSpiHandle14DmaEndCallbackEPvNS_9SpiHandle6ResultE(ptr noundef, i32 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN5daisy19MultiSlaveSpiHandle21DmaTransmitAndReceiveEmPhS1_mPFvPvEPFvS2_NS_9SpiHandle6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(200) %0, i64 noundef %1, ptr noundef %2, ptr noundef %3, i64 noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7) local_unnamed_addr #1 align 2 {
  %9 = getelementptr inbounds i8, ptr %0, i64 88
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %.not = icmp ugt i64 %10, %1
  br i1 %.not, label %.preheader, label %21

.preheader:                                       ; preds = %8
  %11 = getelementptr inbounds i8, ptr %0, i64 168
  br label %12

12:                                               ; preds = %.preheader, %12
  %13 = tail call noundef zeroext i1 @_ZNK5daisy19MultiSlaveSpiHandle11DmaTransfer7IsValidEv(ptr noundef nonnull align 8 dereferenceable(32) %11)
  br i1 %13, label %12, label %14, !llvm.loop !22

14:                                               ; preds = %12
  %15 = trunc i64 %1 to i8
  store i8 %15, ptr %11, align 8, !tbaa !24
  %16 = getelementptr inbounds i8, ptr %0, i64 176
  store ptr %5, ptr %16, align 8, !tbaa !25
  %17 = getelementptr inbounds i8, ptr %0, i64 184
  store ptr %6, ptr %17, align 8, !tbaa !26
  %18 = getelementptr inbounds i8, ptr %0, i64 192
  store ptr %7, ptr %18, align 8, !tbaa !27
  %19 = getelementptr inbounds i8, ptr %0, i64 96
  %20 = tail call noundef i32 @_ZN5daisy9SpiHandle21DmaTransmitAndReceiveEPhS1_mPFvPvEPFvS2_NS0_6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(8) %19, ptr noundef %2, ptr noundef %3, i64 noundef %4, ptr noundef nonnull @_ZN5daisy19MultiSlaveSpiHandle16DmaStartCallbackEPv, ptr noundef nonnull @_ZN5daisy19MultiSlaveSpiHandle14DmaEndCallbackEPvNS_9SpiHandle6ResultE, ptr noundef nonnull %0)
  br label %21

21:                                               ; preds = %8, %14
  %.0 = phi i32 [ %20, %14 ], [ 1, %8 ]
  ret i32 %.0
}

declare noundef i32 @_ZN5daisy9SpiHandle21DmaTransmitAndReceiveEPhS1_mPFvPvEPFvS2_NS0_6ResultEES2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef, ptr noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 88}
!6 = !{!"_ZTSN5daisy19MultiSlaveSpiHandleE", !7, i64 0, !19, i64 96, !11, i64 104, !21, i64 168}
!7 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle6ConfigE", !8, i64 0, !13, i64 56, !14, i64 60, !15, i64 64, !16, i64 72, !17, i64 76, !18, i64 80, !15, i64 88}
!8 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle6ConfigUt_E", !9, i64 0, !9, i64 8, !9, i64 16, !11, i64 24}
!9 = !{!"_ZTS12dsy_gpio_pin", !10, i64 0, !11, i64 4}
!10 = !{!"_ZTS13dsy_gpio_port", !11, i64 0}
!11 = !{!"omnipotent char", !12, i64 0}
!12 = !{!"Simple C++ TBAA"}
!13 = !{!"_ZTSN5daisy9SpiHandle6Config10PeripheralE", !11, i64 0}
!14 = !{!"_ZTSN5daisy9SpiHandle6Config9DirectionE", !11, i64 0}
!15 = !{!"long", !11, i64 0}
!16 = !{!"_ZTSN5daisy9SpiHandle6Config13ClockPolarityE", !11, i64 0}
!17 = !{!"_ZTSN5daisy9SpiHandle6Config10ClockPhaseE", !11, i64 0}
!18 = !{!"_ZTSN5daisy9SpiHandle6Config13BaudPrescalerE", !11, i64 0}
!19 = !{!"_ZTSN5daisy9SpiHandleE", !20, i64 0}
!20 = !{!"any pointer", !11, i64 0}
!21 = !{!"_ZTSN5daisy19MultiSlaveSpiHandle11DmaTransferE", !11, i64 0, !20, i64 8, !20, i64 16, !20, i64 24}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = !{!6, !11, i64 168}
!25 = !{!6, !20, i64 176}
!26 = !{!6, !20, i64 184}
!27 = !{!6, !20, i64 192}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,LCSSAPass,LICMPass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass