; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConfigChannel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_OnePulse_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_OnePulse_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %struct.TIM_OC_InitTypeDef, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 28, ptr %10) #2
  %12 = load i32, ptr %8, align 4, !tbaa !9
  %13 = load i32, ptr %9, align 4, !tbaa !9
  %14 = icmp ne i32 %12, %13
  br i1 %14, label %15, label %181

15:                                               ; preds = %4
  br label %16

16:                                               ; preds = %15
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %17, i32 0, i32 4
  %19 = load i32, ptr %18, align 8, !tbaa !11
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  store i32 2, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %182

22:                                               ; preds = %16
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %23, i32 0, i32 4
  store i32 1, ptr %24, align 8, !tbaa !11
  br label %25

25:                                               ; preds = %22
  br label %26

26:                                               ; preds = %25
  br label %27

27:                                               ; preds = %26
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %28, i32 0, i32 5
  store volatile i32 2, ptr %29, align 4, !tbaa !14
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %30, i32 0, i32 0
  %32 = load i32, ptr %31, align 4, !tbaa !15
  %33 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 0
  store i32 %32, ptr %33, align 4, !tbaa !17
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %34, i32 0, i32 1
  %36 = load i32, ptr %35, align 4, !tbaa !19
  %37 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 1
  store i32 %36, ptr %37, align 4, !tbaa !20
  %38 = load ptr, ptr %7, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %38, i32 0, i32 2
  %40 = load i32, ptr %39, align 4, !tbaa !21
  %41 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 2
  store i32 %40, ptr %41, align 4, !tbaa !22
  %42 = load ptr, ptr %7, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %42, i32 0, i32 3
  %44 = load i32, ptr %43, align 4, !tbaa !23
  %45 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 3
  store i32 %44, ptr %45, align 4, !tbaa !24
  %46 = load ptr, ptr %7, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %46, i32 0, i32 4
  %48 = load i32, ptr %47, align 4, !tbaa !25
  %49 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 5
  store i32 %48, ptr %49, align 4, !tbaa !26
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %50, i32 0, i32 5
  %52 = load i32, ptr %51, align 4, !tbaa !27
  %53 = getelementptr inbounds %struct.TIM_OC_InitTypeDef, ptr %10, i32 0, i32 6
  store i32 %52, ptr %53, align 4, !tbaa !28
  %54 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %54, label %63 [
    i32 0, label %55
    i32 4, label %59
  ]

55:                                               ; preds = %27
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %56, i32 0, i32 0
  %58 = load ptr, ptr %57, align 8, !tbaa !29
  call void @TIM_OC1_SetConfig(ptr noundef %58, ptr noundef %10)
  br label %64

59:                                               ; preds = %27
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %60, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8, !tbaa !29
  call void @TIM_OC2_SetConfig(ptr noundef %62, ptr noundef %10)
  br label %64

63:                                               ; preds = %27
  br label %64

64:                                               ; preds = %63, %59, %55
  %65 = load i32, ptr %9, align 4, !tbaa !9
  switch i32 %65, label %172 [
    i32 0, label %66
    i32 4, label %119
  ]

66:                                               ; preds = %64
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %67, i32 0, i32 0
  %69 = load ptr, ptr %68, align 8, !tbaa !29
  %70 = load ptr, ptr %7, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %70, i32 0, i32 6
  %72 = load i32, ptr %71, align 4, !tbaa !30
  %73 = load ptr, ptr %7, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %73, i32 0, i32 7
  %75 = load i32, ptr %74, align 4, !tbaa !31
  %76 = load ptr, ptr %7, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %76, i32 0, i32 8
  %78 = load i32, ptr %77, align 4, !tbaa !32
  call void @TIM_TI1_SetConfig(ptr noundef %69, i32 noundef %72, i32 noundef %75, i32 noundef %78)
  %79 = load ptr, ptr %6, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %79, i32 0, i32 0
  %81 = load ptr, ptr %80, align 8, !tbaa !29
  %82 = getelementptr inbounds %struct.TIM_TypeDef, ptr %81, i32 0, i32 6
  %83 = load volatile i32, ptr %82, align 4, !tbaa !33
  %84 = zext i32 %83 to i64
  %85 = and i64 %84, -13
  %86 = trunc i64 %85 to i32
  store volatile i32 %86, ptr %82, align 4, !tbaa !33
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %87, i32 0, i32 0
  %89 = load ptr, ptr %88, align 8, !tbaa !29
  %90 = getelementptr inbounds %struct.TIM_TypeDef, ptr %89, i32 0, i32 2
  %91 = load volatile i32, ptr %90, align 4, !tbaa !35
  %92 = zext i32 %91 to i64
  %93 = and i64 %92, -3145841
  %94 = trunc i64 %93 to i32
  store volatile i32 %94, ptr %90, align 4, !tbaa !35
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %95, i32 0, i32 0
  %97 = load ptr, ptr %96, align 8, !tbaa !29
  %98 = getelementptr inbounds %struct.TIM_TypeDef, ptr %97, i32 0, i32 2
  %99 = load volatile i32, ptr %98, align 4, !tbaa !35
  %100 = zext i32 %99 to i64
  %101 = or i64 %100, 80
  %102 = trunc i64 %101 to i32
  store volatile i32 %102, ptr %98, align 4, !tbaa !35
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %103, i32 0, i32 0
  %105 = load ptr, ptr %104, align 8, !tbaa !29
  %106 = getelementptr inbounds %struct.TIM_TypeDef, ptr %105, i32 0, i32 2
  %107 = load volatile i32, ptr %106, align 4, !tbaa !35
  %108 = zext i32 %107 to i64
  %109 = and i64 %108, -65544
  %110 = trunc i64 %109 to i32
  store volatile i32 %110, ptr %106, align 4, !tbaa !35
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %111, i32 0, i32 0
  %113 = load ptr, ptr %112, align 8, !tbaa !29
  %114 = getelementptr inbounds %struct.TIM_TypeDef, ptr %113, i32 0, i32 2
  %115 = load volatile i32, ptr %114, align 4, !tbaa !35
  %116 = zext i32 %115 to i64
  %117 = or i64 %116, 6
  %118 = trunc i64 %117 to i32
  store volatile i32 %118, ptr %114, align 4, !tbaa !35
  br label %173

119:                                              ; preds = %64
  %120 = load ptr, ptr %6, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %120, i32 0, i32 0
  %122 = load ptr, ptr %121, align 8, !tbaa !29
  %123 = load ptr, ptr %7, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %123, i32 0, i32 6
  %125 = load i32, ptr %124, align 4, !tbaa !30
  %126 = load ptr, ptr %7, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %126, i32 0, i32 7
  %128 = load i32, ptr %127, align 4, !tbaa !31
  %129 = load ptr, ptr %7, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.TIM_OnePulse_InitTypeDef, ptr %129, i32 0, i32 8
  %131 = load i32, ptr %130, align 4, !tbaa !32
  call void @TIM_TI2_SetConfig(ptr noundef %122, i32 noundef %125, i32 noundef %128, i32 noundef %131)
  %132 = load ptr, ptr %6, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %132, i32 0, i32 0
  %134 = load ptr, ptr %133, align 8, !tbaa !29
  %135 = getelementptr inbounds %struct.TIM_TypeDef, ptr %134, i32 0, i32 6
  %136 = load volatile i32, ptr %135, align 4, !tbaa !33
  %137 = zext i32 %136 to i64
  %138 = and i64 %137, -3073
  %139 = trunc i64 %138 to i32
  store volatile i32 %139, ptr %135, align 4, !tbaa !33
  %140 = load ptr, ptr %6, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %140, i32 0, i32 0
  %142 = load ptr, ptr %141, align 8, !tbaa !29
  %143 = getelementptr inbounds %struct.TIM_TypeDef, ptr %142, i32 0, i32 2
  %144 = load volatile i32, ptr %143, align 4, !tbaa !35
  %145 = zext i32 %144 to i64
  %146 = and i64 %145, -3145841
  %147 = trunc i64 %146 to i32
  store volatile i32 %147, ptr %143, align 4, !tbaa !35
  %148 = load ptr, ptr %6, align 8, !tbaa !5
  %149 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %148, i32 0, i32 0
  %150 = load ptr, ptr %149, align 8, !tbaa !29
  %151 = getelementptr inbounds %struct.TIM_TypeDef, ptr %150, i32 0, i32 2
  %152 = load volatile i32, ptr %151, align 4, !tbaa !35
  %153 = zext i32 %152 to i64
  %154 = or i64 %153, 96
  %155 = trunc i64 %154 to i32
  store volatile i32 %155, ptr %151, align 4, !tbaa !35
  %156 = load ptr, ptr %6, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %156, i32 0, i32 0
  %158 = load ptr, ptr %157, align 8, !tbaa !29
  %159 = getelementptr inbounds %struct.TIM_TypeDef, ptr %158, i32 0, i32 2
  %160 = load volatile i32, ptr %159, align 4, !tbaa !35
  %161 = zext i32 %160 to i64
  %162 = and i64 %161, -65544
  %163 = trunc i64 %162 to i32
  store volatile i32 %163, ptr %159, align 4, !tbaa !35
  %164 = load ptr, ptr %6, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %164, i32 0, i32 0
  %166 = load ptr, ptr %165, align 8, !tbaa !29
  %167 = getelementptr inbounds %struct.TIM_TypeDef, ptr %166, i32 0, i32 2
  %168 = load volatile i32, ptr %167, align 4, !tbaa !35
  %169 = zext i32 %168 to i64
  %170 = or i64 %169, 6
  %171 = trunc i64 %170 to i32
  store volatile i32 %171, ptr %167, align 4, !tbaa !35
  br label %173

172:                                              ; preds = %64
  br label %173

173:                                              ; preds = %172, %119, %66
  %174 = load ptr, ptr %6, align 8, !tbaa !5
  %175 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %174, i32 0, i32 5
  store volatile i32 1, ptr %175, align 4, !tbaa !14
  br label %176

176:                                              ; preds = %173
  %177 = load ptr, ptr %6, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %177, i32 0, i32 4
  store i32 0, ptr %178, align 8, !tbaa !11
  br label %179

179:                                              ; preds = %176
  br label %180

180:                                              ; preds = %179
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %182

181:                                              ; preds = %4
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %182

182:                                              ; preds = %181, %180, %21
  call void @llvm.lifetime.end.p0(i64 28, ptr %10) #2
  %183 = load i32, ptr %5, align 4
  ret i32 %183
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !10, i64 100}
!15 = !{!16, !10, i64 0}
!16 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32}
!17 = !{!18, !10, i64 0}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!19 = !{!16, !10, i64 4}
!20 = !{!18, !10, i64 4}
!21 = !{!16, !10, i64 8}
!22 = !{!18, !10, i64 8}
!23 = !{!16, !10, i64 12}
!24 = !{!18, !10, i64 12}
!25 = !{!16, !10, i64 16}
!26 = !{!18, !10, i64 20}
!27 = !{!16, !10, i64 20}
!28 = !{!18, !10, i64 24}
!29 = !{!12, !6, i64 0}
!30 = !{!16, !10, i64 24}
!31 = !{!16, !10, i64 28}
!32 = !{!16, !10, i64 32}
!33 = !{!34, !10, i64 24}
!34 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!35 = !{!34, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_OC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_OC1_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_OC2_SetConfig(ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_OnePulse_ConfigChannel(ptr noundef %0, ptr nocapture noundef readonly %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %5 = alloca %struct.TIM_OC_InitTypeDef, align 16
  call void @llvm.lifetime.start.p0(i64 28, ptr nonnull %5) #2
  %.not = icmp eq i32 %2, %3
  br i1 %.not, label %51, label %6

6:                                                ; preds = %4
  %7 = getelementptr inbounds i8, ptr %0, i64 96
  %8 = load i32, ptr %7, align 8, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %51, label %10

10:                                               ; preds = %6
  store i32 1, ptr %7, align 8, !tbaa !5
  %11 = getelementptr inbounds i8, ptr %0, i64 100
  store volatile i32 2, ptr %11, align 4, !tbaa !12
  %12 = load <4 x i32>, ptr %1, align 4, !tbaa !13
  store <4 x i32> %12, ptr %5, align 16, !tbaa !13
  %13 = getelementptr inbounds i8, ptr %1, i64 16
  %14 = getelementptr inbounds i8, ptr %5, i64 20
  %15 = load <2 x i32>, ptr %13, align 4, !tbaa !13
  store <2 x i32> %15, ptr %14, align 4, !tbaa !13
  switch i32 %2, label %20 [
    i32 0, label %16
    i32 4, label %18
  ]

16:                                               ; preds = %10
  %17 = load ptr, ptr %0, align 8, !tbaa !14
  call void @TIM_OC1_SetConfig(ptr noundef %17, ptr noundef nonnull %5)
  br label %20

18:                                               ; preds = %10
  %19 = load ptr, ptr %0, align 8, !tbaa !14
  call void @TIM_OC2_SetConfig(ptr noundef %19, ptr noundef nonnull %5)
  br label %20

20:                                               ; preds = %10, %18, %16
  switch i32 %3, label %50 [
    i32 0, label %21
    i32 4, label %29
  ]

21:                                               ; preds = %20
  %22 = load ptr, ptr %0, align 8, !tbaa !14
  %23 = getelementptr inbounds i8, ptr %1, i64 24
  %24 = load i32, ptr %23, align 4, !tbaa !15
  %25 = getelementptr inbounds i8, ptr %1, i64 28
  %26 = load i32, ptr %25, align 4, !tbaa !17
  %27 = getelementptr inbounds i8, ptr %1, i64 32
  %28 = load i32, ptr %27, align 4, !tbaa !18
  call void @TIM_TI1_SetConfig(ptr noundef %22, i32 noundef %24, i32 noundef %26, i32 noundef %28)
  br label %.sink.split

29:                                               ; preds = %20
  %30 = load ptr, ptr %0, align 8, !tbaa !14
  %31 = getelementptr inbounds i8, ptr %1, i64 24
  %32 = load i32, ptr %31, align 4, !tbaa !15
  %33 = getelementptr inbounds i8, ptr %1, i64 28
  %34 = load i32, ptr %33, align 4, !tbaa !17
  %35 = getelementptr inbounds i8, ptr %1, i64 32
  %36 = load i32, ptr %35, align 4, !tbaa !18
  call void @TIM_TI2_SetConfig(ptr noundef %30, i32 noundef %32, i32 noundef %34, i32 noundef %36)
  br label %.sink.split

.sink.split:                                      ; preds = %21, %29
  %.sink55 = phi i32 [ -3073, %29 ], [ -13, %21 ]
  %.sink46 = phi i32 [ 96, %29 ], [ 80, %21 ]
  %37 = load ptr, ptr %0, align 8, !tbaa !14
  %38 = getelementptr inbounds i8, ptr %37, i64 24
  %39 = load volatile i32, ptr %38, align 4, !tbaa !19
  %40 = and i32 %39, %.sink55
  store volatile i32 %40, ptr %38, align 4, !tbaa !19
  %41 = getelementptr inbounds i8, ptr %37, i64 8
  %42 = load volatile i32, ptr %41, align 4, !tbaa !21
  %43 = and i32 %42, -3145841
  store volatile i32 %43, ptr %41, align 4, !tbaa !21
  %44 = load volatile i32, ptr %41, align 4, !tbaa !21
  %45 = or i32 %44, %.sink46
  store volatile i32 %45, ptr %41, align 4, !tbaa !21
  %46 = load volatile i32, ptr %41, align 4, !tbaa !21
  %47 = and i32 %46, -65544
  store volatile i32 %47, ptr %41, align 4, !tbaa !21
  %48 = load volatile i32, ptr %41, align 4, !tbaa !21
  %49 = or i32 %48, 6
  store volatile i32 %49, ptr %41, align 4, !tbaa !21
  br label %50

50:                                               ; preds = %.sink.split, %20
  store volatile i32 1, ptr %11, align 4, !tbaa !12
  store i32 0, ptr %7, align 8, !tbaa !5
  br label %51

51:                                               ; preds = %4, %6, %50
  %.0 = phi i32 [ 0, %50 ], [ 2, %6 ], [ 1, %4 ]
  call void @llvm.lifetime.end.p0(i64 28, ptr nonnull %5) #2
  ret i32 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 100}
!13 = !{!11, !11, i64 0}
!14 = !{!6, !7, i64 0}
!15 = !{!16, !11, i64 24}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32}
!17 = !{!16, !11, i64 28}
!18 = !{!16, !11, i64 32}
!19 = !{!20, !11, i64 24}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!21 = !{!20, !11, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass