; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Read_Page_16b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  %18 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %18, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %19, ptr %16, align 8, !tbaa !5
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %20, i32 0, i32 3
  %22 = load volatile i32, ptr %21, align 8, !tbaa !11
  %23 = icmp eq i32 %22, 2
  br i1 %23, label %24, label %25

24:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %286

25:                                               ; preds = %4
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %26, i32 0, i32 3
  %28 = load volatile i32, ptr %27, align 8, !tbaa !11
  %29 = icmp eq i32 %28, 1
  br i1 %29, label %30, label %283

30:                                               ; preds = %25
  br label %31

31:                                               ; preds = %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %32, i32 0, i32 2
  %34 = load i32, ptr %33, align 4, !tbaa !14
  %35 = icmp eq i32 %34, 1
  br i1 %35, label %36, label %37

36:                                               ; preds = %31
  store i32 2, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %286

37:                                               ; preds = %31
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %38, i32 0, i32 2
  store i32 1, ptr %39, align 4, !tbaa !14
  br label %40

40:                                               ; preds = %37
  br label %41

41:                                               ; preds = %40
  br label %42

42:                                               ; preds = %41
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %43, i32 0, i32 3
  store volatile i32 2, ptr %44, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %45, i32 0, i32 0
  %47 = load i16, ptr %46, align 2, !tbaa !15
  %48 = zext i16 %47 to i32
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %49, i32 0, i32 2
  %51 = load i16, ptr %50, align 2, !tbaa !18
  %52 = zext i16 %51 to i32
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %53, i32 0, i32 1
  %55 = load i16, ptr %54, align 2, !tbaa !19
  %56 = zext i16 %55 to i32
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %57, i32 0, i32 4
  %59 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %58, i32 0, i32 5
  %60 = load i32, ptr %59, align 4, !tbaa !20
  %61 = mul i32 %56, %60
  %62 = add i32 %52, %61
  %63 = load ptr, ptr %6, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %63, i32 0, i32 4
  %65 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %64, i32 0, i32 2
  %66 = load i32, ptr %65, align 4, !tbaa !21
  %67 = mul i32 %62, %66
  %68 = add i32 %48, %67
  store i32 %68, ptr %14, align 4, !tbaa !9
  br label %69

69:                                               ; preds = %268, %42
  %70 = load i32, ptr %15, align 4, !tbaa !9
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %84

72:                                               ; preds = %69
  %73 = load i32, ptr %14, align 4, !tbaa !9
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %74, i32 0, i32 4
  %76 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %75, i32 0, i32 2
  %77 = load i32, ptr %76, align 4, !tbaa !21
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %78, i32 0, i32 4
  %80 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %79, i32 0, i32 3
  %81 = load i32, ptr %80, align 4, !tbaa !22
  %82 = mul i32 %77, %81
  %83 = icmp ult i32 %73, %82
  br label %84

84:                                               ; preds = %72, %69
  %85 = phi i1 [ false, %69 ], [ %83, %72 ]
  br i1 %85, label %86, label %275

86:                                               ; preds = %84
  %87 = load i32, ptr %12, align 4, !tbaa !9
  %88 = or i32 %87, 65536
  %89 = zext i32 %88 to i64
  %90 = inttoptr i64 %89 to ptr
  store volatile i8 0, ptr %90, align 1, !tbaa !23
  call void @__DSB()
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %91, i32 0, i32 4
  %93 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %92, i32 0, i32 0
  %94 = load i32, ptr %93, align 4, !tbaa !24
  %95 = icmp ule i32 %94, 512
  br i1 %95, label %96, label %151

96:                                               ; preds = %86
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %97, i32 0, i32 4
  %99 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %98, i32 0, i32 2
  %100 = load i32, ptr %99, align 4, !tbaa !21
  %101 = load ptr, ptr %6, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %101, i32 0, i32 4
  %103 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %102, i32 0, i32 3
  %104 = load i32, ptr %103, align 4, !tbaa !22
  %105 = mul i32 %100, %104
  %106 = icmp ule i32 %105, 65535
  br i1 %106, label %107, label %125

107:                                              ; preds = %96
  %108 = load i32, ptr %12, align 4, !tbaa !9
  %109 = or i32 %108, 131072
  %110 = zext i32 %109 to i64
  %111 = inttoptr i64 %110 to ptr
  store volatile i8 0, ptr %111, align 1, !tbaa !23
  call void @__DSB()
  %112 = load i32, ptr %14, align 4, !tbaa !9
  %113 = trunc i32 %112 to i8
  %114 = load i32, ptr %12, align 4, !tbaa !9
  %115 = or i32 %114, 131072
  %116 = zext i32 %115 to i64
  %117 = inttoptr i64 %116 to ptr
  store volatile i8 %113, ptr %117, align 1, !tbaa !23
  call void @__DSB()
  %118 = load i32, ptr %14, align 4, !tbaa !9
  %119 = lshr i32 %118, 8
  %120 = trunc i32 %119 to i8
  %121 = load i32, ptr %12, align 4, !tbaa !9
  %122 = or i32 %121, 131072
  %123 = zext i32 %122 to i64
  %124 = inttoptr i64 %123 to ptr
  store volatile i8 %120, ptr %124, align 1, !tbaa !23
  call void @__DSB()
  br label %150

125:                                              ; preds = %96
  %126 = load i32, ptr %12, align 4, !tbaa !9
  %127 = or i32 %126, 131072
  %128 = zext i32 %127 to i64
  %129 = inttoptr i64 %128 to ptr
  store volatile i8 0, ptr %129, align 1, !tbaa !23
  call void @__DSB()
  %130 = load i32, ptr %14, align 4, !tbaa !9
  %131 = trunc i32 %130 to i8
  %132 = load i32, ptr %12, align 4, !tbaa !9
  %133 = or i32 %132, 131072
  %134 = zext i32 %133 to i64
  %135 = inttoptr i64 %134 to ptr
  store volatile i8 %131, ptr %135, align 1, !tbaa !23
  call void @__DSB()
  %136 = load i32, ptr %14, align 4, !tbaa !9
  %137 = lshr i32 %136, 8
  %138 = trunc i32 %137 to i8
  %139 = load i32, ptr %12, align 4, !tbaa !9
  %140 = or i32 %139, 131072
  %141 = zext i32 %140 to i64
  %142 = inttoptr i64 %141 to ptr
  store volatile i8 %138, ptr %142, align 1, !tbaa !23
  call void @__DSB()
  %143 = load i32, ptr %14, align 4, !tbaa !9
  %144 = lshr i32 %143, 16
  %145 = trunc i32 %144 to i8
  %146 = load i32, ptr %12, align 4, !tbaa !9
  %147 = or i32 %146, 131072
  %148 = zext i32 %147 to i64
  %149 = inttoptr i64 %148 to ptr
  store volatile i8 %145, ptr %149, align 1, !tbaa !23
  call void @__DSB()
  br label %150

150:                                              ; preds = %125, %107
  br label %214

151:                                              ; preds = %86
  %152 = load ptr, ptr %6, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %152, i32 0, i32 4
  %154 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %153, i32 0, i32 2
  %155 = load i32, ptr %154, align 4, !tbaa !21
  %156 = load ptr, ptr %6, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %156, i32 0, i32 4
  %158 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %157, i32 0, i32 3
  %159 = load i32, ptr %158, align 4, !tbaa !22
  %160 = mul i32 %155, %159
  %161 = icmp ule i32 %160, 65535
  br i1 %161, label %162, label %184

162:                                              ; preds = %151
  %163 = load i32, ptr %12, align 4, !tbaa !9
  %164 = or i32 %163, 131072
  %165 = zext i32 %164 to i64
  %166 = inttoptr i64 %165 to ptr
  store volatile i8 0, ptr %166, align 1, !tbaa !23
  call void @__DSB()
  %167 = load i32, ptr %12, align 4, !tbaa !9
  %168 = or i32 %167, 131072
  %169 = zext i32 %168 to i64
  %170 = inttoptr i64 %169 to ptr
  store volatile i8 0, ptr %170, align 1, !tbaa !23
  call void @__DSB()
  %171 = load i32, ptr %14, align 4, !tbaa !9
  %172 = trunc i32 %171 to i8
  %173 = load i32, ptr %12, align 4, !tbaa !9
  %174 = or i32 %173, 131072
  %175 = zext i32 %174 to i64
  %176 = inttoptr i64 %175 to ptr
  store volatile i8 %172, ptr %176, align 1, !tbaa !23
  call void @__DSB()
  %177 = load i32, ptr %14, align 4, !tbaa !9
  %178 = lshr i32 %177, 8
  %179 = trunc i32 %178 to i8
  %180 = load i32, ptr %12, align 4, !tbaa !9
  %181 = or i32 %180, 131072
  %182 = zext i32 %181 to i64
  %183 = inttoptr i64 %182 to ptr
  store volatile i8 %179, ptr %183, align 1, !tbaa !23
  call void @__DSB()
  br label %213

184:                                              ; preds = %151
  %185 = load i32, ptr %12, align 4, !tbaa !9
  %186 = or i32 %185, 131072
  %187 = zext i32 %186 to i64
  %188 = inttoptr i64 %187 to ptr
  store volatile i8 0, ptr %188, align 1, !tbaa !23
  call void @__DSB()
  %189 = load i32, ptr %12, align 4, !tbaa !9
  %190 = or i32 %189, 131072
  %191 = zext i32 %190 to i64
  %192 = inttoptr i64 %191 to ptr
  store volatile i8 0, ptr %192, align 1, !tbaa !23
  call void @__DSB()
  %193 = load i32, ptr %14, align 4, !tbaa !9
  %194 = trunc i32 %193 to i8
  %195 = load i32, ptr %12, align 4, !tbaa !9
  %196 = or i32 %195, 131072
  %197 = zext i32 %196 to i64
  %198 = inttoptr i64 %197 to ptr
  store volatile i8 %194, ptr %198, align 1, !tbaa !23
  call void @__DSB()
  %199 = load i32, ptr %14, align 4, !tbaa !9
  %200 = lshr i32 %199, 8
  %201 = trunc i32 %200 to i8
  %202 = load i32, ptr %12, align 4, !tbaa !9
  %203 = or i32 %202, 131072
  %204 = zext i32 %203 to i64
  %205 = inttoptr i64 %204 to ptr
  store volatile i8 %201, ptr %205, align 1, !tbaa !23
  call void @__DSB()
  %206 = load i32, ptr %14, align 4, !tbaa !9
  %207 = lshr i32 %206, 16
  %208 = trunc i32 %207 to i8
  %209 = load i32, ptr %12, align 4, !tbaa !9
  %210 = or i32 %209, 131072
  %211 = zext i32 %210 to i64
  %212 = inttoptr i64 %211 to ptr
  store volatile i8 %208, ptr %212, align 1, !tbaa !23
  call void @__DSB()
  br label %213

213:                                              ; preds = %184, %162
  br label %214

214:                                              ; preds = %213, %150
  %215 = load i32, ptr %12, align 4, !tbaa !9
  %216 = or i32 %215, 65536
  %217 = zext i32 %216 to i64
  %218 = inttoptr i64 %217 to ptr
  store volatile i8 48, ptr %218, align 1, !tbaa !23
  call void @__DSB()
  %219 = load ptr, ptr %6, align 8, !tbaa !5
  %220 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %219, i32 0, i32 4
  %221 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %220, i32 0, i32 6
  %222 = load i32, ptr %221, align 4, !tbaa !25
  %223 = icmp eq i32 %222, 1
  br i1 %223, label %224, label %249

224:                                              ; preds = %214
  %225 = call i32 @HAL_GetTick()
  store i32 %225, ptr %11, align 4, !tbaa !9
  br label %226

226:                                              ; preds = %243, %224
  %227 = load ptr, ptr %6, align 8, !tbaa !5
  %228 = call i32 @HAL_NAND_Read_Status(ptr noundef %227)
  %229 = icmp ne i32 %228, 64
  br i1 %229, label %230, label %244

230:                                              ; preds = %226
  %231 = call i32 @HAL_GetTick()
  %232 = load i32, ptr %11, align 4, !tbaa !9
  %233 = sub i32 %231, %232
  %234 = icmp ugt i32 %233, 16777216
  br i1 %234, label %235, label %243

235:                                              ; preds = %230
  %236 = load ptr, ptr %6, align 8, !tbaa !5
  %237 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %236, i32 0, i32 3
  store volatile i32 3, ptr %237, align 8, !tbaa !11
  br label %238

238:                                              ; preds = %235
  %239 = load ptr, ptr %6, align 8, !tbaa !5
  %240 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %239, i32 0, i32 2
  store i32 0, ptr %240, align 4, !tbaa !14
  br label %241

241:                                              ; preds = %238
  br label %242

242:                                              ; preds = %241
  store i32 3, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %286

243:                                              ; preds = %230
  br label %226, !llvm.loop !26

244:                                              ; preds = %226
  %245 = load i32, ptr %12, align 4, !tbaa !9
  %246 = or i32 %245, 65536
  %247 = zext i32 %246 to i64
  %248 = inttoptr i64 %247 to ptr
  store volatile i8 0, ptr %248, align 1, !tbaa !23
  call void @__DSB()
  br label %249

249:                                              ; preds = %244, %214
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %250

250:                                              ; preds = %265, %249
  %251 = load i32, ptr %10, align 4, !tbaa !9
  %252 = load ptr, ptr %6, align 8, !tbaa !5
  %253 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %252, i32 0, i32 4
  %254 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %253, i32 0, i32 0
  %255 = load i32, ptr %254, align 4, !tbaa !24
  %256 = icmp ult i32 %251, %255
  br i1 %256, label %257, label %268

257:                                              ; preds = %250
  %258 = load i32, ptr %12, align 4, !tbaa !9
  %259 = zext i32 %258 to i64
  %260 = inttoptr i64 %259 to ptr
  %261 = load i16, ptr %260, align 2, !tbaa !28
  %262 = load ptr, ptr %16, align 8, !tbaa !5
  store i16 %261, ptr %262, align 2, !tbaa !28
  %263 = load ptr, ptr %16, align 8, !tbaa !5
  %264 = getelementptr inbounds i16, ptr %263, i32 1
  store ptr %264, ptr %16, align 8, !tbaa !5
  br label %265

265:                                              ; preds = %257
  %266 = load i32, ptr %10, align 4, !tbaa !9
  %267 = add i32 %266, 1
  store i32 %267, ptr %10, align 4, !tbaa !9
  br label %250, !llvm.loop !29

268:                                              ; preds = %250
  %269 = load i32, ptr %13, align 4, !tbaa !9
  %270 = add i32 %269, 1
  store i32 %270, ptr %13, align 4, !tbaa !9
  %271 = load i32, ptr %15, align 4, !tbaa !9
  %272 = add i32 %271, -1
  store i32 %272, ptr %15, align 4, !tbaa !9
  %273 = load i32, ptr %14, align 4, !tbaa !9
  %274 = add i32 %273, 1
  store i32 %274, ptr %14, align 4, !tbaa !9
  br label %69, !llvm.loop !30

275:                                              ; preds = %84
  %276 = load ptr, ptr %6, align 8, !tbaa !5
  %277 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %276, i32 0, i32 3
  store volatile i32 1, ptr %277, align 8, !tbaa !11
  br label %278

278:                                              ; preds = %275
  %279 = load ptr, ptr %6, align 8, !tbaa !5
  %280 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %279, i32 0, i32 2
  store i32 0, ptr %280, align 4, !tbaa !14
  br label %281

281:                                              ; preds = %278
  br label %282

282:                                              ; preds = %281
  br label %284

283:                                              ; preds = %25
  store i32 1, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %286

284:                                              ; preds = %282
  br label %285

285:                                              ; preds = %284
  store i32 0, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %286

286:                                              ; preds = %285, %283, %242, %36, %24
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %287 = load i32, ptr %5, align 4
  ret i32 %287
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 56}
!23 = !{!7, !7, i64 0}
!24 = !{!12, !10, i64 44}
!25 = !{!12, !10, i64 68}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!17, !17, i64 0}
!29 = distinct !{!29, !27}
!30 = distinct !{!30, !27}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Read_Page_16b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %79, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %79

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %79, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not74 = icmp eq i32 %3, 0
  br i1 %.not74, label %.sink.split83, label %.lr.ph79

.lr.ph79:                                         ; preds = %15
  %18 = getelementptr inbounds i8, ptr %0, i64 64
  %19 = load i32, ptr %18, align 4, !tbaa !13
  %20 = getelementptr inbounds i8, ptr %1, i64 2
  %21 = load i16, ptr %20, align 2, !tbaa !14
  %22 = zext i16 %21 to i32
  %23 = mul i32 %19, %22
  %24 = getelementptr inbounds i8, ptr %1, i64 4
  %25 = load i16, ptr %24, align 2, !tbaa !17
  %26 = zext i16 %25 to i32
  %27 = add i32 %23, %26
  %28 = load i32, ptr %17, align 4, !tbaa !18
  %29 = mul i32 %27, %28
  %30 = load i16, ptr %1, align 2, !tbaa !19
  %31 = zext i16 %30 to i32
  %32 = add i32 %29, %31
  %33 = getelementptr inbounds i8, ptr %0, i64 56
  %34 = getelementptr inbounds i8, ptr %0, i64 68
  br label %35

35:                                               ; preds = %.lr.ph79, %._crit_edge
  %.077 = phi ptr [ %2, %.lr.ph79 ], [ %.1.lcssa, %._crit_edge ]
  %.06676 = phi i32 [ %3, %.lr.ph79 ], [ %77, %._crit_edge ]
  %.06775 = phi i32 [ %32, %.lr.ph79 ], [ %78, %._crit_edge ]
  %36 = load i32, ptr %17, align 4, !tbaa !18
  %37 = load i32, ptr %33, align 4, !tbaa !20
  %38 = mul i32 %37, %36
  %39 = icmp ult i32 %.06775, %38
  br i1 %39, label %40, label %.sink.split83

40:                                               ; preds = %35
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  %41 = load i32, ptr %16, align 4, !tbaa !22
  %42 = icmp ult i32 %41, 513
  %43 = load i32, ptr %17, align 4, !tbaa !18
  %44 = load i32, ptr %33, align 4, !tbaa !20
  %45 = mul i32 %44, %43
  %46 = icmp ult i32 %45, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %42, label %47, label %51

47:                                               ; preds = %40
  %48 = trunc i32 %.06775 to i8
  store volatile i8 %48, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %49 = lshr i32 %.06775, 8
  %50 = trunc i32 %49 to i8
  store volatile i8 %50, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %46, label %57, label %.sink.split

51:                                               ; preds = %40
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %52 = trunc i32 %.06775 to i8
  store volatile i8 %52, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %53 = lshr i32 %.06775, 8
  %54 = trunc i32 %53 to i8
  store volatile i8 %54, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %46, label %57, label %.sink.split

.sink.split:                                      ; preds = %51, %47
  %55 = lshr i32 %.06775, 16
  %56 = trunc i32 %55 to i8
  store volatile i8 %56, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br label %57

57:                                               ; preds = %.sink.split, %51, %47
  store volatile i8 48, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  %58 = load i32, ptr %34, align 4, !tbaa !23
  %59 = icmp eq i32 %58, 1
  br i1 %59, label %60, label %69

60:                                               ; preds = %57
  %61 = tail call i32 @HAL_GetTick() #3
  br label %62

62:                                               ; preds = %64, %60
  %63 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not71 = icmp eq i32 %63, 64
  br i1 %.not71, label %68, label %64

64:                                               ; preds = %62
  %65 = tail call i32 @HAL_GetTick() #3
  %66 = sub i32 %65, %61
  %67 = icmp ugt i32 %66, 16777216
  br i1 %67, label %.sink.split83, label %62, !llvm.loop !24

68:                                               ; preds = %62
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  br label %69

69:                                               ; preds = %68, %57
  %70 = load i32, ptr %16, align 4, !tbaa !22
  %.not81 = icmp eq i32 %70, 0
  br i1 %.not81, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %69
  %.pre = load i16, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !26
  %71 = zext i32 %70 to i64
  %min.iters.check = icmp ult i32 %70, 16
  br i1 %min.iters.check, label %.lr.ph.preheader88, label %vector.ph

vector.ph:                                        ; preds = %.lr.ph.preheader
  %n.vec = and i64 %71, 4294967280
  %72 = shl nuw nsw i64 %n.vec, 1
  %ind.end = getelementptr i8, ptr %.077, i64 %72
  %ind.end85 = trunc nuw i64 %n.vec to i32
  %broadcast.splatinsert = insertelement <8 x i16> poison, i16 %.pre, i64 0
  %broadcast.splat = shufflevector <8 x i16> %broadcast.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %offset.idx = shl i64 %index, 1
  %next.gep = getelementptr i8, ptr %.077, i64 %offset.idx
  %73 = getelementptr i8, ptr %next.gep, i64 16
  store <8 x i16> %broadcast.splat, ptr %next.gep, align 2, !tbaa !26
  store <8 x i16> %broadcast.splat, ptr %73, align 2, !tbaa !26
  %index.next = add nuw i64 %index, 16
  %74 = icmp eq i64 %index.next, %n.vec
  br i1 %74, label %middle.block, label %vector.body, !llvm.loop !27

middle.block:                                     ; preds = %vector.body
  %cmp.n = icmp eq i64 %n.vec, %71
  br i1 %cmp.n, label %._crit_edge, label %.lr.ph.preheader88

.lr.ph.preheader88:                               ; preds = %middle.block, %.lr.ph.preheader
  %.173.ph = phi ptr [ %.077, %.lr.ph.preheader ], [ %ind.end, %middle.block ]
  %.07072.ph = phi i32 [ 0, %.lr.ph.preheader ], [ %ind.end85, %middle.block ]
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader88, %.lr.ph
  %.173 = phi ptr [ %75, %.lr.ph ], [ %.173.ph, %.lr.ph.preheader88 ]
  %.07072 = phi i32 [ %76, %.lr.ph ], [ %.07072.ph, %.lr.ph.preheader88 ]
  store i16 %.pre, ptr %.173, align 2, !tbaa !26
  %75 = getelementptr inbounds i8, ptr %.173, i64 2
  %76 = add nuw i32 %.07072, 1
  %exitcond.not = icmp eq i32 %76, %70
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !30

._crit_edge:                                      ; preds = %.lr.ph, %middle.block, %69
  %.1.lcssa = phi ptr [ %.077, %69 ], [ %ind.end, %middle.block ], [ %75, %.lr.ph ]
  %77 = add i32 %.06676, -1
  %78 = add i32 %.06775, 1
  %.not = icmp eq i32 %77, 0
  br i1 %.not, label %.sink.split83, label %35, !llvm.loop !31

.sink.split83:                                    ; preds = %._crit_edge, %35, %64, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %64 ], [ 1, %35 ], [ 1, %._crit_edge ]
  %.069.ph = phi i32 [ 0, %15 ], [ 3, %64 ], [ 0, %35 ], [ 0, %._crit_edge ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %79

79:                                               ; preds = %.sink.split83, %8, %11, %4
  %.069 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.069.ph, %.sink.split83 ]
  ret i32 %.069
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 64}
!14 = !{!15, !16, i64 2}
!15 = !{!"", !16, i64 0, !16, i64 2, !16, i64 4}
!16 = !{!"short", !8, i64 0}
!17 = !{!15, !16, i64 4}
!18 = !{!6, !11, i64 52}
!19 = !{!15, !16, i64 0}
!20 = !{!6, !11, i64 56}
!21 = !{!8, !8, i64 0}
!22 = !{!6, !11, i64 44}
!23 = !{!6, !11, i64 68}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!16, !16, i64 0}
!27 = distinct !{!27, !25, !28, !29}
!28 = !{!"llvm.loop.isvectorized", i32 1}
!29 = !{!"llvm.loop.unroll.runtime.disable"}
!30 = distinct !{!30, !25, !29, !28}
!31 = distinct !{!31, !25}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass