; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (fmc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.FMC_Bank1_TypeDef = type { [8 x i32] }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @FMC_NORSRAM_Init(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %6 = load ptr, ptr %3, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %6, i32 0, i32 0
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %8, i32 0, i32 0
  %10 = load i32, ptr %9, align 4, !tbaa !9
  %11 = zext i32 %10 to i64
  %12 = getelementptr inbounds [8 x i32], ptr %7, i64 0, i64 %11
  %13 = load volatile i32, ptr %12, align 4, !tbaa !12
  %14 = zext i32 %13 to i64
  %15 = and i64 %14, -2
  %16 = trunc i64 %15 to i32
  store volatile i32 %16, ptr %12, align 4, !tbaa !12
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %17, i32 0, i32 2
  %19 = load i32, ptr %18, align 4, !tbaa !13
  %20 = icmp eq i32 %19, 8
  br i1 %20, label %21, label %22

21:                                               ; preds = %2
  store i32 64, ptr %5, align 4, !tbaa !12
  br label %23

22:                                               ; preds = %2
  store i32 0, ptr %5, align 4, !tbaa !12
  br label %23

23:                                               ; preds = %22, %21
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %26, i32 0, i32 0
  %28 = load i32, ptr %27, align 4, !tbaa !9
  %29 = zext i32 %28 to i64
  %30 = getelementptr inbounds [8 x i32], ptr %25, i64 0, i64 %29
  %31 = load volatile i32, ptr %30, align 4, !tbaa !12
  %32 = zext i32 %31 to i64
  %33 = and i64 %32, -4193152
  %34 = load i32, ptr %5, align 4, !tbaa !12
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !14
  %38 = or i32 %34, %37
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %39, i32 0, i32 2
  %41 = load i32, ptr %40, align 4, !tbaa !13
  %42 = or i32 %38, %41
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %43, i32 0, i32 3
  %45 = load i32, ptr %44, align 4, !tbaa !15
  %46 = or i32 %42, %45
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %47, i32 0, i32 4
  %49 = load i32, ptr %48, align 4, !tbaa !16
  %50 = or i32 %46, %49
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %51, i32 0, i32 5
  %53 = load i32, ptr %52, align 4, !tbaa !17
  %54 = or i32 %50, %53
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %55, i32 0, i32 6
  %57 = load i32, ptr %56, align 4, !tbaa !18
  %58 = or i32 %54, %57
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %59, i32 0, i32 7
  %61 = load i32, ptr %60, align 4, !tbaa !19
  %62 = or i32 %58, %61
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %63, i32 0, i32 8
  %65 = load i32, ptr %64, align 4, !tbaa !20
  %66 = or i32 %62, %65
  %67 = load ptr, ptr %4, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %67, i32 0, i32 9
  %69 = load i32, ptr %68, align 4, !tbaa !21
  %70 = or i32 %66, %69
  %71 = load ptr, ptr %4, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %71, i32 0, i32 10
  %73 = load i32, ptr %72, align 4, !tbaa !22
  %74 = or i32 %70, %73
  %75 = load ptr, ptr %4, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %75, i32 0, i32 11
  %77 = load i32, ptr %76, align 4, !tbaa !23
  %78 = or i32 %74, %77
  %79 = load ptr, ptr %4, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %79, i32 0, i32 12
  %81 = load i32, ptr %80, align 4, !tbaa !24
  %82 = or i32 %78, %81
  %83 = load ptr, ptr %4, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %83, i32 0, i32 13
  %85 = load i32, ptr %84, align 4, !tbaa !25
  %86 = or i32 %82, %85
  %87 = load ptr, ptr %4, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %87, i32 0, i32 14
  %89 = load i32, ptr %88, align 4, !tbaa !26
  %90 = or i32 %86, %89
  %91 = zext i32 %90 to i64
  %92 = or i64 %33, %91
  %93 = trunc i64 %92 to i32
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %4, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %96, i32 0, i32 0
  %98 = load i32, ptr %97, align 4, !tbaa !9
  %99 = zext i32 %98 to i64
  %100 = getelementptr inbounds [8 x i32], ptr %95, i64 0, i64 %99
  store volatile i32 %93, ptr %100, align 4, !tbaa !12
  %101 = load ptr, ptr %4, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %101, i32 0, i32 12
  %103 = load i32, ptr %102, align 4, !tbaa !24
  %104 = icmp eq i32 %103, 1048576
  br i1 %104, label %105, label %126

105:                                              ; preds = %23
  %106 = load ptr, ptr %4, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %106, i32 0, i32 0
  %108 = load i32, ptr %107, align 4, !tbaa !9
  %109 = icmp ne i32 %108, 0
  br i1 %109, label %110, label %126

110:                                              ; preds = %105
  %111 = load ptr, ptr %3, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %111, i32 0, i32 0
  %113 = getelementptr inbounds [8 x i32], ptr %112, i64 0, i64 0
  %114 = load volatile i32, ptr %113, align 4, !tbaa !12
  %115 = zext i32 %114 to i64
  %116 = and i64 %115, -1048577
  %117 = load ptr, ptr %4, align 8, !tbaa !5
  %118 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %117, i32 0, i32 12
  %119 = load i32, ptr %118, align 4, !tbaa !24
  %120 = zext i32 %119 to i64
  %121 = or i64 %116, %120
  %122 = trunc i64 %121 to i32
  %123 = load ptr, ptr %3, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %123, i32 0, i32 0
  %125 = getelementptr inbounds [8 x i32], ptr %124, i64 0, i64 0
  store volatile i32 %122, ptr %125, align 4, !tbaa !12
  br label %126

126:                                              ; preds = %110, %105, %23
  %127 = load ptr, ptr %4, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %127, i32 0, i32 0
  %129 = load i32, ptr %128, align 4, !tbaa !9
  %130 = icmp ne i32 %129, 0
  br i1 %130, label %131, label %140

131:                                              ; preds = %126
  %132 = load ptr, ptr %4, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.FMC_NORSRAM_InitTypeDef, ptr %132, i32 0, i32 13
  %134 = load i32, ptr %133, align 4, !tbaa !25
  %135 = load ptr, ptr %3, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.FMC_Bank1_TypeDef, ptr %135, i32 0, i32 0
  %137 = getelementptr inbounds [8 x i32], ptr %136, i64 0, i64 0
  %138 = load volatile i32, ptr %137, align 4, !tbaa !12
  %139 = or i32 %138, %134
  store volatile i32 %139, ptr %137, align 4, !tbaa !12
  br label %140

140:                                              ; preds = %131, %126
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !7, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!10, !11, i64 8}
!14 = !{!10, !11, i64 4}
!15 = !{!10, !11, i64 12}
!16 = !{!10, !11, i64 16}
!17 = !{!10, !11, i64 20}
!18 = !{!10, !11, i64 24}
!19 = !{!10, !11, i64 28}
!20 = !{!10, !11, i64 32}
!21 = !{!10, !11, i64 36}
!22 = !{!10, !11, i64 40}
!23 = !{!10, !11, i64 44}
!24 = !{!10, !11, i64 48}
!25 = !{!10, !11, i64 52}
!26 = !{!10, !11, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable
define dso_local noundef i32 @FMC_NORSRAM_Init(ptr noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %3 = load i32, ptr %1, align 4, !tbaa !5
  %4 = zext i32 %3 to i64
  %5 = getelementptr inbounds [8 x i32], ptr %0, i64 0, i64 %4
  %6 = load volatile i32, ptr %5, align 4, !tbaa !10
  %7 = and i32 %6, -2
  store volatile i32 %7, ptr %5, align 4, !tbaa !10
  %8 = getelementptr inbounds i8, ptr %1, i64 8
  %9 = load i32, ptr %8, align 4, !tbaa !11
  %10 = icmp eq i32 %9, 8
  %. = select i1 %10, i32 64, i32 0
  %11 = load i32, ptr %1, align 4, !tbaa !5
  %12 = zext i32 %11 to i64
  %13 = getelementptr inbounds [8 x i32], ptr %0, i64 0, i64 %12
  %14 = load volatile i32, ptr %13, align 4, !tbaa !10
  %15 = and i32 %14, -4193152
  %16 = getelementptr inbounds i8, ptr %1, i64 4
  %17 = load i32, ptr %16, align 4, !tbaa !12
  %18 = getelementptr inbounds i8, ptr %1, i64 12
  %19 = load <8 x i32>, ptr %18, align 4, !tbaa !10
  %20 = getelementptr inbounds i8, ptr %1, i64 44
  %21 = getelementptr inbounds i8, ptr %1, i64 48
  %22 = getelementptr inbounds i8, ptr %1, i64 52
  %23 = load <4 x i32>, ptr %20, align 4, !tbaa !10
  %24 = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %19)
  %25 = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %23)
  %op.rdx = or i32 %24, %25
  %op.rdx31 = or i32 %op.rdx, %17
  %op.rdx32 = or i32 %9, %15
  %op.rdx33 = or i32 %op.rdx31, %op.rdx32
  %op.rdx34 = or i32 %op.rdx33, %.
  store volatile i32 %op.rdx34, ptr %13, align 4, !tbaa !10
  %26 = load i32, ptr %21, align 4, !tbaa !13
  %27 = icmp eq i32 %26, 1048576
  br i1 %27, label %28, label %33

28:                                               ; preds = %2
  %29 = load i32, ptr %1, align 4, !tbaa !5
  %.not = icmp eq i32 %29, 0
  br i1 %.not, label %.thread, label %30

30:                                               ; preds = %28
  %31 = load volatile i32, ptr %0, align 4, !tbaa !10
  %32 = or i32 %31, 1048576
  store volatile i32 %32, ptr %0, align 4, !tbaa !10
  br label %33

33:                                               ; preds = %30, %2
  %.pr = load i32, ptr %1, align 4, !tbaa !5
  %.not29 = icmp eq i32 %.pr, 0
  br i1 %.not29, label %.thread, label %34

34:                                               ; preds = %33
  %35 = load i32, ptr %22, align 4, !tbaa !14
  %36 = load volatile i32, ptr %0, align 4, !tbaa !10
  %37 = or i32 %36, %35
  store volatile i32 %37, ptr %0, align 4, !tbaa !10
  br label %.thread

.thread:                                          ; preds = %28, %34, %33
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>) #1

attributes #0 = { nofree norecurse nounwind memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!7, !7, i64 0}
!11 = !{!6, !7, i64 8}
!12 = !{!6, !7, i64 4}
!13 = !{!6, !7, i64 48}
!14 = !{!6, !7, i64 52}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass