; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_IC_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i16 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i16 %3, ptr %9, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %12, i32 0, i32 5
  %14 = load volatile i32, ptr %13, align 4, !tbaa !13
  %15 = icmp eq i32 %14, 2
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

17:                                               ; preds = %4
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %18, i32 0, i32 5
  %20 = load volatile i32, ptr %19, align 4, !tbaa !13
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %22, label %34

22:                                               ; preds = %17
  %23 = load ptr, ptr %8, align 8, !tbaa !5
  %24 = icmp eq ptr %23, null
  br i1 %24, label %25, label %30

25:                                               ; preds = %22
  %26 = load i16, ptr %9, align 2, !tbaa !11
  %27 = zext i16 %26 to i32
  %28 = icmp ugt i32 %27, 0
  br i1 %28, label %29, label %30

29:                                               ; preds = %25
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

30:                                               ; preds = %25, %22
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %31, i32 0, i32 5
  store volatile i32 2, ptr %32, align 4, !tbaa !13
  br label %33

33:                                               ; preds = %30
  br label %35

34:                                               ; preds = %17
  br label %35

35:                                               ; preds = %34, %33
  br label %36

36:                                               ; preds = %35
  %37 = load i32, ptr %7, align 4, !tbaa !9
  switch i32 %37, label %202 [
    i32 0, label %38
    i32 4, label %79
    i32 8, label %120
    i32 12, label %161
  ]

38:                                               ; preds = %36
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %39, i32 0, i32 3
  %41 = getelementptr inbounds [7 x ptr], ptr %40, i64 0, i64 1
  %42 = load ptr, ptr %41, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %42, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %43, align 8, !tbaa !16
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %44, i32 0, i32 3
  %46 = getelementptr inbounds [7 x ptr], ptr %45, i64 0, i64 1
  %47 = load ptr, ptr %46, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %47, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %48, align 8, !tbaa !19
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %49, i32 0, i32 3
  %51 = getelementptr inbounds [7 x ptr], ptr %50, i64 0, i64 1
  %52 = load ptr, ptr %51, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %52, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %53, align 8, !tbaa !20
  %54 = load ptr, ptr %6, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %54, i32 0, i32 3
  %56 = getelementptr inbounds [7 x ptr], ptr %55, i64 0, i64 1
  %57 = load ptr, ptr %56, align 8, !tbaa !5
  %58 = load ptr, ptr %6, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !21
  %61 = getelementptr inbounds %struct.TIM_TypeDef, ptr %60, i32 0, i32 13
  %62 = ptrtoint ptr %61 to i32
  %63 = load ptr, ptr %8, align 8, !tbaa !5
  %64 = ptrtoint ptr %63 to i32
  %65 = load i16, ptr %9, align 2, !tbaa !11
  %66 = zext i16 %65 to i32
  %67 = call i32 @HAL_DMA_Start_IT(ptr noundef %57, i32 noundef %62, i32 noundef %64, i32 noundef %66)
  %68 = icmp ne i32 %67, 0
  br i1 %68, label %69, label %70

69:                                               ; preds = %38
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

70:                                               ; preds = %38
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %71, i32 0, i32 0
  %73 = load ptr, ptr %72, align 8, !tbaa !21
  %74 = getelementptr inbounds %struct.TIM_TypeDef, ptr %73, i32 0, i32 3
  %75 = load volatile i32, ptr %74, align 4, !tbaa !22
  %76 = zext i32 %75 to i64
  %77 = or i64 %76, 512
  %78 = trunc i64 %77 to i32
  store volatile i32 %78, ptr %74, align 4, !tbaa !22
  br label %203

79:                                               ; preds = %36
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %80, i32 0, i32 3
  %82 = getelementptr inbounds [7 x ptr], ptr %81, i64 0, i64 2
  %83 = load ptr, ptr %82, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %83, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %84, align 8, !tbaa !16
  %85 = load ptr, ptr %6, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %85, i32 0, i32 3
  %87 = getelementptr inbounds [7 x ptr], ptr %86, i64 0, i64 2
  %88 = load ptr, ptr %87, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %88, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %89, align 8, !tbaa !19
  %90 = load ptr, ptr %6, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %90, i32 0, i32 3
  %92 = getelementptr inbounds [7 x ptr], ptr %91, i64 0, i64 2
  %93 = load ptr, ptr %92, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %93, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %94, align 8, !tbaa !20
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %95, i32 0, i32 3
  %97 = getelementptr inbounds [7 x ptr], ptr %96, i64 0, i64 2
  %98 = load ptr, ptr %97, align 8, !tbaa !5
  %99 = load ptr, ptr %6, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %99, i32 0, i32 0
  %101 = load ptr, ptr %100, align 8, !tbaa !21
  %102 = getelementptr inbounds %struct.TIM_TypeDef, ptr %101, i32 0, i32 14
  %103 = ptrtoint ptr %102 to i32
  %104 = load ptr, ptr %8, align 8, !tbaa !5
  %105 = ptrtoint ptr %104 to i32
  %106 = load i16, ptr %9, align 2, !tbaa !11
  %107 = zext i16 %106 to i32
  %108 = call i32 @HAL_DMA_Start_IT(ptr noundef %98, i32 noundef %103, i32 noundef %105, i32 noundef %107)
  %109 = icmp ne i32 %108, 0
  br i1 %109, label %110, label %111

110:                                              ; preds = %79
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

111:                                              ; preds = %79
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %112, i32 0, i32 0
  %114 = load ptr, ptr %113, align 8, !tbaa !21
  %115 = getelementptr inbounds %struct.TIM_TypeDef, ptr %114, i32 0, i32 3
  %116 = load volatile i32, ptr %115, align 4, !tbaa !22
  %117 = zext i32 %116 to i64
  %118 = or i64 %117, 1024
  %119 = trunc i64 %118 to i32
  store volatile i32 %119, ptr %115, align 4, !tbaa !22
  br label %203

120:                                              ; preds = %36
  %121 = load ptr, ptr %6, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %121, i32 0, i32 3
  %123 = getelementptr inbounds [7 x ptr], ptr %122, i64 0, i64 3
  %124 = load ptr, ptr %123, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %124, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %125, align 8, !tbaa !16
  %126 = load ptr, ptr %6, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %126, i32 0, i32 3
  %128 = getelementptr inbounds [7 x ptr], ptr %127, i64 0, i64 3
  %129 = load ptr, ptr %128, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %129, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %130, align 8, !tbaa !19
  %131 = load ptr, ptr %6, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %131, i32 0, i32 3
  %133 = getelementptr inbounds [7 x ptr], ptr %132, i64 0, i64 3
  %134 = load ptr, ptr %133, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %134, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %135, align 8, !tbaa !20
  %136 = load ptr, ptr %6, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %136, i32 0, i32 3
  %138 = getelementptr inbounds [7 x ptr], ptr %137, i64 0, i64 3
  %139 = load ptr, ptr %138, align 8, !tbaa !5
  %140 = load ptr, ptr %6, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %140, i32 0, i32 0
  %142 = load ptr, ptr %141, align 8, !tbaa !21
  %143 = getelementptr inbounds %struct.TIM_TypeDef, ptr %142, i32 0, i32 15
  %144 = ptrtoint ptr %143 to i32
  %145 = load ptr, ptr %8, align 8, !tbaa !5
  %146 = ptrtoint ptr %145 to i32
  %147 = load i16, ptr %9, align 2, !tbaa !11
  %148 = zext i16 %147 to i32
  %149 = call i32 @HAL_DMA_Start_IT(ptr noundef %139, i32 noundef %144, i32 noundef %146, i32 noundef %148)
  %150 = icmp ne i32 %149, 0
  br i1 %150, label %151, label %152

151:                                              ; preds = %120
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

152:                                              ; preds = %120
  %153 = load ptr, ptr %6, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %153, i32 0, i32 0
  %155 = load ptr, ptr %154, align 8, !tbaa !21
  %156 = getelementptr inbounds %struct.TIM_TypeDef, ptr %155, i32 0, i32 3
  %157 = load volatile i32, ptr %156, align 4, !tbaa !22
  %158 = zext i32 %157 to i64
  %159 = or i64 %158, 2048
  %160 = trunc i64 %159 to i32
  store volatile i32 %160, ptr %156, align 4, !tbaa !22
  br label %203

161:                                              ; preds = %36
  %162 = load ptr, ptr %6, align 8, !tbaa !5
  %163 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %162, i32 0, i32 3
  %164 = getelementptr inbounds [7 x ptr], ptr %163, i64 0, i64 4
  %165 = load ptr, ptr %164, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %165, i32 0, i32 5
  store ptr @TIM_DMACaptureCplt, ptr %166, align 8, !tbaa !16
  %167 = load ptr, ptr %6, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %167, i32 0, i32 3
  %169 = getelementptr inbounds [7 x ptr], ptr %168, i64 0, i64 4
  %170 = load ptr, ptr %169, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %170, i32 0, i32 6
  store ptr @TIM_DMACaptureHalfCplt, ptr %171, align 8, !tbaa !19
  %172 = load ptr, ptr %6, align 8, !tbaa !5
  %173 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %172, i32 0, i32 3
  %174 = getelementptr inbounds [7 x ptr], ptr %173, i64 0, i64 4
  %175 = load ptr, ptr %174, align 8, !tbaa !5
  %176 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %175, i32 0, i32 9
  store ptr @TIM_DMAError, ptr %176, align 8, !tbaa !20
  %177 = load ptr, ptr %6, align 8, !tbaa !5
  %178 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %177, i32 0, i32 3
  %179 = getelementptr inbounds [7 x ptr], ptr %178, i64 0, i64 4
  %180 = load ptr, ptr %179, align 8, !tbaa !5
  %181 = load ptr, ptr %6, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %181, i32 0, i32 0
  %183 = load ptr, ptr %182, align 8, !tbaa !21
  %184 = getelementptr inbounds %struct.TIM_TypeDef, ptr %183, i32 0, i32 16
  %185 = ptrtoint ptr %184 to i32
  %186 = load ptr, ptr %8, align 8, !tbaa !5
  %187 = ptrtoint ptr %186 to i32
  %188 = load i16, ptr %9, align 2, !tbaa !11
  %189 = zext i16 %188 to i32
  %190 = call i32 @HAL_DMA_Start_IT(ptr noundef %180, i32 noundef %185, i32 noundef %187, i32 noundef %189)
  %191 = icmp ne i32 %190, 0
  br i1 %191, label %192, label %193

192:                                              ; preds = %161
  store i32 1, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

193:                                              ; preds = %161
  %194 = load ptr, ptr %6, align 8, !tbaa !5
  %195 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %194, i32 0, i32 0
  %196 = load ptr, ptr %195, align 8, !tbaa !21
  %197 = getelementptr inbounds %struct.TIM_TypeDef, ptr %196, i32 0, i32 3
  %198 = load volatile i32, ptr %197, align 4, !tbaa !22
  %199 = zext i32 %198 to i64
  %200 = or i64 %199, 4096
  %201 = trunc i64 %200 to i32
  store volatile i32 %201, ptr %197, align 4, !tbaa !22
  br label %203

202:                                              ; preds = %36
  br label %203

203:                                              ; preds = %202, %193, %152, %111, %70
  %204 = load ptr, ptr %6, align 8, !tbaa !5
  %205 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %204, i32 0, i32 0
  %206 = load ptr, ptr %205, align 8, !tbaa !21
  %207 = load i32, ptr %7, align 4, !tbaa !9
  call void @TIM_CCxChannelCmd(ptr noundef %206, i32 noundef %207, i32 noundef 1)
  %208 = load ptr, ptr %6, align 8, !tbaa !5
  %209 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %208, i32 0, i32 0
  %210 = load ptr, ptr %209, align 8, !tbaa !21
  %211 = getelementptr inbounds %struct.TIM_TypeDef, ptr %210, i32 0, i32 2
  %212 = load volatile i32, ptr %211, align 4, !tbaa !24
  %213 = zext i32 %212 to i64
  %214 = and i64 %213, 65543
  %215 = trunc i64 %214 to i32
  store i32 %215, ptr %10, align 4, !tbaa !9
  %216 = load i32, ptr %10, align 4, !tbaa !9
  %217 = zext i32 %216 to i64
  %218 = icmp eq i64 %217, 6
  br i1 %218, label %232, label %219

219:                                              ; preds = %203
  %220 = load i32, ptr %10, align 4, !tbaa !9
  %221 = zext i32 %220 to i64
  %222 = icmp eq i64 %221, 65536
  br i1 %222, label %232, label %223

223:                                              ; preds = %219
  %224 = load ptr, ptr %6, align 8, !tbaa !5
  %225 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %224, i32 0, i32 0
  %226 = load ptr, ptr %225, align 8, !tbaa !21
  %227 = getelementptr inbounds %struct.TIM_TypeDef, ptr %226, i32 0, i32 0
  %228 = load volatile i32, ptr %227, align 4, !tbaa !25
  %229 = zext i32 %228 to i64
  %230 = or i64 %229, 1
  %231 = trunc i64 %230 to i32
  store volatile i32 %231, ptr %227, align 4, !tbaa !25
  br label %232

232:                                              ; preds = %223, %219, %203
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %233

233:                                              ; preds = %232, %192, %151, %110, %69, %29, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %234 = load i32, ptr %5, align 4
  ret i32 %234
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureHalfCplt(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !10, i64 100}
!14 = !{!"", !6, i64 0, !15, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!15 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!16 = !{!17, !6, i64 72}
!17 = !{!"__DMA_HandleTypeDef", !6, i64 0, !18, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!19 = !{!17, !6, i64 80}
!20 = !{!17, !6, i64 104}
!21 = !{!14, !6, i64 0}
!22 = !{!23, !10, i64 12}
!23 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!24 = !{!23, !10, i64 8}
!25 = !{!23, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_CCxChannelCmd(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_IC_Start_DMA(ptr noundef %0, i32 noundef %1, ptr noundef %2, i16 noundef zeroext %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 100
  %6 = load volatile i32, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %114, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 4, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %15

11:                                               ; preds = %8
  %12 = icmp eq ptr %2, null
  %13 = icmp ne i16 %3, 0
  %or.cond = and i1 %12, %13
  br i1 %or.cond, label %114, label %14

14:                                               ; preds = %11
  store volatile i32 2, ptr %5, align 4, !tbaa !5
  br label %15

15:                                               ; preds = %14, %8
  %16 = tail call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 30)
  switch i32 %16, label %._crit_edge [
    i32 0, label %17
    i32 1, label %39
    i32 2, label %61
    i32 3, label %83
  ]

._crit_edge:                                      ; preds = %15
  %.pre = load ptr, ptr %0, align 8, !tbaa !12
  br label %105

17:                                               ; preds = %15
  %18 = getelementptr inbounds i8, ptr %0, i64 48
  %19 = load ptr, ptr %18, align 8, !tbaa !13
  %20 = getelementptr inbounds i8, ptr %19, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %20, align 8, !tbaa !14
  %21 = load ptr, ptr %18, align 8, !tbaa !13
  %22 = getelementptr inbounds i8, ptr %21, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %22, align 8, !tbaa !17
  %23 = load ptr, ptr %18, align 8, !tbaa !13
  %24 = getelementptr inbounds i8, ptr %23, i64 104
  store ptr @TIM_DMAError, ptr %24, align 8, !tbaa !18
  %25 = load ptr, ptr %18, align 8, !tbaa !13
  %26 = load ptr, ptr %0, align 8, !tbaa !12
  %27 = getelementptr inbounds i8, ptr %26, i64 52
  %28 = ptrtoint ptr %27 to i64
  %29 = trunc i64 %28 to i32
  %30 = ptrtoint ptr %2 to i64
  %31 = trunc i64 %30 to i32
  %32 = zext i16 %3 to i32
  %33 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %25, i32 noundef %29, i32 noundef %31, i32 noundef %32) #3
  %.not51 = icmp eq i32 %33, 0
  br i1 %.not51, label %34, label %114

34:                                               ; preds = %17
  %35 = load ptr, ptr %0, align 8, !tbaa !12
  %36 = getelementptr inbounds i8, ptr %35, i64 12
  %37 = load volatile i32, ptr %36, align 4, !tbaa !19
  %38 = or i32 %37, 512
  store volatile i32 %38, ptr %36, align 4, !tbaa !19
  br label %105

39:                                               ; preds = %15
  %40 = getelementptr inbounds i8, ptr %0, i64 56
  %41 = load ptr, ptr %40, align 8, !tbaa !13
  %42 = getelementptr inbounds i8, ptr %41, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %42, align 8, !tbaa !14
  %43 = load ptr, ptr %40, align 8, !tbaa !13
  %44 = getelementptr inbounds i8, ptr %43, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %44, align 8, !tbaa !17
  %45 = load ptr, ptr %40, align 8, !tbaa !13
  %46 = getelementptr inbounds i8, ptr %45, i64 104
  store ptr @TIM_DMAError, ptr %46, align 8, !tbaa !18
  %47 = load ptr, ptr %40, align 8, !tbaa !13
  %48 = load ptr, ptr %0, align 8, !tbaa !12
  %49 = getelementptr inbounds i8, ptr %48, i64 56
  %50 = ptrtoint ptr %49 to i64
  %51 = trunc i64 %50 to i32
  %52 = ptrtoint ptr %2 to i64
  %53 = trunc i64 %52 to i32
  %54 = zext i16 %3 to i32
  %55 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %47, i32 noundef %51, i32 noundef %53, i32 noundef %54) #3
  %.not50 = icmp eq i32 %55, 0
  br i1 %.not50, label %56, label %114

56:                                               ; preds = %39
  %57 = load ptr, ptr %0, align 8, !tbaa !12
  %58 = getelementptr inbounds i8, ptr %57, i64 12
  %59 = load volatile i32, ptr %58, align 4, !tbaa !19
  %60 = or i32 %59, 1024
  store volatile i32 %60, ptr %58, align 4, !tbaa !19
  br label %105

61:                                               ; preds = %15
  %62 = getelementptr inbounds i8, ptr %0, i64 64
  %63 = load ptr, ptr %62, align 8, !tbaa !13
  %64 = getelementptr inbounds i8, ptr %63, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %64, align 8, !tbaa !14
  %65 = load ptr, ptr %62, align 8, !tbaa !13
  %66 = getelementptr inbounds i8, ptr %65, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %66, align 8, !tbaa !17
  %67 = load ptr, ptr %62, align 8, !tbaa !13
  %68 = getelementptr inbounds i8, ptr %67, i64 104
  store ptr @TIM_DMAError, ptr %68, align 8, !tbaa !18
  %69 = load ptr, ptr %62, align 8, !tbaa !13
  %70 = load ptr, ptr %0, align 8, !tbaa !12
  %71 = getelementptr inbounds i8, ptr %70, i64 60
  %72 = ptrtoint ptr %71 to i64
  %73 = trunc i64 %72 to i32
  %74 = ptrtoint ptr %2 to i64
  %75 = trunc i64 %74 to i32
  %76 = zext i16 %3 to i32
  %77 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %69, i32 noundef %73, i32 noundef %75, i32 noundef %76) #3
  %.not49 = icmp eq i32 %77, 0
  br i1 %.not49, label %78, label %114

78:                                               ; preds = %61
  %79 = load ptr, ptr %0, align 8, !tbaa !12
  %80 = getelementptr inbounds i8, ptr %79, i64 12
  %81 = load volatile i32, ptr %80, align 4, !tbaa !19
  %82 = or i32 %81, 2048
  store volatile i32 %82, ptr %80, align 4, !tbaa !19
  br label %105

83:                                               ; preds = %15
  %84 = getelementptr inbounds i8, ptr %0, i64 72
  %85 = load ptr, ptr %84, align 8, !tbaa !13
  %86 = getelementptr inbounds i8, ptr %85, i64 72
  store ptr @TIM_DMACaptureCplt, ptr %86, align 8, !tbaa !14
  %87 = load ptr, ptr %84, align 8, !tbaa !13
  %88 = getelementptr inbounds i8, ptr %87, i64 80
  store ptr @TIM_DMACaptureHalfCplt, ptr %88, align 8, !tbaa !17
  %89 = load ptr, ptr %84, align 8, !tbaa !13
  %90 = getelementptr inbounds i8, ptr %89, i64 104
  store ptr @TIM_DMAError, ptr %90, align 8, !tbaa !18
  %91 = load ptr, ptr %84, align 8, !tbaa !13
  %92 = load ptr, ptr %0, align 8, !tbaa !12
  %93 = getelementptr inbounds i8, ptr %92, i64 64
  %94 = ptrtoint ptr %93 to i64
  %95 = trunc i64 %94 to i32
  %96 = ptrtoint ptr %2 to i64
  %97 = trunc i64 %96 to i32
  %98 = zext i16 %3 to i32
  %99 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %91, i32 noundef %95, i32 noundef %97, i32 noundef %98) #3
  %.not = icmp eq i32 %99, 0
  br i1 %.not, label %100, label %114

100:                                              ; preds = %83
  %101 = load ptr, ptr %0, align 8, !tbaa !12
  %102 = getelementptr inbounds i8, ptr %101, i64 12
  %103 = load volatile i32, ptr %102, align 4, !tbaa !19
  %104 = or i32 %103, 4096
  store volatile i32 %104, ptr %102, align 4, !tbaa !19
  br label %105

105:                                              ; preds = %._crit_edge, %100, %78, %56, %34
  %106 = phi ptr [ %.pre, %._crit_edge ], [ %101, %100 ], [ %79, %78 ], [ %57, %56 ], [ %35, %34 ]
  tail call void @TIM_CCxChannelCmd(ptr noundef %106, i32 noundef %1, i32 noundef 1)
  %107 = load ptr, ptr %0, align 8, !tbaa !12
  %108 = getelementptr inbounds i8, ptr %107, i64 8
  %109 = load volatile i32, ptr %108, align 4, !tbaa !21
  %110 = and i32 %109, 65543
  switch i32 %110, label %111 [
    i32 65536, label %114
    i32 6, label %114
  ]

111:                                              ; preds = %105
  %112 = load volatile i32, ptr %107, align 4, !tbaa !22
  %113 = or i32 %112, 1
  store volatile i32 %113, ptr %107, align 4, !tbaa !22
  br label %114

114:                                              ; preds = %111, %105, %105, %83, %61, %39, %17, %11, %4
  %.0 = phi i32 [ 2, %4 ], [ 1, %11 ], [ 1, %17 ], [ 1, %39 ], [ 1, %61 ], [ 1, %83 ], [ 0, %105 ], [ 0, %105 ], [ 0, %111 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_DMACaptureHalfCplt(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fshl.i32(i32, i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 100}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !7, i64 72}
!15 = !{!"__DMA_HandleTypeDef", !7, i64 0, !16, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!17 = !{!15, !7, i64 80}
!18 = !{!15, !7, i64 104}
!19 = !{!20, !11, i64 12}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!21 = !{!20, !11, i64 8}
!22 = !{!20, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass