; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src/ASwitch.ll (ZN7ASwitchD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.ASwitch = type { %class.Unit, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, %"class.std::vector", i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i8, i32, i32, i8, i8, i8, i32, [4 x i8], %class.ASwitchStats }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl" = type { %"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DataPackage *, std::allocator<DataPackage *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.ASwitchStats = type <{ %class.Stats, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8] }>
%class.Stats = type { ptr }

@_ZTV7ASwitch = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7ASwitchD2Ev(ptr noundef nonnull align 8 dereferenceable(288) %0) unnamed_addr #1 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 32) ({ [6 x ptr] }, ptr @_ZTV7ASwitch, i32 0, i32 0, i32 2), ptr %3, align 8, !tbaa !9
  %4 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 12
  %5 = load ptr, ptr %4, align 8, !tbaa !11
  %6 = icmp eq ptr %5, null
  br i1 %6, label %8, label %7

7:                                                ; preds = %1
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %5) #3
  call void @_ZdlPvm(ptr noundef %5, i64 noundef 120) #4
  br label %8

8:                                                ; preds = %7, %1
  %9 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 13
  %10 = load ptr, ptr %9, align 8, !tbaa !28
  %11 = icmp eq ptr %10, null
  br i1 %11, label %13, label %12

12:                                               ; preds = %8
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %10) #3
  call void @_ZdlPvm(ptr noundef %10, i64 noundef 120) #4
  br label %13

13:                                               ; preds = %12, %8
  %14 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 14
  %15 = load ptr, ptr %14, align 8, !tbaa !29
  %16 = icmp eq ptr %15, null
  br i1 %16, label %18, label %17

17:                                               ; preds = %13
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %15) #3
  call void @_ZdlPvm(ptr noundef %15, i64 noundef 120) #4
  br label %18

18:                                               ; preds = %17, %13
  %19 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 15
  %20 = load ptr, ptr %19, align 8, !tbaa !30
  %21 = icmp eq ptr %20, null
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %20) #3
  call void @_ZdlPvm(ptr noundef %20, i64 noundef 120) #4
  br label %23

23:                                               ; preds = %22, %18
  %24 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 16
  %25 = load ptr, ptr %24, align 8, !tbaa !31
  %26 = icmp eq ptr %25, null
  br i1 %26, label %28, label %27

27:                                               ; preds = %23
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %25) #3
  call void @_ZdlPvm(ptr noundef %25, i64 noundef 120) #4
  br label %28

28:                                               ; preds = %27, %23
  %29 = getelementptr inbounds %class.ASwitch, ptr %3, i32 0, i32 17
  call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %29) #3
  call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %3) #3
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2 align 2

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 96}
!12 = !{!"_ZTS7ASwitch", !13, i64 0, !14, i64 48, !14, i64 52, !14, i64 56, !14, i64 60, !14, i64 64, !14, i64 68, !14, i64 72, !14, i64 76, !14, i64 80, !14, i64 84, !14, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !18, i64 136, !14, i64 160, !6, i64 168, !6, i64 176, !6, i64 184, !6, i64 192, !6, i64 200, !14, i64 208, !22, i64 212, !23, i64 216, !24, i64 220, !25, i64 224, !23, i64 228, !23, i64 229, !23, i64 230, !14, i64 232, !26, i64 240}
!13 = !{!"_ZTS4Unit", !14, i64 8, !15, i64 16}
!14 = !{!"int", !7, i64 0}
!15 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !16, i64 0, !17, i64 8, !7, i64 16}
!16 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!17 = !{!"long", !7, i64 0}
!18 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTS4fl_t", !7, i64 0}
!23 = !{!"bool", !7, i64 0}
!24 = !{!"_ZTS13adderconfig_t", !7, i64 0}
!25 = !{!"_ZTS16adderoperation_t", !7, i64 0}
!26 = !{!"_ZTS12ASwitchStats", !27, i64 0, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40}
!27 = !{!"_ZTS5Stats"}
!28 = !{!12, !6, i64 104}
!29 = !{!12, !6, i64 112}
!30 = !{!12, !6, i64 120}
!31 = !{!12, !6, i64 128}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV7ASwitch = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7ASwitchD2Ev(ptr noundef nonnull align 8 dereferenceable(288) %0) unnamed_addr #1 align 2 {
  store ptr getelementptr inbounds inrange(-16, 32) (i8, ptr @_ZTV7ASwitch, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 96
  %3 = load ptr, ptr %2, align 8, !tbaa !8
  %4 = icmp eq ptr %3, null
  br i1 %4, label %6, label %5

5:                                                ; preds = %1
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %3) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %3, i64 noundef 120) #4
  br label %6

6:                                                ; preds = %5, %1
  %7 = getelementptr inbounds i8, ptr %0, i64 104
  %8 = load ptr, ptr %7, align 8, !tbaa !27
  %9 = icmp eq ptr %8, null
  br i1 %9, label %11, label %10

10:                                               ; preds = %6
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %8) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %8, i64 noundef 120) #4
  br label %11

11:                                               ; preds = %10, %6
  %12 = getelementptr inbounds i8, ptr %0, i64 112
  %13 = load ptr, ptr %12, align 8, !tbaa !28
  %14 = icmp eq ptr %13, null
  br i1 %14, label %16, label %15

15:                                               ; preds = %11
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %13) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %13, i64 noundef 120) #4
  br label %16

16:                                               ; preds = %15, %11
  %17 = getelementptr inbounds i8, ptr %0, i64 120
  %18 = load ptr, ptr %17, align 8, !tbaa !29
  %19 = icmp eq ptr %18, null
  br i1 %19, label %21, label %20

20:                                               ; preds = %16
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %18) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %18, i64 noundef 120) #4
  br label %21

21:                                               ; preds = %20, %16
  %22 = getelementptr inbounds i8, ptr %0, i64 128
  %23 = load ptr, ptr %22, align 8, !tbaa !30
  %24 = icmp eq ptr %23, null
  br i1 %24, label %26, label %25

25:                                               ; preds = %21
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %23) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %23, i64 noundef 120) #4
  br label %26

26:                                               ; preds = %25, %21
  %27 = getelementptr inbounds i8, ptr %0, i64 136
  tail call void @_ZNSt6vectorIP11DataPackageSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %27) #3
  tail call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %0) #3
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2 align 2

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !15, i64 96}
!9 = !{!"_ZTS7ASwitch", !10, i64 0, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !15, i64 96, !15, i64 104, !15, i64 112, !15, i64 120, !15, i64 128, !17, i64 136, !11, i64 160, !15, i64 168, !15, i64 176, !15, i64 184, !15, i64 192, !15, i64 200, !11, i64 208, !21, i64 212, !22, i64 216, !23, i64 220, !24, i64 224, !22, i64 228, !22, i64 229, !22, i64 230, !11, i64 232, !25, i64 240}
!10 = !{!"_ZTS4Unit", !11, i64 8, !13, i64 16}
!11 = !{!"int", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !16, i64 8, !12, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !15, i64 0}
!15 = !{!"any pointer", !12, i64 0}
!16 = !{!"long", !12, i64 0}
!17 = !{!"_ZTSSt6vectorIP11DataPackageSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP11DataPackageSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP11DataPackageSaIS1_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!21 = !{!"_ZTS4fl_t", !12, i64 0}
!22 = !{!"bool", !12, i64 0}
!23 = !{!"_ZTS13adderconfig_t", !12, i64 0}
!24 = !{!"_ZTS16adderoperation_t", !12, i64 0}
!25 = !{!"_ZTS12ASwitchStats", !26, i64 0, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40}
!26 = !{!"_ZTS5Stats"}
!27 = !{!9, !15, i64 104}
!28 = !{!9, !15, i64 112}
!29 = !{!9, !15, i64 120}
!30 = !{!9, !15, i64 128}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,InstCombinePass,SROAPass,TailCallElimPass