; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (ConfigChannel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TIM_HandleTypeDef = type { ptr, %struct.TIM_Base_InitTypeDef, i32, [7 x ptr], i32, i32 }
%struct.TIM_Base_InitTypeDef = type { i32, i32, i32, i32, i32, i32 }
%struct.TIM_IC_InitTypeDef = type { i32, i32, i32, i32 }
%struct.TIM_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_TIM_IC_ConfigChannel(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  br label %8

8:                                                ; preds = %3
  %9 = load ptr, ptr %5, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %9, i32 0, i32 4
  %11 = load i32, ptr %10, align 8, !tbaa !11
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 2, ptr %4, align 4
  br label %160

14:                                               ; preds = %8
  %15 = load ptr, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %15, i32 0, i32 4
  store i32 1, ptr %16, align 8, !tbaa !11
  br label %17

17:                                               ; preds = %14
  br label %18

18:                                               ; preds = %17
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %19, i32 0, i32 5
  store volatile i32 2, ptr %20, align 4, !tbaa !14
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = icmp eq i32 %21, 0
  br i1 %22, label %23, label %53

23:                                               ; preds = %18
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %25, align 8, !tbaa !15
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 4, !tbaa !16
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %30, i32 0, i32 1
  %32 = load i32, ptr %31, align 4, !tbaa !18
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %33, i32 0, i32 3
  %35 = load i32, ptr %34, align 4, !tbaa !19
  call void @TIM_TI1_SetConfig(ptr noundef %26, i32 noundef %29, i32 noundef %32, i32 noundef %35)
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %36, i32 0, i32 0
  %38 = load ptr, ptr %37, align 8, !tbaa !15
  %39 = getelementptr inbounds %struct.TIM_TypeDef, ptr %38, i32 0, i32 6
  %40 = load volatile i32, ptr %39, align 4, !tbaa !20
  %41 = zext i32 %40 to i64
  %42 = and i64 %41, -13
  %43 = trunc i64 %42 to i32
  store volatile i32 %43, ptr %39, align 4, !tbaa !20
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %44, i32 0, i32 2
  %46 = load i32, ptr %45, align 4, !tbaa !22
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %47, i32 0, i32 0
  %49 = load ptr, ptr %48, align 8, !tbaa !15
  %50 = getelementptr inbounds %struct.TIM_TypeDef, ptr %49, i32 0, i32 6
  %51 = load volatile i32, ptr %50, align 4, !tbaa !20
  %52 = or i32 %51, %46
  store volatile i32 %52, ptr %50, align 4, !tbaa !20
  br label %153

53:                                               ; preds = %18
  %54 = load i32, ptr %7, align 4, !tbaa !9
  %55 = icmp eq i32 %54, 4
  br i1 %55, label %56, label %87

56:                                               ; preds = %53
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %57, i32 0, i32 0
  %59 = load ptr, ptr %58, align 8, !tbaa !15
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %60, i32 0, i32 0
  %62 = load i32, ptr %61, align 4, !tbaa !16
  %63 = load ptr, ptr %6, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %63, i32 0, i32 1
  %65 = load i32, ptr %64, align 4, !tbaa !18
  %66 = load ptr, ptr %6, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %66, i32 0, i32 3
  %68 = load i32, ptr %67, align 4, !tbaa !19
  call void @TIM_TI2_SetConfig(ptr noundef %59, i32 noundef %62, i32 noundef %65, i32 noundef %68)
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %69, i32 0, i32 0
  %71 = load ptr, ptr %70, align 8, !tbaa !15
  %72 = getelementptr inbounds %struct.TIM_TypeDef, ptr %71, i32 0, i32 6
  %73 = load volatile i32, ptr %72, align 4, !tbaa !20
  %74 = zext i32 %73 to i64
  %75 = and i64 %74, -3073
  %76 = trunc i64 %75 to i32
  store volatile i32 %76, ptr %72, align 4, !tbaa !20
  %77 = load ptr, ptr %6, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %77, i32 0, i32 2
  %79 = load i32, ptr %78, align 4, !tbaa !22
  %80 = shl i32 %79, 8
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !15
  %84 = getelementptr inbounds %struct.TIM_TypeDef, ptr %83, i32 0, i32 6
  %85 = load volatile i32, ptr %84, align 4, !tbaa !20
  %86 = or i32 %85, %80
  store volatile i32 %86, ptr %84, align 4, !tbaa !20
  br label %152

87:                                               ; preds = %53
  %88 = load i32, ptr %7, align 4, !tbaa !9
  %89 = icmp eq i32 %88, 8
  br i1 %89, label %90, label %120

90:                                               ; preds = %87
  %91 = load ptr, ptr %5, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %91, i32 0, i32 0
  %93 = load ptr, ptr %92, align 8, !tbaa !15
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %94, i32 0, i32 0
  %96 = load i32, ptr %95, align 4, !tbaa !16
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %97, i32 0, i32 1
  %99 = load i32, ptr %98, align 4, !tbaa !18
  %100 = load ptr, ptr %6, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %100, i32 0, i32 3
  %102 = load i32, ptr %101, align 4, !tbaa !19
  call void @TIM_TI3_SetConfig(ptr noundef %93, i32 noundef %96, i32 noundef %99, i32 noundef %102)
  %103 = load ptr, ptr %5, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %103, i32 0, i32 0
  %105 = load ptr, ptr %104, align 8, !tbaa !15
  %106 = getelementptr inbounds %struct.TIM_TypeDef, ptr %105, i32 0, i32 7
  %107 = load volatile i32, ptr %106, align 4, !tbaa !23
  %108 = zext i32 %107 to i64
  %109 = and i64 %108, -13
  %110 = trunc i64 %109 to i32
  store volatile i32 %110, ptr %106, align 4, !tbaa !23
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %111, i32 0, i32 2
  %113 = load i32, ptr %112, align 4, !tbaa !22
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %114, i32 0, i32 0
  %116 = load ptr, ptr %115, align 8, !tbaa !15
  %117 = getelementptr inbounds %struct.TIM_TypeDef, ptr %116, i32 0, i32 7
  %118 = load volatile i32, ptr %117, align 4, !tbaa !23
  %119 = or i32 %118, %113
  store volatile i32 %119, ptr %117, align 4, !tbaa !23
  br label %151

120:                                              ; preds = %87
  %121 = load ptr, ptr %5, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %121, i32 0, i32 0
  %123 = load ptr, ptr %122, align 8, !tbaa !15
  %124 = load ptr, ptr %6, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %124, i32 0, i32 0
  %126 = load i32, ptr %125, align 4, !tbaa !16
  %127 = load ptr, ptr %6, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %127, i32 0, i32 1
  %129 = load i32, ptr %128, align 4, !tbaa !18
  %130 = load ptr, ptr %6, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %130, i32 0, i32 3
  %132 = load i32, ptr %131, align 4, !tbaa !19
  call void @TIM_TI4_SetConfig(ptr noundef %123, i32 noundef %126, i32 noundef %129, i32 noundef %132)
  %133 = load ptr, ptr %5, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %133, i32 0, i32 0
  %135 = load ptr, ptr %134, align 8, !tbaa !15
  %136 = getelementptr inbounds %struct.TIM_TypeDef, ptr %135, i32 0, i32 7
  %137 = load volatile i32, ptr %136, align 4, !tbaa !23
  %138 = zext i32 %137 to i64
  %139 = and i64 %138, -3073
  %140 = trunc i64 %139 to i32
  store volatile i32 %140, ptr %136, align 4, !tbaa !23
  %141 = load ptr, ptr %6, align 8, !tbaa !5
  %142 = getelementptr inbounds %struct.TIM_IC_InitTypeDef, ptr %141, i32 0, i32 2
  %143 = load i32, ptr %142, align 4, !tbaa !22
  %144 = shl i32 %143, 8
  %145 = load ptr, ptr %5, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %145, i32 0, i32 0
  %147 = load ptr, ptr %146, align 8, !tbaa !15
  %148 = getelementptr inbounds %struct.TIM_TypeDef, ptr %147, i32 0, i32 7
  %149 = load volatile i32, ptr %148, align 4, !tbaa !23
  %150 = or i32 %149, %144
  store volatile i32 %150, ptr %148, align 4, !tbaa !23
  br label %151

151:                                              ; preds = %120, %90
  br label %152

152:                                              ; preds = %151, %56
  br label %153

153:                                              ; preds = %152, %23
  %154 = load ptr, ptr %5, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %154, i32 0, i32 5
  store volatile i32 1, ptr %155, align 4, !tbaa !14
  br label %156

156:                                              ; preds = %153
  %157 = load ptr, ptr %5, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.TIM_HandleTypeDef, ptr %157, i32 0, i32 4
  store i32 0, ptr %158, align 8, !tbaa !11
  br label %159

159:                                              ; preds = %156
  store i32 0, ptr %4, align 4
  br label %160

160:                                              ; preds = %159, %13
  %161 = load i32, ptr %4, align 4
  ret i32 %161
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI3_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI4_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 96}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 32, !7, i64 40, !10, i64 96, !10, i64 100}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!12, !10, i64 100}
!15 = !{!12, !6, i64 0}
!16 = !{!17, !10, i64 0}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!18 = !{!17, !10, i64 4}
!19 = !{!17, !10, i64 12}
!20 = !{!21, !10, i64 24}
!21 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104}
!22 = !{!17, !10, i64 8}
!23 = !{!21, !10, i64 28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_TIM_IC_ConfigChannel(ptr noundef %0, ptr nocapture noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 96
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i32 %5, 1
  br i1 %6, label %45, label %7

7:                                                ; preds = %3
  store i32 1, ptr %4, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %0, i64 100
  store volatile i32 2, ptr %8, align 4, !tbaa !12
  %9 = load ptr, ptr %0, align 8, !tbaa !13
  %10 = load i32, ptr %1, align 4, !tbaa !14
  %11 = getelementptr inbounds i8, ptr %1, i64 4
  %12 = load i32, ptr %11, align 4, !tbaa !16
  %13 = getelementptr inbounds i8, ptr %1, i64 12
  %14 = load i32, ptr %13, align 4, !tbaa !17
  %15 = getelementptr inbounds i8, ptr %1, i64 8
  switch i32 %2, label %35 [
    i32 0, label %16
    i32 4, label %22
    i32 8, label %29
  ]

16:                                               ; preds = %7
  tail call void @TIM_TI1_SetConfig(ptr noundef %9, i32 noundef %10, i32 noundef %12, i32 noundef %14)
  %17 = load ptr, ptr %0, align 8, !tbaa !13
  %18 = getelementptr inbounds i8, ptr %17, i64 24
  %19 = load volatile i32, ptr %18, align 4, !tbaa !18
  %20 = and i32 %19, -13
  store volatile i32 %20, ptr %18, align 4, !tbaa !18
  %21 = load i32, ptr %15, align 4, !tbaa !20
  br label %42

22:                                               ; preds = %7
  tail call void @TIM_TI2_SetConfig(ptr noundef %9, i32 noundef %10, i32 noundef %12, i32 noundef %14)
  %23 = load ptr, ptr %0, align 8, !tbaa !13
  %24 = getelementptr inbounds i8, ptr %23, i64 24
  %25 = load volatile i32, ptr %24, align 4, !tbaa !18
  %26 = and i32 %25, -3073
  store volatile i32 %26, ptr %24, align 4, !tbaa !18
  %27 = load i32, ptr %15, align 4, !tbaa !20
  %28 = shl i32 %27, 8
  br label %42

29:                                               ; preds = %7
  tail call void @TIM_TI3_SetConfig(ptr noundef %9, i32 noundef %10, i32 noundef %12, i32 noundef %14)
  %30 = load ptr, ptr %0, align 8, !tbaa !13
  %31 = getelementptr inbounds i8, ptr %30, i64 28
  %32 = load volatile i32, ptr %31, align 4, !tbaa !21
  %33 = and i32 %32, -13
  store volatile i32 %33, ptr %31, align 4, !tbaa !21
  %34 = load i32, ptr %15, align 4, !tbaa !20
  br label %42

35:                                               ; preds = %7
  tail call void @TIM_TI4_SetConfig(ptr noundef %9, i32 noundef %10, i32 noundef %12, i32 noundef %14)
  %36 = load ptr, ptr %0, align 8, !tbaa !13
  %37 = getelementptr inbounds i8, ptr %36, i64 28
  %38 = load volatile i32, ptr %37, align 4, !tbaa !21
  %39 = and i32 %38, -3073
  store volatile i32 %39, ptr %37, align 4, !tbaa !21
  %40 = load i32, ptr %15, align 4, !tbaa !20
  %41 = shl i32 %40, 8
  br label %42

42:                                               ; preds = %22, %35, %29, %16
  %.sink = phi ptr [ %24, %22 ], [ %37, %35 ], [ %31, %29 ], [ %18, %16 ]
  %.sink39 = phi i32 [ %28, %22 ], [ %41, %35 ], [ %34, %29 ], [ %21, %16 ]
  %43 = load volatile i32, ptr %.sink, align 4, !tbaa !22
  %44 = or i32 %43, %.sink39
  store volatile i32 %44, ptr %.sink, align 4, !tbaa !22
  store volatile i32 1, ptr %8, align 4, !tbaa !12
  store i32 0, ptr %4, align 8, !tbaa !5
  br label %45

45:                                               ; preds = %3, %42
  %.0 = phi i32 [ 0, %42 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @TIM_TI1_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI2_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI3_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @TIM_TI4_SetConfig(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 96}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 32, !8, i64 40, !11, i64 96, !11, i64 100}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 100}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 0}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!16 = !{!15, !11, i64 4}
!17 = !{!15, !11, i64 12}
!18 = !{!19, !11, i64 24}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !11, i64 100, !11, i64 104}
!20 = !{!15, !11, i64 8}
!21 = !{!19, !11, i64 28}
!22 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass