; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ADC_HandleTypeDef = type { ptr, %struct.ADC_InitTypeDef, ptr, i32, i32, i32, %struct.ADC_InjectionConfigTypeDef }
%struct.ADC_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.ADC_OversamplingTypeDef }
%struct.ADC_OversamplingTypeDef = type { i32, i32, i32, i32 }
%struct.ADC_InjectionConfigTypeDef = type { i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.ADC_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @ADC_Enable(ptr noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Start_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %11, i32 0, i32 0
  %13 = load ptr, ptr %12, align 8, !tbaa !11
  %14 = icmp eq ptr %13, inttoptr (i64 1073881088 to ptr)
  br i1 %14, label %20, label %15

15:                                               ; preds = %3
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %16, i32 0, i32 0
  %18 = load ptr, ptr %17, align 8, !tbaa !11
  %19 = icmp eq ptr %18, inttoptr (i64 1073881344 to ptr)
  br label %20

20:                                               ; preds = %15, %3
  %21 = phi i1 [ true, %3 ], [ %19, %15 ]
  %22 = zext i1 %21 to i64
  %23 = select i1 %21, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %24 = call i32 @LL_ADC_GetMultimode(ptr noundef %23)
  store i32 %24, ptr %9, align 4, !tbaa !9
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !11
  %28 = call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %27)
  %29 = zext i32 %28 to i64
  %30 = icmp eq i64 %29, 0
  br i1 %30, label %31, label %170

31:                                               ; preds = %20
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %33, i32 0, i32 3
  %35 = load i32, ptr %34, align 8, !tbaa !16
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %173

38:                                               ; preds = %32
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %39, i32 0, i32 3
  store i32 1, ptr %40, align 8, !tbaa !16
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load i32, ptr %9, align 4, !tbaa !9
  %45 = zext i32 %44 to i64
  %46 = icmp eq i64 %45, 0
  br i1 %46, label %55, label %47

47:                                               ; preds = %43
  %48 = load i32, ptr %9, align 4, !tbaa !9
  %49 = zext i32 %48 to i64
  %50 = icmp eq i64 %49, 5
  br i1 %50, label %55, label %51

51:                                               ; preds = %47
  %52 = load i32, ptr %9, align 4, !tbaa !9
  %53 = zext i32 %52 to i64
  %54 = icmp eq i64 %53, 9
  br i1 %54, label %55, label %163

55:                                               ; preds = %51, %47, %43
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = call i32 @ADC_Enable(ptr noundef %56)
  store i32 %57, ptr %8, align 4, !tbaa !9
  %58 = load i32, ptr %8, align 4, !tbaa !9
  %59 = icmp eq i32 %58, 0
  br i1 %59, label %60, label %156

60:                                               ; preds = %55
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %61, i32 0, i32 4
  %63 = load volatile i32, ptr %62, align 4, !tbaa !17
  %64 = zext i32 %63 to i64
  %65 = and i64 %64, -3586
  %66 = or i64 %65, 256
  %67 = trunc i64 %66 to i32
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %68, i32 0, i32 4
  store volatile i32 %67, ptr %69, align 4, !tbaa !17
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %70, i32 0, i32 0
  %72 = load ptr, ptr %71, align 8, !tbaa !11
  %73 = icmp eq ptr %72, inttoptr (i64 1073881344 to ptr)
  br i1 %73, label %74, label %75

74:                                               ; preds = %60
  br label %79

75:                                               ; preds = %60
  %76 = load ptr, ptr %5, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %76, i32 0, i32 0
  %78 = load ptr, ptr %77, align 8, !tbaa !11
  br label %79

79:                                               ; preds = %75, %74
  %80 = phi ptr [ inttoptr (i64 1073881088 to ptr), %74 ], [ %78, %75 ]
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %81, i32 0, i32 0
  %83 = load ptr, ptr %82, align 8, !tbaa !11
  %84 = icmp eq ptr %80, %83
  br i1 %84, label %89, label %85

85:                                               ; preds = %79
  %86 = load i32, ptr %9, align 4, !tbaa !9
  %87 = zext i32 %86 to i64
  %88 = icmp eq i64 %87, 0
  br i1 %88, label %89, label %96

89:                                               ; preds = %85, %79
  %90 = load ptr, ptr %5, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %90, i32 0, i32 4
  %92 = load volatile i32, ptr %91, align 4, !tbaa !17
  %93 = zext i32 %92 to i64
  %94 = and i64 %93, -1048577
  %95 = trunc i64 %94 to i32
  store volatile i32 %95, ptr %91, align 4, !tbaa !17
  br label %96

96:                                               ; preds = %89, %85
  %97 = load ptr, ptr %5, align 8, !tbaa !5
  %98 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %97, i32 0, i32 4
  %99 = load volatile i32, ptr %98, align 4, !tbaa !17
  %100 = zext i32 %99 to i64
  %101 = and i64 %100, 4096
  %102 = icmp ne i64 %101, 0
  br i1 %102, label %103, label %108

103:                                              ; preds = %96
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %104, i32 0, i32 5
  %106 = load volatile i32, ptr %105, align 8, !tbaa !18
  %107 = and i32 %106, -7
  store volatile i32 %107, ptr %105, align 8, !tbaa !18
  br label %111

108:                                              ; preds = %96
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %109, i32 0, i32 5
  store volatile i32 0, ptr %110, align 8, !tbaa !18
  br label %111

111:                                              ; preds = %108, %103
  %112 = load ptr, ptr %5, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %112, i32 0, i32 2
  %114 = load ptr, ptr %113, align 8, !tbaa !19
  %115 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %114, i32 0, i32 5
  store ptr @ADC_DMAConvCplt, ptr %115, align 8, !tbaa !20
  %116 = load ptr, ptr %5, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %116, i32 0, i32 2
  %118 = load ptr, ptr %117, align 8, !tbaa !19
  %119 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %118, i32 0, i32 6
  store ptr @ADC_DMAHalfConvCplt, ptr %119, align 8, !tbaa !23
  %120 = load ptr, ptr %5, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %120, i32 0, i32 2
  %122 = load ptr, ptr %121, align 8, !tbaa !19
  %123 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %122, i32 0, i32 9
  store ptr @ADC_DMAError, ptr %123, align 8, !tbaa !24
  %124 = load ptr, ptr %5, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %124, i32 0, i32 0
  %126 = load ptr, ptr %125, align 8, !tbaa !11
  %127 = getelementptr inbounds %struct.ADC_TypeDef, ptr %126, i32 0, i32 0
  store volatile i32 28, ptr %127, align 4, !tbaa !25
  br label %128

128:                                              ; preds = %111
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %129, i32 0, i32 3
  store i32 0, ptr %130, align 8, !tbaa !16
  br label %131

131:                                              ; preds = %128
  br label %132

132:                                              ; preds = %131
  %133 = load ptr, ptr %5, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %133, i32 0, i32 0
  %135 = load ptr, ptr %134, align 8, !tbaa !11
  %136 = getelementptr inbounds %struct.ADC_TypeDef, ptr %135, i32 0, i32 1
  %137 = load volatile i32, ptr %136, align 4, !tbaa !27
  %138 = zext i32 %137 to i64
  %139 = or i64 %138, 16
  %140 = trunc i64 %139 to i32
  store volatile i32 %140, ptr %136, align 4, !tbaa !27
  %141 = load ptr, ptr %5, align 8, !tbaa !5
  %142 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %141, i32 0, i32 2
  %143 = load ptr, ptr %142, align 8, !tbaa !19
  %144 = load ptr, ptr %5, align 8, !tbaa !5
  %145 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %144, i32 0, i32 0
  %146 = load ptr, ptr %145, align 8, !tbaa !11
  %147 = getelementptr inbounds %struct.ADC_TypeDef, ptr %146, i32 0, i32 16
  %148 = ptrtoint ptr %147 to i32
  %149 = load ptr, ptr %6, align 8, !tbaa !5
  %150 = ptrtoint ptr %149 to i32
  %151 = load i32, ptr %7, align 4, !tbaa !9
  %152 = call i32 @HAL_DMA_Start_IT(ptr noundef %143, i32 noundef %148, i32 noundef %150, i32 noundef %151)
  store i32 %152, ptr %8, align 4, !tbaa !9
  %153 = load ptr, ptr %5, align 8, !tbaa !5
  %154 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %153, i32 0, i32 0
  %155 = load ptr, ptr %154, align 8, !tbaa !11
  call void @LL_ADC_REG_StartConversion(ptr noundef %155)
  br label %162

156:                                              ; preds = %55
  br label %157

157:                                              ; preds = %156
  %158 = load ptr, ptr %5, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %158, i32 0, i32 3
  store i32 0, ptr %159, align 8, !tbaa !16
  br label %160

160:                                              ; preds = %157
  br label %161

161:                                              ; preds = %160
  br label %162

162:                                              ; preds = %161, %132
  br label %169

163:                                              ; preds = %51
  store i32 1, ptr %8, align 4, !tbaa !9
  br label %164

164:                                              ; preds = %163
  %165 = load ptr, ptr %5, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.ADC_HandleTypeDef, ptr %165, i32 0, i32 3
  store i32 0, ptr %166, align 8, !tbaa !16
  br label %167

167:                                              ; preds = %164
  br label %168

168:                                              ; preds = %167
  br label %169

169:                                              ; preds = %168, %162
  br label %171

170:                                              ; preds = %20
  store i32 2, ptr %8, align 4, !tbaa !9
  br label %171

171:                                              ; preds = %170, %169
  %172 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %172, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %173

173:                                              ; preds = %171, %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %174 = load i32, ptr %4, align 4
  ret i32 %174
}

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAConvCplt(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAHalfConvCplt(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAError(ptr noundef) #2

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 88, !10, i64 96, !10, i64 100, !10, i64 104, !15, i64 108}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !14, i64 60}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12}
!15 = !{!"", !10, i64 0, !10, i64 4}
!16 = !{!12, !10, i64 96}
!17 = !{!12, !10, i64 100}
!18 = !{!12, !10, i64 104}
!19 = !{!12, !6, i64 88}
!20 = !{!21, !6, i64 72}
!21 = !{!"__DMA_HandleTypeDef", !6, i64 0, !22, i64 8, !10, i64 56, !10, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !10, i64 120, !10, i64 124, !10, i64 128, !6, i64 136, !6, i64 144, !10, i64 152, !6, i64 160, !6, i64 168, !10, i64 176}
!22 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44}
!23 = !{!21, !6, i64 80}
!24 = !{!21, !6, i64 104}
!25 = !{!26, !10, i64 0}
!26 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !7, i64 80, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !7, i64 112, !10, i64 128, !10, i64 132, !10, i64 136, !10, i64 140, !7, i64 144, !10, i64 160, !10, i64 164, !10, i64 168, !10, i64 172, !10, i64 176, !10, i64 180, !10, i64 184, !10, i64 188, !10, i64 192, !10, i64 196, !10, i64 200}
!27 = !{!26, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @LL_ADC_GetMultimode(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @ADC_Enable(ptr noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @LL_ADC_REG_StartConversion(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_ADC_Start_DMA(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #1 {
  %4 = load ptr, ptr %0, align 8, !tbaa !5
  %5 = icmp eq ptr %4, inttoptr (i64 1073881088 to ptr)
  %6 = icmp eq ptr %4, inttoptr (i64 1073881344 to ptr)
  %spec.select = or i1 %5, %6
  %7 = select i1 %spec.select, ptr inttoptr (i64 1073881856 to ptr), ptr inttoptr (i64 1476551424 to ptr)
  %8 = tail call i32 @LL_ADC_GetMultimode(ptr noundef nonnull %7)
  %9 = load ptr, ptr %0, align 8, !tbaa !5
  %10 = tail call i32 @LL_ADC_REG_IsConversionOngoing(ptr noundef %9)
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %56

12:                                               ; preds = %3
  %13 = getelementptr inbounds i8, ptr %0, i64 96
  %14 = load i32, ptr %13, align 8, !tbaa !14
  %15 = icmp eq i32 %14, 1
  br i1 %15, label %56, label %16

16:                                               ; preds = %12
  store i32 1, ptr %13, align 8, !tbaa !14
  %17 = icmp eq i32 %8, 0
  switch i32 %8, label %55 [
    i32 9, label %18
    i32 5, label %18
    i32 0, label %18
  ]

18:                                               ; preds = %16, %16, %16
  %19 = tail call i32 @ADC_Enable(ptr noundef nonnull %0)
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %54

21:                                               ; preds = %18
  %22 = getelementptr inbounds i8, ptr %0, i64 100
  %23 = load volatile i32, ptr %22, align 4, !tbaa !15
  %24 = and i32 %23, -3842
  %25 = or disjoint i32 %24, 256
  store volatile i32 %25, ptr %22, align 4, !tbaa !15
  %26 = load ptr, ptr %0, align 8, !tbaa !5
  %27 = icmp ne ptr %26, inttoptr (i64 1073881344 to ptr)
  %or.cond8 = or i1 %17, %27
  br i1 %or.cond8, label %28, label %31

28:                                               ; preds = %21
  %29 = load volatile i32, ptr %22, align 4, !tbaa !15
  %30 = and i32 %29, -1048577
  store volatile i32 %30, ptr %22, align 4, !tbaa !15
  br label %31

31:                                               ; preds = %21, %28
  %32 = load volatile i32, ptr %22, align 4, !tbaa !15
  %33 = and i32 %32, 4096
  %.not = icmp eq i32 %33, 0
  %34 = getelementptr inbounds i8, ptr %0, i64 104
  br i1 %.not, label %38, label %35

35:                                               ; preds = %31
  %36 = load volatile i32, ptr %34, align 8, !tbaa !16
  %37 = and i32 %36, -7
  br label %38

38:                                               ; preds = %31, %35
  %.sink = phi i32 [ %37, %35 ], [ 0, %31 ]
  store volatile i32 %.sink, ptr %34, align 8, !tbaa !16
  %39 = getelementptr inbounds i8, ptr %0, i64 88
  %40 = load ptr, ptr %39, align 8, !tbaa !17
  %41 = getelementptr inbounds i8, ptr %40, i64 72
  store ptr @ADC_DMAConvCplt, ptr %41, align 8, !tbaa !18
  %42 = getelementptr inbounds i8, ptr %40, i64 80
  store ptr @ADC_DMAHalfConvCplt, ptr %42, align 8, !tbaa !21
  %43 = getelementptr inbounds i8, ptr %40, i64 104
  store ptr @ADC_DMAError, ptr %43, align 8, !tbaa !22
  store volatile i32 28, ptr %26, align 4, !tbaa !23
  store i32 0, ptr %13, align 8, !tbaa !14
  %44 = getelementptr inbounds i8, ptr %26, i64 4
  %45 = load volatile i32, ptr %44, align 4, !tbaa !25
  %46 = or i32 %45, 16
  store volatile i32 %46, ptr %44, align 4, !tbaa !25
  %47 = getelementptr inbounds i8, ptr %26, i64 64
  %48 = ptrtoint ptr %47 to i64
  %49 = trunc i64 %48 to i32
  %50 = ptrtoint ptr %1 to i64
  %51 = trunc i64 %50 to i32
  %52 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %40, i32 noundef %49, i32 noundef %51, i32 noundef %2) #3
  %53 = load ptr, ptr %0, align 8, !tbaa !5
  tail call void @LL_ADC_REG_StartConversion(ptr noundef %53)
  br label %56

54:                                               ; preds = %18
  store i32 0, ptr %13, align 8, !tbaa !14
  br label %56

55:                                               ; preds = %16
  store i32 0, ptr %13, align 8, !tbaa !14
  br label %56

56:                                               ; preds = %38, %54, %55, %3, %12
  %.0 = phi i32 [ 2, %12 ], [ %52, %38 ], [ %19, %54 ], [ 1, %55 ], [ 2, %3 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAConvCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAHalfConvCplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @ADC_DMAError(ptr noundef) #1

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 88, !11, i64 96, !11, i64 100, !11, i64 104, !13, i64 108}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !12, i64 60}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!13 = !{!"", !11, i64 0, !11, i64 4}
!14 = !{!6, !11, i64 96}
!15 = !{!6, !11, i64 100}
!16 = !{!6, !11, i64 104}
!17 = !{!6, !7, i64 88}
!18 = !{!19, !7, i64 72}
!19 = !{!"__DMA_HandleTypeDef", !7, i64 0, !20, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!20 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!21 = !{!19, !7, i64 80}
!22 = !{!19, !7, i64 104}
!23 = !{!24, !11, i64 0}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !11, i64 96, !11, i64 100, !11, i64 104, !11, i64 108, !8, i64 112, !11, i64 128, !11, i64 132, !11, i64 136, !11, i64 140, !8, i64 144, !11, i64 160, !11, i64 164, !11, i64 168, !11, i64 172, !11, i64 176, !11, i64 180, !11, i64 184, !11, i64 188, !11, i64 192, !11, i64 196, !11, i64 200}
!25 = !{!24, !11, i64 4}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass