; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (8b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.NAND_HandleTypeDef = type { ptr, %struct.FMC_NAND_InitTypeDef, i32, i32, %struct.NAND_DeviceConfigTypeDef }
%struct.FMC_NAND_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_DeviceConfigTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.NAND_AddressTypeDef = type { i16, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @HAL_GetTick() #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_NAND_Write_Page_8b(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  %18 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %18, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %19, ptr %16, align 8, !tbaa !5
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %20, i32 0, i32 3
  %22 = load volatile i32, ptr %21, align 8, !tbaa !11
  %23 = icmp eq i32 %22, 2
  br i1 %23, label %24, label %25

24:                                               ; preds = %4
  store i32 2, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %279

25:                                               ; preds = %4
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %26, i32 0, i32 3
  %28 = load volatile i32, ptr %27, align 8, !tbaa !11
  %29 = icmp eq i32 %28, 1
  br i1 %29, label %30, label %276

30:                                               ; preds = %25
  br label %31

31:                                               ; preds = %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %32, i32 0, i32 2
  %34 = load i32, ptr %33, align 4, !tbaa !14
  %35 = icmp eq i32 %34, 1
  br i1 %35, label %36, label %37

36:                                               ; preds = %31
  store i32 2, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %279

37:                                               ; preds = %31
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %38, i32 0, i32 2
  store i32 1, ptr %39, align 4, !tbaa !14
  br label %40

40:                                               ; preds = %37
  br label %41

41:                                               ; preds = %40
  br label %42

42:                                               ; preds = %41
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %43, i32 0, i32 3
  store volatile i32 2, ptr %44, align 8, !tbaa !11
  store i32 -2147483648, ptr %12, align 4, !tbaa !9
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %45, i32 0, i32 0
  %47 = load i16, ptr %46, align 2, !tbaa !15
  %48 = zext i16 %47 to i32
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %49, i32 0, i32 2
  %51 = load i16, ptr %50, align 2, !tbaa !18
  %52 = zext i16 %51 to i32
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.NAND_AddressTypeDef, ptr %53, i32 0, i32 1
  %55 = load i16, ptr %54, align 2, !tbaa !19
  %56 = zext i16 %55 to i32
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %57, i32 0, i32 4
  %59 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %58, i32 0, i32 5
  %60 = load i32, ptr %59, align 4, !tbaa !20
  %61 = mul i32 %56, %60
  %62 = add i32 %52, %61
  %63 = load ptr, ptr %6, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %63, i32 0, i32 4
  %65 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %64, i32 0, i32 2
  %66 = load i32, ptr %65, align 4, !tbaa !21
  %67 = mul i32 %62, %66
  %68 = add i32 %48, %67
  store i32 %68, ptr %14, align 4, !tbaa !9
  br label %69

69:                                               ; preds = %261, %42
  %70 = load i32, ptr %15, align 4, !tbaa !9
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %84

72:                                               ; preds = %69
  %73 = load i32, ptr %14, align 4, !tbaa !9
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %74, i32 0, i32 4
  %76 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %75, i32 0, i32 2
  %77 = load i32, ptr %76, align 4, !tbaa !21
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %78, i32 0, i32 4
  %80 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %79, i32 0, i32 3
  %81 = load i32, ptr %80, align 4, !tbaa !22
  %82 = mul i32 %77, %81
  %83 = icmp ult i32 %73, %82
  br label %84

84:                                               ; preds = %72, %69
  %85 = phi i1 [ false, %69 ], [ %83, %72 ]
  br i1 %85, label %86, label %268

86:                                               ; preds = %84
  %87 = load i32, ptr %12, align 4, !tbaa !9
  %88 = or i32 %87, 65536
  %89 = zext i32 %88 to i64
  %90 = inttoptr i64 %89 to ptr
  store volatile i8 0, ptr %90, align 1, !tbaa !23
  call void @__DSB()
  %91 = load i32, ptr %12, align 4, !tbaa !9
  %92 = or i32 %91, 65536
  %93 = zext i32 %92 to i64
  %94 = inttoptr i64 %93 to ptr
  store volatile i8 -128, ptr %94, align 1, !tbaa !23
  call void @__DSB()
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %95, i32 0, i32 4
  %97 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %96, i32 0, i32 0
  %98 = load i32, ptr %97, align 4, !tbaa !24
  %99 = icmp ule i32 %98, 512
  br i1 %99, label %100, label %155

100:                                              ; preds = %86
  %101 = load ptr, ptr %6, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %101, i32 0, i32 4
  %103 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %102, i32 0, i32 2
  %104 = load i32, ptr %103, align 4, !tbaa !21
  %105 = load ptr, ptr %6, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %105, i32 0, i32 4
  %107 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %106, i32 0, i32 3
  %108 = load i32, ptr %107, align 4, !tbaa !22
  %109 = mul i32 %104, %108
  %110 = icmp ule i32 %109, 65535
  br i1 %110, label %111, label %129

111:                                              ; preds = %100
  %112 = load i32, ptr %12, align 4, !tbaa !9
  %113 = or i32 %112, 131072
  %114 = zext i32 %113 to i64
  %115 = inttoptr i64 %114 to ptr
  store volatile i8 0, ptr %115, align 1, !tbaa !23
  call void @__DSB()
  %116 = load i32, ptr %14, align 4, !tbaa !9
  %117 = trunc i32 %116 to i8
  %118 = load i32, ptr %12, align 4, !tbaa !9
  %119 = or i32 %118, 131072
  %120 = zext i32 %119 to i64
  %121 = inttoptr i64 %120 to ptr
  store volatile i8 %117, ptr %121, align 1, !tbaa !23
  call void @__DSB()
  %122 = load i32, ptr %14, align 4, !tbaa !9
  %123 = lshr i32 %122, 8
  %124 = trunc i32 %123 to i8
  %125 = load i32, ptr %12, align 4, !tbaa !9
  %126 = or i32 %125, 131072
  %127 = zext i32 %126 to i64
  %128 = inttoptr i64 %127 to ptr
  store volatile i8 %124, ptr %128, align 1, !tbaa !23
  call void @__DSB()
  br label %154

129:                                              ; preds = %100
  %130 = load i32, ptr %12, align 4, !tbaa !9
  %131 = or i32 %130, 131072
  %132 = zext i32 %131 to i64
  %133 = inttoptr i64 %132 to ptr
  store volatile i8 0, ptr %133, align 1, !tbaa !23
  call void @__DSB()
  %134 = load i32, ptr %14, align 4, !tbaa !9
  %135 = trunc i32 %134 to i8
  %136 = load i32, ptr %12, align 4, !tbaa !9
  %137 = or i32 %136, 131072
  %138 = zext i32 %137 to i64
  %139 = inttoptr i64 %138 to ptr
  store volatile i8 %135, ptr %139, align 1, !tbaa !23
  call void @__DSB()
  %140 = load i32, ptr %14, align 4, !tbaa !9
  %141 = lshr i32 %140, 8
  %142 = trunc i32 %141 to i8
  %143 = load i32, ptr %12, align 4, !tbaa !9
  %144 = or i32 %143, 131072
  %145 = zext i32 %144 to i64
  %146 = inttoptr i64 %145 to ptr
  store volatile i8 %142, ptr %146, align 1, !tbaa !23
  call void @__DSB()
  %147 = load i32, ptr %14, align 4, !tbaa !9
  %148 = lshr i32 %147, 16
  %149 = trunc i32 %148 to i8
  %150 = load i32, ptr %12, align 4, !tbaa !9
  %151 = or i32 %150, 131072
  %152 = zext i32 %151 to i64
  %153 = inttoptr i64 %152 to ptr
  store volatile i8 %149, ptr %153, align 1, !tbaa !23
  call void @__DSB()
  br label %154

154:                                              ; preds = %129, %111
  br label %218

155:                                              ; preds = %86
  %156 = load ptr, ptr %6, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %156, i32 0, i32 4
  %158 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %157, i32 0, i32 2
  %159 = load i32, ptr %158, align 4, !tbaa !21
  %160 = load ptr, ptr %6, align 8, !tbaa !5
  %161 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %160, i32 0, i32 4
  %162 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %161, i32 0, i32 3
  %163 = load i32, ptr %162, align 4, !tbaa !22
  %164 = mul i32 %159, %163
  %165 = icmp ule i32 %164, 65535
  br i1 %165, label %166, label %188

166:                                              ; preds = %155
  %167 = load i32, ptr %12, align 4, !tbaa !9
  %168 = or i32 %167, 131072
  %169 = zext i32 %168 to i64
  %170 = inttoptr i64 %169 to ptr
  store volatile i8 0, ptr %170, align 1, !tbaa !23
  call void @__DSB()
  %171 = load i32, ptr %12, align 4, !tbaa !9
  %172 = or i32 %171, 131072
  %173 = zext i32 %172 to i64
  %174 = inttoptr i64 %173 to ptr
  store volatile i8 0, ptr %174, align 1, !tbaa !23
  call void @__DSB()
  %175 = load i32, ptr %14, align 4, !tbaa !9
  %176 = trunc i32 %175 to i8
  %177 = load i32, ptr %12, align 4, !tbaa !9
  %178 = or i32 %177, 131072
  %179 = zext i32 %178 to i64
  %180 = inttoptr i64 %179 to ptr
  store volatile i8 %176, ptr %180, align 1, !tbaa !23
  call void @__DSB()
  %181 = load i32, ptr %14, align 4, !tbaa !9
  %182 = lshr i32 %181, 8
  %183 = trunc i32 %182 to i8
  %184 = load i32, ptr %12, align 4, !tbaa !9
  %185 = or i32 %184, 131072
  %186 = zext i32 %185 to i64
  %187 = inttoptr i64 %186 to ptr
  store volatile i8 %183, ptr %187, align 1, !tbaa !23
  call void @__DSB()
  br label %217

188:                                              ; preds = %155
  %189 = load i32, ptr %12, align 4, !tbaa !9
  %190 = or i32 %189, 131072
  %191 = zext i32 %190 to i64
  %192 = inttoptr i64 %191 to ptr
  store volatile i8 0, ptr %192, align 1, !tbaa !23
  call void @__DSB()
  %193 = load i32, ptr %12, align 4, !tbaa !9
  %194 = or i32 %193, 131072
  %195 = zext i32 %194 to i64
  %196 = inttoptr i64 %195 to ptr
  store volatile i8 0, ptr %196, align 1, !tbaa !23
  call void @__DSB()
  %197 = load i32, ptr %14, align 4, !tbaa !9
  %198 = trunc i32 %197 to i8
  %199 = load i32, ptr %12, align 4, !tbaa !9
  %200 = or i32 %199, 131072
  %201 = zext i32 %200 to i64
  %202 = inttoptr i64 %201 to ptr
  store volatile i8 %198, ptr %202, align 1, !tbaa !23
  call void @__DSB()
  %203 = load i32, ptr %14, align 4, !tbaa !9
  %204 = lshr i32 %203, 8
  %205 = trunc i32 %204 to i8
  %206 = load i32, ptr %12, align 4, !tbaa !9
  %207 = or i32 %206, 131072
  %208 = zext i32 %207 to i64
  %209 = inttoptr i64 %208 to ptr
  store volatile i8 %205, ptr %209, align 1, !tbaa !23
  call void @__DSB()
  %210 = load i32, ptr %14, align 4, !tbaa !9
  %211 = lshr i32 %210, 16
  %212 = trunc i32 %211 to i8
  %213 = load i32, ptr %12, align 4, !tbaa !9
  %214 = or i32 %213, 131072
  %215 = zext i32 %214 to i64
  %216 = inttoptr i64 %215 to ptr
  store volatile i8 %212, ptr %216, align 1, !tbaa !23
  call void @__DSB()
  br label %217

217:                                              ; preds = %188, %166
  br label %218

218:                                              ; preds = %217, %154
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %219

219:                                              ; preds = %234, %218
  %220 = load i32, ptr %10, align 4, !tbaa !9
  %221 = load ptr, ptr %6, align 8, !tbaa !5
  %222 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %221, i32 0, i32 4
  %223 = getelementptr inbounds %struct.NAND_DeviceConfigTypeDef, ptr %222, i32 0, i32 0
  %224 = load i32, ptr %223, align 4, !tbaa !24
  %225 = icmp ult i32 %220, %224
  br i1 %225, label %226, label %237

226:                                              ; preds = %219
  %227 = load ptr, ptr %16, align 8, !tbaa !5
  %228 = load i8, ptr %227, align 1, !tbaa !23
  %229 = load i32, ptr %12, align 4, !tbaa !9
  %230 = zext i32 %229 to i64
  %231 = inttoptr i64 %230 to ptr
  store volatile i8 %228, ptr %231, align 1, !tbaa !23
  %232 = load ptr, ptr %16, align 8, !tbaa !5
  %233 = getelementptr inbounds i8, ptr %232, i32 1
  store ptr %233, ptr %16, align 8, !tbaa !5
  call void @__DSB()
  br label %234

234:                                              ; preds = %226
  %235 = load i32, ptr %10, align 4, !tbaa !9
  %236 = add i32 %235, 1
  store i32 %236, ptr %10, align 4, !tbaa !9
  br label %219, !llvm.loop !25

237:                                              ; preds = %219
  %238 = load i32, ptr %12, align 4, !tbaa !9
  %239 = or i32 %238, 65536
  %240 = zext i32 %239 to i64
  %241 = inttoptr i64 %240 to ptr
  store volatile i8 16, ptr %241, align 1, !tbaa !23
  call void @__DSB()
  %242 = call i32 @HAL_GetTick()
  store i32 %242, ptr %11, align 4, !tbaa !9
  br label %243

243:                                              ; preds = %260, %237
  %244 = load ptr, ptr %6, align 8, !tbaa !5
  %245 = call i32 @HAL_NAND_Read_Status(ptr noundef %244)
  %246 = icmp ne i32 %245, 64
  br i1 %246, label %247, label %261

247:                                              ; preds = %243
  %248 = call i32 @HAL_GetTick()
  %249 = load i32, ptr %11, align 4, !tbaa !9
  %250 = sub i32 %248, %249
  %251 = icmp ugt i32 %250, 16777216
  br i1 %251, label %252, label %260

252:                                              ; preds = %247
  %253 = load ptr, ptr %6, align 8, !tbaa !5
  %254 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %253, i32 0, i32 3
  store volatile i32 3, ptr %254, align 8, !tbaa !11
  br label %255

255:                                              ; preds = %252
  %256 = load ptr, ptr %6, align 8, !tbaa !5
  %257 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %256, i32 0, i32 2
  store i32 0, ptr %257, align 4, !tbaa !14
  br label %258

258:                                              ; preds = %255
  br label %259

259:                                              ; preds = %258
  store i32 3, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %279

260:                                              ; preds = %247
  br label %243, !llvm.loop !27

261:                                              ; preds = %243
  %262 = load i32, ptr %13, align 4, !tbaa !9
  %263 = add i32 %262, 1
  store i32 %263, ptr %13, align 4, !tbaa !9
  %264 = load i32, ptr %15, align 4, !tbaa !9
  %265 = add i32 %264, -1
  store i32 %265, ptr %15, align 4, !tbaa !9
  %266 = load i32, ptr %14, align 4, !tbaa !9
  %267 = add i32 %266, 1
  store i32 %267, ptr %14, align 4, !tbaa !9
  br label %69, !llvm.loop !28

268:                                              ; preds = %84
  %269 = load ptr, ptr %6, align 8, !tbaa !5
  %270 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %269, i32 0, i32 3
  store volatile i32 1, ptr %270, align 8, !tbaa !11
  br label %271

271:                                              ; preds = %268
  %272 = load ptr, ptr %6, align 8, !tbaa !5
  %273 = getelementptr inbounds %struct.NAND_HandleTypeDef, ptr %272, i32 0, i32 2
  store i32 0, ptr %273, align 4, !tbaa !14
  br label %274

274:                                              ; preds = %271
  br label %275

275:                                              ; preds = %274
  br label %277

276:                                              ; preds = %25
  store i32 1, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %279

277:                                              ; preds = %275
  br label %278

278:                                              ; preds = %277
  store i32 0, ptr %5, align 4
  store i32 1, ptr %17, align 4
  br label %279

279:                                              ; preds = %278, %276, %259, %36, %24
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %280 = load i32, ptr %5, align 4
  ret i32 %280
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"", !6, i64 0, !13, i64 8, !10, i64 36, !10, i64 40, !13, i64 44}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24}
!14 = !{!12, !10, i64 36}
!15 = !{!16, !17, i64 0}
!16 = !{!"", !17, i64 0, !17, i64 2, !17, i64 4}
!17 = !{!"short", !7, i64 0}
!18 = !{!16, !17, i64 4}
!19 = !{!16, !17, i64 2}
!20 = !{!12, !10, i64 64}
!21 = !{!12, !10, i64 52}
!22 = !{!12, !10, i64 56}
!23 = !{!7, !7, i64 0}
!24 = !{!12, !10, i64 44}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = distinct !{!27, !26}
!28 = distinct !{!28, !26}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @__DSB() local_unnamed_addr #0

declare i32 @HAL_GetTick() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_NAND_Read_Status(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @HAL_NAND_Write_Page_8b(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, i32 noundef %3) local_unnamed_addr #2 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 2
  br i1 %7, label %73, label %8

8:                                                ; preds = %4
  %9 = load volatile i32, ptr %5, align 8, !tbaa !5
  %10 = icmp eq i32 %9, 1
  br i1 %10, label %11, label %73

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !12
  %14 = icmp eq i32 %13, 1
  br i1 %14, label %73, label %15

15:                                               ; preds = %11
  store i32 1, ptr %12, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 44
  %17 = getelementptr inbounds i8, ptr %0, i64 52
  %.not73 = icmp eq i32 %3, 0
  br i1 %.not73, label %.sink.split82, label %.lr.ph78

.lr.ph78:                                         ; preds = %15
  %18 = getelementptr inbounds i8, ptr %0, i64 64
  %19 = load i32, ptr %18, align 4, !tbaa !13
  %20 = getelementptr inbounds i8, ptr %1, i64 2
  %21 = load i16, ptr %20, align 2, !tbaa !14
  %22 = zext i16 %21 to i32
  %23 = mul i32 %19, %22
  %24 = getelementptr inbounds i8, ptr %1, i64 4
  %25 = load i16, ptr %24, align 2, !tbaa !17
  %26 = zext i16 %25 to i32
  %27 = add i32 %23, %26
  %28 = load i32, ptr %17, align 4, !tbaa !18
  %29 = mul i32 %27, %28
  %30 = load i16, ptr %1, align 2, !tbaa !19
  %31 = zext i16 %30 to i32
  %32 = add i32 %29, %31
  %33 = getelementptr inbounds i8, ptr %0, i64 56
  br label %34

34:                                               ; preds = %.lr.ph78, %70
  %.076 = phi ptr [ %2, %.lr.ph78 ], [ %.1.lcssa, %70 ]
  %.06575 = phi i32 [ %3, %.lr.ph78 ], [ %71, %70 ]
  %.06674 = phi i32 [ %32, %.lr.ph78 ], [ %72, %70 ]
  %35 = load i32, ptr %17, align 4, !tbaa !18
  %36 = load i32, ptr %33, align 4, !tbaa !20
  %37 = mul i32 %36, %35
  %38 = icmp ult i32 %.06674, %37
  br i1 %38, label %39, label %.sink.split82

39:                                               ; preds = %34
  store volatile i8 0, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  store volatile i8 -128, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  %40 = load i32, ptr %16, align 4, !tbaa !22
  %41 = icmp ult i32 %40, 513
  %42 = load i32, ptr %17, align 4, !tbaa !18
  %43 = load i32, ptr %33, align 4, !tbaa !20
  %44 = mul i32 %43, %42
  %45 = icmp ult i32 %44, 65536
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %41, label %46, label %50

46:                                               ; preds = %39
  %47 = trunc i32 %.06674 to i8
  store volatile i8 %47, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %48 = lshr i32 %.06674, 8
  %49 = trunc i32 %48 to i8
  store volatile i8 %49, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %45, label %56, label %.sink.split

50:                                               ; preds = %39
  store volatile i8 0, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %51 = trunc i32 %.06674 to i8
  store volatile i8 %51, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  %52 = lshr i32 %.06674, 8
  %53 = trunc i32 %52 to i8
  store volatile i8 %53, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br i1 %45, label %56, label %.sink.split

.sink.split:                                      ; preds = %50, %46
  %54 = lshr i32 %.06674, 16
  %55 = trunc i32 %54 to i8
  store volatile i8 %55, ptr inttoptr (i64 2147614720 to ptr), align 131072, !tbaa !21
  tail call void @__DSB()
  br label %56

56:                                               ; preds = %.sink.split, %50, %46
  %57 = load i32, ptr %16, align 4, !tbaa !22
  %.not80 = icmp eq i32 %57, 0
  br i1 %.not80, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %56, %.lr.ph
  %.172 = phi ptr [ %59, %.lr.ph ], [ %.076, %56 ]
  %.06971 = phi i32 [ %60, %.lr.ph ], [ 0, %56 ]
  %58 = load i8, ptr %.172, align 1, !tbaa !21
  store volatile i8 %58, ptr inttoptr (i64 2147483648 to ptr), align 2147483648, !tbaa !21
  %59 = getelementptr inbounds i8, ptr %.172, i64 1
  tail call void @__DSB()
  %60 = add nuw i32 %.06971, 1
  %61 = load i32, ptr %16, align 4, !tbaa !22
  %62 = icmp ult i32 %60, %61
  br i1 %62, label %.lr.ph, label %._crit_edge, !llvm.loop !23

._crit_edge:                                      ; preds = %.lr.ph, %56
  %.1.lcssa = phi ptr [ %.076, %56 ], [ %59, %.lr.ph ]
  store volatile i8 16, ptr inttoptr (i64 2147549184 to ptr), align 65536, !tbaa !21
  tail call void @__DSB()
  %63 = tail call i32 @HAL_GetTick() #3
  br label %64

64:                                               ; preds = %66, %._crit_edge
  %65 = tail call i32 @HAL_NAND_Read_Status(ptr noundef %0)
  %.not70 = icmp eq i32 %65, 64
  br i1 %.not70, label %70, label %66

66:                                               ; preds = %64
  %67 = tail call i32 @HAL_GetTick() #3
  %68 = sub i32 %67, %63
  %69 = icmp ugt i32 %68, 16777216
  br i1 %69, label %.sink.split82, label %64, !llvm.loop !25

70:                                               ; preds = %64
  %71 = add i32 %.06575, -1
  %72 = add i32 %.06674, 1
  %.not = icmp eq i32 %71, 0
  br i1 %.not, label %.sink.split82, label %34, !llvm.loop !26

.sink.split82:                                    ; preds = %70, %34, %66, %15
  %.sink = phi i32 [ 1, %15 ], [ 3, %66 ], [ 1, %34 ], [ 1, %70 ]
  %.068.ph = phi i32 [ 0, %15 ], [ 3, %66 ], [ 0, %34 ], [ 0, %70 ]
  store volatile i32 %.sink, ptr %5, align 8, !tbaa !5
  store i32 0, ptr %12, align 4, !tbaa !12
  br label %73

73:                                               ; preds = %.sink.split82, %8, %11, %4
  %.068 = phi i32 [ 2, %4 ], [ 2, %11 ], [ 1, %8 ], [ %.068.ph, %.sink.split82 ]
  ret i32 %.068
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 40}
!6 = !{!"", !7, i64 0, !10, i64 8, !11, i64 36, !11, i64 40, !10, i64 44}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 36}
!13 = !{!6, !11, i64 64}
!14 = !{!15, !16, i64 2}
!15 = !{!"", !16, i64 0, !16, i64 2, !16, i64 4}
!16 = !{!"short", !8, i64 0}
!17 = !{!15, !16, i64 4}
!18 = !{!6, !11, i64 52}
!19 = !{!15, !16, i64 0}
!20 = !{!6, !11, i64 56}
!21 = !{!8, !8, i64 0}
!22 = !{!6, !11, i64 44}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = distinct !{!25, !24}
!26 = distinct !{!26, !24}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass