; LLVM IR from Seeed-Studio/Seeed_Arduino_edgeimpulse :: src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions (shift)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_q7_to_q15_reordered_no_shift(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %12, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %13 = load i32, ptr %6, align 4, !tbaa !9
  %14 = lshr i32 %13, 2
  store i32 %14, ptr %8, align 4, !tbaa !9
  br label %15

15:                                               ; preds = %18, %3
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = icmp ugt i32 %16, 0
  br i1 %17, label %18, label %33

18:                                               ; preds = %15
  %19 = call i32 @arm_nn_read_q7x4_ia(ptr noundef %7)
  store i32 %19, ptr %9, align 4, !tbaa !9
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = call i32 @__ROR(i32 noundef %20, i32 noundef 8)
  %22 = call i32 @__SXTB16(i32 noundef %21)
  store i32 %22, ptr %10, align 4, !tbaa !9
  %23 = load i32, ptr %9, align 4, !tbaa !9
  %24 = call i32 @__SXTB16(i32 noundef %23)
  store i32 %24, ptr %11, align 4, !tbaa !9
  %25 = load i32, ptr %11, align 4, !tbaa !9
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = getelementptr inbounds i32, ptr %26, i32 1
  store ptr %27, ptr %5, align 8, !tbaa !5
  store i32 %25, ptr %26, align 4, !tbaa !9
  %28 = load i32, ptr %10, align 4, !tbaa !9
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds i32, ptr %29, i32 1
  store ptr %30, ptr %5, align 8, !tbaa !5
  store i32 %28, ptr %29, align 4, !tbaa !9
  %31 = load i32, ptr %8, align 4, !tbaa !9
  %32 = add i32 %31, -1
  store i32 %32, ptr %8, align 4, !tbaa !9
  br label %15, !llvm.loop !11

33:                                               ; preds = %15
  %34 = load i32, ptr %6, align 4, !tbaa !9
  %35 = urem i32 %34, 4
  store i32 %35, ptr %8, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %39, %33
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = icmp ugt i32 %37, 0
  br i1 %38, label %39, label %48

39:                                               ; preds = %36
  %40 = load ptr, ptr %7, align 8, !tbaa !5
  %41 = getelementptr inbounds i8, ptr %40, i32 1
  store ptr %41, ptr %7, align 8, !tbaa !5
  %42 = load i8, ptr %40, align 1, !tbaa !13
  %43 = sext i8 %42 to i16
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds i16, ptr %44, i32 1
  store ptr %45, ptr %5, align 8, !tbaa !5
  store i16 %43, ptr %44, align 2, !tbaa !14
  %46 = load i32, ptr %8, align 4, !tbaa !9
  %47 = add i32 %46, -1
  store i32 %47, ptr %8, align 4, !tbaa !9
  br label %36, !llvm.loop !16

48:                                               ; preds = %36
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q7x4_ia(ptr noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SXTB16(i32 noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__ROR(i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"short", !7, i64 0}
!16 = distinct !{!16, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_q7_to_q15_reordered_no_shift(ptr noundef %0, ptr nocapture noundef writeonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = alloca ptr, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #3
  store ptr %0, ptr %4, align 8, !tbaa !5
  %.not16 = icmp ult i32 %2, 4
  br i1 %.not16, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %3
  %5 = lshr i32 %2, 2
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %.018 = phi ptr [ %11, %.lr.ph ], [ %1, %.lr.ph.preheader ]
  %.01317 = phi i32 [ %12, %.lr.ph ], [ %5, %.lr.ph.preheader ]
  %6 = call i32 @arm_nn_read_q7x4_ia(ptr noundef nonnull %4)
  %7 = call i32 @__ROR(i32 noundef %6, i32 noundef 8)
  %8 = call i32 @__SXTB16(i32 noundef %7)
  %9 = call i32 @__SXTB16(i32 noundef %6)
  %10 = getelementptr inbounds i8, ptr %.018, i64 4
  store i32 %9, ptr %.018, align 4, !tbaa !9
  %11 = getelementptr inbounds i8, ptr %.018, i64 8
  store i32 %8, ptr %10, align 4, !tbaa !9
  %12 = add nsw i32 %.01317, -1
  %.not = icmp eq i32 %12, 0
  br i1 %.not, label %._crit_edge.loopexit, label %.lr.ph, !llvm.loop !11

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %.promoted.pre = load ptr, ptr %4, align 8, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %3
  %.promoted = phi ptr [ %0, %3 ], [ %.promoted.pre, %._crit_edge.loopexit ]
  %.0.lcssa = phi ptr [ %1, %3 ], [ %11, %._crit_edge.loopexit ]
  %13 = and i32 %2, 3
  %.not1519 = icmp eq i32 %13, 0
  br i1 %.not1519, label %._crit_edge24, label %.lr.ph23

.lr.ph23:                                         ; preds = %._crit_edge
  %14 = getelementptr inbounds i8, ptr %.promoted, i64 1
  store ptr %14, ptr %4, align 8, !tbaa !5
  %15 = load i8, ptr %.promoted, align 1, !tbaa !13
  %16 = sext i8 %15 to i16
  store i16 %16, ptr %.0.lcssa, align 2, !tbaa !14
  %.not15 = icmp eq i32 %13, 1
  br i1 %.not15, label %._crit_edge24, label %.lr.ph23.1, !llvm.loop !16

.lr.ph23.1:                                       ; preds = %.lr.ph23
  %17 = getelementptr inbounds i8, ptr %.0.lcssa, i64 2
  %18 = getelementptr inbounds i8, ptr %.promoted, i64 2
  store ptr %18, ptr %4, align 8, !tbaa !5
  %19 = load i8, ptr %14, align 1, !tbaa !13
  %20 = sext i8 %19 to i16
  store i16 %20, ptr %17, align 2, !tbaa !14
  %.not15.1 = icmp eq i32 %13, 2
  br i1 %.not15.1, label %._crit_edge24, label %.lr.ph23.2, !llvm.loop !16

.lr.ph23.2:                                       ; preds = %.lr.ph23.1
  %21 = getelementptr inbounds i8, ptr %.0.lcssa, i64 4
  %22 = getelementptr inbounds i8, ptr %.promoted, i64 3
  store ptr %22, ptr %4, align 8, !tbaa !5
  %23 = load i8, ptr %18, align 1, !tbaa !13
  %24 = sext i8 %23 to i16
  store i16 %24, ptr %21, align 2, !tbaa !14
  br label %._crit_edge24

._crit_edge24:                                    ; preds = %.lr.ph23, %.lr.ph23.1, %.lr.ph23.2, %._crit_edge
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @arm_nn_read_q7x4_ia(ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__SXTB16(i32 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @__ROR(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"short", !7, i64 0}
!16 = distinct !{!16, !12}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass