; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src/CollectionBusLine.ll (ZN17CollectionBusLineD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CollectionBusLine = type { %class.Unit, i32, %"class.std::vector", %"class.std::vector.3", ptr, i32, i32, %class.CollectionBusLineStats }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.CollectionBusLineStats = type { %class.Stats, i32, i32, i32, i32, %"class.std::vector.8" }
%class.Stats = type { ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTV17CollectionBusLine = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN22CollectionBusLineStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN17CollectionBusLineD2Ev(ptr noundef nonnull align 8 dereferenceable(168) %0) unnamed_addr #3 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 32) ({ [6 x ptr] }, ptr @_ZTV17CollectionBusLine, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  store i32 0, ptr %3, align 4, !tbaa !11
  br label %6

6:                                                ; preds = %22, %1
  %7 = load i32, ptr %3, align 4, !tbaa !11
  %8 = sext i32 %7 to i64
  %9 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 2
  %10 = call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %9) #4
  %11 = icmp ult i64 %8, %10
  br i1 %11, label %13, label %12

12:                                               ; preds = %6
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  br label %25

13:                                               ; preds = %6
  %14 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 2
  %15 = load i32, ptr %3, align 4, !tbaa !11
  %16 = sext i32 %15 to i64
  %17 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %16) #4
  %18 = load ptr, ptr %17, align 8, !tbaa !5
  %19 = icmp eq ptr %18, null
  br i1 %19, label %21, label %20

20:                                               ; preds = %13
  call void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %18) #4
  call void @_ZdlPvm(ptr noundef %18, i64 noundef 64) #5
  br label %21

21:                                               ; preds = %20, %13
  br label %22

22:                                               ; preds = %21
  %23 = load i32, ptr %3, align 4, !tbaa !11
  %24 = add nsw i32 %23, 1
  store i32 %24, ptr %3, align 4, !tbaa !11
  br label %6, !llvm.loop !13

25:                                               ; preds = %12
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !11
  br label %26

26:                                               ; preds = %42, %25
  %27 = load i32, ptr %4, align 4, !tbaa !11
  %28 = sext i32 %27 to i64
  %29 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 3
  %30 = call noundef i64 @_ZNKSt6vectorIP4FifoSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %29) #4
  %31 = icmp ult i64 %28, %30
  br i1 %31, label %33, label %32

32:                                               ; preds = %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  br label %45

33:                                               ; preds = %26
  %34 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 3
  %35 = load i32, ptr %4, align 4, !tbaa !11
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #4
  %38 = load ptr, ptr %37, align 8, !tbaa !5
  %39 = icmp eq ptr %38, null
  br i1 %39, label %41, label %40

40:                                               ; preds = %33
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %38) #4
  call void @_ZdlPvm(ptr noundef %38, i64 noundef 120) #5
  br label %41

41:                                               ; preds = %40, %33
  br label %42

42:                                               ; preds = %41
  %43 = load i32, ptr %4, align 4, !tbaa !11
  %44 = add nsw i32 %43, 1
  store i32 %44, ptr %4, align 4, !tbaa !11
  br label %26, !llvm.loop !15

45:                                               ; preds = %32
  %46 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 4
  %47 = load ptr, ptr %46, align 8, !tbaa !16
  %48 = icmp eq ptr %47, null
  br i1 %48, label %50, label %49

49:                                               ; preds = %45
  call void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %47) #4
  call void @_ZdlPvm(ptr noundef %47, i64 noundef 64) #5
  br label %50

50:                                               ; preds = %49, %45
  %51 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 7
  call void @_ZN22CollectionBusLineStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %51) #4
  %52 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 3
  call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %52) #4
  %53 = getelementptr inbounds %class.CollectionBusLine, ptr %5, i32 0, i32 2
  call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %53) #4
  call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %5) #4
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP4FifoSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = !{!17, !6, i64 104}
!17 = !{!"_ZTS17CollectionBusLine", !18, i64 0, !12, i64 48, !22, i64 56, !26, i64 80, !6, i64 104, !12, i64 112, !12, i64 116, !30, i64 120}
!18 = !{!"_ZTS4Unit", !12, i64 8, !19, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !21, i64 8, !7, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!21 = !{!"long", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTS22CollectionBusLineStats", !31, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !32, i64 24}
!31 = !{!"_ZTS5Stats"}
!32 = !{!"_ZTSSt6vectorIjSaIjEE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV17CollectionBusLine = external dso_local unnamed_addr constant { [6 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN22CollectionBusLineStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN17CollectionBusLineD2Ev(ptr noundef nonnull align 8 dereferenceable(168) %0) unnamed_addr #2 align 2 {
  store ptr getelementptr inbounds inrange(-16, 32) (i8, ptr @_ZTV17CollectionBusLine, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 56
  %3 = tail call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #3
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %10, %1
  %4 = getelementptr inbounds i8, ptr %0, i64 80
  %5 = tail call noundef i64 @_ZNKSt6vectorIP4FifoSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %.not17 = icmp eq i64 %5, 0
  br i1 %.not17, label %._crit_edge, label %.lr.ph15

.lr.ph:                                           ; preds = %1, %10
  %indvars.iv = phi i64 [ %indvars.iv.next, %10 ], [ 0, %1 ]
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #3
  %7 = load ptr, ptr %6, align 8, !tbaa !8
  %8 = icmp eq ptr %7, null
  br i1 %8, label %10, label %9

9:                                                ; preds = %.lr.ph
  tail call void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %7) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %7, i64 noundef 64) #4
  br label %10

10:                                               ; preds = %.lr.ph, %9
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %11 = tail call noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #3
  %12 = icmp ugt i64 %11, %indvars.iv.next
  br i1 %12, label %.lr.ph, label %.preheader, !llvm.loop !11

._crit_edge:                                      ; preds = %20, %.preheader
  %13 = getelementptr inbounds i8, ptr %0, i64 104
  %14 = load ptr, ptr %13, align 8, !tbaa !13
  %15 = icmp eq ptr %14, null
  br i1 %15, label %24, label %23

.lr.ph15:                                         ; preds = %.preheader, %20
  %indvars.iv19 = phi i64 [ %indvars.iv.next20, %20 ], [ 0, %.preheader ]
  %16 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv19) #3
  %17 = load ptr, ptr %16, align 8, !tbaa !8
  %18 = icmp eq ptr %17, null
  br i1 %18, label %20, label %19

19:                                               ; preds = %.lr.ph15
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %17) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %17, i64 noundef 120) #4
  br label %20

20:                                               ; preds = %.lr.ph15, %19
  %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1
  %21 = tail call noundef i64 @_ZNKSt6vectorIP4FifoSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %22 = icmp ugt i64 %21, %indvars.iv.next20
  br i1 %22, label %.lr.ph15, label %._crit_edge, !llvm.loop !34

23:                                               ; preds = %._crit_edge
  tail call void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %14) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %14, i64 noundef 64) #4
  br label %24

24:                                               ; preds = %23, %._crit_edge
  %25 = getelementptr inbounds i8, ptr %0, i64 120
  tail call void @_ZN22CollectionBusLineStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %25) #3
  tail call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  tail call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #3
  tail call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %0) #3
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP10ConnectionSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10ConnectionSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN10ConnectionD2Ev(ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP4FifoSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #1 align 2

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !9, i64 104}
!14 = !{!"_ZTS17CollectionBusLine", !15, i64 0, !16, i64 48, !20, i64 56, !24, i64 80, !9, i64 104, !16, i64 112, !16, i64 116, !28, i64 120}
!15 = !{!"_ZTS4Unit", !16, i64 8, !17, i64 16}
!16 = !{!"int", !10, i64 0}
!17 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !18, i64 0, !19, i64 8, !10, i64 16}
!18 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!19 = !{!"long", !10, i64 0}
!20 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!24 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!28 = !{!"_ZTS22CollectionBusLineStats", !29, i64 0, !16, i64 8, !16, i64 12, !16, i64 16, !16, i64 20, !30, i64 24}
!29 = !{!"_ZTS5Stats"}
!30 = !{!"_ZTSSt6vectorIjSaIjEE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!34 = distinct !{!34, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass