; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SRAM_HandleTypeDef = type { ptr, ptr, %struct.FMC_NORSRAM_InitTypeDef, i32, i32, ptr }
%struct.FMC_NORSRAM_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__MDMA_HandleTypeDef = type { ptr, %struct.MDMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32 }
%struct.MDMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SRAM_Read_DMA(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %13, i32 0, i32 4
  %15 = load volatile i32, ptr %14, align 8, !tbaa !11
  store i32 %15, ptr %11, align 4, !tbaa !9
  %16 = load i32, ptr %11, align 4, !tbaa !9
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %21, label %18

18:                                               ; preds = %4
  %19 = load i32, ptr %11, align 4, !tbaa !9
  %20 = icmp eq i32 %19, 4
  br i1 %20, label %21, label %68

21:                                               ; preds = %18, %4
  br label %22

22:                                               ; preds = %21
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %23, i32 0, i32 3
  %25 = load i32, ptr %24, align 4, !tbaa !14
  %26 = icmp eq i32 %25, 1
  br i1 %26, label %27, label %28

27:                                               ; preds = %22
  store i32 2, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %71

28:                                               ; preds = %22
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %29, i32 0, i32 3
  store i32 1, ptr %30, align 4, !tbaa !14
  br label %31

31:                                               ; preds = %28
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %34, i32 0, i32 4
  store volatile i32 2, ptr %35, align 8, !tbaa !11
  %36 = load i32, ptr %11, align 4, !tbaa !9
  %37 = icmp eq i32 %36, 1
  br i1 %37, label %38, label %43

38:                                               ; preds = %33
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %39, i32 0, i32 5
  %41 = load ptr, ptr %40, align 8, !tbaa !15
  %42 = getelementptr inbounds %struct.__MDMA_HandleTypeDef, ptr %41, i32 0, i32 5
  store ptr @SRAM_DMACplt, ptr %42, align 8, !tbaa !16
  br label %48

43:                                               ; preds = %33
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %44, i32 0, i32 5
  %46 = load ptr, ptr %45, align 8, !tbaa !15
  %47 = getelementptr inbounds %struct.__MDMA_HandleTypeDef, ptr %46, i32 0, i32 5
  store ptr @SRAM_DMACpltProt, ptr %47, align 8, !tbaa !16
  br label %48

48:                                               ; preds = %43, %38
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %49, i32 0, i32 5
  %51 = load ptr, ptr %50, align 8, !tbaa !15
  %52 = getelementptr inbounds %struct.__MDMA_HandleTypeDef, ptr %51, i32 0, i32 9
  store ptr @SRAM_DMAError, ptr %52, align 8, !tbaa !19
  %53 = load ptr, ptr %6, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %53, i32 0, i32 5
  %55 = load ptr, ptr %54, align 8, !tbaa !15
  %56 = load ptr, ptr %7, align 8, !tbaa !5
  %57 = ptrtoint ptr %56 to i32
  %58 = load ptr, ptr %8, align 8, !tbaa !5
  %59 = ptrtoint ptr %58 to i32
  %60 = load i32, ptr %9, align 4, !tbaa !9
  %61 = mul i32 %60, 4
  %62 = call i32 @HAL_MDMA_Start_IT(ptr noundef %55, i32 noundef %57, i32 noundef %59, i32 noundef %61, i32 noundef 1)
  store i32 %62, ptr %10, align 4, !tbaa !9
  br label %63

63:                                               ; preds = %48
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.SRAM_HandleTypeDef, ptr %64, i32 0, i32 3
  store i32 0, ptr %65, align 4, !tbaa !14
  br label %66

66:                                               ; preds = %63
  br label %67

67:                                               ; preds = %66
  br label %69

68:                                               ; preds = %18
  store i32 1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %71

69:                                               ; preds = %67
  %70 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %70, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %71

71:                                               ; preds = %69, %68, %27
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %72 = load i32, ptr %5, align 4
  ret i32 %72
}

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMACplt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMACpltProt(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMAError(ptr noundef) #1

declare i32 @HAL_MDMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 80}
!12 = !{!"", !6, i64 0, !6, i64 8, !13, i64 16, !10, i64 76, !10, i64 80, !6, i64 88}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!14 = !{!12, !10, i64 76}
!15 = !{!12, !6, i64 88}
!16 = !{!17, !6, i64 80}
!17 = !{!"__MDMA_HandleTypeDef", !6, i64 0, !18, i64 8, !10, i64 64, !10, i64 68, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !6, i64 136, !10, i64 144, !10, i64 148}
!18 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52}
!19 = !{!17, !6, i64 112}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SRAM_Read_DMA(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 80
  %6 = load volatile i32, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i32 %6, 1
  switch i32 %6, label %23 [
    i32 4, label %8
    i32 1, label %8
  ]

8:                                                ; preds = %4, %4
  %9 = getelementptr inbounds i8, ptr %0, i64 76
  %10 = load i32, ptr %9, align 4, !tbaa !12
  %11 = icmp eq i32 %10, 1
  br i1 %11, label %23, label %12

12:                                               ; preds = %8
  store i32 1, ptr %9, align 4, !tbaa !12
  store volatile i32 2, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %0, i64 88
  %14 = load ptr, ptr %13, align 8, !tbaa !13
  %15 = getelementptr inbounds i8, ptr %14, i64 80
  %SRAM_DMACplt.SRAM_DMACpltProt = select i1 %7, ptr @SRAM_DMACplt, ptr @SRAM_DMACpltProt
  store ptr %SRAM_DMACplt.SRAM_DMACpltProt, ptr %15, align 8, !tbaa !14
  %16 = getelementptr inbounds i8, ptr %14, i64 112
  store ptr @SRAM_DMAError, ptr %16, align 8, !tbaa !17
  %17 = ptrtoint ptr %1 to i64
  %18 = trunc i64 %17 to i32
  %19 = ptrtoint ptr %2 to i64
  %20 = trunc i64 %19 to i32
  %21 = shl i32 %3, 2
  %22 = tail call i32 @HAL_MDMA_Start_IT(ptr noundef nonnull %14, i32 noundef %18, i32 noundef %20, i32 noundef %21, i32 noundef 1) #2
  store i32 0, ptr %9, align 4, !tbaa !12
  br label %23

23:                                               ; preds = %4, %8, %12
  %.0 = phi i32 [ %22, %12 ], [ 2, %8 ], [ 1, %4 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMACplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMACpltProt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SRAM_DMAError(ptr noundef) #0

declare i32 @HAL_MDMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 80}
!6 = !{!"", !7, i64 0, !7, i64 8, !10, i64 16, !11, i64 76, !11, i64 80, !7, i64 88}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 76}
!13 = !{!6, !7, i64 88}
!14 = !{!15, !7, i64 80}
!15 = !{!"__MDMA_HandleTypeDef", !7, i64 0, !16, i64 8, !11, i64 64, !11, i64 68, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !11, i64 144, !11, i64 148}
!16 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52}
!17 = !{!15, !7, i64 112}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass