; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (DMA)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SAI_HandleTypeDef = type { ptr, %struct.SAI_InitTypeDef, %struct.SAI_FrameInitTypeDef, %struct.SAI_SlotInitTypeDef, ptr, i16, i16, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SAI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.SAI_PdmInitTypeDef, i32, i32, i32, i32 }
%struct.SAI_PdmInitTypeDef = type { i32, i32, i32 }
%struct.SAI_FrameInitTypeDef = type { i32, i32, i32, i32, i32 }
%struct.SAI_SlotInitTypeDef = type { i32, i32, i32, i32 }
%struct.__DMA_HandleTypeDef = type { ptr, %struct.DMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, ptr, i32, ptr, ptr, i32 }
%struct.DMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SAI_Block_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nounwind uwtable
declare hidden i32 @SAI_InterruptFlag(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SAI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  %8 = load ptr, ptr %6, align 8, !tbaa !5
  %9 = icmp eq ptr %8, null
  br i1 %9, label %14, label %10

10:                                               ; preds = %3
  %11 = load i16, ptr %7, align 2, !tbaa !9
  %12 = zext i16 %11 to i32
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %10, %3
  store i32 1, ptr %4, align 4
  br label %124

15:                                               ; preds = %10
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %16, i32 0, i32 12
  %18 = load volatile i32, ptr %17, align 4, !tbaa !11
  %19 = icmp eq i32 %18, 1
  br i1 %19, label %20, label %123

20:                                               ; preds = %15
  br label %21

21:                                               ; preds = %20
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %22, i32 0, i32 11
  %24 = load i32, ptr %23, align 8, !tbaa !18
  %25 = icmp eq i32 %24, 1
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 2, ptr %4, align 4
  br label %124

27:                                               ; preds = %21
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %28, i32 0, i32 11
  store i32 1, ptr %29, align 8, !tbaa !18
  br label %30

30:                                               ; preds = %27
  br label %31

31:                                               ; preds = %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %33, i32 0, i32 4
  store ptr %32, ptr %34, align 8, !tbaa !19
  %35 = load i16, ptr %7, align 2, !tbaa !9
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %36, i32 0, i32 5
  store i16 %35, ptr %37, align 8, !tbaa !20
  %38 = load i16, ptr %7, align 2, !tbaa !9
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %39, i32 0, i32 6
  store i16 %38, ptr %40, align 2, !tbaa !21
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %41, i32 0, i32 13
  store volatile i32 0, ptr %42, align 8, !tbaa !22
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %43, i32 0, i32 12
  store volatile i32 34, ptr %44, align 4, !tbaa !11
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %45, i32 0, i32 8
  %47 = load ptr, ptr %46, align 8, !tbaa !23
  %48 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %47, i32 0, i32 6
  store ptr @SAI_DMARxHalfCplt, ptr %48, align 8, !tbaa !24
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %49, i32 0, i32 8
  %51 = load ptr, ptr %50, align 8, !tbaa !23
  %52 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %51, i32 0, i32 5
  store ptr @SAI_DMARxCplt, ptr %52, align 8, !tbaa !27
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %53, i32 0, i32 8
  %55 = load ptr, ptr %54, align 8, !tbaa !23
  %56 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %55, i32 0, i32 9
  store ptr @SAI_DMAError, ptr %56, align 8, !tbaa !28
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %57, i32 0, i32 8
  %59 = load ptr, ptr %58, align 8, !tbaa !23
  %60 = getelementptr inbounds %struct.__DMA_HandleTypeDef, ptr %59, i32 0, i32 10
  store ptr null, ptr %60, align 8, !tbaa !29
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %61, i32 0, i32 8
  %63 = load ptr, ptr %62, align 8, !tbaa !23
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %64, i32 0, i32 0
  %66 = load ptr, ptr %65, align 8, !tbaa !30
  %67 = getelementptr inbounds %struct.SAI_Block_TypeDef, ptr %66, i32 0, i32 7
  %68 = ptrtoint ptr %67 to i32
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %69, i32 0, i32 4
  %71 = load ptr, ptr %70, align 8, !tbaa !19
  %72 = ptrtoint ptr %71 to i32
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %73, i32 0, i32 5
  %75 = load i16, ptr %74, align 8, !tbaa !20
  %76 = zext i16 %75 to i32
  %77 = call i32 @HAL_DMA_Start_IT(ptr noundef %63, i32 noundef %68, i32 noundef %72, i32 noundef %76)
  %78 = icmp ne i32 %77, 0
  br i1 %78, label %79, label %84

79:                                               ; preds = %31
  br label %80

80:                                               ; preds = %79
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %81, i32 0, i32 11
  store i32 0, ptr %82, align 8, !tbaa !18
  br label %83

83:                                               ; preds = %80
  store i32 1, ptr %4, align 4
  br label %124

84:                                               ; preds = %31
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %85, i32 0, i32 0
  %87 = load ptr, ptr %86, align 8, !tbaa !30
  %88 = getelementptr inbounds %struct.SAI_Block_TypeDef, ptr %87, i32 0, i32 0
  %89 = load volatile i32, ptr %88, align 4, !tbaa !31
  %90 = zext i32 %89 to i64
  %91 = and i64 %90, 65536
  %92 = icmp eq i64 %91, 0
  br i1 %92, label %93, label %102

93:                                               ; preds = %84
  %94 = load ptr, ptr %5, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !30
  %97 = getelementptr inbounds %struct.SAI_Block_TypeDef, ptr %96, i32 0, i32 0
  %98 = load volatile i32, ptr %97, align 4, !tbaa !31
  %99 = zext i32 %98 to i64
  %100 = or i64 %99, 65536
  %101 = trunc i64 %100 to i32
  store volatile i32 %101, ptr %97, align 4, !tbaa !31
  br label %102

102:                                              ; preds = %93, %84
  %103 = load ptr, ptr %5, align 8, !tbaa !5
  %104 = call i32 @SAI_InterruptFlag(ptr noundef %103, i32 noundef 0)
  %105 = load ptr, ptr %5, align 8, !tbaa !5
  %106 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %105, i32 0, i32 0
  %107 = load ptr, ptr %106, align 8, !tbaa !30
  %108 = getelementptr inbounds %struct.SAI_Block_TypeDef, ptr %107, i32 0, i32 4
  %109 = load volatile i32, ptr %108, align 4, !tbaa !33
  %110 = or i32 %109, %104
  store volatile i32 %110, ptr %108, align 4, !tbaa !33
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %111, i32 0, i32 0
  %113 = load ptr, ptr %112, align 8, !tbaa !30
  %114 = getelementptr inbounds %struct.SAI_Block_TypeDef, ptr %113, i32 0, i32 0
  %115 = load volatile i32, ptr %114, align 4, !tbaa !31
  %116 = zext i32 %115 to i64
  %117 = or i64 %116, 131072
  %118 = trunc i64 %117 to i32
  store volatile i32 %118, ptr %114, align 4, !tbaa !31
  br label %119

119:                                              ; preds = %102
  %120 = load ptr, ptr %5, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.__SAI_HandleTypeDef, ptr %120, i32 0, i32 11
  store i32 0, ptr %121, align 8, !tbaa !18
  br label %122

122:                                              ; preds = %119
  store i32 0, ptr %4, align 4
  br label %124

123:                                              ; preds = %15
  store i32 2, ptr %4, align 4
  br label %124

124:                                              ; preds = %123, %122, %83, %26, %14
  %125 = load i32, ptr %4, align 4
  ret i32 %125
}

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMARxHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMARxCplt(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !14, i64 180}
!12 = !{!"__SAI_HandleTypeDef", !6, i64 0, !13, i64 8, !16, i64 88, !17, i64 108, !6, i64 128, !10, i64 136, !10, i64 138, !6, i64 144, !6, i64 152, !6, i64 160, !6, i64 168, !14, i64 176, !14, i64 180, !14, i64 184}
!13 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44, !14, i64 48, !15, i64 52, !14, i64 64, !14, i64 68, !14, i64 72, !14, i64 76}
!14 = !{!"int", !7, i64 0}
!15 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8}
!16 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16}
!17 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12}
!18 = !{!12, !14, i64 176}
!19 = !{!12, !6, i64 128}
!20 = !{!12, !10, i64 136}
!21 = !{!12, !10, i64 138}
!22 = !{!12, !14, i64 184}
!23 = !{!12, !6, i64 152}
!24 = !{!25, !6, i64 80}
!25 = !{!"__DMA_HandleTypeDef", !6, i64 0, !26, i64 8, !14, i64 56, !14, i64 60, !6, i64 64, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !14, i64 120, !14, i64 124, !14, i64 128, !6, i64 136, !6, i64 144, !14, i64 152, !6, i64 160, !6, i64 168, !14, i64 176}
!26 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28, !14, i64 32, !14, i64 36, !14, i64 40, !14, i64 44}
!27 = !{!25, !6, i64 72}
!28 = !{!25, !6, i64 104}
!29 = !{!25, !6, i64 112}
!30 = !{!12, !6, i64 0}
!31 = !{!32, !14, i64 0}
!32 = !{!"", !14, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !14, i64 16, !14, i64 20, !14, i64 24, !14, i64 28}
!33 = !{!32, !14, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden i32 @SAI_InterruptFlag(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMAError(ptr noundef) #0

declare i32 @HAL_DMA_Start_IT(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @HAL_SAI_Receive_DMA(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = icmp eq ptr %1, null
  %5 = icmp eq i16 %2, 0
  %or.cond = or i1 %4, %5
  br i1 %or.cond, label %49, label %6

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 180
  %8 = load volatile i32, ptr %7, align 4, !tbaa !5
  %9 = icmp eq i32 %8, 1
  br i1 %9, label %10, label %49

10:                                               ; preds = %6
  %11 = getelementptr inbounds i8, ptr %0, i64 176
  %12 = load i32, ptr %11, align 8, !tbaa !16
  %13 = icmp eq i32 %12, 1
  br i1 %13, label %49, label %14

14:                                               ; preds = %10
  store i32 1, ptr %11, align 8, !tbaa !16
  %15 = getelementptr inbounds i8, ptr %0, i64 128
  store ptr %1, ptr %15, align 8, !tbaa !17
  %16 = getelementptr inbounds i8, ptr %0, i64 136
  store i16 %2, ptr %16, align 8, !tbaa !18
  %17 = getelementptr inbounds i8, ptr %0, i64 138
  store i16 %2, ptr %17, align 2, !tbaa !19
  %18 = getelementptr inbounds i8, ptr %0, i64 184
  store volatile i32 0, ptr %18, align 8, !tbaa !20
  store volatile i32 34, ptr %7, align 4, !tbaa !5
  %19 = getelementptr inbounds i8, ptr %0, i64 152
  %20 = load ptr, ptr %19, align 8, !tbaa !21
  %21 = getelementptr inbounds i8, ptr %20, i64 80
  store ptr @SAI_DMARxHalfCplt, ptr %21, align 8, !tbaa !22
  %22 = getelementptr inbounds i8, ptr %20, i64 72
  store ptr @SAI_DMARxCplt, ptr %22, align 8, !tbaa !25
  %23 = getelementptr inbounds i8, ptr %20, i64 104
  store ptr @SAI_DMAError, ptr %23, align 8, !tbaa !26
  %24 = getelementptr inbounds i8, ptr %20, i64 112
  store ptr null, ptr %24, align 8, !tbaa !27
  %25 = load ptr, ptr %0, align 8, !tbaa !28
  %26 = getelementptr inbounds i8, ptr %25, i64 28
  %27 = ptrtoint ptr %26 to i64
  %28 = trunc i64 %27 to i32
  %29 = ptrtoint ptr %1 to i64
  %30 = trunc i64 %29 to i32
  %31 = zext i16 %2 to i32
  %32 = tail call i32 @HAL_DMA_Start_IT(ptr noundef %20, i32 noundef %28, i32 noundef %30, i32 noundef %31) #2
  %.not = icmp eq i32 %32, 0
  br i1 %.not, label %33, label %.sink.split

33:                                               ; preds = %14
  %34 = load ptr, ptr %0, align 8, !tbaa !28
  %35 = load volatile i32, ptr %34, align 4, !tbaa !29
  %36 = and i32 %35, 65536
  %37 = icmp eq i32 %36, 0
  br i1 %37, label %38, label %41

38:                                               ; preds = %33
  %39 = load volatile i32, ptr %34, align 4, !tbaa !29
  %40 = or i32 %39, 65536
  store volatile i32 %40, ptr %34, align 4, !tbaa !29
  br label %41

41:                                               ; preds = %38, %33
  %42 = tail call i32 @SAI_InterruptFlag(ptr noundef nonnull %0, i32 noundef 0)
  %43 = load ptr, ptr %0, align 8, !tbaa !28
  %44 = getelementptr inbounds i8, ptr %43, i64 16
  %45 = load volatile i32, ptr %44, align 4, !tbaa !31
  %46 = or i32 %45, %42
  store volatile i32 %46, ptr %44, align 4, !tbaa !31
  %47 = load volatile i32, ptr %43, align 4, !tbaa !29
  %48 = or i32 %47, 131072
  store volatile i32 %48, ptr %43, align 4, !tbaa !29
  br label %.sink.split

.sink.split:                                      ; preds = %14, %41
  %.0.ph = phi i32 [ 0, %41 ], [ 1, %14 ]
  store i32 0, ptr %11, align 8, !tbaa !16
  br label %49

49:                                               ; preds = %.sink.split, %6, %10, %3
  %.0 = phi i32 [ 1, %3 ], [ 2, %10 ], [ 2, %6 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMARxHalfCplt(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SAI_DMARxCplt(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 180}
!6 = !{!"__SAI_HandleTypeDef", !7, i64 0, !10, i64 8, !13, i64 88, !14, i64 108, !7, i64 128, !15, i64 136, !15, i64 138, !7, i64 144, !7, i64 152, !7, i64 160, !7, i64 168, !11, i64 176, !11, i64 180, !11, i64 184}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !12, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76}
!11 = !{!"int", !8, i64 0}
!12 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16}
!14 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!15 = !{!"short", !8, i64 0}
!16 = !{!6, !11, i64 176}
!17 = !{!6, !7, i64 128}
!18 = !{!6, !15, i64 136}
!19 = !{!6, !15, i64 138}
!20 = !{!6, !11, i64 184}
!21 = !{!6, !7, i64 152}
!22 = !{!23, !7, i64 80}
!23 = !{!"__DMA_HandleTypeDef", !7, i64 0, !24, i64 8, !11, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !11, i64 120, !11, i64 124, !11, i64 128, !7, i64 136, !7, i64 144, !11, i64 152, !7, i64 160, !7, i64 168, !11, i64 176}
!24 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44}
!25 = !{!23, !7, i64 72}
!26 = !{!23, !7, i64 104}
!27 = !{!23, !7, i64 112}
!28 = !{!6, !7, i64 0}
!29 = !{!30, !11, i64 0}
!30 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28}
!31 = !{!30, !11, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass