; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QSPI_HandleTypeDef = type { ptr, %struct.QSPI_InitTypeDef, ptr, i32, i32, ptr, i32, i32, ptr, i32, i32, i32, i32 }
%struct.QSPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.QUADSPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.__MDMA_HandleTypeDef = type { ptr, %struct.MDMA_InitTypeDef, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32 }
%struct.MDMA_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @QSPI_DMAAbortCplt(ptr noundef) #1

declare i32 @HAL_MDMA_Abort_IT(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_QSPI_Abort_IT(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %4, i32 0, i32 10
  %6 = load volatile i32, ptr %5, align 4, !tbaa !11
  %7 = and i32 %6, 2
  %8 = icmp ne i32 %7, 0
  br i1 %8, label %9, label %79

9:                                                ; preds = %1
  br label %10

10:                                               ; preds = %9
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %11, i32 0, i32 9
  store volatile i32 0, ptr %12, align 8, !tbaa !14
  br label %13

13:                                               ; preds = %10
  br label %14

14:                                               ; preds = %13
  %15 = load ptr, ptr %2, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %15, i32 0, i32 10
  store volatile i32 8, ptr %16, align 4, !tbaa !11
  %17 = load ptr, ptr %2, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %17, i32 0, i32 0
  %19 = load ptr, ptr %18, align 8, !tbaa !15
  %20 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %19, i32 0, i32 0
  %21 = load volatile i32, ptr %20, align 4, !tbaa !16
  %22 = zext i32 %21 to i64
  %23 = and i64 %22, -2031617
  %24 = trunc i64 %23 to i32
  store volatile i32 %24, ptr %20, align 4, !tbaa !16
  %25 = load ptr, ptr %2, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !15
  %28 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %27, i32 0, i32 0
  %29 = load volatile i32, ptr %28, align 4, !tbaa !16
  %30 = zext i32 %29 to i64
  %31 = and i64 %30, 4
  %32 = icmp ne i64 %31, 0
  br i1 %32, label %33, label %57

33:                                               ; preds = %14
  %34 = load ptr, ptr %2, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %34, i32 0, i32 0
  %36 = load ptr, ptr %35, align 8, !tbaa !15
  %37 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %36, i32 0, i32 0
  %38 = load volatile i32, ptr %37, align 4, !tbaa !16
  %39 = zext i32 %38 to i64
  %40 = and i64 %39, -5
  %41 = trunc i64 %40 to i32
  store volatile i32 %41, ptr %37, align 4, !tbaa !16
  %42 = load ptr, ptr %2, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %42, i32 0, i32 8
  %44 = load ptr, ptr %43, align 8, !tbaa !18
  %45 = getelementptr inbounds %struct.__MDMA_HandleTypeDef, ptr %44, i32 0, i32 10
  store ptr @QSPI_DMAAbortCplt, ptr %45, align 8, !tbaa !19
  %46 = load ptr, ptr %2, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %46, i32 0, i32 8
  %48 = load ptr, ptr %47, align 8, !tbaa !18
  %49 = call i32 @HAL_MDMA_Abort_IT(ptr noundef %48)
  %50 = icmp ne i32 %49, 0
  br i1 %50, label %51, label %56

51:                                               ; preds = %33
  %52 = load ptr, ptr %2, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %52, i32 0, i32 11
  %54 = load volatile i32, ptr %53, align 8, !tbaa !22
  %55 = or i32 %54, 4
  store volatile i32 %55, ptr %53, align 8, !tbaa !22
  store i32 1, ptr %3, align 4, !tbaa !9
  br label %56

56:                                               ; preds = %51, %33
  br label %78

57:                                               ; preds = %14
  %58 = load ptr, ptr %2, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !15
  %61 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %60, i32 0, i32 3
  store volatile i32 2, ptr %61, align 4, !tbaa !23
  %62 = load ptr, ptr %2, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %62, i32 0, i32 0
  %64 = load ptr, ptr %63, align 8, !tbaa !15
  %65 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %64, i32 0, i32 0
  %66 = load volatile i32, ptr %65, align 4, !tbaa !16
  %67 = zext i32 %66 to i64
  %68 = or i64 %67, 131072
  %69 = trunc i64 %68 to i32
  store volatile i32 %69, ptr %65, align 4, !tbaa !16
  %70 = load ptr, ptr %2, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.QSPI_HandleTypeDef, ptr %70, i32 0, i32 0
  %72 = load ptr, ptr %71, align 8, !tbaa !15
  %73 = getelementptr inbounds %struct.QUADSPI_TypeDef, ptr %72, i32 0, i32 0
  %74 = load volatile i32, ptr %73, align 4, !tbaa !16
  %75 = zext i32 %74 to i64
  %76 = or i64 %75, 2
  %77 = trunc i64 %76 to i32
  store volatile i32 %77, ptr %73, align 4, !tbaa !16
  br label %78

78:                                               ; preds = %57, %56
  br label %79

79:                                               ; preds = %78, %1
  %80 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i32 %80
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 84}
!12 = !{!"", !6, i64 0, !13, i64 8, !6, i64 40, !10, i64 48, !10, i64 52, !6, i64 56, !10, i64 64, !10, i64 68, !6, i64 72, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}
!14 = !{!12, !10, i64 80}
!15 = !{!12, !6, i64 0}
!16 = !{!17, !10, i64 0}
!17 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48}
!18 = !{!12, !6, i64 72}
!19 = !{!20, !6, i64 120}
!20 = !{!"__MDMA_HandleTypeDef", !6, i64 0, !21, i64 8, !10, i64 64, !10, i64 68, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96, !6, i64 104, !6, i64 112, !6, i64 120, !6, i64 128, !6, i64 136, !10, i64 144, !10, i64 148}
!21 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52}
!22 = !{!12, !10, i64 88}
!23 = !{!17, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden void @QSPI_DMAAbortCplt(ptr noundef) #0

declare i32 @HAL_MDMA_Abort_IT(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_QSPI_Abort_IT(ptr noundef %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 84
  %3 = load volatile i32, ptr %2, align 4, !tbaa !5
  %4 = and i32 %3, 2
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %29, label %5

5:                                                ; preds = %1
  %6 = getelementptr inbounds i8, ptr %0, i64 80
  store volatile i32 0, ptr %6, align 8, !tbaa !12
  store volatile i32 8, ptr %2, align 4, !tbaa !5
  %7 = load ptr, ptr %0, align 8, !tbaa !13
  %8 = load volatile i32, ptr %7, align 4, !tbaa !14
  %9 = and i32 %8, -2031617
  store volatile i32 %9, ptr %7, align 4, !tbaa !14
  %10 = load volatile i32, ptr %7, align 4, !tbaa !14
  %11 = and i32 %10, 4
  %.not12 = icmp eq i32 %11, 0
  br i1 %.not12, label %23, label %12

12:                                               ; preds = %5
  %13 = load volatile i32, ptr %7, align 4, !tbaa !14
  %14 = and i32 %13, -5
  store volatile i32 %14, ptr %7, align 4, !tbaa !14
  %15 = getelementptr inbounds i8, ptr %0, i64 72
  %16 = load ptr, ptr %15, align 8, !tbaa !16
  %17 = getelementptr inbounds i8, ptr %16, i64 120
  store ptr @QSPI_DMAAbortCplt, ptr %17, align 8, !tbaa !17
  %18 = tail call i32 @HAL_MDMA_Abort_IT(ptr noundef %16) #2
  %.not13 = icmp eq i32 %18, 0
  br i1 %.not13, label %29, label %19

19:                                               ; preds = %12
  %20 = getelementptr inbounds i8, ptr %0, i64 88
  %21 = load volatile i32, ptr %20, align 8, !tbaa !20
  %22 = or i32 %21, 4
  store volatile i32 %22, ptr %20, align 8, !tbaa !20
  br label %29

23:                                               ; preds = %5
  %24 = getelementptr inbounds i8, ptr %7, i64 12
  store volatile i32 2, ptr %24, align 4, !tbaa !21
  %25 = load volatile i32, ptr %7, align 4, !tbaa !14
  %26 = or i32 %25, 131072
  store volatile i32 %26, ptr %7, align 4, !tbaa !14
  %27 = load volatile i32, ptr %7, align 4, !tbaa !14
  %28 = or i32 %27, 2
  store volatile i32 %28, ptr %7, align 4, !tbaa !14
  br label %29

29:                                               ; preds = %23, %19, %12, %1
  %.0 = phi i32 [ 1, %19 ], [ 0, %12 ], [ 0, %23 ], [ 0, %1 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 84}
!6 = !{!"", !7, i64 0, !10, i64 8, !7, i64 40, !11, i64 48, !11, i64 52, !7, i64 56, !11, i64 64, !11, i64 68, !7, i64 72, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 80}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 0}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48}
!16 = !{!6, !7, i64 72}
!17 = !{!18, !7, i64 120}
!18 = !{!"__MDMA_HandleTypeDef", !7, i64 0, !19, i64 8, !11, i64 64, !11, i64 68, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !11, i64 144, !11, i64 148}
!19 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52}
!20 = !{!6, !11, i64 88}
!21 = !{!15, !11, i64 12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass