; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (usb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.USB_OTG_HostTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @USB_InitFSLSPClkSel(ptr noundef %0, i8 noundef zeroext %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %6 = load ptr, ptr %3, align 8, !tbaa !5
  %7 = ptrtoint ptr %6 to i32
  store i32 %7, ptr %5, align 4, !tbaa !10
  %8 = load i32, ptr %5, align 4, !tbaa !10
  %9 = zext i32 %8 to i64
  %10 = add i64 %9, 1024
  %11 = inttoptr i64 %10 to ptr
  %12 = getelementptr inbounds %struct.USB_OTG_HostTypeDef, ptr %11, i32 0, i32 0
  %13 = load volatile i32, ptr %12, align 4, !tbaa !12
  %14 = zext i32 %13 to i64
  %15 = and i64 %14, -4
  %16 = trunc i64 %15 to i32
  store volatile i32 %16, ptr %12, align 4, !tbaa !12
  %17 = load i8, ptr %4, align 1, !tbaa !9
  %18 = zext i8 %17 to i32
  %19 = zext i32 %18 to i64
  %20 = and i64 %19, 3
  %21 = load i32, ptr %5, align 4, !tbaa !10
  %22 = zext i32 %21 to i64
  %23 = add i64 %22, 1024
  %24 = inttoptr i64 %23 to ptr
  %25 = getelementptr inbounds %struct.USB_OTG_HostTypeDef, ptr %24, i32 0, i32 0
  %26 = load volatile i32, ptr %25, align 4, !tbaa !12
  %27 = zext i32 %26 to i64
  %28 = or i64 %27, %20
  %29 = trunc i64 %28 to i32
  store volatile i32 %29, ptr %25, align 4, !tbaa !12
  %30 = load i8, ptr %4, align 1, !tbaa !9
  %31 = zext i8 %30 to i32
  %32 = icmp eq i32 %31, 1
  br i1 %32, label %33, label %39

33:                                               ; preds = %2
  %34 = load i32, ptr %5, align 4, !tbaa !10
  %35 = zext i32 %34 to i64
  %36 = add i64 %35, 1024
  %37 = inttoptr i64 %36 to ptr
  %38 = getelementptr inbounds %struct.USB_OTG_HostTypeDef, ptr %37, i32 0, i32 1
  store volatile i32 48000, ptr %38, align 4, !tbaa !14
  br label %51

39:                                               ; preds = %2
  %40 = load i8, ptr %4, align 1, !tbaa !9
  %41 = zext i8 %40 to i32
  %42 = icmp eq i32 %41, 2
  br i1 %42, label %43, label %49

43:                                               ; preds = %39
  %44 = load i32, ptr %5, align 4, !tbaa !10
  %45 = zext i32 %44 to i64
  %46 = add i64 %45, 1024
  %47 = inttoptr i64 %46 to ptr
  %48 = getelementptr inbounds %struct.USB_OTG_HostTypeDef, ptr %47, i32 0, i32 1
  store volatile i32 6000, ptr %48, align 4, !tbaa !14
  br label %50

49:                                               ; preds = %39
  br label %50

50:                                               ; preds = %49, %43
  br label %51

51:                                               ; preds = %50, %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 0
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 0}
!13 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24}
!14 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nounwind uwtable
define dso_local noundef i32 @USB_InitFSLSPClkSel(ptr noundef %0, i8 noundef zeroext %1) local_unnamed_addr #0 {
  %3 = ptrtoint ptr %0 to i64
  %4 = and i64 %3, 4294967295
  %5 = add nuw nsw i64 %4, 1024
  %6 = inttoptr i64 %5 to ptr
  %7 = load volatile i32, ptr %6, align 4, !tbaa !5
  %8 = and i32 %7, -4
  store volatile i32 %8, ptr %6, align 4, !tbaa !5
  %9 = and i8 %1, 3
  %10 = load volatile i32, ptr %6, align 4, !tbaa !5
  %11 = zext nneg i8 %9 to i32
  %12 = or i32 %10, %11
  store volatile i32 %12, ptr %6, align 4, !tbaa !5
  switch i8 %1, label %15 [
    i8 1, label %.sink.split
    i8 2, label %13
  ]

13:                                               ; preds = %2
  br label %.sink.split

.sink.split:                                      ; preds = %2, %13
  %.sink = phi i32 [ 6000, %13 ], [ 48000, %2 ]
  %14 = getelementptr inbounds i8, ptr %6, i64 4
  store volatile i32 %.sink, ptr %14, align 4, !tbaa !10
  br label %15

15:                                               ; preds = %.sink.split, %2
  ret i32 0
}

attributes #0 = { nofree norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!6, !7, i64 4}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass