; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (IT)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__SPI_HandleTypeDef = type { ptr, %struct.SPI_InitTypeDef, ptr, i16, i16, ptr, i16, i16, i32, ptr, ptr, ptr, ptr, i32, i32, i32 }
%struct.SPI_InitTypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.SPI_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, [3 x i32], i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Receive_IT(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i16, align 2
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  store i32 0, ptr %8, align 4, !tbaa !11
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %10, i32 0, i32 1
  %12 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 4, !tbaa !13
  %14 = zext i32 %13 to i64
  %15 = icmp eq i64 %14, 0
  br i1 %15, label %16, label %31

16:                                               ; preds = %3
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %17, i32 0, i32 1
  %19 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %18, i32 0, i32 0
  %20 = load i32, ptr %19, align 8, !tbaa !16
  %21 = zext i32 %20 to i64
  %22 = icmp eq i64 %21, 4194304
  br i1 %22, label %23, label %31

23:                                               ; preds = %16
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %24, i32 0, i32 14
  store volatile i32 4, ptr %25, align 4, !tbaa !17
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = load ptr, ptr %6, align 8, !tbaa !5
  %29 = load i16, ptr %7, align 2, !tbaa !9
  %30 = call i32 @HAL_SPI_TransmitReceive_IT(ptr noundef %26, ptr noundef %27, ptr noundef %28, i16 noundef zeroext %29)
  store i32 %30, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %184

31:                                               ; preds = %16, %3
  br label %32

32:                                               ; preds = %31
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %33, i32 0, i32 13
  %35 = load i32, ptr %34, align 8, !tbaa !18
  %36 = icmp eq i32 %35, 1
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %184

38:                                               ; preds = %32
  %39 = load ptr, ptr %5, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %39, i32 0, i32 13
  store i32 1, ptr %40, align 8, !tbaa !18
  br label %41

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %44, i32 0, i32 14
  %46 = load volatile i32, ptr %45, align 4, !tbaa !17
  %47 = icmp ne i32 %46, 1
  br i1 %47, label %48, label %55

48:                                               ; preds = %43
  store i32 2, ptr %8, align 4, !tbaa !11
  br label %49

49:                                               ; preds = %48
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %50, i32 0, i32 13
  store i32 0, ptr %51, align 8, !tbaa !18
  br label %52

52:                                               ; preds = %49
  br label %53

53:                                               ; preds = %52
  %54 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %54, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %184

55:                                               ; preds = %43
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = icmp eq ptr %56, null
  br i1 %57, label %62, label %58

58:                                               ; preds = %55
  %59 = load i16, ptr %7, align 2, !tbaa !9
  %60 = zext i16 %59 to i64
  %61 = icmp eq i64 %60, 0
  br i1 %61, label %62, label %69

62:                                               ; preds = %58, %55
  store i32 1, ptr %8, align 4, !tbaa !11
  br label %63

63:                                               ; preds = %62
  %64 = load ptr, ptr %5, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %64, i32 0, i32 13
  store i32 0, ptr %65, align 8, !tbaa !18
  br label %66

66:                                               ; preds = %63
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %68, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %184

69:                                               ; preds = %58
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %70, i32 0, i32 14
  store volatile i32 4, ptr %71, align 4, !tbaa !17
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %72, i32 0, i32 15
  store volatile i32 0, ptr %73, align 8, !tbaa !19
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %75, i32 0, i32 5
  store ptr %74, ptr %76, align 8, !tbaa !20
  %77 = load i16, ptr %7, align 2, !tbaa !9
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %78, i32 0, i32 6
  store i16 %77, ptr %79, align 8, !tbaa !21
  %80 = load i16, ptr %7, align 2, !tbaa !9
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %81, i32 0, i32 7
  store volatile i16 %80, ptr %82, align 2, !tbaa !22
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %83, i32 0, i32 2
  store ptr null, ptr %84, align 8, !tbaa !23
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %85, i32 0, i32 3
  store i16 0, ptr %86, align 8, !tbaa !24
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %87, i32 0, i32 4
  store volatile i16 0, ptr %88, align 2, !tbaa !25
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %89, i32 0, i32 10
  store ptr null, ptr %90, align 8, !tbaa !26
  %91 = load ptr, ptr %5, align 8, !tbaa !5
  %92 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %91, i32 0, i32 1
  %93 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %92, i32 0, i32 2
  %94 = load i32, ptr %93, align 8, !tbaa !27
  %95 = zext i32 %94 to i64
  %96 = icmp ugt i64 %95, 15
  br i1 %96, label %97, label %100

97:                                               ; preds = %69
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %98, i32 0, i32 9
  store ptr @SPI_RxISR_32BIT, ptr %99, align 8, !tbaa !28
  br label %114

100:                                              ; preds = %69
  %101 = load ptr, ptr %5, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %101, i32 0, i32 1
  %103 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %102, i32 0, i32 2
  %104 = load i32, ptr %103, align 8, !tbaa !27
  %105 = zext i32 %104 to i64
  %106 = icmp ugt i64 %105, 7
  br i1 %106, label %107, label %110

107:                                              ; preds = %100
  %108 = load ptr, ptr %5, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %108, i32 0, i32 9
  store ptr @SPI_RxISR_16BIT, ptr %109, align 8, !tbaa !28
  br label %113

110:                                              ; preds = %100
  %111 = load ptr, ptr %5, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %111, i32 0, i32 9
  store ptr @SPI_RxISR_8BIT, ptr %112, align 8, !tbaa !28
  br label %113

113:                                              ; preds = %110, %107
  br label %114

114:                                              ; preds = %113, %97
  %115 = load ptr, ptr %5, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %115, i32 0, i32 1
  %117 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %116, i32 0, i32 1
  %118 = load i32, ptr %117, align 4, !tbaa !13
  %119 = zext i32 %118 to i64
  %120 = icmp eq i64 %119, 393216
  br i1 %120, label %121, label %130

121:                                              ; preds = %114
  %122 = load ptr, ptr %5, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %122, i32 0, i32 0
  %124 = load ptr, ptr %123, align 8, !tbaa !29
  %125 = getelementptr inbounds %struct.SPI_TypeDef, ptr %124, i32 0, i32 0
  %126 = load volatile i32, ptr %125, align 4, !tbaa !30
  %127 = zext i32 %126 to i64
  %128 = and i64 %127, -2049
  %129 = trunc i64 %128 to i32
  store volatile i32 %129, ptr %125, align 4, !tbaa !30
  br label %130

130:                                              ; preds = %121, %114
  %131 = load ptr, ptr %5, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %131, i32 0, i32 0
  %133 = load ptr, ptr %132, align 8, !tbaa !29
  %134 = getelementptr inbounds %struct.SPI_TypeDef, ptr %133, i32 0, i32 1
  %135 = load volatile i32, ptr %134, align 4, !tbaa !32
  %136 = zext i32 %135 to i64
  %137 = and i64 %136, -65536
  %138 = load i16, ptr %7, align 2, !tbaa !9
  %139 = zext i16 %138 to i64
  %140 = or i64 %137, %139
  %141 = trunc i64 %140 to i32
  %142 = load ptr, ptr %5, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %142, i32 0, i32 0
  %144 = load ptr, ptr %143, align 8, !tbaa !29
  %145 = getelementptr inbounds %struct.SPI_TypeDef, ptr %144, i32 0, i32 1
  store volatile i32 %141, ptr %145, align 4, !tbaa !32
  %146 = load ptr, ptr %5, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %146, i32 0, i32 0
  %148 = load ptr, ptr %147, align 8, !tbaa !29
  %149 = getelementptr inbounds %struct.SPI_TypeDef, ptr %148, i32 0, i32 0
  %150 = load volatile i32, ptr %149, align 4, !tbaa !30
  %151 = zext i32 %150 to i64
  %152 = or i64 %151, 1
  %153 = trunc i64 %152 to i32
  store volatile i32 %153, ptr %149, align 4, !tbaa !30
  %154 = load ptr, ptr %5, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %154, i32 0, i32 0
  %156 = load ptr, ptr %155, align 8, !tbaa !29
  %157 = getelementptr inbounds %struct.SPI_TypeDef, ptr %156, i32 0, i32 4
  %158 = load volatile i32, ptr %157, align 4, !tbaa !33
  %159 = zext i32 %158 to i64
  %160 = or i64 %159, 1865
  %161 = trunc i64 %160 to i32
  store volatile i32 %161, ptr %157, align 4, !tbaa !33
  %162 = load ptr, ptr %5, align 8, !tbaa !5
  %163 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %162, i32 0, i32 1
  %164 = getelementptr inbounds %struct.SPI_InitTypeDef, ptr %163, i32 0, i32 0
  %165 = load i32, ptr %164, align 8, !tbaa !16
  %166 = zext i32 %165 to i64
  %167 = icmp eq i64 %166, 4194304
  br i1 %167, label %168, label %177

168:                                              ; preds = %130
  %169 = load ptr, ptr %5, align 8, !tbaa !5
  %170 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %169, i32 0, i32 0
  %171 = load ptr, ptr %170, align 8, !tbaa !29
  %172 = getelementptr inbounds %struct.SPI_TypeDef, ptr %171, i32 0, i32 0
  %173 = load volatile i32, ptr %172, align 4, !tbaa !30
  %174 = zext i32 %173 to i64
  %175 = or i64 %174, 512
  %176 = trunc i64 %175 to i32
  store volatile i32 %176, ptr %172, align 4, !tbaa !30
  br label %177

177:                                              ; preds = %168, %130
  br label %178

178:                                              ; preds = %177
  %179 = load ptr, ptr %5, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.__SPI_HandleTypeDef, ptr %179, i32 0, i32 13
  store i32 0, ptr %180, align 8, !tbaa !18
  br label %181

181:                                              ; preds = %178
  br label %182

182:                                              ; preds = %181
  %183 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %183, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %184

184:                                              ; preds = %182, %67, %53, %37, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %185 = load i32, ptr %4, align 4
  ret i32 %185
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_SPI_TransmitReceive_IT(ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_32BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_16BIT(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_8BIT(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 12}
!14 = !{!"__SPI_HandleTypeDef", !6, i64 0, !15, i64 8, !6, i64 96, !10, i64 104, !10, i64 106, !6, i64 112, !10, i64 120, !10, i64 122, !12, i64 124, !6, i64 128, !6, i64 136, !6, i64 144, !6, i64 152, !12, i64 160, !12, i64 164, !12, i64 168}
!15 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84}
!16 = !{!14, !12, i64 8}
!17 = !{!14, !12, i64 164}
!18 = !{!14, !12, i64 160}
!19 = !{!14, !12, i64 168}
!20 = !{!14, !6, i64 112}
!21 = !{!14, !10, i64 120}
!22 = !{!14, !10, i64 122}
!23 = !{!14, !6, i64 96}
!24 = !{!14, !10, i64 104}
!25 = !{!14, !10, i64 106}
!26 = !{!14, !6, i64 136}
!27 = !{!14, !12, i64 16}
!28 = !{!14, !6, i64 128}
!29 = !{!14, !6, i64 0}
!30 = !{!31, !12, i64 0}
!31 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !7, i64 36, !12, i64 48, !7, i64 52, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80}
!32 = !{!31, !12, i64 4}
!33 = !{!31, !12, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_SPI_Receive_IT(ptr noundef %0, ptr noundef %1, i16 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = getelementptr inbounds i8, ptr %0, i64 12
  %6 = load i32, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %8, label %14

8:                                                ; preds = %3
  %9 = load i32, ptr %4, align 8, !tbaa !13
  %10 = icmp eq i32 %9, 4194304
  br i1 %10, label %11, label %14

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 164
  store volatile i32 4, ptr %12, align 4, !tbaa !14
  %13 = tail call i32 @HAL_SPI_TransmitReceive_IT(ptr noundef nonnull %0, ptr noundef %1, ptr noundef %1, i16 noundef zeroext %2)
  br label %67

14:                                               ; preds = %3, %8
  %15 = getelementptr inbounds i8, ptr %0, i64 160
  %16 = load i32, ptr %15, align 8, !tbaa !15
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %67, label %18

18:                                               ; preds = %14
  %19 = getelementptr inbounds i8, ptr %0, i64 164
  %20 = load volatile i32, ptr %19, align 4, !tbaa !14
  %.not = icmp eq i32 %20, 1
  br i1 %.not, label %22, label %21

21:                                               ; preds = %18
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %67

22:                                               ; preds = %18
  %23 = icmp eq ptr %1, null
  %24 = icmp eq i16 %2, 0
  %or.cond = or i1 %23, %24
  br i1 %or.cond, label %25, label %26

25:                                               ; preds = %22
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %67

26:                                               ; preds = %22
  store volatile i32 4, ptr %19, align 4, !tbaa !14
  %27 = getelementptr inbounds i8, ptr %0, i64 168
  store volatile i32 0, ptr %27, align 8, !tbaa !16
  %28 = getelementptr inbounds i8, ptr %0, i64 112
  store ptr %1, ptr %28, align 8, !tbaa !17
  %29 = getelementptr inbounds i8, ptr %0, i64 120
  store i16 %2, ptr %29, align 8, !tbaa !18
  %30 = getelementptr inbounds i8, ptr %0, i64 122
  store volatile i16 %2, ptr %30, align 2, !tbaa !19
  %31 = getelementptr inbounds i8, ptr %0, i64 96
  store ptr null, ptr %31, align 8, !tbaa !20
  %32 = getelementptr inbounds i8, ptr %0, i64 104
  store i16 0, ptr %32, align 8, !tbaa !21
  %33 = getelementptr inbounds i8, ptr %0, i64 106
  store volatile i16 0, ptr %33, align 2, !tbaa !22
  %34 = getelementptr inbounds i8, ptr %0, i64 136
  store ptr null, ptr %34, align 8, !tbaa !23
  %35 = getelementptr inbounds i8, ptr %0, i64 16
  %36 = load i32, ptr %35, align 8, !tbaa !24
  %37 = icmp ugt i32 %36, 15
  br i1 %37, label %38, label %40

38:                                               ; preds = %26
  %39 = getelementptr inbounds i8, ptr %0, i64 128
  store ptr @SPI_RxISR_32BIT, ptr %39, align 8, !tbaa !25
  br label %45

40:                                               ; preds = %26
  %41 = icmp ugt i32 %36, 7
  %42 = getelementptr inbounds i8, ptr %0, i64 128
  br i1 %41, label %43, label %44

43:                                               ; preds = %40
  store ptr @SPI_RxISR_16BIT, ptr %42, align 8, !tbaa !25
  br label %45

44:                                               ; preds = %40
  store ptr @SPI_RxISR_8BIT, ptr %42, align 8, !tbaa !25
  br label %45

45:                                               ; preds = %43, %44, %38
  %46 = icmp eq i32 %6, 393216
  %.pre = load ptr, ptr %0, align 8, !tbaa !26
  br i1 %46, label %47, label %50

47:                                               ; preds = %45
  %48 = load volatile i32, ptr %.pre, align 4, !tbaa !27
  %49 = and i32 %48, -2049
  store volatile i32 %49, ptr %.pre, align 4, !tbaa !27
  br label %50

50:                                               ; preds = %47, %45
  %51 = getelementptr inbounds i8, ptr %.pre, i64 4
  %52 = load volatile i32, ptr %51, align 4, !tbaa !29
  %53 = and i32 %52, -65536
  %54 = zext i16 %2 to i32
  %55 = or disjoint i32 %53, %54
  store volatile i32 %55, ptr %51, align 4, !tbaa !29
  %56 = load volatile i32, ptr %.pre, align 4, !tbaa !27
  %57 = or i32 %56, 1
  store volatile i32 %57, ptr %.pre, align 4, !tbaa !27
  %58 = getelementptr inbounds i8, ptr %.pre, i64 16
  %59 = load volatile i32, ptr %58, align 4, !tbaa !30
  %60 = or i32 %59, 1865
  store volatile i32 %60, ptr %58, align 4, !tbaa !30
  %61 = load i32, ptr %4, align 8, !tbaa !13
  %62 = icmp eq i32 %61, 4194304
  br i1 %62, label %63, label %66

63:                                               ; preds = %50
  %64 = load volatile i32, ptr %.pre, align 4, !tbaa !27
  %65 = or i32 %64, 512
  store volatile i32 %65, ptr %.pre, align 4, !tbaa !27
  br label %66

66:                                               ; preds = %50, %63
  store i32 0, ptr %15, align 8, !tbaa !15
  br label %67

67:                                               ; preds = %14, %66, %25, %21, %11
  %.0 = phi i32 [ %13, %11 ], [ 2, %21 ], [ 1, %25 ], [ 0, %66 ], [ 2, %14 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @HAL_SPI_TransmitReceive_IT(ptr noundef, ptr noundef, ptr noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_32BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_16BIT(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @SPI_RxISR_8BIT(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 12}
!6 = !{!"__SPI_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 96, !12, i64 104, !12, i64 106, !7, i64 112, !12, i64 120, !12, i64 122, !11, i64 124, !7, i64 128, !7, i64 136, !7, i64 144, !7, i64 152, !11, i64 160, !11, i64 164, !11, i64 168}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84}
!11 = !{!"int", !8, i64 0}
!12 = !{!"short", !8, i64 0}
!13 = !{!6, !11, i64 8}
!14 = !{!6, !11, i64 164}
!15 = !{!6, !11, i64 160}
!16 = !{!6, !11, i64 168}
!17 = !{!6, !7, i64 112}
!18 = !{!6, !12, i64 120}
!19 = !{!6, !12, i64 122}
!20 = !{!6, !7, i64 96}
!21 = !{!6, !12, i64 104}
!22 = !{!6, !12, i64 106}
!23 = !{!6, !7, i64 136}
!24 = !{!6, !11, i64 16}
!25 = !{!6, !7, i64 128}
!26 = !{!6, !7, i64 0}
!27 = !{!28, !11, i64 0}
!28 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !8, i64 36, !11, i64 48, !8, i64 52, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80}
!29 = !{!28, !11, i64 4}
!30 = !{!28, !11, i64 16}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass