; LLVM IR from lzyrapx/Competitive-Programming :: ACdream/1017（网络流sap）.ll (Z11CreateGraphi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@n = external dso_local global i32, align 4
@K = external dso_local global i32, align 4
@s = external dso_local global i32, align 4
@t = external dso_local global i32, align 4
@S = external dso_local global i32, align 4
@T = external dso_local global i32, align 4
@N = external dso_local global i32, align 4
@head = external dso_local global [50010 x i32], align 16
@idx = external dso_local global i32, align 4
@mp = external dso_local global [120 x [120 x i8]], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiii(i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z11CreateGraphi(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.memset.p0.i64(ptr align 16 @head, i8 -1, i64 200040, i1 false)
  store i32 0, ptr @idx, align 4, !tbaa !5
  store i32 0, ptr @S, align 4, !tbaa !5
  %10 = load i32, ptr %2, align 4, !tbaa !5
  %11 = add nsw i32 %10, 1
  %12 = load i32, ptr @n, align 4, !tbaa !5
  %13 = mul nsw i32 %11, %12
  %14 = add nsw i32 %13, 1
  store i32 %14, ptr @T, align 4, !tbaa !5
  %15 = load i32, ptr %2, align 4, !tbaa !5
  %16 = add nsw i32 %15, 1
  %17 = load i32, ptr @n, align 4, !tbaa !5
  %18 = mul nsw i32 %16, %17
  %19 = add nsw i32 %18, 2
  store i32 %19, ptr @N, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 1, ptr %3, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %67, %1
  %21 = load i32, ptr %3, align 4, !tbaa !5
  %22 = load i32, ptr @n, align 4, !tbaa !5
  %23 = icmp sle i32 %21, %22
  br i1 %23, label %25, label %24

24:                                               ; preds = %20
  store i32 2, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %70

25:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 1, ptr %5, align 4, !tbaa !5
  br label %26

26:                                               ; preds = %63, %25
  %27 = load i32, ptr %5, align 4, !tbaa !5
  %28 = load i32, ptr @n, align 4, !tbaa !5
  %29 = icmp sle i32 %27, %28
  br i1 %29, label %31, label %30

30:                                               ; preds = %26
  store i32 5, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %66

31:                                               ; preds = %26
  %32 = load i32, ptr %3, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = getelementptr inbounds [120 x [120 x i8]], ptr @mp, i64 0, i64 %33
  %35 = load i32, ptr %5, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds [120 x i8], ptr %34, i64 0, i64 %36
  %38 = load i8, ptr %37, align 1, !tbaa !9, !range !11, !noundef !12
  %39 = trunc i8 %38 to i1
  br i1 %39, label %40, label %62

40:                                               ; preds = %31
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 1, ptr %6, align 4, !tbaa !5
  br label %41

41:                                               ; preds = %58, %40
  %42 = load i32, ptr %6, align 4, !tbaa !5
  %43 = load i32, ptr %2, align 4, !tbaa !5
  %44 = icmp sle i32 %42, %43
  br i1 %44, label %46, label %45

45:                                               ; preds = %41
  store i32 8, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %61

46:                                               ; preds = %41
  %47 = load i32, ptr %6, align 4, !tbaa !5
  %48 = sub nsw i32 %47, 1
  %49 = load i32, ptr @n, align 4, !tbaa !5
  %50 = mul nsw i32 %48, %49
  %51 = load i32, ptr %3, align 4, !tbaa !5
  %52 = add nsw i32 %50, %51
  %53 = load i32, ptr %6, align 4, !tbaa !5
  %54 = load i32, ptr @n, align 4, !tbaa !5
  %55 = mul nsw i32 %53, %54
  %56 = load i32, ptr %5, align 4, !tbaa !5
  %57 = add nsw i32 %55, %56
  call void @_Z7addEdgeiii(i32 noundef %52, i32 noundef %57, i32 noundef 1)
  br label %58

58:                                               ; preds = %46
  %59 = load i32, ptr %6, align 4, !tbaa !5
  %60 = add nsw i32 %59, 1
  store i32 %60, ptr %6, align 4, !tbaa !5
  br label %41, !llvm.loop !13

61:                                               ; preds = %45
  br label %62

62:                                               ; preds = %61, %31
  br label %63

63:                                               ; preds = %62
  %64 = load i32, ptr %5, align 4, !tbaa !5
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %5, align 4, !tbaa !5
  br label %26, !llvm.loop !15

66:                                               ; preds = %30
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %3, align 4, !tbaa !5
  %69 = add nsw i32 %68, 1
  store i32 %69, ptr %3, align 4, !tbaa !5
  br label %20, !llvm.loop !16

70:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %71

71:                                               ; preds = %98, %70
  %72 = load i32, ptr %7, align 4, !tbaa !5
  %73 = load i32, ptr @n, align 4, !tbaa !5
  %74 = icmp sle i32 %72, %73
  br i1 %74, label %76, label %75

75:                                               ; preds = %71
  store i32 11, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %101

76:                                               ; preds = %71
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 1, ptr %8, align 4, !tbaa !5
  br label %77

77:                                               ; preds = %94, %76
  %78 = load i32, ptr %8, align 4, !tbaa !5
  %79 = load i32, ptr %2, align 4, !tbaa !5
  %80 = icmp sle i32 %78, %79
  br i1 %80, label %82, label %81

81:                                               ; preds = %77
  store i32 14, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %97

82:                                               ; preds = %77
  %83 = load i32, ptr %8, align 4, !tbaa !5
  %84 = sub nsw i32 %83, 1
  %85 = load i32, ptr @n, align 4, !tbaa !5
  %86 = mul nsw i32 %84, %85
  %87 = load i32, ptr %7, align 4, !tbaa !5
  %88 = add nsw i32 %86, %87
  %89 = load i32, ptr %8, align 4, !tbaa !5
  %90 = load i32, ptr @n, align 4, !tbaa !5
  %91 = mul nsw i32 %89, %90
  %92 = load i32, ptr %7, align 4, !tbaa !5
  %93 = add nsw i32 %91, %92
  call void @_Z7addEdgeiii(i32 noundef %88, i32 noundef %93, i32 noundef 1000000000)
  br label %94

94:                                               ; preds = %82
  %95 = load i32, ptr %8, align 4, !tbaa !5
  %96 = add nsw i32 %95, 1
  store i32 %96, ptr %8, align 4, !tbaa !5
  br label %77, !llvm.loop !17

97:                                               ; preds = %81
  br label %98

98:                                               ; preds = %97
  %99 = load i32, ptr %7, align 4, !tbaa !5
  %100 = add nsw i32 %99, 1
  store i32 %100, ptr %7, align 4, !tbaa !5
  br label %71, !llvm.loop !18

101:                                              ; preds = %75
  %102 = load i32, ptr @S, align 4, !tbaa !5
  %103 = load i32, ptr @s, align 4, !tbaa !5
  %104 = load i32, ptr @K, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef %102, i32 noundef %103, i32 noundef %104)
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 1, ptr %9, align 4, !tbaa !5
  br label %105

105:                                              ; preds = %117, %101
  %106 = load i32, ptr %9, align 4, !tbaa !5
  %107 = load i32, ptr %2, align 4, !tbaa !5
  %108 = icmp sle i32 %106, %107
  br i1 %108, label %110, label %109

109:                                              ; preds = %105
  store i32 17, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %120

110:                                              ; preds = %105
  %111 = load i32, ptr %9, align 4, !tbaa !5
  %112 = load i32, ptr @n, align 4, !tbaa !5
  %113 = mul nsw i32 %111, %112
  %114 = load i32, ptr @t, align 4, !tbaa !5
  %115 = add nsw i32 %113, %114
  %116 = load i32, ptr @T, align 4, !tbaa !5
  call void @_Z7addEdgeiii(i32 noundef %115, i32 noundef %116, i32 noundef 1000000000)
  br label %117

117:                                              ; preds = %110
  %118 = load i32, ptr %9, align 4, !tbaa !5
  %119 = add nsw i32 %118, 1
  store i32 %119, ptr %9, align 4, !tbaa !5
  br label %105, !llvm.loop !19

120:                                              ; preds = %109
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}
!18 = distinct !{!18, !14}
!19 = distinct !{!19, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@n = external dso_local local_unnamed_addr global i32, align 4
@K = external dso_local local_unnamed_addr global i32, align 4
@s = external dso_local local_unnamed_addr global i32, align 4
@t = external dso_local local_unnamed_addr global i32, align 4
@S = external dso_local local_unnamed_addr global i32, align 4
@T = external dso_local local_unnamed_addr global i32, align 4
@N = external dso_local local_unnamed_addr global i32, align 4
@head = external dso_local local_unnamed_addr global [50010 x i32], align 16
@idx = external dso_local local_unnamed_addr global i32, align 4
@mp = external dso_local local_unnamed_addr global [120 x [120 x i8]], align 16

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z7addEdgeiii(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z11CreateGraphi(i32 noundef %0) local_unnamed_addr #0 {
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(200040) @head, i8 -1, i64 200040, i1 false)
  store i32 0, ptr @idx, align 4, !tbaa !5
  store i32 0, ptr @S, align 4, !tbaa !5
  %2 = add i32 %0, 1
  %3 = load i32, ptr @n, align 4, !tbaa !5
  %4 = mul nsw i32 %3, %2
  %5 = add nsw i32 %4, 1
  store i32 %5, ptr @T, align 4, !tbaa !5
  %6 = add nsw i32 %4, 2
  store i32 %6, ptr @N, align 4, !tbaa !5
  %.not47 = icmp slt i32 %3, 1
  br i1 %.not47, label %._crit_edge55, label %.preheader40.preheader

.preheader40.preheader:                           ; preds = %1
  %.not3741 = icmp slt i32 %0, 1
  br label %.preheader40

.preheader40:                                     ; preds = %.preheader40.preheader, %._crit_edge
  %7 = phi i32 [ %3, %.preheader40.preheader ], [ %10, %._crit_edge ]
  %indvars.iv64 = phi i64 [ 1, %.preheader40.preheader ], [ %indvars.iv.next65, %._crit_edge ]
  %.not3643 = icmp slt i32 %7, 1
  %brmerge = or i1 %.not3643, %.not3741
  br i1 %brmerge, label %._crit_edge, label %.lr.ph46.split.preheader

.lr.ph46.split.preheader:                         ; preds = %.preheader40
  %8 = trunc nuw nsw i64 %indvars.iv64 to i32
  br label %.lr.ph46.split

.preheader38:                                     ; preds = %._crit_edge
  %9 = icmp slt i32 %10, 1
  %.not3550 = icmp slt i32 %0, 1
  %or.cond = or i1 %9, %.not3550
  br i1 %or.cond, label %._crit_edge55, label %.preheader

._crit_edge:                                      ; preds = %..loopexit_crit_edge, %.preheader40
  %10 = phi i32 [ %7, %.preheader40 ], [ %25, %..loopexit_crit_edge ]
  %indvars.iv.next65 = add nuw nsw i64 %indvars.iv64, 1
  %11 = sext i32 %10 to i64
  %.not.not = icmp slt i64 %indvars.iv64, %11
  br i1 %.not.not, label %.preheader40, label %.preheader38, !llvm.loop !9

.lr.ph46.split:                                   ; preds = %.lr.ph46.split.preheader, %..loopexit_crit_edge
  %12 = phi i32 [ %7, %.lr.ph46.split.preheader ], [ %25, %..loopexit_crit_edge ]
  %13 = phi i32 [ %7, %.lr.ph46.split.preheader ], [ %26, %..loopexit_crit_edge ]
  %indvars.iv = phi i64 [ 1, %.lr.ph46.split.preheader ], [ %indvars.iv.next, %..loopexit_crit_edge ]
  %14 = getelementptr inbounds [120 x [120 x i8]], ptr @mp, i64 0, i64 %indvars.iv64, i64 %indvars.iv
  %15 = load i8, ptr %14, align 1, !tbaa !12, !range !14, !noundef !15
  %16 = trunc nuw i8 %15 to i1
  br i1 %16, label %.preheader39.preheader, label %..loopexit_crit_edge

.preheader39.preheader:                           ; preds = %.lr.ph46.split
  %17 = trunc nuw nsw i64 %indvars.iv to i32
  br label %.preheader39

.preheader39:                                     ; preds = %.preheader39.preheader, %.preheader39
  %.03042 = phi i32 [ %24, %.preheader39 ], [ 1, %.preheader39.preheader ]
  %18 = add nsw i32 %.03042, -1
  %19 = load i32, ptr @n, align 4, !tbaa !5
  %20 = mul nsw i32 %19, %18
  %21 = add nsw i32 %20, %8
  %22 = mul nsw i32 %19, %.03042
  %23 = add nsw i32 %22, %17
  tail call void @_Z7addEdgeiii(i32 noundef %21, i32 noundef %23, i32 noundef 1)
  %24 = add nuw i32 %.03042, 1
  %exitcond.not = icmp eq i32 %.03042, %0
  br i1 %exitcond.not, label %..loopexit_crit_edge.loopexit, label %.preheader39, !llvm.loop !16

..loopexit_crit_edge.loopexit:                    ; preds = %.preheader39
  %.pre = load i32, ptr @n, align 4, !tbaa !5
  br label %..loopexit_crit_edge

..loopexit_crit_edge:                             ; preds = %..loopexit_crit_edge.loopexit, %.lr.ph46.split
  %25 = phi i32 [ %.pre, %..loopexit_crit_edge.loopexit ], [ %12, %.lr.ph46.split ]
  %26 = phi i32 [ %.pre, %..loopexit_crit_edge.loopexit ], [ %13, %.lr.ph46.split ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %27 = sext i32 %26 to i64
  %.not36.not = icmp slt i64 %indvars.iv, %27
  br i1 %.not36.not, label %.lr.ph46.split, label %._crit_edge, !llvm.loop !17

.preheader:                                       ; preds = %.preheader38, %._crit_edge52
  %.02954 = phi i32 [ %31, %._crit_edge52 ], [ 1, %.preheader38 ]
  br label %33

._crit_edge55:                                    ; preds = %._crit_edge52, %1, %.preheader38
  %28 = load i32, ptr @S, align 4, !tbaa !5
  %29 = load i32, ptr @s, align 4, !tbaa !5
  %30 = load i32, ptr @K, align 4, !tbaa !5
  tail call void @_Z7addEdgeiii(i32 noundef %28, i32 noundef %29, i32 noundef %30)
  %.not3456 = icmp slt i32 %0, 1
  br i1 %.not3456, label %._crit_edge59, label %.lr.ph

._crit_edge52:                                    ; preds = %33
  %31 = add nuw nsw i32 %.02954, 1
  %32 = load i32, ptr @n, align 4, !tbaa !5
  %.not33.not = icmp slt i32 %.02954, %32
  br i1 %.not33.not, label %.preheader, label %._crit_edge55, !llvm.loop !18

33:                                               ; preds = %.preheader, %33
  %.02851 = phi i32 [ 1, %.preheader ], [ %40, %33 ]
  %34 = add nsw i32 %.02851, -1
  %35 = load i32, ptr @n, align 4, !tbaa !5
  %36 = mul nsw i32 %35, %34
  %37 = add nsw i32 %36, %.02954
  %38 = mul nsw i32 %35, %.02851
  %39 = add nsw i32 %38, %.02954
  tail call void @_Z7addEdgeiii(i32 noundef %37, i32 noundef %39, i32 noundef 1000000000)
  %40 = add nuw i32 %.02851, 1
  %exitcond67.not = icmp eq i32 %.02851, %0
  br i1 %exitcond67.not, label %._crit_edge52, label %33, !llvm.loop !19

._crit_edge59:                                    ; preds = %.lr.ph, %._crit_edge55
  ret void

.lr.ph:                                           ; preds = %._crit_edge55, %.lr.ph
  %.057 = phi i32 [ %46, %.lr.ph ], [ 1, %._crit_edge55 ]
  %41 = load i32, ptr @n, align 4, !tbaa !5
  %42 = mul nsw i32 %41, %.057
  %43 = load i32, ptr @t, align 4, !tbaa !5
  %44 = add nsw i32 %42, %43
  %45 = load i32, ptr @T, align 4, !tbaa !5
  tail call void @_Z7addEdgeiii(i32 noundef %44, i32 noundef %45, i32 noundef 1000000000)
  %46 = add nuw i32 %.057, 1
  %exitcond68.not = icmp eq i32 %.057, %0
  br i1 %exitcond68.not, label %._crit_edge59, label %.lr.ph, !llvm.loop !20
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10, !11}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!"llvm.loop.unswitch.partial.disable"}
!12 = !{!13, !13, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = !{i8 0, i8 2}
!15 = !{}
!16 = distinct !{!16, !10}
!17 = distinct !{!17, !10}
!18 = distinct !{!18, !10}
!19 = distinct !{!19, !10}
!20 = distinct !{!20, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass