; LLVM IR from lichen-community-systems/signaletic :: hosts/daisy/vendor/libDaisy/Drivers/STM32H7xx_HAL_Driver/Src (Init)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__DMA2D_HandleTypeDef = type { ptr, %struct.DMA2D_InitTypeDef, ptr, ptr, [2 x %struct.DMA2D_LayerCfgTypeDef], i32, i32, i32 }
%struct.DMA2D_InitTypeDef = type { i32, i32, i32, i32, i32 }
%struct.DMA2D_LayerCfgTypeDef = type { i32, i32, i32, i32, i32, i32, i32 }
%struct.DMA2D_TypeDef = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [236 x i32], [256 x i32], [256 x i32] }

; Function Attrs: nounwind uwtable
define dso_local i32 @HAL_DMA2D_Init(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %4 = load ptr, ptr %3, align 8, !tbaa !5
  %5 = icmp eq ptr %4, null
  br i1 %5, label %6, label %7

6:                                                ; preds = %1
  store i32 1, ptr %2, align 4
  br label %102

7:                                                ; preds = %1
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %8, i32 0, i32 6
  %10 = load volatile i32, ptr %9, align 4, !tbaa !9
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %16

12:                                               ; preds = %7
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %13, i32 0, i32 5
  store i32 0, ptr %14, align 8, !tbaa !13
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  call void @HAL_DMA2D_MspInit(ptr noundef %15)
  br label %16

16:                                               ; preds = %12, %7
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %17, i32 0, i32 6
  store volatile i32 2, ptr %18, align 4, !tbaa !9
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %19, i32 0, i32 0
  %21 = load ptr, ptr %20, align 8, !tbaa !14
  %22 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %21, i32 0, i32 0
  %23 = load volatile i32, ptr %22, align 4, !tbaa !15
  %24 = zext i32 %23 to i64
  %25 = and i64 %24, -196609
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %26, i32 0, i32 1
  %28 = getelementptr inbounds %struct.DMA2D_InitTypeDef, ptr %27, i32 0, i32 0
  %29 = load i32, ptr %28, align 8, !tbaa !17
  %30 = zext i32 %29 to i64
  %31 = or i64 %25, %30
  %32 = trunc i64 %31 to i32
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !14
  %36 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %35, i32 0, i32 0
  store volatile i32 %32, ptr %36, align 4, !tbaa !15
  %37 = load ptr, ptr %3, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !14
  %40 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %39, i32 0, i32 13
  %41 = load volatile i32, ptr %40, align 4, !tbaa !18
  %42 = zext i32 %41 to i64
  %43 = and i64 %42, -8
  %44 = load ptr, ptr %3, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %44, i32 0, i32 1
  %46 = getelementptr inbounds %struct.DMA2D_InitTypeDef, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !19
  %48 = zext i32 %47 to i64
  %49 = or i64 %43, %48
  %50 = trunc i64 %49 to i32
  %51 = load ptr, ptr %3, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %51, i32 0, i32 0
  %53 = load ptr, ptr %52, align 8, !tbaa !14
  %54 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %53, i32 0, i32 13
  store volatile i32 %50, ptr %54, align 4, !tbaa !18
  %55 = load ptr, ptr %3, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %55, i32 0, i32 0
  %57 = load ptr, ptr %56, align 8, !tbaa !14
  %58 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %57, i32 0, i32 16
  %59 = load volatile i32, ptr %58, align 4, !tbaa !20
  %60 = zext i32 %59 to i64
  %61 = and i64 %60, -16384
  %62 = load ptr, ptr %3, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %62, i32 0, i32 1
  %64 = getelementptr inbounds %struct.DMA2D_InitTypeDef, ptr %63, i32 0, i32 2
  %65 = load i32, ptr %64, align 8, !tbaa !21
  %66 = zext i32 %65 to i64
  %67 = or i64 %61, %66
  %68 = trunc i64 %67 to i32
  %69 = load ptr, ptr %3, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %69, i32 0, i32 0
  %71 = load ptr, ptr %70, align 8, !tbaa !14
  %72 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %71, i32 0, i32 16
  store volatile i32 %68, ptr %72, align 4, !tbaa !20
  %73 = load ptr, ptr %3, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %73, i32 0, i32 0
  %75 = load ptr, ptr %74, align 8, !tbaa !14
  %76 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %75, i32 0, i32 13
  %77 = load volatile i32, ptr %76, align 4, !tbaa !18
  %78 = zext i32 %77 to i64
  %79 = and i64 %78, -3145729
  %80 = load ptr, ptr %3, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %80, i32 0, i32 1
  %82 = getelementptr inbounds %struct.DMA2D_InitTypeDef, ptr %81, i32 0, i32 3
  %83 = load i32, ptr %82, align 4, !tbaa !22
  %84 = shl i32 %83, 20
  %85 = load ptr, ptr %3, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %85, i32 0, i32 1
  %87 = getelementptr inbounds %struct.DMA2D_InitTypeDef, ptr %86, i32 0, i32 4
  %88 = load i32, ptr %87, align 8, !tbaa !23
  %89 = shl i32 %88, 21
  %90 = or i32 %84, %89
  %91 = zext i32 %90 to i64
  %92 = or i64 %79, %91
  %93 = trunc i64 %92 to i32
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %94, i32 0, i32 0
  %96 = load ptr, ptr %95, align 8, !tbaa !14
  %97 = getelementptr inbounds %struct.DMA2D_TypeDef, ptr %96, i32 0, i32 13
  store volatile i32 %93, ptr %97, align 4, !tbaa !18
  %98 = load ptr, ptr %3, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %98, i32 0, i32 7
  store volatile i32 0, ptr %99, align 8, !tbaa !24
  %100 = load ptr, ptr %3, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.__DMA2D_HandleTypeDef, ptr %100, i32 0, i32 6
  store volatile i32 1, ptr %101, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  br label %102

102:                                              ; preds = %16, %6
  %103 = load i32, ptr %2, align 4
  ret i32 %103
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_DMA2D_MspInit(ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 108}
!10 = !{!"__DMA2D_HandleTypeDef", !6, i64 0, !11, i64 8, !6, i64 32, !6, i64 40, !7, i64 48, !12, i64 104, !12, i64 108, !12, i64 112}
!11 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !12, i64 104}
!14 = !{!10, !6, i64 0}
!15 = !{!16, !12, i64 0}
!16 = !{!"", !12, i64 0, !12, i64 4, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !7, i64 80, !7, i64 1024, !7, i64 2048}
!17 = !{!10, !12, i64 8}
!18 = !{!16, !12, i64 52}
!19 = !{!10, !12, i64 12}
!20 = !{!16, !12, i64 64}
!21 = !{!10, !12, i64 16}
!22 = !{!10, !12, i64 20}
!23 = !{!10, !12, i64 24}
!24 = !{!10, !12, i64 112}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @HAL_DMA2D_Init(ptr noundef %0) local_unnamed_addr #0 {
  %2 = icmp eq ptr %0, null
  br i1 %2, label %39, label %3

3:                                                ; preds = %1
  %4 = getelementptr inbounds i8, ptr %0, i64 108
  %5 = load volatile i32, ptr %4, align 4, !tbaa !5
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %7, label %9

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 104
  store i32 0, ptr %8, align 8, !tbaa !12
  tail call void @HAL_DMA2D_MspInit(ptr noundef nonnull %0)
  br label %9

9:                                                ; preds = %7, %3
  store volatile i32 2, ptr %4, align 4, !tbaa !5
  %10 = load ptr, ptr %0, align 8, !tbaa !13
  %11 = load volatile i32, ptr %10, align 4, !tbaa !14
  %12 = and i32 %11, -196609
  %13 = getelementptr inbounds i8, ptr %0, i64 8
  %14 = load i32, ptr %13, align 8, !tbaa !16
  %15 = or i32 %12, %14
  store volatile i32 %15, ptr %10, align 4, !tbaa !14
  %16 = getelementptr inbounds i8, ptr %10, i64 52
  %17 = load volatile i32, ptr %16, align 4, !tbaa !17
  %18 = and i32 %17, -8
  %19 = getelementptr inbounds i8, ptr %0, i64 12
  %20 = load i32, ptr %19, align 4, !tbaa !18
  %21 = or i32 %18, %20
  store volatile i32 %21, ptr %16, align 4, !tbaa !17
  %22 = getelementptr inbounds i8, ptr %10, i64 64
  %23 = load volatile i32, ptr %22, align 4, !tbaa !19
  %24 = and i32 %23, -16384
  %25 = getelementptr inbounds i8, ptr %0, i64 16
  %26 = load i32, ptr %25, align 8, !tbaa !20
  %27 = or i32 %24, %26
  store volatile i32 %27, ptr %22, align 4, !tbaa !19
  %28 = load volatile i32, ptr %16, align 4, !tbaa !17
  %29 = and i32 %28, -3145729
  %30 = getelementptr inbounds i8, ptr %0, i64 20
  %31 = load i32, ptr %30, align 4, !tbaa !21
  %32 = shl i32 %31, 20
  %33 = getelementptr inbounds i8, ptr %0, i64 24
  %34 = load i32, ptr %33, align 8, !tbaa !22
  %35 = shl i32 %34, 21
  %36 = or i32 %32, %29
  %37 = or i32 %36, %35
  store volatile i32 %37, ptr %16, align 4, !tbaa !17
  %38 = getelementptr inbounds i8, ptr %0, i64 112
  store volatile i32 0, ptr %38, align 8, !tbaa !23
  store volatile i32 1, ptr %4, align 4, !tbaa !5
  br label %39

39:                                               ; preds = %1, %9
  %.0 = phi i32 [ 0, %9 ], [ 1, %1 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local void @HAL_DMA2D_MspInit(ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 108}
!6 = !{!"__DMA2D_HandleTypeDef", !7, i64 0, !10, i64 8, !7, i64 32, !7, i64 40, !8, i64 48, !11, i64 104, !11, i64 108, !11, i64 112}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16}
!11 = !{!"int", !8, i64 0}
!12 = !{!6, !11, i64 104}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !11, i64 0}
!15 = !{!"", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !8, i64 80, !8, i64 1024, !8, i64 2048}
!16 = !{!6, !11, i64 8}
!17 = !{!15, !11, i64 52}
!18 = !{!6, !11, i64 12}
!19 = !{!15, !11, i64 64}
!20 = !{!6, !11, i64 16}
!21 = !{!6, !11, i64 20}
!22 = !{!6, !11, i64 24}
!23 = !{!6, !11, i64 112}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass