; LLVM IR from lzyrapx/Competitive-Programming :: HDUOJ (2016)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [4 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [4 x i8], align 1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca [100 x i32], align 16
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
  call void @llvm.lifetime.start.p0(i64 400, ptr %3) #5
  call void @llvm.memset.p0.i64(ptr align 16 %3, i8 0, i64 400, i1 false)
  br label %6

6:                                                ; preds = %74, %0
  %7 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %2)
  %8 = xor i32 %7, -1
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = icmp ne i32 %9, 0
  br i1 %10, label %11, label %75

11:                                               ; preds = %6
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %21, %11
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = load i32, ptr %2, align 4, !tbaa !5
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %16, label %24

16:                                               ; preds = %12
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = sext i32 %17 to i64
  %19 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %18
  %20 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef @.str, ptr noundef %19)
  br label %21

21:                                               ; preds = %16
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = add nsw i32 %22, 1
  store i32 %23, ptr %4, align 4, !tbaa !5
  br label %12, !llvm.loop !9

24:                                               ; preds = %12
  store i32 0, ptr %5, align 4, !tbaa !5
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %25

25:                                               ; preds = %41, %24
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = load i32, ptr %2, align 4, !tbaa !5
  %28 = icmp slt i32 %26, %27
  br i1 %28, label %29, label %44

29:                                               ; preds = %25
  %30 = load i32, ptr %4, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %31
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = load i32, ptr %5, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %35
  %37 = load i32, ptr %36, align 4, !tbaa !5
  %38 = icmp sle i32 %33, %37
  br i1 %38, label %39, label %40

39:                                               ; preds = %29
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5) #5
  br label %40

40:                                               ; preds = %39, %29
  br label %41

41:                                               ; preds = %40
  %42 = load i32, ptr %4, align 4, !tbaa !5
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %4, align 4, !tbaa !5
  br label %25, !llvm.loop !11

44:                                               ; preds = %25
  %45 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 0
  %46 = load i32, ptr %5, align 4, !tbaa !5
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %47
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %45, ptr noundef nonnull align 4 dereferenceable(4) %48) #5
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %49

49:                                               ; preds = %71, %44
  %50 = load i32, ptr %4, align 4, !tbaa !5
  %51 = load i32, ptr %2, align 4, !tbaa !5
  %52 = icmp slt i32 %50, %51
  br i1 %52, label %53, label %74

53:                                               ; preds = %49
  %54 = load i32, ptr %4, align 4, !tbaa !5
  %55 = load i32, ptr %2, align 4, !tbaa !5
  %56 = sub nsw i32 %55, 1
  %57 = icmp eq i32 %54, %56
  br i1 %57, label %58, label %64

58:                                               ; preds = %53
  %59 = load i32, ptr %4, align 4, !tbaa !5
  %60 = sext i32 %59 to i64
  %61 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %60
  %62 = load i32, ptr %61, align 4, !tbaa !5
  %63 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, i32 noundef %62)
  br label %70

64:                                               ; preds = %53
  %65 = load i32, ptr %4, align 4, !tbaa !5
  %66 = sext i32 %65 to i64
  %67 = getelementptr inbounds [100 x i32], ptr %3, i64 0, i64 %66
  %68 = load i32, ptr %67, align 4, !tbaa !5
  %69 = call i32 (ptr, ...) @printf(ptr noundef @.str.2, i32 noundef %68)
  br label %70

70:                                               ; preds = %64, %58
  br label %71

71:                                               ; preds = %70
  %72 = load i32, ptr %4, align 4, !tbaa !5
  %73 = add nsw i32 %72, 1
  store i32 %73, ptr %4, align 4, !tbaa !5
  br label %49, !llvm.loop !12

74:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  br label %6, !llvm.loop !13

75:                                               ; preds = %6
  call void @llvm.lifetime.end.p0(i64 400, ptr %3) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

declare i32 @__isoc99_scanf(ptr noundef, ...) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #4

declare i32 @printf(ptr noundef, ...) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [3 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [4 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [4 x i8], align 1

; Function Attrs: mustprogress norecurse nounwind uwtable
define dso_local noundef i32 @main() local_unnamed_addr #0 {
  %1 = alloca i32, align 4
  %2 = alloca [100 x i32], align 16
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #5
  call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %2) #5
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(400) %2, i8 0, i64 400, i1 false)
  %5 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %1)
  %6 = load i32, ptr %1, align 4, !tbaa !5
  %.not16 = icmp eq i32 %6, 0
  br i1 %.not16, label %._crit_edge19, label %.lr.ph18

.lr.ph18:                                         ; preds = %0, %._crit_edge15
  %7 = phi i32 [ %48, %._crit_edge15 ], [ %6, %0 ]
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #5
  store i32 0, ptr %3, align 4, !tbaa !5
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %.lr.ph, label %._crit_edge.thread

._crit_edge.thread:                               ; preds = %.lr.ph18
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %._crit_edge11

.lr.ph:                                           ; preds = %.lr.ph18, %.lr.ph
  %storemerge7 = phi i32 [ %13, %.lr.ph ], [ 0, %.lr.ph18 ]
  %9 = sext i32 %storemerge7 to i64
  %10 = getelementptr inbounds [100 x i32], ptr %2, i64 0, i64 %9
  %11 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %10)
  %12 = load i32, ptr %3, align 4, !tbaa !5
  %13 = add nsw i32 %12, 1
  store i32 %13, ptr %3, align 4, !tbaa !5
  %14 = load i32, ptr %1, align 4, !tbaa !5
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %.lr.ph, label %._crit_edge, !llvm.loop !9

._crit_edge:                                      ; preds = %.lr.ph
  store i32 0, ptr %4, align 4, !tbaa !5
  store i32 0, ptr %3, align 4, !tbaa !5
  %16 = icmp sgt i32 %14, 0
  br i1 %16, label %.lr.ph10, label %._crit_edge11

.lr.ph10:                                         ; preds = %._crit_edge, %26
  %17 = phi i32 [ %27, %26 ], [ %14, %._crit_edge ]
  %storemerge48 = phi i32 [ %29, %26 ], [ 0, %._crit_edge ]
  %18 = sext i32 %storemerge48 to i64
  %19 = getelementptr inbounds [100 x i32], ptr %2, i64 0, i64 %18
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = load i32, ptr %4, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds [100 x i32], ptr %2, i64 0, i64 %22
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %.not6 = icmp sgt i32 %20, %24
  br i1 %.not6, label %26, label %25

25:                                               ; preds = %.lr.ph10
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4) #5
  %.pre = load i32, ptr %3, align 4, !tbaa !5
  %.pre20 = load i32, ptr %1, align 4, !tbaa !5
  br label %26

26:                                               ; preds = %.lr.ph10, %25
  %27 = phi i32 [ %17, %.lr.ph10 ], [ %.pre20, %25 ]
  %28 = phi i32 [ %storemerge48, %.lr.ph10 ], [ %.pre, %25 ]
  %29 = add nsw i32 %28, 1
  store i32 %29, ptr %3, align 4, !tbaa !5
  %30 = icmp slt i32 %29, %27
  br i1 %30, label %.lr.ph10, label %._crit_edge11.loopexit, !llvm.loop !11

._crit_edge11.loopexit:                           ; preds = %26
  %.pre21 = load i32, ptr %4, align 4, !tbaa !5
  br label %._crit_edge11

._crit_edge11:                                    ; preds = %._crit_edge.thread, %._crit_edge11.loopexit, %._crit_edge
  %31 = phi i32 [ %.pre21, %._crit_edge11.loopexit ], [ 0, %._crit_edge ], [ 0, %._crit_edge.thread ]
  %32 = sext i32 %31 to i64
  %33 = getelementptr inbounds [100 x i32], ptr %2, i64 0, i64 %32
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %33) #5
  store i32 0, ptr %3, align 4, !tbaa !5
  %34 = load i32, ptr %1, align 4, !tbaa !5
  %35 = icmp sgt i32 %34, 0
  br i1 %35, label %.lr.ph14, label %._crit_edge15

.lr.ph14:                                         ; preds = %._crit_edge11, %.lr.ph14
  %36 = phi i32 [ %45, %.lr.ph14 ], [ %34, %._crit_edge11 ]
  %storemerge512 = phi i32 [ %44, %.lr.ph14 ], [ 0, %._crit_edge11 ]
  %37 = add nsw i32 %36, -1
  %38 = icmp eq i32 %storemerge512, %37
  %39 = sext i32 %storemerge512 to i64
  %40 = getelementptr inbounds [100 x i32], ptr %2, i64 0, i64 %39
  %41 = load i32, ptr %40, align 4, !tbaa !5
  %.str.1..str.2 = select i1 %38, ptr @.str.1, ptr @.str.2
  %42 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) %.str.1..str.2, i32 noundef %41)
  %43 = load i32, ptr %3, align 4, !tbaa !5
  %44 = add nsw i32 %43, 1
  store i32 %44, ptr %3, align 4, !tbaa !5
  %45 = load i32, ptr %1, align 4, !tbaa !5
  %46 = icmp slt i32 %44, %45
  br i1 %46, label %.lr.ph14, label %._crit_edge15, !llvm.loop !12

._crit_edge15:                                    ; preds = %.lr.ph14, %._crit_edge11
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #5
  %47 = call i32 (ptr, ...) @__isoc99_scanf(ptr noundef nonnull @.str, ptr noundef nonnull %1)
  %48 = load i32, ptr %1, align 4, !tbaa !5
  %.not = icmp eq i32 %48, 0
  br i1 %.not, label %._crit_edge19, label %.lr.ph18, !llvm.loop !13

._crit_edge19:                                    ; preds = %._crit_edge15, %0
  call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %2) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1) #5
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: nofree nounwind
declare noundef i32 @__isoc99_scanf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #4

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress norecurse nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass