; LLVM IR from stonne-simulator/omega :: omega-code/stonne/src/OSMeshSDMemory.ll (ZN14OSMeshSDMemoryD2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.OSMeshSDMemory = type { %class.MemoryController, ptr, ptr, ptr, i32, i32, i32, i32, i32, ptr, i32, %"class.std::vector", %"class.std::vector.3", %"class.std::vector.8", i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, %"class.std::vector.13", %"class.std::vector.13", ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, %"class.std::vector.8", i32, %class.SDMemoryStats }
%class.MemoryController = type { %class.Unit }
%class.Unit = type { ptr, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl" }
%"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl" = type { %"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl_data" }
%"struct.std::_Vector_base<SparseVN, std::allocator<SparseVN>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Fifo *, std::allocator<Fifo *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.SDMemoryStats = type { %class.Stats, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3" }
%class.Stats = type { ptr }

@_ZTV14OSMeshSDMemory = external dso_local unnamed_addr constant { [18 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN13SDMemoryStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(152)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI8SparseVNSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN14OSMeshSDMemoryD2Ev(ptr noundef nonnull align 8 dereferenceable(552) %0) unnamed_addr #3 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 128) ({ [18 x ptr] }, ptr @_ZTV14OSMeshSDMemory, i32 0, i32 0, i32 2), ptr %4, align 8, !tbaa !9
  %5 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 23
  %6 = load ptr, ptr %5, align 8, !tbaa !11
  %7 = icmp eq ptr %6, null
  br i1 %7, label %9, label %8

8:                                                ; preds = %1
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %6) #4
  call void @_ZdlPvm(ptr noundef %6, i64 noundef 120) #5
  br label %9

9:                                                ; preds = %8, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  store i32 0, ptr %3, align 4, !tbaa !40
  br label %10

10:                                               ; preds = %33, %9
  %11 = load i32, ptr %3, align 4, !tbaa !40
  %12 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 16
  %13 = load i32, ptr %12, align 8, !tbaa !41
  %14 = icmp ult i32 %11, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  br label %36

16:                                               ; preds = %10
  %17 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 24
  %18 = load i32, ptr %3, align 4, !tbaa !40
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %19) #4
  %21 = load ptr, ptr %20, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %24, label %23

23:                                               ; preds = %16
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %21) #4
  call void @_ZdlPvm(ptr noundef %21, i64 noundef 120) #5
  br label %24

24:                                               ; preds = %23, %16
  %25 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 25
  %26 = load i32, ptr %3, align 4, !tbaa !40
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %27) #4
  %29 = load ptr, ptr %28, align 8, !tbaa !5
  %30 = icmp eq ptr %29, null
  br i1 %30, label %32, label %31

31:                                               ; preds = %24
  call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %29) #4
  call void @_ZdlPvm(ptr noundef %29, i64 noundef 120) #5
  br label %32

32:                                               ; preds = %31, %24
  br label %33

33:                                               ; preds = %32
  %34 = load i32, ptr %3, align 4, !tbaa !40
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %3, align 4, !tbaa !40
  br label %10, !llvm.loop !42

36:                                               ; preds = %15
  %37 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 50
  call void @_ZN13SDMemoryStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(152) %37) #4
  %38 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 48
  call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %38) #4
  %39 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 25
  call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %39) #4
  %40 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 24
  call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %40) #4
  %41 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 13
  call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %41) #4
  %42 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 12
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %42) #4
  %43 = getelementptr inbounds %class.OSMeshSDMemory, ptr %4, i32 0, i32 11
  call void @_ZNSt6vectorI8SparseVNSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %43) #4
  call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %4) #4
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 224}
!12 = !{!"_ZTS14OSMeshSDMemory", !13, i64 0, !6, i64 48, !6, i64 56, !6, i64 64, !15, i64 72, !15, i64 76, !15, i64 80, !15, i64 84, !15, i64 88, !6, i64 96, !19, i64 104, !20, i64 112, !24, i64 136, !28, i64 160, !15, i64 184, !15, i64 188, !15, i64 192, !15, i64 196, !15, i64 200, !15, i64 204, !15, i64 208, !15, i64 212, !15, i64 216, !6, i64 224, !32, i64 232, !32, i64 256, !6, i64 280, !6, i64 288, !6, i64 296, !15, i64 304, !15, i64 308, !15, i64 312, !15, i64 316, !15, i64 320, !15, i64 324, !15, i64 328, !15, i64 332, !15, i64 336, !36, i64 340, !36, i64 341, !36, i64 342, !36, i64 343, !36, i64 344, !15, i64 348, !15, i64 352, !15, i64 356, !15, i64 360, !15, i64 364, !28, i64 368, !15, i64 392, !37, i64 400}
!13 = !{!"_ZTS16MemoryController", !14, i64 0}
!14 = !{!"_ZTS4Unit", !15, i64 8, !16, i64 16}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !17, i64 0, !18, i64 8, !7, i64 16}
!17 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!18 = !{!"long", !7, i64 0}
!19 = !{!"_ZTS21OSMeshControllerState", !7, i64 0}
!20 = !{!"_ZTSSt6vectorI8SparseVNSaIS0_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseI8SparseVNSaIS0_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!"_ZTSSt6vectorIjSaIjEE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!28 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!36 = !{!"bool", !7, i64 0}
!37 = !{!"_ZTS13SDMemoryStats", !38, i64 0, !15, i64 8, !15, i64 12, !15, i64 16, !15, i64 20, !15, i64 24, !15, i64 28, !15, i64 32, !15, i64 36, !15, i64 40, !15, i64 44, !39, i64 48, !24, i64 56, !24, i64 80, !24, i64 104, !24, i64 128}
!38 = !{!"_ZTS5Stats"}
!39 = !{!"_ZTS8Dataflow", !7, i64 0}
!40 = !{!15, !15, i64 0}
!41 = !{!12, !15, i64 192}
!42 = distinct !{!42, !43}
!43 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV14OSMeshSDMemory = external dso_local unnamed_addr constant { [18 x ptr] }, align 8

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN13SDMemoryStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(152)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI8SparseVNSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN14OSMeshSDMemoryD2Ev(ptr noundef nonnull align 8 dereferenceable(552) %0) unnamed_addr #2 align 2 {
  store ptr getelementptr inbounds inrange(-16, 128) (i8, ptr @_ZTV14OSMeshSDMemory, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 224
  %3 = load ptr, ptr %2, align 8, !tbaa !8
  %4 = icmp eq ptr %3, null
  br i1 %4, label %6, label %5

5:                                                ; preds = %1
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %3) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %3, i64 noundef 120) #4
  br label %6

6:                                                ; preds = %5, %1
  %7 = getelementptr inbounds i8, ptr %0, i64 192
  %8 = load i32, ptr %7, align 8, !tbaa !39
  %.not = icmp eq i32 %8, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 232
  %10 = getelementptr inbounds i8, ptr %0, i64 256
  br label %18

._crit_edge:                                      ; preds = %28, %6
  %11 = getelementptr inbounds i8, ptr %0, i64 400
  tail call void @_ZN13SDMemoryStatsD2Ev(ptr noundef nonnull align 8 dereferenceable(152) %11) #3
  %12 = getelementptr inbounds i8, ptr %0, i64 368
  tail call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  %13 = getelementptr inbounds i8, ptr %0, i64 256
  tail call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  %14 = getelementptr inbounds i8, ptr %0, i64 232
  tail call void @_ZNSt6vectorIP4FifoSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  %15 = getelementptr inbounds i8, ptr %0, i64 160
  tail call void @_ZNSt6vectorIP10ConnectionSaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  %16 = getelementptr inbounds i8, ptr %0, i64 136
  tail call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %16) #3
  %17 = getelementptr inbounds i8, ptr %0, i64 112
  tail call void @_ZNSt6vectorI8SparseVNSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  tail call void @_ZN4UnitD2Ev(ptr noundef nonnull align 8 dereferenceable(48) %0) #3
  ret void

18:                                               ; preds = %.lr.ph, %28
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %28 ]
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %indvars.iv) #3
  %20 = load ptr, ptr %19, align 8, !tbaa !40
  %21 = icmp eq ptr %20, null
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %20) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %20, i64 noundef 120) #4
  br label %23

23:                                               ; preds = %22, %18
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %indvars.iv) #3
  %25 = load ptr, ptr %24, align 8, !tbaa !40
  %26 = icmp eq ptr %25, null
  br i1 %26, label %28, label %27

27:                                               ; preds = %23
  tail call void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120) %25) #3
  tail call void @_ZdlPvm(ptr noundef nonnull %25, i64 noundef 120) #4
  br label %28

28:                                               ; preds = %23, %27
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %29 = load i32, ptr %7, align 8, !tbaa !39
  %30 = zext i32 %29 to i64
  %31 = icmp ult i64 %indvars.iv.next, %30
  br i1 %31, label %18, label %._crit_edge, !llvm.loop !41
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4FifoD2Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP4FifoSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !16, i64 224}
!9 = !{!"_ZTS14OSMeshSDMemory", !10, i64 0, !16, i64 48, !16, i64 56, !16, i64 64, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !16, i64 96, !18, i64 104, !19, i64 112, !23, i64 136, !27, i64 160, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200, !12, i64 204, !12, i64 208, !12, i64 212, !12, i64 216, !16, i64 224, !31, i64 232, !31, i64 256, !16, i64 280, !16, i64 288, !16, i64 296, !12, i64 304, !12, i64 308, !12, i64 312, !12, i64 316, !12, i64 320, !12, i64 324, !12, i64 328, !12, i64 332, !12, i64 336, !35, i64 340, !35, i64 341, !35, i64 342, !35, i64 343, !35, i64 344, !12, i64 348, !12, i64 352, !12, i64 356, !12, i64 360, !12, i64 364, !27, i64 368, !12, i64 392, !36, i64 400}
!10 = !{!"_ZTS16MemoryController", !11, i64 0}
!11 = !{!"_ZTS4Unit", !12, i64 8, !14, i64 16}
!12 = !{!"int", !13, i64 0}
!13 = !{!"omnipotent char", !7, i64 0}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !15, i64 0, !17, i64 8, !13, i64 16}
!15 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !16, i64 0}
!16 = !{!"any pointer", !13, i64 0}
!17 = !{!"long", !13, i64 0}
!18 = !{!"_ZTS21OSMeshControllerState", !13, i64 0}
!19 = !{!"_ZTSSt6vectorI8SparseVNSaIS0_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseI8SparseVNSaIS0_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseI8SparseVNSaIS0_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!23 = !{!"_ZTSSt6vectorIjSaIjEE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!27 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!31 = !{!"_ZTSSt6vectorIP4FifoSaIS1_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIP4FifoSaIS1_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIP4FifoSaIS1_EE17_Vector_impl_dataE", !16, i64 0, !16, i64 8, !16, i64 16}
!35 = !{!"bool", !13, i64 0}
!36 = !{!"_ZTS13SDMemoryStats", !37, i64 0, !12, i64 8, !12, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !38, i64 48, !23, i64 56, !23, i64 80, !23, i64 104, !23, i64 128}
!37 = !{!"_ZTS5Stats"}
!38 = !{!"_ZTS8Dataflow", !13, i64 0}
!39 = !{!9, !12, i64 192}
!40 = !{!16, !16, i64 0}
!41 = distinct !{!41, !42}
!42 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass