; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetMergedConvolution16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base17ConvertFp32ToBf16EPKhRKNS_9ConvParamERKNS0_25SynetMergedConvolution16b8AlgParamEmmPt(ptr noundef %0, ptr noundef nonnull align 8 dereferenceable(180) %1, ptr noundef nonnull align 8 dereferenceable(152) %2, i64 noundef %3, i64 noundef %4, ptr noundef %5) #0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i32, align 4
  %17 = alloca i64, align 8
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !5
  store i64 %3, ptr %10, align 8, !tbaa !9
  store i64 %4, ptr %11, align 8, !tbaa !9
  store ptr %5, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  store ptr %18, ptr %13, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %19, i32 0, i32 2
  %21 = load i64, ptr %20, align 8, !tbaa !11
  %22 = load ptr, ptr %8, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %22, i32 0, i32 0
  %24 = load i64, ptr %23, align 8, !tbaa !16
  %25 = mul i64 %21, %24
  store i64 %25, ptr %14, align 8, !tbaa !9
  %26 = load i64, ptr %10, align 8, !tbaa !9
  %27 = load i64, ptr %14, align 8, !tbaa !9
  %28 = mul i64 %26, %27
  %29 = load ptr, ptr %13, align 8, !tbaa !5
  %30 = getelementptr inbounds float, ptr %29, i64 %28
  store ptr %30, ptr %13, align 8, !tbaa !5
  %31 = load i64, ptr %10, align 8, !tbaa !9
  %32 = load i64, ptr %14, align 8, !tbaa !9
  %33 = mul i64 %31, %32
  %34 = load ptr, ptr %12, align 8, !tbaa !5
  %35 = getelementptr inbounds i16, ptr %34, i64 %33
  store ptr %35, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  %36 = load i64, ptr %10, align 8, !tbaa !9
  store i64 %36, ptr %15, align 8, !tbaa !9
  br label %37

37:                                               ; preds = %67, %6
  %38 = load i64, ptr %15, align 8, !tbaa !9
  %39 = load i64, ptr %11, align 8, !tbaa !9
  %40 = icmp ult i64 %38, %39
  br i1 %40, label %42, label %41

41:                                               ; preds = %37
  store i32 2, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  br label %70

42:                                               ; preds = %37
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #3
  store i64 0, ptr %17, align 8, !tbaa !9
  br label %43

43:                                               ; preds = %57, %42
  %44 = load i64, ptr %17, align 8, !tbaa !9
  %45 = load i64, ptr %14, align 8, !tbaa !9
  %46 = icmp ult i64 %44, %45
  br i1 %46, label %48, label %47

47:                                               ; preds = %43
  store i32 5, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #3
  br label %60

48:                                               ; preds = %43
  %49 = load ptr, ptr %13, align 8, !tbaa !5
  %50 = load i64, ptr %17, align 8, !tbaa !9
  %51 = getelementptr inbounds float, ptr %49, i64 %50
  %52 = load float, ptr %51, align 4, !tbaa !17
  %53 = call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %52)
  %54 = load ptr, ptr %12, align 8, !tbaa !5
  %55 = load i64, ptr %17, align 8, !tbaa !9
  %56 = getelementptr inbounds i16, ptr %54, i64 %55
  store i16 %53, ptr %56, align 2, !tbaa !19
  br label %57

57:                                               ; preds = %48
  %58 = load i64, ptr %17, align 8, !tbaa !9
  %59 = add i64 %58, 1
  store i64 %59, ptr %17, align 8, !tbaa !9
  br label %43, !llvm.loop !21

60:                                               ; preds = %47
  %61 = load i64, ptr %14, align 8, !tbaa !9
  %62 = load ptr, ptr %13, align 8, !tbaa !5
  %63 = getelementptr inbounds float, ptr %62, i64 %61
  store ptr %63, ptr %13, align 8, !tbaa !5
  %64 = load i64, ptr %14, align 8, !tbaa !9
  %65 = load ptr, ptr %12, align 8, !tbaa !5
  %66 = getelementptr inbounds i16, ptr %65, i64 %64
  store ptr %66, ptr %12, align 8, !tbaa !5
  br label %67

67:                                               ; preds = %60
  %68 = load i64, ptr %15, align 8, !tbaa !9
  %69 = add i64 %68, 1
  store i64 %69, ptr %15, align 8, !tbaa !9
  br label %37, !llvm.loop !23

70:                                               ; preds = %41
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !13, i64 24, !14, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !13, i64 56, !14, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !15, i64 152}
!13 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!14 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!15 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!16 = !{!12, !10, i64 0}
!17 = !{!18, !18, i64 0}
!18 = !{!"float", !7, i64 0}
!19 = !{!20, !20, i64 0}
!20 = !{!"short", !7, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = distinct !{!23, !22}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base17ConvertFp32ToBf16EPKhRKNS_9ConvParamERKNS0_25SynetMergedConvolution16b8AlgParamEmmPt(ptr nocapture noundef readonly %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(180) %1, ptr nocapture noundef nonnull readnone align 8 dereferenceable(152) %2, i64 noundef %3, i64 noundef %4, ptr nocapture noundef writeonly %5) local_unnamed_addr #0 {
  %7 = getelementptr inbounds i8, ptr %1, i64 16
  %8 = load i64, ptr %7, align 8, !tbaa !5
  %9 = load i64, ptr %1, align 8, !tbaa !13
  %10 = mul i64 %9, %8
  %11 = icmp uge i64 %3, %4
  %.not = icmp eq i64 %10, 0
  %or.cond = select i1 %11, i1 true, i1 %.not
  br i1 %or.cond, label %._crit_edge31, label %.preheader.us.preheader

.preheader.us.preheader:                          ; preds = %6
  %12 = mul i64 %10, %3
  %13 = getelementptr inbounds float, ptr %0, i64 %12
  %14 = getelementptr inbounds i16, ptr %5, i64 %12
  br label %.preheader.us

.preheader.us:                                    ; preds = %.preheader.us.preheader, %._crit_edge.us
  %.02330.us = phi i64 [ %23, %._crit_edge.us ], [ %3, %.preheader.us.preheader ]
  %.02429.us = phi ptr [ %22, %._crit_edge.us ], [ %14, %.preheader.us.preheader ]
  %.02528.us = phi ptr [ %21, %._crit_edge.us ], [ %13, %.preheader.us.preheader ]
  br label %15

15:                                               ; preds = %.preheader.us, %15
  %.027.us = phi i64 [ 0, %.preheader.us ], [ %20, %15 ]
  %16 = getelementptr inbounds float, ptr %.02528.us, i64 %.027.us
  %17 = load float, ptr %16, align 4, !tbaa !14
  %18 = tail call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %17)
  %19 = getelementptr inbounds i16, ptr %.02429.us, i64 %.027.us
  store i16 %18, ptr %19, align 2, !tbaa !16
  %20 = add nuw i64 %.027.us, 1
  %exitcond.not = icmp eq i64 %20, %10
  br i1 %exitcond.not, label %._crit_edge.us, label %15, !llvm.loop !18

._crit_edge.us:                                   ; preds = %15
  %21 = getelementptr inbounds float, ptr %.02528.us, i64 %10
  %22 = getelementptr inbounds i16, ptr %.02429.us, i64 %10
  %23 = add nuw i64 %.02330.us, 1
  %exitcond33.not = icmp eq i64 %23, %4
  br i1 %exitcond33.not, label %._crit_edge31, label %.preheader.us, !llvm.loop !20

._crit_edge31:                                    ; preds = %._crit_edge.us, %6
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 16}
!6 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !10, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !12, i64 152}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!11 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!12 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!13 = !{!6, !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"float", !8, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"short", !8, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = distinct !{!20, !19}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass