; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseNeural)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [82 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [76 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi = external hidden unnamed_addr constant [216 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [84 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd4Base32NeuralConvolutionForwardConvertNEPKflllllllllllPf(ptr noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, ptr noundef) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd4Base32NeuralConvolutionForwardConvertTEPKflllllllllllPf(ptr noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, ptr noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNNEmmmPKfS2_Pf(i64 noundef, i64 noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNTEmmmPKfS2_Pf(i64 noundef, i64 noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %7, i64 noundef %8, i64 noundef %9, i64 noundef %10, i64 noundef %11, i64 noundef %12, ptr noundef %13, ptr noundef %14, ptr noundef %15, i64 noundef %16, i64 noundef %17, i64 noundef %18, i32 noundef %19) #1 {
  %21 = alloca ptr, align 8
  %22 = alloca i64, align 8
  %23 = alloca i64, align 8
  %24 = alloca i64, align 8
  %25 = alloca ptr, align 8
  %26 = alloca i64, align 8
  %27 = alloca i64, align 8
  %28 = alloca i64, align 8
  %29 = alloca i64, align 8
  %30 = alloca i64, align 8
  %31 = alloca i64, align 8
  %32 = alloca i64, align 8
  %33 = alloca i64, align 8
  %34 = alloca ptr, align 8
  %35 = alloca ptr, align 8
  %36 = alloca ptr, align 8
  %37 = alloca i64, align 8
  %38 = alloca i64, align 8
  %39 = alloca i64, align 8
  %40 = alloca i32, align 4
  %41 = alloca ptr, align 8
  %42 = alloca ptr, align 8
  %43 = alloca i8, align 1
  %44 = alloca i64, align 8
  %45 = alloca i64, align 8
  %46 = alloca i64, align 8
  %47 = alloca i64, align 8
  store ptr %0, ptr %21, align 8, !tbaa !5
  store i64 %1, ptr %22, align 8, !tbaa !9
  store i64 %2, ptr %23, align 8, !tbaa !9
  store i64 %3, ptr %24, align 8, !tbaa !9
  store ptr %4, ptr %25, align 8, !tbaa !5
  store i64 %5, ptr %26, align 8, !tbaa !9
  store i64 %6, ptr %27, align 8, !tbaa !9
  store i64 %7, ptr %28, align 8, !tbaa !9
  store i64 %8, ptr %29, align 8, !tbaa !9
  store i64 %9, ptr %30, align 8, !tbaa !9
  store i64 %10, ptr %31, align 8, !tbaa !9
  store i64 %11, ptr %32, align 8, !tbaa !9
  store i64 %12, ptr %33, align 8, !tbaa !9
  store ptr %13, ptr %34, align 8, !tbaa !5
  store ptr %14, ptr %35, align 8, !tbaa !5
  store ptr %15, ptr %36, align 8, !tbaa !5
  store i64 %16, ptr %37, align 8, !tbaa !9
  store i64 %17, ptr %38, align 8, !tbaa !9
  store i64 %18, ptr %39, align 8, !tbaa !9
  store i32 %19, ptr %40, align 4, !tbaa !11
  %48 = load i64, ptr %37, align 8, !tbaa !9
  %49 = load i64, ptr %22, align 8, !tbaa !9
  %50 = load i64, ptr %28, align 8, !tbaa !9
  %51 = mul i64 2, %50
  %52 = add i64 %49, %51
  %53 = load i64, ptr %32, align 8, !tbaa !9
  %54 = load i64, ptr %26, align 8, !tbaa !9
  %55 = sub i64 %54, 1
  %56 = mul i64 %53, %55
  %57 = add i64 %56, 1
  %58 = sub i64 %52, %57
  %59 = load i64, ptr %30, align 8, !tbaa !9
  %60 = udiv i64 %58, %59
  %61 = add i64 %60, 1
  %62 = icmp eq i64 %48, %61
  br i1 %62, label %63, label %64

63:                                               ; preds = %20
  br label %66

64:                                               ; preds = %20
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 569, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi) #7
  unreachable

65:                                               ; No predecessors!
  br label %66

66:                                               ; preds = %65, %63
  %67 = load i64, ptr %38, align 8, !tbaa !9
  %68 = load i64, ptr %23, align 8, !tbaa !9
  %69 = load i64, ptr %29, align 8, !tbaa !9
  %70 = mul i64 2, %69
  %71 = add i64 %68, %70
  %72 = load i64, ptr %33, align 8, !tbaa !9
  %73 = load i64, ptr %27, align 8, !tbaa !9
  %74 = sub i64 %73, 1
  %75 = mul i64 %72, %74
  %76 = add i64 %75, 1
  %77 = sub i64 %71, %76
  %78 = load i64, ptr %31, align 8, !tbaa !9
  %79 = udiv i64 %77, %78
  %80 = add i64 %79, 1
  %81 = icmp eq i64 %67, %80
  br i1 %81, label %82, label %83

82:                                               ; preds = %66
  br label %85

83:                                               ; preds = %66
  call void @__assert_fail(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 570, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi) #7
  unreachable

84:                                               ; No predecessors!
  br label %85

85:                                               ; preds = %84, %82
  %86 = load i32, ptr %40, align 4, !tbaa !11
  %87 = icmp ne i32 %86, 0
  br i1 %87, label %96, label %88

88:                                               ; preds = %85
  %89 = load ptr, ptr %36, align 8, !tbaa !5
  %90 = load i64, ptr %37, align 8, !tbaa !9
  %91 = load i64, ptr %38, align 8, !tbaa !9
  %92 = mul i64 %90, %91
  %93 = load i64, ptr %39, align 8, !tbaa !9
  %94 = mul i64 %92, %93
  %95 = mul i64 %94, 4
  call void @llvm.memset.p0.i64(ptr align 4 %89, i8 0, i64 %95, i1 false)
  br label %96

96:                                               ; preds = %88, %85
  call void @llvm.lifetime.start.p0(i64 8, ptr %41) #8
  store ptr null, ptr %41, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %42) #8
  store ptr null, ptr %42, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %43) #8
  %97 = load i64, ptr %37, align 8, !tbaa !9
  %98 = load i64, ptr %38, align 8, !tbaa !9
  %99 = mul i64 %97, %98
  %100 = icmp ule i64 %99, 1024
  %101 = zext i1 %100 to i8
  store i8 %101, ptr %43, align 1, !tbaa !13
  %102 = load i64, ptr %26, align 8, !tbaa !9
  %103 = icmp eq i64 %102, 1
  br i1 %103, label %104, label %112

104:                                              ; preds = %96
  %105 = load i64, ptr %27, align 8, !tbaa !9
  %106 = icmp eq i64 %105, 1
  br i1 %106, label %107, label %112

107:                                              ; preds = %104
  %108 = load i8, ptr %43, align 1, !tbaa !13, !range !15, !noundef !16
  %109 = trunc i8 %108 to i1
  br i1 %109, label %112, label %110

110:                                              ; preds = %107
  %111 = load ptr, ptr %21, align 8, !tbaa !5
  store ptr %111, ptr %41, align 8, !tbaa !5
  br label %186

112:                                              ; preds = %107, %104, %96
  call void @llvm.lifetime.start.p0(i64 8, ptr %44) #8
  %113 = load i64, ptr %37, align 8, !tbaa !9
  %114 = load i64, ptr %38, align 8, !tbaa !9
  %115 = mul i64 %113, %114
  %116 = load i64, ptr %24, align 8, !tbaa !9
  %117 = mul i64 %115, %116
  %118 = load i64, ptr %26, align 8, !tbaa !9
  %119 = mul i64 %117, %118
  %120 = load i64, ptr %27, align 8, !tbaa !9
  %121 = mul i64 %119, %120
  %122 = mul i64 %121, 4
  store i64 %122, ptr %44, align 8, !tbaa !9
  %123 = load ptr, ptr %34, align 8, !tbaa !5
  %124 = load ptr, ptr %34, align 8, !tbaa !5
  %125 = call noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef %124, i64 noundef 8)
  %126 = icmp ne ptr %123, %125
  br i1 %126, label %127, label %130

127:                                              ; preds = %112
  %128 = load i64, ptr %44, align 8, !tbaa !9
  %129 = add i64 %128, 8
  store i64 %129, ptr %44, align 8, !tbaa !9
  br label %130

130:                                              ; preds = %127, %112
  %131 = load ptr, ptr %34, align 8, !tbaa !5
  %132 = icmp eq ptr %131, null
  br i1 %132, label %141, label %133

133:                                              ; preds = %130
  %134 = load ptr, ptr %35, align 8, !tbaa !5
  %135 = icmp eq ptr %134, null
  br i1 %135, label %141, label %136

136:                                              ; preds = %133
  %137 = load ptr, ptr %35, align 8, !tbaa !5
  %138 = load i64, ptr %137, align 8, !tbaa !9
  %139 = load i64, ptr %44, align 8, !tbaa !9
  %140 = icmp ult i64 %138, %139
  br i1 %140, label %141, label %151

141:                                              ; preds = %136, %133, %130
  %142 = load i64, ptr %44, align 8, !tbaa !9
  %143 = call noundef ptr @_ZN4Simd8AllocateEmm(i64 noundef %142, i64 noundef 8)
  store ptr %143, ptr %42, align 8, !tbaa !5
  %144 = load ptr, ptr %35, align 8, !tbaa !5
  %145 = icmp ne ptr %144, null
  br i1 %145, label %146, label %149

146:                                              ; preds = %141
  %147 = load i64, ptr %44, align 8, !tbaa !9
  %148 = load ptr, ptr %35, align 8, !tbaa !5
  store i64 %147, ptr %148, align 8, !tbaa !9
  br label %149

149:                                              ; preds = %146, %141
  %150 = load ptr, ptr %42, align 8, !tbaa !5
  store ptr %150, ptr %41, align 8, !tbaa !5
  br label %154

151:                                              ; preds = %136
  %152 = load ptr, ptr %34, align 8, !tbaa !5
  %153 = call noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef %152, i64 noundef 8)
  store ptr %153, ptr %41, align 8, !tbaa !5
  br label %154

154:                                              ; preds = %151, %149
  %155 = load i8, ptr %43, align 1, !tbaa !13, !range !15, !noundef !16
  %156 = trunc i8 %155 to i1
  br i1 %156, label %157, label %171

157:                                              ; preds = %154
  %158 = load ptr, ptr %21, align 8, !tbaa !5
  %159 = load i64, ptr %22, align 8, !tbaa !9
  %160 = load i64, ptr %23, align 8, !tbaa !9
  %161 = load i64, ptr %24, align 8, !tbaa !9
  %162 = load i64, ptr %26, align 8, !tbaa !9
  %163 = load i64, ptr %27, align 8, !tbaa !9
  %164 = load i64, ptr %28, align 8, !tbaa !9
  %165 = load i64, ptr %29, align 8, !tbaa !9
  %166 = load i64, ptr %30, align 8, !tbaa !9
  %167 = load i64, ptr %31, align 8, !tbaa !9
  %168 = load i64, ptr %32, align 8, !tbaa !9
  %169 = load i64, ptr %33, align 8, !tbaa !9
  %170 = load ptr, ptr %41, align 8, !tbaa !5
  call void @_ZN4Simd4Base32NeuralConvolutionForwardConvertTEPKflllllllllllPf(ptr noundef %158, i64 noundef %159, i64 noundef %160, i64 noundef %161, i64 noundef %162, i64 noundef %163, i64 noundef %164, i64 noundef %165, i64 noundef %166, i64 noundef %167, i64 noundef %168, i64 noundef %169, ptr noundef %170)
  br label %185

171:                                              ; preds = %154
  %172 = load ptr, ptr %21, align 8, !tbaa !5
  %173 = load i64, ptr %22, align 8, !tbaa !9
  %174 = load i64, ptr %23, align 8, !tbaa !9
  %175 = load i64, ptr %24, align 8, !tbaa !9
  %176 = load i64, ptr %26, align 8, !tbaa !9
  %177 = load i64, ptr %27, align 8, !tbaa !9
  %178 = load i64, ptr %28, align 8, !tbaa !9
  %179 = load i64, ptr %29, align 8, !tbaa !9
  %180 = load i64, ptr %30, align 8, !tbaa !9
  %181 = load i64, ptr %31, align 8, !tbaa !9
  %182 = load i64, ptr %32, align 8, !tbaa !9
  %183 = load i64, ptr %33, align 8, !tbaa !9
  %184 = load ptr, ptr %41, align 8, !tbaa !5
  call void @_ZN4Simd4Base32NeuralConvolutionForwardConvertNEPKflllllllllllPf(ptr noundef %172, i64 noundef %173, i64 noundef %174, i64 noundef %175, i64 noundef %176, i64 noundef %177, i64 noundef %178, i64 noundef %179, i64 noundef %180, i64 noundef %181, i64 noundef %182, i64 noundef %183, ptr noundef %184)
  br label %185

185:                                              ; preds = %171, %157
  call void @llvm.lifetime.end.p0(i64 8, ptr %44) #8
  br label %186

186:                                              ; preds = %185, %110
  call void @llvm.lifetime.start.p0(i64 8, ptr %45) #8
  %187 = load i64, ptr %39, align 8, !tbaa !9
  store i64 %187, ptr %45, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %46) #8
  %188 = load i64, ptr %38, align 8, !tbaa !9
  %189 = load i64, ptr %37, align 8, !tbaa !9
  %190 = mul i64 %188, %189
  store i64 %190, ptr %46, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %47) #8
  %191 = load i64, ptr %26, align 8, !tbaa !9
  %192 = load i64, ptr %27, align 8, !tbaa !9
  %193 = mul i64 %191, %192
  %194 = load i64, ptr %24, align 8, !tbaa !9
  %195 = mul i64 %193, %194
  store i64 %195, ptr %47, align 8, !tbaa !9
  %196 = load i8, ptr %43, align 1, !tbaa !13, !range !15, !noundef !16
  %197 = trunc i8 %196 to i1
  br i1 %197, label %198, label %205

198:                                              ; preds = %186
  %199 = load i64, ptr %45, align 8, !tbaa !9
  %200 = load i64, ptr %46, align 8, !tbaa !9
  %201 = load i64, ptr %47, align 8, !tbaa !9
  %202 = load ptr, ptr %25, align 8, !tbaa !5
  %203 = load ptr, ptr %41, align 8, !tbaa !5
  %204 = load ptr, ptr %36, align 8, !tbaa !5
  call void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNTEmmmPKfS2_Pf(i64 noundef %199, i64 noundef %200, i64 noundef %201, ptr noundef %202, ptr noundef %203, ptr noundef %204)
  br label %212

205:                                              ; preds = %186
  %206 = load i64, ptr %45, align 8, !tbaa !9
  %207 = load i64, ptr %46, align 8, !tbaa !9
  %208 = load i64, ptr %47, align 8, !tbaa !9
  %209 = load ptr, ptr %25, align 8, !tbaa !5
  %210 = load ptr, ptr %41, align 8, !tbaa !5
  %211 = load ptr, ptr %36, align 8, !tbaa !5
  call void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNNEmmmPKfS2_Pf(i64 noundef %206, i64 noundef %207, i64 noundef %208, ptr noundef %209, ptr noundef %210, ptr noundef %211)
  br label %212

212:                                              ; preds = %205, %198
  %213 = load ptr, ptr %42, align 8, !tbaa !5
  %214 = icmp ne ptr %213, null
  br i1 %214, label %215, label %217

215:                                              ; preds = %212
  %216 = load ptr, ptr %42, align 8, !tbaa !5
  call void @_ZN4Simd4FreeEPv(ptr noundef %216)
  br label %217

217:                                              ; preds = %215, %212
  call void @llvm.lifetime.end.p0(i64 8, ptr %47) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %46) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %45) #8
  call void @llvm.lifetime.end.p0(i64 1, ptr %43) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %42) #8
  call void @llvm.lifetime.end.p0(i64 8, ptr %41) #8
  ret void
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #4

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef, i64 noundef) #5

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef ptr @_ZN4Simd8AllocateEmm(i64 noundef, i64 noundef) #6

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4FreeEPv(ptr noundef) #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #5 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { noreturn nounwind }
attributes #8 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = !{i8 0, i8 2}
!16 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [82 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [76 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi = external hidden unnamed_addr constant [216 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [84 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd4Base32NeuralConvolutionForwardConvertNEPKflllllllllllPf(ptr noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd4Base32NeuralConvolutionForwardConvertTEPKflllllllllllPf(ptr noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNNEmmmPKfS2_Pf(i64 noundef, i64 noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNTEmmmPKfS2_Pf(i64 noundef, i64 noundef, i64 noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef %4, i64 noundef %5, i64 noundef %6, i64 noundef %7, i64 noundef %8, i64 noundef %9, i64 noundef %10, i64 noundef %11, i64 noundef %12, ptr noundef %13, ptr noundef %14, ptr noundef %15, i64 noundef %16, i64 noundef %17, i64 noundef %18, i32 noundef %19) local_unnamed_addr #0 {
  %21 = shl i64 %7, 1
  %22 = add i64 %21, %1
  %23 = add i64 %5, -1
  %24 = mul i64 %23, %11
  %.neg = xor i64 %24, -1
  %25 = add i64 %22, %.neg
  %26 = udiv i64 %25, %9
  %27 = add i64 %26, 1
  %28 = icmp eq i64 %27, %16
  br i1 %28, label %30, label %29

29:                                               ; preds = %20
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 569, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi) #6
  unreachable

30:                                               ; preds = %20
  %31 = shl i64 %8, 1
  %32 = add i64 %31, %2
  %33 = add i64 %6, -1
  %34 = mul i64 %33, %12
  %.neg101 = xor i64 %34, -1
  %35 = add i64 %32, %.neg101
  %36 = udiv i64 %35, %10
  %37 = add i64 %36, 1
  %38 = icmp eq i64 %37, %17
  br i1 %38, label %40, label %39

39:                                               ; preds = %30
  tail call void @__assert_fail(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 570, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base24NeuralConvolutionForwardEPKfmmmS2_mmmmmmmmPvPmPfmmmi) #6
  unreachable

40:                                               ; preds = %30
  %.not = icmp eq i32 %19, 0
  %41 = mul i64 %17, %16
  br i1 %.not, label %42, label %._crit_edge114

42:                                               ; preds = %40
  %43 = shl i64 %41, 2
  %44 = mul i64 %43, %18
  tail call void @llvm.memset.p0.i64(ptr align 4 %15, i8 0, i64 %44, i1 false)
  br label %._crit_edge114

._crit_edge114:                                   ; preds = %40, %42
  %45 = icmp ult i64 %41, 1025
  %46 = icmp ne i64 %5, 1
  %47 = icmp ne i64 %6, 1
  %or.cond.not113 = or i1 %46, %47
  %brmerge = or i1 %or.cond.not113, %45
  %48 = mul i64 %5, %3
  br i1 %brmerge, label %49, label %._crit_edge

49:                                               ; preds = %._crit_edge114
  %50 = shl i64 %48, 2
  %51 = mul i64 %50, %6
  %52 = mul i64 %51, %41
  %53 = tail call noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef %13, i64 noundef 8)
  %.not102 = icmp eq ptr %53, %13
  %54 = add i64 %52, 8
  %spec.select = select i1 %.not102, i64 %52, i64 %54
  %55 = icmp eq ptr %13, null
  %56 = icmp eq ptr %14, null
  %or.cond3 = or i1 %55, %56
  br i1 %or.cond3, label %61, label %57

57:                                               ; preds = %49
  %58 = load i64, ptr %14, align 8, !tbaa !5
  %59 = icmp ult i64 %58, %spec.select
  br i1 %59, label %.thread, label %65

.thread:                                          ; preds = %57
  %60 = tail call noundef ptr @_ZN4Simd8AllocateEmm(i64 noundef %spec.select, i64 noundef 8)
  br label %63

61:                                               ; preds = %49
  %62 = tail call noundef ptr @_ZN4Simd8AllocateEmm(i64 noundef %spec.select, i64 noundef 8)
  br i1 %56, label %67, label %63

63:                                               ; preds = %.thread, %61
  %64 = phi ptr [ %60, %.thread ], [ %62, %61 ]
  store i64 %spec.select, ptr %14, align 8, !tbaa !5
  br label %67

65:                                               ; preds = %57
  %66 = tail call noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef nonnull %13, i64 noundef 8)
  br label %67

67:                                               ; preds = %61, %63, %65
  %.091 = phi ptr [ null, %65 ], [ %64, %63 ], [ %62, %61 ]
  %.0 = phi ptr [ %66, %65 ], [ %64, %63 ], [ %62, %61 ]
  br i1 %45, label %69, label %68

68:                                               ; preds = %67
  tail call void @_ZN4Simd4Base32NeuralConvolutionForwardConvertNEPKflllllllllllPf(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %5, i64 noundef %6, i64 noundef %7, i64 noundef %8, i64 noundef %9, i64 noundef %10, i64 noundef %11, i64 noundef %12, ptr noundef %.0)
  br label %._crit_edge

69:                                               ; preds = %67
  tail call void @_ZN4Simd4Base32NeuralConvolutionForwardConvertTEPKflllllllllllPf(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %5, i64 noundef %6, i64 noundef %7, i64 noundef %8, i64 noundef %9, i64 noundef %10, i64 noundef %11, i64 noundef %12, ptr noundef %.0)
  %70 = mul i64 %48, %6
  tail call void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNTEmmmPKfS2_Pf(i64 noundef %18, i64 noundef %41, i64 noundef %70, ptr noundef %4, ptr noundef %.0, ptr noundef %15)
  br label %72

._crit_edge:                                      ; preds = %._crit_edge114, %68
  %.192.ph = phi ptr [ %.091, %68 ], [ null, %._crit_edge114 ]
  %.1.ph = phi ptr [ %.0, %68 ], [ %0, %._crit_edge114 ]
  %71 = mul i64 %48, %6
  tail call void @_ZN4Simd4Base30NeuralConvolutionForwardGemmNNEmmmPKfS2_Pf(i64 noundef %18, i64 noundef %41, i64 noundef %71, ptr noundef %4, ptr noundef %.1.ph, ptr noundef %15)
  br label %72

72:                                               ; preds = %._crit_edge, %69
  %.192108 = phi ptr [ %.192.ph, %._crit_edge ], [ %.091, %69 ]
  %.not104 = icmp eq ptr %.192108, null
  br i1 %.not104, label %74, label %73

73:                                               ; preds = %72
  tail call void @_ZN4Simd4FreeEPv(ptr noundef nonnull %.192108)
  br label %74

74:                                               ; preds = %73, %72
  ret void
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZN4Simd7AlignHiEPKvm(ptr noundef, i64 noundef) local_unnamed_addr #4

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef ptr @_ZN4Simd8AllocateEmm(i64 noundef, i64 noundef) local_unnamed_addr #5

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4FreeEPv(ptr noundef) local_unnamed_addr #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass