; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseResizerBicubic)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18ResizerByteBicubic18EstimateIndexAlphaEmmmRNS_5ArrayIiEES4_(ptr noundef nonnull align 8 dereferenceable(216) %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef nonnull align 8 dereferenceable(16) %4, ptr noundef nonnull align 8 dereferenceable(16) %5) #0 align 2 {
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca float, align 4
  %14 = alloca i64, align 8
  %15 = alloca float, align 4
  %16 = alloca i32, align 4
  %17 = alloca float, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !9
  store i64 %2, ptr %9, align 8, !tbaa !9
  store i64 %3, ptr %10, align 8, !tbaa !9
  store ptr %4, ptr %11, align 8, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !5
  %18 = load ptr, ptr %7, align 8
  %19 = load ptr, ptr %11, align 8, !tbaa !5
  %20 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %19, i64 noundef %20, i1 noundef zeroext false, i64 noundef 8)
  %21 = load ptr, ptr %12, align 8, !tbaa !5
  %22 = load i64, ptr %9, align 8, !tbaa !9
  %23 = mul i64 %22, 4
  call void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %21, i64 noundef %23, i1 noundef zeroext false, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #7
  %24 = load i64, ptr %8, align 8, !tbaa !9
  %25 = uitofp i64 %24 to float
  %26 = load i64, ptr %9, align 8, !tbaa !9
  %27 = uitofp i64 %26 to float
  %28 = fdiv float %25, %27
  store float %28, ptr %13, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #7
  store i64 0, ptr %14, align 8, !tbaa !9
  br label %29

29:                                               ; preds = %129, %6
  %30 = load i64, ptr %14, align 8, !tbaa !9
  %31 = load i64, ptr %9, align 8, !tbaa !9
  %32 = icmp ult i64 %30, %31
  br i1 %32, label %34, label %33

33:                                               ; preds = %29
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #7
  br label %132

34:                                               ; preds = %29
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #7
  %35 = load i64, ptr %14, align 8, !tbaa !9
  %36 = uitofp i64 %35 to float
  %37 = fadd float %36, 5.000000e-01
  %38 = load float, ptr %13, align 4, !tbaa !11
  %39 = call float @llvm.fmuladd.f32(float %37, float %38, float -5.000000e-01)
  store float %39, ptr %15, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #7
  %40 = load float, ptr %15, align 4, !tbaa !11
  %41 = call noundef float @_ZSt5floorf(float noundef %40)
  %42 = fptosi float %41 to i32
  store i32 %42, ptr %16, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #7
  %43 = load float, ptr %15, align 4, !tbaa !11
  %44 = load i32, ptr %16, align 4, !tbaa !13
  %45 = sitofp i32 %44 to float
  %46 = fsub float %43, %45
  store float %46, ptr %17, align 4, !tbaa !11
  %47 = load i32, ptr %16, align 4, !tbaa !13
  %48 = icmp slt i32 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %34
  store i32 0, ptr %16, align 4, !tbaa !13
  store float 0.000000e+00, ptr %17, align 4, !tbaa !11
  br label %50

50:                                               ; preds = %49, %34
  %51 = load i32, ptr %16, align 4, !tbaa !13
  %52 = load i64, ptr %8, align 8, !tbaa !9
  %53 = trunc i64 %52 to i32
  %54 = sub nsw i32 %53, 2
  %55 = icmp sgt i32 %51, %54
  br i1 %55, label %56, label %60

56:                                               ; preds = %50
  %57 = load i64, ptr %8, align 8, !tbaa !9
  %58 = trunc i64 %57 to i32
  %59 = sub nsw i32 %58, 2
  store i32 %59, ptr %16, align 4, !tbaa !13
  store float 1.000000e+00, ptr %17, align 4, !tbaa !11
  br label %60

60:                                               ; preds = %56, %50
  %61 = load i32, ptr %16, align 4, !tbaa !13
  %62 = load i64, ptr %10, align 8, !tbaa !9
  %63 = trunc i64 %62 to i32
  %64 = mul nsw i32 %61, %63
  %65 = load ptr, ptr %11, align 8, !tbaa !5
  %66 = load i64, ptr %14, align 8, !tbaa !9
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %65, i64 noundef %66)
  store i32 %64, ptr %67, align 4, !tbaa !13
  %68 = load float, ptr %17, align 4, !tbaa !11
  %69 = fsub float 2.000000e+00, %68
  %70 = fmul float 1.280000e+02, %69
  %71 = load float, ptr %17, align 4, !tbaa !11
  %72 = fsub float 1.000000e+00, %71
  %73 = fmul float %70, %72
  %74 = load float, ptr %17, align 4, !tbaa !11
  %75 = fmul float %73, %74
  %76 = fdiv float %75, 6.000000e+00
  %77 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %76)
  %78 = load ptr, ptr %12, align 8, !tbaa !5
  %79 = load i64, ptr %14, align 8, !tbaa !9
  %80 = mul i64 %79, 4
  %81 = add i64 %80, 0
  %82 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %78, i64 noundef %81)
  store i32 %77, ptr %82, align 4, !tbaa !13
  %83 = load float, ptr %17, align 4, !tbaa !11
  %84 = fsub float %83, 2.000000e+00
  %85 = fmul float 1.280000e+02, %84
  %86 = load float, ptr %17, align 4, !tbaa !11
  %87 = fadd float %86, 1.000000e+00
  %88 = fmul float %85, %87
  %89 = load float, ptr %17, align 4, !tbaa !11
  %90 = fsub float 1.000000e+00, %89
  %91 = fmul float %88, %90
  %92 = fdiv float %91, 2.000000e+00
  %93 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %92)
  %94 = load ptr, ptr %12, align 8, !tbaa !5
  %95 = load i64, ptr %14, align 8, !tbaa !9
  %96 = mul i64 %95, 4
  %97 = add i64 %96, 1
  %98 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %94, i64 noundef %97)
  store i32 %93, ptr %98, align 4, !tbaa !13
  %99 = load float, ptr %17, align 4, !tbaa !11
  %100 = fsub float %99, 2.000000e+00
  %101 = fmul float 1.280000e+02, %100
  %102 = load float, ptr %17, align 4, !tbaa !11
  %103 = fadd float %102, 1.000000e+00
  %104 = fmul float %101, %103
  %105 = load float, ptr %17, align 4, !tbaa !11
  %106 = fmul float %104, %105
  %107 = fdiv float %106, 2.000000e+00
  %108 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %107)
  %109 = load ptr, ptr %12, align 8, !tbaa !5
  %110 = load i64, ptr %14, align 8, !tbaa !9
  %111 = mul i64 %110, 4
  %112 = add i64 %111, 2
  %113 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %109, i64 noundef %112)
  store i32 %108, ptr %113, align 4, !tbaa !13
  %114 = load float, ptr %17, align 4, !tbaa !11
  %115 = fadd float 1.000000e+00, %114
  %116 = fmul float 1.280000e+02, %115
  %117 = load float, ptr %17, align 4, !tbaa !11
  %118 = fsub float 1.000000e+00, %117
  %119 = fmul float %116, %118
  %120 = load float, ptr %17, align 4, !tbaa !11
  %121 = fmul float %119, %120
  %122 = fdiv float %121, 6.000000e+00
  %123 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %122)
  %124 = load ptr, ptr %12, align 8, !tbaa !5
  %125 = load i64, ptr %14, align 8, !tbaa !9
  %126 = mul i64 %125, 4
  %127 = add i64 %126, 3
  %128 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %124, i64 noundef %127)
  store i32 %123, ptr %128, align 4, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #7
  br label %129

129:                                              ; preds = %60
  %130 = load i64, ptr %14, align 8, !tbaa !9
  %131 = add i64 %130, 1
  store i64 %131, ptr %14, align 8, !tbaa !9
  br label %29, !llvm.loop !15

132:                                              ; preds = %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #7
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt5floorf(float noundef) #4

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) #5 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd5RoundEf(float noundef) #6

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18ResizerByteBicubic18EstimateIndexAlphaEmmmRNS_5ArrayIiEES4_(ptr nocapture noundef nonnull readnone align 8 dereferenceable(216) %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef nonnull align 8 dereferenceable(16) %4, ptr noundef nonnull align 8 dereferenceable(16) %5) local_unnamed_addr #0 align 2 {
  tail call void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %2, i1 noundef zeroext false, i64 noundef 8)
  %7 = shl i64 %2, 2
  tail call void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %5, i64 noundef %7, i1 noundef zeroext false, i64 noundef 8)
  %8 = uitofp i64 %1 to float
  %9 = uitofp i64 %2 to float
  %10 = fdiv float %8, %9
  %.not = icmp eq i64 %2, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %6
  %11 = trunc i64 %1 to i32
  %12 = add nsw i32 %11, -2
  %13 = trunc i64 %3 to i32
  br label %14

._crit_edge:                                      ; preds = %14, %6
  ret void

14:                                               ; preds = %.lr.ph, %14
  %.04447 = phi i64 [ 0, %.lr.ph ], [ %56, %14 ]
  %15 = uitofp i64 %.04447 to float
  %16 = fadd float %15, 5.000000e-01
  %17 = tail call float @llvm.fmuladd.f32(float %16, float %10, float -5.000000e-01)
  %18 = tail call noundef float @_ZSt5floorf(float noundef %17)
  %19 = fptosi float %18 to i32
  %20 = sitofp i32 %19 to float
  %21 = fsub float %17, %20
  %22 = icmp slt i32 %19, 0
  %.042 = tail call i32 @llvm.smax.i32(i32 %19, i32 0)
  %.0 = select i1 %22, float 0.000000e+00, float %21
  %23 = icmp sgt i32 %.042, %12
  %.143 = tail call i32 @llvm.smin.i32(i32 %.042, i32 %12)
  %.1 = select i1 %23, float 1.000000e+00, float %.0
  %24 = mul nsw i32 %.143, %13
  %25 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %.04447)
  store i32 %24, ptr %25, align 4, !tbaa !5
  %26 = fsub float 2.000000e+00, %.1
  %27 = fmul float %26, 1.280000e+02
  %28 = fsub float 1.000000e+00, %.1
  %29 = fmul float %28, %27
  %30 = fmul float %.1, %29
  %31 = fdiv float %30, 6.000000e+00
  %32 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %31)
  %33 = shl i64 %.04447, 2
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %5, i64 noundef %33)
  store i32 %32, ptr %34, align 4, !tbaa !5
  %35 = fadd float %.1, -2.000000e+00
  %36 = fmul float %35, 1.280000e+02
  %37 = fadd float %.1, 1.000000e+00
  %38 = fmul float %37, %36
  %39 = fmul float %28, %38
  %40 = fmul float %39, 5.000000e-01
  %41 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %40)
  %42 = or disjoint i64 %33, 1
  %43 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %5, i64 noundef %42)
  store i32 %41, ptr %43, align 4, !tbaa !5
  %44 = fmul float %.1, %38
  %45 = fmul float %44, 5.000000e-01
  %46 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %45)
  %47 = or disjoint i64 %33, 2
  %48 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %5, i64 noundef %47)
  store i32 %46, ptr %48, align 4, !tbaa !5
  %49 = fmul float %37, 1.280000e+02
  %50 = fmul float %28, %49
  %51 = fmul float %.1, %50
  %52 = fdiv float %51, 6.000000e+00
  %53 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %52)
  %54 = or disjoint i64 %33, 3
  %55 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16) %5, i64 noundef %54)
  store i32 %53, ptr %55, align 4, !tbaa !5
  %56 = add nuw i64 %.04447, 1
  %exitcond.not = icmp eq i64 %56, %2
  br i1 %exitcond.not, label %._crit_edge, label %14, !llvm.loop !9
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIiE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt5floorf(float noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIiEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) local_unnamed_addr #4 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd5RoundEf(float noundef) local_unnamed_addr #5

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smax.i32(i32, i32) #6

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smin.i32(i32, i32) #6

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass