; LLVM IR from Tudor67/Competitive-Programming :: Codeforces/#703#div2/D/D.ll (Z7isValidRKiRKSt6vectorIiSaIiEES0_S0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@__dso_handle = external hidden global i8
@_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum = external hidden global %"class.std::vector", align 8
@_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum = external hidden global i64, align 8

; Function Attrs: nounwind
declare i32 @__cxa_atexit(ptr, ptr, ptr) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z7isValidRKiRKSt6vectorIiSaIiEES0_S0_(ptr noundef nonnull align 4 dereferenceable(4) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 4 dereferenceable(4) %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %14 = load atomic i8, ptr @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum acquire, align 8
  %15 = icmp eq i8 %14, 0
  br i1 %15, label %16, label %21, !prof !9

16:                                               ; preds = %4
  %17 = call i32 @__cxa_guard_acquire(ptr @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #0
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %21

19:                                               ; preds = %16
  call void @_ZNSt6vectorIiSaIiEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #0
  %20 = call i32 @__cxa_atexit(ptr @_ZNSt6vectorIiSaIiEED2Ev, ptr @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, ptr @__dso_handle) #0
  call void @__cxa_guard_release(ptr @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #0
  br label %21

21:                                               ; preds = %19, %16, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #0
  %22 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #0
  %23 = trunc i64 %22 to i32
  store i32 %23, ptr %9, align 4, !tbaa !10
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %9, ptr noundef nonnull align 4 dereferenceable(4) %24)
  %26 = load i32, ptr %25, align 4, !tbaa !10
  %27 = sext i32 %26 to i64
  call void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %27)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #0
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #0
  store i8 0, ptr %10, align 1, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #0
  store i32 0, ptr %11, align 4, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #0
  store i32 0, ptr %12, align 4, !tbaa !10
  br label %28

28:                                               ; preds = %98, %21
  %29 = load i32, ptr %12, align 4, !tbaa !10
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = load i32, ptr %30, align 4, !tbaa !10
  %32 = icmp slt i32 %29, %31
  br i1 %32, label %34, label %33

33:                                               ; preds = %28
  store i32 2, ptr %13, align 4
  br label %101

34:                                               ; preds = %28
  %35 = load i32, ptr %12, align 4, !tbaa !10
  %36 = load ptr, ptr %8, align 8, !tbaa !5
  %37 = load i32, ptr %36, align 4, !tbaa !10
  %38 = icmp sge i32 %35, %37
  br i1 %38, label %39, label %48

39:                                               ; preds = %34
  %40 = load i32, ptr %12, align 4, !tbaa !10
  %41 = load ptr, ptr %8, align 8, !tbaa !5
  %42 = load i32, ptr %41, align 4, !tbaa !10
  %43 = sub nsw i32 %40, %42
  %44 = sext i32 %43 to i64
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %44) #0
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %45, ptr noundef nonnull align 4 dereferenceable(4) %11)
  %47 = load i32, ptr %46, align 4, !tbaa !10
  store i32 %47, ptr %11, align 4, !tbaa !10
  br label %48

48:                                               ; preds = %39, %34
  %49 = load i32, ptr %12, align 4, !tbaa !10
  %50 = icmp eq i32 %49, 0
  br i1 %50, label %51, label %52

51:                                               ; preds = %48
  br label %58

52:                                               ; preds = %48
  %53 = load i32, ptr %12, align 4, !tbaa !10
  %54 = sub nsw i32 %53, 1
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %55) #0
  %57 = load i32, ptr %56, align 4, !tbaa !10
  br label %58

58:                                               ; preds = %52, %51
  %59 = phi i32 [ 0, %51 ], [ %57, %52 ]
  %60 = load i32, ptr %12, align 4, !tbaa !10
  %61 = sext i32 %60 to i64
  %62 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %61) #0
  store i32 %59, ptr %62, align 4, !tbaa !10
  %63 = load ptr, ptr %6, align 8, !tbaa !5
  %64 = load i32, ptr %12, align 4, !tbaa !10
  %65 = sext i32 %64 to i64
  %66 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %65) #0
  %67 = load i32, ptr %66, align 4, !tbaa !10
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  %69 = load i32, ptr %68, align 4, !tbaa !10
  %70 = icmp slt i32 %67, %69
  br i1 %70, label %71, label %77

71:                                               ; preds = %58
  %72 = load i32, ptr %12, align 4, !tbaa !10
  %73 = sext i32 %72 to i64
  %74 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %73) #0
  %75 = load i32, ptr %74, align 4, !tbaa !10
  %76 = sub nsw i32 %75, 1
  store i32 %76, ptr %74, align 4, !tbaa !10
  br label %83

77:                                               ; preds = %58
  %78 = load i32, ptr %12, align 4, !tbaa !10
  %79 = sext i32 %78 to i64
  %80 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %79) #0
  %81 = load i32, ptr %80, align 4, !tbaa !10
  %82 = add nsw i32 %81, 1
  store i32 %82, ptr %80, align 4, !tbaa !10
  br label %83

83:                                               ; preds = %77, %71
  %84 = load i32, ptr %12, align 4, !tbaa !10
  %85 = load ptr, ptr %8, align 8, !tbaa !5
  %86 = load i32, ptr %85, align 4, !tbaa !10
  %87 = sub nsw i32 %86, 1
  %88 = icmp sge i32 %84, %87
  br i1 %88, label %89, label %97

89:                                               ; preds = %83
  %90 = load i32, ptr %11, align 4, !tbaa !10
  %91 = load i32, ptr %12, align 4, !tbaa !10
  %92 = sext i32 %91 to i64
  %93 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %92) #0
  %94 = load i32, ptr %93, align 4, !tbaa !10
  %95 = icmp slt i32 %90, %94
  br i1 %95, label %96, label %97

96:                                               ; preds = %89
  store i8 1, ptr %10, align 1, !tbaa !12
  store i32 2, ptr %13, align 4
  br label %101

97:                                               ; preds = %89, %83
  br label %98

98:                                               ; preds = %97
  %99 = load i32, ptr %12, align 4, !tbaa !10
  %100 = add nsw i32 %99, 1
  store i32 %100, ptr %12, align 4, !tbaa !10
  br label %28, !llvm.loop !14

101:                                              ; preds = %96, %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #0
  br label %102

102:                                              ; preds = %101
  %103 = load i8, ptr %10, align 1, !tbaa !12, !range !16, !noundef !17
  %104 = trunc i8 %103 to i1
  store i32 1, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #0
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #0
  ret i1 %104
}

; Function Attrs: nounwind
declare i32 @__cxa_guard_acquire(ptr) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @__cxa_guard_release(ptr) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { nounwind }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!"branch_weights", i32 1, i32 1048575}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"bool", !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = !{i8 0, i8 2}
!17 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@__dso_handle = external hidden global i8
@_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum = external hidden global %"class.std::vector", align 8
@_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum = external hidden global i64, align 8

; Function Attrs: nofree nounwind
declare i32 @__cxa_atexit(ptr, ptr, ptr) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z7isValidRKiRKSt6vectorIiSaIiEES0_S0_(ptr nocapture noundef nonnull readonly align 4 dereferenceable(4) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr nocapture noundef nonnull readonly align 4 dereferenceable(4) %3) local_unnamed_addr #1 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = load atomic i8, ptr @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum acquire, align 8
  %8 = icmp eq i8 %7, 0
  br i1 %8, label %9, label %13, !prof !5

9:                                                ; preds = %4
  %10 = tail call i32 @__cxa_guard_acquire(ptr nonnull @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #5
  %.not = icmp eq i32 %10, 0
  br i1 %.not, label %13, label %11

11:                                               ; preds = %9
  tail call void @_ZNSt6vectorIiSaIiEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #5
  %12 = tail call i32 @__cxa_atexit(ptr nonnull @_ZNSt6vectorIiSaIiEED2Ev, ptr nonnull @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, ptr nonnull @__dso_handle) #5
  tail call void @__cxa_guard_release(ptr nonnull @_ZGVZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #5
  br label %13

13:                                               ; preds = %11, %9, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #5
  %14 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum) #5
  %15 = trunc i64 %14 to i32
  store i32 %15, ptr %5, align 4, !tbaa !6
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 4 dereferenceable(4) %2)
  %17 = load i32, ptr %16, align 4, !tbaa !6
  %18 = sext i32 %17 to i64
  call void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %18)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #5
  store i32 0, ptr %6, align 4, !tbaa !6
  %19 = load i32, ptr %2, align 4, !tbaa !6
  %20 = icmp sgt i32 %19, 0
  br i1 %20, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %13
  %21 = load i32, ptr %3, align 4, !tbaa !6
  %.not21.peel = icmp sgt i32 %21, 0
  br i1 %.not21.peel, label %28, label %22

22:                                               ; preds = %.lr.ph.preheader
  %23 = sext i32 %21 to i64
  %24 = sub nsw i64 0, %23
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %24) #5
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %25, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %27 = load i32, ptr %26, align 4, !tbaa !6
  store i32 %27, ptr %6, align 4, !tbaa !6
  br label %28

28:                                               ; preds = %.lr.ph.preheader, %22
  %29 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef 0) #5
  store i32 0, ptr %29, align 4, !tbaa !6
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef 0) #5
  %31 = load i32, ptr %30, align 4, !tbaa !6
  %32 = load i32, ptr %0, align 4, !tbaa !6
  %33 = icmp slt i32 %31, %32
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef 0) #5
  %35 = load i32, ptr %34, align 4, !tbaa !6
  %. = select i1 %33, i32 -1, i32 1
  %36 = add nsw i32 %35, %.
  store i32 %36, ptr %34, align 4, !tbaa !6
  %37 = load i32, ptr %3, align 4, !tbaa !6
  %.not22.peel = icmp sgt i32 %37, 1
  br i1 %.not22.peel, label %43, label %38

38:                                               ; preds = %28
  %39 = load i32, ptr %6, align 4, !tbaa !6
  %40 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef 0) #5
  %41 = load i32, ptr %40, align 4, !tbaa !6
  %42 = icmp slt i32 %39, %41
  br i1 %42, label %._crit_edge, label %43

43:                                               ; preds = %38, %28
  %44 = load i32, ptr %2, align 4, !tbaa !6
  %45 = icmp sgt i32 %44, 1
  br i1 %45, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %43, %73
  %indvars.iv = phi i64 [ %indvars.iv.next, %73 ], [ 1, %43 ]
  %46 = load i32, ptr %3, align 4, !tbaa !6
  %47 = sext i32 %46 to i64
  %.not21 = icmp slt i64 %indvars.iv, %47
  br i1 %.not21, label %53, label %48

48:                                               ; preds = %.lr.ph
  %49 = sub nsw i64 %indvars.iv, %47
  %50 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %49) #5
  %51 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %50, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %52 = load i32, ptr %51, align 4, !tbaa !6
  store i32 %52, ptr %6, align 4, !tbaa !6
  br label %53

53:                                               ; preds = %48, %.lr.ph
  %54 = add nsw i64 %indvars.iv, -1
  %55 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %54) #5
  %56 = load i32, ptr %55, align 4, !tbaa !6
  %57 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %indvars.iv) #5
  store i32 %56, ptr %57, align 4, !tbaa !6
  %58 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #5
  %59 = load i32, ptr %58, align 4, !tbaa !6
  %60 = load i32, ptr %0, align 4, !tbaa !6
  %61 = icmp slt i32 %59, %60
  %62 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %indvars.iv) #5
  %63 = load i32, ptr %62, align 4, !tbaa !6
  %.30 = select i1 %61, i32 -1, i32 1
  %64 = add nsw i32 %63, %.30
  store i32 %64, ptr %62, align 4, !tbaa !6
  %65 = load i32, ptr %3, align 4, !tbaa !6
  %66 = add nsw i32 %65, -1
  %67 = sext i32 %66 to i64
  %.not22 = icmp slt i64 %indvars.iv, %67
  br i1 %.not22, label %73, label %68

68:                                               ; preds = %53
  %69 = load i32, ptr %6, align 4, !tbaa !6
  %70 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ7isValidRKiRKSt6vectorIiSaIiEES0_S0_E7prefSum, i64 noundef %indvars.iv) #5
  %71 = load i32, ptr %70, align 4, !tbaa !6
  %72 = icmp slt i32 %69, %71
  br i1 %72, label %._crit_edge, label %73

73:                                               ; preds = %53, %68
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %74 = load i32, ptr %2, align 4, !tbaa !6
  %75 = sext i32 %74 to i64
  %76 = icmp slt i64 %indvars.iv.next, %75
  br i1 %76, label %.lr.ph, label %._crit_edge, !llvm.loop !10

._crit_edge:                                      ; preds = %73, %68, %38, %43, %13
  %.lcssa = phi i1 [ false, %13 ], [ true, %38 ], [ false, %43 ], [ false, %73 ], [ true, %68 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #5
  ret i1 %.lcssa
}

; Function Attrs: nofree nounwind
declare i32 @__cxa_guard_acquire(ptr) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nofree nounwind
declare void @__cxa_guard_release(ptr) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { nofree nounwind }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!"branch_weights", i32 1, i32 1048575}
!6 = !{!7, !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = distinct !{!10, !11, !12}
!11 = !{!"llvm.loop.mustprogress"}
!12 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopFullUnrollPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass