; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseDetection)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Detection::Data" = type { %"struct.Simd::Deletable", i8, i8, i8, i32, i32, i32, %"struct.Simd::Point", %"class.std::vector", %"class.std::vector.4", %"class.std::vector.9", %"class.std::vector.14", %"class.std::vector.19", %"class.std::vector.24", %"class.std::vector.29" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Point" = type { i64, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.9" = type { %"struct.std::_Vector_base.10" }
%"struct.std::_Vector_base.10" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.14" = type { %"struct.std::_Vector_base.15" }
%"struct.std::_Vector_base.15" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.24" = type { %"struct.std::_Vector_base.25" }
%"struct.std::_Vector_base.25" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.29" = type { %"struct.std::_Vector_base.30" }
%"struct.std::_Vector_base.30" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Detection::Data::Stage" = type { i32, i32, float }
%"struct.Simd::Detection::HidLbpStage" = type { i32, i32, float }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Simd4Base7InitLbpIfEEvRKNS_9Detection4DataEmPNS2_11HidLbpStageIT_EEPS7_(ptr noundef nonnull align 8 dereferenceable(208) %0, i64 noundef %1, ptr noundef %2, ptr noundef %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %11, i32 0, i32 8
  %13 = load i64, ptr %6, align 8, !tbaa !9
  %14 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %13) #2
  %15 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %14, i32 0, i32 0
  %16 = load i32, ptr %15, align 4, !tbaa !11
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  %18 = load i64, ptr %6, align 8, !tbaa !9
  %19 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %17, i64 %18
  %20 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %19, i32 0, i32 0
  store i32 %16, ptr %20, align 4, !tbaa !15
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %21, i32 0, i32 8
  %23 = load i64, ptr %6, align 8, !tbaa !9
  %24 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %23) #2
  %25 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %24, i32 0, i32 1
  %26 = load i32, ptr %25, align 4, !tbaa !17
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = load i64, ptr %6, align 8, !tbaa !9
  %29 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %27, i64 %28
  %30 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %29, i32 0, i32 1
  store i32 %26, ptr %30, align 4, !tbaa !18
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %31, i32 0, i32 8
  %33 = load i64, ptr %6, align 8, !tbaa !9
  %34 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %33) #2
  %35 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %34, i32 0, i32 2
  %36 = load float, ptr %35, align 4, !tbaa !19
  %37 = load ptr, ptr %7, align 8, !tbaa !5
  %38 = load i64, ptr %6, align 8, !tbaa !9
  %39 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %37, i64 %38
  %40 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %39, i32 0, i32 2
  store float %36, ptr %40, align 4, !tbaa !20
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  %42 = load i64, ptr %6, align 8, !tbaa !9
  %43 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %41, i64 %42
  %44 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %43, i32 0, i32 0
  %45 = load i32, ptr %44, align 4, !tbaa !15
  %46 = mul nsw i32 %45, 2
  store i32 %46, ptr %9, align 4, !tbaa !21
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  %47 = load ptr, ptr %7, align 8, !tbaa !5
  %48 = load i64, ptr %6, align 8, !tbaa !9
  %49 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %47, i64 %48
  %50 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %49, i32 0, i32 0
  %51 = load i32, ptr %50, align 4, !tbaa !15
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = load i64, ptr %6, align 8, !tbaa !9
  %54 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %52, i64 %53
  %55 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %54, i32 0, i32 1
  %56 = load i32, ptr %55, align 4, !tbaa !18
  %57 = add nsw i32 %51, %56
  %58 = mul nsw i32 %57, 2
  store i32 %58, ptr %10, align 4, !tbaa !21
  br label %59

59:                                               ; preds = %75, %4
  %60 = load i32, ptr %9, align 4, !tbaa !21
  %61 = load i32, ptr %10, align 4, !tbaa !21
  %62 = icmp slt i32 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  br label %78

64:                                               ; preds = %59
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  %66 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %65, i32 0, i32 11
  %67 = load i32, ptr %9, align 4, !tbaa !21
  %68 = sext i32 %67 to i64
  %69 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %66, i64 noundef %68) #2
  %70 = load float, ptr %69, align 4, !tbaa !22
  %71 = load ptr, ptr %8, align 8, !tbaa !5
  %72 = load i32, ptr %9, align 4, !tbaa !21
  %73 = sext i32 %72 to i64
  %74 = getelementptr inbounds float, ptr %71, i64 %73
  store float %70, ptr %74, align 4, !tbaa !22
  br label %75

75:                                               ; preds = %64
  %76 = load i32, ptr %9, align 4, !tbaa !21
  %77 = add nsw i32 %76, 1
  store i32 %77, ptr %9, align 4, !tbaa !21
  br label %59, !llvm.loop !23

78:                                               ; preds = %63
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"_ZTSN4Simd9Detection4Data5StageE", !13, i64 0, !13, i64 4, !14, i64 8}
!13 = !{!"int", !7, i64 0}
!14 = !{!"float", !7, i64 0}
!15 = !{!16, !13, i64 0}
!16 = !{!"_ZTSN4Simd9Detection11HidLbpStageIfEE", !13, i64 0, !13, i64 4, !14, i64 8}
!17 = !{!12, !13, i64 4}
!18 = !{!16, !13, i64 4}
!19 = !{!12, !14, i64 8}
!20 = !{!16, !14, i64 8}
!21 = !{!13, !13, i64 0}
!22 = !{!14, !14, i64 0}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Detection::HidLbpStage" = type { i32, i32, float }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Simd4Base7InitLbpIfEEvRKNS_9Detection4DataEmPNS2_11HidLbpStageIT_EEPS7_(ptr noundef nonnull align 8 dereferenceable(208) %0, i64 noundef %1, ptr nocapture noundef %2, ptr nocapture noundef writeonly %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #1
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage", ptr %2, i64 %1
  store i32 %7, ptr %8, align 4, !tbaa !11
  %9 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #1
  %10 = getelementptr inbounds i8, ptr %9, i64 4
  %11 = load i32, ptr %10, align 4, !tbaa !13
  %12 = getelementptr inbounds i8, ptr %8, i64 4
  store i32 %11, ptr %12, align 4, !tbaa !14
  %13 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #1
  %14 = getelementptr inbounds i8, ptr %13, i64 8
  %15 = load float, ptr %14, align 4, !tbaa !15
  %16 = getelementptr inbounds i8, ptr %8, i64 8
  store float %15, ptr %16, align 4, !tbaa !16
  %17 = load i32, ptr %12, align 4, !tbaa !14
  %18 = icmp sgt i32 %17, 0
  br i1 %18, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %4
  %19 = load i32, ptr %8, align 4, !tbaa !11
  %20 = shl nsw i32 %19, 1
  %21 = getelementptr inbounds i8, ptr %0, i64 112
  %22 = sext i32 %20 to i64
  %23 = add i32 %17, %19
  %24 = shl i32 %23, 1
  br label %25

._crit_edge:                                      ; preds = %25, %4
  ret void

25:                                               ; preds = %.lr.ph, %25
  %indvars.iv = phi i64 [ %22, %.lr.ph ], [ %indvars.iv.next, %25 ]
  %26 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %indvars.iv) #1
  %27 = load float, ptr %26, align 4, !tbaa !17
  %28 = getelementptr inbounds float, ptr %3, i64 %indvars.iv
  store float %27, ptr %28, align 4, !tbaa !17
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond.not = icmp eq i32 %24, %lftr.wideiv
  br i1 %exitcond.not, label %._crit_edge, label %25, !llvm.loop !18
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN4Simd9Detection4Data5StageE", !7, i64 0, !7, i64 4, !10, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"float", !8, i64 0}
!11 = !{!12, !7, i64 0}
!12 = !{!"_ZTSN4Simd9Detection11HidLbpStageIfEE", !7, i64 0, !7, i64 4, !10, i64 8}
!13 = !{!6, !7, i64 4}
!14 = !{!12, !7, i64 4}
!15 = !{!6, !10, i64 8}
!16 = !{!12, !10, i64 8}
!17 = !{!10, !10, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass