; LLVM IR from libxsmm/libxsmm :: src (generator_common_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.libxsmm_generated_code = type { ptr, i32, i32, i32, i32, i32, i32 }

declare void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef) #0

declare void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #0

declare void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gelu_inv_ps_minimax3_avx512(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9, i32 noundef %10, i32 noundef %11, i32 noundef %12, i32 noundef %13, i32 noundef %14, i32 noundef %15) #1 {
  %17 = alloca ptr, align 8
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca i32, align 4
  %25 = alloca i32, align 4
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca i32, align 4
  %30 = alloca i32, align 4
  %31 = alloca i32, align 4
  %32 = alloca i32, align 4
  store ptr %0, ptr %17, align 8, !tbaa !5
  store i32 %1, ptr %18, align 4, !tbaa !9
  store i32 %2, ptr %19, align 4, !tbaa !9
  store i32 %3, ptr %20, align 4, !tbaa !9
  store i32 %4, ptr %21, align 4, !tbaa !9
  store i32 %5, ptr %22, align 4, !tbaa !9
  store i32 %6, ptr %23, align 4, !tbaa !9
  store i32 %7, ptr %24, align 4, !tbaa !9
  store i32 %8, ptr %25, align 4, !tbaa !9
  store i32 %9, ptr %26, align 4, !tbaa !9
  store i32 %10, ptr %27, align 4, !tbaa !9
  store i32 %11, ptr %28, align 4, !tbaa !9
  store i32 %12, ptr %29, align 4, !tbaa !9
  store i32 %13, ptr %30, align 4, !tbaa !9
  store i32 %14, ptr %31, align 4, !tbaa !9
  store i32 %15, ptr %32, align 4, !tbaa !9
  %33 = load ptr, ptr %17, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.libxsmm_generated_code, ptr %33, i32 0, i32 6
  %35 = load i32, ptr %34, align 4, !tbaa !11
  %36 = icmp uge i32 %35, 1101
  br i1 %36, label %37, label %46

37:                                               ; preds = %16
  %38 = load ptr, ptr %17, align 8, !tbaa !5
  %39 = load i32, ptr %25, align 4, !tbaa !9
  %40 = load i32, ptr %18, align 4, !tbaa !9
  %41 = load i32, ptr %19, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %38, i32 noundef -267569584, i8 noundef signext 122, i32 noundef %39, i32 noundef %40, i32 noundef %41, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 8, i32 noundef 2)
  %42 = load ptr, ptr %17, align 8, !tbaa !5
  %43 = load i32, ptr %19, align 4, !tbaa !9
  %44 = load i32, ptr %26, align 4, !tbaa !9
  %45 = load i32, ptr %20, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %42, i32 noundef 805639899, i8 noundef signext 122, i32 noundef %43, i32 noundef %44, i32 noundef %45)
  br label %68

46:                                               ; preds = %16
  %47 = load ptr, ptr %17, align 8, !tbaa !5
  %48 = load i32, ptr %18, align 4, !tbaa !9
  %49 = load i32, ptr %19, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef %47, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %48, i32 noundef %49)
  %50 = load ptr, ptr %17, align 8, !tbaa !5
  %51 = load i32, ptr %19, align 4, !tbaa !9
  %52 = load i32, ptr %19, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef %50, i32 noundef 606934642, i8 noundef signext 122, i32 noundef %51, i32 noundef %52, i32 noundef 31)
  %53 = load ptr, ptr %17, align 8, !tbaa !5
  %54 = load i32, ptr %19, align 4, !tbaa !9
  %55 = load i32, ptr %19, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef %53, i32 noundef 611128946, i8 noundef signext 122, i32 noundef %54, i32 noundef %55, i32 noundef 31)
  %56 = load ptr, ptr %17, align 8, !tbaa !5
  %57 = load i32, ptr %18, align 4, !tbaa !9
  %58 = load i32, ptr %26, align 4, !tbaa !9
  %59 = load i32, ptr %20, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %56, i32 noundef 805639899, i8 noundef signext 122, i32 noundef %57, i32 noundef %58, i32 noundef %59)
  %60 = load ptr, ptr %17, align 8, !tbaa !5
  %61 = load i32, ptr %20, align 4, !tbaa !9
  %62 = load i32, ptr %25, align 4, !tbaa !9
  %63 = load i32, ptr %20, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %60, i32 noundef 805573981, i8 noundef signext 122, i32 noundef %61, i32 noundef %62, i32 noundef %63)
  %64 = load ptr, ptr %17, align 8, !tbaa !5
  %65 = load i32, ptr %19, align 4, !tbaa !9
  %66 = load i32, ptr %20, align 4, !tbaa !9
  %67 = load i32, ptr %19, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %64, i32 noundef 805639915, i8 noundef signext 122, i32 noundef %65, i32 noundef %66, i32 noundef %67)
  br label %68

68:                                               ; preds = %46, %37
  %69 = load ptr, ptr %17, align 8, !tbaa !5
  %70 = load i32, ptr %20, align 4, !tbaa !9
  %71 = load i32, ptr %21, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef %69, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %70, i32 noundef %71)
  %72 = load ptr, ptr %17, align 8, !tbaa !5
  %73 = load i32, ptr %28, align 4, !tbaa !9
  %74 = load i32, ptr %27, align 4, !tbaa !9
  %75 = load i32, ptr %21, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %72, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %73, i32 noundef %74, i32 noundef %75)
  %76 = load ptr, ptr %17, align 8, !tbaa !5
  %77 = load i32, ptr %32, align 4, !tbaa !9
  %78 = load i32, ptr %21, align 4, !tbaa !9
  %79 = load i32, ptr %24, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %76, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %77, i32 noundef %78, i32 noundef %79, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0)
  %80 = load ptr, ptr %17, align 8, !tbaa !5
  %81 = load i32, ptr %31, align 4, !tbaa !9
  %82 = load i32, ptr %21, align 4, !tbaa !9
  %83 = load i32, ptr %23, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %80, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %81, i32 noundef %82, i32 noundef %83, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0)
  %84 = load ptr, ptr %17, align 8, !tbaa !5
  %85 = load i32, ptr %30, align 4, !tbaa !9
  %86 = load i32, ptr %21, align 4, !tbaa !9
  %87 = load i32, ptr %22, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %84, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %85, i32 noundef %86, i32 noundef %87, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0)
  %88 = load ptr, ptr %17, align 8, !tbaa !5
  %89 = load i32, ptr %23, align 4, !tbaa !9
  %90 = load i32, ptr %20, align 4, !tbaa !9
  %91 = load i32, ptr %24, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %88, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %89, i32 noundef %90, i32 noundef %91)
  %92 = load ptr, ptr %17, align 8, !tbaa !5
  %93 = load i32, ptr %22, align 4, !tbaa !9
  %94 = load i32, ptr %20, align 4, !tbaa !9
  %95 = load i32, ptr %24, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %92, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %93, i32 noundef %94, i32 noundef %95)
  %96 = load ptr, ptr %17, align 8, !tbaa !5
  %97 = load i32, ptr %29, align 4, !tbaa !9
  %98 = load i32, ptr %19, align 4, !tbaa !9
  %99 = load i32, ptr %24, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef %96, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %97, i32 noundef %98, i32 noundef %99)
  %100 = load ptr, ptr %17, align 8, !tbaa !5
  %101 = load i32, ptr %24, align 4, !tbaa !9
  %102 = load i32, ptr %18, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef %100, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %101, i32 noundef %102)
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 28}
!12 = !{!"libxsmm_generated_code", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gelu_inv_ps_minimax3_avx512(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9, i32 noundef %10, i32 noundef %11, i32 noundef %12, i32 noundef %13, i32 noundef %14, i32 noundef %15) local_unnamed_addr #1 {
  %17 = getelementptr inbounds i8, ptr %0, i64 28
  %18 = load i32, ptr %17, align 4, !tbaa !5
  %19 = icmp ugt i32 %18, 1100
  br i1 %19, label %20, label %21

20:                                               ; preds = %16
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef nonnull %0, i32 noundef -267569584, i8 noundef signext 122, i32 noundef %8, i32 noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 8, i32 noundef 2) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805639899, i8 noundef signext 122, i32 noundef %2, i32 noundef %9, i32 noundef %3) #2
  br label %22

21:                                               ; preds = %16
  tail call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef nonnull %0, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %1, i32 noundef %2) #2
  tail call void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef nonnull %0, i32 noundef 606934642, i8 noundef signext 122, i32 noundef %2, i32 noundef %2, i32 noundef 31) #2
  tail call void @libxsmm_x86_instruction_vec_compute_2reg_imm8(ptr noundef nonnull %0, i32 noundef 611128946, i8 noundef signext 122, i32 noundef %2, i32 noundef %2, i32 noundef 31) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805639899, i8 noundef signext 122, i32 noundef %1, i32 noundef %9, i32 noundef %3) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805573981, i8 noundef signext 122, i32 noundef %3, i32 noundef %8, i32 noundef %3) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805639915, i8 noundef signext 122, i32 noundef %2, i32 noundef %3, i32 noundef %2) #2
  br label %22

22:                                               ; preds = %21, %20
  tail call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef nonnull %0, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %3, i32 noundef %4) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %11, i32 noundef %10, i32 noundef %4) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef nonnull %0, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %15, i32 noundef %4, i32 noundef %7, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef nonnull %0, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %14, i32 noundef %4, i32 noundef %6, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef nonnull %0, i32 noundef 805643830, i8 noundef signext 122, i32 noundef %13, i32 noundef %4, i32 noundef %5, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %6, i32 noundef %3, i32 noundef %7) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %5, i32 noundef %3, i32 noundef %7) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg(ptr noundef nonnull %0, i32 noundef 805643944, i8 noundef signext 122, i32 noundef %12, i32 noundef %2, i32 noundef %7) #2
  tail call void @libxsmm_x86_instruction_vec_compute_2reg(ptr noundef nonnull %0, i32 noundef -528083345, i8 noundef signext 122, i32 noundef %7, i32 noundef %1) #2
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 28}
!6 = !{!"libxsmm_generated_code", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,InstCombinePass,SROAPass,TailCallElimPass