; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_64x16_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 0, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %14, i32 noundef 4)
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = mul i32 %16, 4
  call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %15, i32 noundef 8, i32 noundef %17, i32 noundef 43, i32 noundef 1)
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %182, %5
  %19 = load i32, ptr %11, align 4, !tbaa !9
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = icmp ugt i32 %20, 8
  %22 = zext i1 %21 to i64
  %23 = select i1 %21, i32 2, i32 1
  %24 = icmp ult i32 %19, %23
  br i1 %24, label %25, label %185

25:                                               ; preds = %18
  %26 = load i32, ptr %11, align 4, !tbaa !9
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %78

28:                                               ; preds = %25
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %49, %28
  %30 = load i32, ptr %12, align 4, !tbaa !9
  %31 = load i32, ptr %9, align 4, !tbaa !9
  %32 = icmp ugt i32 %31, 3
  br i1 %32, label %33, label %34

33:                                               ; preds = %29
  br label %36

34:                                               ; preds = %29
  %35 = load i32, ptr %9, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %34, %33
  %37 = phi i32 [ 4, %33 ], [ %35, %34 ]
  %38 = icmp ult i32 %30, %37
  br i1 %38, label %39, label %52

39:                                               ; preds = %36
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = load i32, ptr %12, align 4, !tbaa !9
  %42 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %40, i32 noundef -1589592064, i32 noundef %41, i32 noundef %42, i32 noundef 0, i32 noundef 8)
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !9
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = load i32, ptr %10, align 4, !tbaa !9
  %47 = mul i32 %46, 4
  %48 = zext i32 %47 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %43, i32 noundef 4096, i32 noundef %44, i32 noundef 43, i32 noundef %45, i64 noundef %48)
  br label %49

49:                                               ; preds = %39
  %50 = load i32, ptr %12, align 4, !tbaa !9
  %51 = add i32 %50, 1
  store i32 %51, ptr %12, align 4, !tbaa !9
  br label %29, !llvm.loop !11

52:                                               ; preds = %36
  store i32 16, ptr %12, align 4, !tbaa !9
  br label %53

53:                                               ; preds = %74, %52
  %54 = load i32, ptr %12, align 4, !tbaa !9
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = icmp ugt i32 %55, 7
  br i1 %56, label %57, label %58

57:                                               ; preds = %53
  br label %61

58:                                               ; preds = %53
  %59 = load i32, ptr %9, align 4, !tbaa !9
  %60 = add i32 %59, 12
  br label %61

61:                                               ; preds = %58, %57
  %62 = phi i32 [ 20, %57 ], [ %60, %58 ]
  %63 = icmp ult i32 %54, %62
  br i1 %63, label %64, label %77

64:                                               ; preds = %61
  %65 = load ptr, ptr %6, align 8, !tbaa !5
  %66 = load i32, ptr %12, align 4, !tbaa !9
  %67 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %65, i32 noundef -1589592064, i32 noundef %66, i32 noundef %67, i32 noundef 0, i32 noundef 8)
  %68 = load ptr, ptr %6, align 8, !tbaa !5
  %69 = load i32, ptr %7, align 4, !tbaa !9
  %70 = load i32, ptr %7, align 4, !tbaa !9
  %71 = load i32, ptr %10, align 4, !tbaa !9
  %72 = mul i32 %71, 4
  %73 = zext i32 %72 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %68, i32 noundef 4096, i32 noundef %69, i32 noundef 43, i32 noundef %70, i64 noundef %73)
  br label %74

74:                                               ; preds = %64
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = add i32 %75, 1
  store i32 %76, ptr %12, align 4, !tbaa !9
  br label %53, !llvm.loop !13

77:                                               ; preds = %61
  br label %129

78:                                               ; preds = %25
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %79

79:                                               ; preds = %100, %78
  %80 = load i32, ptr %12, align 4, !tbaa !9
  %81 = load i32, ptr %9, align 4, !tbaa !9
  %82 = icmp ugt i32 %81, 11
  br i1 %82, label %83, label %84

83:                                               ; preds = %79
  br label %87

84:                                               ; preds = %79
  %85 = load i32, ptr %9, align 4, !tbaa !9
  %86 = sub i32 %85, 8
  br label %87

87:                                               ; preds = %84, %83
  %88 = phi i32 [ 4, %83 ], [ %86, %84 ]
  %89 = icmp ult i32 %80, %88
  br i1 %89, label %90, label %103

90:                                               ; preds = %87
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = load i32, ptr %12, align 4, !tbaa !9
  %93 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %91, i32 noundef -1589592064, i32 noundef %92, i32 noundef %93, i32 noundef 0, i32 noundef 8)
  %94 = load ptr, ptr %6, align 8, !tbaa !5
  %95 = load i32, ptr %7, align 4, !tbaa !9
  %96 = load i32, ptr %7, align 4, !tbaa !9
  %97 = load i32, ptr %10, align 4, !tbaa !9
  %98 = mul i32 %97, 4
  %99 = zext i32 %98 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %94, i32 noundef 4096, i32 noundef %95, i32 noundef 43, i32 noundef %96, i64 noundef %99)
  br label %100

100:                                              ; preds = %90
  %101 = load i32, ptr %12, align 4, !tbaa !9
  %102 = add i32 %101, 1
  store i32 %102, ptr %12, align 4, !tbaa !9
  br label %79, !llvm.loop !14

103:                                              ; preds = %87
  store i32 16, ptr %12, align 4, !tbaa !9
  br label %104

104:                                              ; preds = %125, %103
  %105 = load i32, ptr %12, align 4, !tbaa !9
  %106 = load i32, ptr %9, align 4, !tbaa !9
  %107 = icmp ugt i32 %106, 15
  br i1 %107, label %108, label %109

108:                                              ; preds = %104
  br label %112

109:                                              ; preds = %104
  %110 = load i32, ptr %9, align 4, !tbaa !9
  %111 = add i32 %110, 4
  br label %112

112:                                              ; preds = %109, %108
  %113 = phi i32 [ 20, %108 ], [ %111, %109 ]
  %114 = icmp ult i32 %105, %113
  br i1 %114, label %115, label %128

115:                                              ; preds = %112
  %116 = load ptr, ptr %6, align 8, !tbaa !5
  %117 = load i32, ptr %12, align 4, !tbaa !9
  %118 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %116, i32 noundef -1589592064, i32 noundef %117, i32 noundef %118, i32 noundef 0, i32 noundef 8)
  %119 = load ptr, ptr %6, align 8, !tbaa !5
  %120 = load i32, ptr %7, align 4, !tbaa !9
  %121 = load i32, ptr %7, align 4, !tbaa !9
  %122 = load i32, ptr %10, align 4, !tbaa !9
  %123 = mul i32 %122, 4
  %124 = zext i32 %123 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %119, i32 noundef 4096, i32 noundef %120, i32 noundef 43, i32 noundef %121, i64 noundef %124)
  br label %125

125:                                              ; preds = %115
  %126 = load i32, ptr %12, align 4, !tbaa !9
  %127 = add i32 %126, 1
  store i32 %127, ptr %12, align 4, !tbaa !9
  br label %104, !llvm.loop !15

128:                                              ; preds = %112
  br label %129

129:                                              ; preds = %128, %77
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %130

130:                                              ; preds = %139, %129
  %131 = load i32, ptr %13, align 4, !tbaa !9
  %132 = icmp ult i32 %131, 2
  br i1 %132, label %133, label %142

133:                                              ; preds = %130
  %134 = load ptr, ptr %6, align 8, !tbaa !5
  %135 = load i32, ptr %13, align 4, !tbaa !9
  %136 = mul i32 %135, 4
  %137 = add i32 0, %136
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %134, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef %137)
  %138 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %138, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %139

139:                                              ; preds = %133
  %140 = load i32, ptr %13, align 4, !tbaa !9
  %141 = add i32 %140, 1
  store i32 %141, ptr %13, align 4, !tbaa !9
  br label %130, !llvm.loop !16

142:                                              ; preds = %130
  store i32 2, ptr %13, align 4, !tbaa !9
  br label %143

143:                                              ; preds = %152, %142
  %144 = load i32, ptr %13, align 4, !tbaa !9
  %145 = icmp ult i32 %144, 4
  br i1 %145, label %146, label %155

146:                                              ; preds = %143
  %147 = load ptr, ptr %6, align 8, !tbaa !5
  %148 = load i32, ptr %13, align 4, !tbaa !9
  %149 = mul i32 %148, 4
  %150 = add i32 1, %149
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %147, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %150)
  %151 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %151, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %152

152:                                              ; preds = %146
  %153 = load i32, ptr %13, align 4, !tbaa !9
  %154 = add i32 %153, 1
  store i32 %154, ptr %13, align 4, !tbaa !9
  br label %143, !llvm.loop !17

155:                                              ; preds = %143
  store i32 4, ptr %13, align 4, !tbaa !9
  br label %156

156:                                              ; preds = %165, %155
  %157 = load i32, ptr %13, align 4, !tbaa !9
  %158 = icmp ult i32 %157, 6
  br i1 %158, label %159, label %168

159:                                              ; preds = %156
  %160 = load ptr, ptr %6, align 8, !tbaa !5
  %161 = load i32, ptr %13, align 4, !tbaa !9
  %162 = mul i32 %161, 4
  %163 = add i32 2, %162
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %160, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef %163)
  %164 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %164, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0)
  br label %165

165:                                              ; preds = %159
  %166 = load i32, ptr %13, align 4, !tbaa !9
  %167 = add i32 %166, 1
  store i32 %167, ptr %13, align 4, !tbaa !9
  br label %156, !llvm.loop !18

168:                                              ; preds = %156
  store i32 6, ptr %13, align 4, !tbaa !9
  br label %169

169:                                              ; preds = %178, %168
  %170 = load i32, ptr %13, align 4, !tbaa !9
  %171 = icmp ult i32 %170, 8
  br i1 %171, label %172, label %181

172:                                              ; preds = %169
  %173 = load ptr, ptr %6, align 8, !tbaa !5
  %174 = load i32, ptr %13, align 4, !tbaa !9
  %175 = mul i32 %174, 4
  %176 = add i32 3, %175
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %173, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef %176)
  %177 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %177, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0)
  br label %178

178:                                              ; preds = %172
  %179 = load i32, ptr %13, align 4, !tbaa !9
  %180 = add i32 %179, 1
  store i32 %180, ptr %13, align 4, !tbaa !9
  br label %169, !llvm.loop !19

181:                                              ; preds = %169
  br label %182

182:                                              ; preds = %181
  %183 = load i32, ptr %11, align 4, !tbaa !9
  %184 = add i32 %183, 1
  store i32 %184, ptr %11, align 4, !tbaa !9
  br label %18, !llvm.loop !20

185:                                              ; preds = %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}
!20 = distinct !{!20, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_64x16_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #1 {
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef 4)
  %6 = shl i32 %2, 2
  tail call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %0, i32 noundef 8, i32 noundef %6, i32 noundef 43, i32 noundef 1)
  %7 = icmp ugt i32 %3, 8
  %8 = icmp ugt i32 %3, 11
  %9 = add nsw i32 %3, -8
  %10 = select i1 %8, i32 4, i32 %9
  %.not = icmp eq i32 %10, 0
  %11 = shl i32 %4, 2
  %12 = zext i32 %11 to i64
  %13 = icmp ugt i32 %3, 15
  %14 = add nuw nsw i32 %3, 4
  %15 = select i1 %13, i32 20, i32 %14
  %16 = icmp ugt i32 %15, 16
  %17 = tail call i32 @llvm.umin.i32(i32 %3, i32 4)
  %.not94 = icmp eq i32 %3, 0
  %18 = icmp ugt i32 %3, 7
  %19 = add nuw nsw i32 %3, 12
  %20 = select i1 %18, i32 20, i32 %19
  %21 = icmp ugt i32 %20, 16
  br label %22

22:                                               ; preds = %5, %.loopexit
  %23 = phi i1 [ true, %5 ], [ false, %.loopexit ]
  br i1 %23, label %.preheader78, label %.preheader81

.preheader81:                                     ; preds = %22
  br i1 %.not, label %.preheader79, label %.lr.ph

.preheader78:                                     ; preds = %22
  br i1 %.not94, label %.preheader77, label %.lr.ph86

.preheader77:                                     ; preds = %.lr.ph86, %.preheader78
  br i1 %21, label %.lr.ph88, label %.loopexit

.lr.ph86:                                         ; preds = %.preheader78, %.lr.ph86
  %.07085 = phi i32 [ %24, %.lr.ph86 ], [ 0, %.preheader78 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589592064, i32 noundef %.07085, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %24 = add nuw nsw i32 %.07085, 1
  %exitcond97.not = icmp eq i32 %24, %17
  br i1 %exitcond97.not, label %.preheader77, label %.lr.ph86, !llvm.loop !5

.lr.ph88:                                         ; preds = %.preheader77, %.lr.ph88
  %.17187 = phi i32 [ %25, %.lr.ph88 ], [ 16, %.preheader77 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589592064, i32 noundef %.17187, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %25 = add nuw i32 %.17187, 1
  %exitcond98.not = icmp eq i32 %25, %20
  br i1 %exitcond98.not, label %.loopexit, label %.lr.ph88, !llvm.loop !7

.preheader79:                                     ; preds = %.lr.ph, %.preheader81
  br i1 %16, label %.lr.ph84, label %.loopexit

.lr.ph:                                           ; preds = %.preheader81, %.lr.ph
  %.27282 = phi i32 [ %26, %.lr.ph ], [ 0, %.preheader81 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589592064, i32 noundef %.27282, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %26 = add nuw i32 %.27282, 1
  %exitcond.not = icmp eq i32 %26, %10
  br i1 %exitcond.not, label %.preheader79, label %.lr.ph, !llvm.loop !8

.lr.ph84:                                         ; preds = %.preheader79, %.lr.ph84
  %.37383 = phi i32 [ %27, %.lr.ph84 ], [ 16, %.preheader79 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589592064, i32 noundef %.37383, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %27 = add nuw i32 %.37383, 1
  %exitcond96.not = icmp eq i32 %27, %15
  br i1 %exitcond96.not, label %.loopexit, label %.lr.ph84, !llvm.loop !9

.loopexit:                                        ; preds = %.lr.ph84, %.lr.ph88, %.preheader79, %.preheader77
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 9) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 13) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 18) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 22) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 27) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 31) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  %28 = and i1 %7, %23
  br i1 %28, label %22, label %29, !llvm.loop !10

29:                                               ; preds = %.loopexit
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}
!9 = distinct !{!9, !6}
!10 = distinct !{!10, !6}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass