; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetMergedConvolution8i)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }
%"class.Simd::Base::SynetMergedConvolution8i" = type { %"class.Simd::SynetMergedConvolution8i", %"struct.Simd::MergConvParam8i", i8, i8, i8, i8, i64, i64, [2 x i64], [5 x i64], [3 x %"struct.Simd::CvtParam"], %"struct.Simd::Array", [2 x %"struct.Simd::Array.1"], %"struct.Simd::Array.0", [2 x %"struct.Simd::Array.0"], [3 x %"struct.Simd::Array.0"], [3 x %"struct.Simd::Array.0"], %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr, ptr, ptr, ptr, [2 x ptr], %"class.std::__cxx11::basic_string" }
%"class.Simd::SynetMergedConvolution8i" = type { %"struct.Simd::Deletable" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::MergConvParam8i" = type { i64, [3 x %"struct.Simd::ConvParam"] }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::CvtParam" = type <{ %"struct.Simd::Array", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", i8, [3 x i8], i32, i32, i32, i32, [4 x i8] }>
%"struct.Simd::Array" = type { ptr, i64 }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Base::SynetMergedConvolution8i::AlgParam" = type { i64, i64, [3 x i64], [3 x i64], [3 x i64], [2 x i64], [3 x i64], i64, i32, i32 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24SynetMergedConvolution8i19ReorderOutputWeightERKNS_9ConvParamERNS_5ArrayIaEE(ptr noundef nonnull align 8 dereferenceable(1376) %0, ptr noundef nonnull align 8 dereferenceable(180) %1, ptr noundef nonnull align 8 dereferenceable(16) %2) #3 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca %"struct.Simd::Array.1", align 8
  %12 = alloca ptr, align 8
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  %15 = alloca i64, align 8
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  %18 = alloca i64, align 8
  %19 = alloca i64, align 8
  %20 = alloca ptr, align 8
  %21 = alloca i64, align 8
  %22 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %23 = load ptr, ptr %4, align 8
  %24 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution8i", ptr %23, i32 0, i32 17
  %25 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr %24, i32 0, i32 0
  %26 = load i64, ptr %25, align 8, !tbaa !9
  %27 = icmp eq i64 %26, 0
  br i1 %27, label %28, label %29

28:                                               ; preds = %3
  br label %167

29:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %30 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution8i", ptr %23, i32 0, i32 17
  %31 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr %30, i32 0, i32 0
  %32 = load i64, ptr %31, align 8, !tbaa !9
  %33 = mul i64 %32, 2
  store i64 %33, ptr %7, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %34, i32 0, i32 0
  %36 = load i64, ptr %35, align 8, !tbaa !23
  %37 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %36, i64 noundef 4)
  store i64 %37, ptr %8, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %38, i32 0, i32 5
  %40 = load i64, ptr %39, align 8, !tbaa !28
  %41 = load i64, ptr %7, align 8, !tbaa !22
  %42 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %40, i64 noundef %41)
  store i64 %42, ptr %9, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %43 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution8i", ptr %23, i32 0, i32 17
  %44 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr %43, i32 0, i32 1
  %45 = load i64, ptr %44, align 8, !tbaa !29
  %46 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %45, i64 noundef 4)
  store i64 %46, ptr %10, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #4
  %47 = load i64, ptr %8, align 8, !tbaa !22
  %48 = load i64, ptr %9, align 8, !tbaa !22
  %49 = mul i64 %47, %48
  %50 = load i64, ptr %7, align 8, !tbaa !22
  %51 = mul i64 %49, %50
  %52 = mul i64 %51, 4
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %11, i64 noundef %52, i1 noundef zeroext false, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %53 = getelementptr inbounds %"struct.Simd::Array.1", ptr %11, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !30
  store ptr %54, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 0, ptr %13, align 8, !tbaa !22
  br label %55

55:                                               ; preds = %160, %29
  %56 = load i64, ptr %13, align 8, !tbaa !22
  %57 = load i64, ptr %8, align 8, !tbaa !22
  %58 = icmp ult i64 %56, %57
  br i1 %58, label %60, label %59

59:                                               ; preds = %55
  store i32 2, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %164

60:                                               ; preds = %55
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  %61 = load i64, ptr %8, align 8, !tbaa !22
  %62 = load i64, ptr %13, align 8, !tbaa !22
  %63 = load i64, ptr %10, align 8, !tbaa !22
  %64 = add i64 %62, %63
  %65 = invoke noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %61, i64 noundef %64)
          to label %66 unwind label %72

66:                                               ; preds = %60
  store i64 %65, ptr %15, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #4
  store i64 0, ptr %18, align 8, !tbaa !22
  br label %67

67:                                               ; preds = %156, %66
  %68 = load i64, ptr %18, align 8, !tbaa !22
  %69 = load i64, ptr %9, align 8, !tbaa !22
  %70 = icmp ult i64 %68, %69
  br i1 %70, label %76, label %71

71:                                               ; preds = %67
  store i32 5, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #4
  br label %159

72:                                               ; preds = %60
  %73 = landingpad { ptr, i32 }
          cleanup
  %74 = extractvalue { ptr, i32 } %73, 0
  store ptr %74, ptr %16, align 8
  %75 = extractvalue { ptr, i32 } %73, 1
  store i32 %75, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %172

76:                                               ; preds = %67
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #4
  %77 = load i64, ptr %13, align 8, !tbaa !22
  store i64 %77, ptr %19, align 8, !tbaa !22
  br label %78

78:                                               ; preds = %152, %76
  %79 = load i64, ptr %19, align 8, !tbaa !22
  %80 = load i64, ptr %15, align 8, !tbaa !22
  %81 = icmp ult i64 %79, %80
  br i1 %81, label %83, label %82

82:                                               ; preds = %78
  store i32 8, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #4
  br label %155

83:                                               ; preds = %78
  call void @llvm.lifetime.start.p0(i64 8, ptr %20) #4
  %84 = load ptr, ptr %6, align 8, !tbaa !5
  %85 = getelementptr inbounds %"struct.Simd::Array.1", ptr %84, i32 0, i32 0
  %86 = load ptr, ptr %85, align 8, !tbaa !30
  %87 = load i64, ptr %19, align 8, !tbaa !22
  %88 = mul i64 %87, 4
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %89, i32 0, i32 5
  %91 = load i64, ptr %90, align 8, !tbaa !28
  %92 = mul i64 %88, %91
  %93 = getelementptr inbounds i8, ptr %86, i64 %92
  %94 = load i64, ptr %18, align 8, !tbaa !22
  %95 = load i64, ptr %7, align 8, !tbaa !22
  %96 = mul i64 %94, %95
  %97 = getelementptr inbounds i8, ptr %93, i64 %96
  store ptr %97, ptr %20, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %21) #4
  store i64 0, ptr %21, align 8, !tbaa !22
  br label %98

98:                                               ; preds = %148, %83
  %99 = load i64, ptr %21, align 8, !tbaa !22
  %100 = load i64, ptr %7, align 8, !tbaa !22
  %101 = icmp ult i64 %99, %100
  br i1 %101, label %103, label %102

102:                                              ; preds = %98
  store i32 11, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %21) #4
  br label %151

103:                                              ; preds = %98
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #4
  store i64 0, ptr %22, align 8, !tbaa !22
  br label %104

104:                                              ; preds = %142, %103
  %105 = load i64, ptr %22, align 8, !tbaa !22
  %106 = icmp ult i64 %105, 4
  br i1 %106, label %108, label %107

107:                                              ; preds = %104
  store i32 14, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #4
  br label %145

108:                                              ; preds = %104
  %109 = load i64, ptr %18, align 8, !tbaa !22
  %110 = load i64, ptr %7, align 8, !tbaa !22
  %111 = mul i64 %109, %110
  %112 = load i64, ptr %21, align 8, !tbaa !22
  %113 = add i64 %111, %112
  %114 = load ptr, ptr %5, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %114, i32 0, i32 5
  %116 = load i64, ptr %115, align 8, !tbaa !28
  %117 = icmp ult i64 %113, %116
  br i1 %117, label %118, label %138

118:                                              ; preds = %108
  %119 = load i64, ptr %19, align 8, !tbaa !22
  %120 = mul i64 %119, 4
  %121 = load i64, ptr %22, align 8, !tbaa !22
  %122 = add i64 %120, %121
  %123 = load ptr, ptr %5, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %123, i32 0, i32 0
  %125 = load i64, ptr %124, align 8, !tbaa !23
  %126 = icmp ult i64 %122, %125
  br i1 %126, label %127, label %138

127:                                              ; preds = %118
  %128 = load ptr, ptr %20, align 8, !tbaa !5
  %129 = load i64, ptr %22, align 8, !tbaa !22
  %130 = load ptr, ptr %5, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %130, i32 0, i32 5
  %132 = load i64, ptr %131, align 8, !tbaa !28
  %133 = mul i64 %129, %132
  %134 = getelementptr inbounds i8, ptr %128, i64 %133
  %135 = load i8, ptr %134, align 1, !tbaa !32
  %136 = load ptr, ptr %12, align 8, !tbaa !5
  %137 = getelementptr inbounds i8, ptr %136, i32 1
  store ptr %137, ptr %12, align 8, !tbaa !5
  store i8 %135, ptr %136, align 1, !tbaa !32
  br label %141

138:                                              ; preds = %118, %108
  %139 = load ptr, ptr %12, align 8, !tbaa !5
  %140 = getelementptr inbounds i8, ptr %139, i32 1
  store ptr %140, ptr %12, align 8, !tbaa !5
  store i8 0, ptr %139, align 1, !tbaa !32
  br label %141

141:                                              ; preds = %138, %127
  br label %142

142:                                              ; preds = %141
  %143 = load i64, ptr %22, align 8, !tbaa !22
  %144 = add i64 %143, 1
  store i64 %144, ptr %22, align 8, !tbaa !22
  br label %104, !llvm.loop !33

145:                                              ; preds = %107
  %146 = load ptr, ptr %20, align 8, !tbaa !5
  %147 = getelementptr inbounds i8, ptr %146, i32 1
  store ptr %147, ptr %20, align 8, !tbaa !5
  br label %148

148:                                              ; preds = %145
  %149 = load i64, ptr %21, align 8, !tbaa !22
  %150 = add i64 %149, 1
  store i64 %150, ptr %21, align 8, !tbaa !22
  br label %98, !llvm.loop !35

151:                                              ; preds = %102
  call void @llvm.lifetime.end.p0(i64 8, ptr %20) #4
  br label %152

152:                                              ; preds = %151
  %153 = load i64, ptr %19, align 8, !tbaa !22
  %154 = add i64 %153, 1
  store i64 %154, ptr %19, align 8, !tbaa !22
  br label %78, !llvm.loop !36

155:                                              ; preds = %82
  br label %156

156:                                              ; preds = %155
  %157 = load i64, ptr %18, align 8, !tbaa !22
  %158 = add i64 %157, 1
  store i64 %158, ptr %18, align 8, !tbaa !22
  br label %67, !llvm.loop !37

159:                                              ; preds = %71
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  br label %160

160:                                              ; preds = %159
  %161 = load i64, ptr %10, align 8, !tbaa !22
  %162 = load i64, ptr %13, align 8, !tbaa !22
  %163 = add i64 %162, %161
  store i64 %163, ptr %13, align 8, !tbaa !22
  br label %55, !llvm.loop !38

164:                                              ; preds = %59
  %165 = load ptr, ptr %6, align 8, !tbaa !5
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %165, ptr noundef nonnull align 8 dereferenceable(16) %11)
          to label %166 unwind label %168

166:                                              ; preds = %164
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %11) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %167

167:                                              ; preds = %166, %28
  ret void

168:                                              ; preds = %164
  %169 = landingpad { ptr, i32 }
          cleanup
  %170 = extractvalue { ptr, i32 } %169, 0
  store ptr %170, ptr %16, align 8
  %171 = extractvalue { ptr, i32 } %169, 1
  store i32 %171, ptr %17, align 4
  br label %172

172:                                              ; preds = %168, %72
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %11) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %173

173:                                              ; preds = %172
  %174 = load ptr, ptr %16, align 8
  %175 = load i32, ptr %17, align 4
  %176 = insertvalue { ptr, i32 } poison, ptr %174, 0
  %177 = insertvalue { ptr, i32 } %176, i32 %175, 1
  resume { ptr, i32 } %177
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) #1

attributes #0 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !14, i64 1152}
!10 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8iE", !11, i64 0, !13, i64 8, !15, i64 568, !15, i64 569, !15, i64 570, !15, i64 571, !14, i64 576, !14, i64 584, !7, i64 592, !7, i64 608, !7, i64 648, !16, i64 960, !7, i64 976, !17, i64 1008, !7, i64 1024, !7, i64 1056, !7, i64 1104, !18, i64 1152, !6, i64 1296, !6, i64 1304, !6, i64 1312, !6, i64 1320, !7, i64 1328, !20, i64 1344}
!11 = !{!"_ZTSN4Simd24SynetMergedConvolution8iE", !12, i64 0}
!12 = !{!"_ZTSN4Simd9DeletableE"}
!13 = !{!"_ZTSN4Simd15MergConvParam8iE", !14, i64 0, !7, i64 8}
!14 = !{!"long", !7, i64 0}
!15 = !{!"bool", !7, i64 0}
!16 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !14, i64 8}
!17 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !14, i64 8}
!18 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8i8AlgParamE", !14, i64 0, !14, i64 8, !7, i64 16, !7, i64 40, !7, i64 64, !7, i64 88, !7, i64 104, !14, i64 128, !19, i64 136, !19, i64 140}
!19 = !{!"int", !7, i64 0}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !14, i64 8, !7, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!22 = !{!14, !14, i64 0}
!23 = !{!24, !14, i64 0}
!24 = !{!"_ZTS25SimdConvolutionParameters", !14, i64 0, !14, i64 8, !14, i64 16, !25, i64 24, !26, i64 28, !14, i64 32, !14, i64 40, !14, i64 48, !25, i64 56, !26, i64 60, !14, i64 64, !14, i64 72, !14, i64 80, !14, i64 88, !14, i64 96, !14, i64 104, !14, i64 112, !14, i64 120, !14, i64 128, !14, i64 136, !14, i64 144, !27, i64 152}
!25 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!26 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!27 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!28 = !{!24, !14, i64 32}
!29 = !{!10, !14, i64 1160}
!30 = !{!31, !6, i64 0}
!31 = !{!"_ZTSN4Simd5ArrayIaEE", !6, i64 0, !14, i64 8}
!32 = !{!7, !7, i64 0}
!33 = distinct !{!33, !34}
!34 = !{!"llvm.loop.mustprogress"}
!35 = distinct !{!35, !34}
!36 = distinct !{!36, !34}
!37 = distinct !{!37, !34}
!38 = distinct !{!38, !34}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24SynetMergedConvolution8i19ReorderOutputWeightERKNS_9ConvParamERNS_5ArrayIaEE(ptr nocapture noundef nonnull readonly align 8 dereferenceable(1376) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(180) %1, ptr noundef nonnull align 8 dereferenceable(16) %2) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca %"struct.Simd::Array.1", align 8
  %5 = getelementptr inbounds i8, ptr %0, i64 1152
  %6 = load i64, ptr %5, align 8, !tbaa !5
  %.fr = freeze i64 %6
  %7 = icmp eq i64 %.fr, 0
  br i1 %7, label %82, label %8

8:                                                ; preds = %3
  %9 = shl i64 %.fr, 1
  %10 = load i64, ptr %1, align 8, !tbaa !21
  %11 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %10, i64 noundef 4)
  %12 = getelementptr inbounds i8, ptr %1, i64 32
  %13 = load i64, ptr %12, align 8, !tbaa !26
  %14 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %13, i64 noundef %9)
  %15 = getelementptr inbounds i8, ptr %0, i64 1160
  %16 = load i64, ptr %15, align 8, !tbaa !27
  %17 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %16, i64 noundef 4)
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #4
  %18 = shl i64 %.fr, 3
  %19 = mul i64 %18, %11
  %20 = mul i64 %19, %14
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %20, i1 noundef zeroext false, i64 noundef 8)
  %21 = load ptr, ptr %4, align 8, !tbaa !28
  %.not = icmp eq i64 %11, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %8
  %.not82 = icmp eq i64 %14, 0
  br i1 %.not82, label %.loopexit, label %.lr.ph.split.us

.lr.ph.split.us:                                  ; preds = %.lr.ph
  %.not84 = icmp eq i64 %9, 0
  br i1 %.not84, label %.preheader55.lr.ph.us, label %.preheader55.lr.ph.us.us

.preheader55.lr.ph.us.us:                         ; preds = %.lr.ph.split.us, %..loopexit_crit_edge.us.us
  %.05073.us.us = phi ptr [ %.us-phi71.us.us, %..loopexit_crit_edge.us.us ], [ %21, %.lr.ph.split.us ]
  %.05172.us.us = phi i64 [ %22, %..loopexit_crit_edge.us.us ], [ 0, %.lr.ph.split.us ]
  %22 = add i64 %.05172.us.us, %17
  %23 = call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %11, i64 noundef %22)
  %24 = icmp ult i64 %.05172.us.us, %23
  br i1 %24, label %.preheader55.us.us.us.us, label %..loopexit_crit_edge.us.us

..loopexit_crit_edge.us.us:                       ; preds = %._crit_edge63.split.us.us.us.us.us, %.preheader55.lr.ph.us.us
  %.us-phi71.us.us = phi ptr [ %.05073.us.us, %.preheader55.lr.ph.us.us ], [ %.5.us.us.us.us.us.3, %._crit_edge63.split.us.us.us.us.us ]
  %25 = icmp ult i64 %22, %11
  br i1 %25, label %.preheader55.lr.ph.us.us, label %._crit_edge, !llvm.loop !30

.preheader55.us.us.us.us:                         ; preds = %.preheader55.lr.ph.us.us, %._crit_edge63.split.us.us.us.us.us
  %.04966.us.us.us.us = phi i64 [ %74, %._crit_edge63.split.us.us.us.us.us ], [ 0, %.preheader55.lr.ph.us.us ]
  %.165.us.us.us.us = phi ptr [ %.5.us.us.us.us.us.3, %._crit_edge63.split.us.us.us.us.us ], [ %.05073.us.us, %.preheader55.lr.ph.us.us ]
  %26 = mul i64 %.04966.us.us.us.us, %9
  br label %.preheader.lr.ph.us.us.us.us.us

.preheader.lr.ph.us.us.us.us.us:                  ; preds = %._crit_edge.us.us.us.us.us, %.preheader55.us.us.us.us
  %.04862.us.us.us.us.us = phi i64 [ %.05172.us.us, %.preheader55.us.us.us.us ], [ %72, %._crit_edge.us.us.us.us.us ]
  %.261.us.us.us.us.us = phi ptr [ %.165.us.us.us.us, %.preheader55.us.us.us.us ], [ %.5.us.us.us.us.us.3, %._crit_edge.us.us.us.us.us ]
  %27 = load ptr, ptr %2, align 8, !tbaa !28
  %28 = shl i64 %.04862.us.us.us.us.us, 2
  %29 = load i64, ptr %12, align 8, !tbaa !26
  %30 = mul i64 %29, %28
  %31 = getelementptr inbounds i8, ptr %27, i64 %30
  %32 = getelementptr inbounds i8, ptr %31, i64 %26
  %33 = or disjoint i64 %28, 1
  %34 = or disjoint i64 %28, 2
  %35 = or disjoint i64 %28, 3
  br label %.preheader.us.us.us.us.us

36:                                               ; preds = %.preheader.us.us.us.us.us
  %37 = load i8, ptr %.04759.us.us.us.us.us, align 1, !tbaa !32
  br label %38

38:                                               ; preds = %36, %.preheader.us.us.us.us.us
  %storemerge.us.us.us.us.us = phi i8 [ %37, %36 ], [ 0, %.preheader.us.us.us.us.us ]
  %.5.us.us.us.us.us = getelementptr inbounds i8, ptr %.358.us.us.us.us.us, i64 1
  store i8 %storemerge.us.us.us.us.us, ptr %.358.us.us.us.us.us, align 1, !tbaa !32
  %39 = load i64, ptr %12, align 8, !tbaa !26
  %40 = icmp ult i64 %67, %39
  %41 = load i64, ptr %1, align 8
  %42 = icmp ult i64 %33, %41
  %or.cond94 = select i1 %40, i1 %42, i1 false
  br i1 %or.cond94, label %43, label %46

43:                                               ; preds = %38
  %44 = getelementptr inbounds i8, ptr %.04759.us.us.us.us.us, i64 %39
  %45 = load i8, ptr %44, align 1, !tbaa !32
  br label %46

46:                                               ; preds = %43, %38
  %storemerge.us.us.us.us.us.1 = phi i8 [ %45, %43 ], [ 0, %38 ]
  %.5.us.us.us.us.us.1 = getelementptr inbounds i8, ptr %.358.us.us.us.us.us, i64 2
  store i8 %storemerge.us.us.us.us.us.1, ptr %.5.us.us.us.us.us, align 1, !tbaa !32
  %47 = load i64, ptr %12, align 8, !tbaa !26
  %48 = icmp ult i64 %67, %47
  %49 = load i64, ptr %1, align 8
  %50 = icmp ult i64 %34, %49
  %or.cond96 = select i1 %48, i1 %50, i1 false
  br i1 %or.cond96, label %51, label %55

51:                                               ; preds = %46
  %52 = shl i64 %47, 1
  %53 = getelementptr inbounds i8, ptr %.04759.us.us.us.us.us, i64 %52
  %54 = load i8, ptr %53, align 1, !tbaa !32
  br label %55

55:                                               ; preds = %51, %46
  %storemerge.us.us.us.us.us.2 = phi i8 [ %54, %51 ], [ 0, %46 ]
  %.5.us.us.us.us.us.2 = getelementptr inbounds i8, ptr %.358.us.us.us.us.us, i64 3
  store i8 %storemerge.us.us.us.us.us.2, ptr %.5.us.us.us.us.us.1, align 1, !tbaa !32
  %56 = load i64, ptr %12, align 8, !tbaa !26
  %57 = icmp ult i64 %67, %56
  %58 = load i64, ptr %1, align 8
  %59 = icmp ult i64 %35, %58
  %or.cond98 = select i1 %57, i1 %59, i1 false
  br i1 %or.cond98, label %60, label %64

60:                                               ; preds = %55
  %61 = mul i64 %56, 3
  %62 = getelementptr inbounds i8, ptr %.04759.us.us.us.us.us, i64 %61
  %63 = load i8, ptr %62, align 1, !tbaa !32
  br label %64

64:                                               ; preds = %60, %55
  %storemerge.us.us.us.us.us.3 = phi i8 [ %63, %60 ], [ 0, %55 ]
  %.5.us.us.us.us.us.3 = getelementptr inbounds i8, ptr %.358.us.us.us.us.us, i64 4
  store i8 %storemerge.us.us.us.us.us.3, ptr %.5.us.us.us.us.us.2, align 1, !tbaa !32
  %65 = getelementptr inbounds i8, ptr %.04759.us.us.us.us.us, i64 1
  %66 = add nuw i64 %.04660.us.us.us.us.us, 1
  %exitcond.not = icmp eq i64 %66, %9
  br i1 %exitcond.not, label %._crit_edge.us.us.us.us.us, label %.preheader.us.us.us.us.us, !llvm.loop !33

.preheader.us.us.us.us.us:                        ; preds = %64, %.preheader.lr.ph.us.us.us.us.us
  %.04660.us.us.us.us.us = phi i64 [ 0, %.preheader.lr.ph.us.us.us.us.us ], [ %66, %64 ]
  %.04759.us.us.us.us.us = phi ptr [ %32, %.preheader.lr.ph.us.us.us.us.us ], [ %65, %64 ]
  %.358.us.us.us.us.us = phi ptr [ %.261.us.us.us.us.us, %.preheader.lr.ph.us.us.us.us.us ], [ %.5.us.us.us.us.us.3, %64 ]
  %67 = add i64 %.04660.us.us.us.us.us, %26
  %68 = load i64, ptr %12, align 8, !tbaa !26
  %69 = icmp ult i64 %67, %68
  %70 = load i64, ptr %1, align 8
  %71 = icmp ult i64 %28, %70
  %or.cond = select i1 %69, i1 %71, i1 false
  br i1 %or.cond, label %36, label %38

._crit_edge.us.us.us.us.us:                       ; preds = %64
  %72 = add nuw i64 %.04862.us.us.us.us.us, 1
  %73 = icmp ult i64 %72, %23
  br i1 %73, label %.preheader.lr.ph.us.us.us.us.us, label %._crit_edge63.split.us.us.us.us.us, !llvm.loop !34

._crit_edge63.split.us.us.us.us.us:               ; preds = %._crit_edge.us.us.us.us.us
  %74 = add nuw i64 %.04966.us.us.us.us, 1
  %exitcond89.not = icmp eq i64 %74, %14
  br i1 %exitcond89.not, label %..loopexit_crit_edge.us.us, label %.preheader55.us.us.us.us, !llvm.loop !35

.preheader55.lr.ph.us:                            ; preds = %.lr.ph.split.us, %.preheader55.lr.ph.us
  %.05172.us = phi i64 [ %75, %.preheader55.lr.ph.us ], [ 0, %.lr.ph.split.us ]
  %75 = add i64 %.05172.us, %17
  %76 = call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %11, i64 noundef %75)
  %77 = icmp ult i64 %75, %11
  br i1 %77, label %.preheader55.lr.ph.us, label %._crit_edge, !llvm.loop !30

._crit_edge:                                      ; preds = %..loopexit_crit_edge.us.us, %.preheader55.lr.ph.us, %.loopexit, %8
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %2, ptr noundef nonnull align 8 dereferenceable(16) %4)
          to label %81 unwind label %83

.loopexit:                                        ; preds = %.lr.ph, %.loopexit
  %.05172 = phi i64 [ %78, %.loopexit ], [ 0, %.lr.ph ]
  %78 = add i64 %.05172, %17
  %79 = call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %11, i64 noundef %78)
  %80 = icmp ult i64 %78, %11
  br i1 %80, label %.loopexit, label %._crit_edge, !llvm.loop !30

81:                                               ; preds = %._crit_edge
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %4) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  br label %82

82:                                               ; preds = %3, %81
  ret void

83:                                               ; preds = %._crit_edge
  %84 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %4) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  resume { ptr, i32 } %84
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) local_unnamed_addr #1

attributes #0 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 1152}
!6 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8iE", !7, i64 0, !9, i64 8, !13, i64 568, !13, i64 569, !13, i64 570, !13, i64 571, !10, i64 576, !10, i64 584, !11, i64 592, !11, i64 608, !11, i64 648, !14, i64 960, !11, i64 976, !16, i64 1008, !11, i64 1024, !11, i64 1056, !11, i64 1104, !17, i64 1152, !15, i64 1296, !15, i64 1304, !15, i64 1312, !15, i64 1320, !11, i64 1328, !19, i64 1344}
!7 = !{!"_ZTSN4Simd24SynetMergedConvolution8iE", !8, i64 0}
!8 = !{!"_ZTSN4Simd9DeletableE"}
!9 = !{!"_ZTSN4Simd15MergConvParam8iE", !10, i64 0, !11, i64 8}
!10 = !{!"long", !11, i64 0}
!11 = !{!"omnipotent char", !12, i64 0}
!12 = !{!"Simple C++ TBAA"}
!13 = !{!"bool", !11, i64 0}
!14 = !{!"_ZTSN4Simd5ArrayIhEE", !15, i64 0, !10, i64 8}
!15 = !{!"any pointer", !11, i64 0}
!16 = !{!"_ZTSN4Simd5ArrayIfEE", !15, i64 0, !10, i64 8}
!17 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8i8AlgParamE", !10, i64 0, !10, i64 8, !11, i64 16, !11, i64 40, !11, i64 64, !11, i64 88, !11, i64 104, !10, i64 128, !18, i64 136, !18, i64 140}
!18 = !{!"int", !11, i64 0}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !10, i64 8, !11, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !15, i64 0}
!21 = !{!22, !10, i64 0}
!22 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !23, i64 24, !24, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !23, i64 56, !24, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !25, i64 152}
!23 = !{!"_ZTS18SimdTensorDataType", !11, i64 0}
!24 = !{!"_ZTS20SimdTensorFormatType", !11, i64 0}
!25 = !{!"_ZTS29SimdConvolutionActivationType", !11, i64 0}
!26 = !{!22, !10, i64 32}
!27 = !{!6, !10, i64 1160}
!28 = !{!29, !15, i64 0}
!29 = !{!"_ZTSN4Simd5ArrayIaEE", !15, i64 0, !10, i64 8}
!30 = distinct !{!30, !31}
!31 = !{!"llvm.loop.mustprogress"}
!32 = !{!11, !11, i64 0}
!33 = distinct !{!33, !31}
!34 = distinct !{!34, !31}
!35 = distinct !{!35, !31}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass