; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_store_2dregblock_aarch64_asimd(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) #2 {
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca [3 x i32], align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca i32, align 4
  store ptr %0, ptr %9, align 8, !tbaa !5
  store i32 %1, ptr %10, align 4, !tbaa !9
  store i32 %2, ptr %11, align 4, !tbaa !9
  store i32 %3, ptr %12, align 4, !tbaa !9
  store i32 %4, ptr %13, align 4, !tbaa !9
  store i32 %5, ptr %14, align 4, !tbaa !9
  store i32 %6, ptr %15, align 4, !tbaa !9
  store i32 %7, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #3
  store i32 0, ptr %18, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #3
  store i32 0, ptr %19, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 12, ptr %20) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #3
  store i32 0, ptr %22, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #3
  store i32 0, ptr %23, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %24) #3
  store i32 0, ptr %24, align 4, !tbaa !9
  %25 = load i32, ptr %14, align 4, !tbaa !9
  %26 = load i32, ptr %12, align 4, !tbaa !9
  %27 = udiv i32 %25, %26
  %28 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  store i32 %27, ptr %28, align 4, !tbaa !9
  %29 = load i32, ptr %14, align 4, !tbaa !9
  %30 = load i32, ptr %12, align 4, !tbaa !9
  %31 = urem i32 %29, %30
  %32 = load i32, ptr %12, align 4, !tbaa !9
  %33 = udiv i32 %32, 2
  %34 = udiv i32 %31, %33
  %35 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 1
  store i32 %34, ptr %35, align 4, !tbaa !9
  %36 = load i32, ptr %14, align 4, !tbaa !9
  %37 = load i32, ptr %12, align 4, !tbaa !9
  %38 = urem i32 %36, %37
  %39 = load i32, ptr %12, align 4, !tbaa !9
  %40 = udiv i32 %39, 2
  %41 = urem i32 %38, %40
  %42 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 2
  store i32 %41, ptr %42, align 4, !tbaa !9
  %43 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %44 = load i32, ptr %43, align 4, !tbaa !9
  %45 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 1
  %46 = load i32, ptr %45, align 4, !tbaa !9
  %47 = add i32 %44, %46
  %48 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 2
  %49 = load i32, ptr %48, align 4, !tbaa !9
  %50 = add i32 %47, %49
  store i32 %50, ptr %21, align 4, !tbaa !9
  %51 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %52 = load i32, ptr %51, align 4, !tbaa !9
  %53 = mul i32 %52, 16
  %54 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 1
  %55 = load i32, ptr %54, align 4, !tbaa !9
  %56 = mul i32 %55, 8
  %57 = add i32 %53, %56
  %58 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 2
  %59 = load i32, ptr %58, align 4, !tbaa !9
  %60 = mul i32 %59, 4
  %61 = add i32 %57, %60
  store i32 %61, ptr %22, align 4, !tbaa !9
  %62 = load i32, ptr %13, align 4, !tbaa !9
  %63 = load i32, ptr %15, align 4, !tbaa !9
  %64 = load i32, ptr %21, align 4, !tbaa !9
  %65 = mul i32 %63, %64
  %66 = sub i32 %62, %65
  store i32 %66, ptr %17, align 4, !tbaa !9
  %67 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %68 = load i32, ptr %67, align 4, !tbaa !9
  %69 = icmp eq i32 %68, 4
  br i1 %69, label %70, label %71

70:                                               ; preds = %8
  store i32 201334784, ptr %23, align 4, !tbaa !9
  store i32 64, ptr %24, align 4, !tbaa !9
  br label %89

71:                                               ; preds = %8
  %72 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %73 = load i32, ptr %72, align 4, !tbaa !9
  %74 = icmp eq i32 %73, 3
  br i1 %74, label %75, label %76

75:                                               ; preds = %71
  store i32 201351168, ptr %23, align 4, !tbaa !9
  store i32 48, ptr %24, align 4, !tbaa !9
  br label %88

76:                                               ; preds = %71
  %77 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %78 = load i32, ptr %77, align 4, !tbaa !9
  %79 = icmp eq i32 %78, 2
  br i1 %79, label %80, label %81

80:                                               ; preds = %76
  store i32 201367552, ptr %23, align 4, !tbaa !9
  store i32 32, ptr %24, align 4, !tbaa !9
  br label %87

81:                                               ; preds = %76
  %82 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %83 = load i32, ptr %82, align 4, !tbaa !9
  %84 = icmp eq i32 %83, 1
  br i1 %84, label %85, label %86

85:                                               ; preds = %81
  store i32 201355264, ptr %23, align 4, !tbaa !9
  store i32 16, ptr %24, align 4, !tbaa !9
  br label %86

86:                                               ; preds = %85, %81
  br label %87

87:                                               ; preds = %86, %80
  br label %88

88:                                               ; preds = %87, %75
  br label %89

89:                                               ; preds = %88, %70
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %90

90:                                               ; preds = %174, %89
  %91 = load i32, ptr %18, align 4, !tbaa !9
  %92 = load i32, ptr %15, align 4, !tbaa !9
  %93 = icmp ult i32 %91, %92
  br i1 %93, label %94, label %177

94:                                               ; preds = %90
  %95 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %96 = load i32, ptr %95, align 4, !tbaa !9
  %97 = icmp ugt i32 %96, 0
  br i1 %97, label %98, label %111

98:                                               ; preds = %94
  %99 = load ptr, ptr %9, align 8, !tbaa !5
  %100 = load i32, ptr %23, align 4, !tbaa !9
  %101 = load i32, ptr %10, align 4, !tbaa !9
  %102 = load i32, ptr %17, align 4, !tbaa !9
  %103 = load i32, ptr %21, align 4, !tbaa !9
  %104 = load i32, ptr %18, align 4, !tbaa !9
  %105 = mul i32 %103, %104
  %106 = add i32 %102, %105
  call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %99, i32 noundef %100, i32 noundef %101, i32 noundef 127, i32 noundef %106, i32 noundef 5)
  %107 = load ptr, ptr %9, align 8, !tbaa !5
  %108 = load i32, ptr %10, align 4, !tbaa !9
  %109 = load i32, ptr %10, align 4, !tbaa !9
  %110 = load i32, ptr %24, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %107, i32 noundef 285212678, i32 noundef %108, i32 noundef %109, i32 noundef %110, i8 noundef zeroext 0)
  br label %111

111:                                              ; preds = %98, %94
  store i32 0, ptr %19, align 4, !tbaa !9
  br label %112

112:                                              ; preds = %130, %111
  %113 = load i32, ptr %19, align 4, !tbaa !9
  %114 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 1
  %115 = load i32, ptr %114, align 4, !tbaa !9
  %116 = icmp ult i32 %113, %115
  br i1 %116, label %117, label %133

117:                                              ; preds = %112
  %118 = load ptr, ptr %9, align 8, !tbaa !5
  %119 = load i32, ptr %10, align 4, !tbaa !9
  %120 = load i32, ptr %17, align 4, !tbaa !9
  %121 = load i32, ptr %19, align 4, !tbaa !9
  %122 = add i32 %120, %121
  %123 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %124 = load i32, ptr %123, align 4, !tbaa !9
  %125 = add i32 %122, %124
  %126 = load i32, ptr %21, align 4, !tbaa !9
  %127 = load i32, ptr %18, align 4, !tbaa !9
  %128 = mul i32 %126, %127
  %129 = add i32 %125, %128
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %118, i32 noundef 1006633990, i32 noundef %119, i32 noundef 127, i32 noundef 8, i32 noundef %129, i32 noundef 6)
  br label %130

130:                                              ; preds = %117
  %131 = load i32, ptr %19, align 4, !tbaa !9
  %132 = add i32 %131, 1
  store i32 %132, ptr %19, align 4, !tbaa !9
  br label %112, !llvm.loop !11

133:                                              ; preds = %112
  store i32 0, ptr %19, align 4, !tbaa !9
  br label %134

134:                                              ; preds = %155, %133
  %135 = load i32, ptr %19, align 4, !tbaa !9
  %136 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 2
  %137 = load i32, ptr %136, align 4, !tbaa !9
  %138 = icmp ult i32 %135, %137
  br i1 %138, label %139, label %158

139:                                              ; preds = %134
  %140 = load ptr, ptr %9, align 8, !tbaa !5
  %141 = load i32, ptr %10, align 4, !tbaa !9
  %142 = load i32, ptr %17, align 4, !tbaa !9
  %143 = load i32, ptr %19, align 4, !tbaa !9
  %144 = add i32 %142, %143
  %145 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 0
  %146 = load i32, ptr %145, align 4, !tbaa !9
  %147 = add i32 %144, %146
  %148 = getelementptr inbounds [3 x i32], ptr %20, i64 0, i64 1
  %149 = load i32, ptr %148, align 4, !tbaa !9
  %150 = add i32 %147, %149
  %151 = load i32, ptr %21, align 4, !tbaa !9
  %152 = load i32, ptr %18, align 4, !tbaa !9
  %153 = mul i32 %151, %152
  %154 = add i32 %150, %153
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %140, i32 noundef 1006633990, i32 noundef %141, i32 noundef 127, i32 noundef 4, i32 noundef %154, i32 noundef 4)
  br label %155

155:                                              ; preds = %139
  %156 = load i32, ptr %19, align 4, !tbaa !9
  %157 = add i32 %156, 1
  store i32 %157, ptr %19, align 4, !tbaa !9
  br label %134, !llvm.loop !13

158:                                              ; preds = %134
  %159 = load i32, ptr %16, align 4, !tbaa !9
  %160 = load i32, ptr %22, align 4, !tbaa !9
  %161 = sub i32 %159, %160
  %162 = icmp ugt i32 %161, 0
  br i1 %162, label %163, label %173

163:                                              ; preds = %158
  %164 = load ptr, ptr %9, align 8, !tbaa !5
  %165 = load i32, ptr %10, align 4, !tbaa !9
  %166 = load i32, ptr %11, align 4, !tbaa !9
  %167 = load i32, ptr %10, align 4, !tbaa !9
  %168 = load i32, ptr %16, align 4, !tbaa !9
  %169 = zext i32 %168 to i64
  %170 = load i32, ptr %22, align 4, !tbaa !9
  %171 = zext i32 %170 to i64
  %172 = sub nsw i64 %169, %171
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %164, i32 noundef 4096, i32 noundef %165, i32 noundef %166, i32 noundef %167, i64 noundef %172)
  br label %173

173:                                              ; preds = %163, %158
  br label %174

174:                                              ; preds = %173
  %175 = load i32, ptr %18, align 4, !tbaa !9
  %176 = add i32 %175, 1
  store i32 %176, ptr %18, align 4, !tbaa !9
  br label %90, !llvm.loop !14

177:                                              ; preds = %90
  %178 = load ptr, ptr %9, align 8, !tbaa !5
  %179 = load i32, ptr %10, align 4, !tbaa !9
  %180 = load i32, ptr %11, align 4, !tbaa !9
  %181 = load i32, ptr %10, align 4, !tbaa !9
  %182 = load i32, ptr %16, align 4, !tbaa !9
  %183 = zext i32 %182 to i64
  %184 = load i32, ptr %15, align 4, !tbaa !9
  %185 = zext i32 %184 to i64
  %186 = mul nsw i64 %183, %185
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %178, i32 noundef 4097, i32 noundef %179, i32 noundef %180, i32 noundef %181, i64 noundef %186)
  call void @llvm.lifetime.end.p0(i64 4, ptr %24) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #3
  call void @llvm.lifetime.end.p0(i64 12, ptr %20) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #3
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.libxsmm_generator_store_2dregblock_aarch64_asimd = private unnamed_addr constant [4 x i32] [i32 201355264, i32 201367552, i32 201351168, i32 201334784], align 4

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_store_2dregblock_aarch64_asimd(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #1 {
  %9 = udiv i32 %5, %3
  %10 = urem i32 %5, %3
  %11 = lshr i32 %3, 1
  %12 = udiv i32 %10, %11
  %13 = urem i32 %10, %11
  %14 = add i32 %12, %9
  %15 = add i32 %14, %13
  %16 = shl i32 %9, 4
  %17 = shl i32 %12, 3
  %18 = add i32 %17, %16
  %19 = shl i32 %13, 2
  %20 = add i32 %18, %19
  %21 = mul i32 %15, %6
  %22 = sub i32 %4, %21
  %switch.tableidx = add i32 %9, -1
  %23 = icmp ult i32 %switch.tableidx, 4
  br i1 %23, label %switch.lookup, label %.fold.split

switch.lookup:                                    ; preds = %8
  %24 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [4 x i32], ptr @switch.table.libxsmm_generator_store_2dregblock_aarch64_asimd, i64 0, i64 %24
  %switch.load = load i32, ptr %switch.gep, align 4
  %switch.idx.mult = shl nuw nsw i32 %switch.tableidx, 4
  %switch.offset = add nuw nsw i32 %switch.idx.mult, 16
  br label %.fold.split

.fold.split:                                      ; preds = %8, %switch.lookup
  %.066 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %8 ]
  %.0 = phi i32 [ %switch.offset, %switch.lookup ], [ 0, %8 ]
  %.not95 = icmp eq i32 %6, 0
  br i1 %.not95, label %.._crit_edge79_crit_edge, label %.lr.ph78

.._crit_edge79_crit_edge:                         ; preds = %.fold.split
  %.pre = zext i32 %7 to i64
  br label %._crit_edge79

.lr.ph78:                                         ; preds = %.fold.split
  %.not = icmp ugt i32 %3, %5
  %.not96 = icmp ugt i32 %11, %10
  %25 = add i32 %22, %9
  %.not97 = icmp eq i32 %13, 0
  %26 = add i32 %14, %22
  %.not72 = icmp eq i32 %20, %7
  %27 = zext i32 %7 to i64
  %28 = zext i32 %20 to i64
  %29 = sub nsw i64 %27, %28
  br i1 %.not, label %.lr.ph78.split.us, label %.lr.ph78.split

.lr.ph78.split.us:                                ; preds = %.lr.ph78, %31
  %.06776.us = phi i32 [ %32, %31 ], [ 0, %.lr.ph78 ]
  br i1 %.not96, label %.preheader.us, label %.lr.ph.us

._crit_edge.us:                                   ; preds = %33, %.preheader.us
  br i1 %.not72, label %31, label %30

30:                                               ; preds = %._crit_edge.us
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef %2, i32 noundef %1, i64 noundef %29) #2
  br label %31

31:                                               ; preds = %30, %._crit_edge.us
  %32 = add nuw i32 %.06776.us, 1
  %exitcond105.not = icmp eq i32 %32, %6
  br i1 %exitcond105.not, label %._crit_edge79, label %.lr.ph78.split.us, !llvm.loop !5

33:                                               ; preds = %.lr.ph75.us, %33
  %.174.us = phi i32 [ 0, %.lr.ph75.us ], [ %35, %33 ]
  %34 = add i32 %44, %.174.us
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %1, i32 noundef 127, i32 noundef 4, i32 noundef %34, i32 noundef 4) #2
  %35 = add nuw nsw i32 %.174.us, 1
  %36 = icmp ult i32 %35, %13
  br i1 %36, label %33, label %._crit_edge.us, !llvm.loop !7

37:                                               ; preds = %.lr.ph.us, %37
  %.06873.us = phi i32 [ 0, %.lr.ph.us ], [ %39, %37 ]
  %38 = add i32 %42, %.06873.us
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %1, i32 noundef 127, i32 noundef 8, i32 noundef %38, i32 noundef 6) #2
  %39 = add nuw i32 %.06873.us, 1
  %40 = icmp ult i32 %39, %12
  br i1 %40, label %37, label %.preheader.us, !llvm.loop !8

.preheader.us:                                    ; preds = %37, %.lr.ph78.split.us
  br i1 %.not97, label %._crit_edge.us, label %.lr.ph75.us

.lr.ph.us:                                        ; preds = %.lr.ph78.split.us
  %41 = mul i32 %.06776.us, %15
  %42 = add i32 %25, %41
  br label %37

.lr.ph75.us:                                      ; preds = %.preheader.us
  %43 = mul i32 %.06776.us, %15
  %44 = add i32 %26, %43
  br label %33

.lr.ph78.split:                                   ; preds = %.lr.ph78
  br i1 %.not96, label %.lr.ph78.split.split, label %.lr.ph.us84

.lr.ph.us84:                                      ; preds = %.lr.ph78.split, %49
  %.06776.us80 = phi i32 [ %50, %49 ], [ 0, %.lr.ph78.split ]
  %45 = mul i32 %.06776.us80, %15
  %46 = add i32 %45, %22
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef %.066, i32 noundef %1, i32 noundef 127, i32 noundef %46, i32 noundef 5) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %1, i32 noundef %1, i32 noundef %.0, i8 noundef zeroext 0) #2
  %47 = add i32 %25, %45
  br label %55

._crit_edge.us87:                                 ; preds = %51, %..preheader_crit_edge.us85
  br i1 %.not72, label %49, label %48

48:                                               ; preds = %._crit_edge.us87
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef %2, i32 noundef %1, i64 noundef %29) #2
  br label %49

49:                                               ; preds = %48, %._crit_edge.us87
  %50 = add nuw i32 %.06776.us80, 1
  %exitcond.not = icmp eq i32 %50, %6
  br i1 %exitcond.not, label %._crit_edge79, label %.lr.ph.us84, !llvm.loop !5

51:                                               ; preds = %.lr.ph75.us86, %51
  %.174.us81 = phi i32 [ 0, %.lr.ph75.us86 ], [ %53, %51 ]
  %52 = add i32 %59, %.174.us81
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %1, i32 noundef 127, i32 noundef 4, i32 noundef %52, i32 noundef 4) #2
  %53 = add nuw nsw i32 %.174.us81, 1
  %54 = icmp ult i32 %53, %13
  br i1 %54, label %51, label %._crit_edge.us87, !llvm.loop !7

55:                                               ; preds = %.lr.ph.us84, %55
  %.06873.us82 = phi i32 [ 0, %.lr.ph.us84 ], [ %57, %55 ]
  %56 = add i32 %47, %.06873.us82
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %1, i32 noundef 127, i32 noundef 8, i32 noundef %56, i32 noundef 6) #2
  %57 = add nuw i32 %.06873.us82, 1
  %58 = icmp ult i32 %57, %12
  br i1 %58, label %55, label %..preheader_crit_edge.us85, !llvm.loop !8

..preheader_crit_edge.us85:                       ; preds = %55
  br i1 %.not97, label %._crit_edge.us87, label %.lr.ph75.us86

.lr.ph75.us86:                                    ; preds = %..preheader_crit_edge.us85
  %59 = add i32 %26, %45
  br label %51

.lr.ph78.split.split:                             ; preds = %.lr.ph78.split
  br i1 %.not97, label %.lr.ph78.split.split.split, label %.preheader.us88

.preheader.us88:                                  ; preds = %.lr.ph78.split.split, %64
  %.06776.us89 = phi i32 [ %65, %64 ], [ 0, %.lr.ph78.split.split ]
  %60 = mul i32 %.06776.us89, %15
  %61 = add i32 %60, %22
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef %.066, i32 noundef %1, i32 noundef 127, i32 noundef %61, i32 noundef 5) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %1, i32 noundef %1, i32 noundef %.0, i8 noundef zeroext 0) #2
  %62 = add i32 %26, %60
  br label %66

63:                                               ; preds = %._crit_edge.us92
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef %2, i32 noundef %1, i64 noundef %29) #2
  br label %64

64:                                               ; preds = %63, %._crit_edge.us92
  %65 = add nuw i32 %.06776.us89, 1
  %exitcond102.not = icmp eq i32 %65, %6
  br i1 %exitcond102.not, label %._crit_edge79, label %.preheader.us88, !llvm.loop !5

66:                                               ; preds = %.preheader.us88, %66
  %.174.us90 = phi i32 [ 0, %.preheader.us88 ], [ %68, %66 ]
  %67 = add i32 %62, %.174.us90
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %1, i32 noundef 127, i32 noundef 4, i32 noundef %67, i32 noundef 4) #2
  %68 = add nuw nsw i32 %.174.us90, 1
  %69 = icmp ult i32 %68, %13
  br i1 %69, label %66, label %._crit_edge.us92, !llvm.loop !7

._crit_edge.us92:                                 ; preds = %66
  br i1 %.not72, label %64, label %63

.lr.ph78.split.split.split:                       ; preds = %.lr.ph78.split.split
  br i1 %.not72, label %.preheader.us93, label %.preheader

.preheader.us93:                                  ; preds = %.lr.ph78.split.split.split, %.preheader.us93
  %.06776.us94 = phi i32 [ %72, %.preheader.us93 ], [ 0, %.lr.ph78.split.split.split ]
  %70 = mul i32 %.06776.us94, %15
  %71 = add i32 %70, %22
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef %.066, i32 noundef %1, i32 noundef 127, i32 noundef %71, i32 noundef 5) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %1, i32 noundef %1, i32 noundef %.0, i8 noundef zeroext 0) #2
  %72 = add nuw i32 %.06776.us94, 1
  %exitcond104.not = icmp eq i32 %72, %6
  br i1 %exitcond104.not, label %._crit_edge79, label %.preheader.us93, !llvm.loop !5

.preheader:                                       ; preds = %.lr.ph78.split.split.split, %.preheader
  %.06776 = phi i32 [ %75, %.preheader ], [ 0, %.lr.ph78.split.split.split ]
  %73 = mul i32 %.06776, %15
  %74 = add i32 %73, %22
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef %.066, i32 noundef %1, i32 noundef 127, i32 noundef %74, i32 noundef 5) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %1, i32 noundef %1, i32 noundef %.0, i8 noundef zeroext 0) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef %2, i32 noundef %1, i64 noundef %29) #2
  %75 = add nuw i32 %.06776, 1
  %exitcond103.not = icmp eq i32 %75, %6
  br i1 %exitcond103.not, label %._crit_edge79, label %.preheader, !llvm.loop !5

._crit_edge79:                                    ; preds = %49, %64, %.preheader, %.preheader.us93, %31, %.._crit_edge79_crit_edge
  %.pre-phi = phi i64 [ %.pre, %.._crit_edge79_crit_edge ], [ %27, %31 ], [ %27, %.preheader.us93 ], [ %27, %.preheader ], [ %27, %64 ], [ %27, %49 ]
  %76 = zext i32 %6 to i64
  %77 = mul nuw nsw i64 %.pre-phi, %76
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4097, i32 noundef %1, i32 noundef %2, i32 noundef %1, i64 noundef %77) #2
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass