; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetMergedConvolution16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"class.Simd::Base::SynetMergedConvolution16b" = type { %"class.Simd::SynetMergedConvolution16b", %"struct.Simd::MergConvParam", %"class.std::__cxx11::basic_string", i8, i8, i8, ptr, ptr, ptr, ptr, [2 x ptr], i64, i64, [4 x i64], %"struct.Simd::Base::SynetMergedConvolution16b::AlgParam", %"struct.Simd::Array", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.1", [3 x %"struct.Simd::Array.1"], [3 x %"struct.Simd::Array.1"] }
%"class.Simd::SynetMergedConvolution16b" = type { %"struct.Simd::Deletable" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::MergConvParam" = type <{ [3 x %"struct.Simd::ConvParam"], i64, i32, [4 x i8] }>
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.Simd::Base::SynetMergedConvolution16b::AlgParam" = type { i64, i64, i64, [3 x i64], [3 x i64], [3 x i64], [2 x i64], [3 x i64], [2 x i64] }
%"struct.Simd::Array" = type { ptr, i64 }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Array.1" = type { ptr, i64 }

@.str.1 = external hidden unnamed_addr constant [95 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [13 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE = external hidden unnamed_addr constant [93 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [9 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(1024) %0, ptr noundef %1, ptr noundef nonnull align 8 dereferenceable(180) %2) #3 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  %13 = alloca i64, align 8
  %14 = alloca ptr, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %4, align 8
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %18, i32 0, i32 20
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = icmp eq i64 %20, 1
  br i1 %21, label %22, label %23

22:                                               ; preds = %3
  br label %25

23:                                               ; preds = %3
  call void @__assert_fail(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 420, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE) #6
  unreachable

24:                                               ; No predecessors!
  br label %25

25:                                               ; preds = %24, %22
  %26 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 14
  %27 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution16b::AlgParam", ptr %26, i32 0, i32 0
  %28 = load i64, ptr %27, align 8, !tbaa !15
  %29 = icmp ne i64 %28, 0
  br i1 %29, label %30, label %153

30:                                               ; preds = %25
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = call noundef zeroext i1 @_ZN4Simd5Is1x1ERK25SimdConvolutionParameters(ptr noundef nonnull align 8 dereferenceable(160) %31)
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  br label %36

34:                                               ; preds = %30
  call void @__assert_fail(ptr noundef @.str.3, ptr noundef @.str.1, i32 noundef 423, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE) #6
  unreachable

35:                                               ; No predecessors!
  br label %36

36:                                               ; preds = %35, %33
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #7
  %37 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 14
  %38 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution16b::AlgParam", ptr %37, i32 0, i32 0
  %39 = load i64, ptr %38, align 8, !tbaa !15
  store i64 %39, ptr %7, align 8, !tbaa !28
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #7
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %40, i32 0, i32 0
  %42 = load i64, ptr %41, align 8, !tbaa !29
  %43 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 14
  %44 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution16b::AlgParam", ptr %43, i32 0, i32 2
  %45 = load i64, ptr %44, align 8, !tbaa !30
  %46 = call noundef i64 @_ZN4Simd7AlignHiEmm(i64 noundef %42, i64 noundef %45)
  store i64 %46, ptr %8, align 8, !tbaa !28
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #7
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %47, i32 0, i32 5
  %49 = load i64, ptr %48, align 8, !tbaa !31
  %50 = load i64, ptr %7, align 8, !tbaa !28
  %51 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %49, i64 noundef %50)
  store i64 %51, ptr %9, align 8, !tbaa !28
  %52 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 16
  %53 = load i64, ptr %8, align 8, !tbaa !28
  %54 = load i64, ptr %9, align 8, !tbaa !28
  %55 = mul i64 %53, %54
  %56 = load i64, ptr %7, align 8, !tbaa !28
  %57 = mul i64 %55, %56
  call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %52, i64 noundef %57, i1 noundef zeroext true, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #7
  %58 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 16
  %59 = getelementptr inbounds %"struct.Simd::Array.0", ptr %58, i32 0, i32 0
  %60 = load ptr, ptr %59, align 8, !tbaa !32
  store ptr %60, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #7
  store i64 0, ptr %11, align 8, !tbaa !28
  br label %61

61:                                               ; preds = %149, %36
  %62 = load i64, ptr %11, align 8, !tbaa !28
  %63 = load i64, ptr %9, align 8, !tbaa !28
  %64 = icmp ult i64 %62, %63
  br i1 %64, label %66, label %65

65:                                               ; preds = %61
  store i32 2, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #7
  br label %152

66:                                               ; preds = %61
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #7
  store i64 0, ptr %13, align 8, !tbaa !28
  br label %67

67:                                               ; preds = %145, %66
  %68 = load i64, ptr %13, align 8, !tbaa !28
  %69 = load i64, ptr %8, align 8, !tbaa !28
  %70 = icmp ult i64 %68, %69
  br i1 %70, label %72, label %71

71:                                               ; preds = %67
  store i32 5, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #7
  br label %148

72:                                               ; preds = %67
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #7
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = load i64, ptr %13, align 8, !tbaa !28
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %75, i32 0, i32 5
  %77 = load i64, ptr %76, align 8, !tbaa !31
  %78 = mul i64 %74, %77
  %79 = getelementptr inbounds float, ptr %73, i64 %78
  %80 = load i64, ptr %11, align 8, !tbaa !28
  %81 = load i64, ptr %7, align 8, !tbaa !28
  %82 = mul i64 %80, %81
  %83 = getelementptr inbounds float, ptr %79, i64 %82
  store ptr %83, ptr %14, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #7
  store i64 0, ptr %15, align 8, !tbaa !28
  br label %84

84:                                               ; preds = %141, %72
  %85 = load i64, ptr %15, align 8, !tbaa !28
  %86 = load i64, ptr %7, align 8, !tbaa !28
  %87 = icmp ult i64 %85, %86
  br i1 %87, label %89, label %88

88:                                               ; preds = %84
  store i32 8, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #7
  br label %144

89:                                               ; preds = %84
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #7
  store i64 0, ptr %16, align 8, !tbaa !28
  br label %90

90:                                               ; preds = %128, %89
  %91 = load i64, ptr %16, align 8, !tbaa !28
  %92 = icmp ult i64 %91, 2
  br i1 %92, label %94, label %93

93:                                               ; preds = %90
  store i32 11, ptr %12, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #7
  br label %131

94:                                               ; preds = %90
  %95 = load i64, ptr %11, align 8, !tbaa !28
  %96 = load i64, ptr %7, align 8, !tbaa !28
  %97 = mul i64 %95, %96
  %98 = load i64, ptr %15, align 8, !tbaa !28
  %99 = add i64 %97, %98
  %100 = load ptr, ptr %6, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %100, i32 0, i32 5
  %102 = load i64, ptr %101, align 8, !tbaa !31
  %103 = icmp ult i64 %99, %102
  br i1 %103, label %104, label %124

104:                                              ; preds = %94
  %105 = load i64, ptr %13, align 8, !tbaa !28
  %106 = load i64, ptr %16, align 8, !tbaa !28
  %107 = add i64 %105, %106
  %108 = load ptr, ptr %6, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %108, i32 0, i32 0
  %110 = load i64, ptr %109, align 8, !tbaa !29
  %111 = icmp ult i64 %107, %110
  br i1 %111, label %112, label %124

112:                                              ; preds = %104
  %113 = load ptr, ptr %14, align 8, !tbaa !5
  %114 = load i64, ptr %16, align 8, !tbaa !28
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %115, i32 0, i32 5
  %117 = load i64, ptr %116, align 8, !tbaa !31
  %118 = mul i64 %114, %117
  %119 = getelementptr inbounds float, ptr %113, i64 %118
  %120 = load float, ptr %119, align 4, !tbaa !33
  %121 = call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %120)
  %122 = load ptr, ptr %10, align 8, !tbaa !5
  %123 = getelementptr inbounds i16, ptr %122, i32 1
  store ptr %123, ptr %10, align 8, !tbaa !5
  store i16 %121, ptr %122, align 2, !tbaa !35
  br label %127

124:                                              ; preds = %104, %94
  %125 = load ptr, ptr %10, align 8, !tbaa !5
  %126 = getelementptr inbounds i16, ptr %125, i32 1
  store ptr %126, ptr %10, align 8, !tbaa !5
  store i16 0, ptr %125, align 2, !tbaa !35
  br label %127

127:                                              ; preds = %124, %112
  br label %128

128:                                              ; preds = %127
  %129 = load i64, ptr %16, align 8, !tbaa !28
  %130 = add i64 %129, 1
  store i64 %130, ptr %16, align 8, !tbaa !28
  br label %90, !llvm.loop !37

131:                                              ; preds = %93
  %132 = load i64, ptr %13, align 8, !tbaa !28
  %133 = load ptr, ptr %6, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %133, i32 0, i32 0
  %135 = load i64, ptr %134, align 8, !tbaa !29
  %136 = icmp ult i64 %132, %135
  br i1 %136, label %137, label %140

137:                                              ; preds = %131
  %138 = load ptr, ptr %14, align 8, !tbaa !5
  %139 = getelementptr inbounds float, ptr %138, i32 1
  store ptr %139, ptr %14, align 8, !tbaa !5
  br label %140

140:                                              ; preds = %137, %131
  br label %141

141:                                              ; preds = %140
  %142 = load i64, ptr %15, align 8, !tbaa !28
  %143 = add i64 %142, 1
  store i64 %143, ptr %15, align 8, !tbaa !28
  br label %84, !llvm.loop !39

144:                                              ; preds = %88
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #7
  br label %145

145:                                              ; preds = %144
  %146 = load i64, ptr %13, align 8, !tbaa !28
  %147 = add i64 %146, 2
  store i64 %147, ptr %13, align 8, !tbaa !28
  br label %67, !llvm.loop !40

148:                                              ; preds = %71
  br label %149

149:                                              ; preds = %148
  %150 = load i64, ptr %11, align 8, !tbaa !28
  %151 = add i64 %150, 1
  store i64 %151, ptr %11, align 8, !tbaa !28
  br label %61, !llvm.loop !41

152:                                              ; preds = %65
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #7
  br label %177

153:                                              ; preds = %25
  %154 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 16
  %155 = load ptr, ptr %6, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %155, i32 0, i32 10
  %157 = load i64, ptr %156, align 8, !tbaa !42
  %158 = load ptr, ptr %6, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %158, i32 0, i32 11
  %160 = load i64, ptr %159, align 8, !tbaa !43
  %161 = mul i64 %157, %160
  %162 = load ptr, ptr %6, align 8, !tbaa !5
  %163 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %162, i32 0, i32 0
  %164 = load i64, ptr %163, align 8, !tbaa !29
  %165 = mul i64 %161, %164
  %166 = load ptr, ptr %6, align 8, !tbaa !5
  %167 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %166, i32 0, i32 5
  %168 = load i64, ptr %167, align 8, !tbaa !31
  %169 = mul i64 %165, %168
  call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %154, i64 noundef %169, i1 noundef zeroext true, i64 noundef 8)
  %170 = load ptr, ptr %5, align 8, !tbaa !5
  %171 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 16
  %172 = getelementptr inbounds %"struct.Simd::Array.0", ptr %171, i32 0, i32 1
  %173 = load i64, ptr %172, align 8, !tbaa !44
  %174 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution16b", ptr %17, i32 0, i32 16
  %175 = getelementptr inbounds %"struct.Simd::Array.0", ptr %174, i32 0, i32 0
  %176 = load ptr, ptr %175, align 8, !tbaa !32
  call void @_ZN4Simd4Base17Float32ToBFloat16EPKfmPt(ptr noundef %170, i64 noundef %173, ptr noundef %176)
  br label %177

177:                                              ; preds = %153, %152
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd5Is1x1ERK25SimdConvolutionParameters(ptr noundef nonnull align 8 dereferenceable(160)) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd7AlignHiEmm(i64 noundef, i64 noundef) #4

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) #4

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #1 align 2

declare void @_ZN4Simd4Base17Float32ToBFloat16EPKfmPt(ptr noundef, i64 noundef, ptr noundef) #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 144}
!10 = !{!"_ZTS25SimdConvolutionParameters", !11, i64 0, !11, i64 8, !11, i64 16, !12, i64 24, !13, i64 28, !11, i64 32, !11, i64 40, !11, i64 48, !12, i64 56, !13, i64 60, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !14, i64 152}
!11 = !{!"long", !7, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!13 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!14 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!15 = !{!16, !11, i64 712}
!16 = !{!"_ZTSN4Simd4Base25SynetMergedConvolution16bE", !17, i64 0, !19, i64 8, !21, i64 576, !23, i64 608, !23, i64 609, !23, i64 610, !6, i64 616, !6, i64 624, !6, i64 632, !6, i64 640, !7, i64 648, !11, i64 664, !11, i64 672, !7, i64 680, !24, i64 712, !25, i64 864, !26, i64 880, !26, i64 896, !27, i64 912, !7, i64 928, !7, i64 976}
!17 = !{!"_ZTSN4Simd25SynetMergedConvolution16bE", !18, i64 0}
!18 = !{!"_ZTSN4Simd9DeletableE"}
!19 = !{!"_ZTSN4Simd13MergConvParamE", !7, i64 0, !11, i64 552, !20, i64 560}
!20 = !{!"_ZTS8SimdBool", !7, i64 0}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !22, i64 0, !11, i64 8, !7, i64 16}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!23 = !{!"bool", !7, i64 0}
!24 = !{!"_ZTSN4Simd4Base25SynetMergedConvolution16b8AlgParamE", !11, i64 0, !11, i64 8, !11, i64 16, !7, i64 24, !7, i64 48, !7, i64 72, !7, i64 96, !7, i64 112, !7, i64 136}
!25 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !11, i64 8}
!26 = !{!"_ZTSN4Simd5ArrayItEE", !6, i64 0, !11, i64 8}
!27 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !11, i64 8}
!28 = !{!11, !11, i64 0}
!29 = !{!10, !11, i64 0}
!30 = !{!16, !11, i64 728}
!31 = !{!10, !11, i64 32}
!32 = !{!16, !6, i64 880}
!33 = !{!34, !34, i64 0}
!34 = !{!"float", !7, i64 0}
!35 = !{!36, !36, i64 0}
!36 = !{!"short", !7, i64 0}
!37 = distinct !{!37, !38}
!38 = !{!"llvm.loop.mustprogress"}
!39 = distinct !{!39, !38}
!40 = distinct !{!40, !38}
!41 = distinct !{!41, !38}
!42 = !{!10, !11, i64 64}
!43 = !{!10, !11, i64 72}
!44 = !{!16, !11, i64 888}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [95 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [13 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE = external hidden unnamed_addr constant [93 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [9 x i8], align 1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) local_unnamed_addr #0

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(1024) %0, ptr noundef %1, ptr noundef nonnull align 8 dereferenceable(180) %2) local_unnamed_addr #2 align 2 {
  %4 = getelementptr inbounds i8, ptr %2, i64 144
  %5 = load i64, ptr %4, align 8, !tbaa !5
  %6 = icmp eq i64 %5, 1
  br i1 %6, label %8, label %7

7:                                                ; preds = %3
  tail call void @__assert_fail(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 420, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE) #5
  unreachable

8:                                                ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 712
  %10 = load i64, ptr %9, align 8, !tbaa !13
  %.not = icmp eq i64 %10, 0
  br i1 %.not, label %54, label %11

11:                                               ; preds = %8
  %12 = tail call noundef zeroext i1 @_ZN4Simd5Is1x1ERK25SimdConvolutionParameters(ptr noundef nonnull align 8 dereferenceable(160) %2)
  br i1 %12, label %14, label %13

13:                                               ; preds = %11
  tail call void @__assert_fail(ptr noundef nonnull @.str.3, ptr noundef nonnull @.str.1, i32 noundef 423, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base25SynetMergedConvolution16b14SetInputWeightEPKfRKNS_9ConvParamE) #5
  unreachable

14:                                               ; preds = %11
  %15 = load i64, ptr %9, align 8, !tbaa !13
  %16 = load i64, ptr %2, align 8, !tbaa !27
  %17 = getelementptr inbounds i8, ptr %0, i64 728
  %18 = load i64, ptr %17, align 8, !tbaa !28
  %19 = tail call noundef i64 @_ZN4Simd7AlignHiEmm(i64 noundef %16, i64 noundef %18)
  %20 = getelementptr inbounds i8, ptr %2, i64 32
  %21 = load i64, ptr %20, align 8, !tbaa !29
  %22 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %21, i64 noundef %15)
  %23 = getelementptr inbounds i8, ptr %0, i64 880
  %24 = mul i64 %19, %15
  %25 = mul i64 %24, %22
  tail call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %23, i64 noundef %25, i1 noundef zeroext true, i64 noundef 8)
  %.not73 = icmp eq i64 %22, 0
  %.not74 = icmp eq i64 %19, 0
  %or.cond = or i1 %.not73, %.not74
  %.not75 = icmp eq i64 %15, 0
  %or.cond80 = select i1 %or.cond, i1 true, i1 %.not75
  br i1 %or.cond80, label %.loopexit, label %.preheader51.us.us.preheader

.preheader51.us.us.preheader:                     ; preds = %14
  %26 = load ptr, ptr %23, align 8, !tbaa !30
  br label %.preheader51.us.us

.preheader51.us.us:                               ; preds = %.preheader51.us.us.preheader, %._crit_edge59.split.us.us.us
  %.04769.us.us = phi i64 [ %53, %._crit_edge59.split.us.us.us ], [ 0, %.preheader51.us.us.preheader ]
  %.04868.us.us = phi ptr [ %.us-phi.us.us.us, %._crit_edge59.split.us.us.us ], [ %26, %.preheader51.us.us.preheader ]
  %27 = mul i64 %.04769.us.us, %15
  %invariant.gep.us.us = getelementptr float, ptr %1, i64 %27
  br label %.preheader.lr.ph.us.us.us

.preheader.lr.ph.us.us.us:                        ; preds = %._crit_edge.us.us.us, %.preheader51.us.us
  %.04658.us.us.us = phi i64 [ 0, %.preheader51.us.us ], [ %51, %._crit_edge.us.us.us ]
  %.14957.us.us.us = phi ptr [ %.04868.us.us, %.preheader51.us.us ], [ %.us-phi.us.us.us, %._crit_edge.us.us.us ]
  %28 = load i64, ptr %20, align 8, !tbaa !29
  %29 = mul i64 %28, %.04658.us.us.us
  %gep.us.us.us = getelementptr float, ptr %invariant.gep.us.us, i64 %29
  %30 = or disjoint i64 %.04658.us.us.us, 1
  br label %.preheader.us.us.us

31:                                               ; preds = %.preheader.us.us.us
  %32 = load i64, ptr %2, align 8, !tbaa !27
  %33 = icmp ult i64 %.04658.us.us.us, %32
  br i1 %33, label %34, label %.preheader.split.us66.us.us.1

34:                                               ; preds = %31
  %35 = load float, ptr %.04555.us.us.us, align 4, !tbaa !31
  %36 = tail call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %35)
  %.pre = load i64, ptr %20, align 8, !tbaa !29
  br label %.preheader.split.us66.us.us.1

.preheader.split.us66.us.us.1:                    ; preds = %34, %31
  %37 = phi i64 [ %.pre, %34 ], [ %46, %31 ]
  %storemerge.us.us.us = phi i16 [ %36, %34 ], [ 0, %31 ]
  %.4.us65.us.us = getelementptr inbounds i8, ptr %.254.us.us.us, i64 2
  store i16 %storemerge.us.us.us, ptr %.254.us.us.us, align 2, !tbaa !33
  %38 = icmp ult i64 %45, %37
  %39 = load i64, ptr %2, align 8
  %40 = icmp ult i64 %30, %39
  %or.cond82 = select i1 %38, i1 %40, i1 false
  br i1 %or.cond82, label %41, label %.split.us61.us.us.loopexit

41:                                               ; preds = %.preheader.split.us66.us.us.1
  %42 = getelementptr inbounds float, ptr %.04555.us.us.us, i64 %37
  %43 = load float, ptr %42, align 4, !tbaa !31
  %44 = tail call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %43)
  br label %.split.us61.us.us.loopexit

.split.us61.us.us.loopexit:                       ; preds = %41, %.preheader.split.us66.us.us.1
  %storemerge.us.us.us.1 = phi i16 [ %44, %41 ], [ 0, %.preheader.split.us66.us.us.1 ]
  store i16 %storemerge.us.us.us.1, ptr %.4.us65.us.us, align 2, !tbaa !33
  br label %.split.us61.us.us

.preheader.us.us.us:                              ; preds = %.split.us61.us.us, %.preheader.lr.ph.us.us.us
  %.04456.us.us.us = phi i64 [ 0, %.preheader.lr.ph.us.us.us ], [ %50, %.split.us61.us.us ]
  %.04555.us.us.us = phi ptr [ %gep.us.us.us, %.preheader.lr.ph.us.us.us ], [ %spec.select.us.us.us, %.split.us61.us.us ]
  %.254.us.us.us = phi ptr [ %.14957.us.us.us, %.preheader.lr.ph.us.us.us ], [ %.us-phi.us.us.us, %.split.us61.us.us ]
  %45 = add i64 %.04456.us.us.us, %27
  %46 = load i64, ptr %20, align 8, !tbaa !29
  %47 = icmp ult i64 %45, %46
  br i1 %47, label %31, label %.preheader.split.us.us.us.us.preheader

.preheader.split.us.us.us.us.preheader:           ; preds = %.preheader.us.us.us
  store i32 0, ptr %.254.us.us.us, align 2
  br label %.split.us61.us.us

.split.us61.us.us:                                ; preds = %.preheader.split.us.us.us.us.preheader, %.split.us61.us.us.loopexit
  %.us-phi.us.us.us = getelementptr i8, ptr %.254.us.us.us, i64 4
  %48 = load i64, ptr %2, align 8, !tbaa !27
  %49 = icmp ult i64 %.04658.us.us.us, %48
  %spec.select.idx.us.us.us = select i1 %49, i64 4, i64 0
  %spec.select.us.us.us = getelementptr inbounds i8, ptr %.04555.us.us.us, i64 %spec.select.idx.us.us.us
  %50 = add nuw i64 %.04456.us.us.us, 1
  %exitcond.not = icmp eq i64 %50, %15
  br i1 %exitcond.not, label %._crit_edge.us.us.us, label %.preheader.us.us.us, !llvm.loop !35

._crit_edge.us.us.us:                             ; preds = %.split.us61.us.us
  %51 = add i64 %.04658.us.us.us, 2
  %52 = icmp ult i64 %51, %19
  br i1 %52, label %.preheader.lr.ph.us.us.us, label %._crit_edge59.split.us.us.us, !llvm.loop !37

._crit_edge59.split.us.us.us:                     ; preds = %._crit_edge.us.us.us
  %53 = add nuw i64 %.04769.us.us, 1
  %exitcond79.not = icmp eq i64 %53, %22
  br i1 %exitcond79.not, label %.loopexit, label %.preheader51.us.us, !llvm.loop !38

54:                                               ; preds = %8
  %55 = getelementptr inbounds i8, ptr %0, i64 880
  %56 = getelementptr inbounds i8, ptr %2, i64 64
  %57 = load i64, ptr %56, align 8, !tbaa !39
  %58 = getelementptr inbounds i8, ptr %2, i64 72
  %59 = load i64, ptr %58, align 8, !tbaa !40
  %60 = mul i64 %59, %57
  %61 = load i64, ptr %2, align 8, !tbaa !27
  %62 = mul i64 %60, %61
  %63 = getelementptr inbounds i8, ptr %2, i64 32
  %64 = load i64, ptr %63, align 8, !tbaa !29
  %65 = mul i64 %62, %64
  tail call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %55, i64 noundef %65, i1 noundef zeroext true, i64 noundef 8)
  %66 = getelementptr inbounds i8, ptr %0, i64 888
  %67 = load i64, ptr %66, align 8, !tbaa !41
  %68 = load ptr, ptr %55, align 8, !tbaa !30
  tail call void @_ZN4Simd4Base17Float32ToBFloat16EPKfmPt(ptr noundef %1, i64 noundef %67, ptr noundef %68)
  br label %.loopexit

.loopexit:                                        ; preds = %._crit_edge59.split.us.us.us, %14, %54
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd5Is1x1ERK25SimdConvolutionParameters(ptr noundef nonnull align 8 dereferenceable(160)) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd7AlignHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #0 align 2

declare void @_ZN4Simd4Base17Float32ToBFloat16EPKfmPt(ptr noundef, i64 noundef, ptr noundef) local_unnamed_addr #4

attributes #0 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 144}
!6 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !10, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !12, i64 152}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!11 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!12 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!13 = !{!14, !7, i64 712}
!14 = !{!"_ZTSN4Simd4Base25SynetMergedConvolution16bE", !15, i64 0, !17, i64 8, !19, i64 576, !22, i64 608, !22, i64 609, !22, i64 610, !21, i64 616, !21, i64 624, !21, i64 632, !21, i64 640, !8, i64 648, !7, i64 664, !7, i64 672, !8, i64 680, !23, i64 712, !24, i64 864, !25, i64 880, !25, i64 896, !26, i64 912, !8, i64 928, !8, i64 976}
!15 = !{!"_ZTSN4Simd25SynetMergedConvolution16bE", !16, i64 0}
!16 = !{!"_ZTSN4Simd9DeletableE"}
!17 = !{!"_ZTSN4Simd13MergConvParamE", !8, i64 0, !7, i64 552, !18, i64 560}
!18 = !{!"_ZTS8SimdBool", !8, i64 0}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !7, i64 8, !8, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !21, i64 0}
!21 = !{!"any pointer", !8, i64 0}
!22 = !{!"bool", !8, i64 0}
!23 = !{!"_ZTSN4Simd4Base25SynetMergedConvolution16b8AlgParamE", !7, i64 0, !7, i64 8, !7, i64 16, !8, i64 24, !8, i64 48, !8, i64 72, !8, i64 96, !8, i64 112, !8, i64 136}
!24 = !{!"_ZTSN4Simd5ArrayIhEE", !21, i64 0, !7, i64 8}
!25 = !{!"_ZTSN4Simd5ArrayItEE", !21, i64 0, !7, i64 8}
!26 = !{!"_ZTSN4Simd5ArrayIfEE", !21, i64 0, !7, i64 8}
!27 = !{!6, !7, i64 0}
!28 = !{!14, !7, i64 728}
!29 = !{!6, !7, i64 32}
!30 = !{!14, !21, i64 880}
!31 = !{!32, !32, i64 0}
!32 = !{!"float", !8, i64 0}
!33 = !{!34, !34, i64 0}
!34 = !{!"short", !8, i64 0}
!35 = distinct !{!35, !36}
!36 = !{!"llvm.loop.mustprogress"}
!37 = distinct !{!37, !36}
!38 = distinct !{!38, !36}
!39 = !{!6, !7, i64 64}
!40 = !{!6, !7, i64 72}
!41 = !{!14, !7, i64 888}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopIdiomRecognizePass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass