; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_vex_mask_load_store.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_mask_load_store(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca [3 x i32], align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  store i32 2, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 12, ptr %13) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %13, ptr align 4 @__const.test_vex_mask_load_store.displ, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %16, ptr noundef %17)
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %79

20:                                               ; preds = %4
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %75, %20
  %22 = load i32, ptr %10, align 4, !tbaa !9
  %23 = icmp ult i32 %22, 16
  br i1 %23, label %24, label %78

24:                                               ; preds = %21
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %25

25:                                               ; preds = %71, %24
  %26 = load i32, ptr %14, align 4, !tbaa !9
  %27 = icmp ult i32 %26, 3
  br i1 %27, label %28, label %74

28:                                               ; preds = %25
  store i32 0, ptr %15, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %67, %28
  %30 = load i32, ptr %15, align 4, !tbaa !9
  %31 = icmp ult i32 %30, 16
  br i1 %31, label %32, label %70

32:                                               ; preds = %29
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %33

33:                                               ; preds = %46, %32
  %34 = load i32, ptr %9, align 4, !tbaa !9
  %35 = icmp ult i32 %34, 16
  br i1 %35, label %36, label %49

36:                                               ; preds = %33
  %37 = load ptr, ptr %6, align 8, !tbaa !5
  %38 = load i32, ptr %8, align 4, !tbaa !9
  %39 = load i32, ptr %10, align 4, !tbaa !9
  %40 = load i32, ptr %14, align 4, !tbaa !9
  %41 = zext i32 %40 to i64
  %42 = getelementptr inbounds [3 x i32], ptr %13, i64 0, i64 %41
  %43 = load i32, ptr %42, align 4, !tbaa !9
  %44 = load i32, ptr %9, align 4, !tbaa !9
  %45 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %37, i32 noundef %38, i32 noundef %39, i32 noundef 127, i32 noundef 0, i32 noundef %43, i8 noundef signext 121, i32 noundef %44, i32 noundef %45, i32 noundef 0)
  br label %46

46:                                               ; preds = %36
  %47 = load i32, ptr %9, align 4, !tbaa !9
  %48 = add i32 %47, 1
  store i32 %48, ptr %9, align 4, !tbaa !9
  br label %33, !llvm.loop !11

49:                                               ; preds = %33
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %50

50:                                               ; preds = %63, %49
  %51 = load i32, ptr %9, align 4, !tbaa !9
  %52 = icmp ult i32 %51, 16
  br i1 %52, label %53, label %66

53:                                               ; preds = %50
  %54 = load ptr, ptr %6, align 8, !tbaa !5
  %55 = load i32, ptr %8, align 4, !tbaa !9
  %56 = load i32, ptr %10, align 4, !tbaa !9
  %57 = load i32, ptr %14, align 4, !tbaa !9
  %58 = zext i32 %57 to i64
  %59 = getelementptr inbounds [3 x i32], ptr %13, i64 0, i64 %58
  %60 = load i32, ptr %59, align 4, !tbaa !9
  %61 = load i32, ptr %9, align 4, !tbaa !9
  %62 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %54, i32 noundef %55, i32 noundef %56, i32 noundef 127, i32 noundef 0, i32 noundef %60, i8 noundef signext 121, i32 noundef %61, i32 noundef %62, i32 noundef 1)
  br label %63

63:                                               ; preds = %53
  %64 = load i32, ptr %9, align 4, !tbaa !9
  %65 = add i32 %64, 1
  store i32 %65, ptr %9, align 4, !tbaa !9
  br label %50, !llvm.loop !13

66:                                               ; preds = %50
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %15, align 4, !tbaa !9
  %69 = add i32 %68, 1
  store i32 %69, ptr %15, align 4, !tbaa !9
  br label %29, !llvm.loop !14

70:                                               ; preds = %29
  br label %71

71:                                               ; preds = %70
  %72 = load i32, ptr %14, align 4, !tbaa !9
  %73 = add i32 %72, 1
  store i32 %73, ptr %14, align 4, !tbaa !9
  br label %25, !llvm.loop !15

74:                                               ; preds = %25
  br label %75

75:                                               ; preds = %74
  %76 = load i32, ptr %10, align 4, !tbaa !9
  %77 = add i32 %76, 1
  store i32 %77, ptr %10, align 4, !tbaa !9
  br label %21, !llvm.loop !16

78:                                               ; preds = %21
  br label %79

79:                                               ; preds = %78, %4
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %80

80:                                               ; preds = %167, %79
  %81 = load i32, ptr %10, align 4, !tbaa !9
  %82 = icmp ult i32 %81, 16
  br i1 %82, label %83, label %170

83:                                               ; preds = %80
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %84

84:                                               ; preds = %163, %83
  %85 = load i32, ptr %11, align 4, !tbaa !9
  %86 = icmp ult i32 %85, 16
  br i1 %86, label %87, label %166

87:                                               ; preds = %84
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %88

88:                                               ; preds = %159, %87
  %89 = load i32, ptr %14, align 4, !tbaa !9
  %90 = icmp ult i32 %89, 3
  br i1 %90, label %91, label %162

91:                                               ; preds = %88
  store i32 0, ptr %15, align 4, !tbaa !9
  br label %92

92:                                               ; preds = %155, %91
  %93 = load i32, ptr %15, align 4, !tbaa !9
  %94 = icmp ult i32 %93, 16
  br i1 %94, label %95, label %158

95:                                               ; preds = %92
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %96

96:                                               ; preds = %128, %95
  %97 = load i32, ptr %9, align 4, !tbaa !9
  %98 = icmp ult i32 %97, 16
  br i1 %98, label %99, label %131

99:                                               ; preds = %96
  %100 = load i32, ptr %7, align 4, !tbaa !9
  %101 = icmp ugt i32 %100, 0
  br i1 %101, label %102, label %115

102:                                              ; preds = %99
  %103 = load i32, ptr %9, align 4, !tbaa !9
  %104 = load i32, ptr %11, align 4, !tbaa !9
  %105 = icmp eq i32 %103, %104
  br i1 %105, label %114, label %106

106:                                              ; preds = %102
  %107 = load i32, ptr %9, align 4, !tbaa !9
  %108 = load i32, ptr %15, align 4, !tbaa !9
  %109 = icmp eq i32 %107, %108
  br i1 %109, label %114, label %110

110:                                              ; preds = %106
  %111 = load i32, ptr %11, align 4, !tbaa !9
  %112 = load i32, ptr %15, align 4, !tbaa !9
  %113 = icmp eq i32 %111, %112
  br i1 %113, label %114, label %115

114:                                              ; preds = %110, %106, %102
  br label %127

115:                                              ; preds = %110, %99
  %116 = load ptr, ptr %6, align 8, !tbaa !5
  %117 = load i32, ptr %8, align 4, !tbaa !9
  %118 = load i32, ptr %10, align 4, !tbaa !9
  %119 = load i32, ptr %11, align 4, !tbaa !9
  %120 = load i32, ptr %12, align 4, !tbaa !9
  %121 = load i32, ptr %14, align 4, !tbaa !9
  %122 = zext i32 %121 to i64
  %123 = getelementptr inbounds [3 x i32], ptr %13, i64 0, i64 %122
  %124 = load i32, ptr %123, align 4, !tbaa !9
  %125 = load i32, ptr %9, align 4, !tbaa !9
  %126 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %116, i32 noundef %117, i32 noundef %118, i32 noundef %119, i32 noundef %120, i32 noundef %124, i8 noundef signext 121, i32 noundef %125, i32 noundef %126, i32 noundef 0)
  br label %127

127:                                              ; preds = %115, %114
  br label %128

128:                                              ; preds = %127
  %129 = load i32, ptr %9, align 4, !tbaa !9
  %130 = add i32 %129, 1
  store i32 %130, ptr %9, align 4, !tbaa !9
  br label %96, !llvm.loop !17

131:                                              ; preds = %96
  %132 = load i32, ptr %7, align 4, !tbaa !9
  %133 = icmp eq i32 %132, 0
  br i1 %133, label %134, label %154

134:                                              ; preds = %131
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %135

135:                                              ; preds = %150, %134
  %136 = load i32, ptr %9, align 4, !tbaa !9
  %137 = icmp ult i32 %136, 16
  br i1 %137, label %138, label %153

138:                                              ; preds = %135
  %139 = load ptr, ptr %6, align 8, !tbaa !5
  %140 = load i32, ptr %8, align 4, !tbaa !9
  %141 = load i32, ptr %10, align 4, !tbaa !9
  %142 = load i32, ptr %11, align 4, !tbaa !9
  %143 = load i32, ptr %12, align 4, !tbaa !9
  %144 = load i32, ptr %14, align 4, !tbaa !9
  %145 = zext i32 %144 to i64
  %146 = getelementptr inbounds [3 x i32], ptr %13, i64 0, i64 %145
  %147 = load i32, ptr %146, align 4, !tbaa !9
  %148 = load i32, ptr %9, align 4, !tbaa !9
  %149 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %139, i32 noundef %140, i32 noundef %141, i32 noundef %142, i32 noundef %143, i32 noundef %147, i8 noundef signext 121, i32 noundef %148, i32 noundef %149, i32 noundef 1)
  br label %150

150:                                              ; preds = %138
  %151 = load i32, ptr %9, align 4, !tbaa !9
  %152 = add i32 %151, 1
  store i32 %152, ptr %9, align 4, !tbaa !9
  br label %135, !llvm.loop !18

153:                                              ; preds = %135
  br label %154

154:                                              ; preds = %153, %131
  br label %155

155:                                              ; preds = %154
  %156 = load i32, ptr %15, align 4, !tbaa !9
  %157 = add i32 %156, 1
  store i32 %157, ptr %15, align 4, !tbaa !9
  br label %92, !llvm.loop !19

158:                                              ; preds = %92
  br label %159

159:                                              ; preds = %158
  %160 = load i32, ptr %14, align 4, !tbaa !9
  %161 = add i32 %160, 1
  store i32 %161, ptr %14, align 4, !tbaa !9
  br label %88, !llvm.loop !20

162:                                              ; preds = %88
  br label %163

163:                                              ; preds = %162
  %164 = load i32, ptr %11, align 4, !tbaa !9
  %165 = add i32 %164, 1
  store i32 %165, ptr %11, align 4, !tbaa !9
  br label %84, !llvm.loop !21

166:                                              ; preds = %84
  br label %167

167:                                              ; preds = %166
  %168 = load i32, ptr %10, align 4, !tbaa !9
  %169 = add i32 %168, 1
  store i32 %169, ptr %10, align 4, !tbaa !9
  br label %80, !llvm.loop !22

170:                                              ; preds = %80
  %171 = load ptr, ptr %6, align 8, !tbaa !5
  %172 = load ptr, ptr %5, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %171, ptr noundef %172)
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  ret void
}

declare void @libxsmm_x86_instruction_vec_mask_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}
!20 = distinct !{!20, !12}
!21 = distinct !{!21, !12}
!22 = distinct !{!22, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_vex_mask_load_store.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_mask_load_store(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %5 = icmp eq i32 %2, 0
  br i1 %5, label %.preheader77, label %.preheader73

.preheader77:                                     ; preds = %4, %10
  %.06784 = phi i32 [ %11, %10 ], [ 0, %4 ]
  br label %.preheader76

.preheader76:                                     ; preds = %.preheader77, %9
  %indvars.iv = phi i64 [ 0, %.preheader77 ], [ %indvars.iv.next, %9 ]
  %6 = getelementptr inbounds [3 x i32], ptr @__const.test_vex_mask_load_store.displ, i64 0, i64 %indvars.iv
  %7 = load i32, ptr %6, align 4, !tbaa !5
  br label %.preheader75

.preheader75:                                     ; preds = %.preheader76, %.preheader75
  %.082 = phi i32 [ 0, %.preheader76 ], [ %8, %.preheader75 ]
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 0, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 1, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 2, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 3, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 4, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 5, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 6, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 7, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 8, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 9, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 10, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 11, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 12, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 13, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 14, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 15, i32 noundef %.082, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 0, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 1, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 2, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 3, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 4, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 5, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 6, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 7, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 8, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 9, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 10, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 11, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 12, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 13, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 14, i32 noundef %.082, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.06784, i32 noundef 127, i32 noundef 0, i32 noundef %7, i8 noundef signext 121, i32 noundef 15, i32 noundef %.082, i32 noundef 1) #2
  %8 = add nuw nsw i32 %.082, 1
  %exitcond.not = icmp eq i32 %8, 16
  br i1 %exitcond.not, label %9, label %.preheader75, !llvm.loop !9

9:                                                ; preds = %.preheader75
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond105.not = icmp eq i64 %indvars.iv.next, 3
  br i1 %exitcond105.not, label %10, label %.preheader76, !llvm.loop !11

10:                                               ; preds = %9
  %11 = add nuw nsw i32 %.06784, 1
  %exitcond106.not = icmp eq i32 %11, 16
  br i1 %exitcond106.not, label %.preheader73.us, label %.preheader77, !llvm.loop !12

.preheader73.us:                                  ; preds = %10, %.split97.us.us
  %.16898.us = phi i32 [ %16, %.split97.us.us ], [ 0, %10 ]
  br label %.preheader72.us.us

.preheader72.us.us:                               ; preds = %.split94.us.us.us, %.preheader73.us
  %.06695.us.us = phi i32 [ 0, %.preheader73.us ], [ %15, %.split94.us.us.us ]
  br label %.preheader71.us.us.us

.preheader71.us.us.us:                            ; preds = %.split91.us.us.us.us, %.preheader72.us.us
  %indvars.iv118 = phi i64 [ %indvars.iv.next119, %.split91.us.us.us.us ], [ 0, %.preheader72.us.us ]
  %12 = getelementptr inbounds [3 x i32], ptr @__const.test_vex_mask_load_store.displ, i64 0, i64 %indvars.iv118
  %13 = load i32, ptr %12, align 4, !tbaa !5
  br label %.preheader70.us.us.us.us

.preheader70.us.us.us.us:                         ; preds = %.preheader70.us.us.us.us, %.preheader71.us.us.us
  %.188.us.us.us.us = phi i32 [ 0, %.preheader71.us.us.us ], [ %14, %.preheader70.us.us.us.us ]
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 0, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 1, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 2, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 3, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 4, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 5, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 6, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 7, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 8, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 9, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 10, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 11, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 12, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 13, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 14, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 15, i32 noundef %.188.us.us.us.us, i32 noundef 0) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 0, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 1, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 2, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 3, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 4, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 5, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 6, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 7, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 8, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 9, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 10, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 11, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 12, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 13, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 14, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898.us, i32 noundef %.06695.us.us, i32 noundef 2, i32 noundef %13, i8 noundef signext 121, i32 noundef 15, i32 noundef %.188.us.us.us.us, i32 noundef 1) #2
  %14 = add nuw nsw i32 %.188.us.us.us.us, 1
  %exitcond117.not = icmp eq i32 %14, 16
  br i1 %exitcond117.not, label %.split91.us.us.us.us, label %.preheader70.us.us.us.us, !llvm.loop !13

.split91.us.us.us.us:                             ; preds = %.preheader70.us.us.us.us
  %indvars.iv.next119 = add nuw nsw i64 %indvars.iv118, 1
  %exitcond121.not = icmp eq i64 %indvars.iv.next119, 3
  br i1 %exitcond121.not, label %.split94.us.us.us, label %.preheader71.us.us.us, !llvm.loop !14

.split94.us.us.us:                                ; preds = %.split91.us.us.us.us
  %15 = add nuw nsw i32 %.06695.us.us, 1
  %exitcond122.not = icmp eq i32 %15, 16
  br i1 %exitcond122.not, label %.split97.us.us, label %.preheader72.us.us, !llvm.loop !15

.split97.us.us:                                   ; preds = %.split94.us.us.us
  %16 = add nuw nsw i32 %.16898.us, 1
  %exitcond123.not = icmp eq i32 %16, 16
  br i1 %exitcond123.not, label %.split101.us, label %.preheader73.us, !llvm.loop !16

.preheader73:                                     ; preds = %4, %.split97
  %.16898 = phi i32 [ %85, %.split97 ], [ 0, %4 ]
  br label %.preheader72

.preheader72:                                     ; preds = %.preheader73, %.split94
  %.06695 = phi i32 [ 0, %.preheader73 ], [ %84, %.split94 ]
  %17 = icmp eq i32 %.06695, 0
  %18 = icmp eq i32 %.06695, 1
  %19 = icmp eq i32 %.06695, 2
  %20 = icmp eq i32 %.06695, 3
  %21 = icmp eq i32 %.06695, 4
  %22 = icmp eq i32 %.06695, 5
  %23 = icmp eq i32 %.06695, 6
  %24 = icmp eq i32 %.06695, 7
  %25 = icmp eq i32 %.06695, 8
  %26 = icmp eq i32 %.06695, 9
  %27 = icmp eq i32 %.06695, 10
  %28 = icmp eq i32 %.06695, 11
  %29 = icmp eq i32 %.06695, 12
  %30 = icmp eq i32 %.06695, 13
  %31 = icmp eq i32 %.06695, 14
  %32 = icmp eq i32 %.06695, 15
  br label %.preheader71

.preheader71:                                     ; preds = %.preheader72, %.split91
  %indvars.iv109 = phi i64 [ 0, %.preheader72 ], [ %indvars.iv.next110, %.split91 ]
  %33 = getelementptr inbounds [3 x i32], ptr @__const.test_vex_mask_load_store.displ, i64 0, i64 %indvars.iv109
  br label %.preheader70

.preheader70:                                     ; preds = %.preheader71, %.split
  %.188 = phi i32 [ 0, %.preheader71 ], [ %83, %.split ]
  %34 = icmp eq i32 %.06695, %.188
  %.fr = freeze i1 %34
  br i1 %.fr, label %.split, label %.preheader70.split.split.preheader

.preheader70.split.split.preheader:               ; preds = %.preheader70
  %35 = icmp eq i32 %.188, 0
  %or.cond = or i1 %17, %35
  br i1 %or.cond, label %.preheader70.split.split.1, label %36

36:                                               ; preds = %.preheader70.split.split.preheader
  %37 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %37, i8 noundef signext 121, i32 noundef 0, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.1

.preheader70.split.split.1:                       ; preds = %36, %.preheader70.split.split.preheader
  %38 = icmp eq i32 %.188, 1
  %or.cond.1 = or i1 %18, %38
  br i1 %or.cond.1, label %.preheader70.split.split.2, label %39

39:                                               ; preds = %.preheader70.split.split.1
  %40 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %40, i8 noundef signext 121, i32 noundef 1, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.2

.preheader70.split.split.2:                       ; preds = %39, %.preheader70.split.split.1
  %41 = icmp eq i32 %.188, 2
  %or.cond.2 = or i1 %19, %41
  br i1 %or.cond.2, label %.preheader70.split.split.3, label %42

42:                                               ; preds = %.preheader70.split.split.2
  %43 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %43, i8 noundef signext 121, i32 noundef 2, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.3

.preheader70.split.split.3:                       ; preds = %42, %.preheader70.split.split.2
  %44 = icmp eq i32 %.188, 3
  %or.cond.3 = or i1 %20, %44
  br i1 %or.cond.3, label %.preheader70.split.split.4, label %45

45:                                               ; preds = %.preheader70.split.split.3
  %46 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %46, i8 noundef signext 121, i32 noundef 3, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.4

.preheader70.split.split.4:                       ; preds = %45, %.preheader70.split.split.3
  %47 = icmp eq i32 %.188, 4
  %or.cond.4 = or i1 %21, %47
  br i1 %or.cond.4, label %.preheader70.split.split.5, label %48

48:                                               ; preds = %.preheader70.split.split.4
  %49 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %49, i8 noundef signext 121, i32 noundef 4, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.5

.preheader70.split.split.5:                       ; preds = %48, %.preheader70.split.split.4
  %50 = icmp eq i32 %.188, 5
  %or.cond.5 = or i1 %22, %50
  br i1 %or.cond.5, label %.preheader70.split.split.6, label %51

51:                                               ; preds = %.preheader70.split.split.5
  %52 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %52, i8 noundef signext 121, i32 noundef 5, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.6

.preheader70.split.split.6:                       ; preds = %51, %.preheader70.split.split.5
  %53 = icmp eq i32 %.188, 6
  %or.cond.6 = or i1 %23, %53
  br i1 %or.cond.6, label %.preheader70.split.split.7, label %54

54:                                               ; preds = %.preheader70.split.split.6
  %55 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %55, i8 noundef signext 121, i32 noundef 6, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.7

.preheader70.split.split.7:                       ; preds = %54, %.preheader70.split.split.6
  %56 = icmp eq i32 %.188, 7
  %or.cond.7 = or i1 %24, %56
  br i1 %or.cond.7, label %.preheader70.split.split.8, label %57

57:                                               ; preds = %.preheader70.split.split.7
  %58 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %58, i8 noundef signext 121, i32 noundef 7, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.8

.preheader70.split.split.8:                       ; preds = %57, %.preheader70.split.split.7
  %59 = icmp eq i32 %.188, 8
  %or.cond.8 = or i1 %25, %59
  br i1 %or.cond.8, label %.preheader70.split.split.9, label %60

60:                                               ; preds = %.preheader70.split.split.8
  %61 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %61, i8 noundef signext 121, i32 noundef 8, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.9

.preheader70.split.split.9:                       ; preds = %60, %.preheader70.split.split.8
  %62 = icmp eq i32 %.188, 9
  %or.cond.9 = or i1 %26, %62
  br i1 %or.cond.9, label %.preheader70.split.split.10, label %63

63:                                               ; preds = %.preheader70.split.split.9
  %64 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %64, i8 noundef signext 121, i32 noundef 9, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.10

.preheader70.split.split.10:                      ; preds = %63, %.preheader70.split.split.9
  %65 = icmp eq i32 %.188, 10
  %or.cond.10 = or i1 %27, %65
  br i1 %or.cond.10, label %.preheader70.split.split.11, label %66

66:                                               ; preds = %.preheader70.split.split.10
  %67 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %67, i8 noundef signext 121, i32 noundef 10, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.11

.preheader70.split.split.11:                      ; preds = %66, %.preheader70.split.split.10
  %68 = icmp eq i32 %.188, 11
  %or.cond.11 = or i1 %28, %68
  br i1 %or.cond.11, label %.preheader70.split.split.12, label %69

69:                                               ; preds = %.preheader70.split.split.11
  %70 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %70, i8 noundef signext 121, i32 noundef 11, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.12

.preheader70.split.split.12:                      ; preds = %69, %.preheader70.split.split.11
  %71 = icmp eq i32 %.188, 12
  %or.cond.12 = or i1 %29, %71
  br i1 %or.cond.12, label %.preheader70.split.split.13, label %72

72:                                               ; preds = %.preheader70.split.split.12
  %73 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %73, i8 noundef signext 121, i32 noundef 12, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.13

.preheader70.split.split.13:                      ; preds = %72, %.preheader70.split.split.12
  %74 = icmp eq i32 %.188, 13
  %or.cond.13 = or i1 %30, %74
  br i1 %or.cond.13, label %.preheader70.split.split.14, label %75

75:                                               ; preds = %.preheader70.split.split.13
  %76 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %76, i8 noundef signext 121, i32 noundef 13, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.14

.preheader70.split.split.14:                      ; preds = %75, %.preheader70.split.split.13
  %77 = icmp eq i32 %.188, 14
  %or.cond.14 = or i1 %31, %77
  br i1 %or.cond.14, label %.preheader70.split.split.15, label %78

78:                                               ; preds = %.preheader70.split.split.14
  %79 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %79, i8 noundef signext 121, i32 noundef 14, i32 noundef %.188, i32 noundef 0) #2
  br label %.preheader70.split.split.15

.preheader70.split.split.15:                      ; preds = %78, %.preheader70.split.split.14
  %80 = icmp eq i32 %.188, 15
  %or.cond.15 = or i1 %32, %80
  br i1 %or.cond.15, label %.split, label %81

81:                                               ; preds = %.preheader70.split.split.15
  %82 = load i32, ptr %33, align 4, !tbaa !5
  tail call void @libxsmm_x86_instruction_vec_mask_move(ptr noundef %1, i32 noundef %3, i32 noundef %.16898, i32 noundef %.06695, i32 noundef 2, i32 noundef %82, i8 noundef signext 121, i32 noundef 15, i32 noundef %.188, i32 noundef 0) #2
  br label %.split

.split:                                           ; preds = %.preheader70.split.split.15, %81, %.preheader70
  %83 = add nuw nsw i32 %.188, 1
  %exitcond108.not = icmp eq i32 %83, 16
  br i1 %exitcond108.not, label %.split91, label %.preheader70, !llvm.loop !13

.split91:                                         ; preds = %.split
  %indvars.iv.next110 = add nuw nsw i64 %indvars.iv109, 1
  %exitcond112.not = icmp eq i64 %indvars.iv.next110, 3
  br i1 %exitcond112.not, label %.split94, label %.preheader71, !llvm.loop !14

.split94:                                         ; preds = %.split91
  %84 = add nuw nsw i32 %.06695, 1
  %exitcond113.not = icmp eq i32 %84, 16
  br i1 %exitcond113.not, label %.split97, label %.preheader72, !llvm.loop !15

.split97:                                         ; preds = %.split94
  %85 = add nuw nsw i32 %.16898, 1
  %exitcond114.not = icmp eq i32 %85, 16
  br i1 %exitcond114.not, label %.split101.us, label %.preheader73, !llvm.loop !16

.split101.us:                                     ; preds = %.split97, %.split97.us.us
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

declare void @libxsmm_x86_instruction_vec_mask_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !10}
!16 = distinct !{!16, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass