; LLVM IR from ermig1979/Simd :: src/Simd/SimdBaseImageSavePpm.ll (ZN4Simd4Base12PxmPrintInitEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN4Simd4Base10g_pxmPrintE = external dso_local global [256 x [4 x i8]], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN4Simd4Base12PxmPrintInitEv() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  store i32 0, ptr %1, align 4, !tbaa !5
  br label %5

5:                                                ; preds = %57, %0
  %6 = load i32, ptr %1, align 4, !tbaa !5
  %7 = icmp slt i32 %6, 256
  br i1 %7, label %9, label %8

8:                                                ; preds = %5
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  br label %60

9:                                                ; preds = %5
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  %10 = load i32, ptr %1, align 4, !tbaa !5
  %11 = sdiv i32 %10, 100
  store i32 %11, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  %12 = load i32, ptr %1, align 4, !tbaa !5
  %13 = sdiv i32 %12, 10
  %14 = srem i32 %13, 10
  store i32 %14, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  %15 = load i32, ptr %1, align 4, !tbaa !5
  %16 = srem i32 %15, 10
  store i32 %16, ptr %4, align 4, !tbaa !5
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %22

19:                                               ; preds = %9
  %20 = load i32, ptr %2, align 4, !tbaa !5
  %21 = add nsw i32 48, %20
  br label %23

22:                                               ; preds = %9
  br label %23

23:                                               ; preds = %22, %19
  %24 = phi i32 [ %21, %19 ], [ 32, %22 ]
  %25 = trunc i32 %24 to i8
  %26 = load i32, ptr %1, align 4, !tbaa !5
  %27 = sext i32 %26 to i64
  %28 = getelementptr inbounds [256 x [4 x i8]], ptr @_ZN4Simd4Base10g_pxmPrintE, i64 0, i64 %27
  %29 = getelementptr inbounds [4 x i8], ptr %28, i64 0, i64 0
  store i8 %25, ptr %29, align 4, !tbaa !9
  %30 = load i32, ptr %3, align 4, !tbaa !5
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %35, label %32

32:                                               ; preds = %23
  %33 = load i32, ptr %2, align 4, !tbaa !5
  %34 = icmp ne i32 %33, 0
  br i1 %34, label %35, label %38

35:                                               ; preds = %32, %23
  %36 = load i32, ptr %3, align 4, !tbaa !5
  %37 = add nsw i32 48, %36
  br label %39

38:                                               ; preds = %32
  br label %39

39:                                               ; preds = %38, %35
  %40 = phi i32 [ %37, %35 ], [ 32, %38 ]
  %41 = trunc i32 %40 to i8
  %42 = load i32, ptr %1, align 4, !tbaa !5
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds [256 x [4 x i8]], ptr @_ZN4Simd4Base10g_pxmPrintE, i64 0, i64 %43
  %45 = getelementptr inbounds [4 x i8], ptr %44, i64 0, i64 1
  store i8 %41, ptr %45, align 1, !tbaa !9
  %46 = load i32, ptr %4, align 4, !tbaa !5
  %47 = add nsw i32 48, %46
  %48 = trunc i32 %47 to i8
  %49 = load i32, ptr %1, align 4, !tbaa !5
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds [256 x [4 x i8]], ptr @_ZN4Simd4Base10g_pxmPrintE, i64 0, i64 %50
  %52 = getelementptr inbounds [4 x i8], ptr %51, i64 0, i64 2
  store i8 %48, ptr %52, align 2, !tbaa !9
  %53 = load i32, ptr %1, align 4, !tbaa !5
  %54 = sext i32 %53 to i64
  %55 = getelementptr inbounds [256 x [4 x i8]], ptr @_ZN4Simd4Base10g_pxmPrintE, i64 0, i64 %54
  %56 = getelementptr inbounds [4 x i8], ptr %55, i64 0, i64 3
  store i8 32, ptr %56, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  br label %57

57:                                               ; preds = %39
  %58 = load i32, ptr %1, align 4, !tbaa !5
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %1, align 4, !tbaa !5
  br label %5, !llvm.loop !10

60:                                               ; preds = %8
  ret i1 true
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZN4Simd4Base10g_pxmPrintE = external dso_local local_unnamed_addr global [256 x [4 x i8]], align 16

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(write, argmem: none, inaccessiblemem: none) uwtable
define dso_local noundef zeroext i1 @_ZN4Simd4Base12PxmPrintInitEv() local_unnamed_addr #0 {
vector.ph:
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %vec.ind = phi <16 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>, %vector.ph ], [ %vec.ind.next, %vector.body ]
  %vec.ind24 = phi <16 x i8> [ <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, %vector.ph ], [ %vec.ind.next25, %vector.body ]
  %0 = udiv <16 x i8> %vec.ind24, <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100>
  %vec.ind24.frozen = freeze <16 x i8> %vec.ind24
  %1 = udiv <16 x i8> %vec.ind24.frozen, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
  %2 = urem <16 x i8> %1, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
  %3 = mul <16 x i8> %1, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
  %.decomposed = sub <16 x i8> %vec.ind24.frozen, %3
  %4 = icmp ugt <16 x i64> %vec.ind, <i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99, i64 99>
  %5 = or disjoint <16 x i8> %0, <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>
  %6 = select <16 x i1> %4, <16 x i8> %5, <16 x i8> <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
  %7 = icmp ne <16 x i8> %2, zeroinitializer
  %8 = or <16 x i1> %4, %7
  %9 = or disjoint <16 x i8> %2, <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>
  %10 = select <16 x i1> %8, <16 x i8> %9, <16 x i8> <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
  %11 = or disjoint <16 x i8> %.decomposed, <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>
  %12 = getelementptr inbounds [256 x [4 x i8]], ptr @_ZN4Simd4Base10g_pxmPrintE, i64 0, i64 %index
  %13 = shufflevector <16 x i8> %6, <16 x i8> %10, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
  %14 = shufflevector <16 x i8> %11, <16 x i8> <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
  %interleaved.vec = shufflevector <32 x i8> %13, <32 x i8> %14, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
  store <64 x i8> %interleaved.vec, ptr %12, align 16, !tbaa !5
  %index.next = add nuw i64 %index, 16
  %vec.ind.next = add <16 x i64> %vec.ind, <i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16, i64 16>
  %vec.ind.next25 = add <16 x i8> %vec.ind24, <i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16>
  %15 = icmp eq i64 %index.next, 256
  br i1 %15, label %middle.block, label %vector.body, !llvm.loop !8

middle.block:                                     ; preds = %vector.body
  ret i1 true
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(write, argmem: none, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = distinct !{!8, !9, !10, !11}
!9 = !{!"llvm.loop.mustprogress"}
!10 = !{!"llvm.loop.isvectorized", i32 1}
!11 = !{!"llvm.loop.unroll.runtime.disable"}


; Effective O3 passes: CorrelatedValuePropagationPass,DivRemPairsPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LoopLoadEliminationPass,LoopRotatePass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass