; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_store_32x32_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6) #0 {
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store i32 %1, ptr %9, align 4, !tbaa !9
  store i32 %2, ptr %10, align 4, !tbaa !9
  store i32 %3, ptr %11, align 4, !tbaa !9
  store i32 %4, ptr %12, align 4, !tbaa !9
  store i32 %5, ptr %13, align 4, !tbaa !9
  store i32 %6, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %21 = load i32, ptr %12, align 4, !tbaa !9
  %22 = icmp ule i32 %21, 16
  %23 = zext i1 %22 to i64
  %24 = select i1 %22, i32 1, i32 2
  store i32 %24, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #3
  %25 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %25, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #3
  store i32 0, ptr %17, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #3
  store i32 0, ptr %18, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #3
  store i32 0, ptr %19, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #3
  store i32 0, ptr %20, align 4, !tbaa !9
  %26 = load ptr, ptr %8, align 8, !tbaa !5
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %26, i32 noundef 4)
  %27 = load i32, ptr %11, align 4, !tbaa !9
  %28 = icmp eq i32 %27, 32
  br i1 %28, label %29, label %32

29:                                               ; preds = %7
  %30 = load ptr, ptr %8, align 8, !tbaa !5
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %30, i32 noundef 0, i32 noundef -1, i32 noundef 11)
  %31 = load ptr, ptr %8, align 8, !tbaa !5
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %31, i32 noundef 2, i32 noundef -1, i32 noundef 11)
  br label %46

32:                                               ; preds = %7
  %33 = load i32, ptr %11, align 4, !tbaa !9
  %34 = icmp uge i32 %33, 16
  br i1 %34, label %35, label %41

35:                                               ; preds = %32
  %36 = load ptr, ptr %8, align 8, !tbaa !5
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %36, i32 noundef 0, i32 noundef -1, i32 noundef 11)
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = load i32, ptr %11, align 4, !tbaa !9
  %39 = sub i32 %38, 16
  %40 = mul i32 %39, 4
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %37, i32 noundef 2, i32 noundef %40, i32 noundef 11)
  br label %45

41:                                               ; preds = %32
  %42 = load ptr, ptr %8, align 8, !tbaa !5
  %43 = load i32, ptr %11, align 4, !tbaa !9
  %44 = mul i32 %43, 4
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %42, i32 noundef 0, i32 noundef %44, i32 noundef 11)
  br label %45

45:                                               ; preds = %41, %35
  br label %46

46:                                               ; preds = %45, %29
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %47

47:                                               ; preds = %191, %46
  %48 = load i32, ptr %17, align 4, !tbaa !9
  %49 = load i32, ptr %15, align 4, !tbaa !9
  %50 = icmp ult i32 %48, %49
  br i1 %50, label %51, label %194

51:                                               ; preds = %47
  store i32 0, ptr %20, align 4, !tbaa !9
  br label %52

52:                                               ; preds = %80, %51
  %53 = load i32, ptr %20, align 4, !tbaa !9
  %54 = icmp ult i32 %53, 4
  br i1 %54, label %55, label %83

55:                                               ; preds = %52
  %56 = load ptr, ptr %8, align 8, !tbaa !5
  %57 = load i32, ptr %17, align 4, !tbaa !9
  %58 = mul i32 %57, 2
  %59 = load i32, ptr %17, align 4, !tbaa !9
  %60 = mul i32 2, %59
  %61 = add i32 12, %60
  %62 = load i32, ptr %20, align 4, !tbaa !9
  %63 = icmp ult i32 %62, 2
  br i1 %63, label %64, label %67

64:                                               ; preds = %55
  %65 = load i32, ptr %20, align 4, !tbaa !9
  %66 = add i32 0, %65
  br label %71

67:                                               ; preds = %55
  %68 = load i32, ptr %20, align 4, !tbaa !9
  %69 = add i32 0, %68
  %70 = add i32 %69, 2
  br label %71

71:                                               ; preds = %67, %64
  %72 = phi i32 [ %66, %64 ], [ %70, %67 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %56, i32 noundef -1064958976, i32 noundef %58, i32 noundef %61, i32 noundef %72)
  %73 = load ptr, ptr %8, align 8, !tbaa !5
  %74 = load i32, ptr %17, align 4, !tbaa !9
  %75 = mul i32 2, %74
  %76 = add i32 12, %75
  %77 = load i32, ptr %17, align 4, !tbaa !9
  %78 = mul i32 2, %77
  %79 = add i32 12, %78
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %73, i32 noundef 285212678, i32 noundef %76, i32 noundef %79, i32 noundef 4, i8 noundef zeroext 0)
  br label %80

80:                                               ; preds = %71
  %81 = load i32, ptr %20, align 4, !tbaa !9
  %82 = add i32 %81, 1
  store i32 %82, ptr %20, align 4, !tbaa !9
  br label %52, !llvm.loop !11

83:                                               ; preds = %52
  %84 = load i32, ptr %11, align 4, !tbaa !9
  %85 = icmp ugt i32 %84, 16
  br i1 %85, label %86, label %119

86:                                               ; preds = %83
  store i32 0, ptr %20, align 4, !tbaa !9
  br label %87

87:                                               ; preds = %115, %86
  %88 = load i32, ptr %20, align 4, !tbaa !9
  %89 = icmp ult i32 %88, 4
  br i1 %89, label %90, label %118

90:                                               ; preds = %87
  %91 = load ptr, ptr %8, align 8, !tbaa !5
  %92 = load i32, ptr %17, align 4, !tbaa !9
  %93 = mul i32 %92, 2
  %94 = add i32 1, %93
  %95 = load i32, ptr %17, align 4, !tbaa !9
  %96 = mul i32 2, %95
  %97 = add i32 13, %96
  %98 = load i32, ptr %20, align 4, !tbaa !9
  %99 = icmp ult i32 %98, 2
  br i1 %99, label %100, label %103

100:                                              ; preds = %90
  %101 = load i32, ptr %20, align 4, !tbaa !9
  %102 = add i32 %101, 2
  br label %106

103:                                              ; preds = %90
  %104 = load i32, ptr %20, align 4, !tbaa !9
  %105 = add i32 4, %104
  br label %106

106:                                              ; preds = %103, %100
  %107 = phi i32 [ %102, %100 ], [ %105, %103 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %91, i32 noundef -1064958976, i32 noundef %94, i32 noundef %97, i32 noundef %107)
  %108 = load ptr, ptr %8, align 8, !tbaa !5
  %109 = load i32, ptr %17, align 4, !tbaa !9
  %110 = mul i32 2, %109
  %111 = add i32 13, %110
  %112 = load i32, ptr %17, align 4, !tbaa !9
  %113 = mul i32 2, %112
  %114 = add i32 13, %113
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %108, i32 noundef 285212678, i32 noundef %111, i32 noundef %114, i32 noundef 4, i8 noundef zeroext 0)
  br label %115

115:                                              ; preds = %106
  %116 = load i32, ptr %20, align 4, !tbaa !9
  %117 = add i32 %116, 1
  store i32 %117, ptr %20, align 4, !tbaa !9
  br label %87, !llvm.loop !13

118:                                              ; preds = %87
  br label %119

119:                                              ; preds = %118, %83
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %120

120:                                              ; preds = %185, %119
  %121 = load i32, ptr %18, align 4, !tbaa !9
  %122 = load i32, ptr %16, align 4, !tbaa !9
  %123 = icmp ugt i32 %122, 16
  br i1 %123, label %124, label %125

124:                                              ; preds = %120
  br label %127

125:                                              ; preds = %120
  %126 = load i32, ptr %16, align 4, !tbaa !9
  br label %127

127:                                              ; preds = %125, %124
  %128 = phi i32 [ 16, %124 ], [ %126, %125 ]
  %129 = icmp ult i32 %121, %128
  br i1 %129, label %130, label %188

130:                                              ; preds = %127
  %131 = load i32, ptr %18, align 4, !tbaa !9
  %132 = icmp ult i32 %131, 8
  br i1 %132, label %133, label %134

133:                                              ; preds = %130
  store i32 0, ptr %19, align 4, !tbaa !9
  br label %135

134:                                              ; preds = %130
  store i32 8, ptr %19, align 4, !tbaa !9
  br label %135

135:                                              ; preds = %134, %133
  %136 = load ptr, ptr %8, align 8, !tbaa !5
  %137 = load i32, ptr %17, align 4, !tbaa !9
  %138 = icmp eq i32 %137, 0
  br i1 %138, label %139, label %141

139:                                              ; preds = %135
  %140 = load i32, ptr %9, align 4, !tbaa !9
  br label %143

141:                                              ; preds = %135
  %142 = load i32, ptr %10, align 4, !tbaa !9
  br label %143

143:                                              ; preds = %141, %139
  %144 = phi i32 [ %140, %139 ], [ %142, %141 ]
  %145 = load i32, ptr %18, align 4, !tbaa !9
  %146 = load i32, ptr %19, align 4, !tbaa !9
  %147 = add i32 %145, %146
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %136, i32 noundef -448733050, i32 noundef %144, i32 noundef 127, i32 noundef 0, i32 noundef %147, i32 noundef 0)
  %148 = load i32, ptr %11, align 4, !tbaa !9
  %149 = icmp ugt i32 %148, 16
  br i1 %149, label %150, label %164

150:                                              ; preds = %143
  %151 = load ptr, ptr %8, align 8, !tbaa !5
  %152 = load i32, ptr %17, align 4, !tbaa !9
  %153 = icmp eq i32 %152, 0
  br i1 %153, label %154, label %156

154:                                              ; preds = %150
  %155 = load i32, ptr %9, align 4, !tbaa !9
  br label %158

156:                                              ; preds = %150
  %157 = load i32, ptr %10, align 4, !tbaa !9
  br label %158

158:                                              ; preds = %156, %154
  %159 = phi i32 [ %155, %154 ], [ %157, %156 ]
  %160 = load i32, ptr %18, align 4, !tbaa !9
  %161 = add i32 %160, 8
  %162 = load i32, ptr %19, align 4, !tbaa !9
  %163 = add i32 %161, %162
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %151, i32 noundef -448733050, i32 noundef %159, i32 noundef 127, i32 noundef 1, i32 noundef %163, i32 noundef 2)
  br label %164

164:                                              ; preds = %158, %143
  %165 = load ptr, ptr %8, align 8, !tbaa !5
  %166 = load i32, ptr %17, align 4, !tbaa !9
  %167 = icmp eq i32 %166, 0
  br i1 %167, label %168, label %170

168:                                              ; preds = %164
  %169 = load i32, ptr %9, align 4, !tbaa !9
  br label %172

170:                                              ; preds = %164
  %171 = load i32, ptr %10, align 4, !tbaa !9
  br label %172

172:                                              ; preds = %170, %168
  %173 = phi i32 [ %169, %168 ], [ %171, %170 ]
  %174 = load i32, ptr %17, align 4, !tbaa !9
  %175 = icmp eq i32 %174, 0
  br i1 %175, label %176, label %178

176:                                              ; preds = %172
  %177 = load i32, ptr %9, align 4, !tbaa !9
  br label %180

178:                                              ; preds = %172
  %179 = load i32, ptr %10, align 4, !tbaa !9
  br label %180

180:                                              ; preds = %178, %176
  %181 = phi i32 [ %177, %176 ], [ %179, %178 ]
  %182 = load i32, ptr %13, align 4, !tbaa !9
  %183 = mul i32 %182, 4
  %184 = zext i32 %183 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %165, i32 noundef 4096, i32 noundef %173, i32 noundef 43, i32 noundef %181, i64 noundef %184)
  br label %185

185:                                              ; preds = %180
  %186 = load i32, ptr %18, align 4, !tbaa !9
  %187 = add i32 %186, 1
  store i32 %187, ptr %18, align 4, !tbaa !9
  br label %120, !llvm.loop !14

188:                                              ; preds = %127
  %189 = load i32, ptr %16, align 4, !tbaa !9
  %190 = sub i32 %189, 16
  store i32 %190, ptr %16, align 4, !tbaa !9
  br label %191

191:                                              ; preds = %188
  %192 = load i32, ptr %17, align 4, !tbaa !9
  %193 = add i32 %192, 1
  store i32 %193, ptr %17, align 4, !tbaa !9
  br label %47, !llvm.loop !15

194:                                              ; preds = %47
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_store_32x32_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6) local_unnamed_addr #0 {
  %8 = icmp ugt i32 %4, 16
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef 4)
  %9 = icmp eq i32 %3, 32
  br i1 %9, label %10, label %11

10:                                               ; preds = %7
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef -1, i32 noundef 11)
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 2, i32 noundef -1, i32 noundef 11)
  br label %18

11:                                               ; preds = %7
  %12 = icmp ugt i32 %3, 15
  br i1 %12, label %13, label %16

13:                                               ; preds = %11
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef -1, i32 noundef 11)
  %14 = shl i32 %3, 2
  %15 = add i32 %14, -64
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 2, i32 noundef %15, i32 noundef 11)
  br label %18

16:                                               ; preds = %11
  %17 = shl nuw nsw i32 %3, 2
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef %17, i32 noundef 11)
  br label %18

18:                                               ; preds = %13, %16, %10
  %19 = icmp ugt i32 %3, 16
  %20 = shl i32 %5, 2
  %21 = zext i32 %20 to i64
  br label %.preheader69

.preheader69:                                     ; preds = %18, %._crit_edge
  %22 = phi i32 [ %1, %18 ], [ %2, %._crit_edge ]
  %23 = phi i1 [ true, %18 ], [ false, %._crit_edge ]
  %.06674 = phi i32 [ 0, %18 ], [ 2, %._crit_edge ]
  %.06773 = phi i32 [ %4, %18 ], [ %34, %._crit_edge ]
  %umin = tail call i32 @llvm.umin.i32(i32 %.06773, i32 16)
  %umax = tail call i32 @llvm.umax.i32(i32 %umin, i32 1)
  %24 = or disjoint i32 %.06674, 12
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %.06674, i32 noundef %24, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %24, i32 noundef %24, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %.06674, i32 noundef %24, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %24, i32 noundef %24, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %.06674, i32 noundef %24, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %24, i32 noundef %24, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %.06674, i32 noundef %24, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %24, i32 noundef %24, i32 noundef 4, i8 noundef zeroext 0) #3
  br i1 %19, label %.preheader, label %.loopexit

.preheader:                                       ; preds = %.preheader69
  %25 = or disjoint i32 %.06674, 1
  %26 = or disjoint i32 %.06674, 13
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %25, i32 noundef %26, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %26, i32 noundef %26, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %25, i32 noundef %26, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %26, i32 noundef %26, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %25, i32 noundef %26, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %26, i32 noundef %26, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef %25, i32 noundef %26, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %26, i32 noundef %26, i32 noundef 4, i8 noundef zeroext 0) #3
  br label %.loopexit

.loopexit:                                        ; preds = %.preheader, %.preheader69
  %.not = icmp eq i32 %.06773, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.loopexit, %32
  %.06572 = phi i32 [ %33, %32 ], [ 0, %.loopexit ]
  %27 = icmp ult i32 %.06572, 8
  %. = select i1 %27, i32 0, i32 8
  %28 = add nuw nsw i32 %., %.06572
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef %22, i32 noundef 127, i32 noundef 0, i32 noundef %28, i32 noundef 0) #3
  br i1 %19, label %29, label %32

29:                                               ; preds = %.lr.ph
  %30 = add nuw nsw i32 %.06572, 8
  %31 = add nuw nsw i32 %30, %.
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef %22, i32 noundef 127, i32 noundef 1, i32 noundef %31, i32 noundef 2) #3
  br label %32

32:                                               ; preds = %29, %.lr.ph
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %22, i32 noundef 43, i32 noundef %22, i64 noundef %21) #3
  %33 = add nuw nsw i32 %.06572, 1
  %exitcond.not = icmp eq i32 %33, %umax
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !5

._crit_edge:                                      ; preds = %32, %.loopexit
  %34 = add i32 %.06773, -16
  %35 = and i1 %8, %23
  br i1 %35, label %.preheader69, label %36, !llvm.loop !7

36:                                               ; preds = %._crit_edge
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass