; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_asimd_move.simd = external hidden unnamed_addr constant [5 x i32], align 16

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local void @test_asimd_move(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca [5 x i32], align 16
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i16, align 2
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 20, ptr %9) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %9, ptr align 16 @__const.test_asimd_move.simd, i64 20, i1 false)
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #4
  store i16 64, ptr %12, align 2, !tbaa !11
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %13, ptr noundef %14)
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = icmp eq i32 %15, 1012942851
  br i1 %16, label %20, label %17

17:                                               ; preds = %3
  %18 = load i32, ptr %6, align 4, !tbaa !9
  %19 = icmp eq i32 %18, 1008748547
  br i1 %19, label %20, label %69

20:                                               ; preds = %17, %3
  store i8 0, ptr %7, align 1, !tbaa !13
  br label %21

21:                                               ; preds = %65, %20
  %22 = load i8, ptr %7, align 1, !tbaa !13
  %23 = zext i8 %22 to i32
  %24 = icmp slt i32 %23, 32
  br i1 %24, label %25, label %68

25:                                               ; preds = %21
  store i8 0, ptr %8, align 1, !tbaa !13
  br label %26

26:                                               ; preds = %61, %25
  %27 = load i8, ptr %8, align 1, !tbaa !13
  %28 = zext i8 %27 to i32
  %29 = icmp slt i32 %28, 64
  br i1 %29, label %30, label %64

30:                                               ; preds = %26
  store i8 0, ptr %10, align 1, !tbaa !13
  br label %31

31:                                               ; preds = %57, %30
  %32 = load i8, ptr %10, align 1, !tbaa !13
  %33 = zext i8 %32 to i32
  %34 = icmp slt i32 %33, 32
  br i1 %34, label %35, label %60

35:                                               ; preds = %31
  store i8 0, ptr %11, align 1, !tbaa !13
  br label %36

36:                                               ; preds = %53, %35
  %37 = load i8, ptr %11, align 1, !tbaa !13
  %38 = zext i8 %37 to i32
  %39 = icmp slt i32 %38, 5
  br i1 %39, label %40, label %56

40:                                               ; preds = %36
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = load i32, ptr %6, align 4, !tbaa !9
  %43 = load i8, ptr %7, align 1, !tbaa !13
  %44 = zext i8 %43 to i32
  %45 = load i8, ptr %8, align 1, !tbaa !13
  %46 = zext i8 %45 to i32
  %47 = load i8, ptr %10, align 1, !tbaa !13
  %48 = zext i8 %47 to i32
  %49 = load i8, ptr %11, align 1, !tbaa !13
  %50 = zext i8 %49 to i64
  %51 = getelementptr inbounds [5 x i32], ptr %9, i64 0, i64 %50
  %52 = load i32, ptr %51, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %41, i32 noundef %42, i32 noundef %44, i32 noundef %46, i32 noundef 0, i32 noundef %48, i32 noundef %52)
  br label %53

53:                                               ; preds = %40
  %54 = load i8, ptr %11, align 1, !tbaa !13
  %55 = add i8 %54, 1
  store i8 %55, ptr %11, align 1, !tbaa !13
  br label %36, !llvm.loop !14

56:                                               ; preds = %36
  br label %57

57:                                               ; preds = %56
  %58 = load i8, ptr %10, align 1, !tbaa !13
  %59 = add i8 %58, 1
  store i8 %59, ptr %10, align 1, !tbaa !13
  br label %31, !llvm.loop !16

60:                                               ; preds = %31
  br label %61

61:                                               ; preds = %60
  %62 = load i8, ptr %8, align 1, !tbaa !13
  %63 = add i8 %62, 1
  store i8 %63, ptr %8, align 1, !tbaa !13
  br label %26, !llvm.loop !17

64:                                               ; preds = %26
  br label %65

65:                                               ; preds = %64
  %66 = load i8, ptr %7, align 1, !tbaa !13
  %67 = add i8 %66, 1
  store i8 %67, ptr %7, align 1, !tbaa !13
  br label %21, !llvm.loop !18

68:                                               ; preds = %21
  br label %109

69:                                               ; preds = %17
  store i8 0, ptr %7, align 1, !tbaa !13
  br label %70

70:                                               ; preds = %105, %69
  %71 = load i8, ptr %7, align 1, !tbaa !13
  %72 = zext i8 %71 to i32
  %73 = icmp slt i32 %72, 32
  br i1 %73, label %74, label %108

74:                                               ; preds = %70
  store i8 0, ptr %10, align 1, !tbaa !13
  br label %75

75:                                               ; preds = %101, %74
  %76 = load i8, ptr %10, align 1, !tbaa !13
  %77 = zext i8 %76 to i32
  %78 = icmp slt i32 %77, 32
  br i1 %78, label %79, label %104

79:                                               ; preds = %75
  store i8 0, ptr %11, align 1, !tbaa !13
  br label %80

80:                                               ; preds = %97, %79
  %81 = load i8, ptr %11, align 1, !tbaa !13
  %82 = zext i8 %81 to i32
  %83 = icmp slt i32 %82, 5
  br i1 %83, label %84, label %100

84:                                               ; preds = %80
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = load i32, ptr %6, align 4, !tbaa !9
  %87 = load i8, ptr %7, align 1, !tbaa !13
  %88 = zext i8 %87 to i32
  %89 = load i16, ptr %12, align 2, !tbaa !11
  %90 = sext i16 %89 to i32
  %91 = load i8, ptr %10, align 1, !tbaa !13
  %92 = zext i8 %91 to i32
  %93 = load i8, ptr %11, align 1, !tbaa !13
  %94 = zext i8 %93 to i64
  %95 = getelementptr inbounds [5 x i32], ptr %9, i64 0, i64 %94
  %96 = load i32, ptr %95, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %85, i32 noundef %86, i32 noundef %88, i32 noundef 0, i32 noundef %90, i32 noundef %92, i32 noundef %96)
  br label %97

97:                                               ; preds = %84
  %98 = load i8, ptr %11, align 1, !tbaa !13
  %99 = add i8 %98, 1
  store i8 %99, ptr %11, align 1, !tbaa !13
  br label %80, !llvm.loop !19

100:                                              ; preds = %80
  br label %101

101:                                              ; preds = %100
  %102 = load i8, ptr %10, align 1, !tbaa !13
  %103 = add i8 %102, 1
  store i8 %103, ptr %10, align 1, !tbaa !13
  br label %75, !llvm.loop !20

104:                                              ; preds = %75
  br label %105

105:                                              ; preds = %104
  %106 = load i8, ptr %7, align 1, !tbaa !13
  %107 = add i8 %106, 1
  store i8 %107, ptr %7, align 1, !tbaa !13
  br label %70, !llvm.loop !21

108:                                              ; preds = %70
  br label %109

109:                                              ; preds = %108, %68
  %110 = load ptr, ptr %5, align 8, !tbaa !5
  %111 = load ptr, ptr %4, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %110, ptr noundef %111)
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 20, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}
!19 = distinct !{!19, !15}
!20 = distinct !{!20, !15}
!21 = distinct !{!21, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_asimd_move.simd = external hidden unnamed_addr constant [5 x i32], align 16

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @test_asimd_move(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %4 = and i32 %2, -4194305
  %or.cond = icmp eq i32 %4, 1008748547
  %.pre84.pre.pre = load i32, ptr @__const.test_asimd_move.simd, align 16, !tbaa !5
  %.pre85.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_asimd_move.simd, i64 4), align 4, !tbaa !5
  %.pre86.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_asimd_move.simd, i64 8), align 8, !tbaa !5
  %.pre87.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_asimd_move.simd, i64 12), align 4, !tbaa !5
  %.pre88.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_asimd_move.simd, i64 16), align 16, !tbaa !5
  br i1 %or.cond, label %.preheader44, label %.preheader47

.preheader44:                                     ; preds = %3, %6
  %indvars.iv76 = phi i32 [ %indvars.iv.next77, %6 ], [ 0, %3 ]
  br label %.preheader43

.preheader43:                                     ; preds = %.preheader44, %5
  %indvars.iv72 = phi i32 [ 0, %.preheader44 ], [ %indvars.iv.next73, %5 ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader43, %.preheader
  %indvars.iv68 = phi i32 [ 0, %.preheader43 ], [ %indvars.iv.next69, %.preheader ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv76, i32 noundef %indvars.iv72, i32 noundef 0, i32 noundef %indvars.iv68, i32 noundef %.pre84.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv76, i32 noundef %indvars.iv72, i32 noundef 0, i32 noundef %indvars.iv68, i32 noundef %.pre85.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv76, i32 noundef %indvars.iv72, i32 noundef 0, i32 noundef %indvars.iv68, i32 noundef %.pre86.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv76, i32 noundef %indvars.iv72, i32 noundef 0, i32 noundef %indvars.iv68, i32 noundef %.pre87.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv76, i32 noundef %indvars.iv72, i32 noundef 0, i32 noundef %indvars.iv68, i32 noundef %.pre88.pre.pre) #2
  %indvars.iv.next69 = add nuw nsw i32 %indvars.iv68, 1
  %exitcond71.not = icmp eq i32 %indvars.iv.next69, 32
  br i1 %exitcond71.not, label %5, label %.preheader, !llvm.loop !9

5:                                                ; preds = %.preheader
  %indvars.iv.next73 = add nuw nsw i32 %indvars.iv72, 1
  %exitcond75.not = icmp eq i32 %indvars.iv.next73, 64
  br i1 %exitcond75.not, label %6, label %.preheader43, !llvm.loop !11

6:                                                ; preds = %5
  %indvars.iv.next77 = add nuw nsw i32 %indvars.iv76, 1
  %exitcond79.not = icmp eq i32 %indvars.iv.next77, 32
  br i1 %exitcond79.not, label %.loopexit, label %.preheader44, !llvm.loop !12

.preheader47:                                     ; preds = %3, %7
  %indvars.iv60 = phi i32 [ %indvars.iv.next61, %7 ], [ 0, %3 ]
  br label %.preheader46

.preheader46:                                     ; preds = %.preheader47, %.preheader46
  %indvars.iv = phi i32 [ 0, %.preheader47 ], [ %indvars.iv.next, %.preheader46 ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv60, i32 noundef 0, i32 noundef 64, i32 noundef %indvars.iv, i32 noundef %.pre84.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv60, i32 noundef 0, i32 noundef 64, i32 noundef %indvars.iv, i32 noundef %.pre85.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv60, i32 noundef 0, i32 noundef 64, i32 noundef %indvars.iv, i32 noundef %.pre86.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv60, i32 noundef 0, i32 noundef 64, i32 noundef %indvars.iv, i32 noundef %.pre87.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv60, i32 noundef 0, i32 noundef 64, i32 noundef %indvars.iv, i32 noundef %.pre88.pre.pre) #2
  %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
  %exitcond.not = icmp eq i32 %indvars.iv.next, 32
  br i1 %exitcond.not, label %7, label %.preheader46, !llvm.loop !13

7:                                                ; preds = %.preheader46
  %indvars.iv.next61 = add nuw nsw i32 %indvars.iv60, 1
  %exitcond63.not = icmp eq i32 %indvars.iv.next61, 32
  br i1 %exitcond63.not, label %.loopexit, label %.preheader47, !llvm.loop !14

.loopexit:                                        ; preds = %7, %6
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass