; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_gpr_alu_compute_shifted_reg.shift = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nounwind uwtable
define dso_local void @test_gpr_alu_compute_shifted_reg(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca [3 x i32], align 4
  %11 = alloca i16, align 2
  %12 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 12, ptr %10) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %10, ptr align 4 @__const.test_gpr_alu_compute_shifted_reg.shift, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  store i16 20, ptr %11, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #4
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %13, ptr noundef %14)
  store i8 0, ptr %7, align 1, !tbaa !13
  br label %15

15:                                               ; preds = %73, %3
  %16 = load i8, ptr %7, align 1, !tbaa !13
  %17 = zext i8 %16 to i32
  %18 = icmp slt i32 %17, 32
  br i1 %18, label %19, label %76

19:                                               ; preds = %15
  store i8 0, ptr %8, align 1, !tbaa !13
  br label %20

20:                                               ; preds = %69, %19
  %21 = load i8, ptr %8, align 1, !tbaa !13
  %22 = zext i8 %21 to i32
  %23 = icmp slt i32 %22, 32
  br i1 %23, label %24, label %72

24:                                               ; preds = %20
  store i8 0, ptr %9, align 1, !tbaa !13
  br label %25

25:                                               ; preds = %65, %24
  %26 = load i8, ptr %9, align 1, !tbaa !13
  %27 = zext i8 %26 to i32
  %28 = icmp slt i32 %27, 32
  br i1 %28, label %29, label %68

29:                                               ; preds = %25
  store i8 0, ptr %12, align 1, !tbaa !13
  br label %30

30:                                               ; preds = %61, %29
  %31 = load i8, ptr %12, align 1, !tbaa !13
  %32 = zext i8 %31 to i32
  %33 = icmp slt i32 %32, 3
  br i1 %33, label %34, label %64

34:                                               ; preds = %30
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  %36 = load i32, ptr %6, align 4, !tbaa !9
  %37 = load i8, ptr %8, align 1, !tbaa !13
  %38 = zext i8 %37 to i32
  %39 = load i8, ptr %9, align 1, !tbaa !13
  %40 = zext i8 %39 to i32
  %41 = load i8, ptr %7, align 1, !tbaa !13
  %42 = zext i8 %41 to i32
  %43 = load i8, ptr %12, align 1, !tbaa !13
  %44 = zext i8 %43 to i64
  %45 = getelementptr inbounds [3 x i32], ptr %10, i64 0, i64 %44
  %46 = load i32, ptr %45, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %35, i32 noundef %36, i32 noundef %38, i32 noundef %40, i32 noundef %42, i32 noundef 0, i32 noundef %46)
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = load i8, ptr %8, align 1, !tbaa !13
  %50 = zext i8 %49 to i32
  %51 = load i8, ptr %9, align 1, !tbaa !13
  %52 = zext i8 %51 to i32
  %53 = load i8, ptr %7, align 1, !tbaa !13
  %54 = zext i8 %53 to i32
  %55 = load i16, ptr %11, align 2, !tbaa !11
  %56 = zext i16 %55 to i32
  %57 = load i8, ptr %12, align 1, !tbaa !13
  %58 = zext i8 %57 to i64
  %59 = getelementptr inbounds [3 x i32], ptr %10, i64 0, i64 %58
  %60 = load i32, ptr %59, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %47, i32 noundef %48, i32 noundef %50, i32 noundef %52, i32 noundef %54, i32 noundef %56, i32 noundef %60)
  br label %61

61:                                               ; preds = %34
  %62 = load i8, ptr %12, align 1, !tbaa !13
  %63 = add i8 %62, 1
  store i8 %63, ptr %12, align 1, !tbaa !13
  br label %30, !llvm.loop !14

64:                                               ; preds = %30
  br label %65

65:                                               ; preds = %64
  %66 = load i8, ptr %9, align 1, !tbaa !13
  %67 = add i8 %66, 1
  store i8 %67, ptr %9, align 1, !tbaa !13
  br label %25, !llvm.loop !16

68:                                               ; preds = %25
  br label %69

69:                                               ; preds = %68
  %70 = load i8, ptr %8, align 1, !tbaa !13
  %71 = add i8 %70, 1
  store i8 %71, ptr %8, align 1, !tbaa !13
  br label %20, !llvm.loop !17

72:                                               ; preds = %20
  br label %73

73:                                               ; preds = %72
  %74 = load i8, ptr %7, align 1, !tbaa !13
  %75 = add i8 %74, 1
  store i8 %75, ptr %7, align 1, !tbaa !13
  br label %15, !llvm.loop !18

76:                                               ; preds = %15
  store i8 32, ptr %7, align 1, !tbaa !13
  br label %77

77:                                               ; preds = %135, %76
  %78 = load i8, ptr %7, align 1, !tbaa !13
  %79 = zext i8 %78 to i32
  %80 = icmp slt i32 %79, 64
  br i1 %80, label %81, label %138

81:                                               ; preds = %77
  store i8 32, ptr %8, align 1, !tbaa !13
  br label %82

82:                                               ; preds = %131, %81
  %83 = load i8, ptr %8, align 1, !tbaa !13
  %84 = zext i8 %83 to i32
  %85 = icmp slt i32 %84, 64
  br i1 %85, label %86, label %134

86:                                               ; preds = %82
  store i8 32, ptr %9, align 1, !tbaa !13
  br label %87

87:                                               ; preds = %127, %86
  %88 = load i8, ptr %9, align 1, !tbaa !13
  %89 = zext i8 %88 to i32
  %90 = icmp slt i32 %89, 64
  br i1 %90, label %91, label %130

91:                                               ; preds = %87
  store i8 0, ptr %12, align 1, !tbaa !13
  br label %92

92:                                               ; preds = %123, %91
  %93 = load i8, ptr %12, align 1, !tbaa !13
  %94 = zext i8 %93 to i32
  %95 = icmp slt i32 %94, 3
  br i1 %95, label %96, label %126

96:                                               ; preds = %92
  %97 = load ptr, ptr %5, align 8, !tbaa !5
  %98 = load i32, ptr %6, align 4, !tbaa !9
  %99 = load i8, ptr %8, align 1, !tbaa !13
  %100 = zext i8 %99 to i32
  %101 = load i8, ptr %9, align 1, !tbaa !13
  %102 = zext i8 %101 to i32
  %103 = load i8, ptr %7, align 1, !tbaa !13
  %104 = zext i8 %103 to i32
  %105 = load i8, ptr %12, align 1, !tbaa !13
  %106 = zext i8 %105 to i64
  %107 = getelementptr inbounds [3 x i32], ptr %10, i64 0, i64 %106
  %108 = load i32, ptr %107, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %97, i32 noundef %98, i32 noundef %100, i32 noundef %102, i32 noundef %104, i32 noundef 0, i32 noundef %108)
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = load i32, ptr %6, align 4, !tbaa !9
  %111 = load i8, ptr %8, align 1, !tbaa !13
  %112 = zext i8 %111 to i32
  %113 = load i8, ptr %9, align 1, !tbaa !13
  %114 = zext i8 %113 to i32
  %115 = load i8, ptr %7, align 1, !tbaa !13
  %116 = zext i8 %115 to i32
  %117 = load i16, ptr %11, align 2, !tbaa !11
  %118 = zext i16 %117 to i32
  %119 = load i8, ptr %12, align 1, !tbaa !13
  %120 = zext i8 %119 to i64
  %121 = getelementptr inbounds [3 x i32], ptr %10, i64 0, i64 %120
  %122 = load i32, ptr %121, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %109, i32 noundef %110, i32 noundef %112, i32 noundef %114, i32 noundef %116, i32 noundef %118, i32 noundef %122)
  br label %123

123:                                              ; preds = %96
  %124 = load i8, ptr %12, align 1, !tbaa !13
  %125 = add i8 %124, 1
  store i8 %125, ptr %12, align 1, !tbaa !13
  br label %92, !llvm.loop !19

126:                                              ; preds = %92
  br label %127

127:                                              ; preds = %126
  %128 = load i8, ptr %9, align 1, !tbaa !13
  %129 = add i8 %128, 1
  store i8 %129, ptr %9, align 1, !tbaa !13
  br label %87, !llvm.loop !20

130:                                              ; preds = %87
  br label %131

131:                                              ; preds = %130
  %132 = load i8, ptr %8, align 1, !tbaa !13
  %133 = add i8 %132, 1
  store i8 %133, ptr %8, align 1, !tbaa !13
  br label %82, !llvm.loop !21

134:                                              ; preds = %82
  br label %135

135:                                              ; preds = %134
  %136 = load i8, ptr %7, align 1, !tbaa !13
  %137 = add i8 %136, 1
  store i8 %137, ptr %7, align 1, !tbaa !13
  br label %77, !llvm.loop !22

138:                                              ; preds = %77
  %139 = load ptr, ptr %5, align 8, !tbaa !5
  %140 = load ptr, ptr %4, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %139, ptr noundef %140)
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  ret void
}

declare void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}
!19 = distinct !{!19, !15}
!20 = distinct !{!20, !15}
!21 = distinct !{!21, !15}
!22 = distinct !{!22, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_gpr_alu_compute_shifted_reg.shift = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @test_gpr_alu_compute_shifted_reg(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %.pre.pre.pre = load i32, ptr @__const.test_gpr_alu_compute_shifted_reg.shift, align 4, !tbaa !5
  %.pre97.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_gpr_alu_compute_shifted_reg.shift, i64 4), align 4, !tbaa !5
  %.pre98.pre.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_gpr_alu_compute_shifted_reg.shift, i64 8), align 4, !tbaa !5
  br label %.preheader62

.preheader62:                                     ; preds = %3, %5
  %indvars.iv77 = phi i32 [ 0, %3 ], [ %indvars.iv.next78, %5 ]
  br label %.preheader61

.preheader61:                                     ; preds = %.preheader62, %4
  %indvars.iv73 = phi i32 [ 0, %.preheader62 ], [ %indvars.iv.next74, %4 ]
  br label %.preheader60

.preheader60:                                     ; preds = %.preheader61, %.preheader60
  %indvars.iv = phi i32 [ 0, %.preheader61 ], [ %indvars.iv.next, %.preheader60 ]
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 0, i32 noundef %.pre.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 20, i32 noundef %.pre.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 0, i32 noundef %.pre97.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 20, i32 noundef %.pre97.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 0, i32 noundef %.pre98.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv73, i32 noundef %indvars.iv, i32 noundef %indvars.iv77, i32 noundef 20, i32 noundef %.pre98.pre.pre) #2
  %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
  %exitcond.not = icmp eq i32 %indvars.iv.next, 32
  br i1 %exitcond.not, label %4, label %.preheader60, !llvm.loop !9

4:                                                ; preds = %.preheader60
  %indvars.iv.next74 = add nuw nsw i32 %indvars.iv73, 1
  %exitcond76.not = icmp eq i32 %indvars.iv.next74, 32
  br i1 %exitcond76.not, label %5, label %.preheader61, !llvm.loop !11

5:                                                ; preds = %4
  %indvars.iv.next78 = add nuw nsw i32 %indvars.iv77, 1
  %exitcond80.not = icmp eq i32 %indvars.iv.next78, 32
  br i1 %exitcond80.not, label %.preheader58, label %.preheader62, !llvm.loop !12

.preheader58:                                     ; preds = %5, %7
  %indvars.iv93 = phi i32 [ %indvars.iv.next94, %7 ], [ 32, %5 ]
  br label %.preheader57

.preheader57:                                     ; preds = %.preheader58, %6
  %indvars.iv89 = phi i32 [ 32, %.preheader58 ], [ %indvars.iv.next90, %6 ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader57, %.preheader
  %indvars.iv85 = phi i32 [ 32, %.preheader57 ], [ %indvars.iv.next86, %.preheader ]
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 0, i32 noundef %.pre.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 20, i32 noundef %.pre.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 0, i32 noundef %.pre97.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 20, i32 noundef %.pre97.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 0, i32 noundef %.pre98.pre.pre) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %1, i32 noundef %2, i32 noundef %indvars.iv89, i32 noundef %indvars.iv85, i32 noundef %indvars.iv93, i32 noundef 20, i32 noundef %.pre98.pre.pre) #2
  %indvars.iv.next86 = add nuw nsw i32 %indvars.iv85, 1
  %exitcond88.not = icmp eq i32 %indvars.iv.next86, 64
  br i1 %exitcond88.not, label %6, label %.preheader, !llvm.loop !13

6:                                                ; preds = %.preheader
  %indvars.iv.next90 = add nuw nsw i32 %indvars.iv89, 1
  %exitcond92.not = icmp eq i32 %indvars.iv.next90, 64
  br i1 %exitcond92.not, label %7, label %.preheader57, !llvm.loop !14

7:                                                ; preds = %6
  %indvars.iv.next94 = add nuw nsw i32 %indvars.iv93, 1
  %exitcond96.not = icmp eq i32 %indvars.iv.next94, 64
  br i1 %exitcond96.not, label %8, label %.preheader58, !llvm.loop !15

8:                                                ; preds = %7
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

declare void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass