; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_transpose_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5) #0 {
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store i32 %2, ptr %9, align 4, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i32 %4, ptr %11, align 4, !tbaa !9
  store i32 %5, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  store i32 0, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  store i32 0, ptr %15, align 4, !tbaa !9
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %16

16:                                               ; preds = %24, %6
  %17 = load i32, ptr %13, align 4, !tbaa !9
  %18 = icmp ult i32 %17, 2
  br i1 %18, label %19, label %27

19:                                               ; preds = %16
  %20 = load ptr, ptr %7, align 8, !tbaa !5
  %21 = load i32, ptr %13, align 4, !tbaa !9
  %22 = add i32 12, %21
  %23 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %20, i32 noundef 1384120320, i32 noundef %22, i8 noundef zeroext 0, i32 noundef %23)
  br label %24

24:                                               ; preds = %19
  %25 = load i32, ptr %13, align 4, !tbaa !9
  %26 = add i32 %25, 1
  store i32 %26, ptr %13, align 4, !tbaa !9
  br label %16, !llvm.loop !11

27:                                               ; preds = %16
  %28 = load i32, ptr %11, align 4, !tbaa !9
  %29 = icmp ugt i32 %28, 16
  br i1 %29, label %30, label %38

30:                                               ; preds = %27
  %31 = load i32, ptr %10, align 4, !tbaa !9
  %32 = icmp eq i32 %31, 0
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  br label %36

34:                                               ; preds = %30
  %35 = load i32, ptr %10, align 4, !tbaa !9
  br label %36

36:                                               ; preds = %34, %33
  %37 = phi i32 [ 16, %33 ], [ %35, %34 ]
  store i32 %37, ptr %15, align 4, !tbaa !9
  br label %46

38:                                               ; preds = %27
  %39 = load i32, ptr %10, align 4, !tbaa !9
  %40 = icmp eq i32 %39, 0
  br i1 %40, label %41, label %42

41:                                               ; preds = %38
  br label %44

42:                                               ; preds = %38
  %43 = load i32, ptr %10, align 4, !tbaa !9
  br label %44

44:                                               ; preds = %42, %41
  %45 = phi i32 [ 32, %41 ], [ %43, %42 ]
  store i32 %45, ptr %15, align 4, !tbaa !9
  br label %46

46:                                               ; preds = %44, %36
  %47 = load i32, ptr %11, align 4, !tbaa !9
  %48 = icmp ugt i32 %47, 16
  br i1 %48, label %49, label %60

49:                                               ; preds = %46
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = load i32, ptr %10, align 4, !tbaa !9
  %52 = icmp ugt i32 %51, 0
  br i1 %52, label %53, label %56

53:                                               ; preds = %49
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = mul nsw i32 %54, 4
  br label %57

56:                                               ; preds = %49
  br label %57

57:                                               ; preds = %56, %53
  %58 = phi i32 [ %55, %53 ], [ -1, %56 ]
  %59 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %50, i32 noundef 0, i32 noundef %58, i32 noundef %59)
  br label %71

60:                                               ; preds = %46
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = load i32, ptr %10, align 4, !tbaa !9
  %63 = icmp ugt i32 %62, 0
  br i1 %63, label %64, label %67

64:                                               ; preds = %60
  %65 = load i32, ptr %10, align 4, !tbaa !9
  %66 = mul nsw i32 %65, 4
  br label %68

67:                                               ; preds = %60
  br label %68

68:                                               ; preds = %67, %64
  %69 = phi i32 [ %66, %64 ], [ -1, %67 ]
  %70 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %61, i32 noundef 8, i32 noundef %69, i32 noundef %70, i32 noundef 0)
  br label %71

71:                                               ; preds = %68, %57
  %72 = load i32, ptr %11, align 4, !tbaa !9
  %73 = icmp ugt i32 %72, 16
  br i1 %73, label %74, label %93

74:                                               ; preds = %71
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %75

75:                                               ; preds = %89, %74
  %76 = load i32, ptr %13, align 4, !tbaa !9
  %77 = load i32, ptr %11, align 4, !tbaa !9
  %78 = icmp ult i32 %76, %77
  br i1 %78, label %79, label %92

79:                                               ; preds = %75
  %80 = load ptr, ptr %7, align 8, !tbaa !5
  %81 = load i32, ptr %8, align 4, !tbaa !9
  %82 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %80, i32 noundef -1522491258, i32 noundef %81, i32 noundef 127, i32 noundef 0, i32 noundef %82, i32 noundef 0)
  %83 = load ptr, ptr %7, align 8, !tbaa !5
  %84 = load i32, ptr %8, align 4, !tbaa !9
  %85 = load i32, ptr %8, align 4, !tbaa !9
  %86 = load i32, ptr %9, align 4, !tbaa !9
  %87 = mul i32 %86, 4
  %88 = zext i32 %87 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %83, i32 noundef 4096, i32 noundef %84, i32 noundef 43, i32 noundef %85, i64 noundef %88)
  br label %89

89:                                               ; preds = %79
  %90 = load i32, ptr %13, align 4, !tbaa !9
  %91 = add i32 %90, 1
  store i32 %91, ptr %13, align 4, !tbaa !9
  br label %75, !llvm.loop !13

92:                                               ; preds = %75
  br label %120

93:                                               ; preds = %71
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %94

94:                                               ; preds = %116, %93
  %95 = load i32, ptr %13, align 4, !tbaa !9
  %96 = load i32, ptr %11, align 4, !tbaa !9
  %97 = icmp ult i32 %95, %96
  br i1 %97, label %98, label %119

98:                                               ; preds = %94
  %99 = load ptr, ptr %7, align 8, !tbaa !5
  %100 = load i32, ptr %13, align 4, !tbaa !9
  %101 = icmp ult i32 %100, 8
  br i1 %101, label %102, label %104

102:                                              ; preds = %98
  %103 = load i32, ptr %13, align 4, !tbaa !9
  br label %107

104:                                              ; preds = %98
  %105 = load i32, ptr %13, align 4, !tbaa !9
  %106 = add i32 %105, 8
  br label %107

107:                                              ; preds = %104, %102
  %108 = phi i32 [ %103, %102 ], [ %106, %104 ]
  %109 = load i32, ptr %8, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %99, i32 noundef -1589624832, i32 noundef %108, i32 noundef %109, i32 noundef 0, i32 noundef 8)
  %110 = load ptr, ptr %7, align 8, !tbaa !5
  %111 = load i32, ptr %8, align 4, !tbaa !9
  %112 = load i32, ptr %8, align 4, !tbaa !9
  %113 = load i32, ptr %9, align 4, !tbaa !9
  %114 = mul i32 %113, 4
  %115 = zext i32 %114 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %110, i32 noundef 4096, i32 noundef %111, i32 noundef 43, i32 noundef %112, i64 noundef %115)
  br label %116

116:                                              ; preds = %107
  %117 = load i32, ptr %13, align 4, !tbaa !9
  %118 = add i32 %117, 1
  store i32 %118, ptr %13, align 4, !tbaa !9
  br label %94, !llvm.loop !14

119:                                              ; preds = %94
  br label %120

120:                                              ; preds = %119, %92
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %121

121:                                              ; preds = %139, %120
  %122 = load i32, ptr %13, align 4, !tbaa !9
  %123 = icmp ult i32 %122, 4
  br i1 %123, label %124, label %142

124:                                              ; preds = %121
  %125 = load ptr, ptr %7, align 8, !tbaa !5
  %126 = load i32, ptr %11, align 4, !tbaa !9
  %127 = icmp ugt i32 %126, 16
  br i1 %127, label %131, label %128

128:                                              ; preds = %124
  %129 = load i32, ptr %13, align 4, !tbaa !9
  %130 = icmp ult i32 %129, 2
  br i1 %130, label %131, label %133

131:                                              ; preds = %128, %124
  %132 = load i32, ptr %13, align 4, !tbaa !9
  br label %136

133:                                              ; preds = %128
  %134 = load i32, ptr %13, align 4, !tbaa !9
  %135 = add i32 %134, 2
  br label %136

136:                                              ; preds = %133, %131
  %137 = phi i32 [ %132, %131 ], [ %135, %133 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %125, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef %137)
  %138 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %138, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %139

139:                                              ; preds = %136
  %140 = load i32, ptr %13, align 4, !tbaa !9
  %141 = add i32 %140, 1
  store i32 %141, ptr %13, align 4, !tbaa !9
  br label %121, !llvm.loop !15

142:                                              ; preds = %121
  %143 = load i32, ptr %11, align 4, !tbaa !9
  %144 = icmp ugt i32 %143, 16
  br i1 %144, label %145, label %157

145:                                              ; preds = %142
  store i32 4, ptr %13, align 4, !tbaa !9
  br label %146

146:                                              ; preds = %153, %145
  %147 = load i32, ptr %13, align 4, !tbaa !9
  %148 = icmp ult i32 %147, 8
  br i1 %148, label %149, label %156

149:                                              ; preds = %146
  %150 = load ptr, ptr %7, align 8, !tbaa !5
  %151 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %150, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %151)
  %152 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %152, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %153

153:                                              ; preds = %149
  %154 = load i32, ptr %13, align 4, !tbaa !9
  %155 = add i32 %154, 1
  store i32 %155, ptr %13, align 4, !tbaa !9
  br label %146, !llvm.loop !16

156:                                              ; preds = %146
  br label %182

157:                                              ; preds = %142
  %158 = load i32, ptr %10, align 4, !tbaa !9
  %159 = icmp ugt i32 %158, 16
  br i1 %159, label %160, label %181

160:                                              ; preds = %157
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %161

161:                                              ; preds = %177, %160
  %162 = load i32, ptr %13, align 4, !tbaa !9
  %163 = icmp ult i32 %162, 4
  br i1 %163, label %164, label %180

164:                                              ; preds = %161
  %165 = load ptr, ptr %7, align 8, !tbaa !5
  %166 = load i32, ptr %13, align 4, !tbaa !9
  %167 = icmp ult i32 %166, 2
  br i1 %167, label %168, label %171

168:                                              ; preds = %164
  %169 = load i32, ptr %13, align 4, !tbaa !9
  %170 = add i32 %169, 2
  br label %174

171:                                              ; preds = %164
  %172 = load i32, ptr %13, align 4, !tbaa !9
  %173 = add i32 %172, 4
  br label %174

174:                                              ; preds = %171, %168
  %175 = phi i32 [ %170, %168 ], [ %173, %171 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %165, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %175)
  %176 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %176, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %177

177:                                              ; preds = %174
  %178 = load i32, ptr %13, align 4, !tbaa !9
  %179 = add i32 %178, 1
  store i32 %179, ptr %13, align 4, !tbaa !9
  br label %161, !llvm.loop !17

180:                                              ; preds = %161
  br label %181

181:                                              ; preds = %180, %157
  br label %182

182:                                              ; preds = %181, %156
  %183 = load ptr, ptr %7, align 8, !tbaa !5
  %184 = load i32, ptr %8, align 4, !tbaa !9
  %185 = load i32, ptr %12, align 4, !tbaa !9
  %186 = load i32, ptr %8, align 4, !tbaa !9
  %187 = load i32, ptr %9, align 4, !tbaa !9
  %188 = load i32, ptr %11, align 4, !tbaa !9
  %189 = mul i32 %187, %188
  %190 = mul i32 %189, 4
  %191 = zext i32 %190 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %183, i32 noundef 4097, i32 noundef %184, i32 noundef %185, i32 noundef %186, i64 noundef %191)
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %192

192:                                              ; preds = %200, %182
  %193 = load i32, ptr %13, align 4, !tbaa !9
  %194 = icmp ult i32 %193, 2
  br i1 %194, label %195, label %203

195:                                              ; preds = %192
  %196 = load ptr, ptr %7, align 8, !tbaa !5
  %197 = load i32, ptr %13, align 4, !tbaa !9
  %198 = add i32 12, %197
  %199 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %196, i32 noundef 1384120320, i32 noundef %198, i8 noundef zeroext 0, i32 noundef %199)
  br label %200

200:                                              ; preds = %195
  %201 = load i32, ptr %13, align 4, !tbaa !9
  %202 = add i32 %201, 1
  store i32 %202, ptr %13, align 4, !tbaa !9
  br label %192, !llvm.loop !18

203:                                              ; preds = %192
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %204

204:                                              ; preds = %211, %203
  %205 = load i32, ptr %13, align 4, !tbaa !9
  %206 = icmp ult i32 %205, 4
  br i1 %206, label %207, label %214

207:                                              ; preds = %204
  %208 = load ptr, ptr %7, align 8, !tbaa !5
  %209 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %208, i32 noundef -1064926208, i32 noundef 0, i32 noundef 12, i32 noundef %209)
  %210 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %210, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %211

211:                                              ; preds = %207
  %212 = load i32, ptr %13, align 4, !tbaa !9
  %213 = add i32 %212, 1
  store i32 %213, ptr %13, align 4, !tbaa !9
  br label %204, !llvm.loop !19

214:                                              ; preds = %204
  %215 = load i32, ptr %11, align 4, !tbaa !9
  %216 = icmp ugt i32 %215, 16
  br i1 %216, label %220, label %217

217:                                              ; preds = %214
  %218 = load i32, ptr %10, align 4, !tbaa !9
  %219 = icmp ugt i32 %218, 16
  br i1 %219, label %220, label %232

220:                                              ; preds = %217, %214
  store i32 4, ptr %13, align 4, !tbaa !9
  br label %221

221:                                              ; preds = %228, %220
  %222 = load i32, ptr %13, align 4, !tbaa !9
  %223 = icmp ult i32 %222, 8
  br i1 %223, label %224, label %231

224:                                              ; preds = %221
  %225 = load ptr, ptr %7, align 8, !tbaa !5
  %226 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %225, i32 noundef -1064926208, i32 noundef 1, i32 noundef 13, i32 noundef %226)
  %227 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %227, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %228

228:                                              ; preds = %224
  %229 = load i32, ptr %13, align 4, !tbaa !9
  %230 = add i32 %229, 1
  store i32 %230, ptr %13, align 4, !tbaa !9
  br label %221, !llvm.loop !20

231:                                              ; preds = %221
  br label %232

232:                                              ; preds = %231, %217
  %233 = load i32, ptr %11, align 4, !tbaa !9
  %234 = icmp ugt i32 %233, 16
  br i1 %234, label %235, label %243

235:                                              ; preds = %232
  %236 = load ptr, ptr %7, align 8, !tbaa !5
  %237 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %236, i32 noundef 0, i32 noundef -1, i32 noundef %237)
  %238 = load ptr, ptr %7, align 8, !tbaa !5
  %239 = load i32, ptr %11, align 4, !tbaa !9
  %240 = sub i32 %239, 16
  %241 = mul i32 %240, 4
  %242 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %238, i32 noundef 1, i32 noundef %241, i32 noundef %242)
  br label %248

243:                                              ; preds = %232
  %244 = load ptr, ptr %7, align 8, !tbaa !5
  %245 = load i32, ptr %11, align 4, !tbaa !9
  %246 = mul i32 %245, 4
  %247 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %244, i32 noundef 0, i32 noundef %246, i32 noundef %247)
  br label %248

248:                                              ; preds = %243, %235
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %249

249:                                              ; preds = %265, %248
  %250 = load i32, ptr %14, align 4, !tbaa !9
  %251 = load i32, ptr %15, align 4, !tbaa !9
  %252 = icmp ult i32 %250, %251
  br i1 %252, label %253, label %268

253:                                              ; preds = %249
  %254 = load ptr, ptr %7, align 8, !tbaa !5
  %255 = load i32, ptr %14, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %254, i32 noundef -448733050, i32 noundef 63, i32 noundef 127, i32 noundef 0, i32 noundef %255, i32 noundef 0)
  %256 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %256, i32 noundef 285212678, i32 noundef 63, i32 noundef 63, i32 noundef 64, i8 noundef zeroext 0)
  %257 = load i32, ptr %11, align 4, !tbaa !9
  %258 = icmp ugt i32 %257, 16
  br i1 %258, label %259, label %264

259:                                              ; preds = %253
  %260 = load ptr, ptr %7, align 8, !tbaa !5
  %261 = load i32, ptr %14, align 4, !tbaa !9
  %262 = add i32 %261, 16
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %260, i32 noundef -448733050, i32 noundef 63, i32 noundef 127, i32 noundef 0, i32 noundef %262, i32 noundef 1)
  %263 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %263, i32 noundef 285212678, i32 noundef 63, i32 noundef 63, i32 noundef 64, i8 noundef zeroext 0)
  br label %264

264:                                              ; preds = %259, %253
  br label %265

265:                                              ; preds = %264
  %266 = load i32, ptr %14, align 4, !tbaa !9
  %267 = add i32 %266, 1
  store i32 %267, ptr %14, align 4, !tbaa !9
  br label %249, !llvm.loop !21

268:                                              ; preds = %249
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}
!20 = distinct !{!20, !12}
!21 = distinct !{!21, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_transpose_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5) local_unnamed_addr #0 {
  tail call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %0, i32 noundef 1384120320, i32 noundef 12, i8 noundef zeroext 0, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %0, i32 noundef 1384120320, i32 noundef 13, i8 noundef zeroext 0, i32 noundef 1) #3
  %7 = icmp ugt i32 %4, 16
  %8 = icmp eq i32 %3, 0
  %9 = select i1 %8, i32 16, i32 %3
  %10 = select i1 %8, i32 32, i32 %3
  %.0 = select i1 %7, i32 %9, i32 %10
  %11 = shl nsw i32 %3, 2
  %12 = select i1 %8, i32 -1, i32 %11
  br i1 %7, label %.preheader119, label %.preheader121

.preheader121:                                    ; preds = %6
  tail call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %0, i32 noundef 8, i32 noundef %12, i32 noundef %5, i32 noundef 0)
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %.loopexit120, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader121
  %13 = shl i32 %2, 2
  %14 = zext i32 %13 to i64
  br label %19

.preheader119:                                    ; preds = %6
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef %12, i32 noundef %5)
  %15 = shl i32 %2, 2
  %16 = zext i32 %15 to i64
  br label %17

17:                                               ; preds = %.preheader119, %17
  %.1125 = phi i32 [ 0, %.preheader119 ], [ %18, %17 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -1522491258, i32 noundef %1, i32 noundef 127, i32 noundef 0, i32 noundef %.1125, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %16) #3
  %18 = add nuw i32 %.1125, 1
  %exitcond135.not = icmp eq i32 %18, %4
  br i1 %exitcond135.not, label %.loopexit120, label %17, !llvm.loop !5

19:                                               ; preds = %.lr.ph, %19
  %.2124 = phi i32 [ 0, %.lr.ph ], [ %23, %19 ]
  %20 = icmp ult i32 %.2124, 8
  %21 = add nuw nsw i32 %.2124, 8
  %22 = select i1 %20, i32 %.2124, i32 %21
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589624832, i32 noundef %22, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %14) #3
  %23 = add nuw i32 %.2124, 1
  %exitcond.not = icmp eq i32 %23, %4
  br i1 %exitcond.not, label %.loopexit120, label %19, !llvm.loop !7

.loopexit120:                                     ; preds = %19, %17, %.preheader121
  %24 = phi i32 [ 5, %.preheader121 ], [ 3, %17 ], [ 5, %19 ]
  %25 = phi i32 [ 4, %.preheader121 ], [ 2, %17 ], [ 4, %19 ]
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef %25) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef %24) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  br i1 %7, label %.loopexit.sink.split, label %26

26:                                               ; preds = %.loopexit120
  %27 = icmp ugt i32 %3, 16
  br i1 %27, label %.loopexit.sink.split, label %.loopexit

.loopexit.sink.split:                             ; preds = %26, %.loopexit120
  %.sink144 = phi i32 [ 4, %.loopexit120 ], [ 2, %26 ]
  %.sink = phi i32 [ 5, %.loopexit120 ], [ 3, %26 ]
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %.sink144) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %.sink) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.sink.split, %26
  %28 = shl i32 %2, 2
  %29 = mul i32 %28, %4
  %30 = zext i32 %29 to i64
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4097, i32 noundef %1, i32 noundef %5, i32 noundef %1, i64 noundef %30) #3
  tail call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %0, i32 noundef 1384120320, i32 noundef 12, i8 noundef zeroext 0, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_move_imm16(ptr noundef %0, i32 noundef 1384120320, i32 noundef 13, i8 noundef zeroext 0, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 0, i32 noundef 12, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 0, i32 noundef 12, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 0, i32 noundef 12, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  %31 = icmp ugt i32 %3, 16
  %or.cond3 = or i1 %31, %7
  br i1 %or.cond3, label %.preheader.preheader, label %.thread

.preheader.preheader:                             ; preds = %.loopexit
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 1, i32 noundef 13, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 1, i32 noundef 13, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 1, i32 noundef 13, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064926208, i32 noundef 1, i32 noundef 13, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  br i1 %7, label %32, label %.thread

32:                                               ; preds = %.preheader.preheader
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef -1, i32 noundef %5)
  %33 = shl i32 %4, 2
  %34 = add i32 %33, -64
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 1, i32 noundef %34, i32 noundef %5)
  br label %36

.thread:                                          ; preds = %.loopexit, %.preheader.preheader
  %35 = shl nuw nsw i32 %4, 2
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef %35, i32 noundef %5)
  br label %36

36:                                               ; preds = %.thread, %32
  %umax = tail call i32 @llvm.umax.i32(i32 %.0, i32 1)
  br label %37

37:                                               ; preds = %36, %40
  %.0108132 = phi i32 [ 0, %36 ], [ %41, %40 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef 63, i32 noundef 127, i32 noundef 0, i32 noundef %.0108132, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 63, i32 noundef 63, i32 noundef 64, i8 noundef zeroext 0) #3
  br i1 %7, label %38, label %40

38:                                               ; preds = %37
  %39 = add i32 %.0108132, 16
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef 63, i32 noundef 127, i32 noundef 0, i32 noundef %39, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 63, i32 noundef 63, i32 noundef 64, i8 noundef zeroext 0) #3
  br label %40

40:                                               ; preds = %37, %38
  %41 = add nuw i32 %.0108132, 1
  %exitcond141.not = icmp eq i32 %41, %umax
  br i1 %exitcond141.not, label %42, label %37, !llvm.loop !8

42:                                               ; preds = %40
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass