; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetGridSample)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::GridSample2dParam" = type { i64, i64, i64, i64, i64, i64, i32, i32, i32, i32 }

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base21SynetGridSample2dInitEmmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9) #0 personality ptr @__gxx_personality_v0 {
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i64, align 8
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca %"struct.Simd::GridSample2dParam", align 8
  %23 = alloca i32, align 4
  %24 = alloca ptr, align 8
  %25 = alloca i32, align 4
  store i64 %0, ptr %12, align 8, !tbaa !5
  store i64 %1, ptr %13, align 8, !tbaa !5
  store i64 %2, ptr %14, align 8, !tbaa !5
  store i64 %3, ptr %15, align 8, !tbaa !5
  store i64 %4, ptr %16, align 8, !tbaa !5
  store i64 %5, ptr %17, align 8, !tbaa !5
  store i32 %6, ptr %18, align 4, !tbaa !9
  store i32 %7, ptr %19, align 4, !tbaa !11
  store i32 %8, ptr %20, align 4, !tbaa !13
  store i32 %9, ptr %21, align 4, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 64, ptr %22) #6
  %26 = load i64, ptr %12, align 8, !tbaa !5
  %27 = load i64, ptr %13, align 8, !tbaa !5
  %28 = load i64, ptr %14, align 8, !tbaa !5
  %29 = load i64, ptr %15, align 8, !tbaa !5
  %30 = load i64, ptr %16, align 8, !tbaa !5
  %31 = load i64, ptr %17, align 8, !tbaa !5
  %32 = load i32, ptr %18, align 4, !tbaa !9
  %33 = load i32, ptr %19, align 4, !tbaa !11
  %34 = load i32, ptr %20, align 4, !tbaa !13
  %35 = load i32, ptr %21, align 4, !tbaa !15
  call void @_ZN4Simd17GridSample2dParamC2Emmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(ptr noundef nonnull align 8 dereferenceable(64) %22, i64 noundef %26, i64 noundef %27, i64 noundef %28, i64 noundef %29, i64 noundef %30, i64 noundef %31, i32 noundef %32, i32 noundef %33, i32 noundef %34, i32 noundef %35)
  %36 = call noundef zeroext i1 @_ZNK4Simd17GridSample2dParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64) %22)
  br i1 %36, label %38, label %37

37:                                               ; preds = %10
  store ptr null, ptr %11, align 8
  store i32 1, ptr %23, align 4
  br label %45

38:                                               ; preds = %10
  %39 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 80) #7
  invoke void @_ZN4Simd4Base20SynetGridSample2dRefC1ERKNS_17GridSample2dParamE(ptr noundef nonnull align 8 dereferenceable(80) %39, ptr noundef nonnull align 8 dereferenceable(64) %22)
          to label %40 unwind label %41

40:                                               ; preds = %38
  store ptr %39, ptr %11, align 8
  store i32 1, ptr %23, align 4
  br label %45

41:                                               ; preds = %38
  %42 = landingpad { ptr, i32 }
          cleanup
  %43 = extractvalue { ptr, i32 } %42, 0
  store ptr %43, ptr %24, align 8
  %44 = extractvalue { ptr, i32 } %42, 1
  store i32 %44, ptr %25, align 4
  call void @_ZdlPvm(ptr noundef %39, i64 noundef 80) #8
  call void @llvm.lifetime.end.p0(i64 64, ptr %22) #6
  br label %47

45:                                               ; preds = %40, %37
  call void @llvm.lifetime.end.p0(i64 64, ptr %22) #6
  %46 = load ptr, ptr %11, align 8
  ret ptr %46

47:                                               ; preds = %41
  %48 = load ptr, ptr %24, align 8
  %49 = load i32, ptr %25, align 4
  %50 = insertvalue { ptr, i32 } poison, ptr %48, 0
  %51 = insertvalue { ptr, i32 } %50, i32 %49, 1
  resume { ptr, i32 } %51
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd17GridSample2dParamC2Emmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(ptr noundef nonnull align 8 dereferenceable(64), i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd17GridSample2dParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64)) #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #3

declare void @_ZN4Simd4Base20SynetGridSample2dRefC1ERKNS_17GridSample2dParamE(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #4

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #5

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS24SimdGridSampleInterpType", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS25SimdGridSamplePaddingType", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"_ZTS8SimdBool", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::GridSample2dParam" = type { i64, i64, i64, i64, i64, i64, i32, i32, i32, i32 }

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base21SynetGridSample2dInitEmmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  %11 = alloca %"struct.Simd::GridSample2dParam", align 8
  call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %11) #6
  call void @_ZN4Simd17GridSample2dParamC2Emmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(ptr noundef nonnull align 8 dereferenceable(64) %11, i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9)
  %12 = call noundef zeroext i1 @_ZNK4Simd17GridSample2dParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64) %11)
  br i1 %12, label %13, label %17

13:                                               ; preds = %10
  %14 = call noalias noundef nonnull dereferenceable(80) ptr @_Znwm(i64 noundef 80) #7
  invoke void @_ZN4Simd4Base20SynetGridSample2dRefC1ERKNS_17GridSample2dParamE(ptr noundef nonnull align 8 dereferenceable(80) %14, ptr noundef nonnull align 8 dereferenceable(64) %11)
          to label %17 unwind label %15

15:                                               ; preds = %13
  %16 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %14, i64 noundef 80) #8
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %11) #6
  resume { ptr, i32 } %16

17:                                               ; preds = %13, %10
  %.0 = phi ptr [ null, %10 ], [ %14, %13 ]
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %11) #6
  ret ptr %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd17GridSample2dParamC2Emmmmmm18SimdTensorDataType24SimdGridSampleInterpType25SimdGridSamplePaddingType8SimdBool(ptr noundef nonnull align 8 dereferenceable(64), i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd17GridSample2dParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #3

declare void @_ZN4Simd4Base20SynetGridSample2dRefC1ERKNS_17GridSample2dParamE(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #4

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #5

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass