; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetPermute)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::PermuteParam" = type <{ %"class.std::vector", %"class.std::vector", i64, i64, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base16SynetPermuteInitEPKmS2_m18SimdTensorDataType(ptr noundef %0, ptr noundef %1, i64 noundef %2, i32 noundef %3) #2 personality ptr @__gxx_personality_v0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca %"struct.Simd::Base::PermuteParam", align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i64 %2, ptr %8, align 8, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 72, ptr %10) #7
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  %16 = load i64, ptr %8, align 8, !tbaa !9
  %17 = load i32, ptr %9, align 4, !tbaa !11
  call void @_ZN4Simd4Base12PermuteParamC2EPKmS3_m18SimdTensorDataTypem(ptr noundef nonnull align 8 dereferenceable(68) %10, ptr noundef %14, ptr noundef %15, i64 noundef %16, i32 noundef %17, i64 noundef 1)
  %18 = invoke noundef zeroext i1 @_ZNK4Simd4Base12PermuteParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(68) %10)
          to label %19 unwind label %21

19:                                               ; preds = %4
  br i1 %18, label %25, label %20

20:                                               ; preds = %19
  store ptr null, ptr %5, align 8
  store i32 1, ptr %13, align 4
  br label %33

21:                                               ; preds = %25, %4
  %22 = landingpad { ptr, i32 }
          cleanup
  %23 = extractvalue { ptr, i32 } %22, 0
  store ptr %23, ptr %11, align 8
  %24 = extractvalue { ptr, i32 } %22, 1
  store i32 %24, ptr %12, align 4
  br label %35

25:                                               ; preds = %19
  %26 = invoke noalias noundef nonnull ptr @_Znwm(i64 noundef 272) #8
          to label %27 unwind label %21

27:                                               ; preds = %25
  invoke void @_ZN4Simd4Base12SynetPermuteC1ERKNS0_12PermuteParamE(ptr noundef nonnull align 8 dereferenceable(272) %26, ptr noundef nonnull align 8 dereferenceable(68) %10)
          to label %28 unwind label %29

28:                                               ; preds = %27
  store ptr %26, ptr %5, align 8
  store i32 1, ptr %13, align 4
  br label %33

29:                                               ; preds = %27
  %30 = landingpad { ptr, i32 }
          cleanup
  %31 = extractvalue { ptr, i32 } %30, 0
  store ptr %31, ptr %11, align 8
  %32 = extractvalue { ptr, i32 } %30, 1
  store i32 %32, ptr %12, align 4
  call void @_ZdlPvm(ptr noundef %26, i64 noundef 272) #9
  br label %35

33:                                               ; preds = %28, %20
  call void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68) %10) #7
  call void @llvm.lifetime.end.p0(i64 72, ptr %10) #7
  %34 = load ptr, ptr %5, align 8
  ret ptr %34

35:                                               ; preds = %29, %21
  call void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68) %10) #7
  call void @llvm.lifetime.end.p0(i64 72, ptr %10) #7
  br label %36

36:                                               ; preds = %35
  %37 = load ptr, ptr %11, align 8
  %38 = load i32, ptr %12, align 4
  %39 = insertvalue { ptr, i32 } poison, ptr %37, 0
  %40 = insertvalue { ptr, i32 } %39, i32 %38, 1
  resume { ptr, i32 } %40
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd4Base12PermuteParamC2EPKmS3_m18SimdTensorDataTypem(ptr noundef nonnull align 8 dereferenceable(68), ptr noundef, ptr noundef, i64 noundef, i32 noundef, i64 noundef) unnamed_addr #3 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd4Base12PermuteParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(68)) #4 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #5

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #6

declare void @_ZN4Simd4Base12SynetPermuteC1ERKNS0_12PermuteParamE(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin allocsize(0) }
attributes #9 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::PermuteParam" = type <{ %"class.std::vector", %"class.std::vector", i64, i64, i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base16SynetPermuteInitEPKmS2_m18SimdTensorDataType(ptr noundef %0, ptr noundef %1, i64 noundef %2, i32 noundef %3) local_unnamed_addr #2 personality ptr @__gxx_personality_v0 {
  %5 = alloca %"struct.Simd::Base::PermuteParam", align 8
  call void @llvm.lifetime.start.p0(i64 72, ptr nonnull %5) #7
  call void @_ZN4Simd4Base12PermuteParamC2EPKmS3_m18SimdTensorDataTypem(ptr noundef nonnull align 8 dereferenceable(68) %5, ptr noundef %0, ptr noundef %1, i64 noundef %2, i32 noundef %3, i64 noundef 1)
  %6 = call noundef zeroext i1 @_ZNK4Simd4Base12PermuteParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(68) %5)
  br i1 %6, label %9, label %14

7:                                                ; preds = %9
  %8 = landingpad { ptr, i32 }
          cleanup
  br label %15

9:                                                ; preds = %4
  %10 = invoke noalias noundef nonnull dereferenceable(272) ptr @_Znwm(i64 noundef 272) #8
          to label %11 unwind label %7

11:                                               ; preds = %9
  invoke void @_ZN4Simd4Base12SynetPermuteC1ERKNS0_12PermuteParamE(ptr noundef nonnull align 8 dereferenceable(272) %10, ptr noundef nonnull align 8 dereferenceable(68) %5)
          to label %14 unwind label %12

12:                                               ; preds = %11
  %13 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %10, i64 noundef 272) #9
  br label %15

14:                                               ; preds = %11, %4
  %.07 = phi ptr [ null, %4 ], [ %10, %11 ]
  call void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68) %5) #7
  call void @llvm.lifetime.end.p0(i64 72, ptr nonnull %5) #7
  ret ptr %.07

15:                                               ; preds = %12, %7
  %.pn = phi { ptr, i32 } [ %13, %12 ], [ %8, %7 ]
  call void @_ZN4Simd4Base12PermuteParamD2Ev(ptr noundef nonnull align 8 dereferenceable(68) %5) #7
  call void @llvm.lifetime.end.p0(i64 72, ptr nonnull %5) #7
  resume { ptr, i32 } %.pn
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd4Base12PermuteParamC2EPKmS3_m18SimdTensorDataTypem(ptr noundef nonnull align 8 dereferenceable(68), ptr noundef, ptr noundef, i64 noundef, i32 noundef, i64 noundef) unnamed_addr #3 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd4Base12PermuteParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(68)) local_unnamed_addr #4 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #5

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #6

declare void @_ZN4Simd4Base12SynetPermuteC1ERKNS0_12PermuteParamE(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { builtin allocsize(0) }
attributes #9 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass