; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseDetection)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Detection::Data" = type { %"struct.Simd::Deletable", i8, i8, i8, i32, i32, i32, %"struct.Simd::Point", %"class.std::vector", %"class.std::vector.4", %"class.std::vector.9", %"class.std::vector.14", %"class.std::vector.19", %"class.std::vector.24", %"class.std::vector.29" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Point" = type { i64, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.9" = type { %"struct.std::_Vector_base.10" }
%"struct.std::_Vector_base.10" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.14" = type { %"struct.std::_Vector_base.15" }
%"struct.std::_Vector_base.15" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.24" = type { %"struct.std::_Vector_base.25" }
%"struct.std::_Vector_base.25" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.29" = type { %"struct.std::_Vector_base.30" }
%"struct.std::_Vector_base.30" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Simd4Base13DetectionInfoEPKvPmS3_P22SimdDetectionInfoFlags(ptr noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %10, ptr %9, align 8, !tbaa !5
  %11 = load ptr, ptr %9, align 8, !tbaa !5
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %54

13:                                               ; preds = %4
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %22

16:                                               ; preds = %13
  %17 = load ptr, ptr %9, align 8, !tbaa !5
  %18 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %17, i32 0, i32 7
  %19 = getelementptr inbounds %"struct.Simd::Point", ptr %18, i32 0, i32 0
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  store i64 %20, ptr %21, align 8, !tbaa !45
  br label %22

22:                                               ; preds = %16, %13
  %23 = load ptr, ptr %7, align 8, !tbaa !5
  %24 = icmp ne ptr %23, null
  br i1 %24, label %25, label %31

25:                                               ; preds = %22
  %26 = load ptr, ptr %9, align 8, !tbaa !5
  %27 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %26, i32 0, i32 7
  %28 = getelementptr inbounds %"struct.Simd::Point", ptr %27, i32 0, i32 1
  %29 = load i64, ptr %28, align 8, !tbaa !46
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 %29, ptr %30, align 8, !tbaa !45
  br label %31

31:                                               ; preds = %25, %22
  %32 = load ptr, ptr %8, align 8, !tbaa !5
  %33 = icmp ne ptr %32, null
  br i1 %33, label %34, label %53

34:                                               ; preds = %31
  %35 = load ptr, ptr %9, align 8, !tbaa !5
  %36 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %35, i32 0, i32 5
  %37 = load i32, ptr %36, align 8, !tbaa !47
  %38 = load ptr, ptr %9, align 8, !tbaa !5
  %39 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %38, i32 0, i32 2
  %40 = load i8, ptr %39, align 1, !tbaa !48, !range !49, !noundef !50
  %41 = trunc i8 %40 to i1
  %42 = zext i1 %41 to i64
  %43 = select i1 %41, i32 4, i32 0
  %44 = or i32 %37, %43
  %45 = load ptr, ptr %9, align 8, !tbaa !5
  %46 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %45, i32 0, i32 3
  %47 = load i8, ptr %46, align 2, !tbaa !51, !range !49, !noundef !50
  %48 = trunc i8 %47 to i1
  %49 = zext i1 %48 to i64
  %50 = select i1 %48, i32 8, i32 0
  %51 = or i32 %44, %50
  %52 = load ptr, ptr %8, align 8, !tbaa !5
  store i32 %51, ptr %52, align 4, !tbaa !52
  br label %53

53:                                               ; preds = %34, %31
  br label %54

54:                                               ; preds = %53, %4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !16, i64 24}
!10 = !{!"_ZTSN4Simd9Detection4DataE", !11, i64 0, !12, i64 8, !12, i64 9, !12, i64 10, !13, i64 12, !14, i64 16, !13, i64 20, !15, i64 24, !17, i64 40, !21, i64 64, !25, i64 88, !29, i64 112, !33, i64 136, !37, i64 160, !41, i64 184}
!11 = !{!"_ZTSN4Simd9DeletableE"}
!12 = !{!"bool", !7, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = !{!"_ZTS22SimdDetectionInfoFlags", !7, i64 0}
!15 = !{!"_ZTSN4Simd5PointIlEE", !16, i64 0, !16, i64 8}
!16 = !{!"long", !7, i64 0}
!17 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data5StageESaIS3_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data5DTreeESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data9DTreeNodeESaIS3_EE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!"_ZTSSt6vectorIfSaIfEE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIiSaIiEE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data11HaarFeatureESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data10LbpFeatureESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE12_Vector_implE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!45 = !{!16, !16, i64 0}
!46 = !{!10, !16, i64 32}
!47 = !{!10, !14, i64 16}
!48 = !{!10, !12, i64 9}
!49 = !{i8 0, i8 2}
!50 = !{}
!51 = !{!10, !12, i64 10}
!52 = !{!14, !14, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
define dso_local void @_ZN4Simd4Base13DetectionInfoEPKvPmS3_P22SimdDetectionInfoFlags(ptr noundef readonly %0, ptr noundef writeonly %1, ptr noundef writeonly %2, ptr noundef writeonly %3) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %27, label %5

5:                                                ; preds = %4
  %.not16 = icmp eq ptr %1, null
  br i1 %.not16, label %9, label %6

6:                                                ; preds = %5
  %7 = getelementptr inbounds i8, ptr %0, i64 24
  %8 = load i64, ptr %7, align 8, !tbaa !5
  store i64 %8, ptr %1, align 8, !tbaa !44
  br label %9

9:                                                ; preds = %6, %5
  %.not17 = icmp eq ptr %2, null
  br i1 %.not17, label %13, label %10

10:                                               ; preds = %9
  %11 = getelementptr inbounds i8, ptr %0, i64 32
  %12 = load i64, ptr %11, align 8, !tbaa !45
  store i64 %12, ptr %2, align 8, !tbaa !44
  br label %13

13:                                               ; preds = %10, %9
  %.not18 = icmp eq ptr %3, null
  br i1 %.not18, label %27, label %14

14:                                               ; preds = %13
  %15 = getelementptr inbounds i8, ptr %0, i64 16
  %16 = load i32, ptr %15, align 8, !tbaa !46
  %17 = getelementptr inbounds i8, ptr %0, i64 9
  %18 = load i8, ptr %17, align 1, !tbaa !47, !range !48, !noundef !49
  %19 = trunc nuw i8 %18 to i1
  %20 = select i1 %19, i32 4, i32 0
  %21 = or i32 %20, %16
  %22 = getelementptr inbounds i8, ptr %0, i64 10
  %23 = load i8, ptr %22, align 2, !tbaa !50, !range !48, !noundef !49
  %24 = trunc nuw i8 %23 to i1
  %25 = select i1 %24, i32 8, i32 0
  %26 = or i32 %21, %25
  store i32 %26, ptr %3, align 4, !tbaa !51
  br label %27

27:                                               ; preds = %13, %14, %4
  ret void
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 24}
!6 = !{!"_ZTSN4Simd9Detection4DataE", !7, i64 0, !8, i64 8, !8, i64 9, !8, i64 10, !11, i64 12, !12, i64 16, !11, i64 20, !13, i64 24, !15, i64 40, !20, i64 64, !24, i64 88, !28, i64 112, !32, i64 136, !36, i64 160, !40, i64 184}
!7 = !{!"_ZTSN4Simd9DeletableE"}
!8 = !{!"bool", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"_ZTS22SimdDetectionInfoFlags", !9, i64 0}
!13 = !{!"_ZTSN4Simd5PointIlEE", !14, i64 0, !14, i64 8}
!14 = !{!"long", !9, i64 0}
!15 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data5StageESaIS3_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5StageESaIS3_EE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!19 = !{!"any pointer", !9, i64 0}
!20 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data5DTreeESaIS3_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data5DTreeESaIS3_EE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!24 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data9DTreeNodeESaIS3_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data9DTreeNodeESaIS3_EE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!28 = !{!"_ZTSSt6vectorIfSaIfEE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!32 = !{!"_ZTSSt6vectorIiSaIiEE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!36 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data11HaarFeatureESaIS3_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data11HaarFeatureESaIS3_EE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!40 = !{!"_ZTSSt6vectorIN4Simd9Detection4Data10LbpFeatureESaIS3_EE", !41, i64 0}
!41 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE12_Vector_implE", !43, i64 0}
!43 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection4Data10LbpFeatureESaIS3_EE17_Vector_impl_dataE", !19, i64 0, !19, i64 8, !19, i64 16}
!44 = !{!14, !14, i64 0}
!45 = !{!6, !14, i64 32}
!46 = !{!6, !12, i64 16}
!47 = !{!6, !8, i64 9}
!48 = !{i8 0, i8 2}
!49 = !{}
!50 = !{!6, !8, i64 10}
!51 = !{!12, !12, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass