; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseDetection)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Rectangle" = type { i64, i64, i64, i64 }
%"struct.Simd::Detection::HidHaarCascade" = type { %"struct.Simd::Detection::HidBase", %"class.std::vector.41", %"class.std::vector.46", %"class.std::vector.51", %"class.std::vector.14", %"class.std::vector.56", float, float, [4 x ptr], [4 x ptr], %"struct.Simd::View", %"struct.Simd::View", %"struct.Simd::View", %"struct.Simd::View", %"struct.Simd::View" }
%"struct.Simd::Detection::HidBase" = type { %"struct.Simd::Deletable", i32, %"struct.Simd::Point", i8, i8, i8, i8, i32 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Point" = type { i64, i64 }
%"class.std::vector.41" = type { %"struct.std::_Vector_base.42" }
%"struct.std::_Vector_base.42" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarNode, std::allocator<Simd::Detection::HidHaarNode>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarNode, std::allocator<Simd::Detection::HidHaarNode>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarNode, std::allocator<Simd::Detection::HidHaarNode>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarNode, std::allocator<Simd::Detection::HidHaarNode>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.46" = type { %"struct.std::_Vector_base.47" }
%"struct.std::_Vector_base.47" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarCascade::Tree, std::allocator<Simd::Detection::HidHaarCascade::Tree>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarCascade::Tree, std::allocator<Simd::Detection::HidHaarCascade::Tree>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarCascade::Tree, std::allocator<Simd::Detection::HidHaarCascade::Tree>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarCascade::Tree, std::allocator<Simd::Detection::HidHaarCascade::Tree>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.51" = type { %"struct.std::_Vector_base.52" }
%"struct.std::_Vector_base.52" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarStage, std::allocator<Simd::Detection::HidHaarStage>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarStage, std::allocator<Simd::Detection::HidHaarStage>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarStage, std::allocator<Simd::Detection::HidHaarStage>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarStage, std::allocator<Simd::Detection::HidHaarStage>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.14" = type { %"struct.std::_Vector_base.15" }
%"struct.std::_Vector_base.15" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.56" = type { %"struct.std::_Vector_base.57" }
%"struct.std::_Vector_base.57" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarFeature, std::allocator<Simd::Detection::HidHaarFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarFeature, std::allocator<Simd::Detection::HidHaarFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidHaarFeature, std::allocator<Simd::Detection::HidHaarFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidHaarFeature, std::allocator<Simd::Detection::HidHaarFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::View" = type <{ i64, i64, i64, i32, [4 x i8], ptr, i8, [7 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd4Base9Detect32fERKNS_9Detection14HidHaarCascadeEmif(ptr noundef nonnull align 8 dereferenceable(472), i64 noundef, i32 noundef, float noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) #2 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef float @_ZN4Simd4Base7Norm32fERKNS_9Detection14HidHaarCascadeEm(ptr noundef nonnull align 8 dereferenceable(472), i64 noundef) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base23DetectionHaarDetect32fiERKNS_9Detection14HidHaarCascadeERKNS_4ViewINS_9AllocatorEEERKNS_9RectangleIlEERS7_(ptr noundef nonnull align 8 dereferenceable(472) %0, ptr noundef nonnull align 8 dereferenceable(41) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef nonnull align 8 dereferenceable(41) %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca float, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  %16 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %15, i32 0, i32 1
  %17 = load i64, ptr %16, align 8, !tbaa !9
  store i64 %17, ptr %9, align 8, !tbaa !12
  br label %18

18:                                               ; preds = %83, %4
  %19 = load i64, ptr %9, align 8, !tbaa !12
  %20 = load ptr, ptr %7, align 8, !tbaa !5
  %21 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %20, i32 0, i32 3
  %22 = load i64, ptr %21, align 8, !tbaa !13
  %23 = icmp slt i64 %19, %22
  br i1 %23, label %25, label %24

24:                                               ; preds = %18
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  br label %86

25:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %26 = load i64, ptr %9, align 8, !tbaa !12
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %"struct.Simd::Detection::HidHaarCascade", ptr %27, i32 0, i32 13
  %29 = getelementptr inbounds %"struct.Simd::View", ptr %28, i32 0, i32 2
  %30 = load i64, ptr %29, align 8, !tbaa !14
  %31 = mul nsw i64 %26, %30
  %32 = udiv i64 %31, 4
  store i64 %32, ptr %11, align 8, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %33 = load i64, ptr %9, align 8, !tbaa !12
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %"struct.Simd::Detection::HidHaarCascade", ptr %34, i32 0, i32 11
  %36 = getelementptr inbounds %"struct.Simd::View", ptr %35, i32 0, i32 2
  %37 = load i64, ptr %36, align 8, !tbaa !45
  %38 = mul nsw i64 %33, %37
  %39 = udiv i64 %38, 4
  store i64 %39, ptr %12, align 8, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %40 = load ptr, ptr %7, align 8, !tbaa !5
  %41 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %40, i32 0, i32 0
  %42 = load i64, ptr %41, align 8, !tbaa !46
  store i64 %42, ptr %13, align 8, !tbaa !12
  br label %43

43:                                               ; preds = %79, %25
  %44 = load i64, ptr %13, align 8, !tbaa !12
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %45, i32 0, i32 2
  %47 = load i64, ptr %46, align 8, !tbaa !47
  %48 = icmp slt i64 %44, %47
  br i1 %48, label %50, label %49

49:                                               ; preds = %43
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %82

50:                                               ; preds = %43
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = load i64, ptr %13, align 8, !tbaa !12
  %53 = load i64, ptr %9, align 8, !tbaa !12
  %54 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41) %51, i64 noundef %52, i64 noundef %53)
  %55 = load i8, ptr %54, align 1, !tbaa !48
  %56 = zext i8 %55 to i32
  %57 = icmp eq i32 %56, 0
  br i1 %57, label %58, label %59

58:                                               ; preds = %50
  br label %79

59:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = load i64, ptr %12, align 8, !tbaa !12
  %62 = load i64, ptr %13, align 8, !tbaa !12
  %63 = add i64 %61, %62
  %64 = call noundef float @_ZN4Simd4Base7Norm32fERKNS_9Detection14HidHaarCascadeEm(ptr noundef nonnull align 8 dereferenceable(472) %60, i64 noundef %63)
  store float %64, ptr %14, align 4, !tbaa !49
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  %66 = load i64, ptr %11, align 8, !tbaa !12
  %67 = load i64, ptr %13, align 8, !tbaa !12
  %68 = sdiv i64 %67, 2
  %69 = add i64 %66, %68
  %70 = load float, ptr %14, align 4, !tbaa !49
  %71 = call noundef i32 @_ZN4Simd4Base9Detect32fERKNS_9Detection14HidHaarCascadeEmif(ptr noundef nonnull align 8 dereferenceable(472) %65, i64 noundef %69, i32 noundef 0, float noundef %70)
  %72 = icmp sgt i32 %71, 0
  br i1 %72, label %73, label %78

73:                                               ; preds = %59
  %74 = load ptr, ptr %8, align 8, !tbaa !5
  %75 = load i64, ptr %13, align 8, !tbaa !12
  %76 = load i64, ptr %9, align 8, !tbaa !12
  %77 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41) %74, i64 noundef %75, i64 noundef %76)
  store i8 1, ptr %77, align 1, !tbaa !48
  br label %78

78:                                               ; preds = %73, %59
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  br label %79

79:                                               ; preds = %78, %58
  %80 = load i64, ptr %13, align 8, !tbaa !12
  %81 = add nsw i64 %80, 2
  store i64 %81, ptr %13, align 8, !tbaa !12
  br label %43, !llvm.loop !50

82:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  br label %83

83:                                               ; preds = %82
  %84 = load i64, ptr %9, align 8, !tbaa !12
  %85 = add nsw i64 %84, 2
  store i64 %85, ptr %9, align 8, !tbaa !12
  br label %18, !llvm.loop !52

86:                                               ; preds = %24
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 8}
!10 = !{!"_ZTSN4Simd9RectangleIlEE", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24}
!11 = !{!"long", !7, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!10, !11, i64 24}
!14 = !{!15, !11, i64 392}
!15 = !{!"_ZTSN4Simd9Detection14HidHaarCascadeE", !16, i64 0, !22, i64 40, !26, i64 64, !30, i64 88, !34, i64 112, !38, i64 136, !42, i64 160, !42, i64 164, !7, i64 168, !7, i64 200, !43, i64 232, !43, i64 280, !43, i64 328, !43, i64 376, !43, i64 424}
!16 = !{!"_ZTSN4Simd9Detection7HidBaseE", !17, i64 0, !18, i64 8, !19, i64 16, !20, i64 32, !20, i64 33, !20, i64 34, !20, i64 35, !21, i64 36}
!17 = !{!"_ZTSN4Simd9DeletableE"}
!18 = !{!"_ZTS22SimdDetectionInfoFlags", !7, i64 0}
!19 = !{!"_ZTSN4Simd5PointIlEE", !11, i64 0, !11, i64 8}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"int", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIN4Simd9Detection11HidHaarNodeESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIN4Simd9Detection12HidHaarStageESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIfSaIfEE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSSt6vectorIN4Simd9Detection14HidHaarFeatureESaIS2_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"float", !7, i64 0}
!43 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEEE", !11, i64 0, !11, i64 8, !11, i64 16, !44, i64 24, !6, i64 32, !20, i64 40}
!44 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEE6FormatE", !7, i64 0}
!45 = !{!15, !11, i64 296}
!46 = !{!10, !11, i64 0}
!47 = !{!10, !11, i64 16}
!48 = !{!7, !7, i64 0}
!49 = !{!42, !42, i64 0}
!50 = distinct !{!50, !51}
!51 = !{!"llvm.loop.mustprogress"}
!52 = distinct !{!52, !51}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd4Base9Detect32fERKNS_9Detection14HidHaarCascadeEmif(ptr noundef nonnull align 8 dereferenceable(472), i64 noundef, i32 noundef, float noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef float @_ZN4Simd4Base7Norm32fERKNS_9Detection14HidHaarCascadeEm(ptr noundef nonnull align 8 dereferenceable(472), i64 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base23DetectionHaarDetect32fiERKNS_9Detection14HidHaarCascadeERKNS_4ViewINS_9AllocatorEEERKNS_9RectangleIlEERS7_(ptr noundef nonnull align 8 dereferenceable(472) %0, ptr noundef nonnull align 8 dereferenceable(41) %1, ptr nocapture noundef nonnull readonly align 8 dereferenceable(32) %2, ptr noundef nonnull align 8 dereferenceable(41) %3) local_unnamed_addr #0 {
  %5 = getelementptr inbounds i8, ptr %2, i64 8
  %6 = load i64, ptr %5, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %2, i64 24
  %8 = load i64, ptr %7, align 8, !tbaa !10
  %9 = icmp slt i64 %6, %8
  br i1 %9, label %.lr.ph28, label %._crit_edge29

.lr.ph28:                                         ; preds = %4
  %10 = getelementptr inbounds i8, ptr %0, i64 392
  %11 = getelementptr inbounds i8, ptr %0, i64 296
  %12 = getelementptr inbounds i8, ptr %2, i64 16
  %13 = load i64, ptr %2, align 8, !tbaa !11
  %14 = load i64, ptr %12, align 8, !tbaa !12
  %15 = icmp slt i64 %13, %14
  br i1 %15, label %.lr.ph28.split, label %._crit_edge29

._crit_edge29:                                    ; preds = %._crit_edge, %.lr.ph28, %4
  ret void

.lr.ph28.split:                                   ; preds = %.lr.ph28, %._crit_edge
  %16 = phi i64 [ %26, %._crit_edge ], [ %8, %.lr.ph28 ]
  %17 = phi i64 [ %27, %._crit_edge ], [ %14, %.lr.ph28 ]
  %.026 = phi i64 [ %28, %._crit_edge ], [ %6, %.lr.ph28 ]
  %18 = load i64, ptr %10, align 8, !tbaa !13
  %19 = mul nsw i64 %18, %.026
  %20 = lshr i64 %19, 2
  %21 = load i64, ptr %11, align 8, !tbaa !45
  %22 = mul nsw i64 %21, %.026
  %23 = lshr i64 %22, 2
  %24 = load i64, ptr %2, align 8, !tbaa !11
  %25 = icmp slt i64 %24, %17
  br i1 %25, label %.lr.ph, label %._crit_edge

._crit_edge.loopexit:                             ; preds = %42
  %.pre = load i64, ptr %7, align 8, !tbaa !10
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.lr.ph28.split
  %26 = phi i64 [ %.pre, %._crit_edge.loopexit ], [ %16, %.lr.ph28.split ]
  %27 = phi i64 [ %44, %._crit_edge.loopexit ], [ %17, %.lr.ph28.split ]
  %28 = add nsw i64 %.026, 2
  %29 = icmp slt i64 %28, %26
  br i1 %29, label %.lr.ph28.split, label %._crit_edge29, !llvm.loop !46

.lr.ph:                                           ; preds = %.lr.ph28.split, %42
  %.02425 = phi i64 [ %43, %42 ], [ %24, %.lr.ph28.split ]
  %30 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41) %1, i64 noundef %.02425, i64 noundef %.026)
  %31 = load i8, ptr %30, align 1, !tbaa !49
  %32 = icmp eq i8 %31, 0
  br i1 %32, label %42, label %33

33:                                               ; preds = %.lr.ph
  %34 = add i64 %.02425, %23
  %35 = tail call noundef float @_ZN4Simd4Base7Norm32fERKNS_9Detection14HidHaarCascadeEm(ptr noundef nonnull align 8 dereferenceable(472) %0, i64 noundef %34)
  %36 = sdiv i64 %.02425, 2
  %37 = add nsw i64 %36, %20
  %38 = tail call noundef i32 @_ZN4Simd4Base9Detect32fERKNS_9Detection14HidHaarCascadeEmif(ptr noundef nonnull align 8 dereferenceable(472) %0, i64 noundef %37, i32 noundef 0, float noundef %35)
  %39 = icmp sgt i32 %38, 0
  br i1 %39, label %40, label %42

40:                                               ; preds = %33
  %41 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41) %3, i64 noundef %.02425, i64 noundef %.026)
  store i8 1, ptr %41, align 1, !tbaa !49
  br label %42

42:                                               ; preds = %33, %40, %.lr.ph
  %43 = add nsw i64 %.02425, 2
  %44 = load i64, ptr %12, align 8, !tbaa !12
  %45 = icmp slt i64 %43, %44
  br i1 %45, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !50
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTSN4Simd9RectangleIlEE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!6, !7, i64 24}
!11 = !{!6, !7, i64 0}
!12 = !{!6, !7, i64 16}
!13 = !{!14, !7, i64 392}
!14 = !{!"_ZTSN4Simd9Detection14HidHaarCascadeE", !15, i64 0, !21, i64 40, !26, i64 64, !30, i64 88, !34, i64 112, !38, i64 136, !42, i64 160, !42, i64 164, !8, i64 168, !8, i64 200, !43, i64 232, !43, i64 280, !43, i64 328, !43, i64 376, !43, i64 424}
!15 = !{!"_ZTSN4Simd9Detection7HidBaseE", !16, i64 0, !17, i64 8, !18, i64 16, !19, i64 32, !19, i64 33, !19, i64 34, !19, i64 35, !20, i64 36}
!16 = !{!"_ZTSN4Simd9DeletableE"}
!17 = !{!"_ZTS22SimdDetectionInfoFlags", !8, i64 0}
!18 = !{!"_ZTSN4Simd5PointIlEE", !7, i64 0, !7, i64 8}
!19 = !{!"bool", !8, i64 0}
!20 = !{!"int", !8, i64 0}
!21 = !{!"_ZTSSt6vectorIN4Simd9Detection11HidHaarNodeESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidHaarNodeESaIS2_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!25 = !{!"any pointer", !8, i64 0}
!26 = !{!"_ZTSSt6vectorIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarCascade4TreeESaIS3_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!30 = !{!"_ZTSSt6vectorIN4Simd9Detection12HidHaarStageESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection12HidHaarStageESaIS2_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!34 = !{!"_ZTSSt6vectorIfSaIfEE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!38 = !{!"_ZTSSt6vectorIN4Simd9Detection14HidHaarFeatureESaIS2_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection14HidHaarFeatureESaIS2_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!42 = !{!"float", !8, i64 0}
!43 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEEE", !7, i64 0, !7, i64 8, !7, i64 16, !44, i64 24, !25, i64 32, !19, i64 40}
!44 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEE6FormatE", !8, i64 0}
!45 = !{!14, !7, i64 296}
!46 = distinct !{!46, !47, !48}
!47 = !{!"llvm.loop.mustprogress"}
!48 = !{!"llvm.loop.unswitch.partial.disable"}
!49 = !{!8, !8, i64 0}
!50 = distinct !{!50, !47}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass