; LLVM IR from libxsmm/libxsmm :: src (generator_gemm_sme_microkernel)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.libxsmm_gp_reg_mapping_struct = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.libxsmm_gemm_descriptor = type <{ i32, i32, i32, i32, i32, i32, i32, i8, [3 x i8], i8, i64, i64, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, i32, i32, i32, i8 }>

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_aarch64_microkernel_sme_16x64(ptr noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, i32 noundef %4, i32 noundef %5) #1 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !9
  store i32 %5, ptr %12, align 4, !tbaa !9
  %13 = load ptr, ptr %7, align 8, !tbaa !5
  %14 = load ptr, ptr %8, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %14, i32 0, i32 1
  %16 = load i32, ptr %15, align 4, !tbaa !11
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %13, i32 noundef -1522491258, i32 noundef %16, i32 noundef 0, i32 noundef 0, i32 noundef 4, i32 noundef 4)
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  %18 = load ptr, ptr %10, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.libxsmm_gemm_descriptor, ptr %18, i32 0, i32 6
  %20 = load i32, ptr %19, align 1, !tbaa !13
  %21 = and i32 %20, 2
  %22 = icmp ugt i32 %21, 0
  br i1 %22, label %23, label %27

23:                                               ; preds = %6
  %24 = load ptr, ptr %8, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %24, i32 0, i32 3
  %26 = load i32, ptr %25, align 4, !tbaa !17
  br label %31

27:                                               ; preds = %6
  %28 = load ptr, ptr %8, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %28, i32 0, i32 13
  %30 = load i32, ptr %29, align 4, !tbaa !18
  br label %31

31:                                               ; preds = %27, %23
  %32 = phi i32 [ %26, %23 ], [ %30, %27 ]
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %17, i32 noundef -1606369280, i32 noundef 0, i32 noundef %32, i32 noundef 0, i32 noundef 8)
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = load ptr, ptr %8, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %34, i32 0, i32 1
  %36 = load i32, ptr %35, align 4, !tbaa !11
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %37, i32 0, i32 22
  %39 = load i32, ptr %38, align 4, !tbaa !19
  %40 = load ptr, ptr %8, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %40, i32 0, i32 1
  %42 = load i32, ptr %41, align 4, !tbaa !11
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %33, i32 noundef 184549383, i32 noundef %36, i32 noundef %39, i32 noundef %42, i32 noundef 0, i32 noundef 0)
  %43 = load ptr, ptr %7, align 8, !tbaa !5
  %44 = load ptr, ptr %10, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.libxsmm_gemm_descriptor, ptr %44, i32 0, i32 6
  %46 = load i32, ptr %45, align 1, !tbaa !13
  %47 = and i32 %46, 2
  %48 = icmp ugt i32 %47, 0
  br i1 %48, label %49, label %53

49:                                               ; preds = %31
  %50 = load ptr, ptr %8, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %50, i32 0, i32 3
  %52 = load i32, ptr %51, align 4, !tbaa !17
  br label %57

53:                                               ; preds = %31
  %54 = load ptr, ptr %8, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %54, i32 0, i32 13
  %56 = load i32, ptr %55, align 4, !tbaa !18
  br label %57

57:                                               ; preds = %53, %49
  %58 = phi i32 [ %52, %49 ], [ %56, %53 ]
  %59 = load ptr, ptr %8, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %59, i32 0, i32 23
  %61 = load i32, ptr %60, align 4, !tbaa !20
  %62 = load ptr, ptr %10, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.libxsmm_gemm_descriptor, ptr %62, i32 0, i32 6
  %64 = load i32, ptr %63, align 1, !tbaa !13
  %65 = and i32 %64, 2
  %66 = icmp ugt i32 %65, 0
  br i1 %66, label %67, label %71

67:                                               ; preds = %57
  %68 = load ptr, ptr %8, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %68, i32 0, i32 3
  %70 = load i32, ptr %69, align 4, !tbaa !17
  br label %75

71:                                               ; preds = %57
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.libxsmm_gp_reg_mapping_struct, ptr %72, i32 0, i32 13
  %74 = load i32, ptr %73, align 4, !tbaa !18
  br label %75

75:                                               ; preds = %71, %67
  %76 = phi i32 [ %70, %67 ], [ %74, %71 ]
  call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %43, i32 noundef 184549383, i32 noundef %58, i32 noundef %61, i32 noundef %76, i32 noundef 0, i32 noundef 0)
  %77 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %77, i32 noundef -2139095040, i32 noundef 0, i32 noundef 0, i32 noundef 4, i32 noundef 0, i32 noundef 4)
  %78 = load i32, ptr %12, align 4, !tbaa !9
  %79 = icmp ugt i32 %78, 16
  br i1 %79, label %80, label %82

80:                                               ; preds = %75
  %81 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %81, i32 noundef -2139095040, i32 noundef 1, i32 noundef 1, i32 noundef 4, i32 noundef 1, i32 noundef 4)
  br label %82

82:                                               ; preds = %80, %75
  %83 = load i32, ptr %12, align 4, !tbaa !9
  %84 = icmp ugt i32 %83, 32
  br i1 %84, label %85, label %87

85:                                               ; preds = %82
  %86 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %86, i32 noundef -2139095040, i32 noundef 2, i32 noundef 2, i32 noundef 4, i32 noundef 2, i32 noundef 4)
  br label %87

87:                                               ; preds = %85, %82
  %88 = load i32, ptr %12, align 4, !tbaa !9
  %89 = icmp ugt i32 %88, 48
  br i1 %89, label %90, label %92

90:                                               ; preds = %87
  %91 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %91, i32 noundef -2139095040, i32 noundef 3, i32 noundef 3, i32 noundef 4, i32 noundef 3, i32 noundef 4)
  br label %92

92:                                               ; preds = %90, %87
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"libxsmm_gp_reg_mapping_struct", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92, !10, i64 96, !10, i64 100, !10, i64 104, !10, i64 108, !10, i64 112, !10, i64 116, !10, i64 120, !10, i64 124, !10, i64 128}
!13 = !{!14, !10, i64 24}
!14 = !{!"libxsmm_gemm_descriptor", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !7, i64 28, !7, i64 29, !7, i64 32, !15, i64 33, !15, i64 41, !7, i64 49, !10, i64 50, !10, i64 54, !10, i64 58, !16, i64 62, !16, i64 64, !7, i64 66, !7, i64 67, !7, i64 68, !7, i64 69, !16, i64 70, !16, i64 72, !16, i64 74, !16, i64 76, !16, i64 78, !16, i64 80, !10, i64 82, !10, i64 86, !10, i64 90, !7, i64 94}
!15 = !{!"long long", !7, i64 0}
!16 = !{!"short", !7, i64 0}
!17 = !{!12, !10, i64 12}
!18 = !{!12, !10, i64 52}
!19 = !{!12, !10, i64 88}
!20 = !{!12, !10, i64 92}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_aarch64_microkernel_sme_16x64(ptr noundef %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readnone %2, ptr nocapture noundef readonly %3, i32 noundef %4, i32 noundef %5) local_unnamed_addr #1 {
  %7 = getelementptr inbounds i8, ptr %1, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -1522491258, i32 noundef %8, i32 noundef 0, i32 noundef 0, i32 noundef 4, i32 noundef 4) #2
  %9 = getelementptr inbounds i8, ptr %3, i64 24
  %10 = load i32, ptr %9, align 1, !tbaa !10
  %11 = and i32 %10, 2
  %.not = icmp eq i32 %11, 0
  %12 = getelementptr inbounds i8, ptr %1, i64 12
  %13 = getelementptr inbounds i8, ptr %1, i64 52
  %.in = select i1 %.not, ptr %13, ptr %12
  %14 = load i32, ptr %.in, align 4, !tbaa !14
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1606369280, i32 noundef 0, i32 noundef %14, i32 noundef 0, i32 noundef 8) #2
  %15 = load i32, ptr %7, align 4, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %1, i64 88
  %17 = load i32, ptr %16, align 4, !tbaa !15
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %0, i32 noundef 184549383, i32 noundef %15, i32 noundef %17, i32 noundef %15, i32 noundef 0, i32 noundef 0) #2
  %18 = load i32, ptr %9, align 1, !tbaa !10
  %19 = and i32 %18, 2
  %.not24 = icmp eq i32 %19, 0
  %.in25 = select i1 %.not24, ptr %13, ptr %12
  %20 = load i32, ptr %.in25, align 4, !tbaa !14
  %21 = getelementptr inbounds i8, ptr %1, i64 92
  %22 = load i32, ptr %21, align 4, !tbaa !16
  tail call void @libxsmm_aarch64_instruction_alu_compute_shifted_reg(ptr noundef %0, i32 noundef 184549383, i32 noundef %20, i32 noundef %22, i32 noundef %20, i32 noundef 0, i32 noundef 0) #2
  tail call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %0, i32 noundef -2139095040, i32 noundef 0, i32 noundef 0, i32 noundef 4, i32 noundef 0, i32 noundef 4) #2
  %23 = icmp ugt i32 %5, 16
  br i1 %23, label %24, label %.thread28

24:                                               ; preds = %6
  tail call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %0, i32 noundef -2139095040, i32 noundef 1, i32 noundef 1, i32 noundef 4, i32 noundef 1, i32 noundef 4) #2
  %25 = icmp ugt i32 %5, 32
  br i1 %25, label %26, label %.thread28

26:                                               ; preds = %24
  tail call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %0, i32 noundef -2139095040, i32 noundef 2, i32 noundef 2, i32 noundef 4, i32 noundef 2, i32 noundef 4) #2
  %27 = icmp ugt i32 %5, 48
  br i1 %27, label %28, label %.thread28

28:                                               ; preds = %26
  tail call void @libxsmm_aarch64_instruction_sme_compute(ptr noundef %0, i32 noundef -2139095040, i32 noundef 3, i32 noundef 3, i32 noundef 4, i32 noundef 3, i32 noundef 4) #2
  br label %.thread28

.thread28:                                        ; preds = %6, %24, %28, %26
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"libxsmm_gp_reg_mapping_struct", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !7, i64 48, !7, i64 52, !7, i64 56, !7, i64 60, !7, i64 64, !7, i64 68, !7, i64 72, !7, i64 76, !7, i64 80, !7, i64 84, !7, i64 88, !7, i64 92, !7, i64 96, !7, i64 100, !7, i64 104, !7, i64 108, !7, i64 112, !7, i64 116, !7, i64 120, !7, i64 124, !7, i64 128}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!11, !7, i64 24}
!11 = !{!"libxsmm_gemm_descriptor", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !8, i64 28, !8, i64 29, !8, i64 32, !12, i64 33, !12, i64 41, !8, i64 49, !7, i64 50, !7, i64 54, !7, i64 58, !13, i64 62, !13, i64 64, !8, i64 66, !8, i64 67, !8, i64 68, !8, i64 69, !13, i64 70, !13, i64 72, !13, i64 74, !13, i64 76, !13, i64 78, !13, i64 80, !7, i64 82, !7, i64 86, !7, i64 90, !8, i64 94}
!12 = !{!"long long", !8, i64 0}
!13 = !{!"short", !8, i64 0}
!14 = !{!7, !7, i64 0}
!15 = !{!6, !7, i64 88}
!16 = !{!6, !7, i64 92}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass