; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local void @test_mask_compute_reg(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i16, align 2
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i16 %4, ptr %10, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %12 = load ptr, ptr %7, align 8, !tbaa !5
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %12, ptr noundef %13)
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %14

14:                                               ; preds = %33, %5
  %15 = load i32, ptr %11, align 4, !tbaa !9
  %16 = icmp ult i32 %15, 8
  br i1 %16, label %17, label %36

17:                                               ; preds = %14
  %18 = load i32, ptr %9, align 4, !tbaa !9
  %19 = icmp ne i32 %18, 0
  br i1 %19, label %20, label %26

20:                                               ; preds = %17
  %21 = load ptr, ptr %7, align 8, !tbaa !5
  %22 = load i32, ptr %8, align 4, !tbaa !9
  %23 = load i32, ptr %11, align 4, !tbaa !9
  %24 = load i16, ptr %10, align 2, !tbaa !11
  %25 = zext i16 %24 to i32
  call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %21, i32 noundef %22, i32 noundef %23, i32 noundef 255, i32 noundef 0, i32 noundef %25)
  br label %32

26:                                               ; preds = %17
  %27 = load ptr, ptr %7, align 8, !tbaa !5
  %28 = load i32, ptr %8, align 4, !tbaa !9
  %29 = load i32, ptr %11, align 4, !tbaa !9
  %30 = load i16, ptr %10, align 2, !tbaa !11
  %31 = zext i16 %30 to i32
  call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %27, i32 noundef %28, i32 noundef %29, i32 noundef 0, i32 noundef 0, i32 noundef %31)
  br label %32

32:                                               ; preds = %26, %20
  br label %33

33:                                               ; preds = %32
  %34 = load i32, ptr %11, align 4, !tbaa !9
  %35 = add i32 %34, 1
  store i32 %35, ptr %11, align 4, !tbaa !9
  br label %14, !llvm.loop !13

36:                                               ; preds = %14
  %37 = load i32, ptr %9, align 4, !tbaa !9
  %38 = icmp ne i32 %37, 0
  br i1 %38, label %53, label %39

39:                                               ; preds = %36
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %40

40:                                               ; preds = %49, %39
  %41 = load i32, ptr %11, align 4, !tbaa !9
  %42 = icmp ult i32 %41, 8
  br i1 %42, label %43, label %52

43:                                               ; preds = %40
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = load i32, ptr %8, align 4, !tbaa !9
  %46 = load i32, ptr %11, align 4, !tbaa !9
  %47 = load i16, ptr %10, align 2, !tbaa !11
  %48 = zext i16 %47 to i32
  call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %44, i32 noundef %45, i32 noundef 0, i32 noundef %46, i32 noundef 0, i32 noundef %48)
  br label %49

49:                                               ; preds = %43
  %50 = load i32, ptr %11, align 4, !tbaa !9
  %51 = add i32 %50, 1
  store i32 %51, ptr %11, align 4, !tbaa !9
  br label %40, !llvm.loop !15

52:                                               ; preds = %40
  br label %53

53:                                               ; preds = %52, %36
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %54

54:                                               ; preds = %73, %53
  %55 = load i32, ptr %11, align 4, !tbaa !9
  %56 = icmp ult i32 %55, 8
  br i1 %56, label %57, label %76

57:                                               ; preds = %54
  %58 = load i32, ptr %9, align 4, !tbaa !9
  %59 = icmp ne i32 %58, 0
  br i1 %59, label %60, label %66

60:                                               ; preds = %57
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = load i32, ptr %8, align 4, !tbaa !9
  %63 = load i32, ptr %11, align 4, !tbaa !9
  %64 = load i16, ptr %10, align 2, !tbaa !11
  %65 = zext i16 %64 to i32
  call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %61, i32 noundef %62, i32 noundef 0, i32 noundef 255, i32 noundef %63, i32 noundef %65)
  br label %72

66:                                               ; preds = %57
  %67 = load ptr, ptr %7, align 8, !tbaa !5
  %68 = load i32, ptr %8, align 4, !tbaa !9
  %69 = load i32, ptr %11, align 4, !tbaa !9
  %70 = load i16, ptr %10, align 2, !tbaa !11
  %71 = zext i16 %70 to i32
  call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %67, i32 noundef %68, i32 noundef 0, i32 noundef 0, i32 noundef %69, i32 noundef %71)
  br label %72

72:                                               ; preds = %66, %60
  br label %73

73:                                               ; preds = %72
  %74 = load i32, ptr %11, align 4, !tbaa !9
  %75 = add i32 %74, 1
  store i32 %75, ptr %11, align 4, !tbaa !9
  br label %54, !llvm.loop !16

76:                                               ; preds = %54
  %77 = load ptr, ptr %7, align 8, !tbaa !5
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %77, ptr noundef %78)
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

declare void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @test_mask_compute_reg(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4) local_unnamed_addr #0 {
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %.not32 = icmp eq i32 %3, 0
  %6 = zext i16 %4 to i32
  br i1 %.not32, label %.split38.us.preheader, label %.split38.preheader

.split38.preheader:                               ; preds = %5
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 1, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 2, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 3, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 4, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 5, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 6, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 7, i32 noundef 255, i32 noundef 0, i32 noundef %6) #2
  br label %.split40.us

.split38.us.preheader:                            ; preds = %5
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 1, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 2, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 3, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 4, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 5, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 6, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 7, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 1, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 2, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 3, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 4, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 5, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 6, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef 7, i32 noundef 0, i32 noundef %6) #2
  br label %.split40.us

.split40.us:                                      ; preds = %.split38.preheader, %.split38.us.preheader
  %.sink49 = phi i32 [ 255, %.split38.preheader ], [ 0, %.split38.us.preheader ]
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 0, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 1, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 2, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 3, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 4, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 5, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 6, i32 noundef %6) #2
  tail call void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef %1, i32 noundef %2, i32 noundef 0, i32 noundef %.sink49, i32 noundef 7, i32 noundef %6) #2
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

declare void @libxsmm_x86_instruction_mask_compute_reg(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass