; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetAdd16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Add16bParam" = type { %"class.std::vector", %"class.std::vector", i32, i32, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base18SynetAdd16bUniform10PreferableERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(64)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base15SynetAdd16bInitEPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef %0, i64 noundef %1, i32 noundef %2, ptr noundef %3, i64 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) #1 personality ptr @__gxx_personality_v0 {
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca i64, align 8
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca %"struct.Simd::Add16bParam", align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  store ptr %0, ptr %10, align 8, !tbaa !5
  store i64 %1, ptr %11, align 8, !tbaa !9
  store i32 %2, ptr %12, align 4, !tbaa !11
  store ptr %3, ptr %13, align 8, !tbaa !5
  store i64 %4, ptr %14, align 8, !tbaa !9
  store i32 %5, ptr %15, align 4, !tbaa !11
  store i32 %6, ptr %16, align 4, !tbaa !11
  store i32 %7, ptr %17, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 64, ptr %18) #6
  %22 = load ptr, ptr %10, align 8, !tbaa !5
  %23 = load i64, ptr %11, align 8, !tbaa !9
  %24 = load i32, ptr %12, align 4, !tbaa !11
  %25 = load ptr, ptr %13, align 8, !tbaa !5
  %26 = load i64, ptr %14, align 8, !tbaa !9
  %27 = load i32, ptr %15, align 4, !tbaa !11
  %28 = load i32, ptr %16, align 4, !tbaa !11
  %29 = load i32, ptr %17, align 4, !tbaa !13
  call void @_ZN4Simd11Add16bParamC2EPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef nonnull align 8 dereferenceable(64) %18, ptr noundef %22, i64 noundef %23, i32 noundef %24, ptr noundef %25, i64 noundef %26, i32 noundef %27, i32 noundef %28, i32 noundef %29)
  %30 = invoke noundef zeroext i1 @_ZN4Simd11Add16bParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64) %18)
          to label %31 unwind label %33

31:                                               ; preds = %8
  br i1 %30, label %37, label %32

32:                                               ; preds = %31
  store ptr null, ptr %9, align 8
  store i32 1, ptr %21, align 4
  br label %49

33:                                               ; preds = %40, %37, %8
  %34 = landingpad { ptr, i32 }
          cleanup
  %35 = extractvalue { ptr, i32 } %34, 0
  store ptr %35, ptr %19, align 8
  %36 = extractvalue { ptr, i32 } %34, 1
  store i32 %36, ptr %20, align 4
  br label %51

37:                                               ; preds = %31
  %38 = invoke noundef zeroext i1 @_ZN4Simd4Base18SynetAdd16bUniform10PreferableERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(64) %18)
          to label %39 unwind label %33

39:                                               ; preds = %37
  br i1 %38, label %40, label %48

40:                                               ; preds = %39
  %41 = invoke noalias noundef nonnull ptr @_Znwm(i64 noundef 88) #7
          to label %42 unwind label %33

42:                                               ; preds = %40
  invoke void @_ZN4Simd4Base18SynetAdd16bUniformC1ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(88) %41, ptr noundef nonnull align 8 dereferenceable(64) %18)
          to label %43 unwind label %44

43:                                               ; preds = %42
  store ptr %41, ptr %9, align 8
  store i32 1, ptr %21, align 4
  br label %49

44:                                               ; preds = %42
  %45 = landingpad { ptr, i32 }
          cleanup
  %46 = extractvalue { ptr, i32 } %45, 0
  store ptr %46, ptr %19, align 8
  %47 = extractvalue { ptr, i32 } %45, 1
  store i32 %47, ptr %20, align 4
  call void @_ZdlPvm(ptr noundef %41, i64 noundef 88) #8
  br label %51

48:                                               ; preds = %39
  store ptr null, ptr %9, align 8
  store i32 1, ptr %21, align 4
  br label %49

49:                                               ; preds = %48, %43, %32
  call void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %18) #6
  call void @llvm.lifetime.end.p0(i64 64, ptr %18) #6
  %50 = load ptr, ptr %9, align 8
  ret ptr %50

51:                                               ; preds = %44, %33
  call void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %18) #6
  call void @llvm.lifetime.end.p0(i64 64, ptr %18) #6
  br label %52

52:                                               ; preds = %51
  %53 = load ptr, ptr %19, align 8
  %54 = load i32, ptr %20, align 4
  %55 = insertvalue { ptr, i32 } poison, ptr %53, 0
  %56 = insertvalue { ptr, i32 } %55, i32 %54, 1
  resume { ptr, i32 } %56
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd11Add16bParamC2EPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef nonnull align 8 dereferenceable(64), ptr noundef, i64 noundef, i32 noundef, ptr noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd11Add16bParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64)) #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #5 align 2

declare void @_ZN4Simd4Base18SynetAdd16bUniformC1ERKNS_11Add16bParamE(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Add16bParam" = type { %"class.std::vector", %"class.std::vector", i32, i32, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base18SynetAdd16bUniform10PreferableERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base15SynetAdd16bInitEPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef %0, i64 noundef %1, i32 noundef %2, ptr noundef %3, i64 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #1 personality ptr @__gxx_personality_v0 {
  %9 = alloca %"struct.Simd::Add16bParam", align 8
  call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %9) #6
  call void @_ZN4Simd11Add16bParamC2EPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef nonnull align 8 dereferenceable(64) %9, ptr noundef %0, i64 noundef %1, i32 noundef %2, ptr noundef %3, i64 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7)
  %10 = call noundef zeroext i1 @_ZN4Simd11Add16bParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64) %9)
  br i1 %10, label %13, label %21

11:                                               ; preds = %16, %13
  %12 = landingpad { ptr, i32 }
          cleanup
  br label %22

13:                                               ; preds = %8
  %14 = invoke noundef zeroext i1 @_ZN4Simd4Base18SynetAdd16bUniform10PreferableERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(64) %9)
          to label %15 unwind label %11

15:                                               ; preds = %13
  br i1 %14, label %16, label %21

16:                                               ; preds = %15
  %17 = invoke noalias noundef nonnull dereferenceable(88) ptr @_Znwm(i64 noundef 88) #7
          to label %18 unwind label %11

18:                                               ; preds = %16
  invoke void @_ZN4Simd4Base18SynetAdd16bUniformC1ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(88) %17, ptr noundef nonnull align 8 dereferenceable(64) %9)
          to label %21 unwind label %19

19:                                               ; preds = %18
  %20 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %17, i64 noundef 88) #8
  br label %22

21:                                               ; preds = %15, %18, %8
  %.011 = phi ptr [ null, %8 ], [ %17, %18 ], [ null, %15 ]
  call void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %9) #6
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %9) #6
  ret ptr %.011

22:                                               ; preds = %19, %11
  %.pn = phi { ptr, i32 } [ %20, %19 ], [ %12, %11 ]
  call void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64) %9) #6
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %9) #6
  resume { ptr, i32 } %.pn
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd11Add16bParamC2EPKmm18SimdTensorDataTypeS2_mS3_S3_20SimdTensorFormatType(ptr noundef nonnull align 8 dereferenceable(64), ptr noundef, i64 noundef, i32 noundef, ptr noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd11Add16bParam5ValidEv(ptr noundef nonnull align 8 dereferenceable(64)) local_unnamed_addr #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd11Add16bParamD2Ev(ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #5 align 2

declare void @_ZN4Simd4Base18SynetAdd16bUniformC1ERKNS_11Add16bParamE(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass