; LLVM IR from ermig1979/Simd :: src/Simd/SimdBaseCpu.ll (ZN4Simd4Base8VendorIdEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZZN4Simd4Base8VendorIdEvE8vendorId = external hidden global [4 x i32], align 16
@_ZGVZN4Simd4Base8VendorIdEvE8vendorId = external hidden global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base5CpuIdEiiPj(i32 noundef, i32 noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base8VendorIdEv() #3 {
  %1 = alloca [4 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr %1) #4
  call void @llvm.memset.p0.i64(ptr align 16 %1, i8 0, i64 16, i1 false)
  %2 = getelementptr inbounds [4 x i32], ptr %1, i64 0, i64 0
  %3 = call noundef zeroext i1 @_ZN4Simd4Base5CpuIdEiiPj(i32 noundef 0, i32 noundef 0, ptr noundef %2)
  %4 = load atomic i8, ptr @_ZGVZN4Simd4Base8VendorIdEvE8vendorId acquire, align 8
  %5 = icmp eq i8 %4, 0
  br i1 %5, label %6, label %16, !prof !5

6:                                                ; preds = %0
  %7 = call i32 @__cxa_guard_acquire(ptr @_ZGVZN4Simd4Base8VendorIdEvE8vendorId) #4
  %8 = icmp ne i32 %7, 0
  br i1 %8, label %9, label %16

9:                                                ; preds = %6
  %10 = getelementptr inbounds [4 x i32], ptr %1, i64 0, i64 1
  %11 = load i32, ptr %10, align 4, !tbaa !6
  store i32 %11, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, align 4, !tbaa !6
  %12 = getelementptr inbounds [4 x i32], ptr %1, i64 0, i64 3
  %13 = load i32, ptr %12, align 4, !tbaa !6
  store i32 %13, ptr getelementptr inbounds (i32, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, i64 1), align 4, !tbaa !6
  %14 = getelementptr inbounds [4 x i32], ptr %1, i64 0, i64 2
  %15 = load i32, ptr %14, align 8, !tbaa !6
  store i32 %15, ptr getelementptr inbounds (i32, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, i64 2), align 4, !tbaa !6
  store i32 0, ptr getelementptr inbounds (i32, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, i64 3), align 4, !tbaa !6
  call void @__cxa_guard_release(ptr @_ZGVZN4Simd4Base8VendorIdEvE8vendorId) #4
  br label %16

16:                                               ; preds = %9, %6, %0
  call void @llvm.lifetime.end.p0(i64 16, ptr %1) #4
  ret ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId
}

; Function Attrs: nounwind
declare i32 @__cxa_guard_acquire(ptr) #4

; Function Attrs: nounwind
declare void @__cxa_guard_release(ptr) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!"branch_weights", i32 1, i32 1048575}
!6 = !{!7, !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZZN4Simd4Base8VendorIdEvE8vendorId = external hidden global [4 x i32], align 16
@_ZGVZN4Simd4Base8VendorIdEvE8vendorId = external hidden global i64, align 8

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base5CpuIdEiiPj(i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef nonnull ptr @_ZN4Simd4Base8VendorIdEv() local_unnamed_addr #3 {
  %1 = alloca [4 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %1) #5
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(16) %1, i8 0, i64 16, i1 false)
  %2 = call noundef zeroext i1 @_ZN4Simd4Base5CpuIdEiiPj(i32 noundef 0, i32 noundef 0, ptr noundef nonnull %1)
  %3 = load atomic i8, ptr @_ZGVZN4Simd4Base8VendorIdEvE8vendorId acquire, align 8
  %4 = icmp eq i8 %3, 0
  br i1 %4, label %5, label %13, !prof !5

5:                                                ; preds = %0
  %6 = call i32 @__cxa_guard_acquire(ptr nonnull @_ZGVZN4Simd4Base8VendorIdEvE8vendorId) #5
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %13, label %7

7:                                                ; preds = %5
  %8 = getelementptr inbounds i8, ptr %1, i64 4
  %9 = load i32, ptr %8, align 4, !tbaa !6
  store i32 %9, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, align 16, !tbaa !6
  %10 = getelementptr inbounds i8, ptr %1, i64 8
  %11 = load <2 x i32>, ptr %10, align 8, !tbaa !6
  %12 = shufflevector <2 x i32> %11, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
  store <2 x i32> %12, ptr getelementptr inbounds (i8, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, i64 4), align 4, !tbaa !6
  store i32 0, ptr getelementptr inbounds (i8, ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId, i64 12), align 4, !tbaa !6
  call void @__cxa_guard_release(ptr nonnull @_ZGVZN4Simd4Base8VendorIdEvE8vendorId) #5
  br label %13

13:                                               ; preds = %7, %5, %0
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %1) #5
  ret ptr @_ZZN4Simd4Base8VendorIdEvE8vendorId
}

; Function Attrs: nofree nounwind
declare i32 @__cxa_guard_acquire(ptr) local_unnamed_addr #4

; Function Attrs: nofree nounwind
declare void @__cxa_guard_release(ptr) local_unnamed_addr #4

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nofree nounwind }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!"branch_weights", i32 1, i32 1048575}
!6 = !{!7, !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass