; LLVM IR from abeaumont/competitive-programming :: cses/2220.ll (Z1fRSt6vectorIiSaIiEE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z1fRSt6vectorIiSaIiEE(ptr noundef nonnull align 8 dereferenceable(24) %0) #0 {
  %2 = alloca i1, align 1
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #2
  store i8 0, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !11
  br label %8

8:                                                ; preds = %81, %1
  %9 = load i32, ptr %5, align 4, !tbaa !11
  %10 = sext i32 %9 to i64
  %11 = load ptr, ptr %3, align 8, !tbaa !5
  %12 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11) #2
  %13 = sub i64 %12, 1
  %14 = icmp ult i64 %10, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %8
  store i32 2, ptr %6, align 4
  br label %84

16:                                               ; preds = %8
  %17 = load i8, ptr %4, align 1, !tbaa !9, !range !13, !noundef !14
  %18 = trunc i8 %17 to i1
  %19 = zext i1 %18 to i32
  %20 = icmp eq i32 %19, 1
  br i1 %20, label %21, label %27

21:                                               ; preds = %16
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  %23 = load i32, ptr %5, align 4, !tbaa !11
  %24 = add nsw i32 %23, 1
  %25 = sext i32 %24 to i64
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %25) #2
  store i32 9, ptr %26, align 4, !tbaa !11
  br label %27

27:                                               ; preds = %21, %16
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = load i32, ptr %5, align 4, !tbaa !11
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30) #2
  %32 = load i32, ptr %31, align 4, !tbaa !11
  %33 = load ptr, ptr %3, align 8, !tbaa !5
  %34 = load i32, ptr %5, align 4, !tbaa !11
  %35 = add nsw i32 %34, 1
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %36) #2
  %38 = load i32, ptr %37, align 4, !tbaa !11
  %39 = icmp eq i32 %32, %38
  br i1 %39, label %40, label %80

40:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %41 = load i32, ptr %5, align 4, !tbaa !11
  %42 = add nsw i32 %41, 1
  store i32 %42, ptr %7, align 4, !tbaa !11
  %43 = load ptr, ptr %3, align 8, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !11
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %45) #2
  %47 = load i32, ptr %46, align 4, !tbaa !11
  %48 = add nsw i32 %47, -1
  store i32 %48, ptr %46, align 4, !tbaa !11
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = load i32, ptr %7, align 4, !tbaa !11
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %51) #2
  %53 = load i32, ptr %52, align 4, !tbaa !11
  %54 = icmp slt i32 %53, 0
  br i1 %54, label %55, label %76

55:                                               ; preds = %40
  br label %56

56:                                               ; preds = %63, %55
  %57 = load ptr, ptr %3, align 8, !tbaa !5
  %58 = load i32, ptr %7, align 4, !tbaa !11
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %57, i64 noundef %59) #2
  %61 = load i32, ptr %60, align 4, !tbaa !11
  %62 = icmp slt i32 %61, 0
  br i1 %62, label %63, label %75

63:                                               ; preds = %56
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = load i32, ptr %7, align 4, !tbaa !11
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %64, i64 noundef %66) #2
  store i32 9, ptr %67, align 4, !tbaa !11
  %68 = load ptr, ptr %3, align 8, !tbaa !5
  %69 = load i32, ptr %7, align 4, !tbaa !11
  %70 = add nsw i32 %69, -1
  store i32 %70, ptr %7, align 4, !tbaa !11
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %71) #2
  %73 = load i32, ptr %72, align 4, !tbaa !11
  %74 = add nsw i32 %73, -1
  store i32 %74, ptr %72, align 4, !tbaa !11
  br label %56, !llvm.loop !15

75:                                               ; preds = %56
  store i1 false, ptr %2, align 1
  store i32 1, ptr %6, align 4
  br label %77

76:                                               ; preds = %40
  store i8 1, ptr %4, align 1, !tbaa !9
  store i32 0, ptr %6, align 4
  br label %77

77:                                               ; preds = %76, %75
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  %78 = load i32, ptr %6, align 4
  switch i32 %78, label %84 [
    i32 0, label %79
  ]

79:                                               ; preds = %77
  br label %80

80:                                               ; preds = %79, %27
  br label %81

81:                                               ; preds = %80
  %82 = load i32, ptr %5, align 4, !tbaa !11
  %83 = add nsw i32 %82, 1
  store i32 %83, ptr %5, align 4, !tbaa !11
  br label %8, !llvm.loop !17

84:                                               ; preds = %77, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  %85 = load i32, ptr %6, align 4
  switch i32 %85, label %87 [
    i32 2, label %86
  ]

86:                                               ; preds = %84
  store i1 true, ptr %2, align 1
  store i32 1, ptr %6, align 4
  br label %87

87:                                               ; preds = %86, %84
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #2
  %88 = load i1, ptr %2, align 1
  ret i1 %88
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z1fRSt6vectorIiSaIiEE(ptr noundef nonnull align 8 dereferenceable(24) %0) local_unnamed_addr #0 {
  %2 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %.not34 = icmp eq i64 %2, 1
  br i1 %.not34, label %.critedge, label %.lr.ph39

.lr.ph39:                                         ; preds = %1, %.thread
  %indvars.iv46 = phi i32 [ %indvars.iv.next47, %.thread ], [ 1, %1 ]
  %indvars.iv = phi i64 [ %3, %.thread ], [ 0, %1 ]
  %.02635 = phi i1 [ %.2, %.thread ], [ false, %1 ]
  %3 = add nuw nsw i64 %indvars.iv, 1
  br i1 %.02635, label %4, label %.lr.ph39._crit_edge

4:                                                ; preds = %.lr.ph39
  %5 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  store i32 9, ptr %5, align 4, !tbaa !5
  br label %.lr.ph39._crit_edge

.lr.ph39._crit_edge:                              ; preds = %.lr.ph39, %4
  %6 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #1
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %10 = icmp eq i32 %7, %9
  br i1 %10, label %11, label %.thread

11:                                               ; preds = %.lr.ph39._crit_edge
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = add nsw i32 %13, -1
  store i32 %14, ptr %12, align 4, !tbaa !5
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %3) #1
  %16 = load i32, ptr %15, align 4, !tbaa !5
  %17 = icmp sgt i32 %16, -1
  br i1 %17, label %.thread, label %.preheader

.preheader:                                       ; preds = %11
  %18 = and i64 %3, 4294967295
  %19 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %18) #1
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = icmp slt i32 %20, 0
  br i1 %21, label %.lr.ph.preheader, label %.critedge

.lr.ph.preheader:                                 ; preds = %.preheader
  %22 = sext i32 %indvars.iv46 to i64
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv49 = phi i64 [ %22, %.lr.ph.preheader ], [ %indvars.iv.next50, %.lr.ph ]
  %23 = phi i64 [ %18, %.lr.ph.preheader ], [ %indvars.iv.next50, %.lr.ph ]
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %23) #1
  store i32 9, ptr %24, align 4, !tbaa !5
  %indvars.iv.next50 = add nsw i64 %indvars.iv49, -1
  %25 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv.next50) #1
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %27 = add nsw i32 %26, -1
  store i32 %27, ptr %25, align 4, !tbaa !5
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv.next50) #1
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = icmp slt i32 %29, 0
  br i1 %30, label %.lr.ph, label %.critedge, !llvm.loop !9

.thread:                                          ; preds = %11, %.lr.ph39._crit_edge
  %.2 = phi i1 [ %.02635, %.lr.ph39._crit_edge ], [ true, %11 ]
  %31 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %32 = add i64 %31, -1
  %.not.not = icmp ugt i64 %32, %3
  %indvars.iv.next47 = add nuw i32 %indvars.iv46, 1
  br i1 %.not.not, label %.lr.ph39, label %.critedge, !llvm.loop !11

.critedge:                                        ; preds = %.thread, %.lr.ph, %.preheader, %1
  %.not.lcssa = phi i1 [ true, %1 ], [ false, %.preheader ], [ false, %.lr.ph ], [ true, %.thread ]
  ret i1 %.not.lcssa
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: AggressiveInstCombinePass,ConstraintEliminationPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass