; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetInnerProduct16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::InnerProductParam16b" = type { i64, i64, i64, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base24SynetInnerProduct16bInitEmmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(i64 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8) #1 personality ptr @__gxx_personality_v0 {
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca %"struct.Simd::InnerProductParam16b", align 8
  %21 = alloca i32, align 4
  %22 = alloca ptr, align 8
  %23 = alloca i32, align 4
  store i64 %0, ptr %11, align 8, !tbaa !5
  store i64 %1, ptr %12, align 8, !tbaa !5
  store i64 %2, ptr %13, align 8, !tbaa !5
  store i32 %3, ptr %14, align 4, !tbaa !9
  store i32 %4, ptr %15, align 4, !tbaa !9
  store i32 %5, ptr %16, align 4, !tbaa !9
  store i32 %6, ptr %17, align 4, !tbaa !11
  store i32 %7, ptr %18, align 4, !tbaa !11
  store i32 %8, ptr %19, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 48, ptr %20) #5
  %24 = load i64, ptr %11, align 8, !tbaa !5
  %25 = load i64, ptr %12, align 8, !tbaa !5
  %26 = load i64, ptr %13, align 8, !tbaa !5
  %27 = load i32, ptr %14, align 4, !tbaa !9
  %28 = load i32, ptr %15, align 4, !tbaa !9
  %29 = load i32, ptr %16, align 4, !tbaa !9
  %30 = load i32, ptr %17, align 4, !tbaa !11
  %31 = load i32, ptr %18, align 4, !tbaa !11
  %32 = load i32, ptr %19, align 4, !tbaa !11
  call void @_ZN4Simd20InnerProductParam16bC2Emmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(ptr noundef nonnull align 8 dereferenceable(48) %20, i64 noundef %24, i64 noundef %25, i64 noundef %26, i32 noundef %27, i32 noundef %28, i32 noundef %29, i32 noundef %30, i32 noundef %31, i32 noundef %32)
  %33 = call noundef zeroext i1 @_ZN4Simd20InnerProductParam16b5ValidEv(ptr noundef nonnull align 8 dereferenceable(48) %20)
  br i1 %33, label %35, label %34

34:                                               ; preds = %9
  store ptr null, ptr %10, align 8
  store i32 1, ptr %21, align 4
  br label %42

35:                                               ; preds = %9
  %36 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 160) #6
  invoke void @_ZN4Simd4Base23SynetInnerProduct16bRefC1ERKNS_20InnerProductParam16bE(ptr noundef nonnull align 8 dereferenceable(160) %36, ptr noundef nonnull align 8 dereferenceable(48) %20)
          to label %37 unwind label %38

37:                                               ; preds = %35
  store ptr %36, ptr %10, align 8
  store i32 1, ptr %21, align 4
  br label %42

38:                                               ; preds = %35
  %39 = landingpad { ptr, i32 }
          cleanup
  %40 = extractvalue { ptr, i32 } %39, 0
  store ptr %40, ptr %22, align 8
  %41 = extractvalue { ptr, i32 } %39, 1
  store i32 %41, ptr %23, align 4
  call void @_ZdlPvm(ptr noundef %36, i64 noundef 160) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr %20) #5
  br label %44

42:                                               ; preds = %37, %34
  call void @llvm.lifetime.end.p0(i64 48, ptr %20) #5
  %43 = load ptr, ptr %10, align 8
  ret ptr %43

44:                                               ; preds = %38
  %45 = load ptr, ptr %22, align 8
  %46 = load i32, ptr %23, align 4
  %47 = insertvalue { ptr, i32 } poison, ptr %45, 0
  %48 = insertvalue { ptr, i32 } %47, i32 %46, 1
  resume { ptr, i32 } %48
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd20InnerProductParam16bC2Emmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(ptr noundef nonnull align 8 dereferenceable(48), i64 noundef, i64 noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd20InnerProductParam16b5ValidEv(ptr noundef nonnull align 8 dereferenceable(48)) #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #4

declare void @_ZN4Simd4Base23SynetInnerProduct16bRefC1ERKNS_20InnerProductParam16bE(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS8SimdBool", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::InnerProductParam16b" = type { i64, i64, i64, i32, i32, i32, i32, i32, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base24SynetInnerProduct16bInitEmmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(i64 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8) local_unnamed_addr #1 personality ptr @__gxx_personality_v0 {
  %10 = alloca %"struct.Simd::InnerProductParam16b", align 8
  call void @llvm.lifetime.start.p0(i64 48, ptr nonnull %10) #5
  call void @_ZN4Simd20InnerProductParam16bC2Emmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(ptr noundef nonnull align 8 dereferenceable(48) %10, i64 noundef %0, i64 noundef %1, i64 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8)
  %11 = call noundef zeroext i1 @_ZN4Simd20InnerProductParam16b5ValidEv(ptr noundef nonnull align 8 dereferenceable(48) %10)
  br i1 %11, label %12, label %16

12:                                               ; preds = %9
  %13 = call noalias noundef nonnull dereferenceable(160) ptr @_Znwm(i64 noundef 160) #6
  invoke void @_ZN4Simd4Base23SynetInnerProduct16bRefC1ERKNS_20InnerProductParam16bE(ptr noundef nonnull align 8 dereferenceable(160) %13, ptr noundef nonnull align 8 dereferenceable(48) %10)
          to label %16 unwind label %14

14:                                               ; preds = %12
  %15 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %13, i64 noundef 160) #7
  call void @llvm.lifetime.end.p0(i64 48, ptr nonnull %10) #5
  resume { ptr, i32 } %15

16:                                               ; preds = %12, %9
  %.0 = phi ptr [ null, %9 ], [ %13, %12 ]
  call void @llvm.lifetime.end.p0(i64 48, ptr nonnull %10) #5
  ret ptr %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd20InnerProductParam16bC2Emmm18SimdTensorDataTypeS1_S1_8SimdBoolS2_S2_(ptr noundef nonnull align 8 dereferenceable(48), i64 noundef, i64 noundef, i64 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd20InnerProductParam16b5ValidEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #2 align 2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #4

declare void @_ZN4Simd4Base23SynetInnerProduct16bRefC1ERKNS_20InnerProductParam16bE(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass