; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution16bNhwcGemm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::SynetConvolution16b" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", %"class.std::__cxx11::basic_string", %"struct.Simd::Array.0", %"struct.Simd::Array.1", %"struct.Simd::Array.1", i8, i8, i8, i64, i64, i64, i64 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Array.1" = type { ptr, i64 }
%"class.Simd::Base::SynetConvolution16bNhwcGemm" = type { %"class.Simd::SynetConvolution16b", %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr, [2 x ptr] }
%"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam" = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base27SynetConvolution16bNhwcGemm9SetWeightEPKf(ptr noundef nonnull align 8 dereferenceable(480) %0, ptr noundef %1) unnamed_addr #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %15 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %16 = getelementptr inbounds %"class.Simd::SynetConvolution16b", ptr %15, i32 0, i32 1
  store ptr %16, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  %17 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcGemm", ptr %15, i32 0, i32 1
  store ptr %17, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %18, i32 0, i32 5
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcGemm", ptr %15, i32 0, i32 1
  %22 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %21, i32 0, i32 3
  %23 = load i64, ptr %22, align 8, !tbaa !15
  %24 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %20, i64 noundef %23)
  store i64 %24, ptr %7, align 8, !tbaa !30
  %25 = getelementptr inbounds %"class.Simd::SynetConvolution16b", ptr %15, i32 0, i32 4
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %26, i32 0, i32 12
  %28 = load i64, ptr %27, align 8, !tbaa !31
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %29, i32 0, i32 10
  %31 = load i64, ptr %30, align 8, !tbaa !32
  %32 = mul i64 %28, %31
  call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %25, i64 noundef %32, i1 noundef zeroext true, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %33 = getelementptr inbounds %"class.Simd::SynetConvolution16b", ptr %15, i32 0, i32 4
  %34 = getelementptr inbounds %"struct.Simd::Array.0", ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !33
  store ptr %35, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  store i64 0, ptr %9, align 8, !tbaa !30
  br label %36

36:                                               ; preds = %125, %2
  %37 = load i64, ptr %9, align 8, !tbaa !30
  %38 = load i64, ptr %7, align 8, !tbaa !30
  %39 = icmp ult i64 %37, %38
  br i1 %39, label %41, label %40

40:                                               ; preds = %36
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  br label %128

41:                                               ; preds = %36
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  store i64 0, ptr %11, align 8, !tbaa !30
  br label %42

42:                                               ; preds = %121, %41
  %43 = load i64, ptr %11, align 8, !tbaa !30
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %44, i32 0, i32 12
  %46 = load i64, ptr %45, align 8, !tbaa !31
  %47 = icmp ult i64 %43, %46
  br i1 %47, label %49, label %48

48:                                               ; preds = %42
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  br label %124

49:                                               ; preds = %42
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = load i64, ptr %11, align 8, !tbaa !30
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %52, i32 0, i32 5
  %54 = load i64, ptr %53, align 8, !tbaa !9
  %55 = mul i64 %51, %54
  %56 = getelementptr inbounds float, ptr %50, i64 %55
  %57 = load i64, ptr %9, align 8, !tbaa !30
  %58 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcGemm", ptr %15, i32 0, i32 1
  %59 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %58, i32 0, i32 3
  %60 = load i64, ptr %59, align 8, !tbaa !15
  %61 = mul i64 %57, %60
  %62 = getelementptr inbounds float, ptr %56, i64 %61
  store ptr %62, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 0, ptr %13, align 8, !tbaa !30
  br label %63

63:                                               ; preds = %117, %49
  %64 = load i64, ptr %13, align 8, !tbaa !30
  %65 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcGemm", ptr %15, i32 0, i32 1
  %66 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %65, i32 0, i32 3
  %67 = load i64, ptr %66, align 8, !tbaa !15
  %68 = icmp ult i64 %64, %67
  br i1 %68, label %70, label %69

69:                                               ; preds = %63
  store i32 8, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %120

70:                                               ; preds = %63
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  store i64 0, ptr %14, align 8, !tbaa !30
  br label %71

71:                                               ; preds = %111, %70
  %72 = load i64, ptr %14, align 8, !tbaa !30
  %73 = icmp ult i64 %72, 2
  br i1 %73, label %75, label %74

74:                                               ; preds = %71
  store i32 11, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  br label %114

75:                                               ; preds = %71
  %76 = load i64, ptr %9, align 8, !tbaa !30
  %77 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcGemm", ptr %15, i32 0, i32 1
  %78 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %77, i32 0, i32 3
  %79 = load i64, ptr %78, align 8, !tbaa !15
  %80 = mul i64 %76, %79
  %81 = load i64, ptr %13, align 8, !tbaa !30
  %82 = add i64 %80, %81
  %83 = load ptr, ptr %5, align 8, !tbaa !5
  %84 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %83, i32 0, i32 5
  %85 = load i64, ptr %84, align 8, !tbaa !9
  %86 = icmp ult i64 %82, %85
  br i1 %86, label %87, label %107

87:                                               ; preds = %75
  %88 = load i64, ptr %11, align 8, !tbaa !30
  %89 = load i64, ptr %14, align 8, !tbaa !30
  %90 = add i64 %88, %89
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution16bNhwcGemm::AlgParam", ptr %91, i32 0, i32 1
  %93 = load i64, ptr %92, align 8, !tbaa !34
  %94 = icmp ult i64 %90, %93
  br i1 %94, label %95, label %107

95:                                               ; preds = %87
  %96 = load ptr, ptr %12, align 8, !tbaa !5
  %97 = load i64, ptr %14, align 8, !tbaa !30
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %98, i32 0, i32 5
  %100 = load i64, ptr %99, align 8, !tbaa !9
  %101 = mul i64 %97, %100
  %102 = getelementptr inbounds float, ptr %96, i64 %101
  %103 = load float, ptr %102, align 4, !tbaa !35
  %104 = call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %103)
  %105 = load ptr, ptr %8, align 8, !tbaa !5
  %106 = getelementptr inbounds i16, ptr %105, i32 1
  store ptr %106, ptr %8, align 8, !tbaa !5
  store i16 %104, ptr %105, align 2, !tbaa !37
  br label %110

107:                                              ; preds = %87, %75
  %108 = load ptr, ptr %8, align 8, !tbaa !5
  %109 = getelementptr inbounds i16, ptr %108, i32 1
  store ptr %109, ptr %8, align 8, !tbaa !5
  store i16 0, ptr %108, align 2, !tbaa !37
  br label %110

110:                                              ; preds = %107, %95
  br label %111

111:                                              ; preds = %110
  %112 = load i64, ptr %14, align 8, !tbaa !30
  %113 = add i64 %112, 1
  store i64 %113, ptr %14, align 8, !tbaa !30
  br label %71, !llvm.loop !39

114:                                              ; preds = %74
  %115 = load ptr, ptr %12, align 8, !tbaa !5
  %116 = getelementptr inbounds float, ptr %115, i32 1
  store ptr %116, ptr %12, align 8, !tbaa !5
  br label %117

117:                                              ; preds = %114
  %118 = load i64, ptr %13, align 8, !tbaa !30
  %119 = add i64 %118, 1
  store i64 %119, ptr %13, align 8, !tbaa !30
  br label %63, !llvm.loop !41

120:                                              ; preds = %69
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  br label %121

121:                                              ; preds = %120
  %122 = load i64, ptr %11, align 8, !tbaa !30
  %123 = add i64 %122, 2
  store i64 %123, ptr %11, align 8, !tbaa !30
  br label %42, !llvm.loop !42

124:                                              ; preds = %48
  br label %125

125:                                              ; preds = %124
  %126 = load i64, ptr %9, align 8, !tbaa !30
  %127 = add i64 %126, 1
  store i64 %127, ptr %9, align 8, !tbaa !30
  br label %36, !llvm.loop !43

128:                                              ; preds = %40
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret void
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) #2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #3 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 32}
!10 = !{!"_ZTS25SimdConvolutionParameters", !11, i64 0, !11, i64 8, !11, i64 16, !12, i64 24, !13, i64 28, !11, i64 32, !11, i64 40, !11, i64 48, !12, i64 56, !13, i64 60, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !14, i64 152}
!11 = !{!"long", !7, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!13 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!14 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!15 = !{!16, !11, i64 352}
!16 = !{!"_ZTSN4Simd4Base27SynetConvolution16bNhwcGemmE", !17, i64 0, !28, i64 328, !6, i64 456, !7, i64 464}
!17 = !{!"_ZTSN4Simd19SynetConvolution16bE", !18, i64 0, !19, i64 8, !22, i64 192, !23, i64 208, !25, i64 240, !26, i64 256, !26, i64 272, !27, i64 288, !27, i64 289, !27, i64 290, !11, i64 296, !11, i64 304, !11, i64 312, !11, i64 320}
!18 = !{!"_ZTSN4Simd9DeletableE"}
!19 = !{!"_ZTSN4Simd9ConvParamE", !10, i64 0, !20, i64 160, !11, i64 168, !21, i64 176}
!20 = !{!"_ZTS8SimdBool", !7, i64 0}
!21 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!22 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !11, i64 8}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !11, i64 8, !7, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!25 = !{!"_ZTSN4Simd5ArrayItEE", !6, i64 0, !11, i64 8}
!26 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !11, i64 8}
!27 = !{!"bool", !7, i64 0}
!28 = !{!"_ZTSN4Simd4Base27SynetConvolution16bNhwcGemm8AlgParamE", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !11, i64 40, !11, i64 48, !11, i64 56, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !29, i64 120, !29, i64 124}
!29 = !{!"int", !7, i64 0}
!30 = !{!11, !11, i64 0}
!31 = !{!28, !11, i64 96}
!32 = !{!28, !11, i64 80}
!33 = !{!17, !6, i64 240}
!34 = !{!28, !11, i64 8}
!35 = !{!36, !36, i64 0}
!36 = !{!"float", !7, i64 0}
!37 = !{!38, !38, i64 0}
!38 = !{!"short", !7, i64 0}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}
!41 = distinct !{!41, !40}
!42 = distinct !{!42, !40}
!43 = distinct !{!43, !40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base27SynetConvolution16bNhwcGemm9SetWeightEPKf(ptr noundef nonnull align 8 dereferenceable(480) %0, ptr nocapture noundef readonly %1) unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 40
  %4 = load i64, ptr %3, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 352
  %6 = load i64, ptr %5, align 8, !tbaa !13
  %7 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %4, i64 noundef %6)
  %8 = getelementptr inbounds i8, ptr %0, i64 240
  %9 = getelementptr inbounds i8, ptr %0, i64 424
  %10 = load i64, ptr %9, align 8, !tbaa !29
  %11 = getelementptr inbounds i8, ptr %0, i64 408
  %12 = load i64, ptr %11, align 8, !tbaa !30
  %13 = mul i64 %12, %10
  tail call void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %8, i64 noundef %13, i1 noundef zeroext true, i64 noundef 8)
  %.not = icmp eq i64 %7, 0
  br i1 %.not, label %._crit_edge48, label %.preheader35.lr.ph

.preheader35.lr.ph:                               ; preds = %2
  %14 = getelementptr inbounds i8, ptr %0, i64 336
  %15 = load i64, ptr %9, align 8, !tbaa !29
  %.not49 = icmp eq i64 %15, 0
  br i1 %.not49, label %._crit_edge48, label %.preheader35.preheader

.preheader35.preheader:                           ; preds = %.preheader35.lr.ph
  %16 = load ptr, ptr %8, align 8, !tbaa !31
  br label %.preheader35

.preheader35:                                     ; preds = %.preheader35.preheader, %._crit_edge43
  %17 = phi i64 [ %20, %._crit_edge43 ], [ %15, %.preheader35.preheader ]
  %18 = phi i64 [ %21, %._crit_edge43 ], [ %15, %.preheader35.preheader ]
  %.03246 = phi i64 [ %22, %._crit_edge43 ], [ 0, %.preheader35.preheader ]
  %.03345 = phi ptr [ %.1.lcssa, %._crit_edge43 ], [ %16, %.preheader35.preheader ]
  %.not50 = icmp eq i64 %18, 0
  br i1 %.not50, label %._crit_edge43, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader35
  %19 = load i64, ptr %5, align 8, !tbaa !13
  %.not51 = icmp eq i64 %19, 0
  br i1 %.not51, label %._crit_edge43, label %.lr.ph.split

._crit_edge48:                                    ; preds = %._crit_edge43, %.preheader35.lr.ph, %2
  ret void

._crit_edge43:                                    ; preds = %._crit_edge, %.lr.ph, %.preheader35
  %20 = phi i64 [ %17, %.preheader35 ], [ %17, %.lr.ph ], [ %41, %._crit_edge ]
  %21 = phi i64 [ 0, %.preheader35 ], [ %18, %.lr.ph ], [ %41, %._crit_edge ]
  %.1.lcssa = phi ptr [ %.03345, %.preheader35 ], [ %.03345, %.lr.ph ], [ %.2.lcssa, %._crit_edge ]
  %22 = add nuw i64 %.03246, 1
  %exitcond.not = icmp eq i64 %22, %7
  br i1 %exitcond.not, label %._crit_edge48, label %.preheader35, !llvm.loop !32

.lr.ph.split:                                     ; preds = %.lr.ph, %._crit_edge
  %23 = phi i64 [ %41, %._crit_edge ], [ %17, %.lr.ph ]
  %24 = phi i64 [ %42, %._crit_edge ], [ %19, %.lr.ph ]
  %25 = phi i64 [ %43, %._crit_edge ], [ %19, %.lr.ph ]
  %26 = phi i64 [ %44, %._crit_edge ], [ %19, %.lr.ph ]
  %.03142 = phi i64 [ %45, %._crit_edge ], [ 0, %.lr.ph ]
  %.141 = phi ptr [ %.2.lcssa, %._crit_edge ], [ %.03345, %.lr.ph ]
  %.not52 = icmp eq i64 %26, 0
  br i1 %.not52, label %._crit_edge, label %.preheader.preheader

.preheader.preheader:                             ; preds = %.lr.ph.split
  %27 = load i64, ptr %3, align 8, !tbaa !5
  %28 = mul i64 %27, %.03142
  %29 = getelementptr inbounds float, ptr %1, i64 %28
  %30 = mul i64 %26, %.03246
  %31 = getelementptr inbounds float, ptr %29, i64 %30
  %32 = or disjoint i64 %.03142, 1
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %60
  %33 = phi i64 [ %61, %60 ], [ %24, %.preheader.preheader ]
  %34 = phi i64 [ %61, %60 ], [ %25, %.preheader.preheader ]
  %.02940 = phi i64 [ %63, %60 ], [ 0, %.preheader.preheader ]
  %.03039 = phi ptr [ %62, %60 ], [ %31, %.preheader.preheader ]
  %.238 = phi ptr [ %.4.1, %60 ], [ %.141, %.preheader.preheader ]
  %35 = mul i64 %34, %.03246
  %36 = add i64 %35, %.02940
  %37 = load i64, ptr %3, align 8, !tbaa !5
  %38 = icmp ult i64 %36, %37
  %39 = load i64, ptr %14, align 8
  %40 = icmp ult i64 %.03142, %39
  %or.cond = select i1 %38, i1 %40, i1 false
  br i1 %or.cond, label %47, label %50

._crit_edge.loopexit:                             ; preds = %60
  %.pre57 = load i64, ptr %9, align 8, !tbaa !29
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.lr.ph.split
  %41 = phi i64 [ %23, %.lr.ph.split ], [ %.pre57, %._crit_edge.loopexit ]
  %42 = phi i64 [ %24, %.lr.ph.split ], [ %61, %._crit_edge.loopexit ]
  %43 = phi i64 [ %25, %.lr.ph.split ], [ %61, %._crit_edge.loopexit ]
  %44 = phi i64 [ 0, %.lr.ph.split ], [ %61, %._crit_edge.loopexit ]
  %.2.lcssa = phi ptr [ %.141, %.lr.ph.split ], [ %.4.1, %._crit_edge.loopexit ]
  %45 = add i64 %.03142, 2
  %46 = icmp ult i64 %45, %41
  br i1 %46, label %.lr.ph.split, label %._crit_edge43, !llvm.loop !35

47:                                               ; preds = %.preheader
  %48 = load float, ptr %.03039, align 4, !tbaa !36
  %49 = tail call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %48)
  %.pre = load i64, ptr %5, align 8, !tbaa !13
  %.pre55 = load i64, ptr %3, align 8, !tbaa !5
  %.pre58 = mul i64 %.pre, %.03246
  %.pre59 = add i64 %.pre58, %.02940
  br label %50

50:                                               ; preds = %.preheader, %47
  %.pre-phi60 = phi i64 [ %36, %.preheader ], [ %.pre59, %47 ]
  %51 = phi i64 [ %33, %.preheader ], [ %.pre, %47 ]
  %52 = phi i64 [ %37, %.preheader ], [ %.pre55, %47 ]
  %storemerge = phi i16 [ 0, %.preheader ], [ %49, %47 ]
  %.4 = getelementptr inbounds i8, ptr %.238, i64 2
  store i16 %storemerge, ptr %.238, align 2, !tbaa !38
  %53 = icmp ult i64 %.pre-phi60, %52
  %54 = load i64, ptr %14, align 8
  %55 = icmp ult i64 %32, %54
  %or.cond64 = select i1 %53, i1 %55, i1 false
  br i1 %or.cond64, label %56, label %60

56:                                               ; preds = %50
  %57 = getelementptr inbounds float, ptr %.03039, i64 %52
  %58 = load float, ptr %57, align 4, !tbaa !36
  %59 = tail call noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef %58)
  %.pre56 = load i64, ptr %5, align 8, !tbaa !13
  br label %60

60:                                               ; preds = %56, %50
  %61 = phi i64 [ %.pre56, %56 ], [ %51, %50 ]
  %storemerge.1 = phi i16 [ %59, %56 ], [ 0, %50 ]
  %.4.1 = getelementptr inbounds i8, ptr %.238, i64 4
  store i16 %storemerge.1, ptr %.4, align 2, !tbaa !38
  %62 = getelementptr inbounds i8, ptr %.03039, i64 4
  %63 = add nuw i64 %.02940, 1
  %64 = icmp ult i64 %63, %61
  br i1 %64, label %.preheader, label %._crit_edge.loopexit, !llvm.loop !40
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayItE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i16 @_ZN4Simd4Base17Float32ToBFloat16Ef(float noundef) local_unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 32}
!6 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !10, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !12, i64 152}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!11 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!12 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!13 = !{!14, !7, i64 352}
!14 = !{!"_ZTSN4Simd4Base27SynetConvolution16bNhwcGemmE", !15, i64 0, !27, i64 328, !21, i64 456, !8, i64 464}
!15 = !{!"_ZTSN4Simd19SynetConvolution16bE", !16, i64 0, !17, i64 8, !20, i64 192, !22, i64 208, !24, i64 240, !25, i64 256, !25, i64 272, !26, i64 288, !26, i64 289, !26, i64 290, !7, i64 296, !7, i64 304, !7, i64 312, !7, i64 320}
!16 = !{!"_ZTSN4Simd9DeletableE"}
!17 = !{!"_ZTSN4Simd9ConvParamE", !6, i64 0, !18, i64 160, !7, i64 168, !19, i64 176}
!18 = !{!"_ZTS8SimdBool", !8, i64 0}
!19 = !{!"_ZTS26SimdSynetCompatibilityType", !8, i64 0}
!20 = !{!"_ZTSN4Simd5ArrayIhEE", !21, i64 0, !7, i64 8}
!21 = !{!"any pointer", !8, i64 0}
!22 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !23, i64 0, !7, i64 8, !8, i64 16}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !21, i64 0}
!24 = !{!"_ZTSN4Simd5ArrayItEE", !21, i64 0, !7, i64 8}
!25 = !{!"_ZTSN4Simd5ArrayIfEE", !21, i64 0, !7, i64 8}
!26 = !{!"bool", !8, i64 0}
!27 = !{!"_ZTSN4Simd4Base27SynetConvolution16bNhwcGemm8AlgParamE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !7, i64 48, !7, i64 56, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !28, i64 120, !28, i64 124}
!28 = !{!"int", !8, i64 0}
!29 = !{!27, !7, i64 96}
!30 = !{!27, !7, i64 80}
!31 = !{!15, !21, i64 240}
!32 = distinct !{!32, !33, !34}
!33 = !{!"llvm.loop.mustprogress"}
!34 = !{!"llvm.loop.unswitch.partial.disable"}
!35 = distinct !{!35, !33, !34}
!36 = !{!37, !37, i64 0}
!37 = !{!"float", !8, i64 0}
!38 = !{!39, !39, i64 0}
!39 = !{!"short", !8, i64 0}
!40 = distinct !{!40, !33}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass