; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetDeconvolution16bNhwcGemm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::Base::SynetDeconvolution16bNhwcGemm" = type { %"class.Simd::SynetDeconvolution16b", %"struct.Simd::Base::SynetDeconvolution16bNhwcGemm::AlgParam", ptr, ptr, ptr, ptr }
%"class.Simd::SynetDeconvolution16b" = type { %"struct.Simd::Deletable", %"struct.Simd::DeconvParam", %"struct.Simd::Array", %"class.std::__cxx11::basic_string", %"struct.Simd::Array.0", %"struct.Simd::Array.1", %"struct.Simd::Array.1", i8, i8, i8, i64, i64, i64, i64 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::DeconvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Array.1" = type { ptr, i64 }
%"struct.Simd::Base::SynetDeconvolution16bNhwcGemm::AlgParam" = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 }

@_ZTVN4Simd4Base29SynetDeconvolution16bNhwcGemmE = external dso_local unnamed_addr constant { [10 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [24 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [99 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE = external hidden unnamed_addr constant [94 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(488) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN4Simd21SynetDeconvolution16bC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(328) %5, ptr noundef nonnull align 8 dereferenceable(180) %6)
  store ptr getelementptr inbounds inrange(-16, 64) ({ [10 x ptr] }, ptr @_ZTVN4Simd4Base29SynetDeconvolution16bNhwcGemmE, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  %7 = getelementptr inbounds %"class.Simd::Base::SynetDeconvolution16bNhwcGemm", ptr %5, i32 0, i32 1
  %8 = getelementptr inbounds %"class.Simd::Base::SynetDeconvolution16bNhwcGemm", ptr %5, i32 0, i32 2
  store ptr null, ptr %8, align 8, !tbaa !11
  %9 = getelementptr inbounds %"class.Simd::Base::SynetDeconvolution16bNhwcGemm", ptr %5, i32 0, i32 3
  store ptr null, ptr %9, align 8, !tbaa !30
  %10 = getelementptr inbounds %"class.Simd::Base::SynetDeconvolution16bNhwcGemm", ptr %5, i32 0, i32 4
  store ptr null, ptr %10, align 8, !tbaa !31
  %11 = getelementptr inbounds %"class.Simd::Base::SynetDeconvolution16bNhwcGemm", ptr %5, i32 0, i32 5
  store ptr null, ptr %11, align 8, !tbaa !32
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %"struct.Simd::DeconvParam", ptr %12, i32 0, i32 1
  %14 = load i32, ptr %13, align 8, !tbaa !33
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %21

16:                                               ; preds = %2
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %17, i32 0, i32 20
  %19 = load i64, ptr %18, align 8, !tbaa !34
  %20 = icmp eq i64 %19, 1
  br label %21

21:                                               ; preds = %16, %2
  %22 = phi i1 [ false, %2 ], [ %20, %16 ]
  br i1 %22, label %23, label %24

23:                                               ; preds = %21
  br label %26

24:                                               ; preds = %21
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 43, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE) #3
  unreachable

25:                                               ; No predecessors!
  br label %26

26:                                               ; preds = %25, %23
  ret void
}

declare void @_ZN4Simd21SynetDeconvolution16bC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 456}
!12 = !{!"_ZTSN4Simd4Base29SynetDeconvolution16bNhwcGemmE", !13, i64 0, !29, i64 328, !6, i64 456, !6, i64 464, !6, i64 472, !6, i64 480}
!13 = !{!"_ZTSN4Simd21SynetDeconvolution16bE", !14, i64 0, !15, i64 8, !23, i64 192, !24, i64 208, !26, i64 240, !27, i64 256, !27, i64 272, !28, i64 288, !28, i64 289, !28, i64 290, !17, i64 296, !17, i64 304, !17, i64 312, !17, i64 320}
!14 = !{!"_ZTSN4Simd9DeletableE"}
!15 = !{!"_ZTSN4Simd11DeconvParamE", !16, i64 0, !21, i64 160, !17, i64 168, !22, i64 176}
!16 = !{!"_ZTS25SimdConvolutionParameters", !17, i64 0, !17, i64 8, !17, i64 16, !18, i64 24, !19, i64 28, !17, i64 32, !17, i64 40, !17, i64 48, !18, i64 56, !19, i64 60, !17, i64 64, !17, i64 72, !17, i64 80, !17, i64 88, !17, i64 96, !17, i64 104, !17, i64 112, !17, i64 120, !17, i64 128, !17, i64 136, !17, i64 144, !20, i64 152}
!17 = !{!"long", !7, i64 0}
!18 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!19 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!20 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!21 = !{!"_ZTS8SimdBool", !7, i64 0}
!22 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!23 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !17, i64 8}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !25, i64 0, !17, i64 8, !7, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!26 = !{!"_ZTSN4Simd5ArrayItEE", !6, i64 0, !17, i64 8}
!27 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !17, i64 8}
!28 = !{!"bool", !7, i64 0}
!29 = !{!"_ZTSN4Simd4Base29SynetDeconvolution16bNhwcGemm8AlgParamE", !17, i64 0, !17, i64 8, !17, i64 16, !17, i64 24, !17, i64 32, !17, i64 40, !17, i64 48, !17, i64 56, !17, i64 64, !17, i64 72, !17, i64 80, !17, i64 88, !17, i64 96, !17, i64 104, !17, i64 112, !17, i64 120}
!30 = !{!12, !6, i64 464}
!31 = !{!12, !6, i64 472}
!32 = !{!12, !6, i64 480}
!33 = !{!15, !21, i64 160}
!34 = !{!16, !17, i64 144}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN4Simd4Base29SynetDeconvolution16bNhwcGemmE = external dso_local unnamed_addr constant { [10 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [24 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [99 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE = external hidden unnamed_addr constant [94 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(488) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 {
  tail call void @_ZN4Simd21SynetDeconvolution16bC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(328) %0, ptr noundef nonnull align 8 dereferenceable(180) %1)
  store ptr getelementptr inbounds inrange(-16, 64) (i8, ptr @_ZTVN4Simd4Base29SynetDeconvolution16bNhwcGemmE, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 456
  %4 = getelementptr inbounds i8, ptr %1, i64 160
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %3, i8 0, i64 32, i1 false)
  %5 = load i32, ptr %4, align 8, !tbaa !8
  %.not = icmp ne i32 %5, 0
  %6 = getelementptr inbounds i8, ptr %1, i64 144
  %7 = load i64, ptr %6, align 8
  %8 = icmp eq i64 %7, 1
  %or.cond = select i1 %.not, i1 %8, i1 false
  br i1 %or.cond, label %9, label %.critedge

.critedge:                                        ; preds = %2
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 43, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base29SynetDeconvolution16bNhwcGemmC2ERKNS_11DeconvParamE) #4
  unreachable

9:                                                ; preds = %2
  ret void
}

declare void @_ZN4Simd21SynetDeconvolution16bC2ERKNS_11DeconvParamE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !16, i64 160}
!9 = !{!"_ZTSN4Simd11DeconvParamE", !10, i64 0, !16, i64 160, !11, i64 168, !17, i64 176}
!10 = !{!"_ZTS25SimdConvolutionParameters", !11, i64 0, !11, i64 8, !11, i64 16, !13, i64 24, !14, i64 28, !11, i64 32, !11, i64 40, !11, i64 48, !13, i64 56, !14, i64 60, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !15, i64 152}
!11 = !{!"long", !12, i64 0}
!12 = !{!"omnipotent char", !7, i64 0}
!13 = !{!"_ZTS18SimdTensorDataType", !12, i64 0}
!14 = !{!"_ZTS20SimdTensorFormatType", !12, i64 0}
!15 = !{!"_ZTS29SimdConvolutionActivationType", !12, i64 0}
!16 = !{!"_ZTS8SimdBool", !12, i64 0}
!17 = !{!"_ZTS26SimdSynetCompatibilityType", !12, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass