; LLVM IR from Tudor67/Competitive-Programming :: Infoarena/ArhivaEducationala/#042_StatisticiDeOrdine/sdo_sol3_quick_select_with_ra_377d3cef (RSt6vectorIiSaIiEE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr noundef nonnull align 4 dereferenceable(4) %0, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 8 dereferenceable(24) %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = load i32, ptr %17, align 4, !tbaa !9
  %19 = call i32 @rand() #5
  %20 = load ptr, ptr %7, align 8, !tbaa !5
  %21 = load i32, ptr %20, align 4, !tbaa !9
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = load i32, ptr %22, align 4, !tbaa !9
  %24 = sub nsw i32 %21, %23
  %25 = add nsw i32 %24, 1
  %26 = srem i32 %19, %25
  %27 = add nsw i32 %18, %26
  store i32 %27, ptr %9, align 4, !tbaa !9
  %28 = load ptr, ptr %8, align 8, !tbaa !5
  %29 = load i32, ptr %9, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30) #5
  %32 = load ptr, ptr %8, align 8, !tbaa !5
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = load i32, ptr %33, align 4, !tbaa !9
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %35) #5
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %31, ptr noundef nonnull align 4 dereferenceable(4) %36) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = load ptr, ptr %7, align 8, !tbaa !5
  %39 = load i32, ptr %38, align 4, !tbaa !9
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %40) #5
  %42 = load i32, ptr %41, align 4, !tbaa !9
  store i32 %42, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = load i32, ptr %43, align 4, !tbaa !9
  store i32 %44, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = load i32, ptr %45, align 4, !tbaa !9
  %47 = sub nsw i32 %46, 1
  store i32 %47, ptr %12, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %74, %4
  %49 = load i32, ptr %11, align 4, !tbaa !9
  %50 = load i32, ptr %12, align 4, !tbaa !9
  %51 = icmp sle i32 %49, %50
  br i1 %51, label %52, label %75

52:                                               ; preds = %48
  %53 = load ptr, ptr %8, align 8, !tbaa !5
  %54 = load i32, ptr %11, align 4, !tbaa !9
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %55) #5
  %57 = load i32, ptr %56, align 4, !tbaa !9
  %58 = load i32, ptr %10, align 4, !tbaa !9
  %59 = icmp slt i32 %57, %58
  br i1 %59, label %60, label %63

60:                                               ; preds = %52
  %61 = load i32, ptr %11, align 4, !tbaa !9
  %62 = add nsw i32 %61, 1
  store i32 %62, ptr %11, align 4, !tbaa !9
  br label %74

63:                                               ; preds = %52
  %64 = load ptr, ptr %8, align 8, !tbaa !5
  %65 = load i32, ptr %11, align 4, !tbaa !9
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %64, i64 noundef %66) #5
  %68 = load ptr, ptr %8, align 8, !tbaa !5
  %69 = load i32, ptr %12, align 4, !tbaa !9
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %70) #5
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %67, ptr noundef nonnull align 4 dereferenceable(4) %71) #5
  %72 = load i32, ptr %12, align 4, !tbaa !9
  %73 = add nsw i32 %72, -1
  store i32 %73, ptr %12, align 4, !tbaa !9
  br label %74

74:                                               ; preds = %63, %60
  br label %48, !llvm.loop !11

75:                                               ; preds = %48
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  %76 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %76, ptr %13, align 4, !tbaa !9
  %77 = load ptr, ptr %8, align 8, !tbaa !5
  %78 = load i32, ptr %13, align 4, !tbaa !9
  %79 = sext i32 %78 to i64
  %80 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %77, i64 noundef %79) #5
  %81 = load ptr, ptr %8, align 8, !tbaa !5
  %82 = load ptr, ptr %7, align 8, !tbaa !5
  %83 = load i32, ptr %82, align 4, !tbaa !9
  %84 = sext i32 %83 to i64
  %85 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %84) #5
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %80, ptr noundef nonnull align 4 dereferenceable(4) %85) #5
  %86 = load ptr, ptr %6, align 8, !tbaa !5
  %87 = load i32, ptr %86, align 4, !tbaa !9
  %88 = load i32, ptr %13, align 4, !tbaa !9
  %89 = icmp eq i32 %87, %88
  br i1 %89, label %90, label %91

90:                                               ; preds = %75
  store i32 1, ptr %14, align 4
  br label %116

91:                                               ; preds = %75
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = load i32, ptr %92, align 4, !tbaa !9
  %94 = load i32, ptr %13, align 4, !tbaa !9
  %95 = icmp slt i32 %93, %94
  br i1 %95, label %96, label %102

96:                                               ; preds = %91
  %97 = load ptr, ptr %5, align 8, !tbaa !5
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #5
  %99 = load i32, ptr %13, align 4, !tbaa !9
  %100 = sub nsw i32 %99, 1
  store i32 %100, ptr %15, align 4, !tbaa !9
  %101 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr noundef nonnull align 4 dereferenceable(4) %97, ptr noundef nonnull align 4 dereferenceable(4) %98, ptr noundef nonnull align 4 dereferenceable(4) %15, ptr noundef nonnull align 8 dereferenceable(24) %101)
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #5
  br label %114

102:                                              ; preds = %91
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = load i32, ptr %103, align 4, !tbaa !9
  %105 = load i32, ptr %13, align 4, !tbaa !9
  %106 = icmp sgt i32 %104, %105
  br i1 %106, label %107, label %113

107:                                              ; preds = %102
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #5
  %108 = load i32, ptr %13, align 4, !tbaa !9
  %109 = add nsw i32 %108, 1
  store i32 %109, ptr %16, align 4, !tbaa !9
  %110 = load ptr, ptr %6, align 8, !tbaa !5
  %111 = load ptr, ptr %7, align 8, !tbaa !5
  %112 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr noundef nonnull align 4 dereferenceable(4) %16, ptr noundef nonnull align 4 dereferenceable(4) %110, ptr noundef nonnull align 4 dereferenceable(4) %111, ptr noundef nonnull align 8 dereferenceable(24) %112)
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #5
  br label %113

113:                                              ; preds = %107, %102
  br label %114

114:                                              ; preds = %113, %96
  br label %115

115:                                              ; preds = %114
  store i32 0, ptr %14, align 4
  br label %116

116:                                              ; preds = %115, %90
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  %117 = load i32, ptr %14, align 4
  switch i32 %117, label %119 [
    i32 0, label %118
    i32 1, label %118
  ]

118:                                              ; preds = %116, %116
  ret void

119:                                              ; preds = %116
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i32 @rand() #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #4 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr nocapture noundef nonnull readonly align 4 dereferenceable(4) %0, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr nocapture noundef nonnull readonly align 4 dereferenceable(4) %2, ptr noundef nonnull align 8 dereferenceable(24) %3) local_unnamed_addr #0 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = load i32, ptr %0, align 4, !tbaa !5
  %8 = tail call i32 @rand() #4
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = load i32, ptr %0, align 4, !tbaa !5
  %11 = add i32 %9, 1
  %12 = sub i32 %11, %10
  %13 = srem i32 %8, %12
  %14 = add nsw i32 %13, %7
  %15 = sext i32 %14 to i64
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %15) #4
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = sext i32 %17 to i64
  %19 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %18) #4
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %16, ptr noundef nonnull align 4 dereferenceable(4) %19) #4
  %20 = load i32, ptr %2, align 4, !tbaa !5
  %21 = sext i32 %20 to i64
  %22 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %21) #4
  %23 = load i32, ptr %22, align 4, !tbaa !5
  %24 = load i32, ptr %0, align 4, !tbaa !5
  %25 = load i32, ptr %2, align 4, !tbaa !5
  %.not43.not = icmp slt i32 %24, %25
  br i1 %.not43.not, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %4
  %26 = add nsw i32 %25, -1
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %38
  %.045 = phi i32 [ %.1, %38 ], [ %24, %.lr.ph.preheader ]
  %.04044 = phi i32 [ %.141, %38 ], [ %26, %.lr.ph.preheader ]
  %27 = sext i32 %.045 to i64
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %27) #4
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = icmp slt i32 %29, %23
  br i1 %30, label %31, label %33

31:                                               ; preds = %.lr.ph
  %32 = add nsw i32 %.045, 1
  br label %38

33:                                               ; preds = %.lr.ph
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %27) #4
  %35 = sext i32 %.04044 to i64
  %36 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %35) #4
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %34, ptr noundef nonnull align 4 dereferenceable(4) %36) #4
  %37 = add nsw i32 %.04044, -1
  br label %38

38:                                               ; preds = %33, %31
  %.141 = phi i32 [ %.04044, %31 ], [ %37, %33 ]
  %.1 = phi i32 [ %32, %31 ], [ %.045, %33 ]
  %.not = icmp sgt i32 %.1, %.141
  br i1 %.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %38, %4
  %.0.lcssa = phi i32 [ %24, %4 ], [ %.1, %38 ]
  %39 = sext i32 %.0.lcssa to i64
  %40 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %39) #4
  %41 = load i32, ptr %2, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %42) #4
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %40, ptr noundef nonnull align 4 dereferenceable(4) %43) #4
  %44 = load i32, ptr %1, align 4, !tbaa !5
  %45 = icmp eq i32 %44, %.0.lcssa
  br i1 %45, label %54, label %46

46:                                               ; preds = %._crit_edge
  %47 = icmp slt i32 %44, %.0.lcssa
  br i1 %47, label %48, label %50

48:                                               ; preds = %46
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #4
  %49 = add nsw i32 %.0.lcssa, -1
  store i32 %49, ptr %5, align 4, !tbaa !5
  call void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr noundef nonnull align 4 dereferenceable(4) %0, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %5, ptr noundef nonnull align 8 dereferenceable(24) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #4
  br label %54

50:                                               ; preds = %46
  %51 = icmp sgt i32 %44, %.0.lcssa
  br i1 %51, label %52, label %54

52:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #4
  %53 = add nsw i32 %.0.lcssa, 1
  store i32 %53, ptr %6, align 4, !tbaa !5
  call void @_Z11quickSelectRKiS0_S0_RSt6vectorIiSaIiEE(ptr noundef nonnull align 4 dereferenceable(4) %6, ptr noundef nonnull align 4 dereferenceable(4) %1, ptr noundef nonnull align 4 dereferenceable(4) %2, ptr noundef nonnull align 8 dereferenceable(24) %3)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #4
  br label %54

54:                                               ; preds = %50, %52, %48, %._crit_edge
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i32 @rand() local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass