; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetMergedConvolution8i)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }
%"class.Simd::Base::SynetMergedConvolution8i" = type { %"class.Simd::SynetMergedConvolution8i", %"struct.Simd::MergConvParam8i", i8, i8, i8, i8, i64, i64, [2 x i64], [5 x i64], [3 x %"struct.Simd::CvtParam"], %"struct.Simd::Array", [2 x %"struct.Simd::Array.1"], %"struct.Simd::Array.0", [2 x %"struct.Simd::Array.0"], [3 x %"struct.Simd::Array.0"], [3 x %"struct.Simd::Array.0"], %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr, ptr, ptr, ptr, [2 x ptr], %"class.std::__cxx11::basic_string" }
%"class.Simd::SynetMergedConvolution8i" = type { %"struct.Simd::Deletable" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::MergConvParam8i" = type { i64, [3 x %"struct.Simd::ConvParam"] }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::CvtParam" = type <{ %"struct.Simd::Array", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", i8, [3 x i8], i32, i32, i32, i32, [4 x i8] }>
%"struct.Simd::Array" = type { ptr, i64 }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Base::SynetMergedConvolution8i::AlgParam" = type { i64, i64, [3 x i64], [3 x i64], [3 x i64], [2 x i64], [3 x i64], i64, i32, i32 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24SynetMergedConvolution8i18ReorderInputWeightERKNS_9ConvParamERNS_5ArrayIaEE(ptr noundef nonnull align 8 dereferenceable(1376) %0, ptr noundef nonnull align 8 dereferenceable(180) %1, ptr noundef nonnull align 8 dereferenceable(16) %2) #3 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca %"struct.Simd::Array.1", align 8
  %12 = alloca ptr, align 8
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca ptr, align 8
  %18 = alloca i64, align 8
  %19 = alloca i64, align 8
  %20 = alloca ptr, align 8
  %21 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %22 = load ptr, ptr %4, align 8
  %23 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution8i", ptr %22, i32 0, i32 17
  %24 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr %23, i32 0, i32 0
  %25 = load i64, ptr %24, align 8, !tbaa !9
  %26 = icmp eq i64 %25, 0
  br i1 %26, label %27, label %28

27:                                               ; preds = %3
  br label %165

28:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %29 = getelementptr inbounds %"class.Simd::Base::SynetMergedConvolution8i", ptr %22, i32 0, i32 17
  %30 = getelementptr inbounds %"struct.Simd::Base::SynetMergedConvolution8i::AlgParam", ptr %29, i32 0, i32 0
  %31 = load i64, ptr %30, align 8, !tbaa !9
  %32 = mul i64 %31, 2
  store i64 %32, ptr %7, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %33 = load ptr, ptr %5, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %33, i32 0, i32 0
  %35 = load i64, ptr %34, align 8, !tbaa !23
  %36 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %35, i64 noundef 4)
  store i64 %36, ptr %8, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %37, i32 0, i32 5
  %39 = load i64, ptr %38, align 8, !tbaa !28
  %40 = load i64, ptr %7, align 8, !tbaa !22
  %41 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %39, i64 noundef %40)
  store i64 %41, ptr %9, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %42, i32 0, i32 10
  %44 = load i64, ptr %43, align 8, !tbaa !29
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %45, i32 0, i32 11
  %47 = load i64, ptr %46, align 8, !tbaa !30
  %48 = mul i64 %44, %47
  store i64 %48, ptr %10, align 8, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #4
  %49 = load i64, ptr %10, align 8, !tbaa !22
  %50 = load i64, ptr %8, align 8, !tbaa !22
  %51 = mul i64 %49, %50
  %52 = load i64, ptr %9, align 8, !tbaa !22
  %53 = mul i64 %51, %52
  %54 = load i64, ptr %7, align 8, !tbaa !22
  %55 = mul i64 %53, %54
  %56 = mul i64 %55, 4
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %11, i64 noundef %56, i1 noundef zeroext false, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %57 = getelementptr inbounds %"struct.Simd::Array.1", ptr %11, i32 0, i32 0
  %58 = load ptr, ptr %57, align 8, !tbaa !31
  store ptr %58, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 0, ptr %13, align 8, !tbaa !22
  br label %59

59:                                               ; preds = %159, %28
  %60 = load i64, ptr %13, align 8, !tbaa !22
  %61 = load i64, ptr %9, align 8, !tbaa !22
  %62 = icmp ult i64 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  store i32 2, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %162

64:                                               ; preds = %59
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  store i64 0, ptr %15, align 8, !tbaa !22
  br label %65

65:                                               ; preds = %155, %64
  %66 = load i64, ptr %15, align 8, !tbaa !22
  %67 = load i64, ptr %10, align 8, !tbaa !22
  %68 = icmp ult i64 %66, %67
  br i1 %68, label %70, label %69

69:                                               ; preds = %65
  store i32 5, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  br label %158

70:                                               ; preds = %65
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  store i64 0, ptr %16, align 8, !tbaa !22
  br label %71

71:                                               ; preds = %151, %70
  %72 = load i64, ptr %16, align 8, !tbaa !22
  %73 = load i64, ptr %8, align 8, !tbaa !22
  %74 = icmp ult i64 %72, %73
  br i1 %74, label %76, label %75

75:                                               ; preds = %71
  store i32 8, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  br label %154

76:                                               ; preds = %71
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  %77 = load ptr, ptr %6, align 8, !tbaa !5
  %78 = getelementptr inbounds %"struct.Simd::Array.1", ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !31
  %80 = load i64, ptr %15, align 8, !tbaa !22
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %81, i32 0, i32 0
  %83 = load i64, ptr %82, align 8, !tbaa !23
  %84 = mul i64 %80, %83
  %85 = load i64, ptr %16, align 8, !tbaa !22
  %86 = mul i64 %85, 4
  %87 = add i64 %84, %86
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %88, i32 0, i32 5
  %90 = load i64, ptr %89, align 8, !tbaa !28
  %91 = mul i64 %87, %90
  %92 = getelementptr inbounds i8, ptr %79, i64 %91
  %93 = load i64, ptr %13, align 8, !tbaa !22
  %94 = load i64, ptr %7, align 8, !tbaa !22
  %95 = mul i64 %93, %94
  %96 = getelementptr inbounds i8, ptr %92, i64 %95
  store ptr %96, ptr %17, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #4
  store i64 0, ptr %18, align 8, !tbaa !22
  br label %97

97:                                               ; preds = %147, %76
  %98 = load i64, ptr %18, align 8, !tbaa !22
  %99 = load i64, ptr %7, align 8, !tbaa !22
  %100 = icmp ult i64 %98, %99
  br i1 %100, label %102, label %101

101:                                              ; preds = %97
  store i32 11, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #4
  br label %150

102:                                              ; preds = %97
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #4
  store i64 0, ptr %19, align 8, !tbaa !22
  br label %103

103:                                              ; preds = %141, %102
  %104 = load i64, ptr %19, align 8, !tbaa !22
  %105 = icmp ult i64 %104, 4
  br i1 %105, label %107, label %106

106:                                              ; preds = %103
  store i32 14, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #4
  br label %144

107:                                              ; preds = %103
  %108 = load i64, ptr %13, align 8, !tbaa !22
  %109 = load i64, ptr %7, align 8, !tbaa !22
  %110 = mul i64 %108, %109
  %111 = load i64, ptr %18, align 8, !tbaa !22
  %112 = add i64 %110, %111
  %113 = load ptr, ptr %5, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %113, i32 0, i32 5
  %115 = load i64, ptr %114, align 8, !tbaa !28
  %116 = icmp ult i64 %112, %115
  br i1 %116, label %117, label %137

117:                                              ; preds = %107
  %118 = load i64, ptr %16, align 8, !tbaa !22
  %119 = mul i64 %118, 4
  %120 = load i64, ptr %19, align 8, !tbaa !22
  %121 = add i64 %119, %120
  %122 = load ptr, ptr %5, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %122, i32 0, i32 0
  %124 = load i64, ptr %123, align 8, !tbaa !23
  %125 = icmp ult i64 %121, %124
  br i1 %125, label %126, label %137

126:                                              ; preds = %117
  %127 = load ptr, ptr %17, align 8, !tbaa !5
  %128 = load i64, ptr %19, align 8, !tbaa !22
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %129, i32 0, i32 5
  %131 = load i64, ptr %130, align 8, !tbaa !28
  %132 = mul i64 %128, %131
  %133 = getelementptr inbounds i8, ptr %127, i64 %132
  %134 = load i8, ptr %133, align 1, !tbaa !33
  %135 = load ptr, ptr %12, align 8, !tbaa !5
  %136 = getelementptr inbounds i8, ptr %135, i32 1
  store ptr %136, ptr %12, align 8, !tbaa !5
  store i8 %134, ptr %135, align 1, !tbaa !33
  br label %140

137:                                              ; preds = %117, %107
  %138 = load ptr, ptr %12, align 8, !tbaa !5
  %139 = getelementptr inbounds i8, ptr %138, i32 1
  store ptr %139, ptr %12, align 8, !tbaa !5
  store i8 0, ptr %138, align 1, !tbaa !33
  br label %140

140:                                              ; preds = %137, %126
  br label %141

141:                                              ; preds = %140
  %142 = load i64, ptr %19, align 8, !tbaa !22
  %143 = add i64 %142, 1
  store i64 %143, ptr %19, align 8, !tbaa !22
  br label %103, !llvm.loop !34

144:                                              ; preds = %106
  %145 = load ptr, ptr %17, align 8, !tbaa !5
  %146 = getelementptr inbounds i8, ptr %145, i32 1
  store ptr %146, ptr %17, align 8, !tbaa !5
  br label %147

147:                                              ; preds = %144
  %148 = load i64, ptr %18, align 8, !tbaa !22
  %149 = add i64 %148, 1
  store i64 %149, ptr %18, align 8, !tbaa !22
  br label %97, !llvm.loop !36

150:                                              ; preds = %101
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  br label %151

151:                                              ; preds = %150
  %152 = load i64, ptr %16, align 8, !tbaa !22
  %153 = add i64 %152, 1
  store i64 %153, ptr %16, align 8, !tbaa !22
  br label %71, !llvm.loop !37

154:                                              ; preds = %75
  br label %155

155:                                              ; preds = %154
  %156 = load i64, ptr %15, align 8, !tbaa !22
  %157 = add i64 %156, 1
  store i64 %157, ptr %15, align 8, !tbaa !22
  br label %65, !llvm.loop !38

158:                                              ; preds = %69
  br label %159

159:                                              ; preds = %158
  %160 = load i64, ptr %13, align 8, !tbaa !22
  %161 = add i64 %160, 1
  store i64 %161, ptr %13, align 8, !tbaa !22
  br label %59, !llvm.loop !39

162:                                              ; preds = %63
  %163 = load ptr, ptr %6, align 8, !tbaa !5
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %163, ptr noundef nonnull align 8 dereferenceable(16) %11)
          to label %164 unwind label %166

164:                                              ; preds = %162
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %11) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %165

165:                                              ; preds = %164, %27
  ret void

166:                                              ; preds = %162
  %167 = landingpad { ptr, i32 }
          cleanup
  %168 = extractvalue { ptr, i32 } %167, 0
  store ptr %168, ptr %20, align 8
  %169 = extractvalue { ptr, i32 } %167, 1
  store i32 %169, ptr %21, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %11) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %170

170:                                              ; preds = %166
  %171 = load ptr, ptr %20, align 8
  %172 = load i32, ptr %21, align 4
  %173 = insertvalue { ptr, i32 } poison, ptr %171, 0
  %174 = insertvalue { ptr, i32 } %173, i32 %172, 1
  resume { ptr, i32 } %174
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) #0 align 2

attributes #0 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !14, i64 1152}
!10 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8iE", !11, i64 0, !13, i64 8, !15, i64 568, !15, i64 569, !15, i64 570, !15, i64 571, !14, i64 576, !14, i64 584, !7, i64 592, !7, i64 608, !7, i64 648, !16, i64 960, !7, i64 976, !17, i64 1008, !7, i64 1024, !7, i64 1056, !7, i64 1104, !18, i64 1152, !6, i64 1296, !6, i64 1304, !6, i64 1312, !6, i64 1320, !7, i64 1328, !20, i64 1344}
!11 = !{!"_ZTSN4Simd24SynetMergedConvolution8iE", !12, i64 0}
!12 = !{!"_ZTSN4Simd9DeletableE"}
!13 = !{!"_ZTSN4Simd15MergConvParam8iE", !14, i64 0, !7, i64 8}
!14 = !{!"long", !7, i64 0}
!15 = !{!"bool", !7, i64 0}
!16 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !14, i64 8}
!17 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !14, i64 8}
!18 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8i8AlgParamE", !14, i64 0, !14, i64 8, !7, i64 16, !7, i64 40, !7, i64 64, !7, i64 88, !7, i64 104, !14, i64 128, !19, i64 136, !19, i64 140}
!19 = !{!"int", !7, i64 0}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !21, i64 0, !14, i64 8, !7, i64 16}
!21 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!22 = !{!14, !14, i64 0}
!23 = !{!24, !14, i64 0}
!24 = !{!"_ZTS25SimdConvolutionParameters", !14, i64 0, !14, i64 8, !14, i64 16, !25, i64 24, !26, i64 28, !14, i64 32, !14, i64 40, !14, i64 48, !25, i64 56, !26, i64 60, !14, i64 64, !14, i64 72, !14, i64 80, !14, i64 88, !14, i64 96, !14, i64 104, !14, i64 112, !14, i64 120, !14, i64 128, !14, i64 136, !14, i64 144, !27, i64 152}
!25 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!26 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!27 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!28 = !{!24, !14, i64 32}
!29 = !{!24, !14, i64 64}
!30 = !{!24, !14, i64 72}
!31 = !{!32, !6, i64 0}
!32 = !{!"_ZTSN4Simd5ArrayIaEE", !6, i64 0, !14, i64 8}
!33 = !{!7, !7, i64 0}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}
!36 = distinct !{!36, !35}
!37 = distinct !{!37, !35}
!38 = distinct !{!38, !35}
!39 = distinct !{!39, !35}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base24SynetMergedConvolution8i18ReorderInputWeightERKNS_9ConvParamERNS_5ArrayIaEE(ptr nocapture noundef nonnull readonly align 8 dereferenceable(1376) %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(180) %1, ptr noundef nonnull align 8 dereferenceable(16) %2) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %4 = alloca %"struct.Simd::Array.1", align 8
  %5 = getelementptr inbounds i8, ptr %0, i64 1152
  %6 = load i64, ptr %5, align 8, !tbaa !5
  %7 = icmp eq i64 %6, 0
  br i1 %7, label %78, label %8

8:                                                ; preds = %3
  %9 = shl i64 %6, 1
  %10 = load i64, ptr %1, align 8, !tbaa !21
  %11 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %10, i64 noundef 4)
  %12 = getelementptr inbounds i8, ptr %1, i64 32
  %13 = load i64, ptr %12, align 8, !tbaa !26
  %14 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %13, i64 noundef %9)
  %15 = getelementptr inbounds i8, ptr %1, i64 64
  %16 = load i64, ptr %15, align 8, !tbaa !27
  %17 = getelementptr inbounds i8, ptr %1, i64 72
  %18 = load i64, ptr %17, align 8, !tbaa !28
  %19 = mul i64 %18, %16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #4
  %20 = shl i64 %6, 3
  %21 = mul i64 %20, %11
  %22 = mul i64 %21, %14
  %23 = mul i64 %22, %19
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %23, i1 noundef zeroext false, i64 noundef 8)
  %.not = icmp eq i64 %14, 0
  br i1 %.not, label %._crit_edge75, label %.preheader55.lr.ph

.preheader55.lr.ph:                               ; preds = %8
  %.not84 = icmp eq i64 %19, 0
  %.not86 = icmp eq i64 %9, 0
  %.not85 = icmp eq i64 %11, 0
  %or.cond = or i1 %.not84, %.not85
  %brmerge = or i1 %or.cond, %.not86
  br i1 %brmerge, label %._crit_edge75, label %.preheader55.us.us.us.preheader

.preheader55.us.us.us.preheader:                  ; preds = %.preheader55.lr.ph
  %24 = load ptr, ptr %4, align 8, !tbaa !29
  br label %.preheader55.us.us.us

.preheader55.us.us.us:                            ; preds = %.preheader55.us.us.us.preheader, %._crit_edge.split.us.split.us.us.us.us
  %.074.us.us.us = phi ptr [ %.5.us.us.us.us.us.us.3, %._crit_edge.split.us.split.us.us.us.us ], [ %24, %.preheader55.us.us.us.preheader ]
  %.04673.us.us.us = phi i64 [ %76, %._crit_edge.split.us.split.us.us.us.us ], [ 0, %.preheader55.us.us.us.preheader ]
  %25 = mul i64 %.04673.us.us.us, %9
  br label %.preheader54.us.us.us.us.us

.preheader54.us.us.us.us.us:                      ; preds = %._crit_edge63.split.us.us.us.us.us.us, %.preheader55.us.us.us
  %.167.us.us.us.us.us = phi ptr [ %.074.us.us.us, %.preheader55.us.us.us ], [ %.5.us.us.us.us.us.us.3, %._crit_edge63.split.us.us.us.us.us.us ]
  %.05165.us.us.us.us.us = phi i64 [ 0, %.preheader55.us.us.us ], [ %75, %._crit_edge63.split.us.us.us.us.us.us ]
  br label %.preheader.lr.ph.us.us.us.us.us.us

.preheader.lr.ph.us.us.us.us.us.us:               ; preds = %._crit_edge.us.us.us.us.us.us, %.preheader54.us.us.us.us.us
  %.262.us.us.us.us.us.us = phi ptr [ %.167.us.us.us.us.us, %.preheader54.us.us.us.us.us ], [ %.5.us.us.us.us.us.us.3, %._crit_edge.us.us.us.us.us.us ]
  %.05061.us.us.us.us.us.us = phi i64 [ 0, %.preheader54.us.us.us.us.us ], [ %74, %._crit_edge.us.us.us.us.us.us ]
  %26 = load ptr, ptr %2, align 8, !tbaa !29
  %27 = load i64, ptr %1, align 8, !tbaa !21
  %28 = mul i64 %27, %.05165.us.us.us.us.us
  %29 = shl i64 %.05061.us.us.us.us.us.us, 2
  %30 = add i64 %28, %29
  %31 = load i64, ptr %12, align 8, !tbaa !26
  %32 = mul i64 %30, %31
  %33 = getelementptr inbounds i8, ptr %26, i64 %32
  %34 = getelementptr inbounds i8, ptr %33, i64 %25
  %35 = or disjoint i64 %29, 1
  %36 = or disjoint i64 %29, 2
  %37 = or disjoint i64 %29, 3
  br label %.preheader.us.us.us.us.us.us

38:                                               ; preds = %.preheader.us.us.us.us.us.us
  %39 = load i8, ptr %.04958.us.us.us.us.us.us, align 1, !tbaa !31
  br label %40

40:                                               ; preds = %38, %.preheader.us.us.us.us.us.us
  %storemerge.us.us.us.us.us.us = phi i8 [ %39, %38 ], [ 0, %.preheader.us.us.us.us.us.us ]
  %.5.us.us.us.us.us.us = getelementptr inbounds i8, ptr %.360.us.us.us.us.us.us, i64 1
  store i8 %storemerge.us.us.us.us.us.us, ptr %.360.us.us.us.us.us.us, align 1, !tbaa !31
  %41 = load i64, ptr %12, align 8, !tbaa !26
  %42 = icmp ult i64 %69, %41
  %43 = load i64, ptr %1, align 8
  %44 = icmp ult i64 %35, %43
  %or.cond96 = select i1 %42, i1 %44, i1 false
  br i1 %or.cond96, label %45, label %48

45:                                               ; preds = %40
  %46 = getelementptr inbounds i8, ptr %.04958.us.us.us.us.us.us, i64 %41
  %47 = load i8, ptr %46, align 1, !tbaa !31
  br label %48

48:                                               ; preds = %45, %40
  %storemerge.us.us.us.us.us.us.1 = phi i8 [ %47, %45 ], [ 0, %40 ]
  %.5.us.us.us.us.us.us.1 = getelementptr inbounds i8, ptr %.360.us.us.us.us.us.us, i64 2
  store i8 %storemerge.us.us.us.us.us.us.1, ptr %.5.us.us.us.us.us.us, align 1, !tbaa !31
  %49 = load i64, ptr %12, align 8, !tbaa !26
  %50 = icmp ult i64 %69, %49
  %51 = load i64, ptr %1, align 8
  %52 = icmp ult i64 %36, %51
  %or.cond98 = select i1 %50, i1 %52, i1 false
  br i1 %or.cond98, label %53, label %57

53:                                               ; preds = %48
  %54 = shl i64 %49, 1
  %55 = getelementptr inbounds i8, ptr %.04958.us.us.us.us.us.us, i64 %54
  %56 = load i8, ptr %55, align 1, !tbaa !31
  br label %57

57:                                               ; preds = %53, %48
  %storemerge.us.us.us.us.us.us.2 = phi i8 [ %56, %53 ], [ 0, %48 ]
  %.5.us.us.us.us.us.us.2 = getelementptr inbounds i8, ptr %.360.us.us.us.us.us.us, i64 3
  store i8 %storemerge.us.us.us.us.us.us.2, ptr %.5.us.us.us.us.us.us.1, align 1, !tbaa !31
  %58 = load i64, ptr %12, align 8, !tbaa !26
  %59 = icmp ult i64 %69, %58
  %60 = load i64, ptr %1, align 8
  %61 = icmp ult i64 %37, %60
  %or.cond100 = select i1 %59, i1 %61, i1 false
  br i1 %or.cond100, label %62, label %66

62:                                               ; preds = %57
  %63 = mul i64 %58, 3
  %64 = getelementptr inbounds i8, ptr %.04958.us.us.us.us.us.us, i64 %63
  %65 = load i8, ptr %64, align 1, !tbaa !31
  br label %66

66:                                               ; preds = %62, %57
  %storemerge.us.us.us.us.us.us.3 = phi i8 [ %65, %62 ], [ 0, %57 ]
  %.5.us.us.us.us.us.us.3 = getelementptr inbounds i8, ptr %.360.us.us.us.us.us.us, i64 4
  store i8 %storemerge.us.us.us.us.us.us.3, ptr %.5.us.us.us.us.us.us.2, align 1, !tbaa !31
  %67 = getelementptr inbounds i8, ptr %.04958.us.us.us.us.us.us, i64 1
  %68 = add nuw i64 %.04859.us.us.us.us.us.us, 1
  %exitcond.not = icmp eq i64 %68, %9
  br i1 %exitcond.not, label %._crit_edge.us.us.us.us.us.us, label %.preheader.us.us.us.us.us.us, !llvm.loop !32

.preheader.us.us.us.us.us.us:                     ; preds = %66, %.preheader.lr.ph.us.us.us.us.us.us
  %.360.us.us.us.us.us.us = phi ptr [ %.262.us.us.us.us.us.us, %.preheader.lr.ph.us.us.us.us.us.us ], [ %.5.us.us.us.us.us.us.3, %66 ]
  %.04859.us.us.us.us.us.us = phi i64 [ 0, %.preheader.lr.ph.us.us.us.us.us.us ], [ %68, %66 ]
  %.04958.us.us.us.us.us.us = phi ptr [ %34, %.preheader.lr.ph.us.us.us.us.us.us ], [ %67, %66 ]
  %69 = add i64 %.04859.us.us.us.us.us.us, %25
  %70 = load i64, ptr %12, align 8, !tbaa !26
  %71 = icmp ult i64 %69, %70
  %72 = load i64, ptr %1, align 8
  %73 = icmp ult i64 %29, %72
  %or.cond94 = select i1 %71, i1 %73, i1 false
  br i1 %or.cond94, label %38, label %40

._crit_edge.us.us.us.us.us.us:                    ; preds = %66
  %74 = add nuw i64 %.05061.us.us.us.us.us.us, 1
  %exitcond90.not = icmp eq i64 %74, %11
  br i1 %exitcond90.not, label %._crit_edge63.split.us.us.us.us.us.us, label %.preheader.lr.ph.us.us.us.us.us.us, !llvm.loop !34

._crit_edge63.split.us.us.us.us.us.us:            ; preds = %._crit_edge.us.us.us.us.us.us
  %75 = add nuw i64 %.05165.us.us.us.us.us, 1
  %exitcond91.not = icmp eq i64 %75, %19
  br i1 %exitcond91.not, label %._crit_edge.split.us.split.us.us.us.us, label %.preheader54.us.us.us.us.us, !llvm.loop !35

._crit_edge.split.us.split.us.us.us.us:           ; preds = %._crit_edge63.split.us.us.us.us.us.us
  %76 = add nuw i64 %.04673.us.us.us, 1
  %exitcond92.not = icmp eq i64 %76, %14
  br i1 %exitcond92.not, label %._crit_edge75, label %.preheader55.us.us.us, !llvm.loop !36

._crit_edge75:                                    ; preds = %._crit_edge.split.us.split.us.us.us.us, %.preheader55.lr.ph, %8
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %2, ptr noundef nonnull align 8 dereferenceable(16) %4)
          to label %77 unwind label %79

77:                                               ; preds = %._crit_edge75
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %4) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  br label %78

78:                                               ; preds = %3, %77
  ret void

79:                                               ; preds = %._crit_edge75
  %80 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %4) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  resume { ptr, i32 } %80
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

attributes #0 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 1152}
!6 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8iE", !7, i64 0, !9, i64 8, !13, i64 568, !13, i64 569, !13, i64 570, !13, i64 571, !10, i64 576, !10, i64 584, !11, i64 592, !11, i64 608, !11, i64 648, !14, i64 960, !11, i64 976, !16, i64 1008, !11, i64 1024, !11, i64 1056, !11, i64 1104, !17, i64 1152, !15, i64 1296, !15, i64 1304, !15, i64 1312, !15, i64 1320, !11, i64 1328, !19, i64 1344}
!7 = !{!"_ZTSN4Simd24SynetMergedConvolution8iE", !8, i64 0}
!8 = !{!"_ZTSN4Simd9DeletableE"}
!9 = !{!"_ZTSN4Simd15MergConvParam8iE", !10, i64 0, !11, i64 8}
!10 = !{!"long", !11, i64 0}
!11 = !{!"omnipotent char", !12, i64 0}
!12 = !{!"Simple C++ TBAA"}
!13 = !{!"bool", !11, i64 0}
!14 = !{!"_ZTSN4Simd5ArrayIhEE", !15, i64 0, !10, i64 8}
!15 = !{!"any pointer", !11, i64 0}
!16 = !{!"_ZTSN4Simd5ArrayIfEE", !15, i64 0, !10, i64 8}
!17 = !{!"_ZTSN4Simd4Base24SynetMergedConvolution8i8AlgParamE", !10, i64 0, !10, i64 8, !11, i64 16, !11, i64 40, !11, i64 64, !11, i64 88, !11, i64 104, !10, i64 128, !18, i64 136, !18, i64 140}
!18 = !{!"int", !11, i64 0}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !20, i64 0, !10, i64 8, !11, i64 16}
!20 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !15, i64 0}
!21 = !{!22, !10, i64 0}
!22 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !23, i64 24, !24, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !23, i64 56, !24, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !25, i64 152}
!23 = !{!"_ZTS18SimdTensorDataType", !11, i64 0}
!24 = !{!"_ZTS20SimdTensorFormatType", !11, i64 0}
!25 = !{!"_ZTS29SimdConvolutionActivationType", !11, i64 0}
!26 = !{!22, !10, i64 32}
!27 = !{!22, !10, i64 64}
!28 = !{!22, !10, i64 72}
!29 = !{!30, !15, i64 0}
!30 = !{!"_ZTSN4Simd5ArrayIaEE", !15, i64 0, !10, i64 8}
!31 = !{!11, !11, i64 0}
!32 = distinct !{!32, !33}
!33 = !{!"llvm.loop.mustprogress"}
!34 = distinct !{!34, !33}
!35 = distinct !{!35, !33}
!36 = distinct !{!36, !33}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass