; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution8i)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }
%"class.Simd::SynetConvolution8i" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", %"class.std::__cxx11::basic_string", ptr, %"struct.Simd::CvtParam", %"struct.Simd::CvtParam", %"struct.Simd::Array.1", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", i8, i8, i64, i64, i64 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.Simd::CvtParam" = type <{ %"struct.Simd::Array", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", i8, [3 x i8], i32, i32, i32, i32, [4 x i8] }>
%"struct.Simd::Array.0" = type { ptr, i64 }
%"class.Simd::Base::SynetConvolution8iNhwcDirect" = type { %"class.Simd::SynetConvolution8i", %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", i64, i64, %"struct.Simd::ConvParam", [3 x ptr] }
%"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam" = type { i64, i64, i64, i64, i64, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base28SynetConvolution8iNhwcDirect13ReorderWeightEv(ptr noundef nonnull align 8 dereferenceable(832) %0) #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca %"struct.Simd::Array.1", align 8
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %18 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #4
  %19 = getelementptr inbounds %"class.Simd::SynetConvolution8i", ptr %18, i32 0, i32 1
  store ptr %19, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #4
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %20, i32 0, i32 0
  %22 = load i64, ptr %21, align 8, !tbaa !9
  %23 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %22, i64 noundef 4)
  store i64 %23, ptr %4, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %24, i32 0, i32 5
  %26 = load i64, ptr %25, align 8, !tbaa !16
  %27 = getelementptr inbounds %"class.Simd::Base::SynetConvolution8iNhwcDirect", ptr %18, i32 0, i32 1
  %28 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", ptr %27, i32 0, i32 0
  %29 = load i64, ptr %28, align 8, !tbaa !17
  %30 = call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %26, i64 noundef %29)
  store i64 %30, ptr %5, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #4
  %31 = load ptr, ptr %3, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %31, i32 0, i32 10
  %33 = load i64, ptr %32, align 8, !tbaa !33
  %34 = load ptr, ptr %3, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %34, i32 0, i32 11
  %36 = load i64, ptr %35, align 8, !tbaa !34
  %37 = mul i64 %33, %36
  %38 = load i64, ptr %4, align 8, !tbaa !15
  %39 = mul i64 %37, %38
  %40 = load i64, ptr %5, align 8, !tbaa !15
  %41 = mul i64 %39, %40
  %42 = getelementptr inbounds %"class.Simd::Base::SynetConvolution8iNhwcDirect", ptr %18, i32 0, i32 1
  %43 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", ptr %42, i32 0, i32 0
  %44 = load i64, ptr %43, align 8, !tbaa !17
  %45 = mul i64 %41, %44
  %46 = mul i64 %45, 4
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %6, i64 noundef %46, i1 noundef zeroext false, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %47 = getelementptr inbounds %"struct.Simd::Array.1", ptr %6, i32 0, i32 0
  %48 = load ptr, ptr %47, align 8, !tbaa !35
  store ptr %48, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  store i64 0, ptr %8, align 8, !tbaa !15
  br label %49

49:                                               ; preds = %175, %1
  %50 = load i64, ptr %8, align 8, !tbaa !15
  %51 = load i64, ptr %5, align 8, !tbaa !15
  %52 = icmp ult i64 %50, %51
  br i1 %52, label %54, label %53

53:                                               ; preds = %49
  store i32 2, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  br label %178

54:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  store i64 0, ptr %10, align 8, !tbaa !15
  br label %55

55:                                               ; preds = %171, %54
  %56 = load i64, ptr %10, align 8, !tbaa !15
  %57 = load ptr, ptr %3, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %57, i32 0, i32 10
  %59 = load i64, ptr %58, align 8, !tbaa !33
  %60 = icmp ult i64 %56, %59
  br i1 %60, label %62, label %61

61:                                               ; preds = %55
  store i32 5, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  br label %174

62:                                               ; preds = %55
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  store i64 0, ptr %11, align 8, !tbaa !15
  br label %63

63:                                               ; preds = %167, %62
  %64 = load i64, ptr %11, align 8, !tbaa !15
  %65 = load ptr, ptr %3, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %65, i32 0, i32 11
  %67 = load i64, ptr %66, align 8, !tbaa !34
  %68 = icmp ult i64 %64, %67
  br i1 %68, label %70, label %69

69:                                               ; preds = %63
  store i32 8, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  br label %170

70:                                               ; preds = %63
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  store i64 0, ptr %12, align 8, !tbaa !15
  br label %71

71:                                               ; preds = %163, %70
  %72 = load i64, ptr %12, align 8, !tbaa !15
  %73 = load i64, ptr %4, align 8, !tbaa !15
  %74 = icmp ult i64 %72, %73
  br i1 %74, label %76, label %75

75:                                               ; preds = %71
  store i32 11, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  br label %166

76:                                               ; preds = %71
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %77 = getelementptr inbounds %"class.Simd::SynetConvolution8i", ptr %18, i32 0, i32 7
  %78 = getelementptr inbounds %"struct.Simd::Array.1", ptr %77, i32 0, i32 0
  %79 = load ptr, ptr %78, align 8, !tbaa !36
  %80 = load i64, ptr %10, align 8, !tbaa !15
  %81 = load ptr, ptr %3, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %81, i32 0, i32 11
  %83 = load i64, ptr %82, align 8, !tbaa !34
  %84 = mul i64 %80, %83
  %85 = load i64, ptr %11, align 8, !tbaa !15
  %86 = add i64 %84, %85
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %87, i32 0, i32 0
  %89 = load i64, ptr %88, align 8, !tbaa !9
  %90 = mul i64 %86, %89
  %91 = load i64, ptr %12, align 8, !tbaa !15
  %92 = mul i64 %91, 4
  %93 = add i64 %90, %92
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %94, i32 0, i32 5
  %96 = load i64, ptr %95, align 8, !tbaa !16
  %97 = mul i64 %93, %96
  %98 = getelementptr inbounds i8, ptr %79, i64 %97
  %99 = load i64, ptr %8, align 8, !tbaa !15
  %100 = getelementptr inbounds %"class.Simd::Base::SynetConvolution8iNhwcDirect", ptr %18, i32 0, i32 1
  %101 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", ptr %100, i32 0, i32 0
  %102 = load i64, ptr %101, align 8, !tbaa !17
  %103 = mul i64 %99, %102
  %104 = getelementptr inbounds i8, ptr %98, i64 %103
  store ptr %104, ptr %13, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  store i64 0, ptr %14, align 8, !tbaa !15
  br label %105

105:                                              ; preds = %159, %76
  %106 = load i64, ptr %14, align 8, !tbaa !15
  %107 = getelementptr inbounds %"class.Simd::Base::SynetConvolution8iNhwcDirect", ptr %18, i32 0, i32 1
  %108 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", ptr %107, i32 0, i32 0
  %109 = load i64, ptr %108, align 8, !tbaa !17
  %110 = icmp ult i64 %106, %109
  br i1 %110, label %112, label %111

111:                                              ; preds = %105
  store i32 14, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  br label %162

112:                                              ; preds = %105
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  store i64 0, ptr %15, align 8, !tbaa !15
  br label %113

113:                                              ; preds = %153, %112
  %114 = load i64, ptr %15, align 8, !tbaa !15
  %115 = icmp ult i64 %114, 4
  br i1 %115, label %117, label %116

116:                                              ; preds = %113
  store i32 17, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  br label %156

117:                                              ; preds = %113
  %118 = load i64, ptr %8, align 8, !tbaa !15
  %119 = getelementptr inbounds %"class.Simd::Base::SynetConvolution8iNhwcDirect", ptr %18, i32 0, i32 1
  %120 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution8iNhwcDirect::AlgParam", ptr %119, i32 0, i32 0
  %121 = load i64, ptr %120, align 8, !tbaa !17
  %122 = mul i64 %118, %121
  %123 = load i64, ptr %14, align 8, !tbaa !15
  %124 = add i64 %122, %123
  %125 = load ptr, ptr %3, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %125, i32 0, i32 5
  %127 = load i64, ptr %126, align 8, !tbaa !16
  %128 = icmp ult i64 %124, %127
  br i1 %128, label %129, label %149

129:                                              ; preds = %117
  %130 = load i64, ptr %12, align 8, !tbaa !15
  %131 = mul i64 %130, 4
  %132 = load i64, ptr %15, align 8, !tbaa !15
  %133 = add i64 %131, %132
  %134 = load ptr, ptr %3, align 8, !tbaa !5
  %135 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %134, i32 0, i32 0
  %136 = load i64, ptr %135, align 8, !tbaa !9
  %137 = icmp ult i64 %133, %136
  br i1 %137, label %138, label %149

138:                                              ; preds = %129
  %139 = load ptr, ptr %13, align 8, !tbaa !5
  %140 = load i64, ptr %15, align 8, !tbaa !15
  %141 = load ptr, ptr %3, align 8, !tbaa !5
  %142 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %141, i32 0, i32 5
  %143 = load i64, ptr %142, align 8, !tbaa !16
  %144 = mul i64 %140, %143
  %145 = getelementptr inbounds i8, ptr %139, i64 %144
  %146 = load i8, ptr %145, align 1, !tbaa !37
  %147 = load ptr, ptr %7, align 8, !tbaa !5
  %148 = getelementptr inbounds i8, ptr %147, i32 1
  store ptr %148, ptr %7, align 8, !tbaa !5
  store i8 %146, ptr %147, align 1, !tbaa !37
  br label %152

149:                                              ; preds = %129, %117
  %150 = load ptr, ptr %7, align 8, !tbaa !5
  %151 = getelementptr inbounds i8, ptr %150, i32 1
  store ptr %151, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %150, align 1, !tbaa !37
  br label %152

152:                                              ; preds = %149, %138
  br label %153

153:                                              ; preds = %152
  %154 = load i64, ptr %15, align 8, !tbaa !15
  %155 = add i64 %154, 1
  store i64 %155, ptr %15, align 8, !tbaa !15
  br label %113, !llvm.loop !38

156:                                              ; preds = %116
  %157 = load ptr, ptr %13, align 8, !tbaa !5
  %158 = getelementptr inbounds i8, ptr %157, i32 1
  store ptr %158, ptr %13, align 8, !tbaa !5
  br label %159

159:                                              ; preds = %156
  %160 = load i64, ptr %14, align 8, !tbaa !15
  %161 = add i64 %160, 1
  store i64 %161, ptr %14, align 8, !tbaa !15
  br label %105, !llvm.loop !40

162:                                              ; preds = %111
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %163

163:                                              ; preds = %162
  %164 = load i64, ptr %12, align 8, !tbaa !15
  %165 = add i64 %164, 1
  store i64 %165, ptr %12, align 8, !tbaa !15
  br label %71, !llvm.loop !41

166:                                              ; preds = %75
  br label %167

167:                                              ; preds = %166
  %168 = load i64, ptr %11, align 8, !tbaa !15
  %169 = add i64 %168, 1
  store i64 %169, ptr %11, align 8, !tbaa !15
  br label %63, !llvm.loop !42

170:                                              ; preds = %69
  br label %171

171:                                              ; preds = %170
  %172 = load i64, ptr %10, align 8, !tbaa !15
  %173 = add i64 %172, 1
  store i64 %173, ptr %10, align 8, !tbaa !15
  br label %55, !llvm.loop !43

174:                                              ; preds = %61
  br label %175

175:                                              ; preds = %174
  %176 = load i64, ptr %8, align 8, !tbaa !15
  %177 = add i64 %176, 1
  store i64 %177, ptr %8, align 8, !tbaa !15
  br label %49, !llvm.loop !44

178:                                              ; preds = %53
  %179 = getelementptr inbounds %"class.Simd::SynetConvolution8i", ptr %18, i32 0, i32 7
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %179, ptr noundef nonnull align 8 dereferenceable(16) %6)
          to label %180 unwind label %181

180:                                              ; preds = %178
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %6) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #4
  ret void

181:                                              ; preds = %178
  %182 = landingpad { ptr, i32 }
          cleanup
  %183 = extractvalue { ptr, i32 } %182, 0
  store ptr %183, ptr %16, align 8
  %184 = extractvalue { ptr, i32 } %182, 1
  store i32 %184, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %6) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #4
  br label %185

185:                                              ; preds = %181
  %186 = load ptr, ptr %16, align 8
  %187 = load i32, ptr %17, align 4
  %188 = insertvalue { ptr, i32 } poison, ptr %186, 0
  %189 = insertvalue { ptr, i32 } %188, i32 %187, 1
  resume { ptr, i32 } %189
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) #2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS25SimdConvolutionParameters", !11, i64 0, !11, i64 8, !11, i64 16, !12, i64 24, !13, i64 28, !11, i64 32, !11, i64 40, !11, i64 48, !12, i64 56, !13, i64 60, !11, i64 64, !11, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !11, i64 144, !14, i64 152}
!11 = !{!"long", !7, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!13 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!14 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!15 = !{!11, !11, i64 0}
!16 = !{!10, !11, i64 32}
!17 = !{!18, !11, i64 552}
!18 = !{!"_ZTSN4Simd4Base28SynetConvolution8iNhwcDirectE", !19, i64 0, !32, i64 552, !11, i64 608, !11, i64 616, !21, i64 624, !7, i64 808}
!19 = !{!"_ZTSN4Simd18SynetConvolution8iE", !20, i64 0, !21, i64 8, !24, i64 192, !25, i64 208, !6, i64 240, !27, i64 248, !27, i64 352, !31, i64 456, !28, i64 472, !28, i64 488, !28, i64 504, !29, i64 520, !29, i64 521, !11, i64 528, !11, i64 536, !11, i64 544}
!20 = !{!"_ZTSN4Simd9DeletableE"}
!21 = !{!"_ZTSN4Simd9ConvParamE", !10, i64 0, !22, i64 160, !11, i64 168, !23, i64 176}
!22 = !{!"_ZTS8SimdBool", !7, i64 0}
!23 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!24 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !11, i64 8}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !26, i64 0, !11, i64 8, !7, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!27 = !{!"_ZTSN4Simd8CvtParamE", !24, i64 0, !28, i64 16, !28, i64 32, !28, i64 48, !28, i64 64, !29, i64 80, !30, i64 84, !30, i64 88, !30, i64 92, !30, i64 96}
!28 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !11, i64 8}
!29 = !{!"bool", !7, i64 0}
!30 = !{!"int", !7, i64 0}
!31 = !{!"_ZTSN4Simd5ArrayIaEE", !6, i64 0, !11, i64 8}
!32 = !{!"_ZTSN4Simd4Base28SynetConvolution8iNhwcDirect8AlgParamE", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24, !11, i64 32, !30, i64 40, !30, i64 44, !30, i64 48}
!33 = !{!10, !11, i64 64}
!34 = !{!10, !11, i64 72}
!35 = !{!31, !6, i64 0}
!36 = !{!19, !6, i64 456}
!37 = !{!7, !7, i64 0}
!38 = distinct !{!38, !39}
!39 = !{!"llvm.loop.mustprogress"}
!40 = distinct !{!40, !39}
!41 = distinct !{!41, !39}
!42 = distinct !{!42, !39}
!43 = distinct !{!43, !39}
!44 = distinct !{!44, !39}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Array.1" = type { ptr, i64 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base28SynetConvolution8iNhwcDirect13ReorderWeightEv(ptr noundef nonnull align 8 dereferenceable(832) %0) local_unnamed_addr #3 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"struct.Simd::Array.1", align 8
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i64, ptr %3, align 8, !tbaa !5
  %5 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %4, i64 noundef 4)
  %6 = getelementptr inbounds i8, ptr %0, i64 40
  %7 = load i64, ptr %6, align 8, !tbaa !13
  %8 = getelementptr inbounds i8, ptr %0, i64 552
  %9 = load i64, ptr %8, align 8, !tbaa !14
  %10 = tail call noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef %7, i64 noundef %9)
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) #4
  %11 = getelementptr inbounds i8, ptr %0, i64 72
  %12 = load i64, ptr %11, align 8, !tbaa !31
  %13 = getelementptr inbounds i8, ptr %0, i64 80
  %14 = load i64, ptr %13, align 8, !tbaa !32
  %15 = load i64, ptr %8, align 8, !tbaa !14
  %16 = shl i64 %5, 2
  %17 = mul i64 %16, %10
  %18 = mul i64 %17, %12
  %19 = mul i64 %18, %14
  %20 = mul i64 %19, %15
  call void @_ZN4Simd5ArrayIaEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %2, i64 noundef %20, i1 noundef zeroext false, i64 noundef 8)
  %.not = icmp eq i64 %10, 0
  br i1 %.not, label %._crit_edge81, label %.preheader53.lr.ph

.preheader53.lr.ph:                               ; preds = %1
  %.not82 = icmp eq i64 %5, 0
  %21 = getelementptr inbounds i8, ptr %0, i64 456
  %22 = load i64, ptr %11, align 8, !tbaa !31
  %.not83 = icmp eq i64 %22, 0
  br i1 %.not83, label %._crit_edge81, label %.preheader53.preheader

.preheader53.preheader:                           ; preds = %.preheader53.lr.ph
  %23 = load ptr, ptr %2, align 8, !tbaa !33
  br label %.preheader53

.preheader53:                                     ; preds = %.preheader53.preheader, %._crit_edge
  %24 = phi i64 [ %112, %._crit_edge ], [ %22, %.preheader53.preheader ]
  %25 = phi i64 [ %113, %._crit_edge ], [ %22, %.preheader53.preheader ]
  %.080 = phi ptr [ %.1.lcssa, %._crit_edge ], [ %23, %.preheader53.preheader ]
  %.04378 = phi i64 [ %114, %._crit_edge ], [ 0, %.preheader53.preheader ]
  %.not84 = icmp eq i64 %25, 0
  br i1 %.not84, label %._crit_edge, label %.preheader52.lr.ph

.preheader52.lr.ph:                               ; preds = %.preheader53
  %26 = load i64, ptr %13, align 8, !tbaa !32
  %.not85 = icmp eq i64 %26, 0
  br i1 %.not85, label %._crit_edge, label %.preheader52

._crit_edge81:                                    ; preds = %._crit_edge, %.preheader53.lr.ph, %1
  %27 = getelementptr inbounds i8, ptr %0, i64 456
  invoke void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16) %27, ptr noundef nonnull align 8 dereferenceable(16) %2)
          to label %120 unwind label %121

.preheader52:                                     ; preds = %.preheader52.lr.ph, %._crit_edge66
  %28 = phi i64 [ %115, %._crit_edge66 ], [ %24, %.preheader52.lr.ph ]
  %29 = phi i64 [ %116, %._crit_edge66 ], [ %26, %.preheader52.lr.ph ]
  %30 = phi i64 [ %117, %._crit_edge66 ], [ %26, %.preheader52.lr.ph ]
  %.175 = phi ptr [ %.2.lcssa, %._crit_edge66 ], [ %.080, %.preheader52.lr.ph ]
  %.04972 = phi i64 [ %118, %._crit_edge66 ], [ 0, %.preheader52.lr.ph ]
  %.not86 = icmp eq i64 %30, 0
  br i1 %.not86, label %._crit_edge66, label %.preheader51.lr.ph

.preheader51.lr.ph:                               ; preds = %.preheader52
  %31 = load i64, ptr %8, align 8
  %.not87 = icmp eq i64 %31, 0
  %or.cond108 = select i1 %.not82, i1 true, i1 %.not87
  br i1 %or.cond108, label %._crit_edge66, label %.preheader51.us

.preheader51.us:                                  ; preds = %.preheader51.lr.ph, %._crit_edge61.us
  %32 = phi i64 [ %106, %._crit_edge61.us ], [ %29, %.preheader51.lr.ph ]
  %33 = phi i64 [ %107, %._crit_edge61.us ], [ %31, %.preheader51.lr.ph ]
  %34 = phi i64 [ %108, %._crit_edge61.us ], [ %31, %.preheader51.lr.ph ]
  %35 = phi i64 [ %109, %._crit_edge61.us ], [ 1, %.preheader51.lr.ph ]
  %.265.us = phi ptr [ %.us-phi.us, %._crit_edge61.us ], [ %.175, %.preheader51.lr.ph ]
  %.04863.us = phi i64 [ %110, %._crit_edge61.us ], [ 0, %.preheader51.lr.ph ]
  %.not88 = icmp eq i64 %35, 0
  br i1 %.not88, label %._crit_edge61.us, label %.lr.ph.split.us70

.lr.ph.split.us70:                                ; preds = %.preheader51.us, %._crit_edge.us
  %36 = phi i64 [ %54, %._crit_edge.us ], [ %33, %.preheader51.us ]
  %37 = phi i64 [ %55, %._crit_edge.us ], [ %34, %.preheader51.us ]
  %.360.us = phi ptr [ %.4.lcssa.us, %._crit_edge.us ], [ %.265.us, %.preheader51.us ]
  %.04759.us68 = phi i64 [ %56, %._crit_edge.us ], [ 0, %.preheader51.us ]
  %38 = shl i64 %.04759.us68, 2
  %.not89 = icmp eq i64 %37, 0
  br i1 %.not89, label %._crit_edge.us, label %.preheader.us.preheader

.preheader.us.preheader:                          ; preds = %.lr.ph.split.us70
  %39 = load ptr, ptr %21, align 8, !tbaa !34
  %40 = load i64, ptr %13, align 8, !tbaa !32
  %41 = mul i64 %40, %.04972
  %42 = add i64 %41, %.04863.us
  %43 = load i64, ptr %3, align 8, !tbaa !5
  %44 = mul i64 %42, %43
  %45 = add i64 %44, %38
  %46 = load i64, ptr %6, align 8, !tbaa !13
  %47 = mul i64 %45, %46
  %48 = getelementptr inbounds i8, ptr %39, i64 %47
  %49 = mul i64 %37, %.04378
  %50 = getelementptr inbounds i8, ptr %48, i64 %49
  %51 = or disjoint i64 %38, 1
  %52 = or disjoint i64 %38, 2
  %53 = or disjoint i64 %38, 3
  br label %.preheader.us

._crit_edge.us:                                   ; preds = %94, %.lr.ph.split.us70
  %54 = phi i64 [ %36, %.lr.ph.split.us70 ], [ %97, %94 ]
  %55 = phi i64 [ 0, %.lr.ph.split.us70 ], [ %97, %94 ]
  %.4.lcssa.us = phi ptr [ %.360.us, %.lr.ph.split.us70 ], [ %.6.us.3, %94 ]
  %56 = add nuw i64 %.04759.us68, 1
  %exitcond.not = icmp eq i64 %56, %5
  br i1 %exitcond.not, label %._crit_edge61.us.loopexit90, label %.lr.ph.split.us70, !llvm.loop !35

57:                                               ; preds = %.preheader.us
  %58 = load i8, ptr %.04656.us, align 1, !tbaa !38
  br label %59

59:                                               ; preds = %57, %.preheader.us
  %storemerge.us = phi i8 [ %58, %57 ], [ 0, %.preheader.us ]
  %.6.us = getelementptr inbounds i8, ptr %.458.us, i64 1
  store i8 %storemerge.us, ptr %.458.us, align 1, !tbaa !38
  %60 = load i64, ptr %8, align 8, !tbaa !14
  %61 = mul i64 %60, %.04378
  %62 = add i64 %61, %.04557.us
  %63 = load i64, ptr %6, align 8, !tbaa !13
  %64 = icmp ult i64 %62, %63
  %65 = load i64, ptr %3, align 8
  %66 = icmp ult i64 %51, %65
  %or.cond103 = select i1 %64, i1 %66, i1 false
  br i1 %or.cond103, label %67, label %70

67:                                               ; preds = %59
  %68 = getelementptr inbounds i8, ptr %.04656.us, i64 %63
  %69 = load i8, ptr %68, align 1, !tbaa !38
  br label %70

70:                                               ; preds = %67, %59
  %storemerge.us.1 = phi i8 [ %69, %67 ], [ 0, %59 ]
  %.6.us.1 = getelementptr inbounds i8, ptr %.458.us, i64 2
  store i8 %storemerge.us.1, ptr %.6.us, align 1, !tbaa !38
  %71 = load i64, ptr %8, align 8, !tbaa !14
  %72 = mul i64 %71, %.04378
  %73 = add i64 %72, %.04557.us
  %74 = load i64, ptr %6, align 8, !tbaa !13
  %75 = icmp ult i64 %73, %74
  %76 = load i64, ptr %3, align 8
  %77 = icmp ult i64 %52, %76
  %or.cond105 = select i1 %75, i1 %77, i1 false
  br i1 %or.cond105, label %78, label %82

78:                                               ; preds = %70
  %79 = shl i64 %74, 1
  %80 = getelementptr inbounds i8, ptr %.04656.us, i64 %79
  %81 = load i8, ptr %80, align 1, !tbaa !38
  br label %82

82:                                               ; preds = %78, %70
  %storemerge.us.2 = phi i8 [ %81, %78 ], [ 0, %70 ]
  %.6.us.2 = getelementptr inbounds i8, ptr %.458.us, i64 3
  store i8 %storemerge.us.2, ptr %.6.us.1, align 1, !tbaa !38
  %83 = load i64, ptr %8, align 8, !tbaa !14
  %84 = mul i64 %83, %.04378
  %85 = add i64 %84, %.04557.us
  %86 = load i64, ptr %6, align 8, !tbaa !13
  %87 = icmp ult i64 %85, %86
  %88 = load i64, ptr %3, align 8
  %89 = icmp ult i64 %53, %88
  %or.cond107 = select i1 %87, i1 %89, i1 false
  br i1 %or.cond107, label %90, label %94

90:                                               ; preds = %82
  %91 = mul i64 %86, 3
  %92 = getelementptr inbounds i8, ptr %.04656.us, i64 %91
  %93 = load i8, ptr %92, align 1, !tbaa !38
  br label %94

94:                                               ; preds = %90, %82
  %storemerge.us.3 = phi i8 [ %93, %90 ], [ 0, %82 ]
  %.6.us.3 = getelementptr inbounds i8, ptr %.458.us, i64 4
  store i8 %storemerge.us.3, ptr %.6.us.2, align 1, !tbaa !38
  %95 = getelementptr inbounds i8, ptr %.04656.us, i64 1
  %96 = add nuw i64 %.04557.us, 1
  %97 = load i64, ptr %8, align 8, !tbaa !14
  %98 = icmp ult i64 %96, %97
  br i1 %98, label %.preheader.us, label %._crit_edge.us, !llvm.loop !39

.preheader.us:                                    ; preds = %.preheader.us.preheader, %94
  %99 = phi i64 [ %97, %94 ], [ %36, %.preheader.us.preheader ]
  %.458.us = phi ptr [ %.6.us.3, %94 ], [ %.360.us, %.preheader.us.preheader ]
  %.04557.us = phi i64 [ %96, %94 ], [ 0, %.preheader.us.preheader ]
  %.04656.us = phi ptr [ %95, %94 ], [ %50, %.preheader.us.preheader ]
  %100 = mul i64 %99, %.04378
  %101 = add i64 %100, %.04557.us
  %102 = load i64, ptr %6, align 8, !tbaa !13
  %103 = icmp ult i64 %101, %102
  %104 = load i64, ptr %3, align 8
  %105 = icmp ult i64 %38, %104
  %or.cond = select i1 %103, i1 %105, i1 false
  br i1 %or.cond, label %57, label %59

._crit_edge61.us.loopexit90:                      ; preds = %._crit_edge.us
  %.pre = load i64, ptr %13, align 8, !tbaa !32
  br label %._crit_edge61.us

._crit_edge61.us:                                 ; preds = %.preheader51.us, %._crit_edge61.us.loopexit90
  %106 = phi i64 [ %.pre, %._crit_edge61.us.loopexit90 ], [ %32, %.preheader51.us ]
  %107 = phi i64 [ %54, %._crit_edge61.us.loopexit90 ], [ %33, %.preheader51.us ]
  %108 = phi i64 [ %55, %._crit_edge61.us.loopexit90 ], [ %34, %.preheader51.us ]
  %109 = phi i64 [ %55, %._crit_edge61.us.loopexit90 ], [ 0, %.preheader51.us ]
  %.us-phi.us = phi ptr [ %.4.lcssa.us, %._crit_edge61.us.loopexit90 ], [ %.265.us, %.preheader51.us ]
  %110 = add nuw i64 %.04863.us, 1
  %111 = icmp ult i64 %110, %106
  br i1 %111, label %.preheader51.us, label %._crit_edge66.loopexit92, !llvm.loop !40

._crit_edge:                                      ; preds = %._crit_edge66, %.preheader52.lr.ph, %.preheader53
  %112 = phi i64 [ %24, %.preheader53 ], [ %24, %.preheader52.lr.ph ], [ %115, %._crit_edge66 ]
  %113 = phi i64 [ 0, %.preheader53 ], [ %25, %.preheader52.lr.ph ], [ %115, %._crit_edge66 ]
  %.1.lcssa = phi ptr [ %.080, %.preheader53 ], [ %.080, %.preheader52.lr.ph ], [ %.2.lcssa, %._crit_edge66 ]
  %114 = add nuw i64 %.04378, 1
  %exitcond95.not = icmp eq i64 %114, %10
  br i1 %exitcond95.not, label %._crit_edge81, label %.preheader53, !llvm.loop !41

._crit_edge66.loopexit92:                         ; preds = %._crit_edge61.us
  %.pre96 = load i64, ptr %11, align 8, !tbaa !31
  br label %._crit_edge66

._crit_edge66:                                    ; preds = %.preheader51.lr.ph, %._crit_edge66.loopexit92, %.preheader52
  %115 = phi i64 [ %28, %.preheader52 ], [ %.pre96, %._crit_edge66.loopexit92 ], [ %28, %.preheader51.lr.ph ]
  %116 = phi i64 [ %29, %.preheader52 ], [ %106, %._crit_edge66.loopexit92 ], [ %29, %.preheader51.lr.ph ]
  %117 = phi i64 [ 0, %.preheader52 ], [ %106, %._crit_edge66.loopexit92 ], [ %30, %.preheader51.lr.ph ]
  %.2.lcssa = phi ptr [ %.175, %.preheader52 ], [ %.us-phi.us, %._crit_edge66.loopexit92 ], [ %.175, %.preheader51.lr.ph ]
  %118 = add nuw i64 %.04972, 1
  %119 = icmp ult i64 %118, %115
  br i1 %119, label %.preheader52, label %._crit_edge, !llvm.loop !42

120:                                              ; preds = %._crit_edge81
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %2) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) #4
  ret void

121:                                              ; preds = %._crit_edge81
  %122 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN4Simd5ArrayIaED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %2) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) #4
  resume { ptr, i32 } %122
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd5DivHiEmm(i64 noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIaE4SwapERKS1_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !10, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !12, i64 152}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!11 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!12 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!13 = !{!6, !7, i64 32}
!14 = !{!15, !7, i64 552}
!15 = !{!"_ZTSN4Simd4Base28SynetConvolution8iNhwcDirectE", !16, i64 0, !30, i64 552, !7, i64 608, !7, i64 616, !18, i64 624, !8, i64 808}
!16 = !{!"_ZTSN4Simd18SynetConvolution8iE", !17, i64 0, !18, i64 8, !21, i64 192, !23, i64 208, !22, i64 240, !25, i64 248, !25, i64 352, !29, i64 456, !26, i64 472, !26, i64 488, !26, i64 504, !27, i64 520, !27, i64 521, !7, i64 528, !7, i64 536, !7, i64 544}
!17 = !{!"_ZTSN4Simd9DeletableE"}
!18 = !{!"_ZTSN4Simd9ConvParamE", !6, i64 0, !19, i64 160, !7, i64 168, !20, i64 176}
!19 = !{!"_ZTS8SimdBool", !8, i64 0}
!20 = !{!"_ZTS26SimdSynetCompatibilityType", !8, i64 0}
!21 = !{!"_ZTSN4Simd5ArrayIhEE", !22, i64 0, !7, i64 8}
!22 = !{!"any pointer", !8, i64 0}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !7, i64 8, !8, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !22, i64 0}
!25 = !{!"_ZTSN4Simd8CvtParamE", !21, i64 0, !26, i64 16, !26, i64 32, !26, i64 48, !26, i64 64, !27, i64 80, !28, i64 84, !28, i64 88, !28, i64 92, !28, i64 96}
!26 = !{!"_ZTSN4Simd5ArrayIfEE", !22, i64 0, !7, i64 8}
!27 = !{!"bool", !8, i64 0}
!28 = !{!"int", !8, i64 0}
!29 = !{!"_ZTSN4Simd5ArrayIaEE", !22, i64 0, !7, i64 8}
!30 = !{!"_ZTSN4Simd4Base28SynetConvolution8iNhwcDirect8AlgParamE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !28, i64 40, !28, i64 44, !28, i64 48}
!31 = !{!6, !7, i64 64}
!32 = !{!6, !7, i64 72}
!33 = !{!29, !22, i64 0}
!34 = !{!16, !22, i64 456}
!35 = distinct !{!35, !36, !37}
!36 = !{!"llvm.loop.mustprogress"}
!37 = !{!"llvm.loop.unswitch.partial.disable"}
!38 = !{!8, !8, i64 0}
!39 = distinct !{!39, !36}
!40 = distinct !{!40, !36, !37}
!41 = distinct !{!41, !36, !37}
!42 = distinct !{!42, !36, !37}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass