; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_rex_vcompute_mem_1reg_general.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

declare void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

; Function Attrs: nounwind uwtable
define dso_local void @test_rex_vcompute_mem_1reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i16 noundef zeroext %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i16, align 2
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca [3 x i32], align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i8, align 1
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i16 %3, ptr %8, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  store i32 2, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 12, ptr %12) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %12, ptr align 4 @__const.test_rex_vcompute_mem_1reg_general.displ, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %15) #4
  store i8 120, ptr %15, align 1, !tbaa !13
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %16, ptr noundef %17)
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %49, %4
  %19 = load i32, ptr %10, align 4, !tbaa !9
  %20 = icmp ult i32 %19, 16
  br i1 %20, label %21, label %52

21:                                               ; preds = %18
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %45, %21
  %23 = load i32, ptr %14, align 4, !tbaa !9
  %24 = icmp ult i32 %23, 16
  br i1 %24, label %25, label %48

25:                                               ; preds = %22
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %26

26:                                               ; preds = %41, %25
  %27 = load i32, ptr %13, align 4, !tbaa !9
  %28 = icmp ult i32 %27, 3
  br i1 %28, label %29, label %44

29:                                               ; preds = %26
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = load i32, ptr %7, align 4, !tbaa !9
  %32 = load i8, ptr %15, align 1, !tbaa !13
  %33 = load i32, ptr %10, align 4, !tbaa !9
  %34 = load i32, ptr %13, align 4, !tbaa !9
  %35 = zext i32 %34 to i64
  %36 = getelementptr inbounds [3 x i32], ptr %12, i64 0, i64 %35
  %37 = load i32, ptr %36, align 4, !tbaa !9
  %38 = load i32, ptr %14, align 4, !tbaa !9
  %39 = load i16, ptr %8, align 2, !tbaa !11
  %40 = zext i16 %39 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %30, i32 noundef %31, i8 noundef signext %32, i32 noundef %33, i32 noundef 127, i32 noundef 0, i32 noundef %37, i32 noundef 0, i32 noundef 255, i32 noundef %38, i32 noundef 0, i32 noundef 0, i32 noundef %40)
  br label %41

41:                                               ; preds = %29
  %42 = load i32, ptr %13, align 4, !tbaa !9
  %43 = add i32 %42, 1
  store i32 %43, ptr %13, align 4, !tbaa !9
  br label %26, !llvm.loop !14

44:                                               ; preds = %26
  br label %45

45:                                               ; preds = %44
  %46 = load i32, ptr %14, align 4, !tbaa !9
  %47 = add i32 %46, 1
  store i32 %47, ptr %14, align 4, !tbaa !9
  br label %22, !llvm.loop !16

48:                                               ; preds = %22
  br label %49

49:                                               ; preds = %48
  %50 = load i32, ptr %10, align 4, !tbaa !9
  %51 = add i32 %50, 1
  store i32 %51, ptr %10, align 4, !tbaa !9
  br label %18, !llvm.loop !17

52:                                               ; preds = %18
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %53

53:                                               ; preds = %94, %52
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = icmp ult i32 %54, 16
  br i1 %55, label %56, label %97

56:                                               ; preds = %53
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %90, %56
  %58 = load i32, ptr %9, align 4, !tbaa !9
  %59 = icmp ult i32 %58, 16
  br i1 %59, label %60, label %93

60:                                               ; preds = %57
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %61

61:                                               ; preds = %86, %60
  %62 = load i32, ptr %14, align 4, !tbaa !9
  %63 = icmp ult i32 %62, 16
  br i1 %63, label %64, label %89

64:                                               ; preds = %61
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %82, %64
  %66 = load i32, ptr %13, align 4, !tbaa !9
  %67 = icmp ult i32 %66, 3
  br i1 %67, label %68, label %85

68:                                               ; preds = %65
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  %70 = load i32, ptr %7, align 4, !tbaa !9
  %71 = load i8, ptr %15, align 1, !tbaa !13
  %72 = load i32, ptr %10, align 4, !tbaa !9
  %73 = load i32, ptr %9, align 4, !tbaa !9
  %74 = load i32, ptr %11, align 4, !tbaa !9
  %75 = load i32, ptr %13, align 4, !tbaa !9
  %76 = zext i32 %75 to i64
  %77 = getelementptr inbounds [3 x i32], ptr %12, i64 0, i64 %76
  %78 = load i32, ptr %77, align 4, !tbaa !9
  %79 = load i32, ptr %14, align 4, !tbaa !9
  %80 = load i16, ptr %8, align 2, !tbaa !11
  %81 = zext i16 %80 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %69, i32 noundef %70, i8 noundef signext %71, i32 noundef %72, i32 noundef %73, i32 noundef %74, i32 noundef %78, i32 noundef 0, i32 noundef 255, i32 noundef %79, i32 noundef 0, i32 noundef 0, i32 noundef %81)
  br label %82

82:                                               ; preds = %68
  %83 = load i32, ptr %13, align 4, !tbaa !9
  %84 = add i32 %83, 1
  store i32 %84, ptr %13, align 4, !tbaa !9
  br label %65, !llvm.loop !18

85:                                               ; preds = %65
  br label %86

86:                                               ; preds = %85
  %87 = load i32, ptr %14, align 4, !tbaa !9
  %88 = add i32 %87, 1
  store i32 %88, ptr %14, align 4, !tbaa !9
  br label %61, !llvm.loop !19

89:                                               ; preds = %61
  br label %90

90:                                               ; preds = %89
  %91 = load i32, ptr %9, align 4, !tbaa !9
  %92 = add i32 %91, 1
  store i32 %92, ptr %9, align 4, !tbaa !9
  br label %57, !llvm.loop !20

93:                                               ; preds = %57
  br label %94

94:                                               ; preds = %93
  %95 = load i32, ptr %10, align 4, !tbaa !9
  %96 = add i32 %95, 1
  store i32 %96, ptr %10, align 4, !tbaa !9
  br label %53, !llvm.loop !21

97:                                               ; preds = %53
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  %99 = load ptr, ptr %5, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %98, ptr noundef %99)
  call void @llvm.lifetime.end.p0(i64 1, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}
!19 = distinct !{!19, !15}
!20 = distinct !{!20, !15}
!21 = distinct !{!21, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_rex_vcompute_mem_1reg_general.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @test_rex_vcompute_mem_1reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i16 noundef zeroext %3) local_unnamed_addr #0 {
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %5 = zext i16 %3 to i32
  %.pre.pre = load i32, ptr @__const.test_rex_vcompute_mem_1reg_general.displ, align 4, !tbaa !5
  %.pre57.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_rex_vcompute_mem_1reg_general.displ, i64 4), align 4, !tbaa !5
  %.pre58.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_rex_vcompute_mem_1reg_general.displ, i64 8), align 4, !tbaa !5
  br label %.preheader42

.preheader42:                                     ; preds = %4, %7
  %.03645 = phi i32 [ 0, %4 ], [ %8, %7 ]
  br label %.preheader41

.preheader41:                                     ; preds = %.preheader42, %.preheader41
  %.03344 = phi i32 [ 0, %.preheader42 ], [ %6, %.preheader41 ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.03645, i32 noundef 127, i32 noundef 0, i32 noundef %.pre.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.03344, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.03645, i32 noundef 127, i32 noundef 0, i32 noundef %.pre57.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.03344, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.03645, i32 noundef 127, i32 noundef 0, i32 noundef %.pre58.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.03344, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  %6 = add nuw nsw i32 %.03344, 1
  %exitcond.not = icmp eq i32 %6, 16
  br i1 %exitcond.not, label %7, label %.preheader41, !llvm.loop !9

7:                                                ; preds = %.preheader41
  %8 = add nuw nsw i32 %.03645, 1
  %exitcond51.not = icmp eq i32 %8, 16
  br i1 %exitcond51.not, label %.preheader39, label %.preheader42, !llvm.loop !11

.preheader39:                                     ; preds = %7, %12
  %.13749 = phi i32 [ %13, %12 ], [ 0, %7 ]
  br label %.preheader38

.preheader38:                                     ; preds = %.preheader39, %10
  %.048 = phi i32 [ 0, %.preheader39 ], [ %11, %10 ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader38, %.preheader
  %.147 = phi i32 [ 0, %.preheader38 ], [ %9, %.preheader ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.13749, i32 noundef %.048, i32 noundef 2, i32 noundef %.pre.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.147, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.13749, i32 noundef %.048, i32 noundef 2, i32 noundef %.pre57.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.147, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 120, i32 noundef %.13749, i32 noundef %.048, i32 noundef 2, i32 noundef %.pre58.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.147, i32 noundef 0, i32 noundef 0, i32 noundef %5) #2
  %9 = add nuw nsw i32 %.147, 1
  %exitcond54.not = icmp eq i32 %9, 16
  br i1 %exitcond54.not, label %10, label %.preheader, !llvm.loop !12

10:                                               ; preds = %.preheader
  %11 = add nuw nsw i32 %.048, 1
  %exitcond55.not = icmp eq i32 %11, 16
  br i1 %exitcond55.not, label %12, label %.preheader38, !llvm.loop !13

12:                                               ; preds = %10
  %13 = add nuw nsw i32 %.13749, 1
  %exitcond56.not = icmp eq i32 %13, 16
  br i1 %exitcond56.not, label %14, label %.preheader39, !llvm.loop !14

14:                                               ; preds = %12
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass