; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution8i)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::CvtParam" = type <{ %"struct.Simd::Array", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", %"struct.Simd::Array.0", i8, [3 x i8], i32, i32, i32, i32, [4 x i8] }>
%"struct.Simd::Array" = type { ptr, i64 }
%"struct.Simd::Array.0" = type { ptr, i64 }

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [88 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType = external hidden unnamed_addr constant [92 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(100) %0, ptr noundef %1, ptr noundef %2, i64 noundef %3, i32 noundef %4) #0 align 2 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca float, align 4
  %14 = alloca float, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i64 %3, ptr %9, align 8, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !11
  %15 = load ptr, ptr %6, align 8
  %16 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 0
  %17 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIhE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %16, i64 noundef %17, i1 noundef zeroext false, i64 noundef 8)
  %18 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 1
  %19 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %18, i64 noundef %19, i1 noundef zeroext false, i64 noundef 8)
  %20 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 2
  %21 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %20, i64 noundef %21, i1 noundef zeroext false, i64 noundef 8)
  %22 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 3
  %23 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %22, i64 noundef %23, i1 noundef zeroext false, i64 noundef 8)
  %24 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 4
  %25 = load i64, ptr %9, align 8, !tbaa !9
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %24, i64 noundef %25, i1 noundef zeroext false, i64 noundef 8)
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #7
  store i64 0, ptr %11, align 8, !tbaa !9
  br label %26

26:                                               ; preds = %53, %5
  %27 = load i64, ptr %11, align 8, !tbaa !9
  %28 = load i64, ptr %9, align 8, !tbaa !9
  %29 = icmp ult i64 %27, %28
  br i1 %29, label %31, label %30

30:                                               ; preds = %26
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #7
  br label %56

31:                                               ; preds = %26
  %32 = load ptr, ptr %7, align 8, !tbaa !5
  %33 = load i64, ptr %11, align 8, !tbaa !9
  %34 = getelementptr inbounds float, ptr %32, i64 %33
  %35 = load float, ptr %34, align 4, !tbaa !13
  %36 = load ptr, ptr %8, align 8, !tbaa !5
  %37 = load i64, ptr %11, align 8, !tbaa !9
  %38 = getelementptr inbounds float, ptr %36, i64 %37
  %39 = load float, ptr %38, align 4, !tbaa !13
  %40 = fcmp ole float %35, %39
  br i1 %40, label %41, label %42

41:                                               ; preds = %31
  br label %44

42:                                               ; preds = %31
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 44, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType) #8
  unreachable

43:                                               ; No predecessors!
  br label %44

44:                                               ; preds = %43, %41
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = load i64, ptr %11, align 8, !tbaa !9
  %47 = getelementptr inbounds float, ptr %45, i64 %46
  %48 = load float, ptr %47, align 4, !tbaa !13
  %49 = fcmp olt float %48, 0.000000e+00
  br i1 %49, label %50, label %52

50:                                               ; preds = %44
  %51 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 5
  store i8 1, ptr %51, align 8, !tbaa !15
  br label %52

52:                                               ; preds = %50, %44
  br label %53

53:                                               ; preds = %52
  %54 = load i64, ptr %11, align 8, !tbaa !9
  %55 = add i64 %54, 1
  store i64 %55, ptr %11, align 8, !tbaa !9
  br label %26, !llvm.loop !21

56:                                               ; preds = %30
  %57 = load i32, ptr %10, align 4, !tbaa !11
  %58 = call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %57)
  %59 = zext i1 %58 to i64
  %60 = select i1 %58, i32 0, i32 0
  %61 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 9
  store i32 %60, ptr %61, align 4, !tbaa !23
  %62 = load i32, ptr %10, align 4, !tbaa !11
  %63 = call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %62)
  %64 = zext i1 %63 to i64
  %65 = select i1 %63, i32 180, i32 255
  %66 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 10
  store i32 %65, ptr %66, align 8, !tbaa !24
  %67 = load i32, ptr %10, align 4, !tbaa !11
  %68 = call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %67)
  %69 = zext i1 %68 to i64
  %70 = select i1 %68, i32 -90, i32 -128
  %71 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 7
  store i32 %70, ptr %71, align 4, !tbaa !25
  %72 = load i32, ptr %10, align 4, !tbaa !11
  %73 = call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %72)
  %74 = zext i1 %73 to i64
  %75 = select i1 %73, i32 90, i32 127
  %76 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 8
  store i32 %75, ptr %76, align 8, !tbaa !26
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #7
  store i64 0, ptr %12, align 8, !tbaa !9
  br label %77

77:                                               ; preds = %160, %56
  %78 = load i64, ptr %12, align 8, !tbaa !9
  %79 = load i64, ptr %9, align 8, !tbaa !9
  %80 = icmp ult i64 %78, %79
  br i1 %80, label %82, label %81

81:                                               ; preds = %77
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #7
  br label %163

82:                                               ; preds = %77
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #7
  %83 = load ptr, ptr %7, align 8, !tbaa !5
  %84 = load i64, ptr %12, align 8, !tbaa !9
  %85 = getelementptr inbounds float, ptr %83, i64 %84
  %86 = load float, ptr %85, align 4, !tbaa !13
  %87 = call noundef float @_ZSt4fabsf(float noundef %86)
  %88 = load ptr, ptr %8, align 8, !tbaa !5
  %89 = load i64, ptr %12, align 8, !tbaa !9
  %90 = getelementptr inbounds float, ptr %88, i64 %89
  %91 = load float, ptr %90, align 4, !tbaa !13
  %92 = call noundef float @_ZSt4fabsf(float noundef %91)
  %93 = call noundef float @_ZSt4fmaxff(float noundef %87, float noundef %92)
  store float %93, ptr %13, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #7
  %94 = load float, ptr %13, align 4, !tbaa !13
  %95 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 5
  %96 = load i8, ptr %95, align 8, !tbaa !15, !range !27, !noundef !28
  %97 = trunc i8 %96 to i1
  br i1 %97, label %98, label %101

98:                                               ; preds = %82
  %99 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 8
  %100 = load i32, ptr %99, align 8, !tbaa !26
  br label %104

101:                                              ; preds = %82
  %102 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 10
  %103 = load i32, ptr %102, align 8, !tbaa !24
  br label %104

104:                                              ; preds = %101, %98
  %105 = phi i32 [ %100, %98 ], [ %103, %101 ]
  %106 = sitofp i32 %105 to float
  %107 = fdiv float %94, %106
  store float %107, ptr %14, align 4, !tbaa !13
  %108 = load float, ptr %14, align 4, !tbaa !13
  %109 = call noundef float @_ZSt4fabsf(float noundef %108)
  %110 = fpext float %109 to double
  %111 = fcmp olt double %110, 0x3E7AD7F29ABCAF48
  br i1 %111, label %112, label %113

112:                                              ; preds = %104
  store float 1.000000e+00, ptr %14, align 4, !tbaa !13
  br label %113

113:                                              ; preds = %112, %104
  %114 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 5
  %115 = load i8, ptr %114, align 8, !tbaa !15, !range !27, !noundef !28
  %116 = trunc i8 %115 to i1
  br i1 %116, label %117, label %121

117:                                              ; preds = %113
  %118 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 7
  %119 = load i32, ptr %118, align 4, !tbaa !25
  %120 = sub nsw i32 0, %119
  br label %124

121:                                              ; preds = %113
  %122 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 9
  %123 = load i32, ptr %122, align 4, !tbaa !23
  br label %124

124:                                              ; preds = %121, %117
  %125 = phi i32 [ %120, %117 ], [ %123, %121 ]
  %126 = trunc i32 %125 to i8
  %127 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 0
  %128 = load i64, ptr %12, align 8, !tbaa !9
  %129 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %127, i64 noundef %128)
  store i8 %126, ptr %129, align 1, !tbaa !29
  %130 = load float, ptr %14, align 4, !tbaa !13
  %131 = fpext float %130 to double
  %132 = fdiv double 1.000000e+00, %131
  %133 = fptrunc double %132 to float
  %134 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 1
  %135 = load i64, ptr %12, align 8, !tbaa !9
  %136 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %134, i64 noundef %135)
  store float %133, ptr %136, align 4, !tbaa !13
  %137 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 0
  %138 = load i64, ptr %12, align 8, !tbaa !9
  %139 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %137, i64 noundef %138)
  %140 = load i8, ptr %139, align 1, !tbaa !29
  %141 = uitofp i8 %140 to float
  %142 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 2
  %143 = load i64, ptr %12, align 8, !tbaa !9
  %144 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %142, i64 noundef %143)
  store float %141, ptr %144, align 4, !tbaa !13
  %145 = load float, ptr %14, align 4, !tbaa !13
  %146 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 3
  %147 = load i64, ptr %12, align 8, !tbaa !9
  %148 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %146, i64 noundef %147)
  store float %145, ptr %148, align 4, !tbaa !13
  %149 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 0
  %150 = load i64, ptr %12, align 8, !tbaa !9
  %151 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %149, i64 noundef %150)
  %152 = load i8, ptr %151, align 1, !tbaa !29
  %153 = uitofp i8 %152 to float
  %154 = fneg float %153
  %155 = load float, ptr %14, align 4, !tbaa !13
  %156 = fmul float %154, %155
  %157 = getelementptr inbounds %"struct.Simd::CvtParam", ptr %15, i32 0, i32 4
  %158 = load i64, ptr %12, align 8, !tbaa !9
  %159 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %157, i64 noundef %158)
  store float %156, ptr %159, align 4, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #7
  br label %160

160:                                              ; preds = %124
  %161 = load i64, ptr %12, align 8, !tbaa !9
  %162 = add i64 %161, 1
  store i64 %162, ptr %12, align 8, !tbaa !9
  br label %77, !llvm.loop !30

163:                                              ; preds = %81
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIhE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #1 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef) #4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt4fmaxff(float noundef, float noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt4fabsf(float noundef) #6

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) #4 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) #4 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }
attributes #8 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"float", !7, i64 0}
!15 = !{!16, !19, i64 80}
!16 = !{!"_ZTSN4Simd8CvtParamE", !17, i64 0, !18, i64 16, !18, i64 32, !18, i64 48, !18, i64 64, !19, i64 80, !20, i64 84, !20, i64 88, !20, i64 92, !20, i64 96}
!17 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !10, i64 8}
!18 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !10, i64 8}
!19 = !{!"bool", !7, i64 0}
!20 = !{!"int", !7, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!16, !20, i64 92}
!24 = !{!16, !20, i64 96}
!25 = !{!16, !20, i64 84}
!26 = !{!16, !20, i64 88}
!27 = !{i8 0, i8 2}
!28 = !{}
!29 = !{!7, !7, i64 0}
!30 = distinct !{!30, !22}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [88 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType = external hidden unnamed_addr constant [92 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(100) %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, i64 noundef %3, i32 noundef %4) local_unnamed_addr #0 align 2 {
  tail call void @_ZN4Simd5ArrayIhE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef %3, i1 noundef zeroext false, i64 noundef 8)
  %6 = getelementptr inbounds i8, ptr %0, i64 16
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %6, i64 noundef %3, i1 noundef zeroext false, i64 noundef 8)
  %7 = getelementptr inbounds i8, ptr %0, i64 32
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %7, i64 noundef %3, i1 noundef zeroext false, i64 noundef 8)
  %8 = getelementptr inbounds i8, ptr %0, i64 48
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %8, i64 noundef %3, i1 noundef zeroext false, i64 noundef 8)
  %9 = getelementptr inbounds i8, ptr %0, i64 64
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %9, i64 noundef %3, i1 noundef zeroext false, i64 noundef 8)
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %5
  %10 = getelementptr inbounds i8, ptr %0, i64 80
  br label %23

._crit_edge:                                      ; preds = %33, %5
  %11 = tail call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %4)
  %12 = getelementptr inbounds i8, ptr %0, i64 92
  store i32 0, ptr %12, align 4, !tbaa !5
  %13 = tail call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %4)
  %14 = select i1 %13, i32 180, i32 255
  %15 = getelementptr inbounds i8, ptr %0, i64 96
  store i32 %14, ptr %15, align 8, !tbaa !15
  %16 = tail call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %4)
  %17 = select i1 %16, i32 -90, i32 -128
  %18 = getelementptr inbounds i8, ptr %0, i64 84
  store i32 %17, ptr %18, align 4, !tbaa !16
  %19 = tail call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %4)
  %20 = select i1 %19, i32 90, i32 127
  %21 = getelementptr inbounds i8, ptr %0, i64 88
  store i32 %20, ptr %21, align 8, !tbaa !17
  br i1 %.not, label %._crit_edge46, label %.lr.ph45

.lr.ph45:                                         ; preds = %._crit_edge
  %22 = getelementptr inbounds i8, ptr %0, i64 80
  br label %35

23:                                               ; preds = %.lr.ph, %33
  %.03742 = phi i64 [ 0, %.lr.ph ], [ %34, %33 ]
  %24 = getelementptr inbounds float, ptr %1, i64 %.03742
  %25 = load float, ptr %24, align 4, !tbaa !18
  %26 = getelementptr inbounds float, ptr %2, i64 %.03742
  %27 = load float, ptr %26, align 4, !tbaa !18
  %28 = fcmp ugt float %25, %27
  br i1 %28, label %29, label %30

29:                                               ; preds = %23
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 44, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd8CvtParam4InitEPKfS2_m26SimdSynetCompatibilityType) #6
  unreachable

30:                                               ; preds = %23
  %31 = fcmp olt float %25, 0.000000e+00
  br i1 %31, label %32, label %33

32:                                               ; preds = %30
  store i8 1, ptr %10, align 8, !tbaa !20
  br label %33

33:                                               ; preds = %30, %32
  %34 = add nuw i64 %.03742, 1
  %exitcond.not = icmp eq i64 %34, %3
  br i1 %exitcond.not, label %._crit_edge, label %23, !llvm.loop !21

._crit_edge46:                                    ; preds = %35, %._crit_edge
  ret void

35:                                               ; preds = %.lr.ph45, %35
  %.03843 = phi i64 [ 0, %.lr.ph45 ], [ %72, %35 ]
  %36 = getelementptr inbounds float, ptr %1, i64 %.03843
  %37 = load float, ptr %36, align 4, !tbaa !18
  %38 = tail call noundef float @_ZSt4fabsf(float noundef %37)
  %39 = getelementptr inbounds float, ptr %2, i64 %.03843
  %40 = load float, ptr %39, align 4, !tbaa !18
  %41 = tail call noundef float @_ZSt4fabsf(float noundef %40)
  %42 = tail call noundef float @_ZSt4fmaxff(float noundef %38, float noundef %41)
  %43 = load i8, ptr %22, align 8, !tbaa !20, !range !23, !noundef !24
  %44 = trunc nuw i8 %43 to i1
  %.val = load i32, ptr %21, align 8
  %.val41 = load i32, ptr %15, align 8
  %45 = select i1 %44, i32 %.val, i32 %.val41
  %46 = sitofp i32 %45 to float
  %47 = fdiv float %42, %46
  %48 = tail call noundef float @_ZSt4fabsf(float noundef %47)
  %49 = fpext float %48 to double
  %50 = fcmp olt double %49, 0x3E7AD7F29ABCAF48
  %.0 = select i1 %50, float 1.000000e+00, float %47
  %51 = load i8, ptr %22, align 8, !tbaa !20, !range !23, !noundef !24
  %52 = trunc nuw i8 %51 to i1
  %53 = load i32, ptr %18, align 4
  %54 = sub nsw i32 0, %53
  %55 = load i32, ptr %12, align 4
  %56 = select i1 %52, i32 %54, i32 %55
  %57 = trunc i32 %56 to i8
  %58 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef %.03843)
  store i8 %57, ptr %58, align 1, !tbaa !25
  %59 = fdiv float 1.000000e+00, %.0
  %60 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %6, i64 noundef %.03843)
  store float %59, ptr %60, align 4, !tbaa !18
  %61 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef %.03843)
  %62 = load i8, ptr %61, align 1, !tbaa !25
  %63 = uitofp i8 %62 to float
  %64 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %7, i64 noundef %.03843)
  store float %63, ptr %64, align 4, !tbaa !18
  %65 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %8, i64 noundef %.03843)
  store float %.0, ptr %65, align 4, !tbaa !18
  %66 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef %.03843)
  %67 = load i8, ptr %66, align 1, !tbaa !25
  %68 = uitofp i8 %67 to float
  %69 = fneg float %68
  %70 = fmul float %.0, %69
  %71 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16) %9, i64 noundef %.03843)
  store float %70, ptr %71, align 4, !tbaa !18
  %72 = add nuw i64 %.03843, 1
  %exitcond48.not = icmp eq i64 %72, %3
  br i1 %exitcond48.not, label %._crit_edge46, label %35, !llvm.loop !26
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIhE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt4fmaxff(float noundef, float noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef float @_ZSt4fabsf(float noundef) local_unnamed_addr #5

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd5ArrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) local_unnamed_addr #3 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZN4Simd5ArrayIfEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) local_unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 92}
!6 = !{!"_ZTSN4Simd8CvtParamE", !7, i64 0, !12, i64 16, !12, i64 32, !12, i64 48, !12, i64 64, !13, i64 80, !14, i64 84, !14, i64 88, !14, i64 92, !14, i64 96}
!7 = !{!"_ZTSN4Simd5ArrayIhEE", !8, i64 0, !11, i64 8}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"long", !9, i64 0}
!12 = !{!"_ZTSN4Simd5ArrayIfEE", !8, i64 0, !11, i64 8}
!13 = !{!"bool", !9, i64 0}
!14 = !{!"int", !9, i64 0}
!15 = !{!6, !14, i64 96}
!16 = !{!6, !14, i64 84}
!17 = !{!6, !14, i64 88}
!18 = !{!19, !19, i64 0}
!19 = !{!"float", !9, i64 0}
!20 = !{!6, !13, i64 80}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{i8 0, i8 2}
!24 = !{}
!25 = !{!9, !9, i64 0}
!26 = distinct !{!26, !22}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass