; LLVM IR from abeaumont/competitive-programming :: codechef/sept18a/photocom.ll (Z1riiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@m = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z1riiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca i64, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  %10 = load i32, ptr %6, align 4, !tbaa !5
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %23

12:                                               ; preds = %4
  %13 = load i32, ptr %8, align 4, !tbaa !5
  %14 = icmp eq i32 %13, 0
  br i1 %14, label %15, label %23

15:                                               ; preds = %12
  %16 = load i32, ptr %7, align 4, !tbaa !5
  %17 = sext i32 %16 to i64
  %18 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %17) #1
  %19 = load i32, ptr %9, align 4, !tbaa !5
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %20) #1
  %22 = load i64, ptr %21, align 8, !tbaa !9
  store i64 %22, ptr %5, align 8
  br label %99

23:                                               ; preds = %12, %4
  %24 = load i32, ptr %6, align 4, !tbaa !5
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %43

26:                                               ; preds = %23
  %27 = load i32, ptr %7, align 4, !tbaa !5
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %28) #1
  %30 = load i32, ptr %9, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #1
  %33 = load i64, ptr %32, align 8, !tbaa !9
  %34 = load i32, ptr %7, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %35) #1
  %37 = load i32, ptr %8, align 4, !tbaa !5
  %38 = sub nsw i32 %37, 1
  %39 = sext i32 %38 to i64
  %40 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %39) #1
  %41 = load i64, ptr %40, align 8, !tbaa !9
  %42 = sub nsw i64 %33, %41
  store i64 %42, ptr %5, align 8
  br label %99

43:                                               ; preds = %23
  %44 = load i32, ptr %8, align 4, !tbaa !5
  %45 = icmp eq i32 %44, 0
  br i1 %45, label %46, label %63

46:                                               ; preds = %43
  %47 = load i32, ptr %7, align 4, !tbaa !5
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %48) #1
  %50 = load i32, ptr %9, align 4, !tbaa !5
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %51) #1
  %53 = load i64, ptr %52, align 8, !tbaa !9
  %54 = load i32, ptr %6, align 4, !tbaa !5
  %55 = sub nsw i32 %54, 1
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %56) #1
  %58 = load i32, ptr %9, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %57, i64 noundef %59) #1
  %61 = load i64, ptr %60, align 8, !tbaa !9
  %62 = sub nsw i64 %53, %61
  store i64 %62, ptr %5, align 8
  br label %99

63:                                               ; preds = %43
  %64 = load i32, ptr %7, align 4, !tbaa !5
  %65 = sext i32 %64 to i64
  %66 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %65) #1
  %67 = load i32, ptr %9, align 4, !tbaa !5
  %68 = sext i32 %67 to i64
  %69 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %66, i64 noundef %68) #1
  %70 = load i64, ptr %69, align 8, !tbaa !9
  %71 = load i32, ptr %7, align 4, !tbaa !5
  %72 = sext i32 %71 to i64
  %73 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %72) #1
  %74 = load i32, ptr %8, align 4, !tbaa !5
  %75 = sub nsw i32 %74, 1
  %76 = sext i32 %75 to i64
  %77 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %76) #1
  %78 = load i64, ptr %77, align 8, !tbaa !9
  %79 = sub nsw i64 %70, %78
  %80 = load i32, ptr %6, align 4, !tbaa !5
  %81 = sub nsw i32 %80, 1
  %82 = sext i32 %81 to i64
  %83 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %82) #1
  %84 = load i32, ptr %9, align 4, !tbaa !5
  %85 = sext i32 %84 to i64
  %86 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %83, i64 noundef %85) #1
  %87 = load i64, ptr %86, align 8, !tbaa !9
  %88 = sub nsw i64 %79, %87
  %89 = load i32, ptr %6, align 4, !tbaa !5
  %90 = sub nsw i32 %89, 1
  %91 = sext i32 %90 to i64
  %92 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %91) #1
  %93 = load i32, ptr %8, align 4, !tbaa !5
  %94 = sub nsw i32 %93, 1
  %95 = sext i32 %94 to i64
  %96 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %92, i64 noundef %95) #1
  %97 = load i64, ptr %96, align 8, !tbaa !9
  %98 = add nsw i64 %88, %97
  store i64 %98, ptr %5, align 8
  br label %99

99:                                               ; preds = %63, %46, %26, %15
  %100 = load i64, ptr %5, align 8
  ret i64 %100
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@m = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z1riiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = icmp eq i32 %2, 0
  %6 = or i32 %2, %0
  %or.cond = icmp eq i32 %6, 0
  br i1 %or.cond, label %7, label %13

7:                                                ; preds = %4
  %8 = sext i32 %1 to i64
  %9 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %8) #1
  %10 = sext i32 %3 to i64
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %10) #1
  %12 = load i64, ptr %11, align 8, !tbaa !5
  br label %52

13:                                               ; preds = %4
  %14 = icmp eq i32 %0, 0
  %15 = sext i32 %1 to i64
  %16 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %15) #1
  %17 = sext i32 %3 to i64
  %18 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %17) #1
  %19 = load i64, ptr %18, align 8, !tbaa !5
  br i1 %14, label %20, label %27

20:                                               ; preds = %13
  %21 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %15) #1
  %22 = add nsw i32 %2, -1
  %23 = sext i32 %22 to i64
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #1
  %25 = load i64, ptr %24, align 8, !tbaa !5
  %26 = sub nsw i64 %19, %25
  br label %52

27:                                               ; preds = %13
  br i1 %5, label %28, label %35

28:                                               ; preds = %27
  %29 = add nsw i32 %0, -1
  %30 = sext i32 %29 to i64
  %31 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %30) #1
  %32 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %17) #1
  %33 = load i64, ptr %32, align 8, !tbaa !5
  %34 = sub nsw i64 %19, %33
  br label %52

35:                                               ; preds = %27
  %36 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %15) #1
  %37 = add nsw i32 %2, -1
  %38 = sext i32 %37 to i64
  %39 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %38) #1
  %40 = load i64, ptr %39, align 8, !tbaa !5
  %41 = add nsw i32 %0, -1
  %42 = sext i32 %41 to i64
  %43 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %42) #1
  %44 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %17) #1
  %45 = load i64, ptr %44, align 8, !tbaa !5
  %46 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @m, i64 noundef %42) #1
  %47 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %38) #1
  %48 = load i64, ptr %47, align 8, !tbaa !5
  %49 = add i64 %40, %45
  %50 = sub i64 %19, %49
  %51 = add nsw i64 %50, %48
  br label %52

52:                                               ; preds = %35, %28, %20, %7
  %.0 = phi i64 [ %12, %7 ], [ %26, %20 ], [ %34, %28 ], [ %51, %35 ]
  ret i64 %.0
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass