; LLVM IR from ermig1979/Simd :: src/Simd/SimdBaseDescrInt.ll (ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [14 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [78 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m = external hidden unnamed_addr constant [74 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m(ptr noundef %0, ptr noundef %1, i64 noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i64 %2, ptr %6, align 8, !tbaa !9
  %11 = load i64, ptr %6, align 8, !tbaa !9
  %12 = urem i64 %11, 8
  %13 = icmp eq i64 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %3
  br label %17

15:                                               ; preds = %3
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 444, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m) #4
  unreachable

16:                                               ; No predecessors!
  br label %17

17:                                               ; preds = %16, %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  store i32 0, ptr %7, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  store i64 0, ptr %8, align 8, !tbaa !9
  br label %18

18:                                               ; preds = %106, %17
  %19 = load i64, ptr %8, align 8, !tbaa !9
  %20 = load i64, ptr %6, align 8, !tbaa !9
  %21 = icmp ult i64 %19, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  br label %109

23:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds i8, ptr %24, i64 0
  %26 = load i32, ptr %25, align 4, !tbaa !11
  store i32 %26, ptr %9, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds i8, ptr %27, i64 0
  %29 = load i32, ptr %28, align 4, !tbaa !11
  store i32 %29, ptr %10, align 4, !tbaa !11
  %30 = load i32, ptr %9, align 4, !tbaa !11
  %31 = lshr i32 %30, 0
  %32 = and i32 %31, 15
  %33 = load i32, ptr %10, align 4, !tbaa !11
  %34 = lshr i32 %33, 0
  %35 = and i32 %34, 15
  %36 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %32, i32 noundef %35)
  %37 = load i32, ptr %7, align 4, !tbaa !11
  %38 = add nsw i32 %37, %36
  store i32 %38, ptr %7, align 4, !tbaa !11
  %39 = load i32, ptr %9, align 4, !tbaa !11
  %40 = lshr i32 %39, 4
  %41 = and i32 %40, 15
  %42 = load i32, ptr %10, align 4, !tbaa !11
  %43 = lshr i32 %42, 4
  %44 = and i32 %43, 15
  %45 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %41, i32 noundef %44)
  %46 = load i32, ptr %7, align 4, !tbaa !11
  %47 = add nsw i32 %46, %45
  store i32 %47, ptr %7, align 4, !tbaa !11
  %48 = load i32, ptr %9, align 4, !tbaa !11
  %49 = lshr i32 %48, 8
  %50 = and i32 %49, 15
  %51 = load i32, ptr %10, align 4, !tbaa !11
  %52 = lshr i32 %51, 8
  %53 = and i32 %52, 15
  %54 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %50, i32 noundef %53)
  %55 = load i32, ptr %7, align 4, !tbaa !11
  %56 = add nsw i32 %55, %54
  store i32 %56, ptr %7, align 4, !tbaa !11
  %57 = load i32, ptr %9, align 4, !tbaa !11
  %58 = lshr i32 %57, 12
  %59 = and i32 %58, 15
  %60 = load i32, ptr %10, align 4, !tbaa !11
  %61 = lshr i32 %60, 12
  %62 = and i32 %61, 15
  %63 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %59, i32 noundef %62)
  %64 = load i32, ptr %7, align 4, !tbaa !11
  %65 = add nsw i32 %64, %63
  store i32 %65, ptr %7, align 4, !tbaa !11
  %66 = load i32, ptr %9, align 4, !tbaa !11
  %67 = lshr i32 %66, 16
  %68 = and i32 %67, 15
  %69 = load i32, ptr %10, align 4, !tbaa !11
  %70 = lshr i32 %69, 16
  %71 = and i32 %70, 15
  %72 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %68, i32 noundef %71)
  %73 = load i32, ptr %7, align 4, !tbaa !11
  %74 = add nsw i32 %73, %72
  store i32 %74, ptr %7, align 4, !tbaa !11
  %75 = load i32, ptr %9, align 4, !tbaa !11
  %76 = lshr i32 %75, 20
  %77 = and i32 %76, 15
  %78 = load i32, ptr %10, align 4, !tbaa !11
  %79 = lshr i32 %78, 20
  %80 = and i32 %79, 15
  %81 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %77, i32 noundef %80)
  %82 = load i32, ptr %7, align 4, !tbaa !11
  %83 = add nsw i32 %82, %81
  store i32 %83, ptr %7, align 4, !tbaa !11
  %84 = load i32, ptr %9, align 4, !tbaa !11
  %85 = lshr i32 %84, 24
  %86 = and i32 %85, 15
  %87 = load i32, ptr %10, align 4, !tbaa !11
  %88 = lshr i32 %87, 24
  %89 = and i32 %88, 15
  %90 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %86, i32 noundef %89)
  %91 = load i32, ptr %7, align 4, !tbaa !11
  %92 = add nsw i32 %91, %90
  store i32 %92, ptr %7, align 4, !tbaa !11
  %93 = load i32, ptr %9, align 4, !tbaa !11
  %94 = lshr i32 %93, 28
  %95 = and i32 %94, 15
  %96 = load i32, ptr %10, align 4, !tbaa !11
  %97 = lshr i32 %96, 28
  %98 = and i32 %97, 15
  %99 = call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %95, i32 noundef %98)
  %100 = load i32, ptr %7, align 4, !tbaa !11
  %101 = add nsw i32 %100, %99
  store i32 %101, ptr %7, align 4, !tbaa !11
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds i8, ptr %102, i64 4
  store ptr %103, ptr %4, align 8, !tbaa !5
  %104 = load ptr, ptr %5, align 8, !tbaa !5
  %105 = getelementptr inbounds i8, ptr %104, i64 4
  store ptr %105, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %106

106:                                              ; preds = %23
  %107 = load i64, ptr %8, align 8, !tbaa !9
  %108 = add i64 %107, 8
  store i64 %108, ptr %8, align 8, !tbaa !9
  br label %18, !llvm.loop !13

109:                                              ; preds = %22
  %110 = load i32, ptr %7, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  ret i32 %110
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef, i32 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [14 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [78 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m = external hidden unnamed_addr constant [74 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, i64 noundef %2) local_unnamed_addr #0 {
  %4 = and i64 %2, 7
  %5 = icmp eq i64 %4, 0
  br i1 %5, label %.preheader, label %6

.preheader:                                       ; preds = %3
  %.not = icmp eq i64 %2, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

6:                                                ; preds = %3
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 444, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base11CorrelationILi4EEEiPKhS3_m) #3
  unreachable

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  %.034.lcssa = phi i32 [ 0, %.preheader ], [ %52, %.lr.ph ]
  ret i32 %.034.lcssa

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %.038 = phi ptr [ %53, %.lr.ph ], [ %0, %.preheader ]
  %.03237 = phi ptr [ %54, %.lr.ph ], [ %1, %.preheader ]
  %.03336 = phi i64 [ %55, %.lr.ph ], [ 0, %.preheader ]
  %.03435 = phi i32 [ %52, %.lr.ph ], [ 0, %.preheader ]
  %7 = load i32, ptr %.038, align 4, !tbaa !5
  %8 = load i32, ptr %.03237, align 4, !tbaa !5
  %9 = and i32 %7, 15
  %10 = and i32 %8, 15
  %11 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %9, i32 noundef %10)
  %12 = add nsw i32 %11, %.03435
  %13 = lshr i32 %7, 4
  %14 = and i32 %13, 15
  %15 = lshr i32 %8, 4
  %16 = and i32 %15, 15
  %17 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %14, i32 noundef %16)
  %18 = add nsw i32 %12, %17
  %19 = lshr i32 %7, 8
  %20 = and i32 %19, 15
  %21 = lshr i32 %8, 8
  %22 = and i32 %21, 15
  %23 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %20, i32 noundef %22)
  %24 = add nsw i32 %18, %23
  %25 = lshr i32 %7, 12
  %26 = and i32 %25, 15
  %27 = lshr i32 %8, 12
  %28 = and i32 %27, 15
  %29 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %26, i32 noundef %28)
  %30 = add nsw i32 %24, %29
  %31 = lshr i32 %7, 16
  %32 = and i32 %31, 15
  %33 = lshr i32 %8, 16
  %34 = and i32 %33, 15
  %35 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %32, i32 noundef %34)
  %36 = add nsw i32 %30, %35
  %37 = lshr i32 %7, 20
  %38 = and i32 %37, 15
  %39 = lshr i32 %8, 20
  %40 = and i32 %39, 15
  %41 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %38, i32 noundef %40)
  %42 = add nsw i32 %36, %41
  %43 = lshr i32 %7, 24
  %44 = and i32 %43, 15
  %45 = lshr i32 %8, 24
  %46 = and i32 %45, 15
  %47 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %44, i32 noundef %46)
  %48 = add nsw i32 %42, %47
  %49 = lshr i32 %7, 28
  %50 = lshr i32 %8, 28
  %51 = tail call noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef %49, i32 noundef %50)
  %52 = add nsw i32 %48, %51
  %53 = getelementptr inbounds i8, ptr %.038, i64 4
  %54 = getelementptr inbounds i8, ptr %.03237, i64 4
  %55 = add i64 %.03336, 8
  %56 = icmp ult i64 %55, %2
  br i1 %56, label %.lr.ph, label %._crit_edge, !llvm.loop !9
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Simd4Base3MulEii(i32 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass