; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_store_16x64_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %14 = load i32, ptr %9, align 4, !tbaa !9
  %15 = udiv i32 %14, 16
  store i32 %15, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 0, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  %16 = load i32, ptr %9, align 4, !tbaa !9
  %17 = urem i32 %16, 16
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %22

19:                                               ; preds = %5
  %20 = load i32, ptr %11, align 4, !tbaa !9
  %21 = add i32 %20, 1
  store i32 %21, ptr %11, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %19, %5
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = load i32, ptr %11, align 4, !tbaa !9
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %23, i32 noundef %24)
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = load i32, ptr %8, align 4, !tbaa !9
  %27 = icmp ult i32 %26, 16
  br i1 %27, label %28, label %31

28:                                               ; preds = %22
  %29 = load i32, ptr %8, align 4, !tbaa !9
  %30 = mul nsw i32 %29, 4
  br label %32

31:                                               ; preds = %22
  br label %32

32:                                               ; preds = %31, %28
  %33 = phi i32 [ %30, %28 ], [ -1, %31 ]
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %25, i32 noundef 0, i32 noundef %33, i32 noundef 41)
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %34

34:                                               ; preds = %41, %32
  %35 = load i32, ptr %12, align 4, !tbaa !9
  %36 = icmp ult i32 %35, 4
  br i1 %36, label %37, label %44

37:                                               ; preds = %34
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %38, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef %39)
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %40, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %41

41:                                               ; preds = %37
  %42 = load i32, ptr %12, align 4, !tbaa !9
  %43 = add i32 %42, 1
  store i32 %43, ptr %12, align 4, !tbaa !9
  br label %34, !llvm.loop !11

44:                                               ; preds = %34
  %45 = load i32, ptr %9, align 4, !tbaa !9
  %46 = icmp ugt i32 %45, 16
  br i1 %46, label %47, label %59

47:                                               ; preds = %44
  store i32 4, ptr %12, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %55, %47
  %49 = load i32, ptr %12, align 4, !tbaa !9
  %50 = icmp ult i32 %49, 8
  br i1 %50, label %51, label %58

51:                                               ; preds = %48
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %52, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef %53)
  %54 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %54, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %55

55:                                               ; preds = %51
  %56 = load i32, ptr %12, align 4, !tbaa !9
  %57 = add i32 %56, 1
  store i32 %57, ptr %12, align 4, !tbaa !9
  br label %48, !llvm.loop !13

58:                                               ; preds = %48
  br label %59

59:                                               ; preds = %58, %44
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %60

60:                                               ; preds = %80, %59
  %61 = load i32, ptr %13, align 4, !tbaa !9
  %62 = load i32, ptr %9, align 4, !tbaa !9
  %63 = icmp ult i32 %62, 32
  br i1 %63, label %64, label %66

64:                                               ; preds = %60
  %65 = load i32, ptr %9, align 4, !tbaa !9
  br label %67

66:                                               ; preds = %60
  br label %67

67:                                               ; preds = %66, %64
  %68 = phi i32 [ %65, %64 ], [ 32, %66 ]
  %69 = icmp ult i32 %61, %68
  br i1 %69, label %70, label %83

70:                                               ; preds = %67
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = load i32, ptr %7, align 4, !tbaa !9
  %73 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %71, i32 noundef -448733050, i32 noundef %72, i32 noundef 127, i32 noundef 0, i32 noundef %73, i32 noundef 0)
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = load i32, ptr %7, align 4, !tbaa !9
  %76 = load i32, ptr %7, align 4, !tbaa !9
  %77 = load i32, ptr %10, align 4, !tbaa !9
  %78 = mul i32 %77, 4
  %79 = zext i32 %78 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %74, i32 noundef 4096, i32 noundef %75, i32 noundef 43, i32 noundef %76, i64 noundef %79)
  br label %80

80:                                               ; preds = %70
  %81 = load i32, ptr %13, align 4, !tbaa !9
  %82 = add i32 %81, 1
  store i32 %82, ptr %13, align 4, !tbaa !9
  br label %60, !llvm.loop !14

83:                                               ; preds = %67
  %84 = load i32, ptr %9, align 4, !tbaa !9
  %85 = icmp ugt i32 %84, 32
  br i1 %85, label %86, label %132

86:                                               ; preds = %83
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %87

87:                                               ; preds = %94, %86
  %88 = load i32, ptr %12, align 4, !tbaa !9
  %89 = icmp ult i32 %88, 4
  br i1 %89, label %90, label %97

90:                                               ; preds = %87
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %91, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef %92)
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %93, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0)
  br label %94

94:                                               ; preds = %90
  %95 = load i32, ptr %12, align 4, !tbaa !9
  %96 = add i32 %95, 1
  store i32 %96, ptr %12, align 4, !tbaa !9
  br label %87, !llvm.loop !15

97:                                               ; preds = %87
  %98 = load i32, ptr %9, align 4, !tbaa !9
  %99 = icmp ugt i32 %98, 48
  br i1 %99, label %100, label %112

100:                                              ; preds = %97
  store i32 4, ptr %12, align 4, !tbaa !9
  br label %101

101:                                              ; preds = %108, %100
  %102 = load i32, ptr %12, align 4, !tbaa !9
  %103 = icmp ult i32 %102, 8
  br i1 %103, label %104, label %111

104:                                              ; preds = %101
  %105 = load ptr, ptr %6, align 8, !tbaa !5
  %106 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %105, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef %106)
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %107, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0)
  br label %108

108:                                              ; preds = %104
  %109 = load i32, ptr %12, align 4, !tbaa !9
  %110 = add i32 %109, 1
  store i32 %110, ptr %12, align 4, !tbaa !9
  br label %101, !llvm.loop !16

111:                                              ; preds = %101
  br label %112

112:                                              ; preds = %111, %97
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %113

113:                                              ; preds = %128, %112
  %114 = load i32, ptr %13, align 4, !tbaa !9
  %115 = load i32, ptr %9, align 4, !tbaa !9
  %116 = sub i32 %115, 32
  %117 = icmp ult i32 %114, %116
  br i1 %117, label %118, label %131

118:                                              ; preds = %113
  %119 = load ptr, ptr %6, align 8, !tbaa !5
  %120 = load i32, ptr %7, align 4, !tbaa !9
  %121 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %119, i32 noundef -448733050, i32 noundef %120, i32 noundef 127, i32 noundef 0, i32 noundef %121, i32 noundef 0)
  %122 = load ptr, ptr %6, align 8, !tbaa !5
  %123 = load i32, ptr %7, align 4, !tbaa !9
  %124 = load i32, ptr %7, align 4, !tbaa !9
  %125 = load i32, ptr %10, align 4, !tbaa !9
  %126 = mul i32 %125, 4
  %127 = zext i32 %126 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %122, i32 noundef 4096, i32 noundef %123, i32 noundef 43, i32 noundef %124, i64 noundef %127)
  br label %128

128:                                              ; preds = %118
  %129 = load i32, ptr %13, align 4, !tbaa !9
  %130 = add i32 %129, 1
  store i32 %130, ptr %13, align 4, !tbaa !9
  br label %113, !llvm.loop !17

131:                                              ; preds = %113
  br label %132

132:                                              ; preds = %131, %83
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_store_16x64_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = lshr i32 %3, 4
  %7 = and i32 %3, 15
  %.not = icmp ne i32 %7, 0
  %8 = zext i1 %.not to i32
  %spec.select = add nuw nsw i32 %6, %8
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef %spec.select)
  %9 = icmp ult i32 %2, 16
  %10 = shl nuw nsw i32 %2, 2
  %11 = select i1 %9, i32 %10, i32 -1
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef %11, i32 noundef 41)
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  %12 = icmp ugt i32 %3, 16
  br i1 %12, label %.loopexit58.thread, label %.loopexit58

.loopexit58.thread:                               ; preds = %5
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  %13 = tail call i32 @llvm.umin.i32(i32 %3, i32 32)
  br label %.lr.ph

.loopexit58:                                      ; preds = %5
  %.not67 = icmp eq i32 %3, 0
  br i1 %.not67, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %.loopexit58.thread, %.loopexit58
  %14 = phi i32 [ %13, %.loopexit58.thread ], [ %3, %.loopexit58 ]
  %15 = shl i32 %4, 2
  %16 = zext i32 %15 to i64
  br label %17

17:                                               ; preds = %.lr.ph, %17
  %.061 = phi i32 [ 0, %.lr.ph ], [ %18, %17 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef %1, i32 noundef 127, i32 noundef 0, i32 noundef %.061, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %16) #3
  %18 = add nuw nsw i32 %.061, 1
  %exitcond.not = icmp eq i32 %18, %14
  br i1 %exitcond.not, label %._crit_edge, label %17, !llvm.loop !5

._crit_edge:                                      ; preds = %17
  %19 = icmp ugt i32 %3, 32
  br i1 %19, label %.preheader56.preheader, label %.loopexit

.preheader56.preheader:                           ; preds = %._crit_edge
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  %20 = icmp ugt i32 %3, 48
  br i1 %20, label %.preheader.preheader, label %.lr.ph66

.preheader.preheader:                             ; preds = %.preheader56.preheader
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  br label %.lr.ph66

.lr.ph66:                                         ; preds = %.preheader56.preheader, %.preheader.preheader
  %21 = shl i32 %4, 2
  %22 = zext i32 %21 to i64
  %23 = add i32 %3, -33
  br label %24

24:                                               ; preds = %.lr.ph66, %24
  %.164 = phi i32 [ 0, %.lr.ph66 ], [ %25, %24 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -448733050, i32 noundef %1, i32 noundef 127, i32 noundef 0, i32 noundef %.164, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %22) #3
  %25 = add nuw i32 %.164, 1
  %exitcond71.not = icmp eq i32 %.164, %23
  br i1 %exitcond71.not, label %.loopexit, label %24, !llvm.loop !7

.loopexit:                                        ; preds = %24, %.loopexit58, %._crit_edge
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass