; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConversion)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [2 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [85 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType = external hidden unnamed_addr constant [175 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i32 noundef %5, ptr noundef %6, ptr noundef %7, ptr noundef %8, i32 noundef %9) #0 {
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i32, align 4
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i64, align 8
  %23 = alloca i32, align 4
  %24 = alloca i64, align 8
  %25 = alloca float, align 4
  %26 = alloca float, align 4
  %27 = alloca i64, align 8
  %28 = alloca i64, align 8
  %29 = alloca i64, align 8
  %30 = alloca i64, align 8
  %31 = alloca i64, align 8
  store ptr %0, ptr %11, align 8, !tbaa !5
  store i64 %1, ptr %12, align 8, !tbaa !9
  store i64 %2, ptr %13, align 8, !tbaa !9
  store i64 %3, ptr %14, align 8, !tbaa !9
  store i64 %4, ptr %15, align 8, !tbaa !9
  store i32 %5, ptr %16, align 4, !tbaa !11
  store ptr %6, ptr %17, align 8, !tbaa !5
  store ptr %7, ptr %18, align 8, !tbaa !5
  store ptr %8, ptr %19, align 8, !tbaa !5
  store i32 %9, ptr %20, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #5
  %32 = load i32, ptr %20, align 4, !tbaa !13
  %33 = call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %32)
  %34 = zext i1 %33 to i64
  %35 = select i1 %33, i32 180, i32 255
  store i32 %35, ptr %21, align 4, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #5
  store i64 0, ptr %22, align 8, !tbaa !9
  br label %36

36:                                               ; preds = %160, %10
  %37 = load i64, ptr %22, align 8, !tbaa !9
  %38 = load i64, ptr %12, align 8, !tbaa !9
  %39 = icmp ult i64 %37, %38
  br i1 %39, label %41, label %40

40:                                               ; preds = %36
  store i32 2, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #5
  br label %163

41:                                               ; preds = %36
  %42 = load i32, ptr %16, align 4, !tbaa !11
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %100

44:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 8, ptr %24) #5
  store i64 0, ptr %24, align 8, !tbaa !9
  br label %45

45:                                               ; preds = %96, %44
  %46 = load i64, ptr %24, align 8, !tbaa !9
  %47 = load i64, ptr %13, align 8, !tbaa !9
  %48 = icmp ult i64 %46, %47
  br i1 %48, label %50, label %49

49:                                               ; preds = %45
  store i32 5, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %24) #5
  br label %99

50:                                               ; preds = %45
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #5
  %51 = load ptr, ptr %17, align 8, !tbaa !5
  %52 = load i64, ptr %24, align 8, !tbaa !9
  %53 = getelementptr inbounds float, ptr %51, i64 %52
  %54 = load float, ptr %53, align 4, !tbaa !17
  store float %54, ptr %25, align 4, !tbaa !17
  call void @llvm.lifetime.start.p0(i64 4, ptr %26) #5
  %55 = load ptr, ptr %18, align 8, !tbaa !5
  %56 = load i64, ptr %24, align 8, !tbaa !9
  %57 = getelementptr inbounds float, ptr %55, i64 %56
  %58 = load float, ptr %57, align 4, !tbaa !17
  store float %58, ptr %26, align 4, !tbaa !17
  call void @llvm.lifetime.start.p0(i64 8, ptr %27) #5
  store i64 0, ptr %27, align 8, !tbaa !9
  br label %59

59:                                               ; preds = %92, %50
  %60 = load i64, ptr %27, align 8, !tbaa !9
  %61 = load i64, ptr %14, align 8, !tbaa !9
  %62 = icmp ult i64 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  store i32 8, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %27) #5
  br label %95

64:                                               ; preds = %59
  call void @llvm.lifetime.start.p0(i64 8, ptr %28) #5
  store i64 0, ptr %28, align 8, !tbaa !9
  br label %65

65:                                               ; preds = %82, %64
  %66 = load i64, ptr %28, align 8, !tbaa !9
  %67 = load i64, ptr %15, align 8, !tbaa !9
  %68 = icmp ult i64 %66, %67
  br i1 %68, label %70, label %69

69:                                               ; preds = %65
  store i32 11, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %28) #5
  br label %85

70:                                               ; preds = %65
  %71 = load ptr, ptr %11, align 8, !tbaa !5
  %72 = load i64, ptr %28, align 8, !tbaa !9
  %73 = getelementptr inbounds float, ptr %71, i64 %72
  %74 = load float, ptr %73, align 4, !tbaa !17
  %75 = load float, ptr %25, align 4, !tbaa !17
  %76 = load float, ptr %26, align 4, !tbaa !17
  %77 = load i32, ptr %21, align 4, !tbaa !15
  %78 = call noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef %74, float noundef %75, float noundef %76, i32 noundef 0, i32 noundef %77)
  %79 = load ptr, ptr %19, align 8, !tbaa !5
  %80 = load i64, ptr %28, align 8, !tbaa !9
  %81 = getelementptr inbounds i8, ptr %79, i64 %80
  store i8 %78, ptr %81, align 1, !tbaa !19
  br label %82

82:                                               ; preds = %70
  %83 = load i64, ptr %28, align 8, !tbaa !9
  %84 = add i64 %83, 1
  store i64 %84, ptr %28, align 8, !tbaa !9
  br label %65, !llvm.loop !20

85:                                               ; preds = %69
  %86 = load i64, ptr %15, align 8, !tbaa !9
  %87 = load ptr, ptr %11, align 8, !tbaa !5
  %88 = getelementptr inbounds float, ptr %87, i64 %86
  store ptr %88, ptr %11, align 8, !tbaa !5
  %89 = load i64, ptr %15, align 8, !tbaa !9
  %90 = load ptr, ptr %19, align 8, !tbaa !5
  %91 = getelementptr inbounds i8, ptr %90, i64 %89
  store ptr %91, ptr %19, align 8, !tbaa !5
  br label %92

92:                                               ; preds = %85
  %93 = load i64, ptr %27, align 8, !tbaa !9
  %94 = add i64 %93, 1
  store i64 %94, ptr %27, align 8, !tbaa !9
  br label %59, !llvm.loop !22

95:                                               ; preds = %63
  call void @llvm.lifetime.end.p0(i64 4, ptr %26) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #5
  br label %96

96:                                               ; preds = %95
  %97 = load i64, ptr %24, align 8, !tbaa !9
  %98 = add i64 %97, 1
  store i64 %98, ptr %24, align 8, !tbaa !9
  br label %45, !llvm.loop !23

99:                                               ; preds = %49
  br label %159

100:                                              ; preds = %41
  %101 = load i32, ptr %16, align 4, !tbaa !11
  %102 = icmp eq i32 %101, 1
  br i1 %102, label %103, label %157

103:                                              ; preds = %100
  call void @llvm.lifetime.start.p0(i64 8, ptr %29) #5
  store i64 0, ptr %29, align 8, !tbaa !9
  br label %104

104:                                              ; preds = %153, %103
  %105 = load i64, ptr %29, align 8, !tbaa !9
  %106 = load i64, ptr %14, align 8, !tbaa !9
  %107 = icmp ult i64 %105, %106
  br i1 %107, label %109, label %108

108:                                              ; preds = %104
  store i32 14, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #5
  br label %156

109:                                              ; preds = %104
  call void @llvm.lifetime.start.p0(i64 8, ptr %30) #5
  store i64 0, ptr %30, align 8, !tbaa !9
  br label %110

110:                                              ; preds = %149, %109
  %111 = load i64, ptr %30, align 8, !tbaa !9
  %112 = load i64, ptr %15, align 8, !tbaa !9
  %113 = icmp ult i64 %111, %112
  br i1 %113, label %115, label %114

114:                                              ; preds = %110
  store i32 17, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %30) #5
  br label %152

115:                                              ; preds = %110
  call void @llvm.lifetime.start.p0(i64 8, ptr %31) #5
  store i64 0, ptr %31, align 8, !tbaa !9
  br label %116

116:                                              ; preds = %139, %115
  %117 = load i64, ptr %31, align 8, !tbaa !9
  %118 = load i64, ptr %13, align 8, !tbaa !9
  %119 = icmp ult i64 %117, %118
  br i1 %119, label %121, label %120

120:                                              ; preds = %116
  store i32 20, ptr %23, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %31) #5
  br label %142

121:                                              ; preds = %116
  %122 = load ptr, ptr %11, align 8, !tbaa !5
  %123 = load i64, ptr %31, align 8, !tbaa !9
  %124 = getelementptr inbounds float, ptr %122, i64 %123
  %125 = load float, ptr %124, align 4, !tbaa !17
  %126 = load ptr, ptr %17, align 8, !tbaa !5
  %127 = load i64, ptr %31, align 8, !tbaa !9
  %128 = getelementptr inbounds float, ptr %126, i64 %127
  %129 = load float, ptr %128, align 4, !tbaa !17
  %130 = load ptr, ptr %18, align 8, !tbaa !5
  %131 = load i64, ptr %31, align 8, !tbaa !9
  %132 = getelementptr inbounds float, ptr %130, i64 %131
  %133 = load float, ptr %132, align 4, !tbaa !17
  %134 = load i32, ptr %21, align 4, !tbaa !15
  %135 = call noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef %125, float noundef %129, float noundef %133, i32 noundef 0, i32 noundef %134)
  %136 = load ptr, ptr %19, align 8, !tbaa !5
  %137 = load i64, ptr %31, align 8, !tbaa !9
  %138 = getelementptr inbounds i8, ptr %136, i64 %137
  store i8 %135, ptr %138, align 1, !tbaa !19
  br label %139

139:                                              ; preds = %121
  %140 = load i64, ptr %31, align 8, !tbaa !9
  %141 = add i64 %140, 1
  store i64 %141, ptr %31, align 8, !tbaa !9
  br label %116, !llvm.loop !24

142:                                              ; preds = %120
  %143 = load i64, ptr %13, align 8, !tbaa !9
  %144 = load ptr, ptr %11, align 8, !tbaa !5
  %145 = getelementptr inbounds float, ptr %144, i64 %143
  store ptr %145, ptr %11, align 8, !tbaa !5
  %146 = load i64, ptr %13, align 8, !tbaa !9
  %147 = load ptr, ptr %19, align 8, !tbaa !5
  %148 = getelementptr inbounds i8, ptr %147, i64 %146
  store ptr %148, ptr %19, align 8, !tbaa !5
  br label %149

149:                                              ; preds = %142
  %150 = load i64, ptr %30, align 8, !tbaa !9
  %151 = add i64 %150, 1
  store i64 %151, ptr %30, align 8, !tbaa !9
  br label %110, !llvm.loop !25

152:                                              ; preds = %114
  br label %153

153:                                              ; preds = %152
  %154 = load i64, ptr %29, align 8, !tbaa !9
  %155 = add i64 %154, 1
  store i64 %155, ptr %29, align 8, !tbaa !9
  br label %104, !llvm.loop !26

156:                                              ; preds = %108
  br label %158

157:                                              ; preds = %100
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 68, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType) #6
  unreachable

158:                                              ; preds = %156
  br label %159

159:                                              ; preds = %158, %99
  br label %160

160:                                              ; preds = %159
  %161 = load i64, ptr %22, align 8, !tbaa !9
  %162 = add i64 %161, 1
  store i64 %162, ptr %22, align 8, !tbaa !9
  br label %36, !llvm.loop !27

163:                                              ; preds = %40
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef) #2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef, float noundef, float noundef, i32 noundef, i32 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"int", !7, i64 0}
!17 = !{!18, !18, i64 0}
!18 = !{!"float", !7, i64 0}
!19 = !{!7, !7, i64 0}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = distinct !{!22, !21}
!23 = distinct !{!23, !21}
!24 = distinct !{!24, !21}
!25 = distinct !{!25, !21}
!26 = distinct !{!26, !21}
!27 = distinct !{!27, !21}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [2 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [85 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType = external hidden unnamed_addr constant [175 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType(ptr nocapture noundef readonly %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i32 noundef %5, ptr nocapture noundef readonly %6, ptr nocapture noundef readonly %7, ptr nocapture noundef writeonly %8, i32 noundef %9) local_unnamed_addr #0 {
  %11 = tail call noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef %9)
  %12 = select i1 %11, i32 180, i32 255
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph125

.lr.ph125:                                        ; preds = %10
  %.not152 = icmp eq i64 %3, 0
  %.not153 = icmp eq i64 %4, 0
  %.not154 = icmp eq i64 %2, 0
  %switch = icmp ult i32 %5, 2
  br i1 %switch, label %.lr.ph125.split, label %43

.lr.ph125.split:                                  ; preds = %.lr.ph125
  %cond = icmp eq i32 %5, 0
  br i1 %cond, label %.lr.ph125.split.split.us, label %.lr.ph125.split.split

.lr.ph125.split.split.us:                         ; preds = %.lr.ph125.split
  %brmerge = or i1 %.not154, %.not152
  %brmerge189 = or i1 %brmerge, %.not153
  br i1 %brmerge189, label %._crit_edge, label %.preheader69.us.us.us.us

.preheader69.us.us.us.us:                         ; preds = %.lr.ph125.split.split.us, %..loopexit_crit_edge.split.us.split.us.us.us.us.us
  %.055124.us.us.us.us = phi ptr [ %23, %..loopexit_crit_edge.split.us.split.us.us.us.us.us ], [ %0, %.lr.ph125.split.split.us ]
  %.056123.us.us.us.us = phi ptr [ %24, %..loopexit_crit_edge.split.us.split.us.us.us.us.us ], [ %8, %.lr.ph125.split.split.us ]
  %.063122.us.us.us.us = phi i64 [ %27, %..loopexit_crit_edge.split.us.split.us.us.us.us.us ], [ 0, %.lr.ph125.split.split.us ]
  br label %.preheader.lr.ph.us.us.us.us.us.us

.preheader.lr.ph.us.us.us.us.us.us:               ; preds = %._crit_edge99.split.us.us.us.us.us.us.us, %.preheader69.us.us.us.us
  %.1105.us.us.us.us.us.us = phi ptr [ %.055124.us.us.us.us, %.preheader69.us.us.us.us ], [ %23, %._crit_edge99.split.us.us.us.us.us.us.us ]
  %.157104.us.us.us.us.us.us = phi ptr [ %.056123.us.us.us.us, %.preheader69.us.us.us.us ], [ %24, %._crit_edge99.split.us.us.us.us.us.us.us ]
  %.062103.us.us.us.us.us.us = phi i64 [ 0, %.preheader69.us.us.us.us ], [ %26, %._crit_edge99.split.us.us.us.us.us.us.us ]
  %13 = getelementptr inbounds float, ptr %6, i64 %.062103.us.us.us.us.us.us
  %14 = load float, ptr %13, align 4, !tbaa !5
  %15 = getelementptr inbounds float, ptr %7, i64 %.062103.us.us.us.us.us.us
  %16 = load float, ptr %15, align 4, !tbaa !5
  br label %.preheader.us.us.us.us.us.us.us

.preheader.us.us.us.us.us.us.us:                  ; preds = %._crit_edge.us.us.us118.us.us.us.us, %.preheader.lr.ph.us.us.us.us.us.us
  %.05498.us.us.us.us.us.us.us = phi i64 [ 0, %.preheader.lr.ph.us.us.us.us.us.us ], [ %25, %._crit_edge.us.us.us118.us.us.us.us ]
  %.297.us.us.us.us.us.us.us = phi ptr [ %.1105.us.us.us.us.us.us, %.preheader.lr.ph.us.us.us.us.us.us ], [ %23, %._crit_edge.us.us.us118.us.us.us.us ]
  %.25896.us.us.us.us.us.us.us = phi ptr [ %.157104.us.us.us.us.us.us, %.preheader.lr.ph.us.us.us.us.us.us ], [ %24, %._crit_edge.us.us.us118.us.us.us.us ]
  br label %17

17:                                               ; preds = %17, %.preheader.us.us.us.us.us.us.us
  %.05395.us.us.us.us.us.us.us = phi i64 [ 0, %.preheader.us.us.us.us.us.us.us ], [ %22, %17 ]
  %18 = getelementptr inbounds float, ptr %.297.us.us.us.us.us.us.us, i64 %.05395.us.us.us.us.us.us.us
  %19 = load float, ptr %18, align 4, !tbaa !5
  %20 = tail call noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef %19, float noundef %14, float noundef %16, i32 noundef 0, i32 noundef %12)
  %21 = getelementptr inbounds i8, ptr %.25896.us.us.us.us.us.us.us, i64 %.05395.us.us.us.us.us.us.us
  store i8 %20, ptr %21, align 1, !tbaa !9
  %22 = add nuw i64 %.05395.us.us.us.us.us.us.us, 1
  %exitcond178.not = icmp eq i64 %22, %4
  br i1 %exitcond178.not, label %._crit_edge.us.us.us118.us.us.us.us, label %17, !llvm.loop !10

._crit_edge.us.us.us118.us.us.us.us:              ; preds = %17
  %23 = getelementptr inbounds float, ptr %.297.us.us.us.us.us.us.us, i64 %4
  %24 = getelementptr inbounds i8, ptr %.25896.us.us.us.us.us.us.us, i64 %4
  %25 = add nuw i64 %.05498.us.us.us.us.us.us.us, 1
  %exitcond179.not = icmp eq i64 %25, %3
  br i1 %exitcond179.not, label %._crit_edge99.split.us.us.us.us.us.us.us, label %.preheader.us.us.us.us.us.us.us, !llvm.loop !12

._crit_edge99.split.us.us.us.us.us.us.us:         ; preds = %._crit_edge.us.us.us118.us.us.us.us
  %26 = add nuw i64 %.062103.us.us.us.us.us.us, 1
  %exitcond180.not = icmp eq i64 %26, %2
  br i1 %exitcond180.not, label %..loopexit_crit_edge.split.us.split.us.us.us.us.us, label %.preheader.lr.ph.us.us.us.us.us.us, !llvm.loop !13

..loopexit_crit_edge.split.us.split.us.us.us.us.us: ; preds = %._crit_edge99.split.us.us.us.us.us.us.us
  %27 = add nuw i64 %.063122.us.us.us.us, 1
  %exitcond181.not = icmp eq i64 %27, %1
  br i1 %exitcond181.not, label %._crit_edge, label %.preheader69.us.us.us.us, !llvm.loop !14

.lr.ph125.split.split:                            ; preds = %.lr.ph125.split
  %brmerge190 = or i1 %.not152, %.not153
  %brmerge191 = or i1 %brmerge190, %.not154
  br i1 %brmerge191, label %._crit_edge, label %.preheader70.us.us.us

.preheader70.us.us.us:                            ; preds = %.lr.ph125.split.split, %..loopexit71_crit_edge.split.us.split.us.us.us.us
  %.055124.us137.us.us = phi ptr [ %38, %..loopexit71_crit_edge.split.us.split.us.us.us.us ], [ %0, %.lr.ph125.split.split ]
  %.056123.us138.us.us = phi ptr [ %39, %..loopexit71_crit_edge.split.us.split.us.us.us.us ], [ %8, %.lr.ph125.split.split ]
  %.063122.us139.us.us = phi i64 [ %42, %..loopexit71_crit_edge.split.us.split.us.us.us.us ], [ 0, %.lr.ph125.split.split ]
  br label %.preheader68.us.us.us.us.us

.preheader68.us.us.us.us.us:                      ; preds = %._crit_edge76.split.us.us.us.us.us.us, %.preheader70.us.us.us
  %.05281.us.us.us.us.us = phi i64 [ 0, %.preheader70.us.us.us ], [ %41, %._crit_edge76.split.us.us.us.us.us.us ]
  %.380.us.us.us.us.us = phi ptr [ %.055124.us137.us.us, %.preheader70.us.us.us ], [ %38, %._crit_edge76.split.us.us.us.us.us.us ]
  %.35979.us.us.us.us.us = phi ptr [ %.056123.us138.us.us, %.preheader70.us.us.us ], [ %39, %._crit_edge76.split.us.us.us.us.us.us ]
  br label %.preheader67.us.us.us.us.us.us

.preheader67.us.us.us.us.us.us:                   ; preds = %._crit_edge.us.us.us.us.us.us, %.preheader68.us.us.us.us.us
  %.05175.us.us.us.us.us.us = phi i64 [ 0, %.preheader68.us.us.us.us.us ], [ %40, %._crit_edge.us.us.us.us.us.us ]
  %.474.us.us.us.us.us.us = phi ptr [ %.380.us.us.us.us.us, %.preheader68.us.us.us.us.us ], [ %38, %._crit_edge.us.us.us.us.us.us ]
  %.46073.us.us.us.us.us.us = phi ptr [ %.35979.us.us.us.us.us, %.preheader68.us.us.us.us.us ], [ %39, %._crit_edge.us.us.us.us.us.us ]
  br label %28

28:                                               ; preds = %28, %.preheader67.us.us.us.us.us.us
  %.072.us.us.us.us.us.us = phi i64 [ 0, %.preheader67.us.us.us.us.us.us ], [ %37, %28 ]
  %29 = getelementptr inbounds float, ptr %.474.us.us.us.us.us.us, i64 %.072.us.us.us.us.us.us
  %30 = load float, ptr %29, align 4, !tbaa !5
  %31 = getelementptr inbounds float, ptr %6, i64 %.072.us.us.us.us.us.us
  %32 = load float, ptr %31, align 4, !tbaa !5
  %33 = getelementptr inbounds float, ptr %7, i64 %.072.us.us.us.us.us.us
  %34 = load float, ptr %33, align 4, !tbaa !5
  %35 = tail call noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef %30, float noundef %32, float noundef %34, i32 noundef 0, i32 noundef %12)
  %36 = getelementptr inbounds i8, ptr %.46073.us.us.us.us.us.us, i64 %.072.us.us.us.us.us.us
  store i8 %35, ptr %36, align 1, !tbaa !9
  %37 = add nuw i64 %.072.us.us.us.us.us.us, 1
  %exitcond.not = icmp eq i64 %37, %2
  br i1 %exitcond.not, label %._crit_edge.us.us.us.us.us.us, label %28, !llvm.loop !15

._crit_edge.us.us.us.us.us.us:                    ; preds = %28
  %38 = getelementptr inbounds float, ptr %.474.us.us.us.us.us.us, i64 %2
  %39 = getelementptr inbounds i8, ptr %.46073.us.us.us.us.us.us, i64 %2
  %40 = add nuw i64 %.05175.us.us.us.us.us.us, 1
  %exitcond172.not = icmp eq i64 %40, %4
  br i1 %exitcond172.not, label %._crit_edge76.split.us.us.us.us.us.us, label %.preheader67.us.us.us.us.us.us, !llvm.loop !16

._crit_edge76.split.us.us.us.us.us.us:            ; preds = %._crit_edge.us.us.us.us.us.us
  %41 = add nuw i64 %.05281.us.us.us.us.us, 1
  %exitcond173.not = icmp eq i64 %41, %3
  br i1 %exitcond173.not, label %..loopexit71_crit_edge.split.us.split.us.us.us.us, label %.preheader68.us.us.us.us.us, !llvm.loop !17

..loopexit71_crit_edge.split.us.split.us.us.us.us: ; preds = %._crit_edge76.split.us.us.us.us.us.us
  %42 = add nuw i64 %.063122.us139.us.us, 1
  %exitcond174.not = icmp eq i64 %42, %1
  br i1 %exitcond174.not, label %._crit_edge, label %.preheader70.us.us.us, !llvm.loop !14

._crit_edge:                                      ; preds = %..loopexit71_crit_edge.split.us.split.us.us.us.us, %..loopexit_crit_edge.split.us.split.us.us.us.us.us, %.lr.ph125.split.split, %.lr.ph125.split.split.us, %10
  ret void

43:                                               ; preds = %.lr.ph125
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 68, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base19SynetConvert32fTo8uEPKfmmmm20SimdTensorFormatTypeS2_S2_Ph26SimdSynetCompatibilityType) #4
  unreachable
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd4Base8NarrowedE26SimdSynetCompatibilityType(i32 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Simd4Base19SynetConvert32fTo8uEfffii(float noundef, float noundef, float noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}
!13 = distinct !{!13, !11}
!14 = distinct !{!14, !11}
!15 = distinct !{!15, !11}
!16 = distinct !{!16, !11}
!17 = distinct !{!17, !11}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass