; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution32fNhwcDirect)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::SynetConvolution32f" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", float, float, ptr, ptr, ptr, %"struct.Simd::Runtime", %"struct.Simd::Runtime.3", %"struct.Simd::Array", ptr, ptr, ptr, %"class.std::__cxx11::basic_string" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Runtime" = type { ptr, %"class.std::vector", %"class.std::__cxx11::basic_string" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Runtime.3" = type { ptr, %"class.std::vector.4", %"class.std::__cxx11::basic_string" }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Simd::Base::SynetConvolution32fNhwcDirect" = type { %"class.Simd::SynetConvolution32f", i64, i64, %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Runtime.9", %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" }
%"struct.Simd::Runtime.9" = type { ptr, %"class.std::vector.10", %"class.std::__cxx11::basic_string" }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" = type { i8, ptr, %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", %"struct.Simd::Array" }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam" = type { i64, i64, i64, i64, i64, [2 x ptr], i64 }

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL3Ev() #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL1Ev() #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL2Ev() #0

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i64 @_ZN4Simd13RestrictRangeImEET_S1_S1_S1_(i64 noundef, i64 noundef, i64 noundef) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd10AlignLoAnyEmm(i64 noundef, i64 noundef) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef, i64 noundef) #0

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect14OldSetAlgParamEm(ptr noundef nonnull align 8 dereferenceable(664) %0, i64 noundef %1) #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !9
  %9 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %10 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %9, i32 0, i32 1
  store ptr %10, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  %11 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %9, i32 0, i32 7
  %12 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old", ptr %11, i32 0, i32 2
  store ptr %12, ptr %6, align 8, !tbaa !5
  %13 = load i64, ptr %4, align 8, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %14, i32 0, i32 0
  store i64 %13, ptr %15, align 8, !tbaa !11
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %16, i32 0, i32 0
  %18 = load i64, ptr %17, align 8, !tbaa !11
  %19 = mul i64 %18, 2
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %20, i32 0, i32 1
  store i64 %19, ptr %21, align 8, !tbaa !13
  %22 = call noundef i64 @_ZN4Simd4Base10AlgCacheL1Ev()
  %23 = udiv i64 %22, 4
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %24, i32 0, i32 10
  %26 = load i64, ptr %25, align 8, !tbaa !14
  %27 = udiv i64 %23, %26
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %28, i32 0, i32 11
  %30 = load i64, ptr %29, align 8, !tbaa !19
  %31 = udiv i64 %27, %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %32, i32 0, i32 1
  %34 = load i64, ptr %33, align 8, !tbaa !13
  %35 = udiv i64 %31, %34
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %36, i32 0, i32 0
  %38 = load i64, ptr %37, align 8, !tbaa !20
  %39 = call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %35, i64 noundef %38)
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %40, i32 0, i32 3
  store i64 %39, ptr %41, align 8, !tbaa !21
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %42, i32 0, i32 6
  %44 = load i64, ptr %43, align 8, !tbaa !22
  store i64 %44, ptr %7, align 8, !tbaa !9
  br label %45

45:                                               ; preds = %82, %2
  %46 = load i64, ptr %7, align 8, !tbaa !9
  %47 = icmp uge i64 %46, 1
  br i1 %47, label %49, label %48

48:                                               ; preds = %45
  store i32 2, ptr %8, align 4
  br label %85

49:                                               ; preds = %45
  %50 = load i64, ptr %7, align 8, !tbaa !9
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %51, i32 0, i32 2
  store i64 %50, ptr %52, align 8, !tbaa !23
  %53 = load ptr, ptr %6, align 8, !tbaa !5
  %54 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %53, i32 0, i32 3
  %55 = load i64, ptr %54, align 8, !tbaa !21
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %56, i32 0, i32 2
  %58 = load i64, ptr %57, align 8, !tbaa !24
  %59 = mul i64 %55, %58
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %60, i32 0, i32 2
  %62 = load i64, ptr %61, align 8, !tbaa !23
  %63 = load ptr, ptr %5, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %63, i32 0, i32 14
  %65 = load i64, ptr %64, align 8, !tbaa !25
  %66 = mul i64 %62, %65
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %67, i32 0, i32 10
  %69 = load i64, ptr %68, align 8, !tbaa !14
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %70, i32 0, i32 12
  %72 = load i64, ptr %71, align 8, !tbaa !26
  %73 = mul i64 %69, %72
  %74 = add i64 %66, %73
  %75 = sub i64 %74, 1
  %76 = mul i64 %59, %75
  %77 = mul i64 %76, 4
  %78 = call noundef i64 @_ZN4Simd4Base10AlgCacheL2Ev()
  %79 = icmp ule i64 %77, %78
  br i1 %79, label %80, label %81

80:                                               ; preds = %49
  store i32 2, ptr %8, align 4
  br label %85

81:                                               ; preds = %49
  br label %82

82:                                               ; preds = %81
  %83 = load i64, ptr %7, align 8, !tbaa !9
  %84 = add i64 %83, -1
  store i64 %84, ptr %7, align 8, !tbaa !9
  br label %45, !llvm.loop !27

85:                                               ; preds = %80, %48
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %86

86:                                               ; preds = %85
  %87 = call noundef i64 @_ZN4Simd4Base10AlgCacheL3Ev()
  %88 = udiv i64 %87, 4
  %89 = load ptr, ptr %5, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %89, i32 0, i32 10
  %91 = load i64, ptr %90, align 8, !tbaa !14
  %92 = udiv i64 %88, %91
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %93, i32 0, i32 11
  %95 = load i64, ptr %94, align 8, !tbaa !19
  %96 = udiv i64 %92, %95
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %97, i32 0, i32 3
  %99 = load i64, ptr %98, align 8, !tbaa !21
  %100 = udiv i64 %96, %99
  %101 = load ptr, ptr %6, align 8, !tbaa !5
  %102 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %101, i32 0, i32 1
  %103 = load i64, ptr %102, align 8, !tbaa !13
  %104 = call noundef i64 @_ZN4Simd10AlignLoAnyEmm(i64 noundef %100, i64 noundef %103)
  %105 = load ptr, ptr %6, align 8, !tbaa !5
  %106 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %105, i32 0, i32 1
  %107 = load i64, ptr %106, align 8, !tbaa !13
  %108 = load ptr, ptr %5, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %108, i32 0, i32 5
  %110 = load i64, ptr %109, align 8, !tbaa !29
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %111, i32 0, i32 1
  %113 = load i64, ptr %112, align 8, !tbaa !13
  %114 = call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %110, i64 noundef %113)
  %115 = call noundef i64 @_ZN4Simd13RestrictRangeImEET_S1_S1_S1_(i64 noundef %104, i64 noundef %107, i64 noundef %114)
  %116 = load ptr, ptr %6, align 8, !tbaa !5
  %117 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %116, i32 0, i32 4
  store i64 %115, ptr %117, align 8, !tbaa !30
  %118 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %9, i32 0, i32 7
  %119 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old", ptr %118, i32 0, i32 3
  %120 = load ptr, ptr %5, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %120, i32 0, i32 5
  %122 = load i64, ptr %121, align 8, !tbaa !29
  %123 = load ptr, ptr %6, align 8, !tbaa !5
  %124 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %123, i32 0, i32 1
  %125 = load i64, ptr %124, align 8, !tbaa !13
  %126 = call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %122, i64 noundef %125)
  %127 = load ptr, ptr %5, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %127, i32 0, i32 10
  %129 = load i64, ptr %128, align 8, !tbaa !14
  %130 = mul i64 %126, %129
  %131 = load ptr, ptr %5, align 8, !tbaa !5
  %132 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %131, i32 0, i32 11
  %133 = load i64, ptr %132, align 8, !tbaa !19
  %134 = mul i64 %130, %133
  %135 = load ptr, ptr %5, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %135, i32 0, i32 0
  %137 = load i64, ptr %136, align 8, !tbaa !20
  %138 = mul i64 %134, %137
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %119, i64 noundef %138, i1 noundef zeroext false, i64 noundef 8)
  %139 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %9, i32 0, i32 4
  %140 = load ptr, ptr %5, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %140, i32 0, i32 5
  %142 = load i64, ptr %141, align 8, !tbaa !29
  %143 = load ptr, ptr %6, align 8, !tbaa !5
  %144 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %143, i32 0, i32 1
  %145 = load i64, ptr %144, align 8, !tbaa !13
  %146 = call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %142, i64 noundef %145)
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %139, i64 noundef %146, i1 noundef zeroext true, i64 noundef 8)
  %147 = load ptr, ptr %5, align 8, !tbaa !5
  %148 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %147, i32 0, i32 21
  %149 = load i32, ptr %148, align 8, !tbaa !31
  %150 = icmp eq i32 %149, 2
  br i1 %150, label %156, label %151

151:                                              ; preds = %86
  %152 = load ptr, ptr %5, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %152, i32 0, i32 21
  %154 = load i32, ptr %153, align 8, !tbaa !31
  %155 = icmp eq i32 %154, 4
  br i1 %155, label %156, label %165

156:                                              ; preds = %151, %86
  %157 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %9, i32 0, i32 5
  %158 = load ptr, ptr %5, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %158, i32 0, i32 5
  %160 = load i64, ptr %159, align 8, !tbaa !29
  %161 = load ptr, ptr %6, align 8, !tbaa !5
  %162 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %161, i32 0, i32 1
  %163 = load i64, ptr %162, align 8, !tbaa !13
  %164 = call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %160, i64 noundef %163)
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %157, i64 noundef %164, i1 noundef zeroext true, i64 noundef 8)
  br label %167

165:                                              ; preds = %151
  %166 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %9, i32 0, i32 5
  call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %166, i64 noundef 2, i1 noundef zeroext true, i64 noundef 8)
  br label %167

167:                                              ; preds = %165, %156
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret void
}

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !7, i64 40, !10, i64 56}
!13 = !{!12, !10, i64 8}
!14 = !{!15, !10, i64 64}
!15 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !16, i64 24, !17, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !16, i64 56, !17, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !18, i64 152}
!16 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!17 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!18 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!19 = !{!15, !10, i64 72}
!20 = !{!15, !10, i64 0}
!21 = !{!12, !10, i64 24}
!22 = !{!15, !10, i64 40}
!23 = !{!12, !10, i64 16}
!24 = !{!15, !10, i64 16}
!25 = !{!15, !10, i64 96}
!26 = !{!15, !10, i64 80}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = !{!15, !10, i64 32}
!30 = !{!12, !10, i64 32}
!31 = !{!15, !18, i64 152}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL3Ev() local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL1Ev() local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd4Base10AlgCacheL2Ev() local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i64 @_ZN4Simd13RestrictRangeImEET_S1_S1_S1_(i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd10AlignLoAnyEmm(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect14OldSetAlgParamEm(ptr noundef nonnull align 8 dereferenceable(664) %0, i64 noundef %1) local_unnamed_addr #2 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = getelementptr inbounds i8, ptr %0, i64 584
  store i64 %1, ptr %4, align 8, !tbaa !5
  %5 = shl i64 %1, 1
  %6 = getelementptr inbounds i8, ptr %0, i64 592
  store i64 %5, ptr %6, align 8, !tbaa !10
  %7 = tail call noundef i64 @_ZN4Simd4Base10AlgCacheL1Ev()
  %8 = lshr i64 %7, 2
  %9 = getelementptr inbounds i8, ptr %0, i64 72
  %10 = load i64, ptr %9, align 8, !tbaa !11
  %11 = udiv i64 %8, %10
  %12 = getelementptr inbounds i8, ptr %0, i64 80
  %13 = load i64, ptr %12, align 8, !tbaa !16
  %14 = udiv i64 %11, %13
  %15 = load i64, ptr %6, align 8, !tbaa !10
  %16 = udiv i64 %14, %15
  %17 = load i64, ptr %3, align 8, !tbaa !17
  %18 = tail call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %16, i64 noundef %17)
  %19 = getelementptr inbounds i8, ptr %0, i64 608
  store i64 %18, ptr %19, align 8, !tbaa !18
  %20 = getelementptr inbounds i8, ptr %0, i64 48
  %21 = load i64, ptr %20, align 8, !tbaa !19
  %22 = getelementptr inbounds i8, ptr %0, i64 600
  %.not41 = icmp eq i64 %21, 0
  br i1 %.not41, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %23 = getelementptr inbounds i8, ptr %0, i64 24
  %24 = getelementptr inbounds i8, ptr %0, i64 104
  %25 = getelementptr inbounds i8, ptr %0, i64 88
  br label %26

26:                                               ; preds = %26, %.lr.ph
  %.042 = phi i64 [ %21, %.lr.ph ], [ %40, %26 ]
  store i64 %.042, ptr %22, align 8, !tbaa !20
  %27 = load i64, ptr %19, align 8, !tbaa !18
  %28 = load i64, ptr %23, align 8, !tbaa !21
  %29 = load i64, ptr %24, align 8, !tbaa !22
  %30 = mul i64 %29, %.042
  %31 = load i64, ptr %9, align 8, !tbaa !11
  %32 = load i64, ptr %25, align 8, !tbaa !23
  %33 = mul i64 %32, %31
  %34 = add i64 %30, 4611686018427387903
  %35 = add i64 %34, %33
  %36 = shl i64 %27, 2
  %37 = mul i64 %36, %28
  %38 = mul i64 %37, %35
  %39 = tail call noundef i64 @_ZN4Simd4Base10AlgCacheL2Ev()
  %.not40 = icmp ule i64 %38, %39
  %40 = add i64 %.042, -1
  %.not = icmp eq i64 %40, 0
  %or.cond = select i1 %.not40, i1 true, i1 %.not
  br i1 %or.cond, label %._crit_edge, label %26, !llvm.loop !24

._crit_edge:                                      ; preds = %26, %2
  %41 = tail call noundef i64 @_ZN4Simd4Base10AlgCacheL3Ev()
  %42 = lshr i64 %41, 2
  %43 = load i64, ptr %9, align 8, !tbaa !11
  %44 = udiv i64 %42, %43
  %45 = load i64, ptr %12, align 8, !tbaa !16
  %46 = udiv i64 %44, %45
  %47 = load i64, ptr %19, align 8, !tbaa !18
  %48 = udiv i64 %46, %47
  %49 = load i64, ptr %6, align 8, !tbaa !10
  %50 = tail call noundef i64 @_ZN4Simd10AlignLoAnyEmm(i64 noundef %48, i64 noundef %49)
  %51 = load i64, ptr %6, align 8, !tbaa !10
  %52 = getelementptr inbounds i8, ptr %0, i64 40
  %53 = load i64, ptr %52, align 8, !tbaa !26
  %54 = tail call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %53, i64 noundef %51)
  %55 = tail call noundef i64 @_ZN4Simd13RestrictRangeImEET_S1_S1_S1_(i64 noundef %50, i64 noundef %51, i64 noundef %54)
  %56 = getelementptr inbounds i8, ptr %0, i64 616
  store i64 %55, ptr %56, align 8, !tbaa !27
  %57 = getelementptr inbounds i8, ptr %0, i64 648
  %58 = load i64, ptr %52, align 8, !tbaa !26
  %59 = load i64, ptr %6, align 8, !tbaa !10
  %60 = tail call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %58, i64 noundef %59)
  %61 = load i64, ptr %9, align 8, !tbaa !11
  %62 = mul i64 %61, %60
  %63 = load i64, ptr %12, align 8, !tbaa !16
  %64 = mul i64 %62, %63
  %65 = load i64, ptr %3, align 8, !tbaa !17
  %66 = mul i64 %64, %65
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %57, i64 noundef %66, i1 noundef zeroext false, i64 noundef 8)
  %67 = getelementptr inbounds i8, ptr %0, i64 472
  %68 = load i64, ptr %52, align 8, !tbaa !26
  %69 = load i64, ptr %6, align 8, !tbaa !10
  %70 = tail call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %68, i64 noundef %69)
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %67, i64 noundef %70, i1 noundef zeroext true, i64 noundef 8)
  %71 = getelementptr inbounds i8, ptr %0, i64 160
  %72 = load i32, ptr %71, align 8, !tbaa !28
  switch i32 %72, label %78 [
    i32 2, label %73
    i32 4, label %73
  ]

73:                                               ; preds = %._crit_edge, %._crit_edge
  %74 = getelementptr inbounds i8, ptr %0, i64 488
  %75 = load i64, ptr %52, align 8, !tbaa !26
  %76 = load i64, ptr %6, align 8, !tbaa !10
  %77 = tail call noundef i64 @_ZN4Simd10AlignHiAnyEmm(i64 noundef %75, i64 noundef %76)
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %74, i64 noundef %77, i1 noundef zeroext true, i64 noundef 8)
  br label %80

78:                                               ; preds = %._crit_edge
  %79 = getelementptr inbounds i8, ptr %0, i64 488
  tail call void @_ZN4Simd5ArrayIfE6ResizeEmbm(ptr noundef nonnull align 8 dereferenceable(16) %79, i64 noundef 2, i1 noundef zeroext true, i64 noundef 8)
  br label %80

80:                                               ; preds = %78, %73
  ret void
}

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !8, i64 40, !7, i64 56}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!6, !7, i64 8}
!11 = !{!12, !7, i64 64}
!12 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !13, i64 24, !14, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !13, i64 56, !14, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !15, i64 152}
!13 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!14 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!15 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!16 = !{!12, !7, i64 72}
!17 = !{!12, !7, i64 0}
!18 = !{!6, !7, i64 24}
!19 = !{!12, !7, i64 40}
!20 = !{!6, !7, i64 16}
!21 = !{!12, !7, i64 16}
!22 = !{!12, !7, i64 96}
!23 = !{!12, !7, i64 80}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = !{!12, !7, i64 32}
!27 = !{!6, !7, i64 32}
!28 = !{!12, !15, i64 152}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass