; LLVM IR from libxsmm/libxsmm :: src (generator_mateltwise_unary_binary_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.libxsmm_generated_code = type { ptr, i32, i32, i32, i32, i32, i32 }

@.str = external hidden unnamed_addr constant [97 x i8], align 1
@libxsmm_ninit = external global i32, align 4
@libxsmm_verbosity = external global i32, align 4
@__func__.libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve = external hidden unnamed_addr constant [66 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @libxsmm_handle_error(ptr noundef, i32 noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) #1

declare i32 @libxsmm_cpuid_vlen32(i32 noundef) #1

declare void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_sve_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6, i8 noundef zeroext %7, i8 noundef zeroext %8, ptr noundef %9) #2 {
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i8, align 1
  %16 = alloca i8, align 1
  %17 = alloca i8, align 1
  %18 = alloca i8, align 1
  %19 = alloca i8, align 1
  %20 = alloca ptr, align 8
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca i8, align 1
  %25 = alloca i32, align 4
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca i32, align 4
  store ptr %0, ptr %11, align 8, !tbaa !5
  store i32 %1, ptr %12, align 4, !tbaa !9
  store i32 %2, ptr %13, align 4, !tbaa !9
  store i32 %3, ptr %14, align 4, !tbaa !9
  store i8 %4, ptr %15, align 1, !tbaa !11
  store i8 %5, ptr %16, align 1, !tbaa !11
  store i8 %6, ptr %17, align 1, !tbaa !11
  store i8 %7, ptr %18, align 1, !tbaa !11
  store i8 %8, ptr %19, align 1, !tbaa !11
  store ptr %9, ptr %20, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #3
  %30 = load ptr, ptr %11, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.libxsmm_generated_code, ptr %30, i32 0, i32 6
  %32 = load i32, ptr %31, align 4, !tbaa !12
  %33 = call i32 @libxsmm_cpuid_vlen32(i32 noundef %32)
  %34 = mul nsw i32 4, %33
  store i32 %34, ptr %21, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #3
  %35 = load i32, ptr %21, align 4, !tbaa !9
  %36 = udiv i32 %35, 8
  store i32 %36, ptr %22, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #3
  %37 = load i32, ptr %22, align 4, !tbaa !9
  %38 = udiv i32 %37, 4
  store i32 %38, ptr %23, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %24) #3
  %39 = load i32, ptr %13, align 4, !tbaa !9
  %40 = and i32 %39, 3
  %41 = trunc i32 %40 to i8
  store i8 %41, ptr %24, align 1, !tbaa !11
  %42 = load ptr, ptr %11, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.libxsmm_generated_code, ptr %42, i32 0, i32 6
  %44 = load i32, ptr %43, align 4, !tbaa !12
  %45 = icmp uge i32 %44, 2301
  br i1 %45, label %46, label %51

46:                                               ; preds = %10
  %47 = load ptr, ptr %11, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.libxsmm_generated_code, ptr %47, i32 0, i32 6
  %49 = load i32, ptr %48, align 4, !tbaa !12
  %50 = icmp ult i32 %49, 2999
  br i1 %50, label %60, label %51

51:                                               ; preds = %46, %10
  %52 = load ptr, ptr %11, align 8, !tbaa !5
  %53 = load i32, ptr @libxsmm_ninit, align 4, !tbaa !9
  %54 = icmp ult i32 1, %53
  br i1 %54, label %55, label %57

55:                                               ; preds = %51
  %56 = load i32, ptr @libxsmm_verbosity, align 4, !tbaa !9
  br label %58

57:                                               ; preds = %51
  br label %58

58:                                               ; preds = %57, %55
  %59 = phi i32 [ %56, %55 ], [ 1, %57 ]
  call void @libxsmm_handle_error(ptr noundef %52, i32 noundef 90005, ptr noundef @__func__.libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve, ptr noundef @.str, i32 noundef 1925, i32 noundef %59)
  br label %60

60:                                               ; preds = %58, %46
  %61 = load i8, ptr %24, align 1, !tbaa !11
  %62 = zext i8 %61 to i32
  %63 = icmp eq i32 %62, 0
  br i1 %63, label %64, label %146

64:                                               ; preds = %60
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #3
  %65 = load i32, ptr %14, align 4, !tbaa !9
  %66 = load i32, ptr %13, align 4, !tbaa !9
  %67 = sub i32 %65, %66
  %68 = icmp ult i32 %67, 3
  br i1 %68, label %69, label %72

69:                                               ; preds = %64
  %70 = load i32, ptr %14, align 4, !tbaa !9
  %71 = and i32 %70, 3
  br label %73

72:                                               ; preds = %64
  br label %73

73:                                               ; preds = %72, %69
  %74 = phi i32 [ %71, %69 ], [ 4, %72 ]
  store i32 %74, ptr %25, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %26) #3
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = add i32 %75, 15
  %77 = udiv i32 %76, 16
  %78 = mul i32 %77, 2
  store i32 %78, ptr %26, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %27) #3
  %79 = load i32, ptr %26, align 4, !tbaa !9
  %80 = load ptr, ptr %20, align 8, !tbaa !5
  %81 = getelementptr inbounds i32, ptr %80, i64 0
  %82 = load i32, ptr %81, align 4, !tbaa !9
  %83 = sub i32 %79, %82
  store i32 %83, ptr %27, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %28) #3
  %84 = load i32, ptr %25, align 4, !tbaa !9
  %85 = load i32, ptr %23, align 4, !tbaa !9
  %86 = mul i32 %84, %85
  %87 = load i32, ptr %27, align 4, !tbaa !9
  %88 = icmp ult i32 %86, %87
  br i1 %88, label %89, label %93

89:                                               ; preds = %73
  %90 = load i32, ptr %25, align 4, !tbaa !9
  %91 = load i32, ptr %23, align 4, !tbaa !9
  %92 = mul i32 %90, %91
  br label %95

93:                                               ; preds = %73
  %94 = load i32, ptr %27, align 4, !tbaa !9
  br label %95

95:                                               ; preds = %93, %89
  %96 = phi i32 [ %92, %89 ], [ %94, %93 ]
  store i32 %96, ptr %28, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %29) #3
  %97 = load i32, ptr %28, align 4, !tbaa !9
  %98 = add i32 %97, 15
  %99 = udiv i32 %98, 16
  %100 = mul i32 %99, 16
  store i32 %100, ptr %29, align 4, !tbaa !9
  %101 = load ptr, ptr %11, align 8, !tbaa !5
  %102 = load i8, ptr %18, align 1, !tbaa !11
  %103 = zext i8 %102 to i32
  %104 = load i32, ptr %29, align 4, !tbaa !9
  %105 = zext i32 %104 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %101, i32 noundef 4097, i32 noundef 63, i32 noundef %103, i32 noundef 63, i64 noundef %105)
  %106 = load ptr, ptr %11, align 8, !tbaa !5
  %107 = load i8, ptr %19, align 1, !tbaa !11
  %108 = zext i8 %107 to i32
  %109 = load i32, ptr %28, align 4, !tbaa !9
  %110 = load i8, ptr %18, align 1, !tbaa !11
  %111 = zext i8 %110 to i32
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %106, i32 noundef %108, i32 noundef %109, i32 noundef %111)
  %112 = load ptr, ptr %11, align 8, !tbaa !5
  %113 = load i8, ptr %16, align 1, !tbaa !11
  %114 = zext i8 %113 to i32
  %115 = load i8, ptr %15, align 1, !tbaa !11
  %116 = zext i8 %115 to i32
  %117 = load i8, ptr %19, align 1, !tbaa !11
  %118 = zext i8 %117 to i32
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %112, i32 noundef -1543462778, i32 noundef %114, i32 noundef 0, i32 noundef 0, i32 noundef %116, i32 noundef %118)
  %119 = load ptr, ptr %11, align 8, !tbaa !5
  %120 = load i8, ptr %15, align 1, !tbaa !11
  %121 = zext i8 %120 to i32
  %122 = load i8, ptr %19, align 1, !tbaa !11
  %123 = zext i8 %122 to i32
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %119, i32 noundef -469704570, i32 noundef 63, i32 noundef 0, i32 noundef 0, i32 noundef %121, i32 noundef %123)
  %124 = load ptr, ptr %11, align 8, !tbaa !5
  %125 = load i8, ptr %19, align 1, !tbaa !11
  %126 = zext i8 %125 to i32
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %124, i32 noundef -2055208954, i32 noundef 63, i32 noundef 0, i32 noundef 0, i32 noundef %126, i32 noundef 0)
  %127 = load ptr, ptr %11, align 8, !tbaa !5
  %128 = load i8, ptr %16, align 1, !tbaa !11
  %129 = zext i8 %128 to i32
  %130 = load i8, ptr %18, align 1, !tbaa !11
  %131 = zext i8 %130 to i32
  %132 = load i8, ptr %16, align 1, !tbaa !11
  %133 = zext i8 %132 to i32
  %134 = load i32, ptr %28, align 4, !tbaa !9
  %135 = zext i32 %134 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %127, i32 noundef 4096, i32 noundef %129, i32 noundef %131, i32 noundef %133, i64 noundef %135)
  %136 = load ptr, ptr %11, align 8, !tbaa !5
  %137 = load i8, ptr %18, align 1, !tbaa !11
  %138 = zext i8 %137 to i32
  %139 = load i32, ptr %29, align 4, !tbaa !9
  %140 = zext i32 %139 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %136, i32 noundef 4096, i32 noundef 63, i32 noundef %138, i32 noundef 63, i64 noundef %140)
  %141 = load i32, ptr %28, align 4, !tbaa !9
  %142 = load ptr, ptr %20, align 8, !tbaa !5
  %143 = getelementptr inbounds i32, ptr %142, i64 0
  %144 = load i32, ptr %143, align 4, !tbaa !9
  %145 = add i32 %144, %141
  store i32 %145, ptr %143, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %29) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %28) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %27) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %26) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #3
  br label %146

146:                                              ; preds = %95, %60
  %147 = load ptr, ptr %11, align 8, !tbaa !5
  %148 = load i32, ptr %13, align 4, !tbaa !9
  %149 = and i32 %148, 2
  %150 = icmp ne i32 %149, 0
  %151 = zext i1 %150 to i64
  %152 = select i1 %150, i32 86000643, i32 85999619
  %153 = load i8, ptr %19, align 1, !tbaa !11
  %154 = zext i8 %153 to i32
  %155 = load i8, ptr %19, align 1, !tbaa !11
  %156 = zext i8 %155 to i32
  %157 = load i8, ptr %17, align 1, !tbaa !11
  %158 = zext i8 %157 to i32
  call void @libxsmm_aarch64_instruction_sve_compute(ptr noundef %147, i32 noundef %152, i32 noundef %154, i32 noundef %156, i8 noundef zeroext 0, i32 noundef %158, i32 noundef 0, i32 noundef 0)
  %159 = load ptr, ptr %11, align 8, !tbaa !5
  %160 = load i32, ptr %13, align 4, !tbaa !9
  %161 = and i32 %160, 1
  %162 = icmp ne i32 %161, 0
  %163 = zext i1 %162 to i64
  %164 = select i1 %162, i32 86000643, i32 85999619
  %165 = load i8, ptr %17, align 1, !tbaa !11
  %166 = zext i8 %165 to i32
  %167 = load i8, ptr %17, align 1, !tbaa !11
  %168 = zext i8 %167 to i32
  %169 = load i8, ptr %17, align 1, !tbaa !11
  %170 = zext i8 %169 to i32
  call void @libxsmm_aarch64_instruction_sve_compute(ptr noundef %159, i32 noundef %164, i32 noundef %166, i32 noundef %168, i8 noundef zeroext 0, i32 noundef %170, i32 noundef 0, i32 noundef 1)
  call void @llvm.lifetime.end.p0(i64 1, ptr %24) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #3
  ret void
}

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 28}
!13 = !{!"libxsmm_generated_code", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [97 x i8], align 1
@libxsmm_ninit = external local_unnamed_addr global i32, align 4
@libxsmm_verbosity = external local_unnamed_addr global i32, align 4
@__func__.libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve = external hidden unnamed_addr constant [66 x i8], align 1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

declare void @libxsmm_handle_error(ptr noundef, i32 noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare i32 @libxsmm_cpuid_vlen32(i32 noundef) local_unnamed_addr #0

declare void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sve_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6, i8 noundef zeroext %7, i8 noundef zeroext %8, ptr nocapture noundef %9) local_unnamed_addr #1 {
  %11 = getelementptr inbounds i8, ptr %0, i64 28
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %13 = tail call i32 @libxsmm_cpuid_vlen32(i32 noundef %12) #3
  %14 = lshr i32 %13, 3
  %15 = and i32 %14, 134217727
  %16 = and i32 %2, 3
  %17 = load i32, ptr %11, align 4, !tbaa !5
  %18 = add i32 %17, -2301
  %or.cond = icmp ult i32 %18, 698
  br i1 %or.cond, label %24, label %19

19:                                               ; preds = %10
  %20 = load i32, ptr @libxsmm_ninit, align 4, !tbaa !11
  %21 = icmp ugt i32 %20, 1
  %22 = load i32, ptr @libxsmm_verbosity, align 4
  %23 = select i1 %21, i32 %22, i32 1
  tail call void @libxsmm_handle_error(ptr noundef nonnull %0, i32 noundef 90005, ptr noundef nonnull @__func__.libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_sve, ptr noundef nonnull @.str, i32 noundef 1925, i32 noundef %23) #3
  br label %24

24:                                               ; preds = %10, %19
  %25 = icmp eq i32 %16, 0
  br i1 %25, label %26, label %._crit_edge

._crit_edge:                                      ; preds = %24
  %.pre = zext i8 %8 to i32
  br label %48

26:                                               ; preds = %24
  %27 = sub i32 %3, %2
  %28 = icmp ult i32 %27, 3
  %29 = and i32 %3, 3
  %30 = select i1 %28, i32 %29, i32 4
  %31 = add i32 %1, 15
  %32 = lshr i32 %31, 3
  %33 = and i32 %32, 536870910
  %34 = load i32, ptr %9, align 4, !tbaa !11
  %35 = sub i32 %33, %34
  %36 = mul nuw nsw i32 %15, %30
  %37 = tail call i32 @llvm.umin.i32(i32 %36, i32 %35)
  %38 = add nuw nsw i32 %37, 15
  %39 = and i32 %38, 2147483632
  %40 = zext i8 %7 to i32
  %41 = zext nneg i32 %39 to i64
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef nonnull %0, i32 noundef 4097, i32 noundef 63, i32 noundef %40, i32 noundef 63, i64 noundef %41) #3
  %42 = zext i8 %8 to i32
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef nonnull %0, i32 noundef %42, i32 noundef %37, i32 noundef %40) #3
  %43 = zext i8 %5 to i32
  %44 = zext i8 %4 to i32
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef nonnull %0, i32 noundef -1543462778, i32 noundef %43, i32 noundef 0, i32 noundef 0, i32 noundef %44, i32 noundef %42) #3
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef nonnull %0, i32 noundef -469704570, i32 noundef 63, i32 noundef 0, i32 noundef 0, i32 noundef %44, i32 noundef %42) #3
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef nonnull %0, i32 noundef -2055208954, i32 noundef 63, i32 noundef 0, i32 noundef 0, i32 noundef %42, i32 noundef 0) #3
  %45 = zext nneg i32 %37 to i64
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef nonnull %0, i32 noundef 4096, i32 noundef %43, i32 noundef %40, i32 noundef %43, i64 noundef %45) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef nonnull %0, i32 noundef 4096, i32 noundef 63, i32 noundef %40, i32 noundef 63, i64 noundef %41) #3
  %46 = load i32, ptr %9, align 4, !tbaa !11
  %47 = add i32 %46, %37
  store i32 %47, ptr %9, align 4, !tbaa !11
  br label %48

48:                                               ; preds = %._crit_edge, %26
  %.pre-phi = phi i32 [ %.pre, %._crit_edge ], [ %42, %26 ]
  %49 = and i32 %2, 2
  %.not = icmp eq i32 %49, 0
  %50 = select i1 %.not, i32 85999619, i32 86000643
  %51 = zext i8 %6 to i32
  tail call void @libxsmm_aarch64_instruction_sve_compute(ptr noundef nonnull %0, i32 noundef %50, i32 noundef %.pre-phi, i32 noundef %.pre-phi, i8 noundef zeroext 0, i32 noundef %51, i32 noundef 0, i32 noundef 0) #3
  %52 = and i32 %2, 1
  %.not56 = icmp eq i32 %52, 0
  %53 = select i1 %.not56, i32 85999619, i32 86000643
  tail call void @libxsmm_aarch64_instruction_sve_compute(ptr noundef nonnull %0, i32 noundef %53, i32 noundef %51, i32 noundef %51, i8 noundef zeroext 0, i32 noundef %51, i32 noundef 0, i32 noundef 1) #3
  ret void
}

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 28}
!6 = !{!"libxsmm_generated_code", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!10, !10, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass