; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution32fNhwcDirect)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunArgs" = type { ptr, ptr, ptr, ptr, ptr, ptr }
%"class.Simd::SynetConvolution32f" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", float, float, ptr, ptr, ptr, %"struct.Simd::Runtime", %"struct.Simd::Runtime.3", %"struct.Simd::Array", ptr, ptr, ptr, %"class.std::__cxx11::basic_string" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Runtime" = type { ptr, %"class.std::vector", %"class.std::__cxx11::basic_string" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Runtime.3" = type { ptr, %"class.std::vector.4", %"class.std::__cxx11::basic_string" }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Simd::Base::SynetConvolution32fNhwcDirect" = type { %"class.Simd::SynetConvolution32f", i64, i64, %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Runtime.9", %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" }
%"struct.Simd::Runtime.9" = type { ptr, %"class.std::vector.10", %"class.std::__cxx11::basic_string" }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" = type { i8, ptr, %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", %"struct.Simd::Array" }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam" = type { i64, i64, i64, i64, i64, [2 x ptr], i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7ForwardEPKfPfS4_(ptr noundef nonnull align 8 dereferenceable(664) %0, ptr noundef %1, ptr noundef %2, ptr noundef %3) unnamed_addr #1 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca %"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunArgs", align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %12 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %13 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 1
  store ptr %13, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  store i64 0, ptr %10, align 8, !tbaa !9
  br label %14

14:                                               ; preds = %61, %4
  %15 = load i64, ptr %10, align 8, !tbaa !9
  %16 = load ptr, ptr %9, align 8, !tbaa !5
  %17 = getelementptr inbounds %"struct.Simd::ConvParam", ptr %16, i32 0, i32 3
  %18 = load i64, ptr %17, align 8, !tbaa !11
  %19 = icmp ult i64 %15, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  br label %64

21:                                               ; preds = %14
  %22 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 7
  %23 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old", ptr %22, i32 0, i32 0
  %24 = load i8, ptr %23, align 8, !tbaa !19, !range !45, !noundef !46
  %25 = trunc i8 %24 to i1
  br i1 %25, label %26, label %41

26:                                               ; preds = %21
  %27 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 7
  %28 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old", ptr %27, i32 0, i32 1
  %29 = load ptr, ptr %28, align 8, !tbaa !47
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 1
  %32 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 7
  %33 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old", ptr %32, i32 0, i32 2
  %34 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 5
  %35 = load ptr, ptr %34, align 8, !tbaa !48
  %36 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 6
  %37 = load ptr, ptr %36, align 8, !tbaa !49
  %38 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 7
  %39 = load ptr, ptr %38, align 8, !tbaa !50
  %40 = load ptr, ptr %8, align 8, !tbaa !5
  call void %29(ptr noundef %30, ptr noundef nonnull align 8 dereferenceable(180) %31, ptr noundef nonnull align 8 dereferenceable(64) %33, ptr noundef %35, ptr noundef %37, ptr noundef %39, ptr noundef %40)
  br label %52

41:                                               ; preds = %21
  %42 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 6
  call void @llvm.lifetime.start.p0(i64 48, ptr %11) #4
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 1
  %45 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 5
  %46 = load ptr, ptr %45, align 8, !tbaa !48
  %47 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 6
  %48 = load ptr, ptr %47, align 8, !tbaa !49
  %49 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %12, i32 0, i32 7
  %50 = load ptr, ptr %49, align 8, !tbaa !50
  %51 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7RunArgsC2EPKfRKNS_9ConvParamES4_S4_S4_Pf(ptr noundef nonnull align 8 dereferenceable(48) %11, ptr noundef %43, ptr noundef nonnull align 8 dereferenceable(180) %44, ptr noundef %46, ptr noundef %48, ptr noundef %50, ptr noundef %51)
  call void @_ZN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE3RunERKS4_(ptr noundef nonnull align 8 dereferenceable(64) %42, ptr noundef nonnull align 8 dereferenceable(48) %11)
  call void @llvm.lifetime.end.p0(i64 48, ptr %11) #4
  br label %52

52:                                               ; preds = %41, %26
  %53 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 1
  %54 = load i64, ptr %53, align 8, !tbaa !51
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  %56 = getelementptr inbounds float, ptr %55, i64 %54
  store ptr %56, ptr %6, align 8, !tbaa !5
  %57 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %12, i32 0, i32 2
  %58 = load i64, ptr %57, align 8, !tbaa !52
  %59 = load ptr, ptr %8, align 8, !tbaa !5
  %60 = getelementptr inbounds float, ptr %59, i64 %58
  store ptr %60, ptr %8, align 8, !tbaa !5
  br label %61

61:                                               ; preds = %52
  %62 = load i64, ptr %10, align 8, !tbaa !9
  %63 = add i64 %62, 1
  store i64 %63, ptr %10, align 8, !tbaa !9
  br label %14, !llvm.loop !53

64:                                               ; preds = %20
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  ret void
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE3RunERKS4_(ptr noundef nonnull align 8 dereferenceable(64), ptr noundef nonnull align 8 dereferenceable(48)) #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7RunArgsC2EPKfRKNS_9ConvParamES4_S4_S4_Pf(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef, ptr noundef nonnull align 8 dereferenceable(180), ptr noundef, ptr noundef, ptr noundef, ptr noundef) unnamed_addr #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 168}
!12 = !{!"_ZTSN4Simd9ConvParamE", !13, i64 0, !17, i64 160, !10, i64 168, !18, i64 176}
!13 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !14, i64 24, !15, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !14, i64 56, !15, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !16, i64 152}
!14 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!15 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!16 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!17 = !{!"_ZTS8SimdBool", !7, i64 0}
!18 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!19 = !{!20, !43, i64 568}
!20 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirectE", !21, i64 0, !10, i64 440, !10, i64 448, !23, i64 456, !23, i64 472, !23, i64 488, !37, i64 504, !42, i64 568}
!21 = !{!"_ZTSN4Simd19SynetConvolution32fE", !22, i64 0, !12, i64 8, !23, i64 192, !24, i64 208, !24, i64 212, !6, i64 216, !6, i64 224, !6, i64 232, !25, i64 240, !32, i64 304, !23, i64 368, !6, i64 384, !6, i64 392, !6, i64 400, !30, i64 408}
!22 = !{!"_ZTSN4Simd9DeletableE"}
!23 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !10, i64 8}
!24 = !{!"float", !7, i64 0}
!25 = !{!"_ZTSN4Simd7RuntimeINS_8GemmFuncENS_8GemmArgsEEE", !6, i64 0, !26, i64 8, !30, i64 32}
!26 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !31, i64 0, !10, i64 8, !7, i64 16}
!31 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!32 = !{!"_ZTSN4Simd7RuntimeINS_10GemmCbFuncENS_10GemmCbArgsEEE", !6, i64 0, !33, i64 8, !30, i64 32}
!33 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEEE", !6, i64 0, !38, i64 8, !30, i64 32}
!38 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect3OldE", !43, i64 0, !6, i64 8, !44, i64 16, !23, i64 80}
!43 = !{!"bool", !7, i64 0}
!44 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !7, i64 40, !10, i64 56}
!45 = !{i8 0, i8 2}
!46 = !{}
!47 = !{!20, !6, i64 576}
!48 = !{!21, !6, i64 216}
!49 = !{!21, !6, i64 224}
!50 = !{!21, !6, i64 232}
!51 = !{!20, !10, i64 440}
!52 = !{!20, !10, i64 448}
!53 = distinct !{!53, !54}
!54 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunArgs" = type { ptr, ptr, ptr, ptr, ptr, ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7ForwardEPKfPfS4_(ptr noundef nonnull align 8 dereferenceable(664) %0, ptr noundef %1, ptr nocapture noundef readnone %2, ptr noundef %3) unnamed_addr #1 align 2 {
  %5 = alloca %"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunArgs", align 8
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = getelementptr inbounds i8, ptr %0, i64 176
  %8 = load i64, ptr %7, align 8, !tbaa !5
  %.not = icmp eq i64 %8, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %4
  %9 = getelementptr inbounds i8, ptr %0, i64 568
  %10 = getelementptr inbounds i8, ptr %0, i64 504
  %11 = getelementptr inbounds i8, ptr %0, i64 216
  %12 = getelementptr inbounds i8, ptr %0, i64 224
  %13 = getelementptr inbounds i8, ptr %0, i64 232
  %14 = getelementptr inbounds i8, ptr %0, i64 576
  %15 = getelementptr inbounds i8, ptr %0, i64 584
  %16 = getelementptr inbounds i8, ptr %0, i64 440
  %17 = getelementptr inbounds i8, ptr %0, i64 448
  br label %18

._crit_edge:                                      ; preds = %30, %4
  ret void

18:                                               ; preds = %.lr.ph, %30
  %.013 = phi i64 [ 0, %.lr.ph ], [ %35, %30 ]
  %.0912 = phi ptr [ %1, %.lr.ph ], [ %32, %30 ]
  %.01011 = phi ptr [ %3, %.lr.ph ], [ %34, %30 ]
  %19 = load i8, ptr %9, align 8, !tbaa !16, !range !43, !noundef !44
  %20 = trunc nuw i8 %19 to i1
  br i1 %20, label %21, label %26

21:                                               ; preds = %18
  %22 = load ptr, ptr %14, align 8, !tbaa !45
  %23 = load ptr, ptr %11, align 8, !tbaa !46
  %24 = load ptr, ptr %12, align 8, !tbaa !47
  %25 = load ptr, ptr %13, align 8, !tbaa !48
  call void %22(ptr noundef %.0912, ptr noundef nonnull align 8 dereferenceable(180) %6, ptr noundef nonnull align 8 dereferenceable(64) %15, ptr noundef %23, ptr noundef %24, ptr noundef %25, ptr noundef %.01011)
  br label %30

26:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 48, ptr nonnull %5) #4
  %27 = load ptr, ptr %11, align 8, !tbaa !46
  %28 = load ptr, ptr %12, align 8, !tbaa !47
  %29 = load ptr, ptr %13, align 8, !tbaa !48
  call void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7RunArgsC2EPKfRKNS_9ConvParamES4_S4_S4_Pf(ptr noundef nonnull align 8 dereferenceable(48) %5, ptr noundef %.0912, ptr noundef nonnull align 8 dereferenceable(180) %6, ptr noundef %27, ptr noundef %28, ptr noundef %29, ptr noundef %.01011)
  call void @_ZN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE3RunERKS4_(ptr noundef nonnull align 8 dereferenceable(64) %10, ptr noundef nonnull align 8 dereferenceable(48) %5)
  call void @llvm.lifetime.end.p0(i64 48, ptr nonnull %5) #4
  br label %30

30:                                               ; preds = %26, %21
  %31 = load i64, ptr %16, align 8, !tbaa !49
  %32 = getelementptr inbounds float, ptr %.0912, i64 %31
  %33 = load i64, ptr %17, align 8, !tbaa !50
  %34 = getelementptr inbounds float, ptr %.01011, i64 %33
  %35 = add nuw i64 %.013, 1
  %36 = load i64, ptr %7, align 8, !tbaa !5
  %37 = icmp ult i64 %35, %36
  br i1 %37, label %18, label %._crit_edge, !llvm.loop !51
}

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE3RunERKS4_(ptr noundef nonnull align 8 dereferenceable(64), ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect7RunArgsC2EPKfRKNS_9ConvParamES4_S4_S4_Pf(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef, ptr noundef nonnull align 8 dereferenceable(180), ptr noundef, ptr noundef, ptr noundef, ptr noundef) unnamed_addr #3 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 168}
!6 = !{!"_ZTSN4Simd9ConvParamE", !7, i64 0, !14, i64 160, !8, i64 168, !15, i64 176}
!7 = !{!"_ZTS25SimdConvolutionParameters", !8, i64 0, !8, i64 8, !8, i64 16, !11, i64 24, !12, i64 28, !8, i64 32, !8, i64 40, !8, i64 48, !11, i64 56, !12, i64 60, !8, i64 64, !8, i64 72, !8, i64 80, !8, i64 88, !8, i64 96, !8, i64 104, !8, i64 112, !8, i64 120, !8, i64 128, !8, i64 136, !8, i64 144, !13, i64 152}
!8 = !{!"long", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"_ZTS18SimdTensorDataType", !9, i64 0}
!12 = !{!"_ZTS20SimdTensorFormatType", !9, i64 0}
!13 = !{!"_ZTS29SimdConvolutionActivationType", !9, i64 0}
!14 = !{!"_ZTS8SimdBool", !9, i64 0}
!15 = !{!"_ZTS26SimdSynetCompatibilityType", !9, i64 0}
!16 = !{!17, !41, i64 568}
!17 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirectE", !18, i64 0, !8, i64 440, !8, i64 448, !20, i64 456, !20, i64 472, !20, i64 488, !35, i64 504, !40, i64 568}
!18 = !{!"_ZTSN4Simd19SynetConvolution32fE", !19, i64 0, !6, i64 8, !20, i64 192, !22, i64 208, !22, i64 212, !21, i64 216, !21, i64 224, !21, i64 232, !23, i64 240, !30, i64 304, !20, i64 368, !21, i64 384, !21, i64 392, !21, i64 400, !28, i64 408}
!19 = !{!"_ZTSN4Simd9DeletableE"}
!20 = !{!"_ZTSN4Simd5ArrayIfEE", !21, i64 0, !8, i64 8}
!21 = !{!"any pointer", !9, i64 0}
!22 = !{!"float", !9, i64 0}
!23 = !{!"_ZTSN4Simd7RuntimeINS_8GemmFuncENS_8GemmArgsEEE", !21, i64 0, !24, i64 8, !28, i64 32}
!24 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !21, i64 0, !21, i64 8, !21, i64 16}
!28 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !29, i64 0, !8, i64 8, !9, i64 16}
!29 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !21, i64 0}
!30 = !{!"_ZTSN4Simd7RuntimeINS_10GemmCbFuncENS_10GemmCbArgsEEE", !21, i64 0, !31, i64 8, !28, i64 32}
!31 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !21, i64 0, !21, i64 8, !21, i64 16}
!35 = !{!"_ZTSN4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEEE", !21, i64 0, !36, i64 8, !28, i64 32}
!36 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_4Base29SynetConvolution32fNhwcDirect7RunFuncENS3_7RunArgsEE9CandidateESaIS7_EE17_Vector_impl_dataE", !21, i64 0, !21, i64 8, !21, i64 16}
!40 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect3OldE", !41, i64 0, !21, i64 8, !42, i64 16, !20, i64 80}
!41 = !{!"bool", !9, i64 0}
!42 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !8, i64 0, !8, i64 8, !8, i64 16, !8, i64 24, !8, i64 32, !9, i64 40, !8, i64 56}
!43 = !{i8 0, i8 2}
!44 = !{}
!45 = !{!17, !21, i64 576}
!46 = !{!18, !21, i64 216}
!47 = !{!18, !21, i64 224}
!48 = !{!18, !21, i64 232}
!49 = !{!17, !8, i64 440}
!50 = !{!17, !8, i64 448}
!51 = distinct !{!51, !52}
!52 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass