; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution16b)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base23SynetConvolution16bInitEmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(i64 noundef %0, ptr noundef %1, i32 noundef %2) #1 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca %"struct.Simd::ConvParam", align 8
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store i64 %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 184, ptr %8) #6
  %12 = load i64, ptr %5, align 8, !tbaa !5
  %13 = load ptr, ptr %6, align 8, !tbaa !9
  %14 = load i32, ptr %7, align 4, !tbaa !11
  call void @_ZN4Simd9ConvParamC2EmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(180) %8, i64 noundef %12, ptr noundef %13, i32 noundef %14)
  %15 = call noundef zeroext i1 @_ZN4Simd9ConvParam5ValidE18SimdTensorDataTypeS1_(ptr noundef nonnull align 8 dereferenceable(180) %8, i32 noundef 0, i32 noundef 7)
  br i1 %15, label %17, label %16

16:                                               ; preds = %3
  store ptr null, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

17:                                               ; preds = %3
  %18 = call noundef zeroext i1 @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwise10PreferableERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(180) %8)
  br i1 %18, label %19, label %26

19:                                               ; preds = %17
  %20 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 368) #7
  invoke void @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwiseC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(368) %20, ptr noundef nonnull align 8 dereferenceable(180) %8)
          to label %21 unwind label %22

21:                                               ; preds = %19
  store ptr %20, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

22:                                               ; preds = %19
  %23 = landingpad { ptr, i32 }
          cleanup
  %24 = extractvalue { ptr, i32 } %23, 0
  store ptr %24, ptr %10, align 8
  %25 = extractvalue { ptr, i32 } %23, 1
  store i32 %25, ptr %11, align 4
  call void @_ZdlPvm(ptr noundef %20, i64 noundef 368) #8
  br label %35

26:                                               ; preds = %17
  %27 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 432) #7
  invoke void @_ZN4Simd4Base23SynetConvolution16bGemmC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(432) %27, ptr noundef nonnull align 8 dereferenceable(180) %8)
          to label %28 unwind label %29

28:                                               ; preds = %26
  store ptr %27, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

29:                                               ; preds = %26
  %30 = landingpad { ptr, i32 }
          cleanup
  %31 = extractvalue { ptr, i32 } %30, 0
  store ptr %31, ptr %10, align 8
  %32 = extractvalue { ptr, i32 } %30, 1
  store i32 %32, ptr %11, align 4
  call void @_ZdlPvm(ptr noundef %27, i64 noundef 432) #8
  br label %35

33:                                               ; preds = %28, %21, %16
  call void @llvm.lifetime.end.p0(i64 184, ptr %8) #6
  %34 = load ptr, ptr %4, align 8
  ret ptr %34

35:                                               ; preds = %29, %22
  call void @llvm.lifetime.end.p0(i64 184, ptr %8) #6
  br label %36

36:                                               ; preds = %35
  %37 = load ptr, ptr %10, align 8
  %38 = load i32, ptr %11, align 4
  %39 = insertvalue { ptr, i32 } poison, ptr %37, 0
  %40 = insertvalue { ptr, i32 } %39, i32 %38, 1
  resume { ptr, i32 } %40
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd9ConvParamC2EmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(180), i64 noundef, ptr noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd9ConvParam5ValidE18SimdTensorDataTypeS1_(ptr noundef nonnull align 8 dereferenceable(180), i32 noundef, i32 noundef) #2 align 2

declare noundef zeroext i1 @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwise10PreferableERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(180)) #3

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #4

declare void @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwiseC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(368), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #5

declare void @_ZN4Simd4Base23SynetConvolution16bGemmC1ERKNS_9ConvParamE(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_ZN4Simd4Base23SynetConvolution16bInitEmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(i64 noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #1 personality ptr @__gxx_personality_v0 {
  %4 = alloca %"struct.Simd::ConvParam", align 8
  call void @llvm.lifetime.start.p0(i64 184, ptr nonnull %4) #6
  call void @_ZN4Simd9ConvParamC2EmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(180) %4, i64 noundef %0, ptr noundef %1, i32 noundef %2)
  %5 = call noundef zeroext i1 @_ZN4Simd9ConvParam5ValidE18SimdTensorDataTypeS1_(ptr noundef nonnull align 8 dereferenceable(180) %4, i32 noundef 0, i32 noundef 7)
  br i1 %5, label %6, label %16

6:                                                ; preds = %3
  %7 = call noundef zeroext i1 @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwise10PreferableERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(180) %4)
  br i1 %7, label %8, label %12

8:                                                ; preds = %6
  %9 = call noalias noundef nonnull dereferenceable(368) ptr @_Znwm(i64 noundef 368) #7
  invoke void @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwiseC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(368) %9, ptr noundef nonnull align 8 dereferenceable(180) %4)
          to label %16 unwind label %10

10:                                               ; preds = %8
  %11 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %9, i64 noundef 368) #8
  br label %17

12:                                               ; preds = %6
  %13 = call noalias noundef nonnull dereferenceable(432) ptr @_Znwm(i64 noundef 432) #7
  invoke void @_ZN4Simd4Base23SynetConvolution16bGemmC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(432) %13, ptr noundef nonnull align 8 dereferenceable(180) %4)
          to label %16 unwind label %14

14:                                               ; preds = %12
  %15 = landingpad { ptr, i32 }
          cleanup
  call void @_ZdlPvm(ptr noundef nonnull %13, i64 noundef 432) #8
  br label %17

16:                                               ; preds = %12, %8, %3
  %.06 = phi ptr [ null, %3 ], [ %9, %8 ], [ %13, %12 ]
  call void @llvm.lifetime.end.p0(i64 184, ptr nonnull %4) #6
  ret ptr %.06

17:                                               ; preds = %14, %10
  %.pn = phi { ptr, i32 } [ %11, %10 ], [ %15, %14 ]
  call void @llvm.lifetime.end.p0(i64 184, ptr nonnull %4) #6
  resume { ptr, i32 } %.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd9ConvParamC2EmPK25SimdConvolutionParameters26SimdSynetCompatibilityType(ptr noundef nonnull align 8 dereferenceable(180), i64 noundef, ptr noundef, i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN4Simd9ConvParam5ValidE18SimdTensorDataTypeS1_(ptr noundef nonnull align 8 dereferenceable(180), i32 noundef, i32 noundef) local_unnamed_addr #2 align 2

declare noundef zeroext i1 @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwise10PreferableERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(180)) local_unnamed_addr #3

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #4

declare void @_ZN4Simd4Base32SynetConvolution16bNhwcDepthwiseC1ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(368), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #3

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) local_unnamed_addr #5

declare void @_ZN4Simd4Base23SynetConvolution16bGemmC1ERKNS_9ConvParamE(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { builtin allocsize(0) }
attributes #8 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass