; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution32fDirectNchw)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"class.Simd::Base::SynetConvolution32fDirectNchw" = type { %"class.Simd::SynetConvolution32f", i64, i64, i64, i64, i64, i64, i64, i32, ptr }
%"class.Simd::SynetConvolution32f" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", float, float, ptr, ptr, ptr, %"struct.Simd::Runtime", %"struct.Simd::Runtime.3", %"struct.Simd::Array", ptr, ptr, ptr, %"class.std::__cxx11::basic_string" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%"struct.Simd::Runtime" = type { ptr, %"class.std::vector", %"class.std::__cxx11::basic_string" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Runtime.3" = type { ptr, %"class.std::vector.4", %"class.std::__cxx11::basic_string" }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

@_ZTVN4Simd4Base29SynetConvolution32fDirectNchwE = external dso_local unnamed_addr constant { [11 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fDirectNchwC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(512) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN4Simd19SynetConvolution32fC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(440) %7, ptr noundef nonnull align 8 dereferenceable(180) %8)
  store ptr getelementptr inbounds inrange(-16, 72) ({ [11 x ptr] }, ptr @_ZTVN4Simd4Base29SynetConvolution32fDirectNchwE, i32 0, i32 0, i32 2), ptr %7, align 8, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %9, i32 0, i32 0
  %11 = load i64, ptr %10, align 8, !tbaa !11
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %12, i32 0, i32 20
  %14 = load i64, ptr %13, align 8, !tbaa !17
  %15 = udiv i64 %11, %14
  %16 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 4
  store i64 %15, ptr %16, align 8, !tbaa !18
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %17, i32 0, i32 16
  %19 = load i64, ptr %18, align 8, !tbaa !40
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %20, i32 0, i32 1
  %22 = load i64, ptr %21, align 8, !tbaa !41
  %23 = add i64 %19, %22
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %24, i32 0, i32 18
  %26 = load i64, ptr %25, align 8, !tbaa !42
  %27 = add i64 %23, %26
  %28 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 5
  store i64 %27, ptr %28, align 8, !tbaa !43
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %29, i32 0, i32 17
  %31 = load i64, ptr %30, align 8, !tbaa !44
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %32, i32 0, i32 2
  %34 = load i64, ptr %33, align 8, !tbaa !45
  %35 = add i64 %31, %34
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %36, i32 0, i32 19
  %38 = load i64, ptr %37, align 8, !tbaa !46
  %39 = add i64 %35, %38
  %40 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 6
  store i64 %39, ptr %40, align 8, !tbaa !47
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %41, i32 0, i32 5
  %43 = load i64, ptr %42, align 8, !tbaa !48
  %44 = load ptr, ptr %4, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %44, i32 0, i32 20
  %46 = load i64, ptr %45, align 8, !tbaa !17
  %47 = udiv i64 %43, %46
  %48 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 7
  store i64 %47, ptr %48, align 8, !tbaa !49
  %49 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 4
  %50 = load i64, ptr %49, align 8, !tbaa !18
  %51 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 7
  %52 = load i64, ptr %51, align 8, !tbaa !49
  %53 = mul i64 %50, %52
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %54, i32 0, i32 10
  %56 = load i64, ptr %55, align 8, !tbaa !50
  %57 = mul i64 %53, %56
  %58 = load ptr, ptr %4, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %58, i32 0, i32 11
  %60 = load i64, ptr %59, align 8, !tbaa !51
  %61 = mul i64 %57, %60
  %62 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 1
  store i64 %61, ptr %62, align 8, !tbaa !52
  %63 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 4
  %64 = load i64, ptr %63, align 8, !tbaa !18
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %65, i32 0, i32 1
  %67 = load i64, ptr %66, align 8, !tbaa !41
  %68 = mul i64 %64, %67
  %69 = load ptr, ptr %4, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %69, i32 0, i32 2
  %71 = load i64, ptr %70, align 8, !tbaa !45
  %72 = mul i64 %68, %71
  %73 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 2
  store i64 %72, ptr %73, align 8, !tbaa !53
  %74 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 7
  %75 = load i64, ptr %74, align 8, !tbaa !49
  %76 = load ptr, ptr %4, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %76, i32 0, i32 6
  %78 = load i64, ptr %77, align 8, !tbaa !54
  %79 = mul i64 %75, %78
  %80 = load ptr, ptr %4, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %80, i32 0, i32 7
  %82 = load i64, ptr %81, align 8, !tbaa !55
  %83 = mul i64 %79, %82
  %84 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 3
  store i64 %83, ptr %84, align 8, !tbaa !56
  %85 = load ptr, ptr %4, align 8, !tbaa !5
  %86 = invoke noundef zeroext i1 @_ZNK4Simd9ConvParam5IsPadEm(ptr noundef nonnull align 8 dereferenceable(180) %85, i64 noundef 0)
          to label %87 unwind label %97

87:                                               ; preds = %2
  %88 = zext i1 %86 to i64
  %89 = select i1 %86, i32 0, i32 1
  %90 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 8
  store i32 %89, ptr %90, align 8, !tbaa !57
  %91 = load ptr, ptr %7, align 8, !tbaa !9
  %92 = getelementptr inbounds ptr, ptr %91, i64 8
  %93 = load ptr, ptr %92, align 8
  %94 = invoke noundef ptr %93(ptr noundef nonnull align 8 dereferenceable(512) %7)
          to label %95 unwind label %97

95:                                               ; preds = %87
  %96 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fDirectNchw", ptr %7, i32 0, i32 9
  store ptr %94, ptr %96, align 8, !tbaa !58
  ret void

97:                                               ; preds = %87, %2
  %98 = landingpad { ptr, i32 }
          cleanup
  %99 = extractvalue { ptr, i32 } %98, 0
  store ptr %99, ptr %5, align 8
  %100 = extractvalue { ptr, i32 } %98, 1
  store i32 %100, ptr %6, align 4
  call void @_ZN4Simd19SynetConvolution32fD2Ev(ptr noundef nonnull align 8 dereferenceable(440) %7) #3
  br label %101

101:                                              ; preds = %97
  %102 = load ptr, ptr %5, align 8
  %103 = load i32, ptr %6, align 4
  %104 = insertvalue { ptr, i32 } poison, ptr %102, 0
  %105 = insertvalue { ptr, i32 } %104, i32 %103, 1
  resume { ptr, i32 } %105
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd19SynetConvolution32fC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(440), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd9ConvParam5IsPadEm(ptr noundef nonnull align 8 dereferenceable(180), i64 noundef) #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd19SynetConvolution32fD2Ev(ptr noundef nonnull align 8 dereferenceable(440)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"_ZTS25SimdConvolutionParameters", !13, i64 0, !13, i64 8, !13, i64 16, !14, i64 24, !15, i64 28, !13, i64 32, !13, i64 40, !13, i64 48, !14, i64 56, !15, i64 60, !13, i64 64, !13, i64 72, !13, i64 80, !13, i64 88, !13, i64 96, !13, i64 104, !13, i64 112, !13, i64 120, !13, i64 128, !13, i64 136, !13, i64 144, !16, i64 152}
!13 = !{!"long", !7, i64 0}
!14 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!15 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!16 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!17 = !{!12, !13, i64 144}
!18 = !{!19, !13, i64 464}
!19 = !{!"_ZTSN4Simd4Base29SynetConvolution32fDirectNchwE", !20, i64 0, !13, i64 440, !13, i64 448, !13, i64 456, !13, i64 464, !13, i64 472, !13, i64 480, !13, i64 488, !39, i64 496, !6, i64 504}
!20 = !{!"_ZTSN4Simd19SynetConvolution32fE", !21, i64 0, !22, i64 8, !25, i64 192, !26, i64 208, !26, i64 212, !6, i64 216, !6, i64 224, !6, i64 232, !27, i64 240, !34, i64 304, !25, i64 368, !6, i64 384, !6, i64 392, !6, i64 400, !32, i64 408}
!21 = !{!"_ZTSN4Simd9DeletableE"}
!22 = !{!"_ZTSN4Simd9ConvParamE", !12, i64 0, !23, i64 160, !13, i64 168, !24, i64 176}
!23 = !{!"_ZTS8SimdBool", !7, i64 0}
!24 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!25 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !13, i64 8}
!26 = !{!"float", !7, i64 0}
!27 = !{!"_ZTSN4Simd7RuntimeINS_8GemmFuncENS_8GemmArgsEEE", !6, i64 0, !28, i64 8, !32, i64 32}
!28 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !33, i64 0, !13, i64 8, !7, i64 16}
!33 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!34 = !{!"_ZTSN4Simd7RuntimeINS_10GemmCbFuncENS_10GemmCbArgsEEE", !6, i64 0, !35, i64 8, !32, i64 32}
!35 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !36, i64 0}
!36 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE12_Vector_implE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!39 = !{!"int", !7, i64 0}
!40 = !{!12, !13, i64 112}
!41 = !{!12, !13, i64 8}
!42 = !{!12, !13, i64 128}
!43 = !{!19, !13, i64 472}
!44 = !{!12, !13, i64 120}
!45 = !{!12, !13, i64 16}
!46 = !{!12, !13, i64 136}
!47 = !{!19, !13, i64 480}
!48 = !{!12, !13, i64 32}
!49 = !{!19, !13, i64 488}
!50 = !{!12, !13, i64 64}
!51 = !{!12, !13, i64 72}
!52 = !{!19, !13, i64 440}
!53 = !{!19, !13, i64 448}
!54 = !{!12, !13, i64 40}
!55 = !{!12, !13, i64 48}
!56 = !{!19, !13, i64 456}
!57 = !{!19, !39, i64 496}
!58 = !{!19, !6, i64 504}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN4Simd4Base29SynetConvolution32fDirectNchwE = external dso_local unnamed_addr constant { [11 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fDirectNchwC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(512) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN4Simd19SynetConvolution32fC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(440) %0, ptr noundef nonnull align 8 dereferenceable(180) %1)
  store ptr getelementptr inbounds inrange(-16, 72) (i8, ptr @_ZTVN4Simd4Base29SynetConvolution32fDirectNchwE, i64 16), ptr %0, align 8, !tbaa !5
  %3 = load i64, ptr %1, align 8, !tbaa !8
  %4 = getelementptr inbounds i8, ptr %1, i64 144
  %5 = load i64, ptr %4, align 8, !tbaa !15
  %6 = udiv i64 %3, %5
  %7 = getelementptr inbounds i8, ptr %0, i64 464
  store i64 %6, ptr %7, align 8, !tbaa !16
  %8 = getelementptr inbounds i8, ptr %1, i64 112
  %9 = getelementptr inbounds i8, ptr %1, i64 8
  %10 = getelementptr inbounds i8, ptr %1, i64 128
  %11 = getelementptr inbounds i8, ptr %0, i64 472
  %12 = load <2 x i64>, ptr %8, align 8, !tbaa !39
  %13 = load <2 x i64>, ptr %9, align 8, !tbaa !39
  %14 = add <2 x i64> %13, %12
  %15 = load <2 x i64>, ptr %10, align 8, !tbaa !39
  %16 = add <2 x i64> %14, %15
  store <2 x i64> %16, ptr %11, align 8, !tbaa !39
  %17 = getelementptr inbounds i8, ptr %1, i64 32
  %18 = load i64, ptr %17, align 8, !tbaa !40
  %19 = udiv i64 %18, %5
  %20 = getelementptr inbounds i8, ptr %0, i64 488
  store i64 %19, ptr %20, align 8, !tbaa !41
  %21 = mul i64 %19, %6
  %22 = getelementptr inbounds i8, ptr %1, i64 64
  %23 = load i64, ptr %22, align 8, !tbaa !42
  %24 = mul i64 %21, %23
  %25 = getelementptr inbounds i8, ptr %1, i64 72
  %26 = load i64, ptr %25, align 8, !tbaa !43
  %27 = mul i64 %24, %26
  %28 = getelementptr inbounds i8, ptr %0, i64 440
  store i64 %27, ptr %28, align 8, !tbaa !44
  %29 = extractelement <2 x i64> %13, i64 0
  %30 = mul i64 %29, %6
  %31 = extractelement <2 x i64> %13, i64 1
  %32 = mul i64 %30, %31
  %33 = getelementptr inbounds i8, ptr %0, i64 448
  store i64 %32, ptr %33, align 8, !tbaa !45
  %34 = getelementptr inbounds i8, ptr %1, i64 40
  %35 = load i64, ptr %34, align 8, !tbaa !46
  %36 = mul i64 %35, %19
  %37 = getelementptr inbounds i8, ptr %1, i64 48
  %38 = load i64, ptr %37, align 8, !tbaa !47
  %39 = mul i64 %36, %38
  %40 = getelementptr inbounds i8, ptr %0, i64 456
  store i64 %39, ptr %40, align 8, !tbaa !48
  %41 = tail call noundef zeroext i1 @_ZNK4Simd9ConvParam5IsPadEm(ptr noundef nonnull align 8 dereferenceable(180) %1, i64 noundef 0)
  %not. = xor i1 %41, true
  %42 = zext i1 %not. to i32
  %43 = getelementptr inbounds i8, ptr %0, i64 496
  store i32 %42, ptr %43, align 8, !tbaa !49
  %44 = load ptr, ptr %0, align 8, !tbaa !5
  %45 = getelementptr inbounds i8, ptr %44, i64 64
  %46 = load ptr, ptr %45, align 8
  %47 = invoke noundef ptr %46(ptr noundef nonnull align 8 dereferenceable(512) %0)
          to label %48 unwind label %50

48:                                               ; preds = %2
  %49 = getelementptr inbounds i8, ptr %0, i64 504
  store ptr %47, ptr %49, align 8, !tbaa !50
  ret void

50:                                               ; preds = %2
  %51 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN4Simd19SynetConvolution32fD2Ev(ptr noundef nonnull align 8 dereferenceable(440) %0) #3
  resume { ptr, i32 } %51
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd19SynetConvolution32fC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(440), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd9ConvParam5IsPadEm(ptr noundef nonnull align 8 dereferenceable(180), i64 noundef) local_unnamed_addr #1 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd19SynetConvolution32fD2Ev(ptr noundef nonnull align 8 dereferenceable(440)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !10, i64 0}
!9 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !12, i64 24, !13, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !12, i64 56, !13, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !14, i64 152}
!10 = !{!"long", !11, i64 0}
!11 = !{!"omnipotent char", !7, i64 0}
!12 = !{!"_ZTS18SimdTensorDataType", !11, i64 0}
!13 = !{!"_ZTS20SimdTensorFormatType", !11, i64 0}
!14 = !{!"_ZTS29SimdConvolutionActivationType", !11, i64 0}
!15 = !{!9, !10, i64 144}
!16 = !{!17, !10, i64 464}
!17 = !{!"_ZTSN4Simd4Base29SynetConvolution32fDirectNchwE", !18, i64 0, !10, i64 440, !10, i64 448, !10, i64 456, !10, i64 464, !10, i64 472, !10, i64 480, !10, i64 488, !38, i64 496, !24, i64 504}
!18 = !{!"_ZTSN4Simd19SynetConvolution32fE", !19, i64 0, !20, i64 8, !23, i64 192, !25, i64 208, !25, i64 212, !24, i64 216, !24, i64 224, !24, i64 232, !26, i64 240, !33, i64 304, !23, i64 368, !24, i64 384, !24, i64 392, !24, i64 400, !31, i64 408}
!19 = !{!"_ZTSN4Simd9DeletableE"}
!20 = !{!"_ZTSN4Simd9ConvParamE", !9, i64 0, !21, i64 160, !10, i64 168, !22, i64 176}
!21 = !{!"_ZTS8SimdBool", !11, i64 0}
!22 = !{!"_ZTS26SimdSynetCompatibilityType", !11, i64 0}
!23 = !{!"_ZTSN4Simd5ArrayIfEE", !24, i64 0, !10, i64 8}
!24 = !{!"any pointer", !11, i64 0}
!25 = !{!"float", !11, i64 0}
!26 = !{!"_ZTSN4Simd7RuntimeINS_8GemmFuncENS_8GemmArgsEEE", !24, i64 0, !27, i64 8, !31, i64 32}
!27 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_8GemmFuncENS0_8GemmArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !24, i64 0, !24, i64 8, !24, i64 16}
!31 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !32, i64 0, !10, i64 8, !11, i64 16}
!32 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !24, i64 0}
!33 = !{!"_ZTSN4Simd7RuntimeINS_10GemmCbFuncENS_10GemmCbArgsEEE", !24, i64 0, !34, i64 8, !31, i64 32}
!34 = !{!"_ZTSSt6vectorIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIN4Simd7RuntimeINS0_10GemmCbFuncENS0_10GemmCbArgsEE9CandidateESaIS5_EE17_Vector_impl_dataE", !24, i64 0, !24, i64 8, !24, i64 16}
!38 = !{!"int", !11, i64 0}
!39 = !{!10, !10, i64 0}
!40 = !{!9, !10, i64 32}
!41 = !{!17, !10, i64 488}
!42 = !{!9, !10, i64 64}
!43 = !{!9, !10, i64 72}
!44 = !{!17, !10, i64 440}
!45 = !{!17, !10, i64 448}
!46 = !{!9, !10, i64 40}
!47 = !{!9, !10, i64 48}
!48 = !{!17, !10, i64 456}
!49 = !{!17, !38, i64 496}
!50 = !{!17, !24, i64 504}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass