; LLVM IR from Tudor67/Competitive-Programming :: Codeforces/#672#div2/C2/C2.ll (Z5eraseiRSt6vectorIiSaIiEEiRx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5eraseiRSt6vectorIiSaIiEEiRx(i32 noundef %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, ptr noundef nonnull align 8 dereferenceable(8) %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  store i32 %0, ptr %5, align 4, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !9
  %9 = load i32, ptr %5, align 4, !tbaa !5
  %10 = icmp sge i32 %9, 1
  br i1 %10, label %11, label %88

11:                                               ; preds = %4
  %12 = load i32, ptr %5, align 4, !tbaa !5
  %13 = load i32, ptr %7, align 4, !tbaa !5
  %14 = icmp sle i32 %12, %13
  br i1 %14, label %15, label %88

15:                                               ; preds = %11
  %16 = load ptr, ptr %6, align 8, !tbaa !9
  %17 = load i32, ptr %5, align 4, !tbaa !5
  %18 = sub nsw i32 %17, 1
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %19) #1
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = load ptr, ptr %6, align 8, !tbaa !9
  %23 = load i32, ptr %5, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %24) #1
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %27 = icmp slt i32 %21, %26
  br i1 %27, label %28, label %51

28:                                               ; preds = %15
  %29 = load ptr, ptr %6, align 8, !tbaa !9
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #1
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = load ptr, ptr %6, align 8, !tbaa !9
  %35 = load i32, ptr %5, align 4, !tbaa !5
  %36 = add nsw i32 %35, 1
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %37) #1
  %39 = load i32, ptr %38, align 4, !tbaa !5
  %40 = icmp sgt i32 %33, %39
  br i1 %40, label %41, label %51

41:                                               ; preds = %28
  %42 = load ptr, ptr %6, align 8, !tbaa !9
  %43 = load i32, ptr %5, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %44) #1
  %46 = load i32, ptr %45, align 4, !tbaa !5
  %47 = sext i32 %46 to i64
  %48 = load ptr, ptr %8, align 8, !tbaa !9
  %49 = load i64, ptr %48, align 8, !tbaa !11
  %50 = sub nsw i64 %49, %47
  store i64 %50, ptr %48, align 8, !tbaa !11
  br label %51

51:                                               ; preds = %41, %28, %15
  %52 = load ptr, ptr %6, align 8, !tbaa !9
  %53 = load i32, ptr %5, align 4, !tbaa !5
  %54 = sub nsw i32 %53, 1
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %55) #1
  %57 = load i32, ptr %56, align 4, !tbaa !5
  %58 = load ptr, ptr %6, align 8, !tbaa !9
  %59 = load i32, ptr %5, align 4, !tbaa !5
  %60 = sext i32 %59 to i64
  %61 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %58, i64 noundef %60) #1
  %62 = load i32, ptr %61, align 4, !tbaa !5
  %63 = icmp sgt i32 %57, %62
  br i1 %63, label %64, label %87

64:                                               ; preds = %51
  %65 = load ptr, ptr %6, align 8, !tbaa !9
  %66 = load i32, ptr %5, align 4, !tbaa !5
  %67 = sext i32 %66 to i64
  %68 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %65, i64 noundef %67) #1
  %69 = load i32, ptr %68, align 4, !tbaa !5
  %70 = load ptr, ptr %6, align 8, !tbaa !9
  %71 = load i32, ptr %5, align 4, !tbaa !5
  %72 = add nsw i32 %71, 1
  %73 = sext i32 %72 to i64
  %74 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %70, i64 noundef %73) #1
  %75 = load i32, ptr %74, align 4, !tbaa !5
  %76 = icmp slt i32 %69, %75
  br i1 %76, label %77, label %87

77:                                               ; preds = %64
  %78 = load ptr, ptr %6, align 8, !tbaa !9
  %79 = load i32, ptr %5, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %80) #1
  %82 = load i32, ptr %81, align 4, !tbaa !5
  %83 = sext i32 %82 to i64
  %84 = load ptr, ptr %8, align 8, !tbaa !9
  %85 = load i64, ptr %84, align 8, !tbaa !11
  %86 = add nsw i64 %85, %83
  store i64 %86, ptr %84, align 8, !tbaa !11
  br label %87

87:                                               ; preds = %77, %64, %51
  br label %88

88:                                               ; preds = %87, %11, %4
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5eraseiRSt6vectorIiSaIiEEiRx(i32 noundef %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, ptr nocapture noundef nonnull align 8 dereferenceable(8) %3) local_unnamed_addr #0 {
  %5 = icmp slt i32 %0, 1
  %.not = icmp sgt i32 %0, %2
  %or.cond = or i1 %5, %.not
  br i1 %or.cond, label %49, label %6

6:                                                ; preds = %4
  %7 = add nsw i32 %0, -1
  %8 = zext nneg i32 %7 to i64
  %9 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %8) #1
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %11 = zext nneg i32 %0 to i64
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = icmp slt i32 %10, %13
  br i1 %14, label %15, label %29

15:                                               ; preds = %6
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %17 = load i32, ptr %16, align 4, !tbaa !5
  %18 = add nuw nsw i32 %0, 1
  %19 = zext nneg i32 %18 to i64
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %19) #1
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = icmp sgt i32 %17, %21
  br i1 %22, label %23, label %29

23:                                               ; preds = %15
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = sext i32 %25 to i64
  %27 = load i64, ptr %3, align 8, !tbaa !9
  %28 = sub nsw i64 %27, %26
  store i64 %28, ptr %3, align 8, !tbaa !9
  br label %29

29:                                               ; preds = %23, %15, %6
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %8) #1
  %31 = load i32, ptr %30, align 4, !tbaa !5
  %32 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = icmp sgt i32 %31, %33
  br i1 %34, label %35, label %49

35:                                               ; preds = %29
  %36 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %37 = load i32, ptr %36, align 4, !tbaa !5
  %38 = add nuw nsw i32 %0, 1
  %39 = zext nneg i32 %38 to i64
  %40 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %39) #1
  %41 = load i32, ptr %40, align 4, !tbaa !5
  %42 = icmp slt i32 %37, %41
  br i1 %42, label %43, label %49

43:                                               ; preds = %35
  %44 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %11) #1
  %45 = load i32, ptr %44, align 4, !tbaa !5
  %46 = sext i32 %45 to i64
  %47 = load i64, ptr %3, align 8, !tbaa !9
  %48 = add nsw i64 %47, %46
  store i64 %48, ptr %3, align 8, !tbaa !9
  br label %49

49:                                               ; preds = %29, %35, %43, %4
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass