; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseDetection)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Rectangle" = type { i64, i64, i64, i64 }
%"struct.Simd::Detection::HidLbpCascade.119" = type { %"struct.Simd::Detection::HidBase", %"class.std::vector.120", %"class.std::vector.125", %"class.std::vector.72", %"class.std::vector.19", %"class.std::vector.19", %"class.std::vector.130", %"struct.Simd::View", %"struct.Simd::View" }
%"struct.Simd::Detection::HidBase" = type { %"struct.Simd::Deletable", i32, %"struct.Simd::Point", i8, i8, i8, i8, i32 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Point" = type { i64, i64 }
%"class.std::vector.120" = type { %"struct.std::_Vector_base.121" }
%"struct.std::_Vector_base.121" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Node, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Node>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Node, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Node>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Node, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Node>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Node, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Node>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.125" = type { %"struct.std::_Vector_base.126" }
%"struct.std::_Vector_base.126" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree, std::allocator<Simd::Detection::HidLbpCascade<int, unsigned short>::Tree>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.72" = type { %"struct.std::_Vector_base.73" }
%"struct.std::_Vector_base.73" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpStage<int>, std::allocator<Simd::Detection::HidLbpStage<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpStage<int>, std::allocator<Simd::Detection::HidLbpStage<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpStage<int>, std::allocator<Simd::Detection::HidLbpStage<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpStage<int>, std::allocator<Simd::Detection::HidLbpStage<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.130" = type { %"struct.std::_Vector_base.131" }
%"struct.std::_Vector_base.131" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpFeature<unsigned short>, std::allocator<Simd::Detection::HidLbpFeature<unsigned short>>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpFeature<unsigned short>, std::allocator<Simd::Detection::HidLbpFeature<unsigned short>>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::HidLbpFeature<unsigned short>, std::allocator<Simd::Detection::HidLbpFeature<unsigned short>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::HidLbpFeature<unsigned short>, std::allocator<Simd::Detection::HidLbpFeature<unsigned short>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::View" = type <{ i64, i64, i64, i32, [4 x i8], ptr, i8, [7 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) #1 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base22DetectionLbpDetect16ipERKNS_9Detection13HidLbpCascadeIitEERKNS_4ViewINS_9AllocatorEEERKNS_9RectangleIlEERS8_(ptr noundef nonnull align 8 dereferenceable(280) %0, ptr noundef nonnull align 8 dereferenceable(41) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef nonnull align 8 dereferenceable(41) %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %13 = load ptr, ptr %7, align 8, !tbaa !5
  %14 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %13, i32 0, i32 1
  %15 = load i64, ptr %14, align 8, !tbaa !9
  store i64 %15, ptr %9, align 8, !tbaa !12
  br label %16

16:                                               ; preds = %67, %4
  %17 = load i64, ptr %9, align 8, !tbaa !12
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  %19 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %18, i32 0, i32 3
  %20 = load i64, ptr %19, align 8, !tbaa !13
  %21 = icmp slt i64 %17, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %16
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  br label %70

23:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %24 = load i64, ptr %9, align 8, !tbaa !12
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %"struct.Simd::Detection::HidLbpCascade.119", ptr %25, i32 0, i32 8
  %27 = getelementptr inbounds %"struct.Simd::View", ptr %26, i32 0, i32 2
  %28 = load i64, ptr %27, align 8, !tbaa !14
  %29 = mul nsw i64 %24, %28
  %30 = udiv i64 %29, 2
  store i64 %30, ptr %11, align 8, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %31 = load ptr, ptr %7, align 8, !tbaa !5
  %32 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %31, i32 0, i32 0
  %33 = load i64, ptr %32, align 8, !tbaa !44
  store i64 %33, ptr %12, align 8, !tbaa !12
  br label %34

34:                                               ; preds = %63, %23
  %35 = load i64, ptr %12, align 8, !tbaa !12
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = getelementptr inbounds %"struct.Simd::Rectangle", ptr %36, i32 0, i32 2
  %38 = load i64, ptr %37, align 8, !tbaa !45
  %39 = icmp slt i64 %35, %38
  br i1 %39, label %41, label %40

40:                                               ; preds = %34
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  br label %66

41:                                               ; preds = %34
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  %43 = load i64, ptr %12, align 8, !tbaa !12
  %44 = load i64, ptr %9, align 8, !tbaa !12
  %45 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41) %42, i64 noundef %43, i64 noundef %44)
  %46 = load i8, ptr %45, align 1, !tbaa !46
  %47 = zext i8 %46 to i32
  %48 = icmp eq i32 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %41
  br label %63

50:                                               ; preds = %41
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = load i64, ptr %11, align 8, !tbaa !12
  %53 = load i64, ptr %12, align 8, !tbaa !12
  %54 = add i64 %52, %53
  %55 = call noundef i32 @_ZN4Simd4Base6DetectIitEEiRKNS_9Detection13HidLbpCascadeIT_T0_EEmi(ptr noundef nonnull align 8 dereferenceable(280) %51, i64 noundef %54, i32 noundef 0)
  %56 = icmp sgt i32 %55, 0
  br i1 %56, label %57, label %62

57:                                               ; preds = %50
  %58 = load ptr, ptr %8, align 8, !tbaa !5
  %59 = load i64, ptr %12, align 8, !tbaa !12
  %60 = load i64, ptr %9, align 8, !tbaa !12
  %61 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41) %58, i64 noundef %59, i64 noundef %60)
  store i8 1, ptr %61, align 1, !tbaa !46
  br label %62

62:                                               ; preds = %57, %50
  br label %63

63:                                               ; preds = %62, %49
  %64 = load i64, ptr %12, align 8, !tbaa !12
  %65 = add nsw i64 %64, 1
  store i64 %65, ptr %12, align 8, !tbaa !12
  br label %34, !llvm.loop !47

66:                                               ; preds = %40
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  br label %67

67:                                               ; preds = %66
  %68 = load i64, ptr %9, align 8, !tbaa !12
  %69 = add nsw i64 %68, 1
  store i64 %69, ptr %9, align 8, !tbaa !12
  br label %16, !llvm.loop !49

70:                                               ; preds = %22
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd4Base6DetectIitEEiRKNS_9Detection13HidLbpCascadeIT_T0_EEmi(ptr noundef nonnull align 8 dereferenceable(280), i64 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 8}
!10 = !{!"_ZTSN4Simd9RectangleIlEE", !11, i64 0, !11, i64 8, !11, i64 16, !11, i64 24}
!11 = !{!"long", !7, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!10, !11, i64 24}
!14 = !{!15, !11, i64 248}
!15 = !{!"_ZTSN4Simd9Detection13HidLbpCascadeIitEE", !16, i64 0, !22, i64 40, !26, i64 64, !30, i64 88, !34, i64 112, !34, i64 136, !38, i64 160, !42, i64 184, !42, i64 232}
!16 = !{!"_ZTSN4Simd9Detection7HidBaseE", !17, i64 0, !18, i64 8, !19, i64 16, !20, i64 32, !20, i64 33, !20, i64 34, !20, i64 35, !21, i64 36}
!17 = !{!"_ZTSN4Simd9DeletableE"}
!18 = !{!"_ZTS22SimdDetectionInfoFlags", !7, i64 0}
!19 = !{!"_ZTSN4Simd5PointIlEE", !11, i64 0, !11, i64 8}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"int", !7, i64 0}
!22 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt6vectorIN4Simd9Detection11HidLbpStageIiEESaIS3_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIiSaIiEE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEEE", !11, i64 0, !11, i64 8, !11, i64 16, !43, i64 24, !6, i64 32, !20, i64 40}
!43 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEE6FormatE", !7, i64 0}
!44 = !{!10, !11, i64 0}
!45 = !{!10, !11, i64 16}
!46 = !{!7, !7, i64 0}
!47 = distinct !{!47, !48}
!48 = !{!"llvm.loop.mustprogress"}
!49 = distinct !{!49, !48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41), i64 noundef, i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base22DetectionLbpDetect16ipERKNS_9Detection13HidLbpCascadeIitEERKNS_4ViewINS_9AllocatorEEERKNS_9RectangleIlEERS8_(ptr noundef nonnull align 8 dereferenceable(280) %0, ptr noundef nonnull align 8 dereferenceable(41) %1, ptr nocapture noundef nonnull readonly align 8 dereferenceable(32) %2, ptr noundef nonnull align 8 dereferenceable(41) %3) local_unnamed_addr #1 {
  %5 = getelementptr inbounds i8, ptr %2, i64 8
  %6 = load i64, ptr %5, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %2, i64 24
  %8 = load i64, ptr %7, align 8, !tbaa !10
  %9 = icmp slt i64 %6, %8
  br i1 %9, label %.lr.ph22, label %._crit_edge23

.lr.ph22:                                         ; preds = %4
  %10 = getelementptr inbounds i8, ptr %0, i64 248
  %11 = getelementptr inbounds i8, ptr %2, i64 16
  %12 = load i64, ptr %2, align 8, !tbaa !11
  %13 = load i64, ptr %11, align 8, !tbaa !12
  %14 = icmp slt i64 %12, %13
  br i1 %14, label %.lr.ph22.split, label %._crit_edge23

._crit_edge23:                                    ; preds = %._crit_edge, %.lr.ph22, %4
  ret void

.lr.ph22.split:                                   ; preds = %.lr.ph22, %._crit_edge
  %15 = phi i64 [ %22, %._crit_edge ], [ %8, %.lr.ph22 ]
  %16 = phi i64 [ %23, %._crit_edge ], [ %13, %.lr.ph22 ]
  %.01820 = phi i64 [ %24, %._crit_edge ], [ %6, %.lr.ph22 ]
  %17 = load i64, ptr %10, align 8, !tbaa !13
  %18 = mul nsw i64 %17, %.01820
  %19 = lshr i64 %18, 1
  %20 = load i64, ptr %2, align 8, !tbaa !11
  %21 = icmp slt i64 %20, %16
  br i1 %21, label %.lr.ph, label %._crit_edge

._crit_edge.loopexit:                             ; preds = %35
  %.pre = load i64, ptr %7, align 8, !tbaa !10
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.lr.ph22.split
  %22 = phi i64 [ %.pre, %._crit_edge.loopexit ], [ %15, %.lr.ph22.split ]
  %23 = phi i64 [ %37, %._crit_edge.loopexit ], [ %16, %.lr.ph22.split ]
  %24 = add nsw i64 %.01820, 1
  %25 = icmp slt i64 %24, %22
  br i1 %25, label %.lr.ph22.split, label %._crit_edge23, !llvm.loop !44

.lr.ph:                                           ; preds = %.lr.ph22.split, %35
  %.019 = phi i64 [ %36, %35 ], [ %20, %.lr.ph22.split ]
  %26 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNK4Simd4ViewINS_9AllocatorEE2AtIhEERKT_mm(ptr noundef nonnull align 8 dereferenceable(41) %1, i64 noundef %.019, i64 noundef %.01820)
  %27 = load i8, ptr %26, align 1, !tbaa !47
  %28 = icmp eq i8 %27, 0
  br i1 %28, label %35, label %29

29:                                               ; preds = %.lr.ph
  %30 = add i64 %.019, %19
  %31 = tail call noundef i32 @_ZN4Simd4Base6DetectIitEEiRKNS_9Detection13HidLbpCascadeIT_T0_EEmi(ptr noundef nonnull align 8 dereferenceable(280) %0, i64 noundef %30, i32 noundef 0)
  %32 = icmp sgt i32 %31, 0
  br i1 %32, label %33, label %35

33:                                               ; preds = %29
  %34 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZN4Simd4ViewINS_9AllocatorEE2AtIhEERT_mm(ptr noundef nonnull align 8 dereferenceable(41) %3, i64 noundef %.019, i64 noundef %.01820)
  store i8 1, ptr %34, align 1, !tbaa !47
  br label %35

35:                                               ; preds = %29, %33, %.lr.ph
  %36 = add nsw i64 %.019, 1
  %37 = load i64, ptr %11, align 8, !tbaa !12
  %38 = icmp slt i64 %36, %37
  br i1 %38, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !48
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd4Base6DetectIitEEiRKNS_9Detection13HidLbpCascadeIT_T0_EEmi(ptr noundef nonnull align 8 dereferenceable(280), i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTSN4Simd9RectangleIlEE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!6, !7, i64 24}
!11 = !{!6, !7, i64 0}
!12 = !{!6, !7, i64 16}
!13 = !{!14, !7, i64 248}
!14 = !{!"_ZTSN4Simd9Detection13HidLbpCascadeIitEE", !15, i64 0, !21, i64 40, !26, i64 64, !30, i64 88, !34, i64 112, !34, i64 136, !38, i64 160, !42, i64 184, !42, i64 232}
!15 = !{!"_ZTSN4Simd9Detection7HidBaseE", !16, i64 0, !17, i64 8, !18, i64 16, !19, i64 32, !19, i64 33, !19, i64 34, !19, i64 35, !20, i64 36}
!16 = !{!"_ZTSN4Simd9DeletableE"}
!17 = !{!"_ZTS22SimdDetectionInfoFlags", !8, i64 0}
!18 = !{!"_ZTSN4Simd5PointIlEE", !7, i64 0, !7, i64 8}
!19 = !{!"bool", !8, i64 0}
!20 = !{!"int", !8, i64 0}
!21 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4NodeESaIS4_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!25 = !{!"any pointer", !8, i64 0}
!26 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpCascadeIitE4TreeESaIS4_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!30 = !{!"_ZTSSt6vectorIN4Simd9Detection11HidLbpStageIiEESaIS3_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection11HidLbpStageIiEESaIS3_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!34 = !{!"_ZTSSt6vectorIiSaIiEE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!38 = !{!"_ZTSSt6vectorIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIN4Simd9Detection13HidLbpFeatureItEESaIS3_EE17_Vector_impl_dataE", !25, i64 0, !25, i64 8, !25, i64 16}
!42 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEEE", !7, i64 0, !7, i64 8, !7, i64 16, !43, i64 24, !25, i64 32, !19, i64 40}
!43 = !{!"_ZTSN4Simd4ViewINS_9AllocatorEE6FormatE", !8, i64 0}
!44 = distinct !{!44, !45, !46}
!45 = !{!"llvm.loop.mustprogress"}
!46 = !{!"llvm.loop.unswitch.partial.disable"}
!47 = !{!8, !8, i64 0}
!48 = distinct !{!48, !45}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass