; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution32fNhwcDirect)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::SynetConvolution32f" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", float, float, ptr, ptr, ptr, %"struct.Simd::Runtime", %"struct.Simd::Runtime.3", %"struct.Simd::Array", ptr, ptr, ptr, %"class.std::__cxx11::basic_string" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Runtime" = type { ptr, %"class.std::vector", %"class.std::__cxx11::basic_string" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmFunc, Simd::GemmArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Runtime.3" = type { ptr, %"class.std::vector.4", %"class.std::__cxx11::basic_string" }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate, std::allocator<Simd::Runtime<Simd::GemmCbFunc, Simd::GemmCbArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.Simd::Base::SynetConvolution32fNhwcDirect" = type { %"class.Simd::SynetConvolution32f", i64, i64, %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Array", %"struct.Simd::Runtime.9", %"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" }
%"struct.Simd::Runtime.9" = type { ptr, %"class.std::vector.10", %"class.std::__cxx11::basic_string" }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate, std::allocator<Simd::Runtime<Simd::Base::SynetConvolution32fNhwcDirect::RunFunc, Simd::Base::SynetConvolution32fNhwcDirect::RunArgs>::Candidate>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::Old" = type { i8, ptr, %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", %"struct.Simd::Array" }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam" = type { i64, i64, i64, i64, i64, [2 x ptr], i64 }
%"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunFunc" = type { %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", %"class.std::__cxx11::basic_string" }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect13ReorderWeightEPKfPf(ptr noundef nonnull align 8 dereferenceable(664) %0, ptr noundef %1, ptr noundef %2) #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  %18 = getelementptr inbounds %"class.Simd::SynetConvolution32f", ptr %17, i32 0, i32 1
  store ptr %18, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  %19 = getelementptr inbounds %"class.Simd::Base::SynetConvolution32fNhwcDirect", ptr %17, i32 0, i32 6
  %20 = call noundef nonnull align 8 dereferenceable(96) ptr @_ZNK4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE2AtEm(ptr noundef nonnull align 8 dereferenceable(64) %19, i64 noundef 0)
  %21 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::RunFunc", ptr %20, i32 0, i32 0
  store ptr %21, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  store i64 0, ptr %9, align 8, !tbaa !9
  br label %22

22:                                               ; preds = %114, %3
  %23 = load i64, ptr %9, align 8, !tbaa !9
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %24, i32 0, i32 5
  %26 = load i64, ptr %25, align 8, !tbaa !11
  %27 = icmp ult i64 %23, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %22
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  br label %120

29:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %30, i32 0, i32 5
  %32 = load i64, ptr %31, align 8, !tbaa !11
  %33 = load i64, ptr %9, align 8, !tbaa !9
  %34 = load ptr, ptr %8, align 8, !tbaa !5
  %35 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %34, i32 0, i32 0
  %36 = load i64, ptr %35, align 8, !tbaa !16
  %37 = add i64 %33, %36
  %38 = call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %32, i64 noundef %37)
  %39 = load i64, ptr %9, align 8, !tbaa !9
  %40 = sub i64 %38, %39
  store i64 %40, ptr %11, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #3
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %41, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  store i64 0, ptr %13, align 8, !tbaa !9
  br label %42

42:                                               ; preds = %107, %29
  %43 = load i64, ptr %13, align 8, !tbaa !9
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %44, i32 0, i32 10
  %46 = load i64, ptr %45, align 8, !tbaa !18
  %47 = icmp ult i64 %43, %46
  br i1 %47, label %49, label %48

48:                                               ; preds = %42
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  br label %110

49:                                               ; preds = %42
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  store i64 0, ptr %14, align 8, !tbaa !9
  br label %50

50:                                               ; preds = %103, %49
  %51 = load i64, ptr %14, align 8, !tbaa !9
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %52, i32 0, i32 11
  %54 = load i64, ptr %53, align 8, !tbaa !19
  %55 = icmp ult i64 %51, %54
  br i1 %55, label %57, label %56

56:                                               ; preds = %50
  store i32 8, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  br label %106

57:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  store i64 0, ptr %15, align 8, !tbaa !9
  br label %58

58:                                               ; preds = %99, %57
  %59 = load i64, ptr %15, align 8, !tbaa !9
  %60 = load ptr, ptr %7, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %60, i32 0, i32 0
  %62 = load i64, ptr %61, align 8, !tbaa !20
  %63 = icmp ult i64 %59, %62
  br i1 %63, label %65, label %64

64:                                               ; preds = %58
  store i32 11, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  br label %102

65:                                               ; preds = %58
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #3
  store i64 0, ptr %16, align 8, !tbaa !9
  br label %66

66:                                               ; preds = %77, %65
  %67 = load i64, ptr %16, align 8, !tbaa !9
  %68 = load i64, ptr %11, align 8, !tbaa !9
  %69 = icmp ult i64 %67, %68
  br i1 %69, label %70, label %80

70:                                               ; preds = %66
  %71 = load ptr, ptr %12, align 8, !tbaa !5
  %72 = load i64, ptr %16, align 8, !tbaa !9
  %73 = getelementptr inbounds float, ptr %71, i64 %72
  %74 = load float, ptr %73, align 4, !tbaa !21
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = getelementptr inbounds float, ptr %75, i32 1
  store ptr %76, ptr %6, align 8, !tbaa !5
  store float %74, ptr %75, align 4, !tbaa !21
  br label %77

77:                                               ; preds = %70
  %78 = load i64, ptr %16, align 8, !tbaa !9
  %79 = add i64 %78, 1
  store i64 %79, ptr %16, align 8, !tbaa !9
  br label %66, !llvm.loop !23

80:                                               ; preds = %66
  br label %81

81:                                               ; preds = %90, %80
  %82 = load i64, ptr %16, align 8, !tbaa !9
  %83 = load ptr, ptr %8, align 8, !tbaa !5
  %84 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %83, i32 0, i32 0
  %85 = load i64, ptr %84, align 8, !tbaa !16
  %86 = icmp ult i64 %82, %85
  br i1 %86, label %87, label %93

87:                                               ; preds = %81
  %88 = load ptr, ptr %6, align 8, !tbaa !5
  %89 = getelementptr inbounds float, ptr %88, i32 1
  store ptr %89, ptr %6, align 8, !tbaa !5
  store float 0.000000e+00, ptr %88, align 4, !tbaa !21
  br label %90

90:                                               ; preds = %87
  %91 = load i64, ptr %16, align 8, !tbaa !9
  %92 = add i64 %91, 1
  store i64 %92, ptr %16, align 8, !tbaa !9
  br label %81, !llvm.loop !25

93:                                               ; preds = %81
  %94 = load ptr, ptr %7, align 8, !tbaa !5
  %95 = getelementptr inbounds %struct.SimdConvolutionParameters, ptr %94, i32 0, i32 5
  %96 = load i64, ptr %95, align 8, !tbaa !11
  %97 = load ptr, ptr %12, align 8, !tbaa !5
  %98 = getelementptr inbounds float, ptr %97, i64 %96
  store ptr %98, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #3
  br label %99

99:                                               ; preds = %93
  %100 = load i64, ptr %15, align 8, !tbaa !9
  %101 = add i64 %100, 1
  store i64 %101, ptr %15, align 8, !tbaa !9
  br label %58, !llvm.loop !26

102:                                              ; preds = %64
  br label %103

103:                                              ; preds = %102
  %104 = load i64, ptr %14, align 8, !tbaa !9
  %105 = add i64 %104, 1
  store i64 %105, ptr %14, align 8, !tbaa !9
  br label %50, !llvm.loop !27

106:                                              ; preds = %56
  br label %107

107:                                              ; preds = %106
  %108 = load i64, ptr %13, align 8, !tbaa !9
  %109 = add i64 %108, 1
  store i64 %109, ptr %13, align 8, !tbaa !9
  br label %42, !llvm.loop !28

110:                                              ; preds = %48
  %111 = load i64, ptr %11, align 8, !tbaa !9
  %112 = load ptr, ptr %5, align 8, !tbaa !5
  %113 = getelementptr inbounds float, ptr %112, i64 %111
  store ptr %113, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  br label %114

114:                                              ; preds = %110
  %115 = load ptr, ptr %8, align 8, !tbaa !5
  %116 = getelementptr inbounds %"struct.Simd::Base::SynetConvolution32fNhwcDirect::AlgParam", ptr %115, i32 0, i32 0
  %117 = load i64, ptr %116, align 8, !tbaa !16
  %118 = load i64, ptr %9, align 8, !tbaa !9
  %119 = add i64 %118, %117
  store i64 %119, ptr %9, align 8, !tbaa !9
  br label %22, !llvm.loop !29

120:                                              ; preds = %28
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret void
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(96) ptr @_ZNK4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE2AtEm(ptr noundef nonnull align 8 dereferenceable(64), i64 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 32}
!12 = !{!"_ZTS25SimdConvolutionParameters", !10, i64 0, !10, i64 8, !10, i64 16, !13, i64 24, !14, i64 28, !10, i64 32, !10, i64 40, !10, i64 48, !13, i64 56, !14, i64 60, !10, i64 64, !10, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !10, i64 144, !15, i64 152}
!13 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!14 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!15 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!16 = !{!17, !10, i64 0}
!17 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !7, i64 40, !10, i64 56}
!18 = !{!12, !10, i64 64}
!19 = !{!12, !10, i64 72}
!20 = !{!12, !10, i64 0}
!21 = !{!22, !22, i64 0}
!22 = !{!"float", !7, i64 0}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}
!25 = distinct !{!25, !24}
!26 = distinct !{!26, !24}
!27 = distinct !{!27, !24}
!28 = distinct !{!28, !24}
!29 = distinct !{!29, !24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution32fNhwcDirect13ReorderWeightEPKfPf(ptr noundef nonnull align 8 dereferenceable(664) %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = getelementptr inbounds i8, ptr %0, i64 504
  %6 = tail call noundef nonnull align 8 dereferenceable(96) ptr @_ZNK4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE2AtEm(ptr noundef nonnull align 8 dereferenceable(64) %5, i64 noundef 0)
  %7 = getelementptr inbounds i8, ptr %0, i64 40
  %8 = load i64, ptr %7, align 8, !tbaa !5
  %.not = icmp eq i64 %8, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 72
  %10 = getelementptr inbounds i8, ptr %0, i64 80
  %.pre = load i64, ptr %6, align 8, !tbaa !13
  br label %11

._crit_edge:                                      ; preds = %._crit_edge101, %3
  ret void

11:                                               ; preds = %.lr.ph, %._crit_edge101
  %12 = phi i64 [ %.pre, %.lr.ph ], [ %61, %._crit_edge101 ]
  %13 = phi i64 [ %8, %.lr.ph ], [ %63, %._crit_edge101 ]
  %.037118 = phi ptr [ %1, %.lr.ph ], [ %60, %._crit_edge101 ]
  %.038117 = phi i64 [ 0, %.lr.ph ], [ %62, %._crit_edge101 ]
  %.039116 = phi ptr [ %2, %.lr.ph ], [ %.140.lcssa, %._crit_edge101 ]
  %14 = add i64 %12, %.038117
  %15 = tail call noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef %13, i64 noundef %14)
  %16 = sub i64 %15, %.038117
  %17 = load i64, ptr %9, align 8, !tbaa !15
  %.not122 = icmp eq i64 %17, 0
  br i1 %.not122, label %._crit_edge101, label %.preheader45.lr.ph

.preheader45.lr.ph:                               ; preds = %11
  %18 = load i64, ptr %10, align 8, !tbaa !16
  %.not123 = icmp eq i64 %18, 0
  %19 = load i64, ptr %4, align 8
  %.not124 = icmp eq i64 %19, 0
  %or.cond = select i1 %.not123, i1 true, i1 %.not124
  br i1 %or.cond, label %._crit_edge101, label %.preheader45.lr.ph.split.us.split.us

.preheader45.lr.ph.split.us.split.us:             ; preds = %.preheader45.lr.ph
  %.not125 = icmp eq i64 %15, %.038117
  br i1 %.not125, label %.preheader45.us.us.preheader, label %.preheader45.us.us.us.preheader

.preheader45.us.us.us.preheader:                  ; preds = %.preheader45.lr.ph.split.us.split.us
  %20 = sub i64 %.038117, %15
  %21 = add i64 %15, 1
  %22 = sub i64 %21, %.038117
  %min.iters.check = icmp ult i64 %16, 8
  %n.vec = and i64 %16, -8
  %23 = shl i64 %n.vec, 2
  %cmp.n = icmp eq i64 %16, %n.vec
  br label %.preheader45.us.us.us

.preheader45.us.us.preheader:                     ; preds = %.preheader45.lr.ph.split.us.split.us
  %24 = shl i64 %19, 2
  %25 = mul i64 %24, %18
  %26 = shl i64 %18, 2
  %27 = mul i64 %26, %19
  %xtraiter = and i64 %17, 1
  %28 = icmp eq i64 %17, 1
  br i1 %28, label %._crit_edge101.loopexit.unr-lcssa, label %.preheader45.us.us.preheader.new

.preheader45.us.us.preheader.new:                 ; preds = %.preheader45.us.us.preheader
  %unroll_iter = and i64 %17, -2
  br label %.preheader45.us.us

.preheader45.us.us.us:                            ; preds = %.preheader45.us.us.us.preheader, %._crit_edge.split.us.split.us.us.us.us
  %.034100.us.us.us = phi i64 [ %50, %._crit_edge.split.us.split.us.us.us.us ], [ 0, %.preheader45.us.us.us.preheader ]
  %.03599.us.us.us = phi ptr [ %43, %._crit_edge.split.us.split.us.us.us.us ], [ %.037118, %.preheader45.us.us.us.preheader ]
  %.14098.us.us.us = phi ptr [ %.5.lcssa.us.us.us.us.us.us, %._crit_edge.split.us.split.us.us.us.us ], [ %.039116, %.preheader45.us.us.us.preheader ]
  %29 = load i64, ptr %6, align 8
  %30 = load i64, ptr %7, align 8
  %umax = tail call i64 @llvm.umax.i64(i64 %29, i64 %22)
  %31 = add i64 %20, %umax
  %32 = shl nuw i64 %31, 2
  %33 = shl i64 %umax, 2
  %34 = icmp ult i64 %16, %29
  %35 = mul i64 %30, -4
  br label %.preheader44.us.us.us.us.us

.preheader44.us.us.us.us.us:                      ; preds = %._crit_edge56.split.us.us.us.us.us.us, %.preheader45.us.us.us
  %.03376.us.us.us.us.us = phi i64 [ 0, %.preheader45.us.us.us ], [ %49, %._crit_edge56.split.us.us.us.us.us.us ]
  %.13675.us.us.us.us.us = phi ptr [ %.03599.us.us.us, %.preheader45.us.us.us ], [ %43, %._crit_edge56.split.us.us.us.us.us.us ]
  %.24174.us.us.us.us.us = phi ptr [ %.14098.us.us.us, %.preheader45.us.us.us ], [ %.5.lcssa.us.us.us.us.us.us, %._crit_edge56.split.us.us.us.us.us.us ]
  %.13675.us.us.us.us.us154 = ptrtoint ptr %.13675.us.us.us.us.us to i64
  br label %.preheader43.us.us.us.us.us.us

.preheader43.us.us.us.us.us.us:                   ; preds = %._crit_edge.us.us.us.us.us.us, %.preheader44.us.us.us.us.us
  %.03255.us.us.us.us.us.us = phi i64 [ 0, %.preheader44.us.us.us.us.us ], [ %44, %._crit_edge.us.us.us.us.us.us ]
  %.254.us.us.us.us.us.us = phi ptr [ %.13675.us.us.us.us.us, %.preheader44.us.us.us.us.us ], [ %43, %._crit_edge.us.us.us.us.us.us ]
  %.353.us.us.us.us.us.us = phi ptr [ %.24174.us.us.us.us.us, %.preheader44.us.us.us.us.us ], [ %.5.lcssa.us.us.us.us.us.us, %._crit_edge.us.us.us.us.us.us ]
  br i1 %min.iters.check, label %scalar.ph.preheader, label %vector.memcheck

scalar.ph.preheader:                              ; preds = %middle.block, %vector.memcheck, %.preheader43.us.us.us.us.us.us
  %.047.us.us.us.us.us.us.ph = phi i64 [ 0, %vector.memcheck ], [ 0, %.preheader43.us.us.us.us.us.us ], [ %n.vec, %middle.block ]
  %.446.us.us.us.us.us.us.ph = phi ptr [ %.353.us.us.us.us.us.us, %vector.memcheck ], [ %.353.us.us.us.us.us.us, %.preheader43.us.us.us.us.us.us ], [ %ind.end, %middle.block ]
  br label %scalar.ph

vector.memcheck:                                  ; preds = %.preheader43.us.us.us.us.us.us
  %36 = mul i64 %35, %.03255.us.us.us.us.us.us
  %37 = sub i64 %36, %.13675.us.us.us.us.us154
  %.353.us.us.us.us.us.us153 = ptrtoint ptr %.353.us.us.us.us.us.us to i64
  %38 = add i64 %37, %.353.us.us.us.us.us.us153
  %diff.check = icmp ult i64 %38, 32
  br i1 %diff.check, label %scalar.ph.preheader, label %vector.ph

vector.ph:                                        ; preds = %vector.memcheck
  %ind.end = getelementptr i8, ptr %.353.us.us.us.us.us.us, i64 %23
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %offset.idx = shl i64 %index, 2
  %next.gep = getelementptr i8, ptr %.353.us.us.us.us.us.us, i64 %offset.idx
  %39 = getelementptr inbounds float, ptr %.254.us.us.us.us.us.us, i64 %index
  %40 = getelementptr inbounds i8, ptr %39, i64 16
  %wide.load = load <4 x float>, ptr %39, align 4, !tbaa !17
  %wide.load157 = load <4 x float>, ptr %40, align 4, !tbaa !17
  %41 = getelementptr i8, ptr %next.gep, i64 16
  store <4 x float> %wide.load, ptr %next.gep, align 4, !tbaa !17
  store <4 x float> %wide.load157, ptr %41, align 4, !tbaa !17
  %index.next = add nuw i64 %index, 8
  %42 = icmp eq i64 %index.next, %n.vec
  br i1 %42, label %middle.block, label %vector.body, !llvm.loop !19

middle.block:                                     ; preds = %vector.body
  br i1 %cmp.n, label %..preheader_crit_edge.us.us.us.us.us.us, label %scalar.ph.preheader

._crit_edge.us.us.us.us.us.us:                    ; preds = %.lr.ph51.us.us.us.us.us.us.preheader, %..preheader_crit_edge.us.us.us.us.us.us
  %.5.lcssa.us.us.us.us.us.us = phi ptr [ %.lcssa, %..preheader_crit_edge.us.us.us.us.us.us ], [ %scevgep, %.lr.ph51.us.us.us.us.us.us.preheader ]
  %43 = getelementptr inbounds float, ptr %.254.us.us.us.us.us.us, i64 %30
  %44 = add nuw i64 %.03255.us.us.us.us.us.us, 1
  %exitcond138.not = icmp eq i64 %44, %19
  br i1 %exitcond138.not, label %._crit_edge56.split.us.us.us.us.us.us, label %.preheader43.us.us.us.us.us.us, !llvm.loop !23

scalar.ph:                                        ; preds = %scalar.ph.preheader, %scalar.ph
  %.047.us.us.us.us.us.us = phi i64 [ %48, %scalar.ph ], [ %.047.us.us.us.us.us.us.ph, %scalar.ph.preheader ]
  %.446.us.us.us.us.us.us = phi ptr [ %47, %scalar.ph ], [ %.446.us.us.us.us.us.us.ph, %scalar.ph.preheader ]
  %45 = getelementptr inbounds float, ptr %.254.us.us.us.us.us.us, i64 %.047.us.us.us.us.us.us
  %46 = load float, ptr %45, align 4, !tbaa !17
  %47 = getelementptr i8, ptr %.446.us.us.us.us.us.us, i64 4
  store float %46, ptr %.446.us.us.us.us.us.us, align 4, !tbaa !17
  %48 = add nuw i64 %.047.us.us.us.us.us.us, 1
  %exitcond.not = icmp eq i64 %48, %16
  br i1 %exitcond.not, label %..preheader_crit_edge.us.us.us.us.us.us, label %scalar.ph, !llvm.loop !24

..preheader_crit_edge.us.us.us.us.us.us:          ; preds = %scalar.ph, %middle.block
  %.lcssa = phi ptr [ %ind.end, %middle.block ], [ %47, %scalar.ph ]
  br i1 %34, label %.lr.ph51.us.us.us.us.us.us.preheader, label %._crit_edge.us.us.us.us.us.us

.lr.ph51.us.us.us.us.us.us.preheader:             ; preds = %..preheader_crit_edge.us.us.us.us.us.us
  tail call void @llvm.memset.p0.i64(ptr align 4 %.lcssa, i8 0, i64 %32, i1 false), !tbaa !17
  %scevgep = getelementptr i8, ptr %.353.us.us.us.us.us.us, i64 %33
  br label %._crit_edge.us.us.us.us.us.us

._crit_edge56.split.us.us.us.us.us.us:            ; preds = %._crit_edge.us.us.us.us.us.us
  %49 = add nuw i64 %.03376.us.us.us.us.us, 1
  %exitcond139.not = icmp eq i64 %49, %18
  br i1 %exitcond139.not, label %._crit_edge.split.us.split.us.us.us.us, label %.preheader44.us.us.us.us.us, !llvm.loop !25

._crit_edge.split.us.split.us.us.us.us:           ; preds = %._crit_edge56.split.us.us.us.us.us.us
  %50 = add nuw i64 %.034100.us.us.us, 1
  %exitcond140.not = icmp eq i64 %50, %17
  br i1 %exitcond140.not, label %._crit_edge101, label %.preheader45.us.us.us, !llvm.loop !26

.preheader45.us.us:                               ; preds = %._crit_edge.split.us.split.us113.us.1, %.preheader45.us.us.preheader.new
  %.14098.us.us = phi ptr [ %.039116, %.preheader45.us.us.preheader.new ], [ %.us-phi96.us.us.1, %._crit_edge.split.us.split.us113.us.1 ]
  %niter = phi i64 [ 0, %.preheader45.us.us.preheader.new ], [ %niter.next.1, %._crit_edge.split.us.split.us113.us.1 ]
  %51 = load i64, ptr %6, align 8
  %.not126 = icmp eq i64 %51, 0
  br i1 %.not126, label %._crit_edge.split.us.split.us113.us, label %.preheader44.us.us90.us.us.preheader

.preheader44.us.us90.us.us.preheader:             ; preds = %.preheader45.us.us
  %52 = mul i64 %25, %51
  tail call void @llvm.memset.p0.i64(ptr align 4 %.14098.us.us, i8 0, i64 %52, i1 false), !tbaa !17
  %53 = mul i64 %27, %51
  %scevgep145 = getelementptr i8, ptr %.14098.us.us, i64 %53
  br label %._crit_edge.split.us.split.us113.us

._crit_edge.split.us.split.us113.us:              ; preds = %.preheader45.us.us, %.preheader44.us.us90.us.us.preheader
  %.us-phi96.us.us = phi ptr [ %scevgep145, %.preheader44.us.us90.us.us.preheader ], [ %.14098.us.us, %.preheader45.us.us ]
  %54 = load i64, ptr %6, align 8
  %.not126.1 = icmp eq i64 %54, 0
  br i1 %.not126.1, label %._crit_edge.split.us.split.us113.us.1, label %.preheader44.us.us90.us.us.preheader.1

.preheader44.us.us90.us.us.preheader.1:           ; preds = %._crit_edge.split.us.split.us113.us
  %55 = mul i64 %25, %54
  tail call void @llvm.memset.p0.i64(ptr align 4 %.us-phi96.us.us, i8 0, i64 %55, i1 false), !tbaa !17
  %56 = mul i64 %27, %54
  %scevgep145.1 = getelementptr i8, ptr %.us-phi96.us.us, i64 %56
  br label %._crit_edge.split.us.split.us113.us.1

._crit_edge.split.us.split.us113.us.1:            ; preds = %.preheader44.us.us90.us.us.preheader.1, %._crit_edge.split.us.split.us113.us
  %.us-phi96.us.us.1 = phi ptr [ %scevgep145.1, %.preheader44.us.us90.us.us.preheader.1 ], [ %.us-phi96.us.us, %._crit_edge.split.us.split.us113.us ]
  %niter.next.1 = add i64 %niter, 2
  %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
  br i1 %niter.ncmp.1, label %._crit_edge101.loopexit.unr-lcssa, label %.preheader45.us.us, !llvm.loop !26

._crit_edge101.loopexit.unr-lcssa:                ; preds = %._crit_edge.split.us.split.us113.us.1, %.preheader45.us.us.preheader
  %.us-phi96.us.us.lcssa.ph = phi ptr [ poison, %.preheader45.us.us.preheader ], [ %.us-phi96.us.us.1, %._crit_edge.split.us.split.us113.us.1 ]
  %.14098.us.us.unr = phi ptr [ %.039116, %.preheader45.us.us.preheader ], [ %.us-phi96.us.us.1, %._crit_edge.split.us.split.us113.us.1 ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %._crit_edge101, label %.preheader45.us.us.epil

.preheader45.us.us.epil:                          ; preds = %._crit_edge101.loopexit.unr-lcssa
  %57 = load i64, ptr %6, align 8
  %.not126.epil = icmp eq i64 %57, 0
  br i1 %.not126.epil, label %._crit_edge101, label %.preheader44.us.us90.us.us.preheader.epil

.preheader44.us.us90.us.us.preheader.epil:        ; preds = %.preheader45.us.us.epil
  %58 = mul i64 %25, %57
  tail call void @llvm.memset.p0.i64(ptr align 4 %.14098.us.us.unr, i8 0, i64 %58, i1 false), !tbaa !17
  %59 = mul i64 %27, %57
  %scevgep145.epil = getelementptr i8, ptr %.14098.us.us.unr, i64 %59
  br label %._crit_edge101

._crit_edge101:                                   ; preds = %._crit_edge.split.us.split.us.us.us.us, %._crit_edge101.loopexit.unr-lcssa, %.preheader44.us.us90.us.us.preheader.epil, %.preheader45.us.us.epil, %.preheader45.lr.ph, %11
  %.140.lcssa = phi ptr [ %.039116, %11 ], [ %.039116, %.preheader45.lr.ph ], [ %.us-phi96.us.us.lcssa.ph, %._crit_edge101.loopexit.unr-lcssa ], [ %scevgep145.epil, %.preheader44.us.us90.us.us.preheader.epil ], [ %.14098.us.us.unr, %.preheader45.us.us.epil ], [ %.5.lcssa.us.us.us.us.us.us, %._crit_edge.split.us.split.us.us.us.us ]
  %60 = getelementptr inbounds float, ptr %.037118, i64 %16
  %61 = load i64, ptr %6, align 8, !tbaa !13
  %62 = add i64 %61, %.038117
  %63 = load i64, ptr %7, align 8, !tbaa !5
  %64 = icmp ult i64 %62, %63
  br i1 %64, label %11, label %._crit_edge, !llvm.loop !27
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZN4Simd3MinImEET_S1_S1_(i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(96) ptr @_ZNK4Simd7RuntimeINS_4Base29SynetConvolution32fNhwcDirect7RunFuncENS2_7RunArgsEE2AtEm(ptr noundef nonnull align 8 dereferenceable(64), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.umax.i64(i64, i64) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 32}
!6 = !{!"_ZTS25SimdConvolutionParameters", !7, i64 0, !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !7, i64 32, !7, i64 40, !7, i64 48, !10, i64 56, !11, i64 60, !7, i64 64, !7, i64 72, !7, i64 80, !7, i64 88, !7, i64 96, !7, i64 104, !7, i64 112, !7, i64 120, !7, i64 128, !7, i64 136, !7, i64 144, !12, i64 152}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS18SimdTensorDataType", !8, i64 0}
!11 = !{!"_ZTS20SimdTensorFormatType", !8, i64 0}
!12 = !{!"_ZTS29SimdConvolutionActivationType", !8, i64 0}
!13 = !{!14, !7, i64 0}
!14 = !{!"_ZTSN4Simd4Base29SynetConvolution32fNhwcDirect8AlgParamE", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !8, i64 40, !7, i64 56}
!15 = !{!6, !7, i64 64}
!16 = !{!6, !7, i64 72}
!17 = !{!18, !18, i64 0}
!18 = !{!"float", !8, i64 0}
!19 = distinct !{!19, !20, !21, !22}
!20 = !{!"llvm.loop.mustprogress"}
!21 = !{!"llvm.loop.isvectorized", i32 1}
!22 = !{!"llvm.loop.unroll.runtime.disable"}
!23 = distinct !{!23, !20}
!24 = distinct !{!24, !20, !21}
!25 = distinct !{!25, !20}
!26 = distinct !{!26, !20}
!27 = distinct !{!27, !20}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopIdiomRecognizePass,LoopInstSimplifyPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass