; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c = external hidden unnamed_addr constant [24 x i32], align 16
@__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_instr_zip = external hidden unnamed_addr constant [2 x i32], align 4

declare void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_2dregblock_mmla_aarch64_asimd(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9, i32 noundef %10, i8 noundef zeroext %11) #2 {
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca ptr, align 8
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca i8, align 1
  %25 = alloca i32, align 4
  %26 = alloca [2 x i32], align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca i32, align 4
  %30 = alloca [2 x i32], align 4
  %31 = alloca i32, align 4
  %32 = alloca [24 x i32], align 16
  %33 = alloca [2 x i32], align 4
  %34 = alloca i32, align 4
  store ptr %0, ptr %13, align 8, !tbaa !5
  store ptr %1, ptr %14, align 8, !tbaa !5
  store ptr %2, ptr %15, align 8, !tbaa !5
  store i32 %3, ptr %16, align 4, !tbaa !9
  store i32 %4, ptr %17, align 4, !tbaa !9
  store i32 %5, ptr %18, align 4, !tbaa !9
  store i32 %6, ptr %19, align 4, !tbaa !9
  store i32 %7, ptr %20, align 4, !tbaa !9
  store i32 %8, ptr %21, align 4, !tbaa !9
  store i32 %9, ptr %22, align 4, !tbaa !9
  store i32 %10, ptr %23, align 4, !tbaa !9
  store i8 %11, ptr %24, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %26) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %27) #4
  store i32 0, ptr %27, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %28) #4
  %35 = load i32, ptr %21, align 4, !tbaa !9
  %36 = udiv i32 %35, 2
  store i32 %36, ptr %28, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %29) #4
  store i32 0, ptr %29, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %30) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %31) #4
  store i32 0, ptr %31, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 96, ptr %32) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %32, ptr align 16 @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 96, i1 false)
  call void @llvm.lifetime.start.p0(i64 8, ptr %33) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %33, ptr align 4 @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_instr_zip, i64 8, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %34) #4
  store i32 7, ptr %34, align 4, !tbaa !9
  %37 = load ptr, ptr %14, align 8, !tbaa !5
  %38 = load ptr, ptr %15, align 8, !tbaa !5
  %39 = load i32, ptr %19, align 4, !tbaa !9
  %40 = load i8, ptr %24, align 1, !tbaa !11
  %41 = icmp ne i8 %40, 0
  br i1 %41, label %42, label %45

42:                                               ; preds = %12
  %43 = getelementptr inbounds [2 x i32], ptr %33, i64 0, i64 0
  store i32 234887171, ptr %43, align 4, !tbaa !9
  %44 = getelementptr inbounds [2 x i32], ptr %33, i64 0, i64 1
  store i32 234903555, ptr %44, align 4, !tbaa !9
  store i32 5, ptr %34, align 4, !tbaa !9
  br label %45

45:                                               ; preds = %42, %12
  %46 = load i32, ptr %20, align 4, !tbaa !9
  %47 = load i32, ptr %18, align 4, !tbaa !9
  %48 = udiv i32 %46, %47
  %49 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  store i32 %48, ptr %49, align 4, !tbaa !9
  %50 = load i32, ptr %20, align 4, !tbaa !9
  %51 = load i32, ptr %18, align 4, !tbaa !9
  %52 = urem i32 %50, %51
  %53 = load i32, ptr %18, align 4, !tbaa !9
  %54 = udiv i32 %53, 2
  %55 = udiv i32 %52, %54
  %56 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 1
  store i32 %55, ptr %56, align 4, !tbaa !9
  %57 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %58 = load i32, ptr %57, align 4, !tbaa !9
  %59 = mul i32 %58, 16
  %60 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 1
  %61 = load i32, ptr %60, align 4, !tbaa !9
  %62 = mul i32 %61, 8
  %63 = add i32 %59, %62
  store i32 %63, ptr %31, align 4, !tbaa !9
  %64 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 0
  %65 = load i32, ptr %64, align 16, !tbaa !9
  store i32 %65, ptr %25, align 4, !tbaa !9
  %66 = load i32, ptr %25, align 4, !tbaa !9
  %67 = sub i32 %66, 2
  %68 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  store i32 %67, ptr %68, align 4, !tbaa !9
  %69 = load i32, ptr %25, align 4, !tbaa !9
  %70 = sub i32 %69, 1
  %71 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  store i32 %70, ptr %71, align 4, !tbaa !9
  %72 = load i32, ptr %23, align 4, !tbaa !9
  %73 = icmp eq i32 %72, 0
  br i1 %73, label %74, label %197

74:                                               ; preds = %45
  store i32 0, ptr %27, align 4, !tbaa !9
  br label %75

75:                                               ; preds = %184, %74
  %76 = load i32, ptr %27, align 4, !tbaa !9
  %77 = load i32, ptr %28, align 4, !tbaa !9
  %78 = icmp ult i32 %76, %77
  br i1 %78, label %79, label %187

79:                                               ; preds = %75
  %80 = load ptr, ptr %13, align 8, !tbaa !5
  %81 = load i32, ptr %16, align 4, !tbaa !9
  %82 = load i32, ptr %17, align 4, !tbaa !9
  %83 = load i32, ptr %17, align 4, !tbaa !9
  %84 = load i32, ptr %22, align 4, !tbaa !9
  %85 = zext i32 %84 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %80, i32 noundef 4096, i32 noundef %81, i32 noundef %82, i32 noundef %83, i64 noundef %85)
  store i32 0, ptr %29, align 4, !tbaa !9
  br label %86

86:                                               ; preds = %133, %79
  %87 = load i32, ptr %29, align 4, !tbaa !9
  %88 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %89 = load i32, ptr %88, align 4, !tbaa !9
  %90 = icmp ult i32 %87, %89
  br i1 %90, label %91, label %136

91:                                               ; preds = %86
  %92 = load ptr, ptr %13, align 8, !tbaa !5
  %93 = load i32, ptr %16, align 4, !tbaa !9
  %94 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  %95 = load i32, ptr %94, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %92, i32 noundef 1010828294, i32 noundef %93, i32 noundef 127, i32 noundef 16, i32 noundef %95, i32 noundef 1)
  %96 = load ptr, ptr %13, align 8, !tbaa !5
  %97 = load i32, ptr %17, align 4, !tbaa !9
  %98 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  %99 = load i32, ptr %98, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %96, i32 noundef 1010828294, i32 noundef %97, i32 noundef 127, i32 noundef 16, i32 noundef %99, i32 noundef 1)
  %100 = load ptr, ptr %13, align 8, !tbaa !5
  %101 = getelementptr inbounds [2 x i32], ptr %33, i64 0, i64 0
  %102 = load i32, ptr %101, align 4, !tbaa !9
  %103 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  %104 = load i32, ptr %103, align 4, !tbaa !9
  %105 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  %106 = load i32, ptr %105, align 4, !tbaa !9
  %107 = load i32, ptr %27, align 4, !tbaa !9
  %108 = mul i32 8, %107
  %109 = load i32, ptr %29, align 4, !tbaa !9
  %110 = mul i32 2, %109
  %111 = add i32 %108, %110
  %112 = zext i32 %111 to i64
  %113 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %112
  %114 = load i32, ptr %113, align 4, !tbaa !9
  %115 = load i32, ptr %34, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %100, i32 noundef %102, i32 noundef %104, i32 noundef %106, i8 noundef zeroext 0, i32 noundef %114, i32 noundef %115)
  %116 = load ptr, ptr %13, align 8, !tbaa !5
  %117 = getelementptr inbounds [2 x i32], ptr %33, i64 0, i64 1
  %118 = load i32, ptr %117, align 4, !tbaa !9
  %119 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  %120 = load i32, ptr %119, align 4, !tbaa !9
  %121 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  %122 = load i32, ptr %121, align 4, !tbaa !9
  %123 = load i32, ptr %27, align 4, !tbaa !9
  %124 = mul i32 8, %123
  %125 = load i32, ptr %29, align 4, !tbaa !9
  %126 = mul i32 2, %125
  %127 = add i32 %124, %126
  %128 = add i32 %127, 1
  %129 = zext i32 %128 to i64
  %130 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %129
  %131 = load i32, ptr %130, align 4, !tbaa !9
  %132 = load i32, ptr %34, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %116, i32 noundef %118, i32 noundef %120, i32 noundef %122, i8 noundef zeroext 0, i32 noundef %131, i32 noundef %132)
  br label %133

133:                                              ; preds = %91
  %134 = load i32, ptr %29, align 4, !tbaa !9
  %135 = add i32 %134, 1
  store i32 %135, ptr %29, align 4, !tbaa !9
  br label %86, !llvm.loop !12

136:                                              ; preds = %86
  store i32 0, ptr %29, align 4, !tbaa !9
  br label %137

137:                                              ; preds = %170, %136
  %138 = load i32, ptr %29, align 4, !tbaa !9
  %139 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 1
  %140 = load i32, ptr %139, align 4, !tbaa !9
  %141 = icmp ult i32 %138, %140
  br i1 %141, label %142, label %173

142:                                              ; preds = %137
  %143 = load ptr, ptr %13, align 8, !tbaa !5
  %144 = load i32, ptr %16, align 4, !tbaa !9
  %145 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  %146 = load i32, ptr %145, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %143, i32 noundef 1010828294, i32 noundef %144, i32 noundef 127, i32 noundef 8, i32 noundef %146, i32 noundef 6)
  %147 = load ptr, ptr %13, align 8, !tbaa !5
  %148 = load i32, ptr %17, align 4, !tbaa !9
  %149 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  %150 = load i32, ptr %149, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %147, i32 noundef 1010828294, i32 noundef %148, i32 noundef 127, i32 noundef 8, i32 noundef %150, i32 noundef 6)
  %151 = load ptr, ptr %13, align 8, !tbaa !5
  %152 = getelementptr inbounds [2 x i32], ptr %33, i64 0, i64 0
  %153 = load i32, ptr %152, align 4, !tbaa !9
  %154 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 0
  %155 = load i32, ptr %154, align 4, !tbaa !9
  %156 = getelementptr inbounds [2 x i32], ptr %26, i64 0, i64 1
  %157 = load i32, ptr %156, align 4, !tbaa !9
  %158 = load i32, ptr %27, align 4, !tbaa !9
  %159 = mul i32 8, %158
  %160 = load i32, ptr %29, align 4, !tbaa !9
  %161 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %162 = load i32, ptr %161, align 4, !tbaa !9
  %163 = add i32 %160, %162
  %164 = mul i32 2, %163
  %165 = add i32 %159, %164
  %166 = zext i32 %165 to i64
  %167 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %166
  %168 = load i32, ptr %167, align 4, !tbaa !9
  %169 = load i32, ptr %34, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %151, i32 noundef %153, i32 noundef %155, i32 noundef %157, i8 noundef zeroext 0, i32 noundef %168, i32 noundef %169)
  br label %170

170:                                              ; preds = %142
  %171 = load i32, ptr %29, align 4, !tbaa !9
  %172 = add i32 %171, 1
  store i32 %172, ptr %29, align 4, !tbaa !9
  br label %137, !llvm.loop !14

173:                                              ; preds = %137
  %174 = load ptr, ptr %13, align 8, !tbaa !5
  %175 = load i32, ptr %16, align 4, !tbaa !9
  %176 = load i32, ptr %17, align 4, !tbaa !9
  %177 = load i32, ptr %16, align 4, !tbaa !9
  %178 = load i32, ptr %22, align 4, !tbaa !9
  %179 = zext i32 %178 to i64
  %180 = mul i64 2, %179
  %181 = load i32, ptr %31, align 4, !tbaa !9
  %182 = zext i32 %181 to i64
  %183 = sub i64 %180, %182
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %174, i32 noundef 4096, i32 noundef %175, i32 noundef %176, i32 noundef %177, i64 noundef %183)
  br label %184

184:                                              ; preds = %173
  %185 = load i32, ptr %27, align 4, !tbaa !9
  %186 = add i32 %185, 1
  store i32 %186, ptr %27, align 4, !tbaa !9
  br label %75, !llvm.loop !15

187:                                              ; preds = %75
  %188 = load ptr, ptr %13, align 8, !tbaa !5
  %189 = load i32, ptr %16, align 4, !tbaa !9
  %190 = load i32, ptr %17, align 4, !tbaa !9
  %191 = load i32, ptr %16, align 4, !tbaa !9
  %192 = load i32, ptr %22, align 4, !tbaa !9
  %193 = zext i32 %192 to i64
  %194 = load i32, ptr %21, align 4, !tbaa !9
  %195 = zext i32 %194 to i64
  %196 = mul nsw i64 %193, %195
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %188, i32 noundef 4097, i32 noundef %189, i32 noundef %190, i32 noundef %191, i64 noundef %196)
  br label %351

197:                                              ; preds = %45
  store i32 0, ptr %27, align 4, !tbaa !9
  br label %198

198:                                              ; preds = %347, %197
  %199 = load i32, ptr %27, align 4, !tbaa !9
  %200 = load i32, ptr %28, align 4, !tbaa !9
  %201 = icmp ult i32 %199, %200
  br i1 %201, label %202, label %350

202:                                              ; preds = %198
  store i32 0, ptr %29, align 4, !tbaa !9
  br label %203

203:                                              ; preds = %262, %202
  %204 = load i32, ptr %29, align 4, !tbaa !9
  %205 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %206 = load i32, ptr %205, align 4, !tbaa !9
  %207 = icmp ult i32 %204, %206
  br i1 %207, label %208, label %265

208:                                              ; preds = %203
  %209 = load ptr, ptr %13, align 8, !tbaa !5
  %210 = load i32, ptr %27, align 4, !tbaa !9
  %211 = mul i32 8, %210
  %212 = load i32, ptr %29, align 4, !tbaa !9
  %213 = mul i32 2, %212
  %214 = add i32 %211, %213
  %215 = zext i32 %214 to i64
  %216 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %215
  %217 = load i32, ptr %216, align 4, !tbaa !9
  %218 = load i32, ptr %27, align 4, !tbaa !9
  %219 = mul i32 8, %218
  %220 = load i32, ptr %29, align 4, !tbaa !9
  %221 = mul i32 2, %220
  %222 = add i32 %219, %221
  %223 = zext i32 %222 to i64
  %224 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %223
  %225 = load i32, ptr %224, align 4, !tbaa !9
  %226 = load i32, ptr %27, align 4, !tbaa !9
  %227 = mul i32 8, %226
  %228 = load i32, ptr %29, align 4, !tbaa !9
  %229 = mul i32 2, %228
  %230 = add i32 %227, %229
  %231 = zext i32 %230 to i64
  %232 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %231
  %233 = load i32, ptr %232, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %209, i32 noundef 773856275, i32 noundef %217, i32 noundef %225, i8 noundef zeroext 0, i32 noundef %233, i32 noundef 1)
  %234 = load ptr, ptr %13, align 8, !tbaa !5
  %235 = load i32, ptr %27, align 4, !tbaa !9
  %236 = mul i32 8, %235
  %237 = load i32, ptr %29, align 4, !tbaa !9
  %238 = mul i32 2, %237
  %239 = add i32 %236, %238
  %240 = add i32 %239, 1
  %241 = zext i32 %240 to i64
  %242 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %241
  %243 = load i32, ptr %242, align 4, !tbaa !9
  %244 = load i32, ptr %27, align 4, !tbaa !9
  %245 = mul i32 8, %244
  %246 = load i32, ptr %29, align 4, !tbaa !9
  %247 = mul i32 2, %246
  %248 = add i32 %245, %247
  %249 = add i32 %248, 1
  %250 = zext i32 %249 to i64
  %251 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %250
  %252 = load i32, ptr %251, align 4, !tbaa !9
  %253 = load i32, ptr %27, align 4, !tbaa !9
  %254 = mul i32 8, %253
  %255 = load i32, ptr %29, align 4, !tbaa !9
  %256 = mul i32 2, %255
  %257 = add i32 %254, %256
  %258 = add i32 %257, 1
  %259 = zext i32 %258 to i64
  %260 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %259
  %261 = load i32, ptr %260, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %234, i32 noundef 773856275, i32 noundef %243, i32 noundef %252, i8 noundef zeroext 0, i32 noundef %261, i32 noundef 1)
  br label %262

262:                                              ; preds = %208
  %263 = load i32, ptr %29, align 4, !tbaa !9
  %264 = add i32 %263, 1
  store i32 %264, ptr %29, align 4, !tbaa !9
  br label %203, !llvm.loop !16

265:                                              ; preds = %203
  store i32 0, ptr %29, align 4, !tbaa !9
  br label %266

266:                                              ; preds = %343, %265
  %267 = load i32, ptr %29, align 4, !tbaa !9
  %268 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 1
  %269 = load i32, ptr %268, align 4, !tbaa !9
  %270 = icmp ult i32 %267, %269
  br i1 %270, label %271, label %346

271:                                              ; preds = %266
  %272 = load ptr, ptr %13, align 8, !tbaa !5
  %273 = load i32, ptr %27, align 4, !tbaa !9
  %274 = mul i32 8, %273
  %275 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %276 = load i32, ptr %275, align 4, !tbaa !9
  %277 = load i32, ptr %29, align 4, !tbaa !9
  %278 = add i32 %276, %277
  %279 = mul i32 2, %278
  %280 = add i32 %274, %279
  %281 = zext i32 %280 to i64
  %282 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %281
  %283 = load i32, ptr %282, align 4, !tbaa !9
  %284 = load i32, ptr %27, align 4, !tbaa !9
  %285 = mul i32 8, %284
  %286 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %287 = load i32, ptr %286, align 4, !tbaa !9
  %288 = load i32, ptr %29, align 4, !tbaa !9
  %289 = add i32 %287, %288
  %290 = mul i32 2, %289
  %291 = add i32 %285, %290
  %292 = zext i32 %291 to i64
  %293 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %292
  %294 = load i32, ptr %293, align 4, !tbaa !9
  %295 = load i32, ptr %27, align 4, !tbaa !9
  %296 = mul i32 8, %295
  %297 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %298 = load i32, ptr %297, align 4, !tbaa !9
  %299 = load i32, ptr %29, align 4, !tbaa !9
  %300 = add i32 %298, %299
  %301 = mul i32 2, %300
  %302 = add i32 %296, %301
  %303 = zext i32 %302 to i64
  %304 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %303
  %305 = load i32, ptr %304, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %272, i32 noundef 773856275, i32 noundef %283, i32 noundef %294, i8 noundef zeroext 0, i32 noundef %305, i32 noundef 0)
  %306 = load ptr, ptr %13, align 8, !tbaa !5
  %307 = load i32, ptr %27, align 4, !tbaa !9
  %308 = mul i32 8, %307
  %309 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %310 = load i32, ptr %309, align 4, !tbaa !9
  %311 = load i32, ptr %29, align 4, !tbaa !9
  %312 = add i32 %310, %311
  %313 = mul i32 2, %312
  %314 = add i32 %308, %313
  %315 = add i32 %314, 1
  %316 = zext i32 %315 to i64
  %317 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %316
  %318 = load i32, ptr %317, align 4, !tbaa !9
  %319 = load i32, ptr %27, align 4, !tbaa !9
  %320 = mul i32 8, %319
  %321 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %322 = load i32, ptr %321, align 4, !tbaa !9
  %323 = load i32, ptr %29, align 4, !tbaa !9
  %324 = add i32 %322, %323
  %325 = mul i32 2, %324
  %326 = add i32 %320, %325
  %327 = add i32 %326, 1
  %328 = zext i32 %327 to i64
  %329 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %328
  %330 = load i32, ptr %329, align 4, !tbaa !9
  %331 = load i32, ptr %27, align 4, !tbaa !9
  %332 = mul i32 8, %331
  %333 = getelementptr inbounds [2 x i32], ptr %30, i64 0, i64 0
  %334 = load i32, ptr %333, align 4, !tbaa !9
  %335 = load i32, ptr %29, align 4, !tbaa !9
  %336 = add i32 %334, %335
  %337 = mul i32 2, %336
  %338 = add i32 %332, %337
  %339 = add i32 %338, 1
  %340 = zext i32 %339 to i64
  %341 = getelementptr inbounds [24 x i32], ptr %32, i64 0, i64 %340
  %342 = load i32, ptr %341, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %306, i32 noundef 773856275, i32 noundef %318, i32 noundef %330, i8 noundef zeroext 0, i32 noundef %342, i32 noundef 0)
  br label %343

343:                                              ; preds = %271
  %344 = load i32, ptr %29, align 4, !tbaa !9
  %345 = add i32 %344, 1
  store i32 %345, ptr %29, align 4, !tbaa !9
  br label %266, !llvm.loop !17

346:                                              ; preds = %266
  br label %347

347:                                              ; preds = %346
  %348 = load i32, ptr %27, align 4, !tbaa !9
  %349 = add i32 %348, 1
  store i32 %349, ptr %27, align 4, !tbaa !9
  br label %198, !llvm.loop !18

350:                                              ; preds = %198
  br label %351

351:                                              ; preds = %350, %187
  call void @llvm.lifetime.end.p0(i64 4, ptr %34) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %33) #4
  call void @llvm.lifetime.end.p0(i64 96, ptr %32) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %31) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %30) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %29) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %28) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %27) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %26) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #4
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}
!15 = distinct !{!15, !13}
!16 = distinct !{!16, !13}
!17 = distinct !{!17, !13}
!18 = distinct !{!18, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c = external hidden unnamed_addr constant [24 x i32], align 16
@__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_instr_zip = external hidden unnamed_addr constant [2 x i32], align 4

declare void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_2dregblock_mmla_aarch64_asimd(ptr noundef %0, ptr nocapture noundef readnone %1, ptr nocapture noundef readnone %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9, i32 noundef %10, i8 noundef zeroext %11) local_unnamed_addr #1 {
  %13 = lshr i32 %8, 1
  %.sroa.0.0.copyload = load i32, ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_instr_zip, align 4
  %.sroa.6.0.copyload = load i32, ptr getelementptr inbounds (i8, ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_instr_zip, i64 4), align 4
  %.not = icmp eq i8 %11, 0
  %.sroa.6.0 = select i1 %.not, i32 %.sroa.6.0.copyload, i32 234903555
  %.sroa.0.0 = select i1 %.not, i32 %.sroa.0.0.copyload, i32 234887171
  %.0 = select i1 %.not, i32 7, i32 5
  %14 = udiv i32 %7, %5
  %15 = urem i32 %7, %5
  %16 = lshr i32 %5, 1
  %17 = udiv i32 %15, %16
  %18 = shl i32 %14, 4
  %19 = shl i32 %17, 3
  %20 = add i32 %19, %18
  %21 = load i32, ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, align 16, !tbaa !5
  %22 = add i32 %21, -2
  %23 = add i32 %21, -1
  %24 = icmp eq i32 %10, 0
  %.not141 = icmp ult i32 %8, 2
  br i1 %24, label %.preheader118, label %.preheader121

.preheader121:                                    ; preds = %12
  br i1 %.not141, label %.loopexit, label %.preheader120.lr.ph

.preheader120.lr.ph:                              ; preds = %.preheader121
  %.not139 = icmp ugt i32 %5, %7
  %.not140 = icmp ugt i32 %16, %15
  br i1 %.not140, label %.preheader120.lr.ph.split, label %.preheader120.us.preheader

.preheader120.us.preheader:                       ; preds = %.preheader120.lr.ph
  %25 = zext i32 %14 to i64
  %26 = zext i32 %17 to i64
  br label %.preheader120.us

.preheader120.us:                                 ; preds = %.preheader120.us.preheader, %._crit_edge.us
  %.1125.us = phi i32 [ %50, %._crit_edge.us ], [ 0, %.preheader120.us.preheader ]
  %.pre161 = shl i32 %.1125.us, 3
  br i1 %.not139, label %.preheader119.us.preheader, label %.lr.ph.us

.preheader119.us.preheader:                       ; preds = %.lr.ph.us, %.preheader120.us
  br label %.preheader119.us

.preheader119.us:                                 ; preds = %.preheader119.us.preheader, %.preheader119.us
  %indvars.iv147 = phi i64 [ %indvars.iv.next148, %.preheader119.us ], [ 0, %.preheader119.us.preheader ]
  %27 = trunc nuw i64 %indvars.iv147 to i32
  %28 = add i32 %14, %27
  %29 = shl i32 %28, 1
  %30 = add i32 %29, %.pre161
  %31 = zext i32 %30 to i64
  %32 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %31
  %33 = load i32, ptr %32, align 8, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %33, i32 noundef %33, i8 noundef zeroext 0, i32 noundef %33, i32 noundef 0) #2
  %34 = or disjoint i32 %30, 1
  %35 = zext i32 %34 to i64
  %36 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %35
  %37 = load i32, ptr %36, align 4, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %37, i32 noundef %37, i8 noundef zeroext 0, i32 noundef %37, i32 noundef 0) #2
  %indvars.iv.next148 = add nuw nsw i64 %indvars.iv147, 1
  %38 = icmp ult i64 %indvars.iv.next148, %26
  br i1 %38, label %.preheader119.us, label %._crit_edge.us, !llvm.loop !9

.lr.ph.us:                                        ; preds = %.preheader120.us, %.lr.ph.us
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph.us ], [ 0, %.preheader120.us ]
  %39 = trunc nuw i64 %indvars.iv to i32
  %40 = shl i32 %39, 1
  %41 = add i32 %40, %.pre161
  %42 = zext i32 %41 to i64
  %43 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %42
  %44 = load i32, ptr %43, align 8, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %44, i32 noundef %44, i8 noundef zeroext 0, i32 noundef %44, i32 noundef 1) #2
  %45 = or disjoint i32 %41, 1
  %46 = zext i32 %45 to i64
  %47 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %46
  %48 = load i32, ptr %47, align 4, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %48, i32 noundef %48, i8 noundef zeroext 0, i32 noundef %48, i32 noundef 1) #2
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %49 = icmp ult i64 %indvars.iv.next, %25
  br i1 %49, label %.lr.ph.us, label %.preheader119.us.preheader, !llvm.loop !11

._crit_edge.us:                                   ; preds = %.preheader119.us
  %50 = add nuw nsw i32 %.1125.us, 1
  %exitcond.not = icmp eq i32 %50, %13
  br i1 %exitcond.not, label %.loopexit, label %.preheader120.us, !llvm.loop !12

.preheader120.lr.ph.split:                        ; preds = %.preheader120.lr.ph
  br i1 %.not139, label %.loopexit, label %.preheader120.us126.preheader

.preheader120.us126.preheader:                    ; preds = %.preheader120.lr.ph.split
  %51 = zext i32 %14 to i64
  br label %.preheader120.us126

.preheader120.us126:                              ; preds = %.preheader120.us126.preheader, %..preheader119_crit_edge.us131
  %.1125.us127 = phi i32 [ %65, %..preheader119_crit_edge.us131 ], [ 0, %.preheader120.us126.preheader ]
  %52 = shl i32 %.1125.us127, 3
  br label %53

53:                                               ; preds = %.preheader120.us126, %53
  %indvars.iv150 = phi i64 [ 0, %.preheader120.us126 ], [ %indvars.iv.next151, %53 ]
  %54 = trunc nuw i64 %indvars.iv150 to i32
  %55 = shl i32 %54, 1
  %56 = add i32 %55, %52
  %57 = zext i32 %56 to i64
  %58 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %57
  %59 = load i32, ptr %58, align 8, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %59, i32 noundef %59, i8 noundef zeroext 0, i32 noundef %59, i32 noundef 1) #2
  %60 = or disjoint i32 %56, 1
  %61 = zext i32 %60 to i64
  %62 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %61
  %63 = load i32, ptr %62, align 4, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773856275, i32 noundef %63, i32 noundef %63, i8 noundef zeroext 0, i32 noundef %63, i32 noundef 1) #2
  %indvars.iv.next151 = add nuw nsw i64 %indvars.iv150, 1
  %64 = icmp ult i64 %indvars.iv.next151, %51
  br i1 %64, label %53, label %..preheader119_crit_edge.us131, !llvm.loop !11

..preheader119_crit_edge.us131:                   ; preds = %53
  %65 = add nuw nsw i32 %.1125.us127, 1
  %exitcond153.not = icmp eq i32 %65, %13
  br i1 %exitcond153.not, label %.loopexit, label %.preheader120.us126, !llvm.loop !12

.preheader118:                                    ; preds = %12
  %.pre = zext i32 %9 to i64
  br i1 %.not141, label %._crit_edge137, label %.lr.ph136

.lr.ph136:                                        ; preds = %.preheader118
  %.not142 = icmp ugt i32 %5, %7
  %.not143 = icmp ugt i32 %16, %15
  %66 = shl nuw nsw i64 %.pre, 1
  %67 = zext i32 %20 to i64
  %68 = sub nsw i64 %66, %67
  %69 = zext i32 %14 to i64
  %70 = zext i32 %17 to i64
  br label %71

71:                                               ; preds = %.lr.ph136, %._crit_edge
  %.0113135 = phi i32 [ 0, %.lr.ph136 ], [ %95, %._crit_edge ]
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %3, i32 noundef %4, i32 noundef %4, i64 noundef %.pre) #2
  br i1 %.not142, label %.preheader, label %.lr.ph

.lr.ph:                                           ; preds = %71
  %72 = shl i32 %.0113135, 3
  br label %74

.preheader:                                       ; preds = %74, %71
  br i1 %.not143, label %._crit_edge, label %.lr.ph134

.lr.ph134:                                        ; preds = %.preheader
  %73 = shl i32 %.0113135, 3
  br label %86

74:                                               ; preds = %.lr.ph, %74
  %indvars.iv154 = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next155, %74 ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1010828294, i32 noundef %3, i32 noundef 127, i32 noundef 16, i32 noundef %22, i32 noundef 1) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1010828294, i32 noundef %4, i32 noundef 127, i32 noundef 16, i32 noundef %23, i32 noundef 1) #2
  %75 = trunc nuw i64 %indvars.iv154 to i32
  %76 = shl i32 %75, 1
  %77 = add i32 %76, %72
  %78 = zext i32 %77 to i64
  %79 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %78
  %80 = load i32, ptr %79, align 8, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef %.sroa.0.0, i32 noundef %22, i32 noundef %23, i8 noundef zeroext 0, i32 noundef %80, i32 noundef %.0) #2
  %81 = or disjoint i32 %77, 1
  %82 = zext i32 %81 to i64
  %83 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %82
  %84 = load i32, ptr %83, align 4, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef %.sroa.6.0, i32 noundef %22, i32 noundef %23, i8 noundef zeroext 0, i32 noundef %84, i32 noundef %.0) #2
  %indvars.iv.next155 = add nuw nsw i64 %indvars.iv154, 1
  %85 = icmp ult i64 %indvars.iv.next155, %69
  br i1 %85, label %74, label %.preheader, !llvm.loop !13

86:                                               ; preds = %.lr.ph134, %86
  %indvars.iv157 = phi i64 [ 0, %.lr.ph134 ], [ %indvars.iv.next158, %86 ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1010828294, i32 noundef %3, i32 noundef 127, i32 noundef 8, i32 noundef %22, i32 noundef 6) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1010828294, i32 noundef %4, i32 noundef 127, i32 noundef 8, i32 noundef %23, i32 noundef 6) #2
  %87 = trunc nuw i64 %indvars.iv157 to i32
  %88 = add i32 %14, %87
  %89 = shl i32 %88, 1
  %90 = add i32 %89, %73
  %91 = zext i32 %90 to i64
  %92 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_load_2dregblock_mmla_aarch64_asimd.l_vr_c, i64 0, i64 %91
  %93 = load i32, ptr %92, align 8, !tbaa !5
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef %.sroa.0.0, i32 noundef %22, i32 noundef %23, i8 noundef zeroext 0, i32 noundef %93, i32 noundef %.0) #2
  %indvars.iv.next158 = add nuw nsw i64 %indvars.iv157, 1
  %94 = icmp ult i64 %indvars.iv.next158, %70
  br i1 %94, label %86, label %._crit_edge, !llvm.loop !14

._crit_edge:                                      ; preds = %86, %.preheader
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %3, i32 noundef %4, i32 noundef %3, i64 noundef %68) #2
  %95 = add nuw nsw i32 %.0113135, 1
  %exitcond160.not = icmp eq i32 %95, %13
  br i1 %exitcond160.not, label %._crit_edge137, label %71, !llvm.loop !15

._crit_edge137:                                   ; preds = %._crit_edge, %.preheader118
  %96 = zext i32 %8 to i64
  %97 = mul nuw nsw i64 %.pre, %96
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4097, i32 noundef %3, i32 noundef %4, i32 noundef %3, i64 noundef %97) #2
  br label %.loopexit

.loopexit:                                        ; preds = %._crit_edge.us, %..preheader119_crit_edge.us131, %.preheader120.lr.ph.split, %.preheader121, %._crit_edge137
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass