; LLVM IR from abeaumont/competitive-programming :: codeforces/1169/c.ll (Z5solvei)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@n = external dso_local global i32, align 4
@m = external dso_local global i32, align 4
@a = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5solvei(i32 noundef %0) #0 {
  %2 = alloca i1, align 1
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  %7 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef 0) #2
  %8 = load i32, ptr %7, align 4, !tbaa !5
  store i32 %8, ptr %4, align 4, !tbaa !5
  %9 = load i32, ptr %4, align 4, !tbaa !5
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = add nsw i32 %9, %10
  %12 = load i32, ptr @m, align 4, !tbaa !5
  %13 = icmp sge i32 %11, %12
  br i1 %13, label %14, label %15

14:                                               ; preds = %1
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %15

15:                                               ; preds = %14, %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 1, ptr %5, align 4, !tbaa !5
  br label %16

16:                                               ; preds = %80, %15
  %17 = load i32, ptr %5, align 4, !tbaa !5
  %18 = load i32, ptr @n, align 4, !tbaa !5
  %19 = icmp slt i32 %17, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %16
  store i32 2, ptr %6, align 4
  br label %83

21:                                               ; preds = %16
  %22 = load i32, ptr %5, align 4, !tbaa !5
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %23) #2
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = icmp sle i32 %25, %26
  br i1 %27, label %28, label %38

28:                                               ; preds = %21
  %29 = load i32, ptr %5, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %30) #2
  %32 = load i32, ptr %31, align 4, !tbaa !5
  %33 = load i32, ptr %3, align 4, !tbaa !5
  %34 = add nsw i32 %32, %33
  %35 = load i32, ptr %4, align 4, !tbaa !5
  %36 = icmp sge i32 %34, %35
  br i1 %36, label %37, label %38

37:                                               ; preds = %28
  br label %80

38:                                               ; preds = %28, %21
  %39 = load i32, ptr %5, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %40) #2
  %42 = load i32, ptr %41, align 4, !tbaa !5
  %43 = load i32, ptr %4, align 4, !tbaa !5
  %44 = icmp sgt i32 %42, %43
  br i1 %44, label %45, label %66

45:                                               ; preds = %38
  %46 = load i32, ptr %5, align 4, !tbaa !5
  %47 = sext i32 %46 to i64
  %48 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %47) #2
  %49 = load i32, ptr %48, align 4, !tbaa !5
  %50 = load i32, ptr %3, align 4, !tbaa !5
  %51 = add nsw i32 %49, %50
  %52 = load i32, ptr @m, align 4, !tbaa !5
  %53 = icmp sge i32 %51, %52
  br i1 %53, label %54, label %66

54:                                               ; preds = %45
  %55 = load i32, ptr %5, align 4, !tbaa !5
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %56) #2
  %58 = load i32, ptr %57, align 4, !tbaa !5
  %59 = load i32, ptr %3, align 4, !tbaa !5
  %60 = add nsw i32 %58, %59
  %61 = load i32, ptr @m, align 4, !tbaa !5
  %62 = srem i32 %60, %61
  %63 = load i32, ptr %4, align 4, !tbaa !5
  %64 = icmp sge i32 %62, %63
  br i1 %64, label %65, label %66

65:                                               ; preds = %54
  br label %80

66:                                               ; preds = %54, %45, %38
  %67 = load i32, ptr %5, align 4, !tbaa !5
  %68 = sext i32 %67 to i64
  %69 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %68) #2
  %70 = load i32, ptr %69, align 4, !tbaa !5
  %71 = load i32, ptr %4, align 4, !tbaa !5
  %72 = icmp sgt i32 %70, %71
  br i1 %72, label %73, label %78

73:                                               ; preds = %66
  %74 = load i32, ptr %5, align 4, !tbaa !5
  %75 = sext i32 %74 to i64
  %76 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %75) #2
  %77 = load i32, ptr %76, align 4, !tbaa !5
  store i32 %77, ptr %4, align 4, !tbaa !5
  br label %79

78:                                               ; preds = %66
  store i1 false, ptr %2, align 1
  store i32 1, ptr %6, align 4
  br label %83

79:                                               ; preds = %73
  br label %80

80:                                               ; preds = %79, %65, %37
  %81 = load i32, ptr %5, align 4, !tbaa !5
  %82 = add nsw i32 %81, 1
  store i32 %82, ptr %5, align 4, !tbaa !5
  br label %16, !llvm.loop !9

83:                                               ; preds = %78, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  %84 = load i32, ptr %6, align 4
  switch i32 %84, label %86 [
    i32 2, label %85
  ]

85:                                               ; preds = %83
  store i1 true, ptr %2, align 1
  store i32 1, ptr %6, align 4
  br label %86

86:                                               ; preds = %85, %83
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  %87 = load i1, ptr %2, align 1
  ret i1 %87
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@n = external dso_local local_unnamed_addr global i32, align 4
@m = external dso_local local_unnamed_addr global i32, align 4
@a = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5solvei(i32 noundef %0) local_unnamed_addr #0 {
  %2 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef 0) #1
  %3 = load i32, ptr @n, align 4, !tbaa !5
  %.not2829 = icmp slt i32 %3, 2
  br i1 %.not2829, label %.critedge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %1
  %4 = load i32, ptr %2, align 4, !tbaa !5
  %5 = add nsw i32 %4, %0
  %6 = load i32, ptr @m, align 4, !tbaa !5
  %.not = icmp slt i32 %5, %6
  %spec.store.select = select i1 %.not, i32 %4, i32 0
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %35
  %indvars.iv = phi i64 [ 1, %.lr.ph.preheader ], [ %indvars.iv.next, %35 ]
  %.02130 = phi i32 [ %spec.store.select, %.lr.ph.preheader ], [ %.1, %35 ]
  %7 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %8 = load i32, ptr %7, align 4, !tbaa !5
  %.not24 = icmp sgt i32 %8, %.02130
  br i1 %.not24, label %13, label %9

9:                                                ; preds = %.lr.ph
  %10 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %11 = load i32, ptr %10, align 4, !tbaa !5
  %12 = add nsw i32 %11, %0
  %.not25 = icmp slt i32 %12, %.02130
  br i1 %.not25, label %13, label %35

13:                                               ; preds = %9, %.lr.ph
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = icmp sgt i32 %15, %.02130
  br i1 %16, label %17, label %28

17:                                               ; preds = %13
  %18 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %19 = load i32, ptr %18, align 4, !tbaa !5
  %20 = add nsw i32 %19, %0
  %21 = load i32, ptr @m, align 4, !tbaa !5
  %.not26 = icmp slt i32 %20, %21
  br i1 %.not26, label %28, label %22

22:                                               ; preds = %17
  %23 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %25 = add nsw i32 %24, %0
  %26 = load i32, ptr @m, align 4, !tbaa !5
  %27 = srem i32 %25, %26
  %.not27 = icmp slt i32 %27, %.02130
  br i1 %.not27, label %28, label %35

28:                                               ; preds = %22, %17, %13
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %31 = icmp sgt i32 %30, %.02130
  br i1 %31, label %32, label %.critedge

32:                                               ; preds = %28
  %33 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %indvars.iv) #1
  %34 = load i32, ptr %33, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %22, %9, %32
  %.1 = phi i32 [ %.02130, %9 ], [ %.02130, %22 ], [ %34, %32 ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %36 = load i32, ptr @n, align 4, !tbaa !5
  %37 = sext i32 %36 to i64
  %.not28.not = icmp slt i64 %indvars.iv.next, %37
  br i1 %.not28.not, label %.lr.ph, label %.critedge, !llvm.loop !9

.critedge:                                        ; preds = %28, %35, %1
  %.not28.lcssa = phi i1 [ true, %1 ], [ true, %35 ], [ false, %28 ]
  ret i1 %.not28.lcssa
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass