; LLVM IR from NVIDIA/DALI :: dali/pipeline/executor (op_graph_storage)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.108" = type { %"struct.std::_Vector_base.109" }
%"struct.std::_Vector_base.109" = type { %"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4dali23CreateEventsForMixedOpsERNS_9EventPoolERKNS_7OpGraphEi(ptr dead_on_unwind noalias writable sret(%"class.std::vector.108") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef %3) #1 personality ptr @__gxx_personality_v0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i1, align 1
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %5, align 8
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !9
  store i1 false, ptr %9, align 1
  call void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  %16 = invoke noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %15, i32 noundef 2)
          to label %17 unwind label %27

17:                                               ; preds = %4
  invoke void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %16)
          to label %18 unwind label %27

18:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %19

19:                                               ; preds = %65, %18
  %20 = load i32, ptr %12, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = load ptr, ptr %7, align 8, !tbaa !5
  %23 = invoke noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %22, i32 noundef 2)
          to label %24 unwind label %31

24:                                               ; preds = %19
  %25 = icmp slt i64 %21, %23
  br i1 %25, label %35, label %26

26:                                               ; preds = %24
  store i32 2, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  br label %69

27:                                               ; preds = %17, %4
  %28 = landingpad { ptr, i32 }
          cleanup
  %29 = extractvalue { ptr, i32 } %28, 0
  store ptr %29, ptr %10, align 8
  %30 = extractvalue { ptr, i32 } %28, 1
  store i32 %30, ptr %11, align 4
  br label %73

31:                                               ; preds = %35, %19
  %32 = landingpad { ptr, i32 }
          cleanup
  %33 = extractvalue { ptr, i32 } %32, 0
  store ptr %33, ptr %10, align 8
  %34 = extractvalue { ptr, i32 } %32, 1
  store i32 %34, ptr %11, align 4
  br label %68

35:                                               ; preds = %24
  %36 = load i32, ptr %12, align 4, !tbaa !9
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %37) #4
  %39 = load i32, ptr %8, align 4, !tbaa !9
  %40 = sext i32 %39 to i64
  invoke void @_ZNSt6vectorIP10CUevent_stSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %40)
          to label %41 unwind label %31

41:                                               ; preds = %35
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %42

42:                                               ; preds = %57, %41
  %43 = load i32, ptr %14, align 4, !tbaa !9
  %44 = load i32, ptr %8, align 4, !tbaa !9
  %45 = icmp slt i32 %43, %44
  br i1 %45, label %47, label %46

46:                                               ; preds = %42
  store i32 5, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  br label %64

47:                                               ; preds = %42
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = invoke noundef ptr @_ZN4dali9EventPool8GetEventEv(ptr noundef nonnull align 8 dereferenceable(24) %48)
          to label %50 unwind label %60

50:                                               ; preds = %47
  %51 = load i32, ptr %12, align 4, !tbaa !9
  %52 = sext i32 %51 to i64
  %53 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %52) #4
  %54 = load i32, ptr %14, align 4, !tbaa !9
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10CUevent_stSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %55) #4
  store ptr %49, ptr %56, align 8, !tbaa !5
  br label %57

57:                                               ; preds = %50
  %58 = load i32, ptr %14, align 4, !tbaa !9
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %14, align 4, !tbaa !9
  br label %42, !llvm.loop !11

60:                                               ; preds = %47
  %61 = landingpad { ptr, i32 }
          cleanup
  %62 = extractvalue { ptr, i32 } %61, 0
  store ptr %62, ptr %10, align 8
  %63 = extractvalue { ptr, i32 } %61, 1
  store i32 %63, ptr %11, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  br label %68

64:                                               ; preds = %46
  br label %65

65:                                               ; preds = %64
  %66 = load i32, ptr %12, align 4, !tbaa !9
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %12, align 4, !tbaa !9
  br label %19, !llvm.loop !13

68:                                               ; preds = %60, %31
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  br label %73

69:                                               ; preds = %26
  store i1 true, ptr %9, align 1
  store i32 1, ptr %13, align 4
  %70 = load i1, ptr %9, align 1
  br i1 %70, label %72, label %71

71:                                               ; preds = %69
  call void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %72

72:                                               ; preds = %71, %69
  ret void

73:                                               ; preds = %68, %27
  call void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %74

74:                                               ; preds = %73
  %75 = load ptr, ptr %10, align 8
  %76 = load i32, ptr %11, align 4
  %77 = insertvalue { ptr, i32 } poison, ptr %75, 0
  %78 = insertvalue { ptr, i32 } %77, i32 %76, 1
  resume { ptr, i32 } %78
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217), i32 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP10CUevent_stSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN4dali9EventPool8GetEventEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10CUevent_stSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.108" = type { %"struct.std::_Vector_base.109" }
%"struct.std::_Vector_base.109" = type { %"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<CUevent_st *>, std::allocator<std::vector<CUevent_st *>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4dali23CreateEventsForMixedOpsERNS_9EventPoolERKNS_7OpGraphEi(ptr dead_on_unwind noalias nonnull writable sret(%"class.std::vector.108") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef %3) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  tail call void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %5 = tail call noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef 2)
  invoke void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %5)
          to label %.preheader21 unwind label %19

.preheader21:                                     ; preds = %4
  %6 = tail call noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef 2)
  %7 = icmp sgt i64 %6, 0
  br i1 %7, label %.lr.ph24, label %._crit_edge25

.lr.ph24:                                         ; preds = %.preheader21
  %8 = sext i32 %3 to i64
  %9 = icmp sgt i32 %3, 0
  br i1 %9, label %.lr.ph24.split.us.preheader, label %.lr.ph24.split

.lr.ph24.split.us.preheader:                      ; preds = %.lr.ph24
  %wide.trip.count = zext nneg i32 %3 to i64
  br label %.lr.ph24.split.us

.lr.ph24.split.us:                                ; preds = %.lr.ph24.split.us.preheader, %._crit_edge.us
  %indvars.iv34 = phi i64 [ 0, %.lr.ph24.split.us.preheader ], [ %indvars.iv.next35, %._crit_edge.us ]
  %10 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv34) #3
  invoke void @_ZNSt6vectorIP10CUevent_stSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %8)
          to label %.preheader.us unwind label %.split.us

.preheader.us:                                    ; preds = %.lr.ph24.split.us, %12
  %indvars.iv31 = phi i64 [ %indvars.iv.next32, %12 ], [ 0, %.lr.ph24.split.us ]
  %11 = invoke noundef ptr @_ZN4dali9EventPool8GetEventEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
          to label %12 unwind label %.split27.us

12:                                               ; preds = %.preheader.us
  %13 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv34) #3
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10CUevent_stSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %indvars.iv31) #3
  store ptr %11, ptr %14, align 8, !tbaa !5
  %indvars.iv.next32 = add nuw nsw i64 %indvars.iv31, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next32, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge.us, label %.preheader.us, !llvm.loop !9

._crit_edge.us:                                   ; preds = %12
  %indvars.iv.next35 = add nuw nsw i64 %indvars.iv34, 1
  %15 = tail call noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef 2)
  %16 = icmp sgt i64 %15, %indvars.iv.next35
  br i1 %16, label %.lr.ph24.split.us, label %._crit_edge25, !llvm.loop !11

.split.us:                                        ; preds = %.lr.ph24.split.us
  %17 = landingpad { ptr, i32 }
          cleanup
  br label %25

.split27.us:                                      ; preds = %.preheader.us
  %18 = landingpad { ptr, i32 }
          cleanup
  br label %25

19:                                               ; preds = %4
  %20 = landingpad { ptr, i32 }
          cleanup
  br label %25

.split:                                           ; preds = %.lr.ph24.split
  %21 = landingpad { ptr, i32 }
          cleanup
  br label %25

.lr.ph24.split:                                   ; preds = %.lr.ph24, %.preheader
  %indvars.iv = phi i64 [ %indvars.iv.next, %.preheader ], [ 0, %.lr.ph24 ]
  %22 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #3
  invoke void @_ZNSt6vectorIP10CUevent_stSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %8)
          to label %.preheader unwind label %.split

.preheader:                                       ; preds = %.lr.ph24.split
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %23 = tail call noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217) %2, i32 noundef 2)
  %24 = icmp sgt i64 %23, %indvars.iv.next
  br i1 %24, label %.lr.ph24.split, label %._crit_edge25, !llvm.loop !11

._crit_edge25:                                    ; preds = %.preheader, %._crit_edge.us, %.preheader21
  ret void

25:                                               ; preds = %.split, %.split.us, %.split27.us, %19
  %.pn.pn = phi { ptr, i32 } [ %20, %19 ], [ %18, %.split27.us ], [ %21, %.split ], [ %17, %.split.us ]
  tail call void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  resume { ptr, i32 } %.pn.pn
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK4dali7OpGraph5NumOpENS_6OpTypeE(ptr noundef nonnull align 8 dereferenceable(217), i32 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIP10CUevent_stSaIS1_EE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZN4dali9EventPool8GetEventEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10CUevent_stSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIS_IP10CUevent_stSaIS1_EESaIS3_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass