; LLVM IR from kazunetakahashi/atcoder :: 2019/0915_ABC141/past/F.ll (Z9make_maxiRSt6vectorIxSaIxEEx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z9make_maxiRSt6vectorIxSaIxEEx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i64 %1, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = call noundef i64 @_ZNKSt6vectorIxSaIxEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  %17 = trunc i64 %16 to i32
  store i32 %17, ptr %5, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %18 = load i64, ptr %4, align 8, !tbaa !9
  %19 = sub nsw i64 2305843009213693951, %18
  store i64 %19, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store i64 0, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 61, ptr %9, align 4, !tbaa !11
  br label %20

20:                                               ; preds = %111, %2
  %21 = load i32, ptr %9, align 4, !tbaa !11
  %22 = icmp sge i32 %21, 0
  br i1 %22, label %24, label %23

23:                                               ; preds = %20
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %114

24:                                               ; preds = %20
  %25 = load i64, ptr %6, align 8, !tbaa !9
  %26 = load i32, ptr %9, align 4, !tbaa !11
  %27 = zext i32 %26 to i64
  %28 = ashr i64 %25, %27
  %29 = and i64 %28, 1
  %30 = icmp ne i64 %29, 0
  br i1 %30, label %31, label %110

31:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #3
  store i8 0, ptr %11, align 1, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %32 = load i32, ptr %8, align 4, !tbaa !11
  store i32 %32, ptr %12, align 4, !tbaa !11
  br label %33

33:                                               ; preds = %59, %31
  %34 = load i32, ptr %12, align 4, !tbaa !11
  %35 = load i32, ptr %5, align 4, !tbaa !11
  %36 = icmp slt i32 %34, %35
  br i1 %36, label %38, label %37

37:                                               ; preds = %33
  store i32 5, ptr %10, align 4
  br label %62

38:                                               ; preds = %33
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = load i32, ptr %12, align 4, !tbaa !11
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %41) #3
  %43 = load i64, ptr %42, align 8, !tbaa !9
  %44 = load i32, ptr %9, align 4, !tbaa !11
  %45 = zext i32 %44 to i64
  %46 = ashr i64 %43, %45
  %47 = and i64 %46, 1
  %48 = icmp ne i64 %47, 0
  br i1 %48, label %49, label %58

49:                                               ; preds = %38
  %50 = load ptr, ptr %3, align 8, !tbaa !5
  %51 = load i32, ptr %12, align 4, !tbaa !11
  %52 = sext i32 %51 to i64
  %53 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %52) #3
  %54 = load ptr, ptr %3, align 8, !tbaa !5
  %55 = load i32, ptr %8, align 4, !tbaa !11
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %54, i64 noundef %56) #3
  call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %53, ptr noundef nonnull align 8 dereferenceable(8) %57) #3
  store i8 1, ptr %11, align 1, !tbaa !13
  store i32 5, ptr %10, align 4
  br label %62

58:                                               ; preds = %38
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr %12, align 4, !tbaa !11
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %12, align 4, !tbaa !11
  br label %33, !llvm.loop !15

62:                                               ; preds = %49, %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %63

63:                                               ; preds = %62
  %64 = load i8, ptr %11, align 1, !tbaa !13, !range !17, !noundef !18
  %65 = trunc i8 %64 to i1
  br i1 %65, label %67, label %66

66:                                               ; preds = %63
  store i32 4, ptr %10, align 4
  br label %107

67:                                               ; preds = %63
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !11
  br label %68

68:                                               ; preds = %101, %67
  %69 = load i32, ptr %13, align 4, !tbaa !11
  %70 = load i32, ptr %5, align 4, !tbaa !11
  %71 = icmp slt i32 %69, %70
  br i1 %71, label %73, label %72

72:                                               ; preds = %68
  store i32 8, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  br label %104

73:                                               ; preds = %68
  %74 = load i32, ptr %13, align 4, !tbaa !11
  %75 = load i32, ptr %8, align 4, !tbaa !11
  %76 = icmp ne i32 %74, %75
  br i1 %76, label %77, label %100

77:                                               ; preds = %73
  %78 = load ptr, ptr %3, align 8, !tbaa !5
  %79 = load i32, ptr %13, align 4, !tbaa !11
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %80) #3
  %82 = load i64, ptr %81, align 8, !tbaa !9
  %83 = load i32, ptr %9, align 4, !tbaa !11
  %84 = zext i32 %83 to i64
  %85 = ashr i64 %82, %84
  %86 = and i64 %85, 1
  %87 = icmp ne i64 %86, 0
  br i1 %87, label %88, label %100

88:                                               ; preds = %77
  %89 = load ptr, ptr %3, align 8, !tbaa !5
  %90 = load i32, ptr %8, align 4, !tbaa !11
  %91 = sext i32 %90 to i64
  %92 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %89, i64 noundef %91) #3
  %93 = load i64, ptr %92, align 8, !tbaa !9
  %94 = load ptr, ptr %3, align 8, !tbaa !5
  %95 = load i32, ptr %13, align 4, !tbaa !11
  %96 = sext i32 %95 to i64
  %97 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %94, i64 noundef %96) #3
  %98 = load i64, ptr %97, align 8, !tbaa !9
  %99 = xor i64 %98, %93
  store i64 %99, ptr %97, align 8, !tbaa !9
  br label %100

100:                                              ; preds = %88, %77, %73
  br label %101

101:                                              ; preds = %100
  %102 = load i32, ptr %13, align 4, !tbaa !11
  %103 = add nsw i32 %102, 1
  store i32 %103, ptr %13, align 4, !tbaa !11
  br label %68, !llvm.loop !19

104:                                              ; preds = %72
  %105 = load i32, ptr %8, align 4, !tbaa !11
  %106 = add nsw i32 %105, 1
  store i32 %106, ptr %8, align 4, !tbaa !11
  store i32 0, ptr %10, align 4
  br label %107

107:                                              ; preds = %104, %66
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #3
  %108 = load i32, ptr %10, align 4
  switch i32 %108, label %135 [
    i32 0, label %109
    i32 4, label %111
  ]

109:                                              ; preds = %107
  br label %110

110:                                              ; preds = %109, %24
  br label %111

111:                                              ; preds = %110, %107
  %112 = load i32, ptr %9, align 4, !tbaa !11
  %113 = add nsw i32 %112, -1
  store i32 %113, ptr %9, align 4, !tbaa !11
  br label %20, !llvm.loop !20

114:                                              ; preds = %23
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  store i32 0, ptr %14, align 4, !tbaa !11
  br label %115

115:                                              ; preds = %128, %114
  %116 = load i32, ptr %14, align 4, !tbaa !11
  %117 = load i32, ptr %8, align 4, !tbaa !11
  %118 = icmp slt i32 %116, %117
  br i1 %118, label %120, label %119

119:                                              ; preds = %115
  store i32 11, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  br label %131

120:                                              ; preds = %115
  %121 = load ptr, ptr %3, align 8, !tbaa !5
  %122 = load i32, ptr %14, align 4, !tbaa !11
  %123 = sext i32 %122 to i64
  %124 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %121, i64 noundef %123) #3
  %125 = load i64, ptr %124, align 8, !tbaa !9
  %126 = load i64, ptr %7, align 8, !tbaa !9
  %127 = xor i64 %126, %125
  store i64 %127, ptr %7, align 8, !tbaa !9
  br label %128

128:                                              ; preds = %120
  %129 = load i32, ptr %14, align 4, !tbaa !11
  %130 = add nsw i32 %129, 1
  store i32 %130, ptr %14, align 4, !tbaa !11
  br label %115, !llvm.loop !21

131:                                              ; preds = %119
  %132 = load i64, ptr %7, align 8, !tbaa !9
  %133 = load i64, ptr %6, align 8, !tbaa !9
  %134 = and i64 %132, %133
  store i32 1, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i64 %134

135:                                              ; preds = %107
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIxSaIxEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"bool", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = distinct !{!19, !16}
!20 = distinct !{!20, !16}
!21 = distinct !{!21, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z9make_maxiRSt6vectorIxSaIxEEx(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1) local_unnamed_addr #0 {
  %3 = tail call noundef i64 @_ZNKSt6vectorIxSaIxEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %4 = trunc i64 %3 to i32
  %5 = sub nsw i64 2305843009213693951, %1
  %6 = icmp sgt i32 %4, 0
  br i1 %6, label %.split.us.preheader, label %.split.preheader

.split.preheader:                                 ; preds = %2
  %sext = shl i64 %3, 32
  %wide.trip.count = ashr exact i64 %sext, 32
  br label %.split

.split.us.preheader:                              ; preds = %2
  %wide.trip.count69 = and i64 %3, 2147483647
  %wide.trip.count74 = and i64 %3, 2147483647
  br label %.split.us

.split.us:                                        ; preds = %.split.us.preheader, %.critedge.us
  %indvars.iv76 = phi i64 [ 61, %.split.us.preheader ], [ %indvars.iv.next77, %.critedge.us ]
  %.04251.us = phi i32 [ 0, %.split.us.preheader ], [ %.2.us, %.critedge.us ]
  %7 = shl nuw i64 1, %indvars.iv76
  %8 = and i64 %7, %5
  %.not.us = icmp ne i64 %8, 0
  %9 = icmp slt i32 %.04251.us, %4
  %or.cond = select i1 %.not.us, i1 %9, i1 false
  br i1 %or.cond, label %.lr.ph.us.preheader, label %.critedge.us

.lr.ph.us.preheader:                              ; preds = %.split.us
  %10 = sext i32 %.04251.us to i64
  br label %.lr.ph.us

11:                                               ; preds = %.lr.ph.us
  %indvars.iv.next67 = add nsw i64 %indvars.iv66, 1
  %exitcond70.not = icmp eq i64 %indvars.iv.next67, %wide.trip.count69
  br i1 %exitcond70.not, label %.critedge.us, label %.lr.ph.us, !llvm.loop !5

.lr.ph.us:                                        ; preds = %.lr.ph.us.preheader, %11
  %indvars.iv66 = phi i64 [ %10, %.lr.ph.us.preheader ], [ %indvars.iv.next67, %11 ]
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv66) #2
  %13 = load i64, ptr %12, align 8, !tbaa !7
  %14 = and i64 %13, %7
  %.not44.us = icmp eq i64 %14, 0
  br i1 %.not44.us, label %11, label %.lr.ph50.us

.lr.ph50.us:                                      ; preds = %.lr.ph.us
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv66) #2
  %16 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %10) #2
  tail call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %15, ptr noundef nonnull align 8 dereferenceable(8) %16) #2
  %17 = zext i32 %.04251.us to i64
  br label %18

18:                                               ; preds = %.lr.ph50.us, %29
  %indvars.iv71 = phi i64 [ 0, %.lr.ph50.us ], [ %indvars.iv.next72, %29 ]
  %.not45.us = icmp eq i64 %indvars.iv71, %17
  br i1 %.not45.us, label %29, label %19

19:                                               ; preds = %18
  %20 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv71) #2
  %21 = load i64, ptr %20, align 8, !tbaa !7
  %22 = and i64 %21, %7
  %.not46.us = icmp eq i64 %22, 0
  br i1 %.not46.us, label %29, label %23

23:                                               ; preds = %19
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %10) #2
  %25 = load i64, ptr %24, align 8, !tbaa !7
  %26 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv71) #2
  %27 = load i64, ptr %26, align 8, !tbaa !7
  %28 = xor i64 %27, %25
  store i64 %28, ptr %26, align 8, !tbaa !7
  br label %29

29:                                               ; preds = %23, %19, %18
  %indvars.iv.next72 = add nuw nsw i64 %indvars.iv71, 1
  %exitcond75.not = icmp eq i64 %indvars.iv.next72, %wide.trip.count74
  br i1 %exitcond75.not, label %._crit_edge.us, label %18, !llvm.loop !11

.critedge.us:                                     ; preds = %11, %._crit_edge.us, %.split.us
  %.2.us = phi i32 [ %.04251.us, %.split.us ], [ %30, %._crit_edge.us ], [ %.04251.us, %11 ]
  %indvars.iv.next77 = add nsw i64 %indvars.iv76, -1
  %.not85 = icmp eq i64 %indvars.iv76, 0
  br i1 %.not85, label %.preheader, label %.split.us, !llvm.loop !12

._crit_edge.us:                                   ; preds = %29
  %30 = add nsw i32 %.04251.us, 1
  br label %.critedge.us

.preheader:                                       ; preds = %.critedge, %.critedge.us
  %.us-phi = phi i32 [ %.2.us, %.critedge.us ], [ %.2, %.critedge ]
  %31 = icmp sgt i32 %.us-phi, 0
  br i1 %31, label %.lr.ph55.preheader, label %._crit_edge

.lr.ph55.preheader:                               ; preds = %.preheader
  %wide.trip.count82 = zext nneg i32 %.us-phi to i64
  br label %.lr.ph55

.split:                                           ; preds = %.split.preheader, %.critedge
  %indvars.iv63 = phi i64 [ 61, %.split.preheader ], [ %indvars.iv.next64, %.critedge ]
  %.04251 = phi i32 [ 0, %.split.preheader ], [ %.2, %.critedge ]
  %32 = shl nuw i64 1, %indvars.iv63
  %33 = and i64 %32, %5
  %.not = icmp ne i64 %33, 0
  %34 = icmp slt i32 %.04251, %4
  %or.cond56 = select i1 %.not, i1 %34, i1 false
  br i1 %or.cond56, label %.lr.ph.preheader, label %.critedge

.lr.ph.preheader:                                 ; preds = %.split
  %35 = sext i32 %.04251 to i64
  br label %.lr.ph

36:                                               ; preds = %.lr.ph
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.critedge, label %.lr.ph, !llvm.loop !5

.lr.ph:                                           ; preds = %.lr.ph.preheader, %36
  %indvars.iv = phi i64 [ %35, %.lr.ph.preheader ], [ %indvars.iv.next, %36 ]
  %37 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #2
  %38 = load i64, ptr %37, align 8, !tbaa !7
  %39 = and i64 %38, %32
  %.not44 = icmp eq i64 %39, 0
  br i1 %.not44, label %36, label %40

40:                                               ; preds = %.lr.ph
  %41 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #2
  %42 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %35) #2
  tail call void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8) %41, ptr noundef nonnull align 8 dereferenceable(8) %42) #2
  %43 = add nsw i32 %.04251, 1
  br label %.critedge

.critedge:                                        ; preds = %36, %40, %.split
  %.2 = phi i32 [ %.04251, %.split ], [ %43, %40 ], [ %.04251, %36 ]
  %indvars.iv.next64 = add nsw i64 %indvars.iv63, -1
  %.not84 = icmp eq i64 %indvars.iv63, 0
  br i1 %.not84, label %.preheader, label %.split, !llvm.loop !12

._crit_edge:                                      ; preds = %.lr.ph55, %.preheader
  %.043.lcssa = phi i64 [ 0, %.preheader ], [ %47, %.lr.ph55 ]
  %44 = and i64 %.043.lcssa, %5
  ret i64 %44

.lr.ph55:                                         ; preds = %.lr.ph55.preheader, %.lr.ph55
  %indvars.iv79 = phi i64 [ 0, %.lr.ph55.preheader ], [ %indvars.iv.next80, %.lr.ph55 ]
  %.04353 = phi i64 [ 0, %.lr.ph55.preheader ], [ %47, %.lr.ph55 ]
  %45 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv79) #2
  %46 = load i64, ptr %45, align 8, !tbaa !7
  %47 = xor i64 %46, %.04353
  %indvars.iv.next80 = add nuw nsw i64 %indvars.iv79, 1
  %exitcond83.not = icmp eq i64 %indvars.iv.next80, %wide.trip.count82
  br i1 %exitcond83.not, label %._crit_edge, label %.lr.ph55, !llvm.loop !13
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIxSaIxEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIxENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"long long", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = distinct !{!11, !6}
!12 = distinct !{!12, !6}
!13 = distinct !{!13, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass