; LLVM IR from libxsmm/libxsmm :: src (generator_mateltwise_unary_binary_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_asimd(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6, ptr noundef %7) #1 {
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i8, align 1
  %13 = alloca i8, align 1
  %14 = alloca i8, align 1
  %15 = alloca i8, align 1
  %16 = alloca ptr, align 8
  store ptr %0, ptr %9, align 8, !tbaa !5
  store i32 %1, ptr %10, align 4, !tbaa !9
  store i32 %2, ptr %11, align 4, !tbaa !9
  store i8 %3, ptr %12, align 1, !tbaa !11
  store i8 %4, ptr %13, align 1, !tbaa !11
  store i8 %5, ptr %14, align 1, !tbaa !11
  store i8 %6, ptr %15, align 1, !tbaa !11
  store ptr %7, ptr %16, align 8, !tbaa !5
  %17 = load i32, ptr %10, align 4, !tbaa !9
  %18 = urem i32 %17, 2
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %56

20:                                               ; preds = %8
  %21 = load i32, ptr %10, align 4, !tbaa !9
  %22 = load i32, ptr %11, align 4, !tbaa !9
  %23 = sub i32 %22, 1
  %24 = icmp eq i32 %21, %23
  br i1 %24, label %25, label %35

25:                                               ; preds = %20
  %26 = load ptr, ptr %9, align 8, !tbaa !5
  %27 = load i8, ptr %15, align 1, !tbaa !11
  %28 = zext i8 %27 to i32
  %29 = load i8, ptr %14, align 1, !tbaa !11
  %30 = zext i8 %29 to i32
  call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %26, i32 noundef 230735875, i32 noundef %28, i32 noundef 63, i32 noundef %30, i32 noundef 1)
  %31 = load ptr, ptr %16, align 8, !tbaa !5
  %32 = getelementptr inbounds i32, ptr %31, i64 0
  %33 = load i32, ptr %32, align 4, !tbaa !9
  %34 = add i32 %33, 1
  store i32 %34, ptr %32, align 4, !tbaa !9
  br label %41

35:                                               ; preds = %20
  %36 = load ptr, ptr %9, align 8, !tbaa !5
  %37 = load i8, ptr %15, align 1, !tbaa !11
  %38 = zext i8 %37 to i32
  %39 = load i8, ptr %14, align 1, !tbaa !11
  %40 = zext i8 %39 to i32
  call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %36, i32 noundef 222347266, i32 noundef %38, i32 noundef 127, i32 noundef %40, i32 noundef 1)
  br label %41

41:                                               ; preds = %35, %25
  %42 = load ptr, ptr %9, align 8, !tbaa !5
  %43 = load i8, ptr %14, align 1, !tbaa !11
  %44 = zext i8 %43 to i32
  %45 = load i8, ptr %12, align 1, !tbaa !11
  %46 = zext i8 %45 to i32
  %47 = load i8, ptr %14, align 1, !tbaa !11
  %48 = zext i8 %47 to i32
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %42, i32 noundef 236985363, i32 noundef %44, i32 noundef %46, i8 noundef zeroext 0, i32 noundef %48, i32 noundef 1)
  %49 = load ptr, ptr %9, align 8, !tbaa !5
  %50 = load i8, ptr %14, align 1, !tbaa !11
  %51 = zext i8 %50 to i32
  %52 = load i8, ptr %12, align 1, !tbaa !11
  %53 = zext i8 %52 to i32
  %54 = load i8, ptr %14, align 1, !tbaa !11
  %55 = zext i8 %54 to i32
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %49, i32 noundef 773884931, i32 noundef %51, i32 noundef %53, i8 noundef zeroext 0, i32 noundef %55, i32 noundef 5)
  br label %80

56:                                               ; preds = %8
  %57 = load ptr, ptr %9, align 8, !tbaa !5
  %58 = load i8, ptr %15, align 1, !tbaa !11
  %59 = zext i8 %58 to i32
  %60 = load i8, ptr %14, align 1, !tbaa !11
  %61 = zext i8 %60 to i32
  call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %57, i32 noundef 230735875, i32 noundef %59, i32 noundef 63, i32 noundef %61, i32 noundef 1)
  %62 = load ptr, ptr %16, align 8, !tbaa !5
  %63 = getelementptr inbounds i32, ptr %62, i64 0
  %64 = load i32, ptr %63, align 4, !tbaa !9
  %65 = add i32 %64, 1
  store i32 %65, ptr %63, align 4, !tbaa !9
  %66 = load ptr, ptr %9, align 8, !tbaa !5
  %67 = load i8, ptr %14, align 1, !tbaa !11
  %68 = zext i8 %67 to i32
  %69 = load i8, ptr %13, align 1, !tbaa !11
  %70 = zext i8 %69 to i32
  %71 = load i8, ptr %14, align 1, !tbaa !11
  %72 = zext i8 %71 to i32
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %66, i32 noundef 236985363, i32 noundef %68, i32 noundef %70, i8 noundef zeroext 0, i32 noundef %72, i32 noundef 1)
  %73 = load ptr, ptr %9, align 8, !tbaa !5
  %74 = load i8, ptr %14, align 1, !tbaa !11
  %75 = zext i8 %74 to i32
  %76 = load i8, ptr %13, align 1, !tbaa !11
  %77 = zext i8 %76 to i32
  %78 = load i8, ptr %14, align 1, !tbaa !11
  %79 = zext i8 %78 to i32
  call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %73, i32 noundef 773884931, i32 noundef %75, i32 noundef %77, i8 noundef zeroext 0, i32 noundef %79, i32 noundef 5)
  br label %80

80:                                               ; preds = %56, %41
  ret void
}

declare void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_unary_binary_aarch64_load_bitmask_2bytemult_asimd(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6, ptr nocapture noundef %7) local_unnamed_addr #1 {
  %9 = and i32 %1, 1
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %11, label %22

11:                                               ; preds = %8
  %12 = add i32 %2, -1
  %13 = icmp eq i32 %12, %1
  %14 = zext i8 %6 to i32
  %15 = zext i8 %5 to i32
  br i1 %13, label %16, label %19

16:                                               ; preds = %11
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef 230735875, i32 noundef %14, i32 noundef 63, i32 noundef %15, i32 noundef 1) #2
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = add i32 %17, 1
  store i32 %18, ptr %7, align 4, !tbaa !5
  br label %20

19:                                               ; preds = %11
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef 222347266, i32 noundef %14, i32 noundef 127, i32 noundef %15, i32 noundef 1) #2
  br label %20

20:                                               ; preds = %19, %16
  %21 = zext i8 %3 to i32
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 236985363, i32 noundef %15, i32 noundef %21, i8 noundef zeroext 0, i32 noundef %15, i32 noundef 1) #2
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773884931, i32 noundef %15, i32 noundef %21, i8 noundef zeroext 0, i32 noundef %15, i32 noundef 5) #2
  br label %28

22:                                               ; preds = %8
  %23 = zext i8 %6 to i32
  %24 = zext i8 %5 to i32
  tail call void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef %0, i32 noundef 230735875, i32 noundef %23, i32 noundef 63, i32 noundef %24, i32 noundef 1) #2
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = add i32 %25, 1
  store i32 %26, ptr %7, align 4, !tbaa !5
  %27 = zext i8 %4 to i32
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 236985363, i32 noundef %24, i32 noundef %27, i8 noundef zeroext 0, i32 noundef %24, i32 noundef 1) #2
  tail call void @libxsmm_aarch64_instruction_asimd_compute(ptr noundef %0, i32 noundef 773884931, i32 noundef %24, i32 noundef %27, i8 noundef zeroext 0, i32 noundef %24, i32 noundef 5) #2
  br label %28

28:                                               ; preds = %22, %20
  ret void
}

declare void @libxsmm_aarch64_instruction_asimd_struct_r_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass