; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_32x32_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5) #2 {
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store i32 %2, ptr %9, align 4, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i32 %4, ptr %11, align 4, !tbaa !9
  store i32 %5, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %19 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %19, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  store i32 0, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  store i32 0, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #3
  store i32 0, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #3
  store i32 0, ptr %17, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #3
  %20 = load i32, ptr %11, align 4, !tbaa !9
  %21 = icmp ule i32 %20, 16
  %22 = zext i1 %21 to i64
  %23 = select i1 %21, i32 1, i32 2
  store i32 %23, ptr %18, align 4, !tbaa !9
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %24, i32 noundef 4)
  %25 = load ptr, ptr %7, align 8, !tbaa !5
  %26 = load i32, ptr %10, align 4, !tbaa !9
  %27 = mul i32 %26, 4
  call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %25, i32 noundef 8, i32 noundef %27, i32 noundef 43, i32 noundef 0)
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %28

28:                                               ; preds = %155, %6
  %29 = load i32, ptr %14, align 4, !tbaa !9
  %30 = load i32, ptr %18, align 4, !tbaa !9
  %31 = icmp ult i32 %29, %30
  br i1 %31, label %32, label %158

32:                                               ; preds = %28
  store i32 0, ptr %15, align 4, !tbaa !9
  br label %33

33:                                               ; preds = %81, %32
  %34 = load i32, ptr %15, align 4, !tbaa !9
  %35 = load i32, ptr %13, align 4, !tbaa !9
  %36 = icmp ugt i32 %35, 16
  br i1 %36, label %37, label %38

37:                                               ; preds = %33
  br label %40

38:                                               ; preds = %33
  %39 = load i32, ptr %13, align 4, !tbaa !9
  br label %40

40:                                               ; preds = %38, %37
  %41 = phi i32 [ 16, %37 ], [ %39, %38 ]
  %42 = icmp ult i32 %34, %41
  br i1 %42, label %43, label %84

43:                                               ; preds = %40
  %44 = load i32, ptr %15, align 4, !tbaa !9
  %45 = icmp ult i32 %44, 8
  br i1 %45, label %46, label %47

46:                                               ; preds = %43
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %48

47:                                               ; preds = %43
  store i32 8, ptr %16, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %47, %46
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = load i32, ptr %15, align 4, !tbaa !9
  %51 = load i32, ptr %16, align 4, !tbaa !9
  %52 = add i32 %50, %51
  %53 = load i32, ptr %14, align 4, !tbaa !9
  %54 = icmp eq i32 %53, 0
  br i1 %54, label %55, label %57

55:                                               ; preds = %48
  %56 = load i32, ptr %8, align 4, !tbaa !9
  br label %59

57:                                               ; preds = %48
  %58 = load i32, ptr %9, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %57, %55
  %60 = phi i32 [ %56, %55 ], [ %58, %57 ]
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %49, i32 noundef -1589624832, i32 noundef %52, i32 noundef %60, i32 noundef 0, i32 noundef 8)
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = load i32, ptr %14, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 0
  br i1 %63, label %64, label %66

64:                                               ; preds = %59
  %65 = load i32, ptr %8, align 4, !tbaa !9
  br label %68

66:                                               ; preds = %59
  %67 = load i32, ptr %9, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %66, %64
  %69 = phi i32 [ %65, %64 ], [ %67, %66 ]
  %70 = load i32, ptr %14, align 4, !tbaa !9
  %71 = icmp eq i32 %70, 0
  br i1 %71, label %72, label %74

72:                                               ; preds = %68
  %73 = load i32, ptr %8, align 4, !tbaa !9
  br label %76

74:                                               ; preds = %68
  %75 = load i32, ptr %9, align 4, !tbaa !9
  br label %76

76:                                               ; preds = %74, %72
  %77 = phi i32 [ %73, %72 ], [ %75, %74 ]
  %78 = load i32, ptr %12, align 4, !tbaa !9
  %79 = mul i32 %78, 4
  %80 = zext i32 %79 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %61, i32 noundef 4096, i32 noundef %69, i32 noundef 43, i32 noundef %77, i64 noundef %80)
  br label %81

81:                                               ; preds = %76
  %82 = load i32, ptr %15, align 4, !tbaa !9
  %83 = add i32 %82, 1
  store i32 %83, ptr %15, align 4, !tbaa !9
  br label %33, !llvm.loop !11

84:                                               ; preds = %40
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %85

85:                                               ; preds = %113, %84
  %86 = load i32, ptr %17, align 4, !tbaa !9
  %87 = icmp ult i32 %86, 4
  br i1 %87, label %88, label %116

88:                                               ; preds = %85
  %89 = load ptr, ptr %7, align 8, !tbaa !5
  %90 = load i32, ptr %14, align 4, !tbaa !9
  %91 = mul i32 %90, 2
  %92 = load i32, ptr %14, align 4, !tbaa !9
  %93 = mul i32 2, %92
  %94 = add i32 12, %93
  %95 = load i32, ptr %17, align 4, !tbaa !9
  %96 = icmp ult i32 %95, 2
  br i1 %96, label %97, label %100

97:                                               ; preds = %88
  %98 = load i32, ptr %17, align 4, !tbaa !9
  %99 = add i32 0, %98
  br label %104

100:                                              ; preds = %88
  %101 = load i32, ptr %17, align 4, !tbaa !9
  %102 = add i32 0, %101
  %103 = add i32 %102, 2
  br label %104

104:                                              ; preds = %100, %97
  %105 = phi i32 [ %99, %97 ], [ %103, %100 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %89, i32 noundef -1065090048, i32 noundef %91, i32 noundef %94, i32 noundef %105)
  %106 = load ptr, ptr %7, align 8, !tbaa !5
  %107 = load i32, ptr %14, align 4, !tbaa !9
  %108 = mul i32 2, %107
  %109 = add i32 12, %108
  %110 = load i32, ptr %14, align 4, !tbaa !9
  %111 = mul i32 2, %110
  %112 = add i32 12, %111
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %106, i32 noundef 285212678, i32 noundef %109, i32 noundef %112, i32 noundef 4, i8 noundef zeroext 0)
  br label %113

113:                                              ; preds = %104
  %114 = load i32, ptr %17, align 4, !tbaa !9
  %115 = add i32 %114, 1
  store i32 %115, ptr %17, align 4, !tbaa !9
  br label %85, !llvm.loop !13

116:                                              ; preds = %85
  %117 = load i32, ptr %10, align 4, !tbaa !9
  %118 = icmp ugt i32 %117, 16
  br i1 %118, label %119, label %152

119:                                              ; preds = %116
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %120

120:                                              ; preds = %148, %119
  %121 = load i32, ptr %17, align 4, !tbaa !9
  %122 = icmp ult i32 %121, 4
  br i1 %122, label %123, label %151

123:                                              ; preds = %120
  %124 = load ptr, ptr %7, align 8, !tbaa !5
  %125 = load i32, ptr %14, align 4, !tbaa !9
  %126 = mul i32 %125, 2
  %127 = add i32 1, %126
  %128 = load i32, ptr %14, align 4, !tbaa !9
  %129 = mul i32 2, %128
  %130 = add i32 13, %129
  %131 = load i32, ptr %17, align 4, !tbaa !9
  %132 = icmp ult i32 %131, 2
  br i1 %132, label %133, label %136

133:                                              ; preds = %123
  %134 = load i32, ptr %17, align 4, !tbaa !9
  %135 = add i32 %134, 2
  br label %139

136:                                              ; preds = %123
  %137 = load i32, ptr %17, align 4, !tbaa !9
  %138 = add i32 %137, 4
  br label %139

139:                                              ; preds = %136, %133
  %140 = phi i32 [ %135, %133 ], [ %138, %136 ]
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %124, i32 noundef -1065090048, i32 noundef %127, i32 noundef %130, i32 noundef %140)
  %141 = load ptr, ptr %7, align 8, !tbaa !5
  %142 = load i32, ptr %14, align 4, !tbaa !9
  %143 = mul i32 2, %142
  %144 = add i32 13, %143
  %145 = load i32, ptr %14, align 4, !tbaa !9
  %146 = mul i32 2, %145
  %147 = add i32 13, %146
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %141, i32 noundef 285212678, i32 noundef %144, i32 noundef %147, i32 noundef 4, i8 noundef zeroext 0)
  br label %148

148:                                              ; preds = %139
  %149 = load i32, ptr %17, align 4, !tbaa !9
  %150 = add i32 %149, 1
  store i32 %150, ptr %17, align 4, !tbaa !9
  br label %120, !llvm.loop !14

151:                                              ; preds = %120
  br label %152

152:                                              ; preds = %151, %116
  %153 = load i32, ptr %13, align 4, !tbaa !9
  %154 = sub i32 %153, 16
  store i32 %154, ptr %13, align 4, !tbaa !9
  br label %155

155:                                              ; preds = %152
  %156 = load i32, ptr %14, align 4, !tbaa !9
  %157 = add i32 %156, 1
  store i32 %157, ptr %14, align 4, !tbaa !9
  br label %28, !llvm.loop !15

158:                                              ; preds = %28
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  ret void
}

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_load_32x32_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5) local_unnamed_addr #1 {
  %7 = icmp ugt i32 %4, 16
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef 4)
  %8 = shl i32 %3, 2
  tail call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %0, i32 noundef 8, i32 noundef %8, i32 noundef 43, i32 noundef 0)
  %9 = shl i32 %5, 2
  %10 = zext i32 %9 to i64
  %11 = icmp ugt i32 %3, 16
  br label %.preheader55

.preheader55:                                     ; preds = %6, %.loopexit
  %.060 = phi i32 [ %4, %6 ], [ %20, %.loopexit ]
  %12 = phi i32 [ %1, %6 ], [ %2, %.loopexit ]
  %13 = phi i1 [ true, %6 ], [ false, %.loopexit ]
  %.05359 = phi i32 [ 0, %6 ], [ 2, %.loopexit ]
  %umin = tail call i32 @llvm.umin.i32(i32 %.060, i32 16)
  %umax = tail call i32 @llvm.umax.i32(i32 %umin, i32 1)
  %.not = icmp eq i32 %.060, 0
  br i1 %.not, label %.preheader54, label %.lr.ph

.preheader54:                                     ; preds = %.lr.ph, %.preheader55
  %14 = or disjoint i32 %.05359, 12
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %.05359, i32 noundef %14, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %14, i32 noundef %14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %.05359, i32 noundef %14, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %14, i32 noundef %14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %.05359, i32 noundef %14, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %14, i32 noundef %14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %.05359, i32 noundef %14, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %14, i32 noundef %14, i32 noundef 4, i8 noundef zeroext 0) #3
  br i1 %11, label %.preheader, label %.loopexit

.lr.ph:                                           ; preds = %.preheader55, %.lr.ph
  %.05256 = phi i32 [ %17, %.lr.ph ], [ 0, %.preheader55 ]
  %15 = icmp ult i32 %.05256, 8
  %. = select i1 %15, i32 0, i32 8
  %16 = add nuw nsw i32 %., %.05256
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1589624832, i32 noundef %16, i32 noundef %12, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %12, i32 noundef 43, i32 noundef %12, i64 noundef %10) #3
  %17 = add nuw nsw i32 %.05256, 1
  %exitcond.not = icmp eq i32 %17, %umax
  br i1 %exitcond.not, label %.preheader54, label %.lr.ph, !llvm.loop !5

.preheader:                                       ; preds = %.preheader54
  %18 = or disjoint i32 %.05359, 1
  %19 = or disjoint i32 %.05359, 13
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %18, i32 noundef %19, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %19, i32 noundef %19, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %18, i32 noundef %19, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %19, i32 noundef %19, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %18, i32 noundef %19, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %19, i32 noundef %19, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef %18, i32 noundef %19, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef %19, i32 noundef %19, i32 noundef 4, i8 noundef zeroext 0) #3
  br label %.loopexit

.loopexit:                                        ; preds = %.preheader, %.preheader54
  %20 = add i32 %.060, -16
  %21 = and i1 %7, %13
  br i1 %21, label %.preheader55, label %22, !llvm.loop !7

22:                                               ; preds = %.loopexit
  ret void
}

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass