; LLVM IR from ermig1979/Simd :: src/Simd/SimdBaseSynetAdd16b.ll (ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::Base::SynetAdd16bUniform" = type { %"class.Simd::SynetAdd16b", i64, ptr }
%"class.Simd::SynetAdd16b" = type { %"struct.Simd::Deletable", %"struct.Simd::Add16bParam" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Add16bParam" = type { %"class.std::vector", %"class.std::vector", i32, i32, i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTVN4Simd4Base18SynetAdd16bUniformE = external dso_local unnamed_addr constant { [5 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [21 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [81 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE = external hidden unnamed_addr constant [72 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd11SynetAdd16bC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(72), ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(88) %0, ptr noundef nonnull align 8 dereferenceable(64) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN4Simd11SynetAdd16bC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(72) %8, ptr noundef nonnull align 8 dereferenceable(64) %9)
  store ptr getelementptr inbounds inrange(-16, 24) ({ [5 x ptr] }, ptr @_ZTVN4Simd4Base18SynetAdd16bUniformE, i32 0, i32 0, i32 2), ptr %8, align 8, !tbaa !9
  %10 = getelementptr inbounds %"class.Simd::Base::SynetAdd16bUniform", ptr %8, i32 0, i32 1
  store i64 0, ptr %10, align 8, !tbaa !11
  %11 = getelementptr inbounds %"class.Simd::Base::SynetAdd16bUniform", ptr %8, i32 0, i32 2
  store ptr null, ptr %11, align 8, !tbaa !23
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %12, i32 0, i32 0
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %14, i32 0, i32 1
  %16 = invoke noundef zeroext i1 @_ZSteqImSaImEEbRKSt6vectorIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(24) %13, ptr noundef nonnull align 8 dereferenceable(24) %15)
          to label %17 unwind label %20

17:                                               ; preds = %2
  br i1 %16, label %18, label %19

18:                                               ; preds = %17
  br label %25

19:                                               ; preds = %17
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 90, ptr noundef @__PRETTY_FUNCTION__._ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE) #6
  unreachable

20:                                               ; preds = %46, %2
  %21 = landingpad { ptr, i32 }
          cleanup
  %22 = extractvalue { ptr, i32 } %21, 0
  store ptr %22, ptr %5, align 8
  %23 = extractvalue { ptr, i32 } %21, 1
  store i32 %23, ptr %6, align 4
  call void @_ZN4Simd11SynetAdd16bD2Ev(ptr noundef nonnull align 8 dereferenceable(72) %8) #7
  br label %59

24:                                               ; No predecessors!
  br label %25

25:                                               ; preds = %24, %18
  %26 = getelementptr inbounds %"class.Simd::Base::SynetAdd16bUniform", ptr %8, i32 0, i32 1
  store i64 1, ptr %26, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #7
  store i64 0, ptr %7, align 8, !tbaa !24
  br label %27

27:                                               ; preds = %43, %25
  %28 = load i64, ptr %7, align 8, !tbaa !24
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  %30 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %29, i32 0, i32 0
  %31 = call noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %30) #7
  %32 = icmp ult i64 %28, %31
  br i1 %32, label %34, label %33

33:                                               ; preds = %27
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #7
  br label %46

34:                                               ; preds = %27
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %35, i32 0, i32 0
  %37 = load i64, ptr %7, align 8, !tbaa !24
  %38 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %37) #7
  %39 = load i64, ptr %38, align 8, !tbaa !24
  %40 = getelementptr inbounds %"class.Simd::Base::SynetAdd16bUniform", ptr %8, i32 0, i32 1
  %41 = load i64, ptr %40, align 8, !tbaa !11
  %42 = mul i64 %41, %39
  store i64 %42, ptr %40, align 8, !tbaa !11
  br label %43

43:                                               ; preds = %34
  %44 = load i64, ptr %7, align 8, !tbaa !24
  %45 = add i64 %44, 1
  store i64 %45, ptr %7, align 8, !tbaa !24
  br label %27, !llvm.loop !25

46:                                               ; preds = %33
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %47, i32 0, i32 2
  %49 = load i32, ptr %48, align 8, !tbaa !27
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %50, i32 0, i32 3
  %52 = load i32, ptr %51, align 4, !tbaa !28
  %53 = load ptr, ptr %4, align 8, !tbaa !5
  %54 = getelementptr inbounds %"struct.Simd::Add16bParam", ptr %53, i32 0, i32 4
  %55 = load i32, ptr %54, align 8, !tbaa !29
  %56 = invoke noundef ptr @_ZN4Simd4BaseL16GetAdd16bUniformE18SimdTensorDataTypeS1_S1_(i32 noundef %49, i32 noundef %52, i32 noundef %55)
          to label %57 unwind label %20

57:                                               ; preds = %46
  %58 = getelementptr inbounds %"class.Simd::Base::SynetAdd16bUniform", ptr %8, i32 0, i32 2
  store ptr %56, ptr %58, align 8, !tbaa !23
  ret void

59:                                               ; preds = %20
  %60 = load ptr, ptr %5, align 8
  %61 = load i32, ptr %6, align 4
  %62 = insertvalue { ptr, i32 } poison, ptr %60, 0
  %63 = insertvalue { ptr, i32 } %62, i32 %61, 1
  resume { ptr, i32 } %63
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZSteqImSaImEEbRKSt6vectorIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #4 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #3

; Function Attrs: mustprogress uwtable
declare hidden noundef ptr @_ZN4Simd4BaseL16GetAdd16bUniformE18SimdTensorDataTypeS1_S1_(i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd11SynetAdd16bD2Ev(ptr noundef nonnull align 8 dereferenceable(72)) unnamed_addr #5 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { noreturn nounwind }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !22, i64 72}
!12 = !{!"_ZTSN4Simd4Base18SynetAdd16bUniformE", !13, i64 0, !22, i64 72, !6, i64 80}
!13 = !{!"_ZTSN4Simd11SynetAdd16bE", !14, i64 0, !15, i64 8}
!14 = !{!"_ZTSN4Simd9DeletableE"}
!15 = !{!"_ZTSN4Simd11Add16bParamE", !16, i64 0, !16, i64 24, !20, i64 48, !20, i64 52, !20, i64 56, !21, i64 60}
!16 = !{!"_ZTSSt6vectorImSaImEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseImSaImEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!21 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!22 = !{!"long", !7, i64 0}
!23 = !{!12, !6, i64 80}
!24 = !{!22, !22, i64 0}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = !{!15, !20, i64 48}
!28 = !{!15, !20, i64 52}
!29 = !{!15, !20, i64 56}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN4Simd4Base18SynetAdd16bUniformE = external dso_local unnamed_addr constant { [5 x ptr] }, align 8
@.str = external hidden unnamed_addr constant [21 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [81 x i8], align 1
@__PRETTY_FUNCTION__._ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE = external hidden unnamed_addr constant [72 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Simd11SynetAdd16bC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(72), ptr noundef nonnull align 8 dereferenceable(64)) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(88) %0, ptr noundef nonnull align 8 dereferenceable(64) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN4Simd11SynetAdd16bC2ERKNS_11Add16bParamE(ptr noundef nonnull align 8 dereferenceable(72) %0, ptr noundef nonnull align 8 dereferenceable(64) %1)
  store ptr getelementptr inbounds inrange(-16, 24) (i8, ptr @_ZTVN4Simd4Base18SynetAdd16bUniformE, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 72
  %4 = getelementptr inbounds i8, ptr %1, i64 24
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %3, i8 0, i64 16, i1 false)
  %5 = invoke noundef zeroext i1 @_ZSteqImSaImEEbRKSt6vectorIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %4)
          to label %6 unwind label %8

6:                                                ; preds = %2
  br i1 %5, label %10, label %7

7:                                                ; preds = %6
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 90, ptr noundef nonnull @__PRETTY_FUNCTION__._ZN4Simd4Base18SynetAdd16bUniformC2ERKNS_11Add16bParamE) #6
  unreachable

8:                                                ; preds = %._crit_edge, %2
  %9 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN4Simd11SynetAdd16bD2Ev(ptr noundef nonnull align 8 dereferenceable(72) %0) #7
  resume { ptr, i32 } %9

10:                                               ; preds = %6
  store i64 1, ptr %3, align 8, !tbaa !8
  %11 = tail call noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %.not = icmp eq i64 %11, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %10
  %12 = getelementptr inbounds i8, ptr %1, i64 48
  %13 = load i32, ptr %12, align 8, !tbaa !22
  %14 = getelementptr inbounds i8, ptr %1, i64 52
  %15 = load i32, ptr %14, align 4, !tbaa !23
  %16 = getelementptr inbounds i8, ptr %1, i64 56
  %17 = load i32, ptr %16, align 8, !tbaa !24
  %18 = invoke noundef ptr @_ZN4Simd4BaseL16GetAdd16bUniformE18SimdTensorDataTypeS1_S1_(i32 noundef %13, i32 noundef %15, i32 noundef %17)
          to label %26 unwind label %8

.lr.ph:                                           ; preds = %10, %.lr.ph
  %.013 = phi i64 [ %23, %.lr.ph ], [ 0, %10 ]
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %.013) #7
  %20 = load i64, ptr %19, align 8, !tbaa !25
  %21 = load i64, ptr %3, align 8, !tbaa !8
  %22 = mul i64 %21, %20
  store i64 %22, ptr %3, align 8, !tbaa !8
  %23 = add nuw i64 %.013, 1
  %24 = tail call noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %25 = icmp ult i64 %23, %24
  br i1 %25, label %.lr.ph, label %._crit_edge, !llvm.loop !26

26:                                               ; preds = %._crit_edge
  %27 = getelementptr inbounds i8, ptr %0, i64 80
  store ptr %18, ptr %27, align 8, !tbaa !28
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZSteqImSaImEEbRKSt6vectorIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef ptr @_ZN4Simd4BaseL16GetAdd16bUniformE18SimdTensorDataTypeS1_S1_(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd11SynetAdd16bD2Ev(ptr noundef nonnull align 8 dereferenceable(72)) unnamed_addr #4 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #5

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #6 = { noreturn nounwind }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !21, i64 72}
!9 = !{!"_ZTSN4Simd4Base18SynetAdd16bUniformE", !10, i64 0, !21, i64 72, !17, i64 80}
!10 = !{!"_ZTSN4Simd11SynetAdd16bE", !11, i64 0, !12, i64 8}
!11 = !{!"_ZTSN4Simd9DeletableE"}
!12 = !{!"_ZTSN4Simd11Add16bParamE", !13, i64 0, !13, i64 24, !19, i64 48, !19, i64 52, !19, i64 56, !20, i64 60}
!13 = !{!"_ZTSSt6vectorImSaImEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseImSaImEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!17 = !{!"any pointer", !18, i64 0}
!18 = !{!"omnipotent char", !7, i64 0}
!19 = !{!"_ZTS18SimdTensorDataType", !18, i64 0}
!20 = !{!"_ZTS20SimdTensorFormatType", !18, i64 0}
!21 = !{!"long", !18, i64 0}
!22 = !{!12, !19, i64 48}
!23 = !{!12, !19, i64 52}
!24 = !{!12, !19, i64 56}
!25 = !{!21, !21, i64 0}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!9, !17, i64 80}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass