; LLVM IR from ermig1979/Simd :: src/Test/TestNeural.ll (ZN4Test5CheckERN4Simd6Neural7NetworkERKNS_11TrainSampleEfb)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::pair" = type { float, float }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Test::TrainSample" = type { %"class.std::vector.3", %"class.std::vector.8", %"class.std::vector.3" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<std::vector<float, Simd::Allocator<float>>, std::allocator<std::vector<float, Simd::Allocator<float>>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<float, Simd::Allocator<float>>, std::allocator<std::vector<float, Simd::Allocator<float>>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<float, Simd::Allocator<float>>, std::allocator<std::vector<float, Simd::Allocator<float>>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<float, Simd::Allocator<float>>, std::allocator<std::vector<float, Simd::Allocator<float>>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local <2 x float> @_ZN4Test5CheckERN4Simd6Neural7NetworkERKNS_11TrainSampleEfb(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(72) %1, float noundef %2, i1 noundef zeroext %3) #1 personality ptr @__gxx_personality_v0 {
  %5 = alloca %"struct.std::pair", align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca float, align 4
  %9 = alloca i8, align 1
  %10 = alloca double, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  %15 = alloca ptr, align 8
  %16 = alloca i64, align 8
  %17 = alloca %"class.std::vector.13", align 8
  %18 = alloca float, align 4
  %19 = alloca i64, align 8
  %20 = alloca ptr, align 8
  %21 = alloca i32, align 4
  %22 = alloca float, align 4
  %23 = alloca i64, align 8
  %24 = alloca float, align 4
  %25 = alloca float, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store float %2, ptr %8, align 4, !tbaa !9
  %26 = zext i1 %3 to i8
  store i8 %26, ptr %9, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #7
  store double 0.000000e+00, ptr %10, align 8, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #7
  store i64 0, ptr %11, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #7
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK4Simd6Neural7Network11OutputIndexEv(ptr noundef nonnull align 8 dereferenceable(24) %27)
  %29 = call noundef i64 @_ZNK4Simd6Neural5Index6VolumeEv(ptr noundef nonnull align 8 dereferenceable(24) %28)
  store i64 %29, ptr %12, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #7
  store i64 0, ptr %13, align 8, !tbaa !15
  br label %30

30:                                               ; preds = %137, %4
  %31 = load i64, ptr %13, align 8, !tbaa !15
  %32 = load ptr, ptr %7, align 8, !tbaa !5
  %33 = getelementptr inbounds %"struct.Test::TrainSample", ptr %32, i32 0, i32 0
  %34 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %33) #7
  %35 = icmp ult i64 %31, %34
  br i1 %35, label %37, label %36

36:                                               ; preds = %30
  store i32 2, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #7
  br label %140

37:                                               ; preds = %30
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #7
  %38 = load ptr, ptr %7, align 8, !tbaa !5
  %39 = getelementptr inbounds %"struct.Test::TrainSample", ptr %38, i32 0, i32 2
  %40 = load i64, ptr %13, align 8, !tbaa !15
  %41 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %40) #7
  store ptr %41, ptr %15, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #7
  %42 = load ptr, ptr %7, align 8, !tbaa !5
  %43 = getelementptr inbounds %"struct.Test::TrainSample", ptr %42, i32 0, i32 1
  %44 = load i64, ptr %13, align 8, !tbaa !15
  %45 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %44) #7
  %46 = load i64, ptr %45, align 8, !tbaa !15
  store i64 %46, ptr %16, align 8, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 24, ptr %17) #7
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = load ptr, ptr %7, align 8, !tbaa !5
  %49 = getelementptr inbounds %"struct.Test::TrainSample", ptr %48, i32 0, i32 0
  %50 = load i64, ptr %13, align 8, !tbaa !15
  %51 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %50) #7
  %52 = load i8, ptr %9, align 1, !tbaa !11, !range !17, !noundef !18
  %53 = trunc i8 %52 to i1
  %54 = zext i1 %53 to i64
  %55 = select i1 %53, i32 1, i32 0
  %56 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZN4Simd6Neural7Network7PredictERKSt6vectorIfNS_9AllocatorIfEEEmNS0_5Layer6MethodE(ptr noundef nonnull align 8 dereferenceable(24) %47, ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef 0, i32 noundef %55)
  call void @_ZNSt6vectorIfN4Simd9AllocatorIfEEEC2ERKS3_(ptr noundef nonnull align 8 dereferenceable(24) %17, ptr noundef nonnull align 8 dereferenceable(24) %56)
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #7
  store float 0.000000e+00, ptr %18, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #7
  store i64 0, ptr %19, align 8, !tbaa !15
  br label %57

57:                                               ; preds = %75, %37
  %58 = load i64, ptr %19, align 8, !tbaa !15
  %59 = load i64, ptr %12, align 8, !tbaa !15
  %60 = icmp ult i64 %58, %59
  br i1 %60, label %62, label %61

61:                                               ; preds = %57
  store i32 5, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #7
  br label %82

62:                                               ; preds = %57
  %63 = load ptr, ptr %15, align 8, !tbaa !5
  %64 = load i64, ptr %19, align 8, !tbaa !15
  %65 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %64) #7
  %66 = load float, ptr %65, align 4, !tbaa !9
  %67 = load i64, ptr %19, align 8, !tbaa !15
  %68 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %67) #7
  %69 = load float, ptr %68, align 4, !tbaa !9
  %70 = fsub float %66, %69
  %71 = invoke noundef float @_ZN4Simd6SquareIfEET_S1_(float noundef %70)
          to label %72 unwind label %78

72:                                               ; preds = %62
  %73 = load float, ptr %18, align 4, !tbaa !9
  %74 = fadd float %73, %71
  store float %74, ptr %18, align 4, !tbaa !9
  br label %75

75:                                               ; preds = %72
  %76 = load i64, ptr %19, align 8, !tbaa !15
  %77 = add i64 %76, 1
  store i64 %77, ptr %19, align 8, !tbaa !15
  br label %57, !llvm.loop !19

78:                                               ; preds = %62
  %79 = landingpad { ptr, i32 }
          cleanup
  %80 = extractvalue { ptr, i32 } %79, 0
  store ptr %80, ptr %20, align 8
  %81 = extractvalue { ptr, i32 } %79, 1
  store i32 %81, ptr %21, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #7
  call void @_ZNSt6vectorIfN4Simd9AllocatorIfEEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #7
  call void @llvm.lifetime.end.p0(i64 24, ptr %17) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #7
  br label %157

82:                                               ; preds = %61
  %83 = load float, ptr %18, align 4, !tbaa !9
  %84 = load i64, ptr %12, align 8, !tbaa !15
  %85 = uitofp i64 %84 to float
  %86 = fdiv float %83, %85
  %87 = fpext float %86 to double
  %88 = load double, ptr %10, align 8, !tbaa !13
  %89 = fadd double %88, %87
  store double %89, ptr %10, align 8, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #7
  %90 = load i64, ptr %16, align 8, !tbaa !15
  %91 = load i64, ptr %12, align 8, !tbaa !15
  %92 = icmp ult i64 %90, %91
  br i1 %92, label %93, label %98

93:                                               ; preds = %82
  %94 = load ptr, ptr %15, align 8, !tbaa !5
  %95 = load i64, ptr %16, align 8, !tbaa !15
  %96 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %94, i64 noundef %95) #7
  %97 = load float, ptr %96, align 4, !tbaa !9
  br label %100

98:                                               ; preds = %82
  %99 = load float, ptr %8, align 4, !tbaa !9
  br label %100

100:                                              ; preds = %98, %93
  %101 = phi float [ %97, %93 ], [ %99, %98 ]
  store float %101, ptr %22, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %23) #7
  store i64 0, ptr %23, align 8, !tbaa !15
  br label %102

102:                                              ; preds = %132, %100
  %103 = load i64, ptr %23, align 8, !tbaa !15
  %104 = load i64, ptr %12, align 8, !tbaa !15
  %105 = icmp ult i64 %103, %104
  br i1 %105, label %107, label %106

106:                                              ; preds = %102
  store i32 8, ptr %14, align 4
  br label %135

107:                                              ; preds = %102
  %108 = load i64, ptr %23, align 8, !tbaa !15
  %109 = load i64, ptr %16, align 8, !tbaa !15
  %110 = icmp eq i64 %108, %109
  br i1 %110, label %111, label %121

111:                                              ; preds = %107
  %112 = load i64, ptr %23, align 8, !tbaa !15
  %113 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %112) #7
  %114 = load float, ptr %113, align 4, !tbaa !9
  %115 = load float, ptr %8, align 4, !tbaa !9
  %116 = fcmp olt float %114, %115
  br i1 %116, label %117, label %120

117:                                              ; preds = %111
  %118 = load i64, ptr %11, align 8, !tbaa !15
  %119 = add i64 %118, 1
  store i64 %119, ptr %11, align 8, !tbaa !15
  store i32 8, ptr %14, align 4
  br label %135

120:                                              ; preds = %111
  br label %131

121:                                              ; preds = %107
  %122 = load i64, ptr %23, align 8, !tbaa !15
  %123 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %122) #7
  %124 = load float, ptr %123, align 4, !tbaa !9
  %125 = load float, ptr %22, align 4, !tbaa !9
  %126 = fcmp ogt float %124, %125
  br i1 %126, label %127, label %130

127:                                              ; preds = %121
  %128 = load i64, ptr %11, align 8, !tbaa !15
  %129 = add i64 %128, 1
  store i64 %129, ptr %11, align 8, !tbaa !15
  store i32 8, ptr %14, align 4
  br label %135

130:                                              ; preds = %121
  br label %131

131:                                              ; preds = %130, %120
  br label %132

132:                                              ; preds = %131
  %133 = load i64, ptr %23, align 8, !tbaa !15
  %134 = add i64 %133, 1
  store i64 %134, ptr %23, align 8, !tbaa !15
  br label %102, !llvm.loop !21

135:                                              ; preds = %127, %117, %106
  call void @llvm.lifetime.end.p0(i64 8, ptr %23) #7
  br label %136

136:                                              ; preds = %135
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #7
  call void @_ZNSt6vectorIfN4Simd9AllocatorIfEEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %17) #7
  call void @llvm.lifetime.end.p0(i64 24, ptr %17) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #7
  br label %137

137:                                              ; preds = %136
  %138 = load i64, ptr %13, align 8, !tbaa !15
  %139 = add i64 %138, 1
  store i64 %139, ptr %13, align 8, !tbaa !15
  br label %30, !llvm.loop !22

140:                                              ; preds = %36
  call void @llvm.lifetime.start.p0(i64 4, ptr %24) #7
  %141 = load double, ptr %10, align 8, !tbaa !13
  %142 = load ptr, ptr %7, align 8, !tbaa !5
  %143 = getelementptr inbounds %"struct.Test::TrainSample", ptr %142, i32 0, i32 0
  %144 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %143) #7
  %145 = uitofp i64 %144 to double
  %146 = fdiv double %141, %145
  %147 = call double @sqrt(double noundef %146) #7
  %148 = fptrunc double %147 to float
  store float %148, ptr %24, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #7
  %149 = load i64, ptr %11, align 8, !tbaa !15
  %150 = uitofp i64 %149 to float
  %151 = load ptr, ptr %7, align 8, !tbaa !5
  %152 = getelementptr inbounds %"struct.Test::TrainSample", ptr %151, i32 0, i32 0
  %153 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %152) #7
  %154 = uitofp i64 %153 to float
  %155 = fdiv float %150, %154
  store float %155, ptr %25, align 4, !tbaa !9
  call void @_ZNSt4pairIffEC2IffTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS3_S4_EEEbE4typeELb1EEEOS3_OS4_(ptr noundef nonnull align 4 dereferenceable(8) %5, ptr noundef nonnull align 4 dereferenceable(4) %24, ptr noundef nonnull align 4 dereferenceable(4) %25)
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr %24) #7
  store i32 1, ptr %14, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #7
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #7
  %156 = load <2 x float>, ptr %5, align 4
  ret <2 x float> %156

157:                                              ; preds = %78
  %158 = load ptr, ptr %20, align 8
  %159 = load i32, ptr %21, align 4
  %160 = insertvalue { ptr, i32 } poison, ptr %158, 0
  %161 = insertvalue { ptr, i32 } %160, i32 %159, 1
  resume { ptr, i32 } %161
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK4Simd6Neural7Network11OutputIndexEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK4Simd6Neural5Index6VolumeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN4Simd6Neural7Network7PredictERKSt6vectorIfNS_9AllocatorIfEEEmNS0_5Layer6MethodE(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, i32 noundef) #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIfN4Simd9AllocatorIfEEEC2ERKS3_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #5 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd6SquareIfEET_S1_(float noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfN4Simd9AllocatorIfEEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare double @sqrt(double noundef) #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIffEC2IffTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS3_S4_EEEbE4typeELb1EEEOS3_OS4_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"float", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"double", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}
!21 = distinct !{!21, !20}
!22 = distinct !{!22, !20}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::pair" = type { float, float }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, Simd::Allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local <2 x float> @_ZN4Test5CheckERN4Simd6Neural7NetworkERKNS_11TrainSampleEfb(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(72) %1, float noundef %2, i1 noundef zeroext %3) local_unnamed_addr #1 personality ptr @__gxx_personality_v0 {
  %5 = alloca %"struct.std::pair", align 8
  %6 = alloca %"class.std::vector.13", align 8
  %7 = alloca float, align 4
  %8 = alloca float, align 4
  %9 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK4Simd6Neural7Network11OutputIndexEv(ptr noundef nonnull align 8 dereferenceable(24) %0)
  %10 = tail call noundef i64 @_ZNK4Simd6Neural5Index6VolumeEv(ptr noundef nonnull align 8 dereferenceable(24) %9)
  %11 = tail call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %.not = icmp eq i64 %11, 0
  br i1 %.not, label %._crit_edge58, label %.lr.ph57

.lr.ph57:                                         ; preds = %4
  %12 = getelementptr inbounds i8, ptr %1, i64 48
  %13 = getelementptr inbounds i8, ptr %1, i64 24
  %14 = zext i1 %3 to i32
  %.not61 = icmp eq i64 %10, 0
  %15 = uitofp i64 %10 to float
  br label %26

._crit_edge58.loopexit:                           ; preds = %.loopexit
  %16 = uitofp i64 %.1 to float
  br label %._crit_edge58

._crit_edge58:                                    ; preds = %._crit_edge58.loopexit, %4
  %.044.lcssa = phi float [ 0.000000e+00, %4 ], [ %16, %._crit_edge58.loopexit ]
  %.041.lcssa = phi double [ 0.000000e+00, %4 ], [ %59, %._crit_edge58.loopexit ]
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #7
  %17 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %18 = uitofp i64 %17 to double
  %19 = fdiv double %.041.lcssa, %18
  %20 = call double @sqrt(double noundef %19) #7
  %21 = fptrunc double %20 to float
  store float %21, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %8) #7
  %22 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %23 = uitofp i64 %22 to float
  %24 = fdiv float %.044.lcssa, %23
  store float %24, ptr %8, align 4, !tbaa !5
  call void @_ZNSt4pairIffEC2IffTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS3_S4_EEEbE4typeELb1EEEOS3_OS4_(ptr noundef nonnull align 4 dereferenceable(8) %5, ptr noundef nonnull align 4 dereferenceable(4) %7, ptr noundef nonnull align 4 dereferenceable(4) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %8) #7
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #7
  %25 = load <2 x float>, ptr %5, align 8
  ret <2 x float> %25

26:                                               ; preds = %.lr.ph57, %.loopexit
  %.04155 = phi double [ 0.000000e+00, %.lr.ph57 ], [ %59, %.loopexit ]
  %.04454 = phi i64 [ 0, %.lr.ph57 ], [ %.1, %.loopexit ]
  %.04553 = phi i64 [ 0, %.lr.ph57 ], [ %60, %.loopexit ]
  %27 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %.04553) #7
  %28 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %.04553) #7
  %29 = load i64, ptr %28, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %6) #7
  %30 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %.04553) #7
  %31 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZN4Simd6Neural7Network7PredictERKSt6vectorIfNS_9AllocatorIfEEEmNS0_5Layer6MethodE(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %30, i64 noundef 0, i32 noundef %14)
  call void @_ZNSt6vectorIfN4Simd9AllocatorIfEEEC2ERKS3_(ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %31)
  br i1 %.not61, label %.loopexit, label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph
  %32 = icmp ult i64 %29, %10
  br i1 %32, label %.thread, label %.lr.ph52.preheader

.lr.ph:                                           ; preds = %26, %.lr.ph
  %.04249 = phi i64 [ %40, %.lr.ph ], [ 0, %26 ]
  %.04348 = phi float [ %39, %.lr.ph ], [ 0.000000e+00, %26 ]
  %33 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %27, i64 noundef %.04249) #7
  %34 = load float, ptr %33, align 4, !tbaa !5
  %35 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %.04249) #7
  %36 = load float, ptr %35, align 4, !tbaa !5
  %37 = fsub float %34, %36
  %38 = call noundef float @_ZN4Simd6SquareIfEET_S1_(float noundef %37)
  %39 = fadd float %.04348, %38
  %40 = add nuw i64 %.04249, 1
  %exitcond.not = icmp eq i64 %40, %10
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !11

.thread:                                          ; preds = %._crit_edge
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %27, i64 noundef %29) #7
  %42 = load float, ptr %41, align 4, !tbaa !5
  br label %.lr.ph52.preheader

.lr.ph52.preheader:                               ; preds = %._crit_edge, %.thread
  %43 = phi float [ %42, %.thread ], [ %2, %._crit_edge ]
  br label %.lr.ph52

.lr.ph52:                                         ; preds = %.lr.ph52.preheader, %57
  %.050 = phi i64 [ %58, %57 ], [ 0, %.lr.ph52.preheader ]
  %44 = icmp eq i64 %.050, %29
  br i1 %44, label %45, label %51

45:                                               ; preds = %.lr.ph52
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %29) #7
  %47 = load float, ptr %46, align 4, !tbaa !5
  %48 = fcmp olt float %47, %2
  br i1 %48, label %49, label %57

49:                                               ; preds = %45
  %50 = add i64 %.04454, 1
  br label %.loopexit

51:                                               ; preds = %.lr.ph52
  %52 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %.050) #7
  %53 = load float, ptr %52, align 4, !tbaa !5
  %54 = fcmp ogt float %53, %43
  br i1 %54, label %55, label %57

55:                                               ; preds = %51
  %56 = add i64 %.04454, 1
  br label %.loopexit

57:                                               ; preds = %45, %51
  %58 = add nuw i64 %.050, 1
  %exitcond64.not = icmp eq i64 %58, %10
  br i1 %exitcond64.not, label %.loopexit, label %.lr.ph52, !llvm.loop !13

.loopexit:                                        ; preds = %57, %26, %55, %49
  %.pn68 = phi float [ %39, %49 ], [ %39, %55 ], [ 0.000000e+00, %26 ], [ %39, %57 ]
  %.1 = phi i64 [ %50, %49 ], [ %56, %55 ], [ %.04454, %26 ], [ %.04454, %57 ]
  %.pn.in = fdiv float %.pn68, %15
  %.pn = fpext float %.pn.in to double
  %59 = fadd double %.04155, %.pn
  call void @_ZNSt6vectorIfN4Simd9AllocatorIfEEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #7
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %6) #7
  %60 = add nuw i64 %.04553, 1
  %61 = call noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #7
  %62 = icmp ult i64 %60, %61
  br i1 %62, label %26, label %._crit_edge58.loopexit, !llvm.loop !14
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK4Simd6Neural7Network11OutputIndexEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNK4Simd6Neural5Index6VolumeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IfN4Simd9AllocatorIfEEESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZN4Simd6Neural7Network7PredictERKSt6vectorIfNS_9AllocatorIfEEEmNS0_5Layer6MethodE(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, i32 noundef) local_unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIfN4Simd9AllocatorIfEEEC2ERKS3_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #5 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd6SquareIfEET_S1_(float noundef) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfN4Simd9AllocatorIfEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfN4Simd9AllocatorIfEEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @sqrt(double noundef) local_unnamed_addr #6

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIffEC2IffTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS3_S4_EEEbE4typeELb1EEEOS3_OS4_(ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass