; LLVM IR from libxsmm/libxsmm :: src (generator_gemm_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c = external hidden unnamed_addr constant [24 x i32], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9) #1 {
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca [2 x i32], align 4
  %25 = alloca i32, align 4
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca i8, align 1
  %30 = alloca [24 x i32], align 16
  %31 = alloca i32, align 4
  %32 = alloca i32, align 4
  %33 = alloca i32, align 4
  %34 = alloca i32, align 4
  %35 = alloca i32, align 4
  %36 = alloca i32, align 4
  %37 = alloca i32, align 4
  %38 = alloca i32, align 4
  %39 = alloca i32, align 4
  %40 = alloca i32, align 4
  %41 = alloca i32, align 4
  %42 = alloca i32, align 4
  %43 = alloca i32, align 4
  %44 = alloca i32, align 4
  %45 = alloca i32, align 4
  %46 = alloca i32, align 4
  %47 = alloca i32, align 4
  %48 = alloca i32, align 4
  %49 = alloca i32, align 4
  %50 = alloca i32, align 4
  %51 = alloca i32, align 4
  %52 = alloca i32, align 4
  store ptr %0, ptr %11, align 8, !tbaa !5
  store ptr %1, ptr %12, align 8, !tbaa !5
  store ptr %2, ptr %13, align 8, !tbaa !5
  store i32 %3, ptr %14, align 4, !tbaa !9
  store i32 %4, ptr %15, align 4, !tbaa !9
  store i32 %5, ptr %16, align 4, !tbaa !9
  store i32 %6, ptr %17, align 4, !tbaa !9
  store i32 %7, ptr %18, align 4, !tbaa !9
  store i32 %8, ptr %19, align 4, !tbaa !9
  store i32 %9, ptr %20, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #5
  store i32 2, ptr %21, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #5
  store i32 0, ptr %22, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #5
  store i32 0, ptr %23, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %24) #5
  call void @llvm.memset.p0.i64(ptr align 4 %24, i8 0, i64 8, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #5
  %53 = load i32, ptr %20, align 4, !tbaa !9
  %54 = icmp ugt i32 %53, 0
  br i1 %54, label %55, label %59

55:                                               ; preds = %10
  %56 = load i32, ptr %19, align 4, !tbaa !9
  %57 = add i32 %56, 1
  %58 = udiv i32 %57, 2
  br label %61

59:                                               ; preds = %10
  %60 = load i32, ptr %19, align 4, !tbaa !9
  br label %61

61:                                               ; preds = %59, %55
  %62 = phi i32 [ %58, %55 ], [ %60, %59 ]
  store i32 %62, ptr %25, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %26) #5
  store i32 0, ptr %26, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %27) #5
  store i32 0, ptr %27, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %28) #5
  store i32 0, ptr %28, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %29) #5
  store i8 0, ptr %29, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 96, ptr %30) #5
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %30, ptr align 16 @__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c, i64 96, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %31) #5
  store i32 0, ptr %31, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %32) #5
  store i32 0, ptr %32, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %33) #5
  store i32 16, ptr %33, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %34) #5
  store i32 0, ptr %34, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %35) #5
  store i32 1, ptr %35, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %36) #5
  store i32 2, ptr %36, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %37) #5
  store i32 3, ptr %37, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %38) #5
  store i32 4, ptr %38, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %39) #5
  store i32 5, ptr %39, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %40) #5
  store i32 6, ptr %40, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %41) #5
  store i32 7, ptr %41, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %42) #5
  store i32 8, ptr %42, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %43) #5
  store i32 9, ptr %43, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %44) #5
  store i32 10, ptr %44, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %45) #5
  store i32 11, ptr %45, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %46) #5
  store i32 12, ptr %46, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %47) #5
  store i32 13, ptr %47, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %48) #5
  store i32 14, ptr %48, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %49) #5
  store i32 15, ptr %49, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %50) #5
  store i32 6, ptr %50, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %51) #5
  store i32 5, ptr %51, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %52) #5
  store i32 0, ptr %52, align 4, !tbaa !9
  %63 = load ptr, ptr %12, align 8, !tbaa !5
  %64 = load ptr, ptr %13, align 8, !tbaa !5
  %65 = load i32, ptr %18, align 4, !tbaa !9
  %66 = load i32, ptr %16, align 4, !tbaa !9
  %67 = udiv i32 %65, %66
  %68 = getelementptr inbounds [2 x i32], ptr %24, i64 0, i64 0
  store i32 %67, ptr %68, align 4, !tbaa !9
  %69 = load i32, ptr %18, align 4, !tbaa !9
  %70 = load i32, ptr %16, align 4, !tbaa !9
  %71 = urem i32 %69, %70
  store i32 %71, ptr %28, align 4, !tbaa !9
  %72 = load i32, ptr %28, align 4, !tbaa !9
  %73 = icmp ugt i32 %72, 0
  %74 = zext i1 %73 to i32
  %75 = getelementptr inbounds [2 x i32], ptr %24, i64 0, i64 1
  store i32 %74, ptr %75, align 4, !tbaa !9
  %76 = getelementptr inbounds [2 x i32], ptr %24, i64 0, i64 0
  %77 = load i32, ptr %76, align 4, !tbaa !9
  %78 = getelementptr inbounds [2 x i32], ptr %24, i64 0, i64 1
  %79 = load i32, ptr %78, align 4, !tbaa !9
  %80 = add i32 %77, %79
  store i32 %80, ptr %26, align 4, !tbaa !9
  %81 = load i32, ptr %17, align 4, !tbaa !9
  %82 = load i32, ptr %19, align 4, !tbaa !9
  %83 = load i32, ptr %26, align 4, !tbaa !9
  %84 = mul i32 %82, %83
  %85 = sub i32 %81, %84
  store i32 %85, ptr %27, align 4, !tbaa !9
  %86 = load i32, ptr %20, align 4, !tbaa !9
  %87 = icmp ugt i32 %86, 0
  br i1 %87, label %88, label %91

88:                                               ; preds = %61
  %89 = getelementptr inbounds [24 x i32], ptr %30, i64 0, i64 0
  %90 = load i32, ptr %89, align 16, !tbaa !9
  store i32 %90, ptr %27, align 4, !tbaa !9
  br label %91

91:                                               ; preds = %88, %61
  %92 = load i32, ptr %27, align 4, !tbaa !9
  %93 = load i32, ptr %33, align 4, !tbaa !9
  %94 = icmp ult i32 %92, %93
  br i1 %94, label %95, label %115

95:                                               ; preds = %91
  %96 = load ptr, ptr %11, align 8, !tbaa !5
  %97 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %96, i32 noundef 6, i32 noundef %97)
  %98 = load i32, ptr %27, align 4, !tbaa !9
  store i32 %98, ptr %22, align 4, !tbaa !9
  br label %99

99:                                               ; preds = %111, %95
  %100 = load i32, ptr %22, align 4, !tbaa !9
  %101 = load i32, ptr %33, align 4, !tbaa !9
  %102 = icmp ule i32 %100, %101
  br i1 %102, label %103, label %114

103:                                              ; preds = %99
  %104 = load ptr, ptr %11, align 8, !tbaa !5
  %105 = load i32, ptr %15, align 4, !tbaa !9
  %106 = load i32, ptr %22, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %104, i32 noundef -444579834, i32 noundef %105, i32 noundef 127, i32 noundef 0, i32 noundef %106, i32 noundef 127)
  %107 = load ptr, ptr %11, align 8, !tbaa !5
  %108 = load i32, ptr %15, align 4, !tbaa !9
  %109 = load i32, ptr %14, align 4, !tbaa !9
  %110 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %107, i32 noundef 4096, i32 noundef %108, i32 noundef %109, i32 noundef %110, i64 noundef 64)
  br label %111

111:                                              ; preds = %103
  %112 = load i32, ptr %22, align 4, !tbaa !9
  %113 = add i32 %112, 1
  store i32 %113, ptr %22, align 4, !tbaa !9
  br label %99, !llvm.loop !12

114:                                              ; preds = %99
  br label %115

115:                                              ; preds = %114, %91
  %116 = load ptr, ptr %11, align 8, !tbaa !5
  %117 = load i32, ptr %34, align 4, !tbaa !9
  %118 = load i32, ptr %35, align 4, !tbaa !9
  %119 = load i32, ptr %36, align 4, !tbaa !9
  %120 = load i32, ptr %37, align 4, !tbaa !9
  %121 = load i32, ptr %38, align 4, !tbaa !9
  %122 = load i32, ptr %39, align 4, !tbaa !9
  %123 = load i32, ptr %40, align 4, !tbaa !9
  %124 = load i32, ptr %41, align 4, !tbaa !9
  %125 = load i32, ptr %42, align 4, !tbaa !9
  %126 = load i32, ptr %43, align 4, !tbaa !9
  %127 = load i32, ptr %44, align 4, !tbaa !9
  %128 = load i32, ptr %45, align 4, !tbaa !9
  %129 = load i32, ptr %14, align 4, !tbaa !9
  %130 = load i32, ptr %21, align 4, !tbaa !9
  %131 = load i8, ptr %29, align 1, !tbaa !11
  call void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %116, i32 noundef %117, i32 noundef %118, i32 noundef %119, i32 noundef %120, i32 noundef %121, i32 noundef %122, i32 noundef %123, i32 noundef %124, i32 noundef %125, i32 noundef %126, i32 noundef %127, i32 noundef %128, i32 noundef %129, i32 noundef %130, i8 noundef zeroext %131)
  store i32 0, ptr %22, align 4, !tbaa !9
  br label %132

132:                                              ; preds = %242, %115
  %133 = load i32, ptr %22, align 4, !tbaa !9
  %134 = load i32, ptr %25, align 4, !tbaa !9
  %135 = icmp ult i32 %133, %134
  br i1 %135, label %136, label %245

136:                                              ; preds = %132
  store i32 0, ptr %23, align 4, !tbaa !9
  br label %137

137:                                              ; preds = %238, %136
  %138 = load i32, ptr %23, align 4, !tbaa !9
  %139 = load i32, ptr %26, align 4, !tbaa !9
  %140 = icmp ult i32 %138, %139
  br i1 %140, label %141, label %241

141:                                              ; preds = %137
  store i32 0, ptr %31, align 4, !tbaa !9
  br label %142

142:                                              ; preds = %234, %141
  %143 = load i32, ptr %31, align 4, !tbaa !9
  %144 = load i32, ptr %20, align 4, !tbaa !9
  %145 = icmp ule i32 %143, %144
  br i1 %145, label %146, label %237

146:                                              ; preds = %142
  %147 = load i32, ptr %20, align 4, !tbaa !9
  %148 = icmp eq i32 %147, 0
  br i1 %148, label %149, label %157

149:                                              ; preds = %146
  %150 = load i32, ptr %27, align 4, !tbaa !9
  %151 = load i32, ptr %23, align 4, !tbaa !9
  %152 = add i32 %150, %151
  %153 = load i32, ptr %26, align 4, !tbaa !9
  %154 = load i32, ptr %22, align 4, !tbaa !9
  %155 = mul i32 %153, %154
  %156 = add i32 %152, %155
  store i32 %156, ptr %32, align 4, !tbaa !9
  br label %168

157:                                              ; preds = %146
  %158 = load i32, ptr %22, align 4, !tbaa !9
  %159 = mul i32 8, %158
  %160 = load i32, ptr %23, align 4, !tbaa !9
  %161 = mul i32 2, %160
  %162 = add i32 %159, %161
  %163 = load i32, ptr %31, align 4, !tbaa !9
  %164 = add i32 %162, %163
  %165 = zext i32 %164 to i64
  %166 = getelementptr inbounds [24 x i32], ptr %30, i64 0, i64 %165
  %167 = load i32, ptr %166, align 4, !tbaa !9
  store i32 %167, ptr %32, align 4, !tbaa !9
  br label %168

168:                                              ; preds = %157, %149
  %169 = load i32, ptr %27, align 4, !tbaa !9
  %170 = load i32, ptr %33, align 4, !tbaa !9
  %171 = icmp ult i32 %169, %170
  br i1 %171, label %172, label %196

172:                                              ; preds = %168
  %173 = load i32, ptr %32, align 4, !tbaa !9
  %174 = load i32, ptr %33, align 4, !tbaa !9
  %175 = icmp ule i32 %173, %174
  br i1 %175, label %176, label %193

176:                                              ; preds = %172
  %177 = load i32, ptr %33, align 4, !tbaa !9
  store i32 %177, ptr %52, align 4, !tbaa !9
  %178 = load ptr, ptr %11, align 8, !tbaa !5
  %179 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %178, i32 noundef 6, i32 noundef %179)
  %180 = load ptr, ptr %11, align 8, !tbaa !5
  %181 = load i32, ptr %15, align 4, !tbaa !9
  %182 = load i32, ptr %14, align 4, !tbaa !9
  %183 = load i32, ptr %15, align 4, !tbaa !9
  %184 = load i32, ptr %32, align 4, !tbaa !9
  %185 = zext i32 %184 to i64
  %186 = load i32, ptr %27, align 4, !tbaa !9
  %187 = zext i32 %186 to i64
  %188 = sub nsw i64 %185, %187
  %189 = mul nsw i64 %188, 64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %180, i32 noundef 4096, i32 noundef %181, i32 noundef %182, i32 noundef %183, i64 noundef %189)
  %190 = load ptr, ptr %11, align 8, !tbaa !5
  %191 = load i32, ptr %15, align 4, !tbaa !9
  %192 = load i32, ptr %52, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %190, i32 noundef -2055192570, i32 noundef %191, i32 noundef 127, i32 noundef 0, i32 noundef %192, i32 noundef 127)
  br label %195

193:                                              ; preds = %172
  %194 = load i32, ptr %32, align 4, !tbaa !9
  store i32 %194, ptr %52, align 4, !tbaa !9
  br label %195

195:                                              ; preds = %193, %176
  br label %198

196:                                              ; preds = %168
  %197 = load i32, ptr %32, align 4, !tbaa !9
  store i32 %197, ptr %52, align 4, !tbaa !9
  br label %198

198:                                              ; preds = %196, %195
  %199 = load ptr, ptr %11, align 8, !tbaa !5
  %200 = load i32, ptr %52, align 4, !tbaa !9
  %201 = load i32, ptr %47, align 4, !tbaa !9
  %202 = load i32, ptr %48, align 4, !tbaa !9
  %203 = load i32, ptr %49, align 4, !tbaa !9
  %204 = load i32, ptr %50, align 4, !tbaa !9
  %205 = load i32, ptr %51, align 4, !tbaa !9
  %206 = load i32, ptr %34, align 4, !tbaa !9
  %207 = load i32, ptr %35, align 4, !tbaa !9
  %208 = load i32, ptr %36, align 4, !tbaa !9
  %209 = load i32, ptr %37, align 4, !tbaa !9
  %210 = load i32, ptr %38, align 4, !tbaa !9
  %211 = load i32, ptr %39, align 4, !tbaa !9
  %212 = load i32, ptr %40, align 4, !tbaa !9
  %213 = load i32, ptr %41, align 4, !tbaa !9
  %214 = load i32, ptr %42, align 4, !tbaa !9
  %215 = load i32, ptr %43, align 4, !tbaa !9
  %216 = load i32, ptr %44, align 4, !tbaa !9
  %217 = load i32, ptr %45, align 4, !tbaa !9
  %218 = load i32, ptr %46, align 4, !tbaa !9
  %219 = load i32, ptr %21, align 4, !tbaa !9
  %220 = load i8, ptr %29, align 1, !tbaa !11
  call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %199, i32 noundef %200, i32 noundef %201, i32 noundef %202, i32 noundef %203, i32 noundef %204, i32 noundef %205, i32 noundef %206, i32 noundef %207, i32 noundef %208, i32 noundef %209, i32 noundef %210, i32 noundef %211, i32 noundef %212, i32 noundef %213, i32 noundef %214, i32 noundef %215, i32 noundef %216, i32 noundef %217, i32 noundef %218, i32 noundef %219, i8 noundef zeroext %220)
  %221 = load i32, ptr %27, align 4, !tbaa !9
  %222 = load i32, ptr %33, align 4, !tbaa !9
  %223 = icmp ult i32 %221, %222
  br i1 %223, label %224, label %233

224:                                              ; preds = %198
  %225 = load i32, ptr %32, align 4, !tbaa !9
  %226 = load i32, ptr %33, align 4, !tbaa !9
  %227 = icmp ule i32 %225, %226
  br i1 %227, label %228, label %232

228:                                              ; preds = %224
  %229 = load ptr, ptr %11, align 8, !tbaa !5
  %230 = load i32, ptr %15, align 4, !tbaa !9
  %231 = load i32, ptr %52, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %229, i32 noundef -444579834, i32 noundef %230, i32 noundef 127, i32 noundef 0, i32 noundef %231, i32 noundef 127)
  br label %232

232:                                              ; preds = %228, %224
  br label %233

233:                                              ; preds = %232, %198
  br label %234

234:                                              ; preds = %233
  %235 = load i32, ptr %31, align 4, !tbaa !9
  %236 = add i32 %235, 1
  store i32 %236, ptr %31, align 4, !tbaa !9
  br label %142, !llvm.loop !14

237:                                              ; preds = %142
  br label %238

238:                                              ; preds = %237
  %239 = load i32, ptr %23, align 4, !tbaa !9
  %240 = add i32 %239, 1
  store i32 %240, ptr %23, align 4, !tbaa !9
  br label %137, !llvm.loop !15

241:                                              ; preds = %137
  br label %242

242:                                              ; preds = %241
  %243 = load i32, ptr %22, align 4, !tbaa !9
  %244 = add i32 %243, 1
  store i32 %244, ptr %22, align 4, !tbaa !9
  br label %132, !llvm.loop !16

245:                                              ; preds = %132
  %246 = load i32, ptr %27, align 4, !tbaa !9
  %247 = load i32, ptr %33, align 4, !tbaa !9
  %248 = icmp ult i32 %246, %247
  br i1 %248, label %249, label %269

249:                                              ; preds = %245
  %250 = load ptr, ptr %11, align 8, !tbaa !5
  %251 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %250, i32 noundef 6, i32 noundef %251)
  %252 = load i32, ptr %27, align 4, !tbaa !9
  store i32 %252, ptr %22, align 4, !tbaa !9
  br label %253

253:                                              ; preds = %265, %249
  %254 = load i32, ptr %22, align 4, !tbaa !9
  %255 = load i32, ptr %33, align 4, !tbaa !9
  %256 = icmp ule i32 %254, %255
  br i1 %256, label %257, label %268

257:                                              ; preds = %253
  %258 = load ptr, ptr %11, align 8, !tbaa !5
  %259 = load i32, ptr %15, align 4, !tbaa !9
  %260 = load i32, ptr %22, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %258, i32 noundef -2055192570, i32 noundef %259, i32 noundef 127, i32 noundef 0, i32 noundef %260, i32 noundef 127)
  %261 = load ptr, ptr %11, align 8, !tbaa !5
  %262 = load i32, ptr %15, align 4, !tbaa !9
  %263 = load i32, ptr %14, align 4, !tbaa !9
  %264 = load i32, ptr %15, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %261, i32 noundef 4096, i32 noundef %262, i32 noundef %263, i32 noundef %264, i64 noundef 64)
  br label %265

265:                                              ; preds = %257
  %266 = load i32, ptr %22, align 4, !tbaa !9
  %267 = add i32 %266, 1
  store i32 %267, ptr %22, align 4, !tbaa !9
  br label %253, !llvm.loop !17

268:                                              ; preds = %253
  br label %269

269:                                              ; preds = %268, %245
  call void @llvm.lifetime.end.p0(i64 4, ptr %52) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %51) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %50) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %49) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %48) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %47) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %46) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %45) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %44) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %43) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %42) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %41) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %40) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %39) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %38) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %37) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %36) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %35) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %34) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %33) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %32) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %31) #5
  call void @llvm.lifetime.end.p0(i64 96, ptr %30) #5
  call void @llvm.lifetime.end.p0(i64 1, ptr %29) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %28) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %27) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %26) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %24) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #5
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #2

declare void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}
!15 = distinct !{!15, !13}
!16 = distinct !{!16, !13}
!17 = distinct !{!17, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c = external hidden unnamed_addr constant [24 x i32], align 16

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve(ptr noundef %0, ptr nocapture noundef readnone %1, ptr nocapture noundef readnone %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8, i32 noundef %9) local_unnamed_addr #0 {
  %.not = icmp eq i32 %9, 0
  %11 = add i32 %8, 1
  %12 = lshr i32 %11, 1
  %13 = select i1 %.not, i32 %8, i32 %12
  %14 = udiv i32 %7, %5
  %15 = urem i32 %7, %5
  %16 = icmp ne i32 %15, 0
  %17 = zext i1 %16 to i32
  %18 = add i32 %14, %17
  %19 = mul i32 %18, %8
  %20 = sub i32 %6, %19
  %21 = load i32, ptr @__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c, align 16
  %spec.select = select i1 %.not, i32 %20, i32 %21
  %22 = icmp ult i32 %spec.select, 16
  br i1 %22, label %23, label %.loopexit135

23:                                               ; preds = %10
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  br label %24

24:                                               ; preds = %23, %24
  %.0123136 = phi i32 [ %spec.select, %23 ], [ %25, %24 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -444579834, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef %.0123136, i32 noundef 127) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %4, i32 noundef %3, i32 noundef %4, i64 noundef 64) #2
  %25 = add i32 %.0123136, 1
  %exitcond.not = icmp eq i32 %25, 17
  br i1 %exitcond.not, label %.loopexit135, label %24, !llvm.loop !5

.loopexit135:                                     ; preds = %24, %10
  tail call void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef %3, i32 noundef 2, i8 noundef zeroext 0) #2
  %.not153 = icmp eq i32 %13, 0
  br i1 %.not153, label %._crit_edge145, label %.preheader134.lr.ph

.preheader134.lr.ph:                              ; preds = %.loopexit135
  %.not154 = icmp eq i32 %18, 0
  %26 = zext nneg i32 %spec.select to i64
  br i1 %.not154, label %._crit_edge145, label %.preheader134.lr.ph.split.us

.preheader134.lr.ph.split.us:                     ; preds = %.preheader134.lr.ph
  br i1 %22, label %.preheader134.us.us, label %.preheader134.lr.ph.split.us.split

.preheader134.us.us:                              ; preds = %.preheader134.lr.ph.split.us, %._crit_edge.split.us.us.us
  %.1144.us.us = phi i32 [ %50, %._crit_edge.split.us.us.us ], [ 0, %.preheader134.lr.ph.split.us ]
  %27 = shl i32 %.1144.us.us, 3
  %28 = mul i32 %.1144.us.us, %18
  %29 = add i32 %28, %20
  br label %.preheader.us.us.us

.preheader.us.us.us:                              ; preds = %.split.us142.us.us, %.preheader134.us.us
  %.0124138.us.us.us = phi i32 [ 0, %.preheader134.us.us ], [ %48, %.split.us142.us.us ]
  %30 = shl i32 %.0124138.us.us.us, 1
  %31 = add i32 %30, %27
  %32 = add i32 %29, %.0124138.us.us.us
  br label %33

33:                                               ; preds = %46, %.preheader.us.us.us
  %.0126137.us139.us.us = phi i32 [ 0, %.preheader.us.us.us ], [ %47, %46 ]
  br i1 %.not, label %39, label %34

34:                                               ; preds = %33
  %35 = add i32 %31, %.0126137.us139.us.us
  %36 = zext i32 %35 to i64
  %37 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c, i64 0, i64 %36
  %38 = load i32, ptr %37, align 4, !tbaa !7
  br label %39

39:                                               ; preds = %33, %34
  %.0127.us140.us.us = phi i32 [ %38, %34 ], [ %32, %33 ]
  %40 = icmp ult i32 %.0127.us140.us.us, 17
  br i1 %40, label %42, label %41

41:                                               ; preds = %39
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %0, i32 noundef %.0127.us140.us.us, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 6, i32 noundef 5, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 2, i8 noundef zeroext 0) #2
  br label %46

42:                                               ; preds = %39
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  %43 = zext nneg i32 %.0127.us140.us.us to i64
  %44 = sub nsw i64 %43, %26
  %45 = shl nsw i64 %44, 6
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %4, i32 noundef %3, i32 noundef %4, i64 noundef %45) #2
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -2055192570, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef 16, i32 noundef 127) #2
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %0, i32 noundef 16, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 6, i32 noundef 5, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 2, i8 noundef zeroext 0) #2
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -444579834, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef 16, i32 noundef 127) #2
  br label %46

46:                                               ; preds = %42, %41
  %47 = add i32 %.0126137.us139.us.us, 1
  %.not130.us141.us.us = icmp ugt i32 %47, %9
  br i1 %.not130.us141.us.us, label %.split.us142.us.us, label %33, !llvm.loop !11

.split.us142.us.us:                               ; preds = %46
  %48 = add nuw i32 %.0124138.us.us.us, 1
  %49 = icmp ult i32 %48, %18
  br i1 %49, label %.preheader.us.us.us, label %._crit_edge.split.us.us.us, !llvm.loop !12

._crit_edge.split.us.us.us:                       ; preds = %.split.us142.us.us
  %50 = add nuw i32 %.1144.us.us, 1
  %exitcond160.not = icmp eq i32 %50, %13
  br i1 %exitcond160.not, label %._crit_edge145, label %.preheader134.us.us, !llvm.loop !13

.preheader134.lr.ph.split.us.split:               ; preds = %.preheader134.lr.ph.split.us
  br i1 %.not, label %.preheader134.us.us150, label %.preheader134.us

.preheader134.us.us150:                           ; preds = %.preheader134.lr.ph.split.us.split, %._crit_edge.split.us148.split.us.us
  %.1144.us.us151 = phi i32 [ %56, %._crit_edge.split.us148.split.us.us ], [ 0, %.preheader134.lr.ph.split.us.split ]
  %51 = mul i32 %.1144.us.us151, %18
  %52 = add i32 %51, %20
  br label %.split.us.us.split.us.us.us

.split.us.us.split.us.us.us:                      ; preds = %.split.us.us.split.us.us.us, %.preheader134.us.us150
  %.0124138.us147.us.us = phi i32 [ 0, %.preheader134.us.us150 ], [ %54, %.split.us.us.split.us.us.us ]
  %53 = add i32 %52, %.0124138.us147.us.us
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %0, i32 noundef %53, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 6, i32 noundef 5, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 2, i8 noundef zeroext 0) #2
  %54 = add nuw i32 %.0124138.us147.us.us, 1
  %55 = icmp ult i32 %54, %18
  br i1 %55, label %.split.us.us.split.us.us.us, label %._crit_edge.split.us148.split.us.us, !llvm.loop !12

._crit_edge.split.us148.split.us.us:              ; preds = %.split.us.us.split.us.us.us
  %56 = add nuw i32 %.1144.us.us151, 1
  %exitcond159.not = icmp eq i32 %56, %13
  br i1 %exitcond159.not, label %._crit_edge145, label %.preheader134.us.us150, !llvm.loop !13

.preheader134.us:                                 ; preds = %.preheader134.lr.ph.split.us.split, %._crit_edge.split.us148.split
  %.1144.us = phi i32 [ %68, %._crit_edge.split.us148.split ], [ 0, %.preheader134.lr.ph.split.us.split ]
  %57 = shl i32 %.1144.us, 3
  br label %.preheader.us146

.preheader.us146:                                 ; preds = %.preheader134.us, %.split.us.us.split
  %.0124138.us147 = phi i32 [ 0, %.preheader134.us ], [ %66, %.split.us.us.split ]
  %58 = shl i32 %.0124138.us147, 1
  %59 = add i32 %58, %57
  br label %60

60:                                               ; preds = %60, %.preheader.us146
  %.0126137.us.us = phi i32 [ 0, %.preheader.us146 ], [ %65, %60 ]
  %61 = add i32 %59, %.0126137.us.us
  %62 = zext i32 %61 to i64
  %63 = getelementptr inbounds [24 x i32], ptr @__const.libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_sve.l_vr_c, i64 0, i64 %62
  %64 = load i32, ptr %63, align 4, !tbaa !7
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef %0, i32 noundef %64, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 6, i32 noundef 5, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 2, i8 noundef zeroext 0) #2
  %65 = add i32 %.0126137.us.us, 1
  %.not130.us.us = icmp ugt i32 %65, %9
  br i1 %.not130.us.us, label %.split.us.us.split, label %60, !llvm.loop !11

.split.us.us.split:                               ; preds = %60
  %66 = add nuw i32 %.0124138.us147, 1
  %67 = icmp ult i32 %66, %18
  br i1 %67, label %.preheader.us146, label %._crit_edge.split.us148.split, !llvm.loop !12

._crit_edge.split.us148.split:                    ; preds = %.split.us.us.split
  %68 = add nuw i32 %.1144.us, 1
  %exitcond158.not = icmp eq i32 %68, %13
  br i1 %exitcond158.not, label %._crit_edge145, label %.preheader134.us, !llvm.loop !13

._crit_edge145:                                   ; preds = %._crit_edge.split.us148.split, %._crit_edge.split.us148.split.us.us, %._crit_edge.split.us.us.us, %.preheader134.lr.ph, %.loopexit135
  br i1 %22, label %69, label %.loopexit

69:                                               ; preds = %._crit_edge145
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  br label %70

70:                                               ; preds = %69, %70
  %.2152 = phi i32 [ %spec.select, %69 ], [ %71, %70 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -2055192570, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef %.2152, i32 noundef 127) #2
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %4, i32 noundef %3, i32 noundef %4, i64 noundef 64) #2
  %71 = add i32 %.2152, 1
  %exitcond161.not = icmp eq i32 %71, 17
  br i1 %exitcond161.not, label %.loopexit, label %70, !llvm.loop !14

.loopexit:                                        ; preds = %70, %._crit_edge145
  ret void
}

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"int", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = distinct !{!11, !6}
!12 = distinct !{!12, !6}
!13 = distinct !{!13, !6}
!14 = distinct !{!14, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass