; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseImageSaveJpeg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::BitBuf" = type { i32, [2048 x [2 x i16]] }

@_ZN4Simd4Base10HuffmanYdcE = external dso_local constant <{ [12 x [2 x i16]], [244 x [2 x i16]] }>, align 16
@_ZN4Simd4Base11HuffmanUVdcE = external dso_local constant <{ [12 x [2 x i16]], [244 x [2 x i16]] }>, align 16
@_ZN4Simd4Base10HuffmanYacE = external dso_local constant [256 x [2 x i16]], align 16
@_ZN4Simd4Base11HuffmanUVacE = external dso_local constant [256 x [2 x i16]], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base6BitBufC2Ev(ptr noundef nonnull align 4 dereferenceable(8196)) unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base7GrayToYEPKhiiiPfi(ptr noundef, i32 noundef, i32 noundef, i32 noundef, ptr noundef, i32 noundef) #1

; Function Attrs: mustprogress uwtable
declare hidden noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196), ptr noundef, i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base19JpegProcessDuGrayUvERNS0_6BitBufE(ptr noundef nonnull align 4 dereferenceable(8196)) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd4Base6BitBuf4FullEj(ptr noundef nonnull align 4 dereferenceable(8196), i32 noundef) #1 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef, i64 noundef) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18JpegWriteBlockNv12ERNS_18OutputMemoryStreamEiiPKhiS4_iPKfS6_Pi(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, i32 noundef %4, ptr noundef %5, i32 noundef %6, ptr noundef %7, ptr noundef %8, ptr noundef %9) #2 {
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca ptr, align 8
  %15 = alloca i32, align 4
  %16 = alloca ptr, align 8
  %17 = alloca i32, align 4
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca ptr, align 8
  %21 = alloca ptr, align 8
  %22 = alloca ptr, align 8
  %23 = alloca ptr, align 8
  %24 = alloca [256 x float], align 16
  %25 = alloca [64 x float], align 16
  %26 = alloca [64 x float], align 16
  %27 = alloca i8, align 1
  %28 = alloca %"struct.Simd::Base::BitBuf", align 4
  %29 = alloca i32, align 4
  %30 = alloca i32, align 4
  %31 = alloca i32, align 4
  store ptr %0, ptr %11, align 8, !tbaa !5
  store i32 %1, ptr %12, align 4, !tbaa !9
  store i32 %2, ptr %13, align 4, !tbaa !9
  store ptr %3, ptr %14, align 8, !tbaa !5
  store i32 %4, ptr %15, align 4, !tbaa !9
  store ptr %5, ptr %16, align 8, !tbaa !5
  store i32 %6, ptr %17, align 4, !tbaa !9
  store ptr %7, ptr %18, align 8, !tbaa !5
  store ptr %8, ptr %19, align 8, !tbaa !5
  store ptr %9, ptr %20, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %21) #4
  %32 = load ptr, ptr %20, align 8, !tbaa !5
  %33 = getelementptr inbounds i32, ptr %32, i64 0
  store ptr %33, ptr %21, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #4
  %34 = load ptr, ptr %20, align 8, !tbaa !5
  %35 = getelementptr inbounds i32, ptr %34, i64 1
  store ptr %35, ptr %22, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %23) #4
  %36 = load ptr, ptr %20, align 8, !tbaa !5
  %37 = getelementptr inbounds i32, ptr %36, i64 2
  store ptr %37, ptr %23, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1024, ptr %24) #4
  call void @llvm.lifetime.start.p0(i64 256, ptr %25) #4
  call void @llvm.lifetime.start.p0(i64 256, ptr %26) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %27) #4
  %38 = load ptr, ptr %16, align 8, !tbaa !5
  %39 = icmp eq ptr %38, null
  %40 = zext i1 %39 to i8
  store i8 %40, ptr %27, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8196, ptr %28) #4
  call void @_ZN4Simd4Base6BitBufC2Ev(ptr noundef nonnull align 4 dereferenceable(8196) %28)
  call void @llvm.lifetime.start.p0(i64 4, ptr %29) #4
  store i32 0, ptr %29, align 4, !tbaa !9
  br label %41

41:                                               ; preds = %138, %10
  %42 = load i32, ptr %29, align 4, !tbaa !9
  %43 = load i32, ptr %13, align 4, !tbaa !9
  %44 = icmp slt i32 %42, %43
  br i1 %44, label %46, label %45

45:                                               ; preds = %41
  store i32 2, ptr %30, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %29) #4
  br label %141

46:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 4, ptr %31) #4
  store i32 0, ptr %31, align 4, !tbaa !9
  br label %47

47:                                               ; preds = %134, %46
  %48 = load i32, ptr %31, align 4, !tbaa !9
  %49 = load i32, ptr %12, align 4, !tbaa !9
  %50 = icmp slt i32 %48, %49
  br i1 %50, label %52, label %51

51:                                               ; preds = %47
  store i32 5, ptr %30, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %31) #4
  br label %137

52:                                               ; preds = %47
  %53 = load ptr, ptr %14, align 8, !tbaa !5
  %54 = load i32, ptr %31, align 4, !tbaa !9
  %55 = sext i32 %54 to i64
  %56 = getelementptr inbounds i8, ptr %53, i64 %55
  %57 = load i32, ptr %15, align 4, !tbaa !9
  %58 = load i32, ptr %13, align 4, !tbaa !9
  %59 = load i32, ptr %29, align 4, !tbaa !9
  %60 = sub nsw i32 %58, %59
  %61 = load i32, ptr %12, align 4, !tbaa !9
  %62 = load i32, ptr %31, align 4, !tbaa !9
  %63 = sub nsw i32 %61, %62
  %64 = getelementptr inbounds [256 x float], ptr %24, i64 0, i64 0
  call void @_ZN4Simd4Base7GrayToYEPKhiiiPfi(ptr noundef %56, i32 noundef %57, i32 noundef %60, i32 noundef %63, ptr noundef %64, i32 noundef 16)
  %65 = getelementptr inbounds [256 x float], ptr %24, i64 0, i64 0
  %66 = getelementptr inbounds float, ptr %65, i64 0
  %67 = load ptr, ptr %18, align 8, !tbaa !5
  %68 = load ptr, ptr %21, align 8, !tbaa !5
  %69 = load i32, ptr %68, align 4, !tbaa !9
  %70 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %66, i32 noundef 16, ptr noundef %67, i32 noundef %69, ptr noundef @_ZN4Simd4Base10HuffmanYdcE, ptr noundef @_ZN4Simd4Base10HuffmanYacE)
  %71 = load ptr, ptr %21, align 8, !tbaa !5
  store i32 %70, ptr %71, align 4, !tbaa !9
  %72 = getelementptr inbounds [256 x float], ptr %24, i64 0, i64 0
  %73 = getelementptr inbounds float, ptr %72, i64 8
  %74 = load ptr, ptr %18, align 8, !tbaa !5
  %75 = load ptr, ptr %21, align 8, !tbaa !5
  %76 = load i32, ptr %75, align 4, !tbaa !9
  %77 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %73, i32 noundef 16, ptr noundef %74, i32 noundef %76, ptr noundef @_ZN4Simd4Base10HuffmanYdcE, ptr noundef @_ZN4Simd4Base10HuffmanYacE)
  %78 = load ptr, ptr %21, align 8, !tbaa !5
  store i32 %77, ptr %78, align 4, !tbaa !9
  %79 = getelementptr inbounds [256 x float], ptr %24, i64 0, i64 0
  %80 = getelementptr inbounds float, ptr %79, i64 128
  %81 = load ptr, ptr %18, align 8, !tbaa !5
  %82 = load ptr, ptr %21, align 8, !tbaa !5
  %83 = load i32, ptr %82, align 4, !tbaa !9
  %84 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %80, i32 noundef 16, ptr noundef %81, i32 noundef %83, ptr noundef @_ZN4Simd4Base10HuffmanYdcE, ptr noundef @_ZN4Simd4Base10HuffmanYacE)
  %85 = load ptr, ptr %21, align 8, !tbaa !5
  store i32 %84, ptr %85, align 4, !tbaa !9
  %86 = getelementptr inbounds [256 x float], ptr %24, i64 0, i64 0
  %87 = getelementptr inbounds float, ptr %86, i64 136
  %88 = load ptr, ptr %18, align 8, !tbaa !5
  %89 = load ptr, ptr %21, align 8, !tbaa !5
  %90 = load i32, ptr %89, align 4, !tbaa !9
  %91 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %87, i32 noundef 16, ptr noundef %88, i32 noundef %90, ptr noundef @_ZN4Simd4Base10HuffmanYdcE, ptr noundef @_ZN4Simd4Base10HuffmanYacE)
  %92 = load ptr, ptr %21, align 8, !tbaa !5
  store i32 %91, ptr %92, align 4, !tbaa !9
  %93 = load i8, ptr %27, align 1, !tbaa !11, !range !13, !noundef !14
  %94 = trunc i8 %93 to i1
  br i1 %94, label %95, label %96

95:                                               ; preds = %52
  call void @_ZN4Simd4Base19JpegProcessDuGrayUvERNS0_6BitBufE(ptr noundef nonnull align 4 dereferenceable(8196) %28)
  br label %124

96:                                               ; preds = %52
  %97 = load ptr, ptr %16, align 8, !tbaa !5
  %98 = load i32, ptr %31, align 4, !tbaa !9
  %99 = sext i32 %98 to i64
  %100 = getelementptr inbounds i8, ptr %97, i64 %99
  %101 = load i32, ptr %17, align 4, !tbaa !9
  %102 = load i32, ptr %13, align 4, !tbaa !9
  %103 = load i32, ptr %29, align 4, !tbaa !9
  %104 = sub nsw i32 %102, %103
  %105 = call noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef %104)
  %106 = load i32, ptr %12, align 4, !tbaa !9
  %107 = load i32, ptr %31, align 4, !tbaa !9
  %108 = sub nsw i32 %106, %107
  %109 = call noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef %108)
  %110 = getelementptr inbounds [64 x float], ptr %25, i64 0, i64 0
  %111 = getelementptr inbounds [64 x float], ptr %26, i64 0, i64 0
  call void @_ZN4Simd4Base8Nv12ToUvEPKhiiiPfS3_(ptr noundef %100, i32 noundef %101, i32 noundef %105, i32 noundef %109, ptr noundef %110, ptr noundef %111)
  %112 = getelementptr inbounds [64 x float], ptr %25, i64 0, i64 0
  %113 = load ptr, ptr %19, align 8, !tbaa !5
  %114 = load ptr, ptr %22, align 8, !tbaa !5
  %115 = load i32, ptr %114, align 4, !tbaa !9
  %116 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %112, i32 noundef 8, ptr noundef %113, i32 noundef %115, ptr noundef @_ZN4Simd4Base11HuffmanUVdcE, ptr noundef @_ZN4Simd4Base11HuffmanUVacE)
  %117 = load ptr, ptr %22, align 8, !tbaa !5
  store i32 %116, ptr %117, align 4, !tbaa !9
  %118 = getelementptr inbounds [64 x float], ptr %26, i64 0, i64 0
  %119 = load ptr, ptr %19, align 8, !tbaa !5
  %120 = load ptr, ptr %23, align 8, !tbaa !5
  %121 = load i32, ptr %120, align 4, !tbaa !9
  %122 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %28, ptr noundef %118, i32 noundef 8, ptr noundef %119, i32 noundef %121, ptr noundef @_ZN4Simd4Base11HuffmanUVdcE, ptr noundef @_ZN4Simd4Base11HuffmanUVacE)
  %123 = load ptr, ptr %23, align 8, !tbaa !5
  store i32 %122, ptr %123, align 4, !tbaa !9
  br label %124

124:                                              ; preds = %96, %95
  %125 = call noundef zeroext i1 @_ZNK4Simd4Base6BitBuf4FullEj(ptr noundef nonnull align 4 dereferenceable(8196) %28, i32 noundef 1024)
  br i1 %125, label %126, label %133

126:                                              ; preds = %124
  %127 = load ptr, ptr %11, align 8, !tbaa !5
  %128 = getelementptr inbounds %"struct.Simd::Base::BitBuf", ptr %28, i32 0, i32 1
  %129 = getelementptr inbounds [2048 x [2 x i16]], ptr %128, i64 0, i64 0
  %130 = getelementptr inbounds %"struct.Simd::Base::BitBuf", ptr %28, i32 0, i32 0
  %131 = load i32, ptr %130, align 4, !tbaa !15
  %132 = zext i32 %131 to i64
  call void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56) %127, ptr noundef %129, i64 noundef %132)
  call void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196) %28)
  br label %133

133:                                              ; preds = %126, %124
  br label %134

134:                                              ; preds = %133
  %135 = load i32, ptr %31, align 4, !tbaa !9
  %136 = add nsw i32 %135, 16
  store i32 %136, ptr %31, align 4, !tbaa !9
  br label %47, !llvm.loop !17

137:                                              ; preds = %51
  br label %138

138:                                              ; preds = %137
  %139 = load i32, ptr %29, align 4, !tbaa !9
  %140 = add nsw i32 %139, 16
  store i32 %140, ptr %29, align 4, !tbaa !9
  br label %41, !llvm.loop !19

141:                                              ; preds = %45
  %142 = load ptr, ptr %11, align 8, !tbaa !5
  %143 = getelementptr inbounds %"struct.Simd::Base::BitBuf", ptr %28, i32 0, i32 1
  %144 = getelementptr inbounds [2048 x [2 x i16]], ptr %143, i64 0, i64 0
  %145 = getelementptr inbounds %"struct.Simd::Base::BitBuf", ptr %28, i32 0, i32 0
  %146 = load i32, ptr %145, align 4, !tbaa !15
  %147 = zext i32 %146 to i64
  call void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56) %142, ptr noundef %144, i64 noundef %147)
  call void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196) %28)
  call void @llvm.lifetime.end.p0(i64 8196, ptr %28) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %27) #4
  call void @llvm.lifetime.end.p0(i64 256, ptr %26) #4
  call void @llvm.lifetime.end.p0(i64 256, ptr %25) #4
  call void @llvm.lifetime.end.p0(i64 1024, ptr %24) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %23) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %21) #4
  ret void
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8Nv12ToUvEPKhiiiPfS3_(ptr noundef, i32 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!16, !10, i64 0}
!16 = !{!"_ZTSN4Simd4Base6BitBufE", !10, i64 0, !7, i64 4}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Base::BitBuf" = type { i32, [2048 x [2 x i16]] }

@_ZN4Simd4Base10HuffmanYdcE = external dso_local constant <{ [12 x [2 x i16]], [244 x [2 x i16]] }>, align 16
@_ZN4Simd4Base11HuffmanUVdcE = external dso_local constant <{ [12 x [2 x i16]], [244 x [2 x i16]] }>, align 16
@_ZN4Simd4Base10HuffmanYacE = external dso_local constant [256 x [2 x i16]], align 16
@_ZN4Simd4Base11HuffmanUVacE = external dso_local constant [256 x [2 x i16]], align 16

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base6BitBufC2Ev(ptr noundef nonnull align 4 dereferenceable(8196)) unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base7GrayToYEPKhiiiPfi(ptr noundef, i32 noundef, i32 noundef, i32 noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare hidden noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196), ptr noundef, i32 noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base19JpegProcessDuGrayUvERNS0_6BitBufE(ptr noundef nonnull align 4 dereferenceable(8196)) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Simd4Base6BitBuf4FullEj(ptr noundef nonnull align 4 dereferenceable(8196), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef, i64 noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base18JpegWriteBlockNv12ERNS_18OutputMemoryStreamEiiPKhiS4_iPKfS6_Pi(ptr noundef nonnull align 8 dereferenceable(56) %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, i32 noundef %4, ptr noundef %5, i32 noundef %6, ptr noundef %7, ptr noundef %8, ptr nocapture noundef %9) local_unnamed_addr #2 {
  %11 = alloca [256 x float], align 16
  %12 = alloca [64 x float], align 16
  %13 = alloca [64 x float], align 16
  %14 = alloca %"struct.Simd::Base::BitBuf", align 4
  %15 = getelementptr inbounds i8, ptr %9, i64 4
  %16 = getelementptr inbounds i8, ptr %9, i64 8
  call void @llvm.lifetime.start.p0(i64 1024, ptr nonnull %11) #4
  call void @llvm.lifetime.start.p0(i64 256, ptr nonnull %12) #4
  call void @llvm.lifetime.start.p0(i64 256, ptr nonnull %13) #4
  %17 = icmp eq ptr %5, null
  call void @llvm.lifetime.start.p0(i64 8196, ptr nonnull %14) #4
  call void @_ZN4Simd4Base6BitBufC2Ev(ptr noundef nonnull align 4 dereferenceable(8196) %14)
  %18 = icmp sgt i32 %2, 0
  br i1 %18, label %.preheader.lr.ph, label %._crit_edge50

.preheader.lr.ph:                                 ; preds = %10
  %19 = icmp sgt i32 %1, 0
  %20 = getelementptr inbounds i8, ptr %11, i64 32
  %21 = getelementptr inbounds i8, ptr %11, i64 512
  %22 = getelementptr inbounds i8, ptr %11, i64 544
  %23 = getelementptr inbounds i8, ptr %14, i64 4
  br i1 %19, label %.preheader.us, label %._crit_edge50

.preheader.us:                                    ; preds = %.preheader.lr.ph, %._crit_edge.us
  %.04449.us = phi i32 [ %51, %._crit_edge.us ], [ 0, %.preheader.lr.ph ]
  %24 = sub nsw i32 %2, %.04449.us
  br label %25

25:                                               ; preds = %.preheader.us, %48
  %indvars.iv = phi i64 [ 0, %.preheader.us ], [ %indvars.iv.next, %48 ]
  %26 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv
  %27 = trunc i64 %indvars.iv to i32
  %28 = sub i32 %1, %27
  call void @_ZN4Simd4Base7GrayToYEPKhiiiPfi(ptr noundef %26, i32 noundef %4, i32 noundef %24, i32 noundef %28, ptr noundef nonnull %11, i32 noundef 16)
  %29 = load i32, ptr %9, align 4, !tbaa !5
  %30 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %11, i32 noundef 16, ptr noundef %7, i32 noundef %29, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYdcE, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYacE)
  store i32 %30, ptr %9, align 4, !tbaa !5
  %31 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %20, i32 noundef 16, ptr noundef %7, i32 noundef %30, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYdcE, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYacE)
  store i32 %31, ptr %9, align 4, !tbaa !5
  %32 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %21, i32 noundef 16, ptr noundef %7, i32 noundef %31, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYdcE, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYacE)
  store i32 %32, ptr %9, align 4, !tbaa !5
  %33 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %22, i32 noundef 16, ptr noundef %7, i32 noundef %32, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYdcE, ptr noundef nonnull @_ZN4Simd4Base10HuffmanYacE)
  store i32 %33, ptr %9, align 4, !tbaa !5
  br i1 %17, label %42, label %34

34:                                               ; preds = %25
  %35 = getelementptr inbounds i8, ptr %5, i64 %indvars.iv
  %36 = call noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef %24)
  %37 = call noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef %28)
  call void @_ZN4Simd4Base8Nv12ToUvEPKhiiiPfS3_(ptr noundef nonnull %35, i32 noundef %6, i32 noundef %36, i32 noundef %37, ptr noundef nonnull %12, ptr noundef nonnull %13)
  %38 = load i32, ptr %15, align 4, !tbaa !5
  %39 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %12, i32 noundef 8, ptr noundef %8, i32 noundef %38, ptr noundef nonnull @_ZN4Simd4Base11HuffmanUVdcE, ptr noundef nonnull @_ZN4Simd4Base11HuffmanUVacE)
  store i32 %39, ptr %15, align 4, !tbaa !5
  %40 = load i32, ptr %16, align 4, !tbaa !5
  %41 = call noundef i32 @_ZN4Simd4BaseL13JpegProcessDuERNS0_6BitBufEPfiPKfiPA2_KtS8_(ptr noundef nonnull align 4 dereferenceable(8196) %14, ptr noundef nonnull %13, i32 noundef 8, ptr noundef %8, i32 noundef %40, ptr noundef nonnull @_ZN4Simd4Base11HuffmanUVdcE, ptr noundef nonnull @_ZN4Simd4Base11HuffmanUVacE)
  store i32 %41, ptr %16, align 4, !tbaa !5
  br label %43

42:                                               ; preds = %25
  call void @_ZN4Simd4Base19JpegProcessDuGrayUvERNS0_6BitBufE(ptr noundef nonnull align 4 dereferenceable(8196) %14)
  br label %43

43:                                               ; preds = %42, %34
  %44 = call noundef zeroext i1 @_ZNK4Simd4Base6BitBuf4FullEj(ptr noundef nonnull align 4 dereferenceable(8196) %14, i32 noundef 1024)
  br i1 %44, label %45, label %48

45:                                               ; preds = %43
  %46 = load i32, ptr %14, align 4, !tbaa !9
  %47 = zext i32 %46 to i64
  call void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull %23, i64 noundef %47)
  call void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196) %14)
  br label %48

48:                                               ; preds = %45, %43
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 16
  %49 = trunc nuw i64 %indvars.iv.next to i32
  %50 = icmp slt i32 %49, %1
  br i1 %50, label %25, label %._crit_edge.us, !llvm.loop !11

._crit_edge.us:                                   ; preds = %48
  %51 = add nuw nsw i32 %.04449.us, 16
  %52 = icmp slt i32 %51, %2
  br i1 %52, label %.preheader.us, label %._crit_edge50, !llvm.loop !13

._crit_edge50:                                    ; preds = %._crit_edge.us, %.preheader.lr.ph, %10
  %53 = getelementptr inbounds i8, ptr %14, i64 4
  %54 = load i32, ptr %14, align 4, !tbaa !9
  %55 = zext i32 %54 to i64
  call void @_ZN4Simd4Base9WriteBitsERNS_18OutputMemoryStreamEPA2_Ktm(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull %53, i64 noundef %55)
  call void @_ZN4Simd4Base6BitBuf5ClearEv(ptr noundef nonnull align 4 dereferenceable(8196) %14)
  call void @llvm.lifetime.end.p0(i64 8196, ptr nonnull %14) #4
  call void @llvm.lifetime.end.p0(i64 256, ptr nonnull %13) #4
  call void @llvm.lifetime.end.p0(i64 256, ptr nonnull %12) #4
  call void @llvm.lifetime.end.p0(i64 1024, ptr nonnull %11) #4
  ret void
}

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8Nv12ToUvEPKhiiiPfS3_(ptr noundef, i32 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN4Simd4Base6UvSizeEi(i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 0}
!10 = !{!"_ZTSN4Simd4Base6BitBufE", !6, i64 0, !7, i64 4}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass