; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_compute_3reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) #0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i8, align 1
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i16 %4, ptr %11, align 2, !tbaa !11
  store i32 %5, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #3
  %15 = load i32, ptr %12, align 4, !tbaa !9
  %16 = icmp ne i32 %15, 0
  %17 = zext i1 %16 to i64
  %18 = select i1 %16, i32 120, i32 121
  %19 = trunc i32 %18 to i8
  store i8 %19, ptr %14, align 1, !tbaa !13
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  %21 = load ptr, ptr %7, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %20, ptr noundef %21)
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %43, %6
  %23 = load i32, ptr %13, align 4, !tbaa !9
  %24 = icmp ult i32 %23, 16
  br i1 %24, label %25, label %46

25:                                               ; preds = %22
  %26 = load i32, ptr %10, align 4, !tbaa !9
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %35

28:                                               ; preds = %25
  %29 = load ptr, ptr %8, align 8, !tbaa !5
  %30 = load i32, ptr %9, align 4, !tbaa !9
  %31 = load i8, ptr %14, align 1, !tbaa !13
  %32 = load i32, ptr %13, align 4, !tbaa !9
  %33 = load i16, ptr %11, align 2, !tbaa !11
  %34 = zext i16 %33 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %29, i32 noundef %30, i8 noundef signext %31, i32 noundef %32, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %34)
  br label %42

35:                                               ; preds = %25
  %36 = load ptr, ptr %8, align 8, !tbaa !5
  %37 = load i32, ptr %9, align 4, !tbaa !9
  %38 = load i8, ptr %14, align 1, !tbaa !13
  %39 = load i32, ptr %13, align 4, !tbaa !9
  %40 = load i16, ptr %11, align 2, !tbaa !11
  %41 = zext i16 %40 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %36, i32 noundef %37, i8 noundef signext %38, i32 noundef %39, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %41)
  br label %42

42:                                               ; preds = %35, %28
  br label %43

43:                                               ; preds = %42
  %44 = load i32, ptr %13, align 4, !tbaa !9
  %45 = add i32 %44, 1
  store i32 %45, ptr %13, align 4, !tbaa !9
  br label %22, !llvm.loop !14

46:                                               ; preds = %22
  %47 = load i32, ptr %10, align 4, !tbaa !9
  %48 = icmp ne i32 %47, 0
  br i1 %48, label %64, label %49

49:                                               ; preds = %46
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %50

50:                                               ; preds = %60, %49
  %51 = load i32, ptr %13, align 4, !tbaa !9
  %52 = icmp ult i32 %51, 16
  br i1 %52, label %53, label %63

53:                                               ; preds = %50
  %54 = load ptr, ptr %8, align 8, !tbaa !5
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = load i8, ptr %14, align 1, !tbaa !13
  %57 = load i32, ptr %13, align 4, !tbaa !9
  %58 = load i16, ptr %11, align 2, !tbaa !11
  %59 = zext i16 %58 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %54, i32 noundef %55, i8 noundef signext %56, i32 noundef 0, i32 noundef %57, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %59)
  br label %60

60:                                               ; preds = %53
  %61 = load i32, ptr %13, align 4, !tbaa !9
  %62 = add i32 %61, 1
  store i32 %62, ptr %13, align 4, !tbaa !9
  br label %50, !llvm.loop !16

63:                                               ; preds = %50
  br label %64

64:                                               ; preds = %63, %46
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %86, %64
  %66 = load i32, ptr %13, align 4, !tbaa !9
  %67 = icmp ult i32 %66, 16
  br i1 %67, label %68, label %89

68:                                               ; preds = %65
  %69 = load i32, ptr %10, align 4, !tbaa !9
  %70 = icmp ne i32 %69, 0
  br i1 %70, label %71, label %78

71:                                               ; preds = %68
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = load i32, ptr %9, align 4, !tbaa !9
  %74 = load i8, ptr %14, align 1, !tbaa !13
  %75 = load i32, ptr %13, align 4, !tbaa !9
  %76 = load i16, ptr %11, align 2, !tbaa !11
  %77 = zext i16 %76 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %72, i32 noundef %73, i8 noundef signext %74, i32 noundef 0, i32 noundef 255, i32 noundef %75, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %77)
  br label %85

78:                                               ; preds = %68
  %79 = load ptr, ptr %8, align 8, !tbaa !5
  %80 = load i32, ptr %9, align 4, !tbaa !9
  %81 = load i8, ptr %14, align 1, !tbaa !13
  %82 = load i32, ptr %13, align 4, !tbaa !9
  %83 = load i16, ptr %11, align 2, !tbaa !11
  %84 = zext i16 %83 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %79, i32 noundef %80, i8 noundef signext %81, i32 noundef 0, i32 noundef 0, i32 noundef %82, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %84)
  br label %85

85:                                               ; preds = %78, %71
  br label %86

86:                                               ; preds = %85
  %87 = load i32, ptr %13, align 4, !tbaa !9
  %88 = add i32 %87, 1
  store i32 %88, ptr %13, align 4, !tbaa !9
  br label %65, !llvm.loop !17

89:                                               ; preds = %65
  %90 = load ptr, ptr %8, align 8, !tbaa !5
  %91 = load ptr, ptr %7, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %90, ptr noundef %91)
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_compute_3reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) local_unnamed_addr #0 {
  %.not = icmp eq i32 %5, 0
  %7 = select i1 %.not, i8 121, i8 120
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %.not39 = icmp eq i32 %3, 0
  %8 = zext i16 %4 to i32
  br i1 %.not39, label %.split45.us.preheader, label %.split45.preheader

.split45.preheader:                               ; preds = %6
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 1, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 2, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 3, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 4, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 5, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 6, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 7, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 8, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 9, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 10, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 11, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 12, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 13, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 14, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 15, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  br label %.split47.us

.split45.us.preheader:                            ; preds = %6
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 1, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 2, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 3, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 4, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 5, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 6, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 7, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 8, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 9, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 10, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 11, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 12, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 13, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 14, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 15, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 1, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 2, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 3, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 4, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 5, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 6, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 7, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 8, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 9, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 10, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 11, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 12, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 13, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 14, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef 15, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  br label %.split47.us

.split47.us:                                      ; preds = %.split45.preheader, %.split45.us.preheader
  %.sink64 = phi i32 [ 255, %.split45.preheader ], [ 0, %.split45.us.preheader ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 1, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 2, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 3, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 4, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 5, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 6, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 7, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 8, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 9, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 10, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 11, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 12, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 13, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 14, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef 0, i32 noundef %.sink64, i32 noundef 15, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %8) #2
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass