; LLVM IR from abeaumont/competitive-programming :: cses/1739.ll (Z6toggleii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@k = external dso_local global i32, align 4
@t = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6toggleii(i32 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %9 = load i32, ptr @k, align 4, !tbaa !5
  %10 = sub nsw i32 %9, 1
  %11 = load i32, ptr %3, align 4, !tbaa !5
  %12 = add nsw i32 %11, %10
  store i32 %12, ptr %3, align 4, !tbaa !5
  %13 = load i32, ptr @k, align 4, !tbaa !5
  %14 = sub nsw i32 %13, 1
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = add nsw i32 %15, %14
  store i32 %16, ptr %4, align 4, !tbaa !5
  %17 = load i32, ptr %3, align 4, !tbaa !5
  %18 = sext i32 %17 to i64
  %19 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %18) #2
  %20 = load i32, ptr %4, align 4, !tbaa !5
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #2
  %23 = load i32, ptr %22, align 4, !tbaa !5
  %24 = icmp ne i32 %23, 0
  %25 = xor i1 %24, true
  %26 = zext i1 %25 to i32
  %27 = load i32, ptr %3, align 4, !tbaa !5
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %28) #2
  %30 = load i32, ptr %4, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #2
  store i32 %26, ptr %32, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  %33 = load i32, ptr %4, align 4, !tbaa !5
  %34 = sdiv i32 %33, 2
  store i32 %34, ptr %5, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %64, %2
  %36 = load i32, ptr %5, align 4, !tbaa !5
  %37 = icmp sgt i32 %36, 0
  br i1 %37, label %39, label %38

38:                                               ; preds = %35
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  br label %67

39:                                               ; preds = %35
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %41) #2
  %43 = load i32, ptr %5, align 4, !tbaa !5
  %44 = mul nsw i32 %43, 2
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %45) #2
  %47 = load i32, ptr %46, align 4, !tbaa !5
  %48 = load i32, ptr %3, align 4, !tbaa !5
  %49 = sext i32 %48 to i64
  %50 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %49) #2
  %51 = load i32, ptr %5, align 4, !tbaa !5
  %52 = mul nsw i32 %51, 2
  %53 = add nsw i32 %52, 1
  %54 = sext i32 %53 to i64
  %55 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %54) #2
  %56 = load i32, ptr %55, align 4, !tbaa !5
  %57 = add nsw i32 %47, %56
  %58 = load i32, ptr %3, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %59) #2
  %61 = load i32, ptr %5, align 4, !tbaa !5
  %62 = sext i32 %61 to i64
  %63 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %62) #2
  store i32 %57, ptr %63, align 4, !tbaa !5
  br label %64

64:                                               ; preds = %39
  %65 = load i32, ptr %5, align 4, !tbaa !5
  %66 = sdiv i32 %65, 2
  store i32 %66, ptr %5, align 4, !tbaa !5
  br label %35, !llvm.loop !9

67:                                               ; preds = %38
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  %68 = load i32, ptr %3, align 4, !tbaa !5
  %69 = sdiv i32 %68, 2
  store i32 %69, ptr %6, align 4, !tbaa !5
  br label %70

70:                                               ; preds = %134, %67
  %71 = load i32, ptr %6, align 4, !tbaa !5
  %72 = icmp sgt i32 %71, 0
  br i1 %72, label %74, label %73

73:                                               ; preds = %70
  store i32 5, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %137

74:                                               ; preds = %70
  %75 = load i32, ptr %6, align 4, !tbaa !5
  %76 = mul nsw i32 %75, 2
  %77 = sext i32 %76 to i64
  %78 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %77) #2
  %79 = load i32, ptr %4, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %80) #2
  %82 = load i32, ptr %81, align 4, !tbaa !5
  %83 = load i32, ptr %6, align 4, !tbaa !5
  %84 = mul nsw i32 %83, 2
  %85 = add nsw i32 %84, 1
  %86 = sext i32 %85 to i64
  %87 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %86) #2
  %88 = load i32, ptr %4, align 4, !tbaa !5
  %89 = sext i32 %88 to i64
  %90 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %87, i64 noundef %89) #2
  %91 = load i32, ptr %90, align 4, !tbaa !5
  %92 = add nsw i32 %82, %91
  %93 = load i32, ptr %6, align 4, !tbaa !5
  %94 = sext i32 %93 to i64
  %95 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %94) #2
  %96 = load i32, ptr %4, align 4, !tbaa !5
  %97 = sext i32 %96 to i64
  %98 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %95, i64 noundef %97) #2
  store i32 %92, ptr %98, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %99 = load i32, ptr %4, align 4, !tbaa !5
  %100 = sdiv i32 %99, 2
  store i32 %100, ptr %8, align 4, !tbaa !5
  br label %101

101:                                              ; preds = %130, %74
  %102 = load i32, ptr %8, align 4, !tbaa !5
  %103 = icmp sgt i32 %102, 0
  br i1 %103, label %105, label %104

104:                                              ; preds = %101
  store i32 8, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  br label %133

105:                                              ; preds = %101
  %106 = load i32, ptr %6, align 4, !tbaa !5
  %107 = sext i32 %106 to i64
  %108 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %107) #2
  %109 = load i32, ptr %8, align 4, !tbaa !5
  %110 = mul nsw i32 %109, 2
  %111 = sext i32 %110 to i64
  %112 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %108, i64 noundef %111) #2
  %113 = load i32, ptr %112, align 4, !tbaa !5
  %114 = load i32, ptr %6, align 4, !tbaa !5
  %115 = sext i32 %114 to i64
  %116 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %115) #2
  %117 = load i32, ptr %8, align 4, !tbaa !5
  %118 = mul nsw i32 %117, 2
  %119 = add nsw i32 %118, 1
  %120 = sext i32 %119 to i64
  %121 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %116, i64 noundef %120) #2
  %122 = load i32, ptr %121, align 4, !tbaa !5
  %123 = add nsw i32 %113, %122
  %124 = load i32, ptr %6, align 4, !tbaa !5
  %125 = sext i32 %124 to i64
  %126 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %125) #2
  %127 = load i32, ptr %8, align 4, !tbaa !5
  %128 = sext i32 %127 to i64
  %129 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %126, i64 noundef %128) #2
  store i32 %123, ptr %129, align 4, !tbaa !5
  br label %130

130:                                              ; preds = %105
  %131 = load i32, ptr %8, align 4, !tbaa !5
  %132 = sdiv i32 %131, 2
  store i32 %132, ptr %8, align 4, !tbaa !5
  br label %101, !llvm.loop !11

133:                                              ; preds = %104
  br label %134

134:                                              ; preds = %133
  %135 = load i32, ptr %6, align 4, !tbaa !5
  %136 = sdiv i32 %135, 2
  store i32 %136, ptr %6, align 4, !tbaa !5
  br label %70, !llvm.loop !12

137:                                              ; preds = %73
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@k = external dso_local local_unnamed_addr global i32, align 4
@t = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6toggleii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = load i32, ptr @k, align 4, !tbaa !5
  %.fr46 = freeze i32 %3
  %4 = add i32 %.fr46, -1
  %5 = add nsw i32 %4, %0
  %6 = add i32 %4, %1
  %7 = sext i32 %5 to i64
  %8 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %7) #1
  %9 = sext i32 %6 to i64
  %10 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %9) #1
  %11 = load i32, ptr %10, align 4, !tbaa !5
  %.not = icmp eq i32 %11, 0
  %12 = zext i1 %.not to i32
  %13 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %7) #1
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %9) #1
  store i32 %12, ptr %14, align 4, !tbaa !5
  %15 = sdiv i32 %6, 2
  %16 = icmp sgt i32 %6, 1
  br i1 %16, label %.lr.ph, label %._crit_edge.thread

._crit_edge:                                      ; preds = %.lr.ph
  %17 = icmp sgt i32 %5, 1
  br i1 %17, label %.lr.ph42, label %._crit_edge43

._crit_edge.thread:                               ; preds = %2
  %18 = icmp sgt i32 %5, 1
  br i1 %18, label %.lr.ph42.thread, label %._crit_edge43

.lr.ph42.thread:                                  ; preds = %._crit_edge.thread
  %19 = lshr i32 %5, 1
  br label %.lr.ph42.split.preheader

.lr.ph42:                                         ; preds = %._crit_edge
  %20 = lshr i32 %5, 1
  br i1 %16, label %.lr.ph38.us, label %.lr.ph42.split.preheader

.lr.ph42.split.preheader:                         ; preds = %.lr.ph42.thread, %.lr.ph42
  %.03340.ph = phi i32 [ %20, %.lr.ph42 ], [ %19, %.lr.ph42.thread ]
  br label %.lr.ph42.split

.lr.ph38.us:                                      ; preds = %.lr.ph42, %._crit_edge39.us
  %.03340.us = phi i32 [ %51, %._crit_edge39.us ], [ %20, %.lr.ph42 ]
  %21 = shl nuw nsw i32 %.03340.us, 1
  %22 = zext nneg i32 %21 to i64
  %23 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %22) #1
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %9) #1
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = or disjoint i32 %21, 1
  %27 = zext nneg i32 %26 to i64
  %28 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %27) #1
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %9) #1
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %31 = add nsw i32 %30, %25
  %32 = zext nneg i32 %.03340.us to i64
  %33 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %32) #1
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %9) #1
  store i32 %31, ptr %34, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %.lr.ph38.us, %35
  %.036.us = phi i32 [ %15, %.lr.ph38.us ], [ %50, %35 ]
  %36 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %32) #1
  %37 = shl nuw nsw i32 %.036.us, 1
  %38 = zext nneg i32 %37 to i64
  %39 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %38) #1
  %40 = load i32, ptr %39, align 4, !tbaa !5
  %41 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %32) #1
  %42 = or disjoint i32 %37, 1
  %43 = zext nneg i32 %42 to i64
  %44 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %43) #1
  %45 = load i32, ptr %44, align 4, !tbaa !5
  %46 = add nsw i32 %45, %40
  %47 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %32) #1
  %48 = zext nneg i32 %.036.us to i64
  %49 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %47, i64 noundef %48) #1
  store i32 %46, ptr %49, align 4, !tbaa !5
  %50 = lshr i32 %.036.us, 1
  %.not48 = icmp ult i32 %.036.us, 2
  br i1 %.not48, label %._crit_edge39.us, label %35, !llvm.loop !9

._crit_edge39.us:                                 ; preds = %35
  %51 = lshr i32 %.03340.us, 1
  %.not49 = icmp ult i32 %.03340.us, 2
  br i1 %.not49, label %._crit_edge43, label %.lr.ph38.us, !llvm.loop !11

.lr.ph:                                           ; preds = %2, %.lr.ph
  %.03435 = phi i32 [ %66, %.lr.ph ], [ %15, %2 ]
  %52 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %7) #1
  %53 = shl nuw nsw i32 %.03435, 1
  %54 = zext nneg i32 %53 to i64
  %55 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %54) #1
  %56 = load i32, ptr %55, align 4, !tbaa !5
  %57 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %7) #1
  %58 = or disjoint i32 %53, 1
  %59 = zext nneg i32 %58 to i64
  %60 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %57, i64 noundef %59) #1
  %61 = load i32, ptr %60, align 4, !tbaa !5
  %62 = add nsw i32 %61, %56
  %63 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %7) #1
  %64 = zext nneg i32 %.03435 to i64
  %65 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %64) #1
  store i32 %62, ptr %65, align 4, !tbaa !5
  %66 = lshr i32 %.03435, 1
  %.not44 = icmp ult i32 %.03435, 2
  br i1 %.not44, label %._crit_edge, label %.lr.ph, !llvm.loop !12

._crit_edge43:                                    ; preds = %.lr.ph42.split, %._crit_edge39.us, %._crit_edge.thread, %._crit_edge
  ret void

.lr.ph42.split:                                   ; preds = %.lr.ph42.split.preheader, %.lr.ph42.split
  %.03340 = phi i32 [ %81, %.lr.ph42.split ], [ %.03340.ph, %.lr.ph42.split.preheader ]
  %67 = shl nuw nsw i32 %.03340, 1
  %68 = zext nneg i32 %67 to i64
  %69 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %68) #1
  %70 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %69, i64 noundef %9) #1
  %71 = load i32, ptr %70, align 4, !tbaa !5
  %72 = or disjoint i32 %67, 1
  %73 = zext nneg i32 %72 to i64
  %74 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %73) #1
  %75 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %74, i64 noundef %9) #1
  %76 = load i32, ptr %75, align 4, !tbaa !5
  %77 = add nsw i32 %76, %71
  %78 = zext nneg i32 %.03340 to i64
  %79 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @t, i64 noundef %78) #1
  %80 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %79, i64 noundef %9) #1
  store i32 %77, ptr %80, align 4, !tbaa !5
  %81 = lshr i32 %.03340, 1
  %.not47 = icmp ult i32 %.03340, 2
  br i1 %.not47, label %._crit_edge43, label %.lr.ph42.split, !llvm.loop !11
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass