; LLVM IR from libxsmm/libxsmm :: src (generator_gemm_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_asimd(ptr noundef %0, ptr noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8) #1 {
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  %22 = alloca [3 x i32], align 4
  %23 = alloca i32, align 4
  %24 = alloca i32, align 4
  %25 = alloca i32, align 4
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca i32, align 4
  %30 = alloca i32, align 4
  %31 = alloca i32, align 4
  %32 = alloca i32, align 4
  %33 = alloca i32, align 4
  %34 = alloca i32, align 4
  %35 = alloca i32, align 4
  %36 = alloca i32, align 4
  %37 = alloca i32, align 4
  %38 = alloca i32, align 4
  %39 = alloca i32, align 4
  %40 = alloca i32, align 4
  %41 = alloca i32, align 4
  %42 = alloca i32, align 4
  %43 = alloca i32, align 4
  %44 = alloca i32, align 4
  store ptr %0, ptr %10, align 8, !tbaa !5
  store ptr %1, ptr %11, align 8, !tbaa !5
  store ptr %2, ptr %12, align 8, !tbaa !5
  store i32 %3, ptr %13, align 4, !tbaa !9
  store i32 %4, ptr %14, align 4, !tbaa !9
  store i32 %5, ptr %15, align 4, !tbaa !9
  store i32 %6, ptr %16, align 4, !tbaa !9
  store i32 %7, ptr %17, align 4, !tbaa !9
  store i32 %8, ptr %18, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #3
  store i32 0, ptr %20, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #3
  store i32 0, ptr %21, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 12, ptr %22) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %24) #3
  store i32 0, ptr %24, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #3
  store i32 18, ptr %25, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %26) #3
  store i32 0, ptr %26, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %27) #3
  store i32 1, ptr %27, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %28) #3
  store i32 2, ptr %28, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %29) #3
  store i32 3, ptr %29, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #3
  store i32 4, ptr %30, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %31) #3
  store i32 5, ptr %31, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %32) #3
  store i32 6, ptr %32, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %33) #3
  store i32 7, ptr %33, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %34) #3
  store i32 8, ptr %34, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %35) #3
  store i32 9, ptr %35, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %36) #3
  store i32 10, ptr %36, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %37) #3
  store i32 11, ptr %37, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %38) #3
  store i32 12, ptr %38, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %39) #3
  store i32 13, ptr %39, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %40) #3
  store i32 14, ptr %40, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %41) #3
  store i32 15, ptr %41, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %42) #3
  store i32 16, ptr %42, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %43) #3
  store i32 17, ptr %43, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %44) #3
  store i32 0, ptr %44, align 4, !tbaa !9
  %45 = load ptr, ptr %11, align 8, !tbaa !5
  %46 = load ptr, ptr %12, align 8, !tbaa !5
  %47 = load i32, ptr %17, align 4, !tbaa !9
  %48 = load i32, ptr %15, align 4, !tbaa !9
  %49 = udiv i32 %47, %48
  %50 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 0
  store i32 %49, ptr %50, align 4, !tbaa !9
  %51 = load i32, ptr %17, align 4, !tbaa !9
  %52 = load i32, ptr %15, align 4, !tbaa !9
  %53 = urem i32 %51, %52
  %54 = load i32, ptr %15, align 4, !tbaa !9
  %55 = udiv i32 %54, 2
  %56 = udiv i32 %53, %55
  %57 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 1
  store i32 %56, ptr %57, align 4, !tbaa !9
  %58 = load i32, ptr %17, align 4, !tbaa !9
  %59 = load i32, ptr %15, align 4, !tbaa !9
  %60 = urem i32 %58, %59
  %61 = load i32, ptr %15, align 4, !tbaa !9
  %62 = udiv i32 %61, 2
  %63 = urem i32 %60, %62
  %64 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 2
  store i32 %63, ptr %64, align 4, !tbaa !9
  %65 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 0
  %66 = load i32, ptr %65, align 4, !tbaa !9
  %67 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 1
  %68 = load i32, ptr %67, align 4, !tbaa !9
  %69 = add i32 %66, %68
  %70 = getelementptr inbounds [3 x i32], ptr %22, i64 0, i64 2
  %71 = load i32, ptr %70, align 4, !tbaa !9
  %72 = add i32 %69, %71
  store i32 %72, ptr %23, align 4, !tbaa !9
  %73 = load i32, ptr %16, align 4, !tbaa !9
  %74 = load i32, ptr %18, align 4, !tbaa !9
  %75 = load i32, ptr %23, align 4, !tbaa !9
  %76 = mul i32 %74, %75
  %77 = sub i32 %73, %76
  store i32 %77, ptr %19, align 4, !tbaa !9
  %78 = load i32, ptr %19, align 4, !tbaa !9
  %79 = load i32, ptr %25, align 4, !tbaa !9
  %80 = icmp ult i32 %78, %79
  br i1 %80, label %81, label %97

81:                                               ; preds = %9
  %82 = load ptr, ptr %10, align 8, !tbaa !5
  %83 = load i32, ptr %14, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %82, i32 noundef 6, i32 noundef %83)
  %84 = load i32, ptr %19, align 4, !tbaa !9
  store i32 %84, ptr %20, align 4, !tbaa !9
  br label %85

85:                                               ; preds = %93, %81
  %86 = load i32, ptr %20, align 4, !tbaa !9
  %87 = load i32, ptr %25, align 4, !tbaa !9
  %88 = icmp ule i32 %86, %87
  br i1 %88, label %89, label %96

89:                                               ; preds = %85
  %90 = load ptr, ptr %10, align 8, !tbaa !5
  %91 = load i32, ptr %14, align 4, !tbaa !9
  %92 = load i32, ptr %20, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %90, i32 noundef 1006633990, i32 noundef %91, i32 noundef 127, i32 noundef 64, i32 noundef %92, i32 noundef 1)
  br label %93

93:                                               ; preds = %89
  %94 = load i32, ptr %20, align 4, !tbaa !9
  %95 = add i32 %94, 1
  store i32 %95, ptr %20, align 4, !tbaa !9
  br label %85, !llvm.loop !11

96:                                               ; preds = %85
  br label %97

97:                                               ; preds = %96, %9
  %98 = load ptr, ptr %10, align 8, !tbaa !5
  %99 = load i32, ptr %26, align 4, !tbaa !9
  %100 = load i32, ptr %27, align 4, !tbaa !9
  %101 = load i32, ptr %28, align 4, !tbaa !9
  %102 = load i32, ptr %29, align 4, !tbaa !9
  %103 = load i32, ptr %30, align 4, !tbaa !9
  %104 = load i32, ptr %31, align 4, !tbaa !9
  %105 = load i32, ptr %32, align 4, !tbaa !9
  %106 = load i32, ptr %33, align 4, !tbaa !9
  %107 = load i32, ptr %34, align 4, !tbaa !9
  %108 = load i32, ptr %35, align 4, !tbaa !9
  %109 = load i32, ptr %36, align 4, !tbaa !9
  %110 = load i32, ptr %37, align 4, !tbaa !9
  %111 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %98, i32 noundef %99, i32 noundef %100, i32 noundef %101, i32 noundef %102, i32 noundef %103, i32 noundef %104, i32 noundef %105, i32 noundef %106, i32 noundef %107, i32 noundef %108, i32 noundef %109, i32 noundef %110, i32 noundef %111, i32 noundef 5)
  store i32 0, ptr %20, align 4, !tbaa !9
  br label %112

112:                                              ; preds = %196, %97
  %113 = load i32, ptr %20, align 4, !tbaa !9
  %114 = load i32, ptr %18, align 4, !tbaa !9
  %115 = icmp ult i32 %113, %114
  br i1 %115, label %116, label %199

116:                                              ; preds = %112
  store i32 0, ptr %21, align 4, !tbaa !9
  br label %117

117:                                              ; preds = %192, %116
  %118 = load i32, ptr %21, align 4, !tbaa !9
  %119 = load i32, ptr %23, align 4, !tbaa !9
  %120 = icmp ult i32 %118, %119
  br i1 %120, label %121, label %195

121:                                              ; preds = %117
  %122 = load i32, ptr %19, align 4, !tbaa !9
  %123 = load i32, ptr %21, align 4, !tbaa !9
  %124 = add i32 %122, %123
  %125 = load i32, ptr %23, align 4, !tbaa !9
  %126 = load i32, ptr %20, align 4, !tbaa !9
  %127 = mul i32 %125, %126
  %128 = add i32 %124, %127
  store i32 %128, ptr %24, align 4, !tbaa !9
  %129 = load i32, ptr %19, align 4, !tbaa !9
  %130 = load i32, ptr %25, align 4, !tbaa !9
  %131 = icmp ult i32 %129, %130
  br i1 %131, label %132, label %156

132:                                              ; preds = %121
  %133 = load i32, ptr %24, align 4, !tbaa !9
  %134 = load i32, ptr %25, align 4, !tbaa !9
  %135 = icmp ule i32 %133, %134
  br i1 %135, label %136, label %153

136:                                              ; preds = %132
  %137 = load i32, ptr %25, align 4, !tbaa !9
  store i32 %137, ptr %44, align 4, !tbaa !9
  %138 = load ptr, ptr %10, align 8, !tbaa !5
  %139 = load i32, ptr %14, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %138, i32 noundef 6, i32 noundef %139)
  %140 = load ptr, ptr %10, align 8, !tbaa !5
  %141 = load i32, ptr %14, align 4, !tbaa !9
  %142 = load i32, ptr %13, align 4, !tbaa !9
  %143 = load i32, ptr %14, align 4, !tbaa !9
  %144 = load i32, ptr %24, align 4, !tbaa !9
  %145 = zext i32 %144 to i64
  %146 = load i32, ptr %19, align 4, !tbaa !9
  %147 = zext i32 %146 to i64
  %148 = sub nsw i64 %145, %147
  %149 = mul nsw i64 %148, 64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %140, i32 noundef 4096, i32 noundef %141, i32 noundef %142, i32 noundef %143, i64 noundef %149)
  %150 = load ptr, ptr %10, align 8, !tbaa !5
  %151 = load i32, ptr %14, align 4, !tbaa !9
  %152 = load i32, ptr %44, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %150, i32 noundef 1027604486, i32 noundef %151, i32 noundef 127, i32 noundef 0, i32 noundef %152, i32 noundef 1)
  br label %155

153:                                              ; preds = %132
  %154 = load i32, ptr %24, align 4, !tbaa !9
  store i32 %154, ptr %44, align 4, !tbaa !9
  br label %155

155:                                              ; preds = %153, %136
  br label %158

156:                                              ; preds = %121
  %157 = load i32, ptr %24, align 4, !tbaa !9
  store i32 %157, ptr %44, align 4, !tbaa !9
  br label %158

158:                                              ; preds = %156, %155
  %159 = load ptr, ptr %10, align 8, !tbaa !5
  %160 = load i32, ptr %44, align 4, !tbaa !9
  %161 = load i32, ptr %39, align 4, !tbaa !9
  %162 = load i32, ptr %40, align 4, !tbaa !9
  %163 = load i32, ptr %41, align 4, !tbaa !9
  %164 = load i32, ptr %42, align 4, !tbaa !9
  %165 = load i32, ptr %43, align 4, !tbaa !9
  %166 = load i32, ptr %26, align 4, !tbaa !9
  %167 = load i32, ptr %27, align 4, !tbaa !9
  %168 = load i32, ptr %28, align 4, !tbaa !9
  %169 = load i32, ptr %29, align 4, !tbaa !9
  %170 = load i32, ptr %30, align 4, !tbaa !9
  %171 = load i32, ptr %31, align 4, !tbaa !9
  %172 = load i32, ptr %32, align 4, !tbaa !9
  %173 = load i32, ptr %33, align 4, !tbaa !9
  %174 = load i32, ptr %34, align 4, !tbaa !9
  %175 = load i32, ptr %35, align 4, !tbaa !9
  %176 = load i32, ptr %36, align 4, !tbaa !9
  %177 = load i32, ptr %37, align 4, !tbaa !9
  %178 = load i32, ptr %38, align 4, !tbaa !9
  call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %159, i32 noundef %160, i32 noundef %161, i32 noundef %162, i32 noundef %163, i32 noundef %164, i32 noundef %165, i32 noundef %166, i32 noundef %167, i32 noundef %168, i32 noundef %169, i32 noundef %170, i32 noundef %171, i32 noundef %172, i32 noundef %173, i32 noundef %174, i32 noundef %175, i32 noundef %176, i32 noundef %177, i32 noundef %178, i32 noundef 5)
  %179 = load i32, ptr %19, align 4, !tbaa !9
  %180 = load i32, ptr %25, align 4, !tbaa !9
  %181 = icmp ult i32 %179, %180
  br i1 %181, label %182, label %191

182:                                              ; preds = %158
  %183 = load i32, ptr %24, align 4, !tbaa !9
  %184 = load i32, ptr %25, align 4, !tbaa !9
  %185 = icmp ule i32 %183, %184
  br i1 %185, label %186, label %190

186:                                              ; preds = %182
  %187 = load ptr, ptr %10, align 8, !tbaa !5
  %188 = load i32, ptr %14, align 4, !tbaa !9
  %189 = load i32, ptr %44, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %187, i32 noundef 1023410182, i32 noundef %188, i32 noundef 127, i32 noundef 0, i32 noundef %189, i32 noundef 1)
  br label %190

190:                                              ; preds = %186, %182
  br label %191

191:                                              ; preds = %190, %158
  br label %192

192:                                              ; preds = %191
  %193 = load i32, ptr %21, align 4, !tbaa !9
  %194 = add i32 %193, 1
  store i32 %194, ptr %21, align 4, !tbaa !9
  br label %117, !llvm.loop !13

195:                                              ; preds = %117
  br label %196

196:                                              ; preds = %195
  %197 = load i32, ptr %20, align 4, !tbaa !9
  %198 = add i32 %197, 1
  store i32 %198, ptr %20, align 4, !tbaa !9
  br label %112, !llvm.loop !14

199:                                              ; preds = %112
  %200 = load i32, ptr %19, align 4, !tbaa !9
  %201 = load i32, ptr %25, align 4, !tbaa !9
  %202 = icmp ult i32 %200, %201
  br i1 %202, label %203, label %219

203:                                              ; preds = %199
  %204 = load ptr, ptr %10, align 8, !tbaa !5
  %205 = load i32, ptr %14, align 4, !tbaa !9
  call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %204, i32 noundef 6, i32 noundef %205)
  %206 = load i32, ptr %19, align 4, !tbaa !9
  store i32 %206, ptr %20, align 4, !tbaa !9
  br label %207

207:                                              ; preds = %215, %203
  %208 = load i32, ptr %20, align 4, !tbaa !9
  %209 = load i32, ptr %25, align 4, !tbaa !9
  %210 = icmp ule i32 %208, %209
  br i1 %210, label %211, label %218

211:                                              ; preds = %207
  %212 = load ptr, ptr %10, align 8, !tbaa !5
  %213 = load i32, ptr %14, align 4, !tbaa !9
  %214 = load i32, ptr %20, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %212, i32 noundef 1010828294, i32 noundef %213, i32 noundef 127, i32 noundef 64, i32 noundef %214, i32 noundef 1)
  br label %215

215:                                              ; preds = %211
  %216 = load i32, ptr %20, align 4, !tbaa !9
  %217 = add i32 %216, 1
  store i32 %217, ptr %20, align 4, !tbaa !9
  br label %207, !llvm.loop !15

218:                                              ; preds = %207
  br label %219

219:                                              ; preds = %218, %199
  call void @llvm.lifetime.end.p0(i64 4, ptr %44) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %43) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %42) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %41) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %40) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %39) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %38) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %37) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %36) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %35) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %34) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %33) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %32) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %31) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %29) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %28) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %27) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %26) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %24) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #3
  call void @llvm.lifetime.end.p0(i64 12, ptr %22) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #3
  ret void
}

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generator_gemm_apply_sigmoid_fusion_2dregblock_aarch64_asimd(ptr noundef %0, ptr nocapture noundef readnone %1, ptr nocapture noundef readnone %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7, i32 noundef %8) local_unnamed_addr #0 {
  %10 = udiv i32 %7, %5
  %11 = urem i32 %7, %5
  %12 = lshr i32 %5, 1
  %13 = udiv i32 %11, %12
  %14 = urem i32 %11, %12
  %15 = add i32 %13, %10
  %16 = add i32 %15, %14
  %17 = mul i32 %16, %8
  %18 = sub i32 %6, %17
  %19 = icmp ult i32 %18, 18
  br i1 %19, label %20, label %.loopexit114

20:                                               ; preds = %9
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  br label %21

21:                                               ; preds = %20, %21
  %.0103115 = phi i32 [ %18, %20 ], [ %22, %21 ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1006633990, i32 noundef %4, i32 noundef 127, i32 noundef 64, i32 noundef %.0103115, i32 noundef 1) #2
  %22 = add nuw nsw i32 %.0103115, 1
  %23 = icmp ult i32 %.0103115, 18
  br i1 %23, label %21, label %.loopexit114, !llvm.loop !5

.loopexit114:                                     ; preds = %21, %9
  tail call void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %0, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef %3, i32 noundef 5) #2
  %.not = icmp eq i32 %8, 0
  br i1 %.not, label %._crit_edge118, label %.preheader.lr.ph

.preheader.lr.ph:                                 ; preds = %.loopexit114
  %.not123 = icmp eq i32 %16, 0
  %24 = zext nneg i32 %18 to i64
  br i1 %.not123, label %._crit_edge118, label %.preheader.lr.ph.split.us

.preheader.lr.ph.split.us:                        ; preds = %.preheader.lr.ph
  br i1 %19, label %.preheader.us.us.preheader, label %.preheader.us

.preheader.us.us.preheader:                       ; preds = %.preheader.lr.ph.split.us
  %25 = zext i32 %16 to i64
  br label %.preheader.us.us

.preheader.us.us:                                 ; preds = %.preheader.us.us.preheader, %._crit_edge.split.us120.us
  %.1117.us.us = phi i32 [ %39, %._crit_edge.split.us120.us ], [ 0, %.preheader.us.us.preheader ]
  %26 = mul i32 %.1117.us.us, %16
  %27 = add i32 %26, %18
  br label %28

28:                                               ; preds = %.preheader.us.us, %37
  %indvars.iv = phi i64 [ 0, %.preheader.us.us ], [ %indvars.iv.next, %37 ]
  %29 = trunc nuw i64 %indvars.iv to i32
  %30 = add i32 %27, %29
  %31 = icmp ult i32 %30, 19
  br i1 %31, label %33, label %32

32:                                               ; preds = %28
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %0, i32 noundef %30, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 16, i32 noundef 17, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 5) #2
  br label %37

33:                                               ; preds = %28
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  %34 = zext nneg i32 %30 to i64
  %35 = sub nsw i64 %34, %24
  %36 = shl nsw i64 %35, 6
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %4, i32 noundef %3, i32 noundef %4, i64 noundef %36) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1027604486, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef 18, i32 noundef 1) #2
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %0, i32 noundef 18, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 16, i32 noundef 17, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 5) #2
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1023410182, i32 noundef %4, i32 noundef 127, i32 noundef 0, i32 noundef 18, i32 noundef 1) #2
  br label %37

37:                                               ; preds = %33, %32
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %38 = icmp ult i64 %indvars.iv.next, %25
  br i1 %38, label %28, label %._crit_edge.split.us120.us, !llvm.loop !7

._crit_edge.split.us120.us:                       ; preds = %37
  %39 = add nuw i32 %.1117.us.us, 1
  %exitcond127.not = icmp eq i32 %39, %8
  br i1 %exitcond127.not, label %._crit_edge118, label %.preheader.us.us, !llvm.loop !8

.preheader.us:                                    ; preds = %.preheader.lr.ph.split.us, %._crit_edge.split.us.us
  %.1117.us = phi i32 [ %46, %._crit_edge.split.us.us ], [ 0, %.preheader.lr.ph.split.us ]
  %40 = mul i32 %.1117.us, %16
  %41 = add i32 %40, %18
  br label %42

42:                                               ; preds = %42, %.preheader.us
  %.0104116.us.us = phi i32 [ 0, %.preheader.us ], [ %44, %42 ]
  %43 = add i32 %41, %.0104116.us.us
  tail call void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef %0, i32 noundef %43, i32 noundef 13, i32 noundef 14, i32 noundef 15, i32 noundef 16, i32 noundef 17, i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i32 noundef 10, i32 noundef 11, i32 noundef 12, i32 noundef 5) #2
  %44 = add nuw i32 %.0104116.us.us, 1
  %45 = icmp ult i32 %44, %16
  br i1 %45, label %42, label %._crit_edge.split.us.us, !llvm.loop !7

._crit_edge.split.us.us:                          ; preds = %42
  %46 = add nuw i32 %.1117.us, 1
  %exitcond.not = icmp eq i32 %46, %8
  br i1 %exitcond.not, label %._crit_edge118, label %.preheader.us, !llvm.loop !8

._crit_edge118:                                   ; preds = %._crit_edge.split.us.us, %._crit_edge.split.us120.us, %.preheader.lr.ph, %.loopexit114
  br i1 %19, label %47, label %.loopexit

47:                                               ; preds = %._crit_edge118
  tail call void @libxsmm_generator_gemm_getval_stack_var_aarch64(ptr noundef %0, i32 noundef 6, i32 noundef %4)
  br label %48

48:                                               ; preds = %47, %48
  %.2122 = phi i32 [ %18, %47 ], [ %49, %48 ]
  tail call void @libxsmm_aarch64_instruction_asimd_move(ptr noundef %0, i32 noundef 1010828294, i32 noundef %4, i32 noundef 127, i32 noundef 64, i32 noundef %.2122, i32 noundef 1) #2
  %49 = add nuw nsw i32 %.2122, 1
  %50 = icmp ult i32 %.2122, 18
  br i1 %50, label %48, label %.loopexit, !llvm.loop !9

.loopexit:                                        ; preds = %48, %._crit_edge118
  ret void
}

declare void @libxsmm_aarch64_instruction_asimd_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_generator_prepare_coeffs_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_generator_sigmoid_ps_rational_78_aarch64_asimd(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}
!9 = distinct !{!9, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass