; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseBackground)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8AdjustLoERKhRhi(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8AdjustHiERKhRhi(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base27BackgroundAdjustRangeMaskedEPhmmmS1_mS1_mS1_mhPKhm(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef %4, i64 noundef %5, ptr noundef %6, i64 noundef %7, ptr noundef %8, i64 noundef %9, i8 noundef zeroext %10, ptr noundef %11, i64 noundef %12) #2 {
  %14 = alloca ptr, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i64, align 8
  %18 = alloca ptr, align 8
  %19 = alloca i64, align 8
  %20 = alloca ptr, align 8
  %21 = alloca i64, align 8
  %22 = alloca ptr, align 8
  %23 = alloca i64, align 8
  %24 = alloca i8, align 1
  %25 = alloca ptr, align 8
  %26 = alloca i64, align 8
  %27 = alloca i64, align 8
  %28 = alloca i32, align 4
  %29 = alloca i64, align 8
  store ptr %0, ptr %14, align 8, !tbaa !5
  store i64 %1, ptr %15, align 8, !tbaa !9
  store i64 %2, ptr %16, align 8, !tbaa !9
  store i64 %3, ptr %17, align 8, !tbaa !9
  store ptr %4, ptr %18, align 8, !tbaa !5
  store i64 %5, ptr %19, align 8, !tbaa !9
  store ptr %6, ptr %20, align 8, !tbaa !5
  store i64 %7, ptr %21, align 8, !tbaa !9
  store ptr %8, ptr %22, align 8, !tbaa !5
  store i64 %9, ptr %23, align 8, !tbaa !9
  store i8 %10, ptr %24, align 1, !tbaa !11
  store ptr %11, ptr %25, align 8, !tbaa !5
  store i64 %12, ptr %26, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %27) #3
  store i64 0, ptr %27, align 8, !tbaa !9
  br label %30

30:                                               ; preds = %90, %13
  %31 = load i64, ptr %27, align 8, !tbaa !9
  %32 = load i64, ptr %17, align 8, !tbaa !9
  %33 = icmp ult i64 %31, %32
  br i1 %33, label %35, label %34

34:                                               ; preds = %30
  store i32 2, ptr %28, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %27) #3
  br label %93

35:                                               ; preds = %30
  call void @llvm.lifetime.start.p0(i64 8, ptr %29) #3
  store i64 0, ptr %29, align 8, !tbaa !9
  br label %36

36:                                               ; preds = %71, %35
  %37 = load i64, ptr %29, align 8, !tbaa !9
  %38 = load i64, ptr %16, align 8, !tbaa !9
  %39 = icmp ult i64 %37, %38
  br i1 %39, label %41, label %40

40:                                               ; preds = %36
  store i32 5, ptr %28, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #3
  br label %74

41:                                               ; preds = %36
  %42 = load ptr, ptr %25, align 8, !tbaa !5
  %43 = load i64, ptr %29, align 8, !tbaa !9
  %44 = getelementptr inbounds i8, ptr %42, i64 %43
  %45 = load i8, ptr %44, align 1, !tbaa !11
  %46 = icmp ne i8 %45, 0
  br i1 %46, label %47, label %64

47:                                               ; preds = %41
  %48 = load ptr, ptr %14, align 8, !tbaa !5
  %49 = load i64, ptr %29, align 8, !tbaa !9
  %50 = getelementptr inbounds i8, ptr %48, i64 %49
  %51 = load ptr, ptr %18, align 8, !tbaa !5
  %52 = load i64, ptr %29, align 8, !tbaa !9
  %53 = getelementptr inbounds i8, ptr %51, i64 %52
  %54 = load i8, ptr %24, align 1, !tbaa !11
  %55 = zext i8 %54 to i32
  call void @_ZN4Simd4Base8AdjustLoERKhRhi(ptr noundef nonnull align 1 dereferenceable(1) %50, ptr noundef nonnull align 1 dereferenceable(1) %53, i32 noundef %55)
  %56 = load ptr, ptr %20, align 8, !tbaa !5
  %57 = load i64, ptr %29, align 8, !tbaa !9
  %58 = getelementptr inbounds i8, ptr %56, i64 %57
  %59 = load ptr, ptr %22, align 8, !tbaa !5
  %60 = load i64, ptr %29, align 8, !tbaa !9
  %61 = getelementptr inbounds i8, ptr %59, i64 %60
  %62 = load i8, ptr %24, align 1, !tbaa !11
  %63 = zext i8 %62 to i32
  call void @_ZN4Simd4Base8AdjustHiERKhRhi(ptr noundef nonnull align 1 dereferenceable(1) %58, ptr noundef nonnull align 1 dereferenceable(1) %61, i32 noundef %63)
  br label %64

64:                                               ; preds = %47, %41
  %65 = load ptr, ptr %14, align 8, !tbaa !5
  %66 = load i64, ptr %29, align 8, !tbaa !9
  %67 = getelementptr inbounds i8, ptr %65, i64 %66
  store i8 0, ptr %67, align 1, !tbaa !11
  %68 = load ptr, ptr %20, align 8, !tbaa !5
  %69 = load i64, ptr %29, align 8, !tbaa !9
  %70 = getelementptr inbounds i8, ptr %68, i64 %69
  store i8 0, ptr %70, align 1, !tbaa !11
  br label %71

71:                                               ; preds = %64
  %72 = load i64, ptr %29, align 8, !tbaa !9
  %73 = add i64 %72, 1
  store i64 %73, ptr %29, align 8, !tbaa !9
  br label %36, !llvm.loop !12

74:                                               ; preds = %40
  %75 = load i64, ptr %19, align 8, !tbaa !9
  %76 = load ptr, ptr %18, align 8, !tbaa !5
  %77 = getelementptr inbounds i8, ptr %76, i64 %75
  store ptr %77, ptr %18, align 8, !tbaa !5
  %78 = load i64, ptr %23, align 8, !tbaa !9
  %79 = load ptr, ptr %22, align 8, !tbaa !5
  %80 = getelementptr inbounds i8, ptr %79, i64 %78
  store ptr %80, ptr %22, align 8, !tbaa !5
  %81 = load i64, ptr %15, align 8, !tbaa !9
  %82 = load ptr, ptr %14, align 8, !tbaa !5
  %83 = getelementptr inbounds i8, ptr %82, i64 %81
  store ptr %83, ptr %14, align 8, !tbaa !5
  %84 = load i64, ptr %21, align 8, !tbaa !9
  %85 = load ptr, ptr %20, align 8, !tbaa !5
  %86 = getelementptr inbounds i8, ptr %85, i64 %84
  store ptr %86, ptr %20, align 8, !tbaa !5
  %87 = load i64, ptr %26, align 8, !tbaa !9
  %88 = load ptr, ptr %25, align 8, !tbaa !5
  %89 = getelementptr inbounds i8, ptr %88, i64 %87
  store ptr %89, ptr %25, align 8, !tbaa !5
  br label %90

90:                                               ; preds = %74
  %91 = load i64, ptr %27, align 8, !tbaa !9
  %92 = add i64 %91, 1
  store i64 %92, ptr %27, align 8, !tbaa !9
  br label %30, !llvm.loop !14

93:                                               ; preds = %34
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8AdjustLoERKhRhi(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd4Base8AdjustHiERKhRhi(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN4Simd4Base27BackgroundAdjustRangeMaskedEPhmmmS1_mS1_mS1_mhPKhm(ptr noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, ptr noundef %4, i64 noundef %5, ptr noundef %6, i64 noundef %7, ptr noundef %8, i64 noundef %9, i8 noundef zeroext %10, ptr nocapture noundef readonly %11, i64 noundef %12) local_unnamed_addr #1 {
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %._crit_edge44, label %.preheader.lr.ph

.preheader.lr.ph:                                 ; preds = %13
  %.not45 = icmp eq i64 %2, 0
  %14 = zext i8 %10 to i32
  br i1 %.not45, label %._crit_edge44, label %.preheader.us

.preheader.us:                                    ; preds = %.preheader.lr.ph, %._crit_edge.us
  %.03143.us = phi i64 [ %32, %._crit_edge.us ], [ 0, %.preheader.lr.ph ]
  %.03242.us = phi ptr [ %29, %._crit_edge.us ], [ %0, %.preheader.lr.ph ]
  %.03341.us = phi ptr [ %31, %._crit_edge.us ], [ %11, %.preheader.lr.ph ]
  %.03440.us = phi ptr [ %27, %._crit_edge.us ], [ %4, %.preheader.lr.ph ]
  %.03539.us = phi ptr [ %30, %._crit_edge.us ], [ %6, %.preheader.lr.ph ]
  %.03638.us = phi ptr [ %28, %._crit_edge.us ], [ %8, %.preheader.lr.ph ]
  br label %15

15:                                               ; preds = %.preheader.us, %23
  %.037.us = phi i64 [ 0, %.preheader.us ], [ %26, %23 ]
  %16 = getelementptr inbounds i8, ptr %.03341.us, i64 %.037.us
  %17 = load i8, ptr %16, align 1, !tbaa !5
  %.not.us = icmp eq i8 %17, 0
  br i1 %.not.us, label %23, label %18

18:                                               ; preds = %15
  %19 = getelementptr inbounds i8, ptr %.03242.us, i64 %.037.us
  %20 = getelementptr inbounds i8, ptr %.03440.us, i64 %.037.us
  tail call void @_ZN4Simd4Base8AdjustLoERKhRhi(ptr noundef nonnull align 1 dereferenceable(1) %19, ptr noundef nonnull align 1 dereferenceable(1) %20, i32 noundef %14)
  %21 = getelementptr inbounds i8, ptr %.03539.us, i64 %.037.us
  %22 = getelementptr inbounds i8, ptr %.03638.us, i64 %.037.us
  tail call void @_ZN4Simd4Base8AdjustHiERKhRhi(ptr noundef nonnull align 1 dereferenceable(1) %21, ptr noundef nonnull align 1 dereferenceable(1) %22, i32 noundef %14)
  br label %23

23:                                               ; preds = %18, %15
  %24 = getelementptr inbounds i8, ptr %.03242.us, i64 %.037.us
  store i8 0, ptr %24, align 1, !tbaa !5
  %25 = getelementptr inbounds i8, ptr %.03539.us, i64 %.037.us
  store i8 0, ptr %25, align 1, !tbaa !5
  %26 = add nuw i64 %.037.us, 1
  %exitcond.not = icmp eq i64 %26, %2
  br i1 %exitcond.not, label %._crit_edge.us, label %15, !llvm.loop !8

._crit_edge.us:                                   ; preds = %23
  %27 = getelementptr inbounds i8, ptr %.03440.us, i64 %5
  %28 = getelementptr inbounds i8, ptr %.03638.us, i64 %9
  %29 = getelementptr inbounds i8, ptr %.03242.us, i64 %1
  %30 = getelementptr inbounds i8, ptr %.03539.us, i64 %7
  %31 = getelementptr inbounds i8, ptr %.03341.us, i64 %12
  %32 = add nuw i64 %.03143.us, 1
  %exitcond47.not = icmp eq i64 %32, %3
  br i1 %exitcond47.not, label %._crit_edge44, label %.preheader.us, !llvm.loop !10

._crit_edge44:                                    ; preds = %._crit_edge.us, %.preheader.lr.ph, %13
  ret void
}

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}
!10 = distinct !{!10, !9}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass