; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_vex_compute_mem_2reg_general.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

declare void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #3

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_compute_mem_2reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) #0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca [3 x i32], align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i8, align 1
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i16 %4, ptr %11, align 2, !tbaa !11
  store i32 %5, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #4
  store i32 2, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 12, ptr %16) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %16, ptr align 4 @__const.test_vex_compute_mem_2reg_general.displ, i64 12, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %19) #4
  %20 = load i32, ptr %12, align 4, !tbaa !9
  %21 = icmp ne i32 %20, 0
  %22 = zext i1 %21 to i64
  %23 = select i1 %21, i32 120, i32 121
  %24 = trunc i32 %23 to i8
  store i8 %24, ptr %19, align 1, !tbaa !13
  %25 = load ptr, ptr %8, align 8, !tbaa !5
  %26 = load ptr, ptr %7, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %25, ptr noundef %26)
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %27

27:                                               ; preds = %85, %6
  %28 = load i32, ptr %14, align 4, !tbaa !9
  %29 = icmp ult i32 %28, 16
  br i1 %29, label %30, label %88

30:                                               ; preds = %27
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %31

31:                                               ; preds = %81, %30
  %32 = load i32, ptr %18, align 4, !tbaa !9
  %33 = icmp ult i32 %32, 16
  br i1 %33, label %34, label %84

34:                                               ; preds = %31
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %35

35:                                               ; preds = %77, %34
  %36 = load i32, ptr %17, align 4, !tbaa !9
  %37 = icmp ult i32 %36, 3
  br i1 %37, label %38, label %80

38:                                               ; preds = %35
  %39 = load i32, ptr %10, align 4, !tbaa !9
  %40 = icmp ne i32 %39, 0
  br i1 %40, label %41, label %53

41:                                               ; preds = %38
  %42 = load ptr, ptr %8, align 8, !tbaa !5
  %43 = load i32, ptr %9, align 4, !tbaa !9
  %44 = load i8, ptr %19, align 1, !tbaa !13
  %45 = load i32, ptr %14, align 4, !tbaa !9
  %46 = load i32, ptr %17, align 4, !tbaa !9
  %47 = zext i32 %46 to i64
  %48 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %47
  %49 = load i32, ptr %48, align 4, !tbaa !9
  %50 = load i32, ptr %18, align 4, !tbaa !9
  %51 = load i16, ptr %11, align 2, !tbaa !11
  %52 = zext i16 %51 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %42, i32 noundef %43, i8 noundef signext %44, i32 noundef %45, i32 noundef 127, i32 noundef 0, i32 noundef %49, i32 noundef 0, i32 noundef 255, i32 noundef %50, i32 noundef 0, i32 noundef 0, i32 noundef %52)
  br label %76

53:                                               ; preds = %38
  %54 = load ptr, ptr %8, align 8, !tbaa !5
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = load i8, ptr %19, align 1, !tbaa !13
  %57 = load i32, ptr %14, align 4, !tbaa !9
  %58 = load i32, ptr %17, align 4, !tbaa !9
  %59 = zext i32 %58 to i64
  %60 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %59
  %61 = load i32, ptr %60, align 4, !tbaa !9
  %62 = load i32, ptr %18, align 4, !tbaa !9
  %63 = load i16, ptr %11, align 2, !tbaa !11
  %64 = zext i16 %63 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %54, i32 noundef %55, i8 noundef signext %56, i32 noundef %57, i32 noundef 127, i32 noundef 0, i32 noundef %61, i32 noundef 0, i32 noundef %62, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %64)
  %65 = load ptr, ptr %8, align 8, !tbaa !5
  %66 = load i32, ptr %9, align 4, !tbaa !9
  %67 = load i8, ptr %19, align 1, !tbaa !13
  %68 = load i32, ptr %14, align 4, !tbaa !9
  %69 = load i32, ptr %17, align 4, !tbaa !9
  %70 = zext i32 %69 to i64
  %71 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %70
  %72 = load i32, ptr %71, align 4, !tbaa !9
  %73 = load i32, ptr %18, align 4, !tbaa !9
  %74 = load i16, ptr %11, align 2, !tbaa !11
  %75 = zext i16 %74 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %65, i32 noundef %66, i8 noundef signext %67, i32 noundef %68, i32 noundef 127, i32 noundef 0, i32 noundef %72, i32 noundef 0, i32 noundef 0, i32 noundef %73, i32 noundef 0, i32 noundef 0, i32 noundef %75)
  br label %76

76:                                               ; preds = %53, %41
  br label %77

77:                                               ; preds = %76
  %78 = load i32, ptr %17, align 4, !tbaa !9
  %79 = add i32 %78, 1
  store i32 %79, ptr %17, align 4, !tbaa !9
  br label %35, !llvm.loop !14

80:                                               ; preds = %35
  br label %81

81:                                               ; preds = %80
  %82 = load i32, ptr %18, align 4, !tbaa !9
  %83 = add i32 %82, 1
  store i32 %83, ptr %18, align 4, !tbaa !9
  br label %31, !llvm.loop !16

84:                                               ; preds = %31
  br label %85

85:                                               ; preds = %84
  %86 = load i32, ptr %14, align 4, !tbaa !9
  %87 = add i32 %86, 1
  store i32 %87, ptr %14, align 4, !tbaa !9
  br label %27, !llvm.loop !17

88:                                               ; preds = %27
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %89

89:                                               ; preds = %161, %88
  %90 = load i32, ptr %14, align 4, !tbaa !9
  %91 = icmp ult i32 %90, 16
  br i1 %91, label %92, label %164

92:                                               ; preds = %89
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %93

93:                                               ; preds = %157, %92
  %94 = load i32, ptr %13, align 4, !tbaa !9
  %95 = icmp ult i32 %94, 16
  br i1 %95, label %96, label %160

96:                                               ; preds = %93
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %97

97:                                               ; preds = %153, %96
  %98 = load i32, ptr %18, align 4, !tbaa !9
  %99 = icmp ult i32 %98, 16
  br i1 %99, label %100, label %156

100:                                              ; preds = %97
  store i32 0, ptr %17, align 4, !tbaa !9
  br label %101

101:                                              ; preds = %149, %100
  %102 = load i32, ptr %17, align 4, !tbaa !9
  %103 = icmp ult i32 %102, 3
  br i1 %103, label %104, label %152

104:                                              ; preds = %101
  %105 = load i32, ptr %10, align 4, !tbaa !9
  %106 = icmp ne i32 %105, 0
  br i1 %106, label %107, label %121

107:                                              ; preds = %104
  %108 = load ptr, ptr %8, align 8, !tbaa !5
  %109 = load i32, ptr %9, align 4, !tbaa !9
  %110 = load i8, ptr %19, align 1, !tbaa !13
  %111 = load i32, ptr %14, align 4, !tbaa !9
  %112 = load i32, ptr %13, align 4, !tbaa !9
  %113 = load i32, ptr %15, align 4, !tbaa !9
  %114 = load i32, ptr %17, align 4, !tbaa !9
  %115 = zext i32 %114 to i64
  %116 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %115
  %117 = load i32, ptr %116, align 4, !tbaa !9
  %118 = load i32, ptr %18, align 4, !tbaa !9
  %119 = load i16, ptr %11, align 2, !tbaa !11
  %120 = zext i16 %119 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %108, i32 noundef %109, i8 noundef signext %110, i32 noundef %111, i32 noundef %112, i32 noundef %113, i32 noundef %117, i32 noundef 0, i32 noundef 255, i32 noundef %118, i32 noundef 0, i32 noundef 0, i32 noundef %120)
  br label %148

121:                                              ; preds = %104
  %122 = load ptr, ptr %8, align 8, !tbaa !5
  %123 = load i32, ptr %9, align 4, !tbaa !9
  %124 = load i8, ptr %19, align 1, !tbaa !13
  %125 = load i32, ptr %14, align 4, !tbaa !9
  %126 = load i32, ptr %13, align 4, !tbaa !9
  %127 = load i32, ptr %15, align 4, !tbaa !9
  %128 = load i32, ptr %17, align 4, !tbaa !9
  %129 = zext i32 %128 to i64
  %130 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %129
  %131 = load i32, ptr %130, align 4, !tbaa !9
  %132 = load i32, ptr %18, align 4, !tbaa !9
  %133 = load i16, ptr %11, align 2, !tbaa !11
  %134 = zext i16 %133 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %122, i32 noundef %123, i8 noundef signext %124, i32 noundef %125, i32 noundef %126, i32 noundef %127, i32 noundef %131, i32 noundef 0, i32 noundef %132, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %134)
  %135 = load ptr, ptr %8, align 8, !tbaa !5
  %136 = load i32, ptr %9, align 4, !tbaa !9
  %137 = load i8, ptr %19, align 1, !tbaa !13
  %138 = load i32, ptr %14, align 4, !tbaa !9
  %139 = load i32, ptr %13, align 4, !tbaa !9
  %140 = load i32, ptr %15, align 4, !tbaa !9
  %141 = load i32, ptr %17, align 4, !tbaa !9
  %142 = zext i32 %141 to i64
  %143 = getelementptr inbounds [3 x i32], ptr %16, i64 0, i64 %142
  %144 = load i32, ptr %143, align 4, !tbaa !9
  %145 = load i32, ptr %18, align 4, !tbaa !9
  %146 = load i16, ptr %11, align 2, !tbaa !11
  %147 = zext i16 %146 to i32
  call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %135, i32 noundef %136, i8 noundef signext %137, i32 noundef %138, i32 noundef %139, i32 noundef %140, i32 noundef %144, i32 noundef 0, i32 noundef 0, i32 noundef %145, i32 noundef 0, i32 noundef 0, i32 noundef %147)
  br label %148

148:                                              ; preds = %121, %107
  br label %149

149:                                              ; preds = %148
  %150 = load i32, ptr %17, align 4, !tbaa !9
  %151 = add i32 %150, 1
  store i32 %151, ptr %17, align 4, !tbaa !9
  br label %101, !llvm.loop !18

152:                                              ; preds = %101
  br label %153

153:                                              ; preds = %152
  %154 = load i32, ptr %18, align 4, !tbaa !9
  %155 = add i32 %154, 1
  store i32 %155, ptr %18, align 4, !tbaa !9
  br label %97, !llvm.loop !19

156:                                              ; preds = %97
  br label %157

157:                                              ; preds = %156
  %158 = load i32, ptr %13, align 4, !tbaa !9
  %159 = add i32 %158, 1
  store i32 %159, ptr %13, align 4, !tbaa !9
  br label %93, !llvm.loop !20

160:                                              ; preds = %93
  br label %161

161:                                              ; preds = %160
  %162 = load i32, ptr %14, align 4, !tbaa !9
  %163 = add i32 %162, 1
  store i32 %163, ptr %14, align 4, !tbaa !9
  br label %89, !llvm.loop !21

164:                                              ; preds = %89
  %165 = load ptr, ptr %8, align 8, !tbaa !5
  %166 = load ptr, ptr %7, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %165, ptr noundef %166)
  call void @llvm.lifetime.end.p0(i64 1, ptr %19) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #4
  call void @llvm.lifetime.end.p0(i64 12, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}
!19 = distinct !{!19, !15}
!20 = distinct !{!20, !15}
!21 = distinct !{!21, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@__const.test_vex_compute_mem_2reg_general.displ = external hidden unnamed_addr constant [3 x i32], align 4

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

declare void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @test_vex_compute_mem_2reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) local_unnamed_addr #0 {
  %.not = icmp eq i32 %5, 0
  %7 = select i1 %.not, i8 121, i8 120
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %.not74 = icmp eq i32 %3, 0
  %8 = zext i16 %4 to i32
  %.pre119.pre = load i32, ptr @__const.test_vex_compute_mem_2reg_general.displ, align 4, !tbaa !5
  %.pre120.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_vex_compute_mem_2reg_general.displ, i64 4), align 4, !tbaa !5
  %.pre121.pre = load i32, ptr getelementptr inbounds (i8, ptr @__const.test_vex_compute_mem_2reg_general.displ, i64 8), align 4, !tbaa !5
  br i1 %.not74, label %.preheader79.us, label %.preheader79

.preheader79.us:                                  ; preds = %6, %.split83.us.us
  %.07184.us = phi i32 [ %10, %.split83.us.us ], [ 0, %6 ]
  br label %.preheader78.us.us

.preheader78.us.us:                               ; preds = %.preheader78.us.us, %.preheader79.us
  %.06881.us.us = phi i32 [ 0, %.preheader79.us ], [ %9, %.preheader78.us.us ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184.us, i32 noundef 127, i32 noundef 0, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.06881.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  %9 = add nuw nsw i32 %.06881.us.us, 1
  %exitcond105.not = icmp eq i32 %9, 16
  br i1 %exitcond105.not, label %.split83.us.us, label %.preheader78.us.us, !llvm.loop !9

.split83.us.us:                                   ; preds = %.preheader78.us.us
  %10 = add nuw nsw i32 %.07184.us, 1
  %exitcond106.not = icmp eq i32 %10, 16
  br i1 %exitcond106.not, label %.preheader77, label %.preheader79.us, !llvm.loop !11

.preheader79:                                     ; preds = %6, %.split83
  %.07184 = phi i32 [ %15, %.split83 ], [ 0, %6 ]
  br label %.preheader78

.preheader77:                                     ; preds = %.split83, %.split83.us.us
  br i1 %.not74, label %.preheader76.us, label %.preheader76

.preheader76.us:                                  ; preds = %.preheader77, %.split94.us.us
  %.17295.us = phi i32 [ %13, %.split94.us.us ], [ 0, %.preheader77 ]
  br label %.preheader75.us.us

.preheader75.us.us:                               ; preds = %.split91.us.us.us, %.preheader76.us
  %.092.us.us = phi i32 [ 0, %.preheader76.us ], [ %12, %.split91.us.us.us ]
  br label %.preheader.us.us.us

.preheader.us.us.us:                              ; preds = %.preheader.us.us.us, %.preheader75.us.us
  %.189.us.us.us = phi i32 [ 0, %.preheader75.us.us ], [ %11, %.preheader.us.us.us ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295.us, i32 noundef %.092.us.us, i32 noundef 2, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef 0, i32 noundef %.189.us.us.us, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  %11 = add nuw nsw i32 %.189.us.us.us, 1
  %exitcond114.not = icmp eq i32 %11, 16
  br i1 %exitcond114.not, label %.split91.us.us.us, label %.preheader.us.us.us, !llvm.loop !12

.split91.us.us.us:                                ; preds = %.preheader.us.us.us
  %12 = add nuw nsw i32 %.092.us.us, 1
  %exitcond115.not = icmp eq i32 %12, 16
  br i1 %exitcond115.not, label %.split94.us.us, label %.preheader75.us.us, !llvm.loop !13

.split94.us.us:                                   ; preds = %.split91.us.us.us
  %13 = add nuw nsw i32 %.17295.us, 1
  %exitcond116.not = icmp eq i32 %13, 16
  br i1 %exitcond116.not, label %.split98.us, label %.preheader76.us, !llvm.loop !14

.preheader78:                                     ; preds = %.preheader79, %.preheader78
  %.06881 = phi i32 [ 0, %.preheader79 ], [ %14, %.preheader78 ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184, i32 noundef 127, i32 noundef 0, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.06881, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184, i32 noundef 127, i32 noundef 0, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.06881, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.07184, i32 noundef 127, i32 noundef 0, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.06881, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  %14 = add nuw nsw i32 %.06881, 1
  %exitcond.not = icmp eq i32 %14, 16
  br i1 %exitcond.not, label %.split83, label %.preheader78, !llvm.loop !9

.split83:                                         ; preds = %.preheader78
  %15 = add nuw nsw i32 %.07184, 1
  %exitcond102.not = icmp eq i32 %15, 16
  br i1 %exitcond102.not, label %.preheader77, label %.preheader79, !llvm.loop !11

.preheader76:                                     ; preds = %.preheader77, %.split94
  %.17295 = phi i32 [ %18, %.split94 ], [ 0, %.preheader77 ]
  br label %.preheader75

.preheader75:                                     ; preds = %.preheader76, %.split91
  %.092 = phi i32 [ 0, %.preheader76 ], [ %17, %.split91 ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader75, %.preheader
  %.189 = phi i32 [ 0, %.preheader75 ], [ %16, %.preheader ]
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295, i32 noundef %.092, i32 noundef 2, i32 noundef %.pre119.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.189, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295, i32 noundef %.092, i32 noundef 2, i32 noundef %.pre120.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.189, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  tail call void @libxsmm_x86_instruction_vec_compute_mem_2reg_mask_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext %7, i32 noundef %.17295, i32 noundef %.092, i32 noundef 2, i32 noundef %.pre121.pre, i32 noundef 0, i32 noundef 255, i32 noundef %.189, i32 noundef 0, i32 noundef 0, i32 noundef %8) #2
  %16 = add nuw nsw i32 %.189, 1
  %exitcond109.not = icmp eq i32 %16, 16
  br i1 %exitcond109.not, label %.split91, label %.preheader, !llvm.loop !12

.split91:                                         ; preds = %.preheader
  %17 = add nuw nsw i32 %.092, 1
  %exitcond110.not = icmp eq i32 %17, 16
  br i1 %exitcond110.not, label %.split94, label %.preheader75, !llvm.loop !13

.split94:                                         ; preds = %.split91
  %18 = add nuw nsw i32 %.17295, 1
  %exitcond111.not = icmp eq i32 %18, 16
  br i1 %exitcond111.not, label %.split98.us, label %.preheader76, !llvm.loop !14

.split98.us:                                      ; preds = %.split94, %.split94.us.us
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass