; LLVM IR from libxsmm/libxsmm :: samples/encoder (encoder_x86)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local void @test_evex_compute_3reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) #0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i16 %4, ptr %11, align 2, !tbaa !11
  store i32 %5, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %16 = load i32, ptr %12, align 4, !tbaa !9
  %17 = icmp eq i32 %16, 32
  %18 = zext i1 %17 to i64
  %19 = select i1 %17, i32 0, i32 1
  store i32 %19, ptr %15, align 4, !tbaa !9
  %20 = load ptr, ptr %8, align 8, !tbaa !5
  %21 = load ptr, ptr %7, align 8, !tbaa !5
  call void @reset_code_buffer(ptr noundef %20, ptr noundef %21)
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %51, %6
  %23 = load i32, ptr %13, align 4, !tbaa !9
  %24 = icmp ult i32 %23, 32
  br i1 %24, label %25, label %54

25:                                               ; preds = %22
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %26

26:                                               ; preds = %47, %25
  %27 = load i32, ptr %14, align 4, !tbaa !9
  %28 = icmp ult i32 %27, 8
  br i1 %28, label %29, label %50

29:                                               ; preds = %26
  %30 = load i32, ptr %10, align 4, !tbaa !9
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %39

32:                                               ; preds = %29
  %33 = load ptr, ptr %8, align 8, !tbaa !5
  %34 = load i32, ptr %9, align 4, !tbaa !9
  %35 = load i32, ptr %13, align 4, !tbaa !9
  %36 = load i32, ptr %14, align 4, !tbaa !9
  %37 = load i16, ptr %11, align 2, !tbaa !11
  %38 = zext i16 %37 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %33, i32 noundef %34, i8 noundef signext 122, i32 noundef %35, i32 noundef 255, i32 noundef 0, i32 noundef %36, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %38)
  br label %46

39:                                               ; preds = %29
  %40 = load ptr, ptr %8, align 8, !tbaa !5
  %41 = load i32, ptr %9, align 4, !tbaa !9
  %42 = load i32, ptr %13, align 4, !tbaa !9
  %43 = load i32, ptr %14, align 4, !tbaa !9
  %44 = load i16, ptr %11, align 2, !tbaa !11
  %45 = zext i16 %44 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %40, i32 noundef %41, i8 noundef signext 122, i32 noundef %42, i32 noundef 0, i32 noundef 0, i32 noundef %43, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %45)
  br label %46

46:                                               ; preds = %39, %32
  br label %47

47:                                               ; preds = %46
  %48 = load i32, ptr %14, align 4, !tbaa !9
  %49 = add i32 %48, 1
  store i32 %49, ptr %14, align 4, !tbaa !9
  br label %26, !llvm.loop !13

50:                                               ; preds = %26
  br label %51

51:                                               ; preds = %50
  %52 = load i32, ptr %13, align 4, !tbaa !9
  %53 = add i32 %52, 1
  store i32 %53, ptr %13, align 4, !tbaa !9
  br label %22, !llvm.loop !15

54:                                               ; preds = %22
  %55 = load i32, ptr %10, align 4, !tbaa !9
  %56 = icmp ne i32 %55, 0
  br i1 %56, label %80, label %57

57:                                               ; preds = %54
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %76, %57
  %59 = load i32, ptr %13, align 4, !tbaa !9
  %60 = icmp ult i32 %59, 32
  br i1 %60, label %61, label %79

61:                                               ; preds = %58
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %62

62:                                               ; preds = %72, %61
  %63 = load i32, ptr %14, align 4, !tbaa !9
  %64 = icmp ult i32 %63, 8
  br i1 %64, label %65, label %75

65:                                               ; preds = %62
  %66 = load ptr, ptr %8, align 8, !tbaa !5
  %67 = load i32, ptr %9, align 4, !tbaa !9
  %68 = load i32, ptr %13, align 4, !tbaa !9
  %69 = load i32, ptr %14, align 4, !tbaa !9
  %70 = load i16, ptr %11, align 2, !tbaa !11
  %71 = zext i16 %70 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %66, i32 noundef %67, i8 noundef signext 122, i32 noundef 0, i32 noundef %68, i32 noundef 0, i32 noundef %69, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %71)
  br label %72

72:                                               ; preds = %65
  %73 = load i32, ptr %14, align 4, !tbaa !9
  %74 = add i32 %73, 1
  store i32 %74, ptr %14, align 4, !tbaa !9
  br label %62, !llvm.loop !16

75:                                               ; preds = %62
  br label %76

76:                                               ; preds = %75
  %77 = load i32, ptr %13, align 4, !tbaa !9
  %78 = add i32 %77, 1
  store i32 %78, ptr %13, align 4, !tbaa !9
  br label %58, !llvm.loop !17

79:                                               ; preds = %58
  br label %80

80:                                               ; preds = %79, %54
  %81 = load i32, ptr %15, align 4, !tbaa !9
  store i32 %81, ptr %13, align 4, !tbaa !9
  br label %82

82:                                               ; preds = %112, %80
  %83 = load i32, ptr %13, align 4, !tbaa !9
  %84 = load i32, ptr %12, align 4, !tbaa !9
  %85 = icmp ult i32 %83, %84
  br i1 %85, label %86, label %115

86:                                               ; preds = %82
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %87

87:                                               ; preds = %108, %86
  %88 = load i32, ptr %14, align 4, !tbaa !9
  %89 = icmp ult i32 %88, 8
  br i1 %89, label %90, label %111

90:                                               ; preds = %87
  %91 = load i32, ptr %10, align 4, !tbaa !9
  %92 = icmp ne i32 %91, 0
  br i1 %92, label %93, label %100

93:                                               ; preds = %90
  %94 = load ptr, ptr %8, align 8, !tbaa !5
  %95 = load i32, ptr %9, align 4, !tbaa !9
  %96 = load i32, ptr %13, align 4, !tbaa !9
  %97 = load i32, ptr %14, align 4, !tbaa !9
  %98 = load i16, ptr %11, align 2, !tbaa !11
  %99 = zext i16 %98 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %94, i32 noundef %95, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %96, i32 noundef %97, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %99)
  br label %107

100:                                              ; preds = %90
  %101 = load ptr, ptr %8, align 8, !tbaa !5
  %102 = load i32, ptr %9, align 4, !tbaa !9
  %103 = load i32, ptr %13, align 4, !tbaa !9
  %104 = load i32, ptr %14, align 4, !tbaa !9
  %105 = load i16, ptr %11, align 2, !tbaa !11
  %106 = zext i16 %105 to i32
  call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %101, i32 noundef %102, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %103, i32 noundef %104, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %106)
  br label %107

107:                                              ; preds = %100, %93
  br label %108

108:                                              ; preds = %107
  %109 = load i32, ptr %14, align 4, !tbaa !9
  %110 = add i32 %109, 1
  store i32 %110, ptr %14, align 4, !tbaa !9
  br label %87, !llvm.loop !18

111:                                              ; preds = %87
  br label %112

112:                                              ; preds = %111
  %113 = load i32, ptr %13, align 4, !tbaa !9
  %114 = add i32 %113, 1
  store i32 %114, ptr %13, align 4, !tbaa !9
  br label %82, !llvm.loop !19

115:                                              ; preds = %82
  %116 = load ptr, ptr %8, align 8, !tbaa !5
  %117 = load ptr, ptr %7, align 8, !tbaa !5
  call void @dump_code_buffer(ptr noundef %116, ptr noundef %117)
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  ret void
}

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}
!18 = distinct !{!18, !14}
!19 = distinct !{!19, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @reset_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dump_code_buffer(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @test_evex_compute_3reg_general(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i16 noundef zeroext %4, i32 noundef %5) local_unnamed_addr #0 {
  %7 = icmp ne i32 %5, 32
  %8 = zext i1 %7 to i32
  tail call void @reset_code_buffer(ptr noundef %1, ptr noundef %0)
  %.not49 = icmp eq i32 %3, 0
  %9 = zext i16 %4 to i32
  br i1 %.not49, label %.preheader52.us, label %.preheader52

.preheader52.us:                                  ; preds = %6, %.preheader52.us
  %.054.us = phi i32 [ %10, %.preheader52.us ], [ 0, %6 ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 1, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 2, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 3, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 4, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 5, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 6, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054.us, i32 noundef 0, i32 noundef 0, i32 noundef 7, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  %10 = add nuw nsw i32 %.054.us, 1
  %exitcond67.not = icmp eq i32 %10, 32
  br i1 %exitcond67.not, label %.split57.us, label %.preheader52.us, !llvm.loop !5

.preheader52:                                     ; preds = %6, %.preheader52
  %.054 = phi i32 [ %11, %.preheader52 ], [ 0, %6 ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 1, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 2, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 3, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 4, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 5, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 6, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef %.054, i32 noundef 255, i32 noundef 0, i32 noundef 7, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  %11 = add nuw nsw i32 %.054, 1
  %exitcond.not = icmp eq i32 %11, 32
  br i1 %exitcond.not, label %.split57.us, label %.preheader52, !llvm.loop !5

.split57.us:                                      ; preds = %.preheader52, %.preheader52.us
  br i1 %.not49, label %.preheader50, label %.loopexit.thread

.preheader50:                                     ; preds = %.split57.us, %.preheader50
  %.159 = phi i32 [ %12, %.preheader50 ], [ 0, %.split57.us ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 1, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 2, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 3, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 4, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 5, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 6, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef %.159, i32 noundef 0, i32 noundef 7, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  %12 = add nuw nsw i32 %.159, 1
  %exitcond69.not = icmp eq i32 %12, 32
  br i1 %exitcond69.not, label %.loopexit, label %.preheader50, !llvm.loop !7

.loopexit:                                        ; preds = %.preheader50
  %13 = icmp ult i32 %8, %5
  br i1 %13, label %.preheader.lr.ph, label %._crit_edge

.loopexit.thread:                                 ; preds = %.split57.us
  %14 = icmp ult i32 %8, %5
  br i1 %14, label %.preheader.preheader, label %._crit_edge

.preheader.lr.ph:                                 ; preds = %.loopexit
  br i1 %.not49, label %.preheader.us, label %.preheader.preheader

.preheader.preheader:                             ; preds = %.loopexit.thread, %.preheader.lr.ph
  br label %.preheader

.preheader.us:                                    ; preds = %.preheader.lr.ph, %.preheader.us
  %.263.us = phi i32 [ %15, %.preheader.us ], [ %8, %.preheader.lr.ph ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 1, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 2, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 3, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 4, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 5, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 6, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 0, i32 noundef %.263.us, i32 noundef 7, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  %15 = add nuw i32 %.263.us, 1
  %exitcond73.not = icmp eq i32 %15, %5
  br i1 %exitcond73.not, label %._crit_edge, label %.preheader.us, !llvm.loop !8

.preheader:                                       ; preds = %.preheader.preheader, %.preheader
  %.263 = phi i32 [ %16, %.preheader ], [ %8, %.preheader.preheader ]
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 0, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 1, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 2, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 3, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 4, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 5, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 6, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  tail call void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef %1, i32 noundef %2, i8 noundef signext 122, i32 noundef 0, i32 noundef 255, i32 noundef %.263, i32 noundef 7, i32 noundef 0, i8 noundef zeroext 0, i32 noundef %9) #2
  %16 = add nuw i32 %.263, 1
  %exitcond71.not = icmp eq i32 %16, %5
  br i1 %exitcond71.not, label %._crit_edge, label %.preheader, !llvm.loop !8

._crit_edge:                                      ; preds = %.preheader, %.preheader.us, %.loopexit.thread, %.loopexit
  tail call void @dump_code_buffer(ptr noundef %1, ptr noundef %0)
  ret void
}

declare void @libxsmm_x86_instruction_vec_compute_3reg_mask_sae_imm8(ptr noundef, i32 noundef, i8 noundef signext, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass