; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseSynetConvolution16bNhwcSpecV0)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Simd::Base::SynetConvolution16bNhwcSpecV0" = type { %"class.Simd::SynetConvolution16b", %"struct.Simd::Base::SynetConvolution16bNhwcSpecV0::AlgParam", %"struct.Simd::Array.2", ptr, ptr, ptr }
%"class.Simd::SynetConvolution16b" = type { %"struct.Simd::Deletable", %"struct.Simd::ConvParam", %"struct.Simd::Array", %"class.std::__cxx11::basic_string", %"struct.Simd::Array.0", %"struct.Simd::Array.1", %"struct.Simd::Array.1", i8, i8, i8, i64, i64, i64, i64 }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::ConvParam" = type <{ %struct.SimdConvolutionParameters, i32, [4 x i8], i64, i32, [4 x i8] }>
%struct.SimdConvolutionParameters = type { i64, i64, i64, i32, i32, i64, i64, i64, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32 }
%"struct.Simd::Array" = type { ptr, i64 }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.Simd::Array.0" = type { ptr, i64 }
%"struct.Simd::Array.1" = type { ptr, i64 }
%"struct.Simd::Base::SynetConvolution16bNhwcSpecV0::AlgParam" = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 }
%"struct.Simd::Array.2" = type { ptr, i64 }

@_ZTVN4Simd4Base29SynetConvolution16bNhwcSpecV0E = external dso_local unnamed_addr constant { [11 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution16bNhwcSpecV0C2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(568) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN4Simd19SynetConvolution16bC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(328) %7, ptr noundef nonnull align 8 dereferenceable(180) %8)
  store ptr getelementptr inbounds inrange(-16, 72) ({ [11 x ptr] }, ptr @_ZTVN4Simd4Base29SynetConvolution16bNhwcSpecV0E, i32 0, i32 0, i32 2), ptr %7, align 8, !tbaa !9
  %9 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcSpecV0", ptr %7, i32 0, i32 1
  %10 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcSpecV0", ptr %7, i32 0, i32 2
  invoke void @_ZN4Simd5ArrayIiEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %10, i64 noundef 0, i1 noundef zeroext false, i64 noundef 8)
          to label %11 unwind label %15

11:                                               ; preds = %2
  %12 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcSpecV0", ptr %7, i32 0, i32 3
  store ptr null, ptr %12, align 8, !tbaa !11
  %13 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcSpecV0", ptr %7, i32 0, i32 4
  store ptr null, ptr %13, align 8, !tbaa !31
  %14 = getelementptr inbounds %"class.Simd::Base::SynetConvolution16bNhwcSpecV0", ptr %7, i32 0, i32 5
  store ptr null, ptr %14, align 8, !tbaa !32
  ret void

15:                                               ; preds = %2
  %16 = landingpad { ptr, i32 }
          cleanup
  %17 = extractvalue { ptr, i32 } %16, 0
  store ptr %17, ptr %5, align 8
  %18 = extractvalue { ptr, i32 } %16, 1
  store i32 %18, ptr %6, align 4
  call void @_ZN4Simd19SynetConvolution16bD2Ev(ptr noundef nonnull align 8 dereferenceable(328) %7) #4
  br label %19

19:                                               ; preds = %15
  %20 = load ptr, ptr %5, align 8
  %21 = load i32, ptr %6, align 4
  %22 = insertvalue { ptr, i32 } poison, ptr %20, 0
  %23 = insertvalue { ptr, i32 } %22, i32 %21, 1
  resume { ptr, i32 } %23
}

declare void @_ZN4Simd19SynetConvolution16bC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIiEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #2 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd19SynetConvolution16bD2Ev(ptr noundef nonnull align 8 dereferenceable(328)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 544}
!12 = !{!"_ZTSN4Simd4Base29SynetConvolution16bNhwcSpecV0E", !13, i64 0, !29, i64 328, !30, i64 528, !6, i64 544, !6, i64 552, !6, i64 560}
!13 = !{!"_ZTSN4Simd19SynetConvolution16bE", !14, i64 0, !15, i64 8, !23, i64 192, !24, i64 208, !26, i64 240, !27, i64 256, !27, i64 272, !28, i64 288, !28, i64 289, !28, i64 290, !17, i64 296, !17, i64 304, !17, i64 312, !17, i64 320}
!14 = !{!"_ZTSN4Simd9DeletableE"}
!15 = !{!"_ZTSN4Simd9ConvParamE", !16, i64 0, !21, i64 160, !17, i64 168, !22, i64 176}
!16 = !{!"_ZTS25SimdConvolutionParameters", !17, i64 0, !17, i64 8, !17, i64 16, !18, i64 24, !19, i64 28, !17, i64 32, !17, i64 40, !17, i64 48, !18, i64 56, !19, i64 60, !17, i64 64, !17, i64 72, !17, i64 80, !17, i64 88, !17, i64 96, !17, i64 104, !17, i64 112, !17, i64 120, !17, i64 128, !17, i64 136, !17, i64 144, !20, i64 152}
!17 = !{!"long", !7, i64 0}
!18 = !{!"_ZTS18SimdTensorDataType", !7, i64 0}
!19 = !{!"_ZTS20SimdTensorFormatType", !7, i64 0}
!20 = !{!"_ZTS29SimdConvolutionActivationType", !7, i64 0}
!21 = !{!"_ZTS8SimdBool", !7, i64 0}
!22 = !{!"_ZTS26SimdSynetCompatibilityType", !7, i64 0}
!23 = !{!"_ZTSN4Simd5ArrayIhEE", !6, i64 0, !17, i64 8}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !25, i64 0, !17, i64 8, !7, i64 16}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!26 = !{!"_ZTSN4Simd5ArrayItEE", !6, i64 0, !17, i64 8}
!27 = !{!"_ZTSN4Simd5ArrayIfEE", !6, i64 0, !17, i64 8}
!28 = !{!"bool", !7, i64 0}
!29 = !{!"_ZTSN4Simd4Base29SynetConvolution16bNhwcSpecV08AlgParamE", !17, i64 0, !17, i64 8, !17, i64 16, !17, i64 24, !17, i64 32, !17, i64 40, !17, i64 48, !17, i64 56, !17, i64 64, !17, i64 72, !17, i64 80, !17, i64 88, !17, i64 96, !17, i64 104, !17, i64 112, !17, i64 120, !17, i64 128, !17, i64 136, !17, i64 144, !17, i64 152, !17, i64 160, !17, i64 168, !17, i64 176, !17, i64 184, !17, i64 192}
!30 = !{!"_ZTSN4Simd5ArrayIiEE", !6, i64 0, !17, i64 8}
!31 = !{!12, !6, i64 552}
!32 = !{!12, !6, i64 560}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN4Simd4Base29SynetConvolution16bNhwcSpecV0E = external dso_local unnamed_addr constant { [11 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base29SynetConvolution16bNhwcSpecV0C2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(568) %0, ptr noundef nonnull align 8 dereferenceable(180) %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN4Simd19SynetConvolution16bC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(328) %0, ptr noundef nonnull align 8 dereferenceable(180) %1)
  store ptr getelementptr inbounds inrange(-16, 72) (i8, ptr @_ZTVN4Simd4Base29SynetConvolution16bNhwcSpecV0E, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 528
  invoke void @_ZN4Simd5ArrayIiEC2Embm(ptr noundef nonnull align 8 dereferenceable(16) %3, i64 noundef 0, i1 noundef zeroext false, i64 noundef 8)
          to label %4 unwind label %6

4:                                                ; preds = %2
  %5 = getelementptr inbounds i8, ptr %0, i64 544
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %5, i8 0, i64 24, i1 false)
  ret void

6:                                                ; preds = %2
  %7 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN4Simd19SynetConvolution16bD2Ev(ptr noundef nonnull align 8 dereferenceable(328) %0) #5
  resume { ptr, i32 } %7
}

declare void @_ZN4Simd19SynetConvolution16bC2ERKNS_9ConvParamE(ptr noundef nonnull align 8 dereferenceable(328), ptr noundef nonnull align 8 dereferenceable(180)) unnamed_addr #1

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local void @_ZN4Simd5ArrayIiEC2Embm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef, i1 noundef zeroext, i64 noundef) unnamed_addr #2 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4Simd19SynetConvolution16bD2Ev(ptr noundef nonnull align 8 dereferenceable(328)) unnamed_addr #3 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,InstCombinePass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass