; LLVM IR from ermig1979/Simd :: src/Simd (SimdBaseDetection)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Detection::Data" = type { %"struct.Simd::Deletable", i8, i8, i8, i32, i32, i32, %"struct.Simd::Point", %"class.std::vector", %"class.std::vector.4", %"class.std::vector.9", %"class.std::vector.14", %"class.std::vector.19", %"class.std::vector.24", %"class.std::vector.29" }
%"struct.Simd::Deletable" = type { ptr }
%"struct.Simd::Point" = type { i64, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::Stage, std::allocator<Simd::Detection::Data::Stage>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.4" = type { %"struct.std::_Vector_base.5" }
%"struct.std::_Vector_base.5" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTree, std::allocator<Simd::Detection::Data::DTree>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.9" = type { %"struct.std::_Vector_base.10" }
%"struct.std::_Vector_base.10" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::DTreeNode, std::allocator<Simd::Detection::Data::DTreeNode>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.14" = type { %"struct.std::_Vector_base.15" }
%"struct.std::_Vector_base.15" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.19" = type { %"struct.std::_Vector_base.20" }
%"struct.std::_Vector_base.20" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.24" = type { %"struct.std::_Vector_base.25" }
%"struct.std::_Vector_base.25" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::HaarFeature, std::allocator<Simd::Detection::Data::HaarFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.29" = type { %"struct.std::_Vector_base.30" }
%"struct.std::_Vector_base.30" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl" = type { %"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Simd::Detection::Data::LbpFeature, std::allocator<Simd::Detection::Data::LbpFeature>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.Simd::Detection::Data::Stage" = type { i32, i32, float }
%"struct.Simd::Detection::HidLbpStage.61" = type { i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base7InitLbpIiEEvRKNS_9Detection4DataEmPNS2_11HidLbpStageIT_EEPS7_(ptr noundef nonnull align 8 dereferenceable(208) %0, i64 noundef %1, ptr noundef %2, ptr noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca float, align 4
  %10 = alloca float, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca float, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #6
  store float 0.000000e+00, ptr %9, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #6
  store float 0.000000e+00, ptr %10, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #6
  store i32 0, ptr %11, align 4, !tbaa !13
  br label %16

16:                                               ; preds = %57, %4
  %17 = load i32, ptr %11, align 4, !tbaa !13
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %18, i32 0, i32 8
  %20 = load i64, ptr %6, align 8, !tbaa !9
  %21 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %20) #6
  %22 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %21, i32 0, i32 1
  %23 = load i32, ptr %22, align 4, !tbaa !15
  %24 = icmp slt i32 %17, %23
  br i1 %24, label %26, label %25

25:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #6
  br label %60

26:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #6
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %27, i32 0, i32 11
  %29 = call noundef ptr @_ZNKSt6vectorIfSaIfEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %28) #6
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %30, i32 0, i32 8
  %32 = load i64, ptr %6, align 8, !tbaa !9
  %33 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %32) #6
  %34 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %33, i32 0, i32 0
  %35 = load i32, ptr %34, align 4, !tbaa !17
  %36 = load i32, ptr %11, align 4, !tbaa !13
  %37 = add nsw i32 %35, %36
  %38 = mul nsw i32 %37, 2
  %39 = sext i32 %38 to i64
  %40 = getelementptr inbounds float, ptr %29, i64 %39
  store ptr %40, ptr %12, align 8, !tbaa !5
  %41 = load ptr, ptr %12, align 8, !tbaa !5
  %42 = getelementptr inbounds float, ptr %41, i64 0
  %43 = load ptr, ptr %12, align 8, !tbaa !5
  %44 = getelementptr inbounds float, ptr %43, i64 1
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %42, ptr noundef nonnull align 4 dereferenceable(4) %44)
  %46 = load float, ptr %45, align 4, !tbaa !11
  %47 = load float, ptr %9, align 4, !tbaa !11
  %48 = fadd float %47, %46
  store float %48, ptr %9, align 4, !tbaa !11
  %49 = load ptr, ptr %12, align 8, !tbaa !5
  %50 = getelementptr inbounds float, ptr %49, i64 0
  %51 = load ptr, ptr %12, align 8, !tbaa !5
  %52 = getelementptr inbounds float, ptr %51, i64 1
  %53 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %50, ptr noundef nonnull align 4 dereferenceable(4) %52)
  %54 = load float, ptr %53, align 4, !tbaa !11
  %55 = load float, ptr %10, align 4, !tbaa !11
  %56 = fadd float %55, %54
  store float %56, ptr %10, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #6
  br label %57

57:                                               ; preds = %26
  %58 = load i32, ptr %11, align 4, !tbaa !13
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %11, align 4, !tbaa !13
  br label %16, !llvm.loop !18

60:                                               ; preds = %25
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #6
  %61 = load float, ptr %9, align 4, !tbaa !11
  %62 = call noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef %61)
  %63 = load float, ptr %10, align 4, !tbaa !11
  %64 = call noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef %63)
  %65 = call noundef float @_ZN4Simd3MaxIfEET_S1_S1_(float noundef %62, float noundef %64)
  %66 = fdiv float 0x40DCCC9320000000, %65
  store float %66, ptr %13, align 4, !tbaa !11
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %67, i32 0, i32 8
  %69 = load i64, ptr %6, align 8, !tbaa !9
  %70 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %69) #6
  %71 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %70, i32 0, i32 0
  %72 = load i32, ptr %71, align 4, !tbaa !17
  %73 = load ptr, ptr %7, align 8, !tbaa !5
  %74 = load i64, ptr %6, align 8, !tbaa !9
  %75 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %73, i64 %74
  %76 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %75, i32 0, i32 0
  store i32 %72, ptr %76, align 4, !tbaa !20
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  %78 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %77, i32 0, i32 8
  %79 = load i64, ptr %6, align 8, !tbaa !9
  %80 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %79) #6
  %81 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %80, i32 0, i32 1
  %82 = load i32, ptr %81, align 4, !tbaa !15
  %83 = load ptr, ptr %7, align 8, !tbaa !5
  %84 = load i64, ptr %6, align 8, !tbaa !9
  %85 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %83, i64 %84
  %86 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %85, i32 0, i32 1
  store i32 %82, ptr %86, align 4, !tbaa !22
  %87 = load ptr, ptr %5, align 8, !tbaa !5
  %88 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %87, i32 0, i32 8
  %89 = load i64, ptr %6, align 8, !tbaa !9
  %90 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %88, i64 noundef %89) #6
  %91 = getelementptr inbounds %"struct.Simd::Detection::Data::Stage", ptr %90, i32 0, i32 2
  %92 = load float, ptr %91, align 4, !tbaa !23
  %93 = load float, ptr %13, align 4, !tbaa !11
  %94 = fmul float %92, %93
  %95 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %94)
  %96 = load ptr, ptr %7, align 8, !tbaa !5
  %97 = load i64, ptr %6, align 8, !tbaa !9
  %98 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %96, i64 %97
  %99 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %98, i32 0, i32 2
  store i32 %95, ptr %99, align 4, !tbaa !24
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #6
  %100 = load ptr, ptr %7, align 8, !tbaa !5
  %101 = load i64, ptr %6, align 8, !tbaa !9
  %102 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %100, i64 %101
  %103 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %102, i32 0, i32 0
  %104 = load i32, ptr %103, align 4, !tbaa !20
  %105 = mul nsw i32 %104, 2
  store i32 %105, ptr %14, align 4, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #6
  %106 = load ptr, ptr %7, align 8, !tbaa !5
  %107 = load i64, ptr %6, align 8, !tbaa !9
  %108 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %106, i64 %107
  %109 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %108, i32 0, i32 0
  %110 = load i32, ptr %109, align 4, !tbaa !20
  %111 = load ptr, ptr %7, align 8, !tbaa !5
  %112 = load i64, ptr %6, align 8, !tbaa !9
  %113 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %111, i64 %112
  %114 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %113, i32 0, i32 1
  %115 = load i32, ptr %114, align 4, !tbaa !22
  %116 = add nsw i32 %110, %115
  %117 = mul nsw i32 %116, 2
  store i32 %117, ptr %15, align 4, !tbaa !13
  br label %118

118:                                              ; preds = %137, %60
  %119 = load i32, ptr %14, align 4, !tbaa !13
  %120 = load i32, ptr %15, align 4, !tbaa !13
  %121 = icmp slt i32 %119, %120
  br i1 %121, label %123, label %122

122:                                              ; preds = %118
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #6
  br label %140

123:                                              ; preds = %118
  %124 = load ptr, ptr %5, align 8, !tbaa !5
  %125 = getelementptr inbounds %"struct.Simd::Detection::Data", ptr %124, i32 0, i32 11
  %126 = load i32, ptr %14, align 4, !tbaa !13
  %127 = sext i32 %126 to i64
  %128 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %125, i64 noundef %127) #6
  %129 = load float, ptr %128, align 4, !tbaa !11
  %130 = load float, ptr %13, align 4, !tbaa !11
  %131 = fmul float %129, %130
  %132 = call noundef i32 @_ZN4Simd5RoundEf(float noundef %131)
  %133 = load ptr, ptr %8, align 8, !tbaa !5
  %134 = load i32, ptr %14, align 4, !tbaa !13
  %135 = sext i32 %134 to i64
  %136 = getelementptr inbounds i32, ptr %133, i64 %135
  store i32 %132, ptr %136, align 4, !tbaa !13
  br label %137

137:                                              ; preds = %123
  %138 = load i32, ptr %14, align 4, !tbaa !13
  %139 = add nsw i32 %138, 1
  store i32 %139, ptr %14, align 4, !tbaa !13
  br label %118, !llvm.loop !25

140:                                              ; preds = %122
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #6
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNKSt6vectorIfSaIfEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd3MaxIfEET_S1_S1_(float noundef, float noundef) #4

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef) #4

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd5RoundEf(float noundef) #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"float", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!16, !14, i64 4}
!16 = !{!"_ZTSN4Simd9Detection4Data5StageE", !14, i64 0, !14, i64 4, !12, i64 8}
!17 = !{!16, !14, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!21, !14, i64 0}
!21 = !{!"_ZTSN4Simd9Detection11HidLbpStageIiEE", !14, i64 0, !14, i64 4, !14, i64 8}
!22 = !{!21, !14, i64 4}
!23 = !{!16, !12, i64 8}
!24 = !{!21, !14, i64 8}
!25 = distinct !{!25, !19}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.Simd::Detection::HidLbpStage.61" = type { i32, i32, i32 }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Simd4Base7InitLbpIiEEvRKNS_9Detection4DataEmPNS2_11HidLbpStageIT_EEPS7_(ptr noundef nonnull align 8 dereferenceable(208) %0, i64 noundef %1, ptr nocapture noundef %2, ptr nocapture noundef writeonly %3) local_unnamed_addr #1 {
  %5 = getelementptr inbounds i8, ptr %0, i64 40
  %6 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %7 = getelementptr inbounds i8, ptr %6, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !5
  %9 = icmp sgt i32 %8, 0
  br i1 %9, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %4
  %10 = getelementptr inbounds i8, ptr %0, i64 112
  br label %36

._crit_edge:                                      ; preds = %36, %4
  %.043.lcssa = phi float [ 0.000000e+00, %4 ], [ %50, %36 ]
  %.0.lcssa = phi float [ 0.000000e+00, %4 ], [ %47, %36 ]
  %11 = tail call noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef %.0.lcssa)
  %12 = tail call noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef %.043.lcssa)
  %13 = tail call noundef float @_ZN4Simd3MaxIfEET_S1_S1_(float noundef %11, float noundef %12)
  %14 = fdiv float 0x40DCCC9320000000, %13
  %15 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %16 = load i32, ptr %15, align 4, !tbaa !11
  %17 = getelementptr inbounds %"struct.Simd::Detection::HidLbpStage.61", ptr %2, i64 %1
  store i32 %16, ptr %17, align 4, !tbaa !12
  %18 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %19 = getelementptr inbounds i8, ptr %18, i64 4
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %17, i64 4
  store i32 %20, ptr %21, align 4, !tbaa !14
  %22 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %23 = getelementptr inbounds i8, ptr %22, i64 8
  %24 = load float, ptr %23, align 4, !tbaa !15
  %25 = fmul float %14, %24
  %26 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %25)
  %27 = getelementptr inbounds i8, ptr %17, i64 8
  store i32 %26, ptr %27, align 4, !tbaa !16
  %28 = load i32, ptr %21, align 4, !tbaa !14
  %29 = icmp sgt i32 %28, 0
  br i1 %29, label %.lr.ph52, label %._crit_edge53

.lr.ph52:                                         ; preds = %._crit_edge
  %30 = load i32, ptr %17, align 4, !tbaa !12
  %31 = shl nsw i32 %30, 1
  %32 = getelementptr inbounds i8, ptr %0, i64 112
  %33 = sext i32 %31 to i64
  %34 = add i32 %28, %30
  %35 = shl i32 %34, 1
  br label %56

36:                                               ; preds = %.lr.ph, %36
  %.047 = phi float [ 0.000000e+00, %.lr.ph ], [ %47, %36 ]
  %.04346 = phi float [ 0.000000e+00, %.lr.ph ], [ %50, %36 ]
  %.04445 = phi i32 [ 0, %.lr.ph ], [ %51, %36 ]
  %37 = tail call noundef ptr @_ZNKSt6vectorIfSaIfEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #5
  %38 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %39 = load i32, ptr %38, align 4, !tbaa !11
  %40 = add nsw i32 %39, %.04445
  %41 = shl nsw i32 %40, 1
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds float, ptr %37, i64 %42
  %44 = getelementptr inbounds i8, ptr %43, i64 4
  %45 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %43, ptr noundef nonnull align 4 dereferenceable(4) %44)
  %46 = load float, ptr %45, align 4, !tbaa !17
  %47 = fadd float %.047, %46
  %48 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %43, ptr noundef nonnull align 4 dereferenceable(4) %44)
  %49 = load float, ptr %48, align 4, !tbaa !17
  %50 = fadd float %.04346, %49
  %51 = add nuw nsw i32 %.04445, 1
  %52 = tail call noundef nonnull align 4 dereferenceable(12) ptr @_ZNKSt6vectorIN4Simd9Detection4Data5StageESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %1) #5
  %53 = getelementptr inbounds i8, ptr %52, i64 4
  %54 = load i32, ptr %53, align 4, !tbaa !5
  %55 = icmp slt i32 %51, %54
  br i1 %55, label %36, label %._crit_edge, !llvm.loop !18

._crit_edge53:                                    ; preds = %56, %._crit_edge
  ret void

56:                                               ; preds = %.lr.ph52, %56
  %indvars.iv = phi i64 [ %33, %.lr.ph52 ], [ %indvars.iv.next, %56 ]
  %57 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %indvars.iv) #5
  %58 = load float, ptr %57, align 4, !tbaa !17
  %59 = fmul float %14, %58
  %60 = tail call noundef i32 @_ZN4Simd5RoundEf(float noundef %59)
  %61 = getelementptr inbounds i32, ptr %3, i64 %indvars.iv
  store i32 %60, ptr %61, align 4, !tbaa !20
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond.not = icmp eq i32 %35, %lftr.wideiv
  br i1 %exitcond.not, label %._crit_edge53, label %56, !llvm.loop !21
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNKSt6vectorIfSaIfEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIfERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd3MaxIfEET_S1_S1_(float noundef, float noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local noundef float @_ZN4Simd3AbsIfEET_S1_(float noundef) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress uwtable
declare dso_local noundef i32 @_ZN4Simd5RoundEf(float noundef) local_unnamed_addr #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTSN4Simd9Detection4Data5StageE", !7, i64 0, !7, i64 4, !10, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"float", !8, i64 0}
!11 = !{!6, !7, i64 0}
!12 = !{!13, !7, i64 0}
!13 = !{!"_ZTSN4Simd9Detection11HidLbpStageIiEE", !7, i64 0, !7, i64 4, !7, i64 8}
!14 = !{!13, !7, i64 4}
!15 = !{!6, !10, i64 8}
!16 = !{!13, !7, i64 8}
!17 = !{!10, !10, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!7, !7, i64 0}
!21 = distinct !{!21, !19}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass