; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_load_16x64_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %14 = load i32, ptr %9, align 4, !tbaa !9
  %15 = udiv i32 %14, 16
  store i32 %15, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 0, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  %16 = load i32, ptr %9, align 4, !tbaa !9
  %17 = urem i32 %16, 16
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %22

19:                                               ; preds = %5
  %20 = load i32, ptr %11, align 4, !tbaa !9
  %21 = add i32 %20, 1
  store i32 %21, ptr %11, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %19, %5
  %23 = load ptr, ptr %6, align 8, !tbaa !5
  %24 = load i32, ptr %11, align 4, !tbaa !9
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %23, i32 noundef %24)
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = load i32, ptr %8, align 4, !tbaa !9
  %27 = icmp ult i32 %26, 16
  br i1 %27, label %28, label %31

28:                                               ; preds = %22
  %29 = load i32, ptr %8, align 4, !tbaa !9
  %30 = mul nsw i32 %29, 4
  br label %32

31:                                               ; preds = %22
  br label %32

32:                                               ; preds = %31, %28
  %33 = phi i32 [ %30, %28 ], [ -1, %31 ]
  call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %25, i32 noundef 0, i32 noundef %33, i32 noundef 41)
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %34

34:                                               ; preds = %54, %32
  %35 = load i32, ptr %12, align 4, !tbaa !9
  %36 = load i32, ptr %9, align 4, !tbaa !9
  %37 = icmp ult i32 %36, 32
  br i1 %37, label %38, label %40

38:                                               ; preds = %34
  %39 = load i32, ptr %9, align 4, !tbaa !9
  br label %41

40:                                               ; preds = %34
  br label %41

41:                                               ; preds = %40, %38
  %42 = phi i32 [ %39, %38 ], [ 32, %40 ]
  %43 = icmp ult i32 %35, %42
  br i1 %43, label %44, label %57

44:                                               ; preds = %41
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = load i32, ptr %7, align 4, !tbaa !9
  %47 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %45, i32 noundef -1522491258, i32 noundef %46, i32 noundef 127, i32 noundef 0, i32 noundef %47, i32 noundef 0)
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = load i32, ptr %7, align 4, !tbaa !9
  %51 = load i32, ptr %10, align 4, !tbaa !9
  %52 = mul i32 %51, 4
  %53 = zext i32 %52 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %48, i32 noundef 4096, i32 noundef %49, i32 noundef 43, i32 noundef %50, i64 noundef %53)
  br label %54

54:                                               ; preds = %44
  %55 = load i32, ptr %12, align 4, !tbaa !9
  %56 = add i32 %55, 1
  store i32 %56, ptr %12, align 4, !tbaa !9
  br label %34, !llvm.loop !11

57:                                               ; preds = %41
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %65, %57
  %59 = load i32, ptr %13, align 4, !tbaa !9
  %60 = icmp ult i32 %59, 4
  br i1 %60, label %61, label %68

61:                                               ; preds = %58
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %62, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef %63)
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %64, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %65

65:                                               ; preds = %61
  %66 = load i32, ptr %13, align 4, !tbaa !9
  %67 = add i32 %66, 1
  store i32 %67, ptr %13, align 4, !tbaa !9
  br label %58, !llvm.loop !13

68:                                               ; preds = %58
  %69 = load i32, ptr %9, align 4, !tbaa !9
  %70 = icmp ugt i32 %69, 16
  br i1 %70, label %71, label %83

71:                                               ; preds = %68
  store i32 4, ptr %13, align 4, !tbaa !9
  br label %72

72:                                               ; preds = %79, %71
  %73 = load i32, ptr %13, align 4, !tbaa !9
  %74 = icmp ult i32 %73, 8
  br i1 %74, label %75, label %82

75:                                               ; preds = %72
  %76 = load ptr, ptr %6, align 8, !tbaa !5
  %77 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %76, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef %77)
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %78, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %79

79:                                               ; preds = %75
  %80 = load i32, ptr %13, align 4, !tbaa !9
  %81 = add i32 %80, 1
  store i32 %81, ptr %13, align 4, !tbaa !9
  br label %72, !llvm.loop !14

82:                                               ; preds = %72
  br label %83

83:                                               ; preds = %82, %68
  %84 = load i32, ptr %9, align 4, !tbaa !9
  %85 = icmp ugt i32 %84, 32
  br i1 %85, label %86, label %132

86:                                               ; preds = %83
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %87

87:                                               ; preds = %102, %86
  %88 = load i32, ptr %12, align 4, !tbaa !9
  %89 = load i32, ptr %9, align 4, !tbaa !9
  %90 = sub i32 %89, 32
  %91 = icmp ult i32 %88, %90
  br i1 %91, label %92, label %105

92:                                               ; preds = %87
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  %94 = load i32, ptr %7, align 4, !tbaa !9
  %95 = load i32, ptr %12, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %93, i32 noundef -1522491258, i32 noundef %94, i32 noundef 127, i32 noundef 0, i32 noundef %95, i32 noundef 0)
  %96 = load ptr, ptr %6, align 8, !tbaa !5
  %97 = load i32, ptr %7, align 4, !tbaa !9
  %98 = load i32, ptr %7, align 4, !tbaa !9
  %99 = load i32, ptr %10, align 4, !tbaa !9
  %100 = mul i32 %99, 4
  %101 = zext i32 %100 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %96, i32 noundef 4096, i32 noundef %97, i32 noundef 43, i32 noundef %98, i64 noundef %101)
  br label %102

102:                                              ; preds = %92
  %103 = load i32, ptr %12, align 4, !tbaa !9
  %104 = add i32 %103, 1
  store i32 %104, ptr %12, align 4, !tbaa !9
  br label %87, !llvm.loop !15

105:                                              ; preds = %87
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %106

106:                                              ; preds = %113, %105
  %107 = load i32, ptr %13, align 4, !tbaa !9
  %108 = icmp ult i32 %107, 4
  br i1 %108, label %109, label %116

109:                                              ; preds = %106
  %110 = load ptr, ptr %6, align 8, !tbaa !5
  %111 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %110, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef %111)
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %112, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0)
  br label %113

113:                                              ; preds = %109
  %114 = load i32, ptr %13, align 4, !tbaa !9
  %115 = add i32 %114, 1
  store i32 %115, ptr %13, align 4, !tbaa !9
  br label %106, !llvm.loop !16

116:                                              ; preds = %106
  %117 = load i32, ptr %9, align 4, !tbaa !9
  %118 = icmp ugt i32 %117, 48
  br i1 %118, label %119, label %131

119:                                              ; preds = %116
  store i32 4, ptr %13, align 4, !tbaa !9
  br label %120

120:                                              ; preds = %127, %119
  %121 = load i32, ptr %13, align 4, !tbaa !9
  %122 = icmp ult i32 %121, 8
  br i1 %122, label %123, label %130

123:                                              ; preds = %120
  %124 = load ptr, ptr %6, align 8, !tbaa !5
  %125 = load i32, ptr %13, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %124, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef %125)
  %126 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %126, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0)
  br label %127

127:                                              ; preds = %123
  %128 = load i32, ptr %13, align 4, !tbaa !9
  %129 = add i32 %128, 1
  store i32 %129, ptr %13, align 4, !tbaa !9
  br label %120, !llvm.loop !17

130:                                              ; preds = %120
  br label %131

131:                                              ; preds = %130, %116
  br label %132

132:                                              ; preds = %131, %83
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sve_move(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_load_16x64_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = lshr i32 %3, 4
  %7 = and i32 %3, 15
  %.not = icmp ne i32 %7, 0
  %8 = zext i1 %.not to i32
  %spec.select = add nuw nsw i32 %6, %8
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef %spec.select)
  %9 = icmp ult i32 %2, 16
  %10 = shl nuw nsw i32 %2, 2
  %11 = select i1 %9, i32 %10, i32 -1
  tail call void @libxsmm_generator_set_p_register_aarch64_sve(ptr noundef %0, i32 noundef 0, i32 noundef %11, i32 noundef 41)
  %12 = tail call i32 @llvm.umin.i32(i32 %3, i32 32)
  %.not66 = icmp eq i32 %3, 0
  br i1 %.not66, label %.preheader58, label %.lr.ph

.lr.ph:                                           ; preds = %5
  %13 = shl i32 %4, 2
  %14 = zext i32 %13 to i64
  br label %16

.preheader58:                                     ; preds = %16, %5
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 0, i32 noundef 12, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  %15 = icmp ugt i32 %3, 16
  br i1 %15, label %.preheader57.preheader, label %.thread

16:                                               ; preds = %.lr.ph, %16
  %.05159 = phi i32 [ 0, %.lr.ph ], [ %17, %16 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -1522491258, i32 noundef %1, i32 noundef 127, i32 noundef 0, i32 noundef %.05159, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %14) #3
  %17 = add nuw nsw i32 %.05159, 1
  %exitcond.not = icmp eq i32 %17, %12
  br i1 %exitcond.not, label %.preheader58, label %16, !llvm.loop !5

.preheader57.preheader:                           ; preds = %.preheader58
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 1, i32 noundef 13, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  %18 = icmp ugt i32 %3, 32
  br i1 %18, label %.lr.ph63, label %.thread

.lr.ph63:                                         ; preds = %.preheader57.preheader
  %19 = shl i32 %4, 2
  %20 = zext i32 %19 to i64
  %21 = add i32 %3, -33
  br label %23

.preheader55:                                     ; preds = %23
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 1) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 2) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 2, i32 noundef 14, i32 noundef 3) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  %22 = icmp ugt i32 %3, 48
  br i1 %22, label %.preheader.preheader, label %.thread

23:                                               ; preds = %.lr.ph63, %23
  %.15262 = phi i32 [ 0, %.lr.ph63 ], [ %24, %23 ]
  tail call void @libxsmm_aarch64_instruction_sve_move(ptr noundef %0, i32 noundef -1522491258, i32 noundef %1, i32 noundef 127, i32 noundef 0, i32 noundef %.15262, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %20) #3
  %24 = add nuw i32 %.15262, 1
  %exitcond70.not = icmp eq i32 %.15262, %21
  br i1 %exitcond70.not, label %.preheader55, label %23, !llvm.loop !7

.preheader.preheader:                             ; preds = %.preheader55
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 5) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 6) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1065090048, i32 noundef 3, i32 noundef 15, i32 noundef 7) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  br label %.thread

.thread:                                          ; preds = %.preheader.preheader, %.preheader58, %.preheader55, %.preheader57.preheader
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass