; LLVM IR from NVIDIA/DALI :: dali/pipeline/operator/builtin (make_contiguous)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN4dali12OperatorBaseE = external dso_local constant { ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_10CPUBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_12MixedBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_10GPUBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN4dali21SetMakeContiguousModeERNS_12OperatorBaseENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(400) %0, i32 noundef %1) #2 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %14, label %12

12:                                               ; preds = %2
  %13 = call ptr @__dynamic_cast(ptr %10, ptr @_ZTIN4dali12OperatorBaseE, ptr @_ZTIN4dali18MakeContiguousBaseINS_10CPUBackendEEE, i64 0) #4
  br label %15

14:                                               ; preds = %2
  br label %15

15:                                               ; preds = %14, %12
  %16 = phi ptr [ %13, %12 ], [ null, %14 ]
  store ptr %16, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %22

19:                                               ; preds = %15
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = load i32, ptr %5, align 4, !tbaa !9
  call void @_ZN4dali18MakeContiguousBaseINS_10CPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %20, i32 noundef %21)
  br label %57

22:                                               ; preds = %15
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = icmp eq ptr %23, null
  br i1 %24, label %27, label %25

25:                                               ; preds = %22
  %26 = call ptr @__dynamic_cast(ptr %23, ptr @_ZTIN4dali12OperatorBaseE, ptr @_ZTIN4dali18MakeContiguousBaseINS_12MixedBackendEEE, i64 0) #4
  br label %28

27:                                               ; preds = %22
  br label %28

28:                                               ; preds = %27, %25
  %29 = phi ptr [ %26, %25 ], [ null, %27 ]
  store ptr %29, ptr %7, align 8, !tbaa !5
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = icmp ne ptr %30, null
  br i1 %31, label %32, label %35

32:                                               ; preds = %28
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = load i32, ptr %5, align 4, !tbaa !9
  call void @_ZN4dali18MakeContiguousBaseINS_12MixedBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %33, i32 noundef %34)
  br label %53

35:                                               ; preds = %28
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = icmp eq ptr %36, null
  br i1 %37, label %40, label %38

38:                                               ; preds = %35
  %39 = call ptr @__dynamic_cast(ptr %36, ptr @_ZTIN4dali12OperatorBaseE, ptr @_ZTIN4dali18MakeContiguousBaseINS_10GPUBackendEEE, i64 0) #4
  br label %41

40:                                               ; preds = %35
  br label %41

41:                                               ; preds = %40, %38
  %42 = phi ptr [ %39, %38 ], [ null, %40 ]
  store ptr %42, ptr %8, align 8, !tbaa !5
  %43 = load ptr, ptr %8, align 8, !tbaa !5
  %44 = icmp ne ptr %43, null
  br i1 %44, label %45, label %48

45:                                               ; preds = %41
  %46 = load ptr, ptr %8, align 8, !tbaa !5
  %47 = load i32, ptr %5, align 4, !tbaa !9
  call void @_ZN4dali18MakeContiguousBaseINS_10GPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %46, i32 noundef %47)
  br label %49

48:                                               ; preds = %41
  store i1 false, ptr %3, align 1
  store i32 1, ptr %9, align 4
  br label %50

49:                                               ; preds = %45
  store i32 0, ptr %9, align 4
  br label %50

50:                                               ; preds = %49, %48
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %51 = load i32, ptr %9, align 4
  switch i32 %51, label %54 [
    i32 0, label %52
  ]

52:                                               ; preds = %50
  br label %53

53:                                               ; preds = %52, %32
  store i32 0, ptr %9, align 4
  br label %54

54:                                               ; preds = %53, %50
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  %55 = load i32, ptr %9, align 4
  switch i32 %55, label %58 [
    i32 0, label %56
  ]

56:                                               ; preds = %54
  br label %57

57:                                               ; preds = %56, %19
  store i32 0, ptr %9, align 4
  br label %58

58:                                               ; preds = %57, %54
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  %59 = load i32, ptr %9, align 4
  switch i32 %59, label %63 [
    i32 0, label %60
    i32 1, label %61
  ]

60:                                               ; preds = %58
  store i1 true, ptr %3, align 1
  br label %61

61:                                               ; preds = %60, %58
  %62 = load i1, ptr %3, align 1
  ret i1 %62

63:                                               ; preds = %58
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_10CPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_12MixedBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_10GPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind willreturn memory(read) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN4dali18MakeContiguousModeE", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTIN4dali12OperatorBaseE = external dso_local constant { ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_10CPUBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_12MixedBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8
@_ZTIN4dali18MakeContiguousBaseINS_10GPUBackendEEE = external dso_local constant { ptr, ptr, ptr }, align 8

; Function Attrs: mustprogress nofree nounwind willreturn memory(read)
declare ptr @__dynamic_cast(ptr, ptr, ptr, i64) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN4dali21SetMakeContiguousModeERNS_12OperatorBaseENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(400) %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = tail call ptr @__dynamic_cast(ptr nonnull %0, ptr nonnull @_ZTIN4dali12OperatorBaseE, ptr nonnull @_ZTIN4dali18MakeContiguousBaseINS_10CPUBackendEEE, i64 0) #2
  %.not = icmp eq ptr %3, null
  br i1 %.not, label %5, label %4

4:                                                ; preds = %2
  tail call void @_ZN4dali18MakeContiguousBaseINS_10CPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %3, i32 noundef %1)
  br label %.critedge

5:                                                ; preds = %2
  %6 = tail call ptr @__dynamic_cast(ptr nonnull %0, ptr nonnull @_ZTIN4dali12OperatorBaseE, ptr nonnull @_ZTIN4dali18MakeContiguousBaseINS_12MixedBackendEEE, i64 0) #2
  %.not22 = icmp eq ptr %6, null
  br i1 %.not22, label %8, label %7

7:                                                ; preds = %5
  tail call void @_ZN4dali18MakeContiguousBaseINS_12MixedBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %6, i32 noundef %1)
  br label %.critedge

8:                                                ; preds = %5
  %9 = tail call ptr @__dynamic_cast(ptr nonnull %0, ptr nonnull @_ZTIN4dali12OperatorBaseE, ptr nonnull @_ZTIN4dali18MakeContiguousBaseINS_10GPUBackendEEE, i64 0) #2
  %.not23.not = icmp eq ptr %9, null
  br i1 %.not23.not, label %.critedge, label %10

10:                                               ; preds = %8
  tail call void @_ZN4dali18MakeContiguousBaseINS_10GPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716) %9, i32 noundef %1)
  br label %.critedge

.critedge:                                        ; preds = %7, %10, %4, %8
  %.5 = phi i1 [ false, %8 ], [ true, %4 ], [ true, %10 ], [ true, %7 ]
  ret i1 %.5
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_10CPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_12MixedBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4dali18MakeContiguousBaseINS_10GPUBackendEE7SetModeENS_18MakeContiguousModeE(ptr noundef nonnull align 8 dereferenceable(716), i32 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nofree nounwind willreturn memory(read) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass