; LLVM IR from libxsmm/libxsmm :: src (generator_common_aarch64)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_store_64x16_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 0, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  store i32 0, ptr %13, align 4, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_generator_set_w_reg_sme(ptr noundef %14, i32 noundef 4)
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = mul i32 %16, 4
  call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %15, i32 noundef 8, i32 noundef %17, i32 noundef 43, i32 noundef 1)
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %182, %5
  %19 = load i32, ptr %11, align 4, !tbaa !9
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = icmp ugt i32 %20, 8
  %22 = zext i1 %21 to i64
  %23 = select i1 %21, i32 2, i32 1
  %24 = icmp ult i32 %19, %23
  br i1 %24, label %25, label %185

25:                                               ; preds = %18
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %26

26:                                               ; preds = %35, %25
  %27 = load i32, ptr %12, align 4, !tbaa !9
  %28 = icmp ult i32 %27, 2
  br i1 %28, label %29, label %38

29:                                               ; preds = %26
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = load i32, ptr %12, align 4, !tbaa !9
  %32 = mul i32 %31, 4
  %33 = add i32 0, %32
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %30, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef %33)
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %34, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0)
  br label %35

35:                                               ; preds = %29
  %36 = load i32, ptr %12, align 4, !tbaa !9
  %37 = add i32 %36, 1
  store i32 %37, ptr %12, align 4, !tbaa !9
  br label %26, !llvm.loop !11

38:                                               ; preds = %26
  store i32 2, ptr %12, align 4, !tbaa !9
  br label %39

39:                                               ; preds = %48, %38
  %40 = load i32, ptr %12, align 4, !tbaa !9
  %41 = icmp ult i32 %40, 4
  br i1 %41, label %42, label %51

42:                                               ; preds = %39
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = load i32, ptr %12, align 4, !tbaa !9
  %45 = mul i32 %44, 4
  %46 = add i32 1, %45
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %43, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef %46)
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %47, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0)
  br label %48

48:                                               ; preds = %42
  %49 = load i32, ptr %12, align 4, !tbaa !9
  %50 = add i32 %49, 1
  store i32 %50, ptr %12, align 4, !tbaa !9
  br label %39, !llvm.loop !13

51:                                               ; preds = %39
  store i32 4, ptr %12, align 4, !tbaa !9
  br label %52

52:                                               ; preds = %61, %51
  %53 = load i32, ptr %12, align 4, !tbaa !9
  %54 = icmp ult i32 %53, 6
  br i1 %54, label %55, label %64

55:                                               ; preds = %52
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = load i32, ptr %12, align 4, !tbaa !9
  %58 = mul i32 %57, 4
  %59 = add i32 2, %58
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %56, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef %59)
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %60, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0)
  br label %61

61:                                               ; preds = %55
  %62 = load i32, ptr %12, align 4, !tbaa !9
  %63 = add i32 %62, 1
  store i32 %63, ptr %12, align 4, !tbaa !9
  br label %52, !llvm.loop !14

64:                                               ; preds = %52
  store i32 6, ptr %12, align 4, !tbaa !9
  br label %65

65:                                               ; preds = %74, %64
  %66 = load i32, ptr %12, align 4, !tbaa !9
  %67 = icmp ult i32 %66, 8
  br i1 %67, label %68, label %77

68:                                               ; preds = %65
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  %70 = load i32, ptr %12, align 4, !tbaa !9
  %71 = mul i32 %70, 4
  %72 = add i32 3, %71
  call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %69, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef %72)
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %73, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0)
  br label %74

74:                                               ; preds = %68
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = add i32 %75, 1
  store i32 %76, ptr %12, align 4, !tbaa !9
  br label %65, !llvm.loop !15

77:                                               ; preds = %65
  %78 = load i32, ptr %11, align 4, !tbaa !9
  %79 = icmp eq i32 %78, 0
  br i1 %79, label %80, label %130

80:                                               ; preds = %77
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %81

81:                                               ; preds = %101, %80
  %82 = load i32, ptr %13, align 4, !tbaa !9
  %83 = load i32, ptr %9, align 4, !tbaa !9
  %84 = icmp ugt i32 %83, 3
  br i1 %84, label %85, label %86

85:                                               ; preds = %81
  br label %88

86:                                               ; preds = %81
  %87 = load i32, ptr %9, align 4, !tbaa !9
  br label %88

88:                                               ; preds = %86, %85
  %89 = phi i32 [ 4, %85 ], [ %87, %86 ]
  %90 = icmp ult i32 %82, %89
  br i1 %90, label %91, label %104

91:                                               ; preds = %88
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = load i32, ptr %13, align 4, !tbaa !9
  %94 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %92, i32 noundef -1587494912, i32 noundef %93, i32 noundef %94, i32 noundef 0, i32 noundef 8)
  %95 = load ptr, ptr %6, align 8, !tbaa !5
  %96 = load i32, ptr %7, align 4, !tbaa !9
  %97 = load i32, ptr %7, align 4, !tbaa !9
  %98 = load i32, ptr %10, align 4, !tbaa !9
  %99 = mul i32 %98, 4
  %100 = zext i32 %99 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %95, i32 noundef 4096, i32 noundef %96, i32 noundef 43, i32 noundef %97, i64 noundef %100)
  br label %101

101:                                              ; preds = %91
  %102 = load i32, ptr %13, align 4, !tbaa !9
  %103 = add i32 %102, 1
  store i32 %103, ptr %13, align 4, !tbaa !9
  br label %81, !llvm.loop !16

104:                                              ; preds = %88
  store i32 16, ptr %13, align 4, !tbaa !9
  br label %105

105:                                              ; preds = %126, %104
  %106 = load i32, ptr %13, align 4, !tbaa !9
  %107 = load i32, ptr %9, align 4, !tbaa !9
  %108 = icmp ugt i32 %107, 7
  br i1 %108, label %109, label %110

109:                                              ; preds = %105
  br label %113

110:                                              ; preds = %105
  %111 = load i32, ptr %9, align 4, !tbaa !9
  %112 = add i32 %111, 12
  br label %113

113:                                              ; preds = %110, %109
  %114 = phi i32 [ 20, %109 ], [ %112, %110 ]
  %115 = icmp ult i32 %106, %114
  br i1 %115, label %116, label %129

116:                                              ; preds = %113
  %117 = load ptr, ptr %6, align 8, !tbaa !5
  %118 = load i32, ptr %13, align 4, !tbaa !9
  %119 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %117, i32 noundef -1587494912, i32 noundef %118, i32 noundef %119, i32 noundef 0, i32 noundef 8)
  %120 = load ptr, ptr %6, align 8, !tbaa !5
  %121 = load i32, ptr %7, align 4, !tbaa !9
  %122 = load i32, ptr %7, align 4, !tbaa !9
  %123 = load i32, ptr %10, align 4, !tbaa !9
  %124 = mul i32 %123, 4
  %125 = zext i32 %124 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %120, i32 noundef 4096, i32 noundef %121, i32 noundef 43, i32 noundef %122, i64 noundef %125)
  br label %126

126:                                              ; preds = %116
  %127 = load i32, ptr %13, align 4, !tbaa !9
  %128 = add i32 %127, 1
  store i32 %128, ptr %13, align 4, !tbaa !9
  br label %105, !llvm.loop !17

129:                                              ; preds = %113
  br label %181

130:                                              ; preds = %77
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %131

131:                                              ; preds = %152, %130
  %132 = load i32, ptr %13, align 4, !tbaa !9
  %133 = load i32, ptr %9, align 4, !tbaa !9
  %134 = icmp ugt i32 %133, 11
  br i1 %134, label %135, label %136

135:                                              ; preds = %131
  br label %139

136:                                              ; preds = %131
  %137 = load i32, ptr %9, align 4, !tbaa !9
  %138 = sub i32 %137, 8
  br label %139

139:                                              ; preds = %136, %135
  %140 = phi i32 [ 4, %135 ], [ %138, %136 ]
  %141 = icmp ult i32 %132, %140
  br i1 %141, label %142, label %155

142:                                              ; preds = %139
  %143 = load ptr, ptr %6, align 8, !tbaa !5
  %144 = load i32, ptr %13, align 4, !tbaa !9
  %145 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %143, i32 noundef -1587494912, i32 noundef %144, i32 noundef %145, i32 noundef 0, i32 noundef 8)
  %146 = load ptr, ptr %6, align 8, !tbaa !5
  %147 = load i32, ptr %7, align 4, !tbaa !9
  %148 = load i32, ptr %7, align 4, !tbaa !9
  %149 = load i32, ptr %10, align 4, !tbaa !9
  %150 = mul i32 %149, 4
  %151 = zext i32 %150 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %146, i32 noundef 4096, i32 noundef %147, i32 noundef 43, i32 noundef %148, i64 noundef %151)
  br label %152

152:                                              ; preds = %142
  %153 = load i32, ptr %13, align 4, !tbaa !9
  %154 = add i32 %153, 1
  store i32 %154, ptr %13, align 4, !tbaa !9
  br label %131, !llvm.loop !18

155:                                              ; preds = %139
  store i32 16, ptr %13, align 4, !tbaa !9
  br label %156

156:                                              ; preds = %177, %155
  %157 = load i32, ptr %13, align 4, !tbaa !9
  %158 = load i32, ptr %9, align 4, !tbaa !9
  %159 = icmp ugt i32 %158, 15
  br i1 %159, label %160, label %161

160:                                              ; preds = %156
  br label %164

161:                                              ; preds = %156
  %162 = load i32, ptr %9, align 4, !tbaa !9
  %163 = add i32 %162, 4
  br label %164

164:                                              ; preds = %161, %160
  %165 = phi i32 [ 20, %160 ], [ %163, %161 ]
  %166 = icmp ult i32 %157, %165
  br i1 %166, label %167, label %180

167:                                              ; preds = %164
  %168 = load ptr, ptr %6, align 8, !tbaa !5
  %169 = load i32, ptr %13, align 4, !tbaa !9
  %170 = load i32, ptr %7, align 4, !tbaa !9
  call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %168, i32 noundef -1587494912, i32 noundef %169, i32 noundef %170, i32 noundef 0, i32 noundef 8)
  %171 = load ptr, ptr %6, align 8, !tbaa !5
  %172 = load i32, ptr %7, align 4, !tbaa !9
  %173 = load i32, ptr %7, align 4, !tbaa !9
  %174 = load i32, ptr %10, align 4, !tbaa !9
  %175 = mul i32 %174, 4
  %176 = zext i32 %175 to i64
  call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %171, i32 noundef 4096, i32 noundef %172, i32 noundef 43, i32 noundef %173, i64 noundef %176)
  br label %177

177:                                              ; preds = %167
  %178 = load i32, ptr %13, align 4, !tbaa !9
  %179 = add i32 %178, 1
  store i32 %179, ptr %13, align 4, !tbaa !9
  br label %156, !llvm.loop !19

180:                                              ; preds = %164
  br label %181

181:                                              ; preds = %180, %129
  br label %182

182:                                              ; preds = %181
  %183 = load i32, ptr %11, align 4, !tbaa !9
  %184 = add i32 %183, 1
  store i32 %184, ptr %11, align 4, !tbaa !9
  br label %18, !llvm.loop !20

185:                                              ; preds = %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}
!20 = distinct !{!20, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_w_reg_sme(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @libxsmm_aarch64_instruction_sme_mov(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @libxsmm_aarch64_instruction_sme_mova(ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @libxsmm_generated_store_64x16_aarch64_sme(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #1 {
  tail call void @libxsmm_generator_set_w_reg_sme(ptr noundef %0, i32 noundef 4)
  %6 = shl i32 %2, 2
  tail call void @libxsmm_generator_set_pn_register_aarch64_sve2(ptr noundef %0, i32 noundef 8, i32 noundef %6, i32 noundef 43, i32 noundef 1)
  %7 = icmp ugt i32 %3, 8
  %8 = icmp ugt i32 %3, 11
  %9 = add nsw i32 %3, -8
  %10 = select i1 %8, i32 4, i32 %9
  %.not = icmp eq i32 %10, 0
  %11 = shl i32 %4, 2
  %12 = zext i32 %11 to i64
  %13 = icmp ugt i32 %3, 15
  %14 = add nuw nsw i32 %3, 4
  %15 = select i1 %13, i32 20, i32 %14
  %16 = icmp ugt i32 %15, 16
  %17 = tail call i32 @llvm.umin.i32(i32 %3, i32 4)
  %.not95 = icmp eq i32 %3, 0
  %18 = icmp ugt i32 %3, 7
  %19 = add nuw nsw i32 %3, 12
  %20 = select i1 %18, i32 20, i32 %19
  %21 = icmp ugt i32 %20, 16
  br label %.preheader82

.preheader82:                                     ; preds = %5, %.loopexit
  %22 = phi i1 [ true, %5 ], [ false, %.loopexit ]
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 0) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 0, i32 noundef 12, i32 noundef 4) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 12, i32 noundef 12, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 9) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 1, i32 noundef 13, i32 noundef 13) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 13, i32 noundef 13, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 18) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 2, i32 noundef 14, i32 noundef 22) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 14, i32 noundef 14, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 27) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  tail call void @libxsmm_aarch64_instruction_sme_mova(ptr noundef %0, i32 noundef -1064958976, i32 noundef 3, i32 noundef 15, i32 noundef 31) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm12(ptr noundef %0, i32 noundef 285212678, i32 noundef 15, i32 noundef 15, i32 noundef 4, i8 noundef zeroext 0) #3
  br i1 %22, label %.preheader75, label %.preheader78

.preheader78:                                     ; preds = %.preheader82
  br i1 %.not, label %.preheader76, label %.lr.ph

.preheader75:                                     ; preds = %.preheader82
  br i1 %.not95, label %.preheader, label %.lr.ph91

.preheader:                                       ; preds = %.lr.ph91, %.preheader75
  br i1 %21, label %.lr.ph93, label %.loopexit

.lr.ph91:                                         ; preds = %.preheader75, %.lr.ph91
  %.090 = phi i32 [ %23, %.lr.ph91 ], [ 0, %.preheader75 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1587494912, i32 noundef %.090, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %23 = add nuw nsw i32 %.090, 1
  %exitcond98.not = icmp eq i32 %23, %17
  br i1 %exitcond98.not, label %.preheader, label %.lr.ph91, !llvm.loop !5

.lr.ph93:                                         ; preds = %.preheader, %.lr.ph93
  %.192 = phi i32 [ %24, %.lr.ph93 ], [ 16, %.preheader ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1587494912, i32 noundef %.192, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %24 = add nuw i32 %.192, 1
  %exitcond99.not = icmp eq i32 %24, %20
  br i1 %exitcond99.not, label %.loopexit, label %.lr.ph93, !llvm.loop !7

.preheader76:                                     ; preds = %.lr.ph, %.preheader78
  br i1 %16, label %.lr.ph89, label %.loopexit

.lr.ph:                                           ; preds = %.preheader78, %.lr.ph
  %.287 = phi i32 [ %25, %.lr.ph ], [ 0, %.preheader78 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1587494912, i32 noundef %.287, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %25 = add nuw i32 %.287, 1
  %exitcond.not = icmp eq i32 %25, %10
  br i1 %exitcond.not, label %.preheader76, label %.lr.ph, !llvm.loop !8

.lr.ph89:                                         ; preds = %.preheader76, %.lr.ph89
  %.388 = phi i32 [ %26, %.lr.ph89 ], [ 16, %.preheader76 ]
  tail call void @libxsmm_aarch64_instruction_sme_mov(ptr noundef %0, i32 noundef -1587494912, i32 noundef %.388, i32 noundef %1, i32 noundef 0, i32 noundef 8) #3
  tail call void @libxsmm_aarch64_instruction_alu_compute_imm64(ptr noundef %0, i32 noundef 4096, i32 noundef %1, i32 noundef 43, i32 noundef %1, i64 noundef %12) #3
  %26 = add nuw i32 %.388, 1
  %exitcond97.not = icmp eq i32 %26, %15
  br i1 %exitcond97.not, label %.loopexit, label %.lr.ph89, !llvm.loop !9

.loopexit:                                        ; preds = %.lr.ph89, %.lr.ph93, %.preheader76, %.preheader
  %27 = and i1 %7, %22
  br i1 %27, label %.preheader82, label %28, !llvm.loop !10

28:                                               ; preds = %.loopexit
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}
!9 = distinct !{!9, !6}
!10 = distinct !{!10, !6}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass