; LLVM IR from Overload-Technologies/Overload :: Dependencies/soloud/src/audiosource/ay/sndchip.ll (ZN7SNDCHIP10apply_regsEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.SNDCHIP = type <{ %class.SNDRENDER, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, [2 x i8], [6 x [32 x i32]], i32, %union.anon, i32, i32, i32, i32, %struct.SNDCHIP_VOLTAB, %struct.SNDCHIP_PANTAB, [4 x i8] }>
%class.SNDRENDER = type { ptr, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%union.anon = type { [16 x i8] }
%struct.SNDCHIP_VOLTAB = type { [32 x i32] }
%struct.SNDCHIP_PANTAB = type { [6 x i32] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164), i8 noundef zeroext) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164), i32 noundef, i8 noundef zeroext) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7SNDCHIP10apply_regsEj(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %7 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  store i8 0, ptr %5, align 1, !tbaa !11
  br label %8

8:                                                ; preds = %27, %2
  %9 = load i8, ptr %5, align 1, !tbaa !11
  %10 = zext i8 %9 to i32
  %11 = icmp slt i32 %10, 16
  br i1 %11, label %13, label %12

12:                                               ; preds = %8
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  br label %30

13:                                               ; preds = %8
  %14 = load i8, ptr %5, align 1, !tbaa !11
  call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %7, i8 noundef zeroext %14)
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  %15 = getelementptr inbounds %class.SNDCHIP, ptr %7, i32 0, i32 37
  %16 = load i8, ptr %5, align 1, !tbaa !11
  %17 = zext i8 %16 to i64
  %18 = getelementptr inbounds [16 x i8], ptr %15, i64 0, i64 %17
  %19 = load i8, ptr %18, align 1, !tbaa !11
  store i8 %19, ptr %6, align 1, !tbaa !11
  %20 = load i32, ptr %4, align 4, !tbaa !9
  %21 = load i8, ptr %6, align 1, !tbaa !11
  %22 = zext i8 %21 to i32
  %23 = xor i32 %22, 1
  %24 = trunc i32 %23 to i8
  call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %7, i32 noundef %20, i8 noundef zeroext %24)
  %25 = load i32, ptr %4, align 4, !tbaa !9
  %26 = load i8, ptr %6, align 1, !tbaa !11
  call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %7, i32 noundef %25, i8 noundef zeroext %26)
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #3
  br label %27

27:                                               ; preds = %13
  %28 = load i8, ptr %5, align 1, !tbaa !11
  %29 = add i8 %28, 1
  store i8 %29, ptr %5, align 1, !tbaa !11
  br label %8, !llvm.loop !12

30:                                               ; preds = %12
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164), i8 noundef zeroext) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164), i32 noundef, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7SNDCHIP10apply_regsEj(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 980
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 0)
  %4 = load i8, ptr %3, align 4, !tbaa !5
  %5 = xor i8 %4, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %5)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %4)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 1)
  %6 = getelementptr inbounds i8, ptr %0, i64 981
  %7 = load i8, ptr %6, align 1, !tbaa !5
  %8 = xor i8 %7, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %8)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %7)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 2)
  %9 = getelementptr inbounds i8, ptr %0, i64 982
  %10 = load i8, ptr %9, align 2, !tbaa !5
  %11 = xor i8 %10, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %11)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %10)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 3)
  %12 = getelementptr inbounds i8, ptr %0, i64 983
  %13 = load i8, ptr %12, align 1, !tbaa !5
  %14 = xor i8 %13, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %14)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %13)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 4)
  %15 = getelementptr inbounds i8, ptr %0, i64 984
  %16 = load i8, ptr %15, align 8, !tbaa !5
  %17 = xor i8 %16, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %17)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %16)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 5)
  %18 = getelementptr inbounds i8, ptr %0, i64 985
  %19 = load i8, ptr %18, align 1, !tbaa !5
  %20 = xor i8 %19, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %20)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %19)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 6)
  %21 = getelementptr inbounds i8, ptr %0, i64 986
  %22 = load i8, ptr %21, align 2, !tbaa !5
  %23 = xor i8 %22, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %23)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %22)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 7)
  %24 = getelementptr inbounds i8, ptr %0, i64 987
  %25 = load i8, ptr %24, align 1, !tbaa !5
  %26 = xor i8 %25, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %26)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %25)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 8)
  %27 = getelementptr inbounds i8, ptr %0, i64 988
  %28 = load i8, ptr %27, align 4, !tbaa !5
  %29 = xor i8 %28, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %29)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %28)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 9)
  %30 = getelementptr inbounds i8, ptr %0, i64 989
  %31 = load i8, ptr %30, align 1, !tbaa !5
  %32 = xor i8 %31, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %32)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %31)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 10)
  %33 = getelementptr inbounds i8, ptr %0, i64 990
  %34 = load i8, ptr %33, align 2, !tbaa !5
  %35 = xor i8 %34, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %35)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %34)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 11)
  %36 = getelementptr inbounds i8, ptr %0, i64 991
  %37 = load i8, ptr %36, align 1, !tbaa !5
  %38 = xor i8 %37, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %38)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %37)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 12)
  %39 = getelementptr inbounds i8, ptr %0, i64 992
  %40 = load i8, ptr %39, align 8, !tbaa !5
  %41 = xor i8 %40, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %41)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %40)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 13)
  %42 = getelementptr inbounds i8, ptr %0, i64 993
  %43 = load i8, ptr %42, align 1, !tbaa !5
  %44 = xor i8 %43, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %44)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %43)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 14)
  %45 = getelementptr inbounds i8, ptr %0, i64 994
  %46 = load i8, ptr %45, align 2, !tbaa !5
  %47 = xor i8 %46, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %47)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %46)
  tail call void @_ZN7SNDCHIP6selectEh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i8 noundef zeroext 15)
  %48 = getelementptr inbounds i8, ptr %0, i64 995
  %49 = load i8, ptr %48, align 1, !tbaa !5
  %50 = xor i8 %49, 1
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %50)
  tail call void @_ZN7SNDCHIP5writeEjh(ptr noundef nonnull align 8 dereferenceable(1164) %0, i32 noundef %1, i8 noundef zeroext %49)
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass