; LLVM IR from holzschu/ios_system :: libinfo/gen.subproj (rthdr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ip6_rthdr0 = type { i8, i8, i8, i8, i8, [3 x i8], [0 x %struct.in6_addr] }
%struct.in6_addr = type { %union.anon }
%union.anon = type { [4 x i32] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @inet6_rth_space(i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local ptr @inet6_rth_init(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %13, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %14 = load i32, ptr %8, align 4, !tbaa !9
  switch i32 %14, label %44 [
    i32 0, label %15
  ]

15:                                               ; preds = %4
  %16 = load i32, ptr %7, align 4, !tbaa !9
  %17 = load i32, ptr %9, align 4, !tbaa !9
  %18 = call i32 @inet6_rth_space(i32 noundef 0, i32 noundef %17)
  %19 = icmp ult i32 %16, %18
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  store ptr null, ptr %5, align 8
  store i32 1, ptr %12, align 4
  br label %47

21:                                               ; preds = %15
  %22 = load i32, ptr %9, align 4, !tbaa !9
  %23 = icmp slt i32 %22, 0
  br i1 %23, label %27, label %24

24:                                               ; preds = %21
  %25 = load i32, ptr %9, align 4, !tbaa !9
  %26 = icmp sgt i32 %25, 127
  br i1 %26, label %27, label %28

27:                                               ; preds = %24, %21
  store ptr null, ptr %5, align 8
  store i32 1, ptr %12, align 4
  br label %47

28:                                               ; preds = %24
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = zext i32 %30 to i64
  call void @llvm.memset.p0.i64(ptr align 1 %29, i8 0, i64 %31, i1 false)
  %32 = load ptr, ptr %10, align 8, !tbaa !5
  store ptr %32, ptr %11, align 8, !tbaa !5
  %33 = load i32, ptr %9, align 4, !tbaa !9
  %34 = mul nsw i32 %33, 2
  %35 = trunc i32 %34 to i8
  %36 = load ptr, ptr %11, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.ip6_rthdr0, ptr %36, i32 0, i32 1
  store i8 %35, ptr %37, align 1, !tbaa !11
  %38 = load ptr, ptr %11, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.ip6_rthdr0, ptr %38, i32 0, i32 2
  store i8 0, ptr %39, align 2, !tbaa !13
  %40 = load ptr, ptr %11, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.ip6_rthdr0, ptr %40, i32 0, i32 3
  store i8 0, ptr %41, align 1, !tbaa !14
  %42 = load ptr, ptr %11, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.ip6_rthdr0, ptr %42, i32 0, i32 4
  store i8 0, ptr %43, align 4, !tbaa !15
  br label %45

44:                                               ; preds = %4
  store ptr null, ptr %5, align 8
  store i32 1, ptr %12, align 4
  br label %47

45:                                               ; preds = %28
  %46 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %46, ptr %5, align 8
  store i32 1, ptr %12, align 4
  br label %47

47:                                               ; preds = %45, %44, %27, %20
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  %48 = load ptr, ptr %5, align 8
  ret ptr %48
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 1}
!12 = !{!"ip6_rthdr0", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !7, i64 4, !7, i64 5, !7, i64 8}
!13 = !{!12, !7, i64 2}
!14 = !{!12, !7, i64 3}
!15 = !{!12, !7, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @inet6_rth_space(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @inet6_rth_init(ptr noundef writeonly %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 {
  %cond = icmp eq i32 %2, 0
  br i1 %cond, label %5, label %15

5:                                                ; preds = %4
  %6 = tail call i32 @inet6_rth_space(i32 noundef 0, i32 noundef %3)
  %7 = icmp ugt i32 %6, %1
  %or.cond = icmp ugt i32 %3, 127
  %or.cond18 = or i1 %or.cond, %7
  br i1 %or.cond18, label %15, label %8

8:                                                ; preds = %5
  %9 = zext i32 %1 to i64
  tail call void @llvm.memset.p0.i64(ptr align 1 %0, i8 0, i64 %9, i1 false)
  %.tr = trunc nuw i32 %3 to i8
  %10 = shl nuw i8 %.tr, 1
  %11 = getelementptr inbounds i8, ptr %0, i64 1
  store i8 %10, ptr %11, align 1, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %0, i64 2
  store i8 0, ptr %12, align 2, !tbaa !9
  %13 = getelementptr inbounds i8, ptr %0, i64 3
  store i8 0, ptr %13, align 1, !tbaa !10
  %14 = getelementptr inbounds i8, ptr %0, i64 4
  store i8 0, ptr %14, align 4, !tbaa !11
  br label %15

15:                                               ; preds = %4, %5, %8
  %.0 = phi ptr [ %0, %8 ], [ null, %5 ], [ null, %4 ]
  ret ptr %.0
}

attributes #0 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 1}
!6 = !{!"ip6_rthdr0", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !7, i64 4, !7, i64 5, !7, i64 8}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!6, !7, i64 2}
!10 = !{!6, !7, i64 3}
!11 = !{!6, !7, i64 4}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass