; LLVM IR from Overload-Technologies/Overload :: Dependencies/assimp/code/AssetLib/FBX (FBXConverter)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.aiVector3t = type { float, float, float }

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN10aiVector3tIfEC2Efff(ptr noundef nonnull align 4 dereferenceable(12), float noundef, float noundef, float noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local { <2 x float>, float } @_ZN6Assimp3FBX12FBXConverter30TransformationCompDefaultValueENS1_18TransformationCompE(ptr noundef nonnull align 8 dereferenceable(489) %0, i32 noundef %1) #2 align 2 {
  %3 = alloca %class.aiVector3t, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca { <2 x float>, float }, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %7 = load ptr, ptr %4, align 8
  %8 = load i32, ptr %5, align 4, !tbaa !9
  %9 = icmp eq i32 %8, 12
  br i1 %9, label %10, label %11

10:                                               ; preds = %2
  call void @_ZN10aiVector3tIfEC2Efff(ptr noundef nonnull align 4 dereferenceable(12) %3, float noundef 1.000000e+00, float noundef 1.000000e+00, float noundef 1.000000e+00)
  br label %12

11:                                               ; preds = %2
  call void @_ZN10aiVector3tIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(12) %3) #3
  br label %12

12:                                               ; preds = %11, %10
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %6, ptr align 4 %3, i64 12, i1 false)
  %13 = load { <2 x float>, float }, ptr %6, align 8
  ret { <2 x float>, float } %13
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN10aiVector3tIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(12)) unnamed_addr #1 align 2

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN6Assimp3FBX12FBXConverter18TransformationCompE", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.aiVector3t = type { float, float, float }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN10aiVector3tIfEC2Efff(ptr noundef nonnull align 4 dereferenceable(12), float noundef, float noundef, float noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local { <2 x float>, float } @_ZN6Assimp3FBX12FBXConverter30TransformationCompDefaultValueENS1_18TransformationCompE(ptr nocapture noundef nonnull readnone align 8 dereferenceable(489) %0, i32 noundef %1) local_unnamed_addr #0 align 2 {
  %3 = alloca %class.aiVector3t, align 8
  %4 = icmp eq i32 %1, 12
  br i1 %4, label %5, label %6

5:                                                ; preds = %2
  call void @_ZN10aiVector3tIfEC2Efff(ptr noundef nonnull align 4 dereferenceable(12) %3, float noundef 1.000000e+00, float noundef 1.000000e+00, float noundef 1.000000e+00)
  br label %7

6:                                                ; preds = %2
  call void @_ZN10aiVector3tIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(12) %3) #1
  br label %7

7:                                                ; preds = %6, %5
  %.sroa.0.0.copyload = load <2 x float>, ptr %3, align 8
  %.sroa.2.0..sroa_idx = getelementptr inbounds i8, ptr %3, i64 8
  %.sroa.2.0.copyload = load float, ptr %.sroa.2.0..sroa_idx, align 8
  %.fca.0.insert = insertvalue { <2 x float>, float } poison, <2 x float> %.sroa.0.0.copyload, 0
  %.fca.1.insert = insertvalue { <2 x float>, float } %.fca.0.insert, float %.sroa.2.0.copyload, 1
  ret { <2 x float>, float } %.fca.1.insert
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN10aiVector3tIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(12)) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,PostOrderFunctionAttrsPass,SROAPass