; LLVM IR from Lakhankumawat/LearnCPP :: B-Backtracking (TheKnight’stourproblem)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z7displayRSt6vectorIS_IiSaIiEESaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = icmp slt i32 %11, 0
  br i1 %12, label %34, label %13

13:                                               ; preds = %5
  %14 = load i32, ptr %9, align 4, !tbaa !9
  %15 = icmp slt i32 %14, 0
  br i1 %15, label %34, label %16

16:                                               ; preds = %13
  %17 = load i32, ptr %8, align 4, !tbaa !9
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = icmp sge i32 %17, %18
  br i1 %19, label %34, label %20

20:                                               ; preds = %16
  %21 = load i32, ptr %9, align 4, !tbaa !9
  %22 = load i32, ptr %7, align 4, !tbaa !9
  %23 = icmp sge i32 %21, %22
  br i1 %23, label %34, label %24

24:                                               ; preds = %20
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = load i32, ptr %8, align 4, !tbaa !9
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %27) #2
  %29 = load i32, ptr %9, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30) #2
  %32 = load i32, ptr %31, align 4, !tbaa !9
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %35

34:                                               ; preds = %24, %20, %16, %13, %5
  br label %138

35:                                               ; preds = %24
  %36 = load i32, ptr %10, align 4, !tbaa !9
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = load i32, ptr %7, align 4, !tbaa !9
  %39 = mul nsw i32 %37, %38
  %40 = icmp eq i32 %36, %39
  br i1 %40, label %41, label %58

41:                                               ; preds = %35
  %42 = load i32, ptr %10, align 4, !tbaa !9
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = load i32, ptr %8, align 4, !tbaa !9
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %45) #2
  %47 = load i32, ptr %9, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #2
  store i32 %42, ptr %49, align 4, !tbaa !9
  %50 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_Z7displayRSt6vectorIS_IiSaIiEESaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %50)
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = load i32, ptr %8, align 4, !tbaa !9
  %53 = sext i32 %52 to i64
  %54 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef %53) #2
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %54, i64 noundef %56) #2
  store i32 0, ptr %57, align 4, !tbaa !9
  br label %138

58:                                               ; preds = %35
  %59 = load i32, ptr %10, align 4, !tbaa !9
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = load i32, ptr %8, align 4, !tbaa !9
  %62 = sext i32 %61 to i64
  %63 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %62) #2
  %64 = load i32, ptr %9, align 4, !tbaa !9
  %65 = sext i32 %64 to i64
  %66 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %65) #2
  store i32 %59, ptr %66, align 4, !tbaa !9
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = load i32, ptr %7, align 4, !tbaa !9
  %69 = load i32, ptr %8, align 4, !tbaa !9
  %70 = sub nsw i32 %69, 2
  %71 = load i32, ptr %9, align 4, !tbaa !9
  %72 = add nsw i32 %71, 1
  %73 = load i32, ptr %10, align 4, !tbaa !9
  %74 = add nsw i32 %73, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %67, i32 noundef %68, i32 noundef %70, i32 noundef %72, i32 noundef %74)
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = load i32, ptr %7, align 4, !tbaa !9
  %77 = load i32, ptr %8, align 4, !tbaa !9
  %78 = sub nsw i32 %77, 1
  %79 = load i32, ptr %9, align 4, !tbaa !9
  %80 = add nsw i32 %79, 2
  %81 = load i32, ptr %10, align 4, !tbaa !9
  %82 = add nsw i32 %81, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %75, i32 noundef %76, i32 noundef %78, i32 noundef %80, i32 noundef %82)
  %83 = load ptr, ptr %6, align 8, !tbaa !5
  %84 = load i32, ptr %7, align 4, !tbaa !9
  %85 = load i32, ptr %8, align 4, !tbaa !9
  %86 = add nsw i32 %85, 1
  %87 = load i32, ptr %9, align 4, !tbaa !9
  %88 = add nsw i32 %87, 2
  %89 = load i32, ptr %10, align 4, !tbaa !9
  %90 = add nsw i32 %89, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %83, i32 noundef %84, i32 noundef %86, i32 noundef %88, i32 noundef %90)
  %91 = load ptr, ptr %6, align 8, !tbaa !5
  %92 = load i32, ptr %7, align 4, !tbaa !9
  %93 = load i32, ptr %8, align 4, !tbaa !9
  %94 = add nsw i32 %93, 2
  %95 = load i32, ptr %9, align 4, !tbaa !9
  %96 = add nsw i32 %95, 1
  %97 = load i32, ptr %10, align 4, !tbaa !9
  %98 = add nsw i32 %97, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %91, i32 noundef %92, i32 noundef %94, i32 noundef %96, i32 noundef %98)
  %99 = load ptr, ptr %6, align 8, !tbaa !5
  %100 = load i32, ptr %7, align 4, !tbaa !9
  %101 = load i32, ptr %8, align 4, !tbaa !9
  %102 = add nsw i32 %101, 2
  %103 = load i32, ptr %9, align 4, !tbaa !9
  %104 = sub nsw i32 %103, 1
  %105 = load i32, ptr %10, align 4, !tbaa !9
  %106 = add nsw i32 %105, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %99, i32 noundef %100, i32 noundef %102, i32 noundef %104, i32 noundef %106)
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = load i32, ptr %7, align 4, !tbaa !9
  %109 = load i32, ptr %8, align 4, !tbaa !9
  %110 = add nsw i32 %109, 1
  %111 = load i32, ptr %9, align 4, !tbaa !9
  %112 = sub nsw i32 %111, 2
  %113 = load i32, ptr %10, align 4, !tbaa !9
  %114 = add nsw i32 %113, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %107, i32 noundef %108, i32 noundef %110, i32 noundef %112, i32 noundef %114)
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = load i32, ptr %7, align 4, !tbaa !9
  %117 = load i32, ptr %8, align 4, !tbaa !9
  %118 = sub nsw i32 %117, 1
  %119 = load i32, ptr %9, align 4, !tbaa !9
  %120 = sub nsw i32 %119, 2
  %121 = load i32, ptr %10, align 4, !tbaa !9
  %122 = add nsw i32 %121, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %115, i32 noundef %116, i32 noundef %118, i32 noundef %120, i32 noundef %122)
  %123 = load ptr, ptr %6, align 8, !tbaa !5
  %124 = load i32, ptr %7, align 4, !tbaa !9
  %125 = load i32, ptr %8, align 4, !tbaa !9
  %126 = sub nsw i32 %125, 2
  %127 = load i32, ptr %9, align 4, !tbaa !9
  %128 = sub nsw i32 %127, 1
  %129 = load i32, ptr %10, align 4, !tbaa !9
  %130 = add nsw i32 %129, 1
  call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %123, i32 noundef %124, i32 noundef %126, i32 noundef %128, i32 noundef %130)
  %131 = load ptr, ptr %6, align 8, !tbaa !5
  %132 = load i32, ptr %8, align 4, !tbaa !9
  %133 = sext i32 %132 to i64
  %134 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %131, i64 noundef %133) #2
  %135 = load i32, ptr %9, align 4, !tbaa !9
  %136 = sext i32 %135 to i64
  %137 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %134, i64 noundef %136) #2
  store i32 0, ptr %137, align 4, !tbaa !9
  br label %138

138:                                              ; preds = %58, %41, %34
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z7displayRSt6vectorIS_IiSaIiEESaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = or i32 %3, %2
  %or.cond.not = icmp sgt i32 %6, -1
  %.not = icmp slt i32 %2, %1
  %or.cond = and i1 %.not, %or.cond.not
  %.not70 = icmp slt i32 %3, %1
  %or.cond72 = and i1 %.not70, %or.cond
  br i1 %or.cond72, label %7, label %common.ret

7:                                                ; preds = %5
  %8 = zext nneg i32 %2 to i64
  %9 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #2
  %10 = zext nneg i32 %3 to i64
  %11 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %10) #2
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %.not71 = icmp eq i32 %12, 0
  br i1 %.not71, label %13, label %common.ret

13:                                               ; preds = %7
  %14 = mul nsw i32 %1, %1
  %15 = icmp eq i32 %14, %4
  %16 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #2
  %17 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %10) #2
  store i32 %4, ptr %17, align 4, !tbaa !5
  br i1 %15, label %18, label %21

18:                                               ; preds = %13
  tail call void @_Z7displayRSt6vectorIS_IiSaIiEESaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %0)
  br label %common.ret.sink.split

common.ret.sink.split:                            ; preds = %21, %18
  %19 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #2
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %10) #2
  store i32 0, ptr %20, align 4, !tbaa !5
  br label %common.ret

common.ret:                                       ; preds = %common.ret.sink.split, %7, %5
  ret void

21:                                               ; preds = %13
  %22 = add nsw i32 %2, -2
  %23 = add nuw nsw i32 %3, 1
  %24 = add nsw i32 %4, 1
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %22, i32 noundef %23, i32 noundef %24)
  %25 = add nsw i32 %2, -1
  %26 = add nuw nsw i32 %3, 2
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %25, i32 noundef %26, i32 noundef %24)
  %27 = add nuw nsw i32 %2, 1
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %27, i32 noundef %26, i32 noundef %24)
  %28 = add nuw nsw i32 %2, 2
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %28, i32 noundef %23, i32 noundef %24)
  %29 = add nsw i32 %3, -1
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %28, i32 noundef %29, i32 noundef %24)
  %30 = add nsw i32 %3, -2
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %27, i32 noundef %30, i32 noundef %24)
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %25, i32 noundef %30, i32 noundef %24)
  tail call void @_Z16printKnightsTourRSt6vectorIS_IiSaIiEESaIS1_EEiiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %22, i32 noundef %29, i32 noundef %24)
  br label %common.ret.sink.split
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass