; LLVM IR from control-flow-attestation/c-flat :: samples/soldering (Iron)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.IronStruct = type { %struct.HistoryStruct, i32, i8, i8, i32, i8, i8, i8, i32, [2 x i32], i8, i32, i32, i16, i16, i8, i16, i8, i8, i8, i16, i32, i32, i8, i32, i32, i32 }
%struct.HistoryStruct = type { i8, [8 x i32] }

declare void @digitalWrite(i8 noundef zeroext, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @getPower(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @applyPower(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  %4 = load ptr, ptr %2, align 8, !tbaa !5
  %5 = call zeroext i8 @getPower(ptr noundef %4)
  store i8 %5, ptr %3, align 1, !tbaa !9
  %6 = load ptr, ptr %2, align 8, !tbaa !5
  %7 = getelementptr inbounds %struct.IronStruct, ptr %6, i32 0, i32 9
  %8 = getelementptr inbounds [2 x i32], ptr %7, i64 0, i64 1
  %9 = load i32, ptr %8, align 4, !tbaa !10
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.IronStruct, ptr %10, i32 0, i32 8
  %12 = load i32, ptr %11, align 4, !tbaa !12
  %13 = add nsw i32 %12, 1
  %14 = icmp sgt i32 %9, %13
  br i1 %14, label %15, label %16

15:                                               ; preds = %1
  store i8 0, ptr %3, align 1, !tbaa !9
  br label %16

16:                                               ; preds = %15, %1
  %17 = load i8, ptr %3, align 1, !tbaa !9
  %18 = zext i8 %17 to i32
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %24

20:                                               ; preds = %16
  %21 = load ptr, ptr %2, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.IronStruct, ptr %21, i32 0, i32 2
  %23 = load i8, ptr %22, align 4, !tbaa !17
  call void @digitalWrite(i8 noundef zeroext %23, i8 noundef zeroext 0)
  br label %24

24:                                               ; preds = %20, %16
  %25 = load ptr, ptr %2, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.IronStruct, ptr %25, i32 0, i32 5
  %27 = load i8, ptr %26, align 4, !tbaa !18, !range !19, !noundef !20
  %28 = trunc i8 %27 to i1
  br i1 %28, label %29, label %37

29:                                               ; preds = %24
  %30 = load ptr, ptr %2, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.IronStruct, ptr %30, i32 0, i32 2
  %32 = load i8, ptr %31, align 4, !tbaa !17
  %33 = load i8, ptr %3, align 1, !tbaa !9
  %34 = zext i8 %33 to i32
  %35 = and i32 %34, 255
  %36 = trunc i32 %35 to i8
  call void @analogWrite(i8 noundef zeroext %32, i8 noundef zeroext %36)
  br label %37

37:                                               ; preds = %29, %24
  %38 = load ptr, ptr %2, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.IronStruct, ptr %38, i32 0, i32 0
  %40 = load i8, ptr %3, align 1, !tbaa !9
  %41 = zext i8 %40 to i32
  call void @put(ptr noundef %39, i32 noundef %41)
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  ret void
}

declare void @analogWrite(i8 noundef zeroext, i8 noundef zeroext) #0

declare void @put(ptr noundef, i32 noundef) #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 52}
!13 = !{!"IronStruct", !14, i64 0, !11, i64 36, !7, i64 40, !7, i64 41, !11, i64 44, !15, i64 48, !15, i64 49, !15, i64 50, !11, i64 52, !7, i64 56, !15, i64 64, !11, i64 68, !11, i64 72, !16, i64 76, !16, i64 78, !15, i64 80, !16, i64 82, !7, i64 84, !7, i64 85, !7, i64 86, !16, i64 88, !11, i64 92, !11, i64 96, !7, i64 100, !11, i64 104, !11, i64 108, !11, i64 112}
!14 = !{!"HistoryStruct", !7, i64 0, !7, i64 4}
!15 = !{!"_Bool", !7, i64 0}
!16 = !{!"short", !7, i64 0}
!17 = !{!13, !7, i64 40}
!18 = !{!13, !15, i64 48}
!19 = !{i8 0, i8 2}
!20 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @digitalWrite(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @getPower(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @applyPower(ptr noundef %0) local_unnamed_addr #1 {
  %2 = tail call zeroext i8 @getPower(ptr noundef %0)
  %3 = getelementptr inbounds i8, ptr %0, i64 60
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 52
  %6 = load i32, ptr %5, align 4, !tbaa !9
  %7 = add nsw i32 %6, 1
  %8 = icmp sgt i32 %4, %7
  %spec.select = select i1 %8, i8 0, i8 %2
  %9 = icmp eq i8 %spec.select, 0
  br i1 %9, label %10, label %13

10:                                               ; preds = %1
  %11 = getelementptr inbounds i8, ptr %0, i64 40
  %12 = load i8, ptr %11, align 4, !tbaa !14
  tail call void @digitalWrite(i8 noundef zeroext %12, i8 noundef zeroext 0) #2
  br label %13

13:                                               ; preds = %10, %1
  %14 = getelementptr inbounds i8, ptr %0, i64 48
  %15 = load i8, ptr %14, align 4, !tbaa !15, !range !16, !noundef !17
  %16 = trunc nuw i8 %15 to i1
  br i1 %16, label %17, label %20

17:                                               ; preds = %13
  %18 = getelementptr inbounds i8, ptr %0, i64 40
  %19 = load i8, ptr %18, align 4, !tbaa !14
  tail call void @analogWrite(i8 noundef zeroext %19, i8 noundef zeroext %spec.select) #2
  br label %20

20:                                               ; preds = %17, %13
  %21 = zext i8 %spec.select to i32
  tail call void @put(ptr noundef nonnull %0, i32 noundef %21) #2
  ret void
}

declare void @analogWrite(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

declare void @put(ptr noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 52}
!10 = !{!"IronStruct", !11, i64 0, !6, i64 36, !7, i64 40, !7, i64 41, !6, i64 44, !12, i64 48, !12, i64 49, !12, i64 50, !6, i64 52, !7, i64 56, !12, i64 64, !6, i64 68, !6, i64 72, !13, i64 76, !13, i64 78, !12, i64 80, !13, i64 82, !7, i64 84, !7, i64 85, !7, i64 86, !13, i64 88, !6, i64 92, !6, i64 96, !7, i64 100, !6, i64 104, !6, i64 108, !6, i64 112}
!11 = !{!"HistoryStruct", !7, i64 0, !7, i64 4}
!12 = !{!"_Bool", !7, i64 0}
!13 = !{!"short", !7, i64 0}
!14 = !{!10, !7, i64 40}
!15 = !{!10, !12, i64 48}
!16 = !{i8 0, i8 2}
!17 = !{}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass