; LLVM IR from kazunetakahashi/atcoder :: 2019/0707_ABC133/F.ll (ZN3LCA4initEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.LCA = type { i32, i32, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<LCA::Edge>, std::allocator<std::vector<LCA::Edge>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<LCA::Edge>, std::allocator<std::vector<LCA::Edge>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<LCA::Edge>, std::allocator<std::vector<LCA::Edge>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<LCA::Edge>, std::allocator<std::vector<LCA::Edge>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<LCA::Vertex, std::allocator<LCA::Vertex>>::_Vector_impl" }
%"struct.std::_Vector_base<LCA::Vertex, std::allocator<LCA::Vertex>>::_Vector_impl" = type { %"struct.std::_Vector_base<LCA::Vertex, std::allocator<LCA::Vertex>>::_Vector_impl_data" }
%"struct.std::_Vector_base<LCA::Vertex, std::allocator<LCA::Vertex>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3LCA4initEv(ptr noundef nonnull align 8 dereferenceable(88) %0) #1 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %6 = load ptr, ptr %2, align 8
  %7 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 1
  %8 = load i32, ptr %7, align 4, !tbaa !9
  call void @_ZN3LCA3dfsEiixi(ptr noundef nonnull align 8 dereferenceable(88) %6, i32 noundef %8, i32 noundef 0, i64 noundef 0, i32 noundef -1)
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !24
  br label %9

9:                                                ; preds = %62, %1
  %10 = load i32, ptr %3, align 4, !tbaa !24
  %11 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 2
  %12 = load i32, ptr %11, align 8, !tbaa !25
  %13 = sub nsw i32 %12, 1
  %14 = icmp slt i32 %10, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %9
  store i32 2, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %65

16:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !24
  br label %17

17:                                               ; preds = %58, %16
  %18 = load i32, ptr %5, align 4, !tbaa !24
  %19 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 0
  %20 = load i32, ptr %19, align 8, !tbaa !26
  %21 = icmp slt i32 %18, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %17
  store i32 5, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %61

23:                                               ; preds = %17
  %24 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 5
  %25 = load i32, ptr %5, align 4, !tbaa !24
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %26) #3
  %28 = load i32, ptr %3, align 4, !tbaa !24
  %29 = sext i32 %28 to i64
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %27, i64 noundef %29) #3
  %31 = load i32, ptr %30, align 4, !tbaa !24
  %32 = icmp ne i32 %31, -1
  br i1 %32, label %33, label %57

33:                                               ; preds = %23
  %34 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 5
  %35 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 5
  %36 = load i32, ptr %5, align 4, !tbaa !24
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %37) #3
  %39 = load i32, ptr %3, align 4, !tbaa !24
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %40) #3
  %42 = load i32, ptr %41, align 4, !tbaa !24
  %43 = sext i32 %42 to i64
  %44 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %43) #3
  %45 = load i32, ptr %3, align 4, !tbaa !24
  %46 = sext i32 %45 to i64
  %47 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %44, i64 noundef %46) #3
  %48 = load i32, ptr %47, align 4, !tbaa !24
  %49 = getelementptr inbounds %class.LCA, ptr %6, i32 0, i32 5
  %50 = load i32, ptr %5, align 4, !tbaa !24
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %51) #3
  %53 = load i32, ptr %3, align 4, !tbaa !24
  %54 = add nsw i32 %53, 1
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %55) #3
  store i32 %48, ptr %56, align 4, !tbaa !24
  br label %57

57:                                               ; preds = %33, %23
  br label %58

58:                                               ; preds = %57
  %59 = load i32, ptr %5, align 4, !tbaa !24
  %60 = add nsw i32 %59, 1
  store i32 %60, ptr %5, align 4, !tbaa !24
  br label %17, !llvm.loop !27

61:                                               ; preds = %22
  br label %62

62:                                               ; preds = %61
  %63 = load i32, ptr %3, align 4, !tbaa !24
  %64 = add nsw i32 %63, 1
  store i32 %64, ptr %3, align 4, !tbaa !24
  br label %9, !llvm.loop !29

65:                                               ; preds = %15
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3LCA3dfsEiixi(ptr noundef nonnull align 8 dereferenceable(88), i32 noundef, i32 noundef, i64 noundef, i32 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 4}
!10 = !{!"_ZTS3LCA", !11, i64 0, !11, i64 4, !11, i64 8, !12, i64 16, !16, i64 40, !20, i64 64}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIS_IN3LCA4EdgeESaIS1_EESaIS3_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!"_ZTSSt6vectorIN3LCA6VertexESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIN3LCA6VertexESaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN3LCA6VertexESaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIN3LCA6VertexESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!11, !11, i64 0}
!25 = !{!10, !11, i64 8}
!26 = !{!10, !11, i64 0}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = distinct !{!29, !28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3LCA4initEv(ptr noundef nonnull align 8 dereferenceable(88) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 4
  %3 = load i32, ptr %2, align 4, !tbaa !5
  tail call void @_ZN3LCA3dfsEiixi(ptr noundef nonnull align 8 dereferenceable(88) %0, i32 noundef %3, i32 noundef 0, i64 noundef 0, i32 noundef -1)
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = load i32, ptr %4, align 8, !tbaa !23
  %6 = icmp sgt i32 %5, 1
  br i1 %6, label %.preheader.lr.ph, label %._crit_edge14

.preheader.lr.ph:                                 ; preds = %1
  %7 = getelementptr inbounds i8, ptr %0, i64 64
  %8 = load i32, ptr %0, align 8, !tbaa !24
  %9 = icmp sgt i32 %8, 0
  br i1 %9, label %.preheader, label %._crit_edge14

.preheader:                                       ; preds = %.preheader.lr.ph, %._crit_edge
  %10 = phi i32 [ %14, %._crit_edge ], [ %5, %.preheader.lr.ph ]
  %11 = phi i32 [ %15, %._crit_edge ], [ %8, %.preheader.lr.ph ]
  %indvars.iv17 = phi i64 [ %13, %._crit_edge ], [ 0, %.preheader.lr.ph ]
  %12 = icmp sgt i32 %11, 0
  %13 = add nuw nsw i64 %indvars.iv17, 1
  br i1 %12, label %.lr.ph, label %._crit_edge

._crit_edge14:                                    ; preds = %._crit_edge, %.preheader.lr.ph, %1
  ret void

._crit_edge.loopexit:                             ; preds = %32
  %.pre = load i32, ptr %4, align 8, !tbaa !23
  br label %._crit_edge

._crit_edge:                                      ; preds = %.preheader, %._crit_edge.loopexit
  %14 = phi i32 [ %.pre, %._crit_edge.loopexit ], [ %10, %.preheader ]
  %15 = phi i32 [ %33, %._crit_edge.loopexit ], [ %11, %.preheader ]
  %16 = add nsw i32 %14, -1
  %17 = sext i32 %16 to i64
  %18 = icmp slt i64 %13, %17
  br i1 %18, label %.preheader, label %._crit_edge14, !llvm.loop !25

.lr.ph:                                           ; preds = %.preheader, %32
  %indvars.iv = phi i64 [ %indvars.iv.next, %32 ], [ 0, %.preheader ]
  %19 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %indvars.iv) #2
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %indvars.iv17) #2
  %21 = load i32, ptr %20, align 4, !tbaa !28
  %.not = icmp eq i32 %21, -1
  br i1 %.not, label %32, label %22

22:                                               ; preds = %.lr.ph
  %23 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %indvars.iv) #2
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %indvars.iv17) #2
  %25 = load i32, ptr %24, align 4, !tbaa !28
  %26 = sext i32 %25 to i64
  %27 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %26) #2
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %27, i64 noundef %indvars.iv17) #2
  %29 = load i32, ptr %28, align 4, !tbaa !28
  %30 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %indvars.iv) #2
  %31 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %30, i64 noundef %13) #2
  store i32 %29, ptr %31, align 4, !tbaa !28
  br label %32

32:                                               ; preds = %.lr.ph, %22
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %33 = load i32, ptr %0, align 8, !tbaa !24
  %34 = sext i32 %33 to i64
  %35 = icmp slt i64 %indvars.iv.next, %34
  br i1 %35, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !29
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3LCA3dfsEiixi(ptr noundef nonnull align 8 dereferenceable(88), i32 noundef, i32 noundef, i64 noundef, i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTS3LCA", !7, i64 0, !7, i64 4, !7, i64 8, !10, i64 16, !15, i64 40, !19, i64 64}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIS_IN3LCA4EdgeESaIS1_EESaIS3_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN3LCA4EdgeESaIS2_EESaIS4_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"_ZTSSt6vectorIN3LCA6VertexESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN3LCA6VertexESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN3LCA6VertexESaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN3LCA6VertexESaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!23 = !{!6, !7, i64 8}
!24 = !{!6, !7, i64 0}
!25 = distinct !{!25, !26, !27}
!26 = !{!"llvm.loop.mustprogress"}
!27 = !{!"llvm.loop.unswitch.partial.disable"}
!28 = !{!7, !7, i64 0}
!29 = distinct !{!29, !26}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass