; LLVM IR from xirc/cp-algorithm :: atcoder/abc038/D/main.ll (Z6updateiiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@segtree = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updateiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #3 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  store i32 %4, ptr %10, align 4, !tbaa !5
  %12 = load i32, ptr %10, align 4, !tbaa !5
  %13 = load i32, ptr %9, align 4, !tbaa !5
  %14 = sub nsw i32 %12, %13
  %15 = icmp sle i32 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %5
  br label %71

17:                                               ; preds = %5
  %18 = load i32, ptr %10, align 4, !tbaa !5
  %19 = load i32, ptr %9, align 4, !tbaa !5
  %20 = sub nsw i32 %18, %19
  %21 = icmp eq i32 %20, 1
  br i1 %21, label %22, label %31

22:                                               ; preds = %17
  %23 = load i32, ptr %8, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %24) #4
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %25, ptr noundef nonnull align 4 dereferenceable(4) %7)
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = load i32, ptr %8, align 4, !tbaa !5
  %29 = sext i32 %28 to i64
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %29) #4
  store i32 %27, ptr %30, align 4, !tbaa !5
  br label %71

31:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %32 = load i32, ptr %9, align 4, !tbaa !5
  %33 = load i32, ptr %10, align 4, !tbaa !5
  %34 = add nsw i32 %32, %33
  %35 = sdiv i32 %34, 2
  store i32 %35, ptr %11, align 4, !tbaa !5
  %36 = load i32, ptr %6, align 4, !tbaa !5
  %37 = load i32, ptr %11, align 4, !tbaa !5
  %38 = icmp slt i32 %36, %37
  br i1 %38, label %39, label %47

39:                                               ; preds = %31
  %40 = load i32, ptr %6, align 4, !tbaa !5
  %41 = load i32, ptr %7, align 4, !tbaa !5
  %42 = load i32, ptr %8, align 4, !tbaa !5
  %43 = mul nsw i32 %42, 2
  %44 = add nsw i32 %43, 1
  %45 = load i32, ptr %9, align 4, !tbaa !5
  %46 = load i32, ptr %11, align 4, !tbaa !5
  call void @_Z6updateiiiii(i32 noundef %40, i32 noundef %41, i32 noundef %44, i32 noundef %45, i32 noundef %46)
  br label %55

47:                                               ; preds = %31
  %48 = load i32, ptr %6, align 4, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !5
  %50 = load i32, ptr %8, align 4, !tbaa !5
  %51 = mul nsw i32 %50, 2
  %52 = add nsw i32 %51, 2
  %53 = load i32, ptr %11, align 4, !tbaa !5
  %54 = load i32, ptr %10, align 4, !tbaa !5
  call void @_Z6updateiiiii(i32 noundef %48, i32 noundef %49, i32 noundef %52, i32 noundef %53, i32 noundef %54)
  br label %55

55:                                               ; preds = %47, %39
  %56 = load i32, ptr %8, align 4, !tbaa !5
  %57 = mul nsw i32 %56, 2
  %58 = add nsw i32 %57, 1
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %59) #4
  %61 = load i32, ptr %8, align 4, !tbaa !5
  %62 = mul nsw i32 %61, 2
  %63 = add nsw i32 %62, 2
  %64 = sext i32 %63 to i64
  %65 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %64) #4
  %66 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %60, ptr noundef nonnull align 4 dereferenceable(4) %65)
  %67 = load i32, ptr %66, align 4, !tbaa !5
  %68 = load i32, ptr %8, align 4, !tbaa !5
  %69 = sext i32 %68 to i64
  %70 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %69) #4
  store i32 %67, ptr %70, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  br label %71

71:                                               ; preds = %55, %22, %16
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@segtree = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updateiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = alloca i32, align 4
  store i32 %1, ptr %6, align 4, !tbaa !5
  %7 = sub nsw i32 %4, %3
  %8 = icmp slt i32 %7, 1
  br i1 %8, label %35, label %9

9:                                                ; preds = %5
  %10 = icmp eq i32 %7, 1
  br i1 %10, label %11, label %17

11:                                               ; preds = %9
  %12 = sext i32 %2 to i64
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %12) #2
  %14 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %13, ptr noundef nonnull align 4 dereferenceable(4) %6)
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %12) #2
  store i32 %15, ptr %16, align 4, !tbaa !5
  br label %35

17:                                               ; preds = %9
  %18 = add nsw i32 %4, %3
  %19 = sdiv i32 %18, 2
  %20 = icmp sgt i32 %19, %0
  %21 = shl nsw i32 %2, 1
  br i1 %20, label %22, label %24

22:                                               ; preds = %17
  %23 = or disjoint i32 %21, 1
  tail call void @_Z6updateiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %23, i32 noundef %3, i32 noundef %19)
  %.pre25 = add nsw i32 %21, 2
  br label %26

24:                                               ; preds = %17
  %25 = add nsw i32 %21, 2
  tail call void @_Z6updateiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %25, i32 noundef %19, i32 noundef %4)
  %.pre = or disjoint i32 %21, 1
  br label %26

26:                                               ; preds = %24, %22
  %.pre-phi26 = phi i32 [ %25, %24 ], [ %.pre25, %22 ]
  %.pre-phi24 = phi i32 [ %.pre, %24 ], [ %23, %22 ]
  %27 = sext i32 %.pre-phi24 to i64
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %27) #2
  %29 = sext i32 %.pre-phi26 to i64
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %29) #2
  %31 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %28, ptr noundef nonnull align 4 dereferenceable(4) %30)
  %32 = load i32, ptr %31, align 4, !tbaa !5
  %33 = sext i32 %2 to i64
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @segtree, i64 noundef %33) #2
  store i32 %32, ptr %34, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %5, %26, %11
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass