; LLVM IR from Stephane-D/SGDK :: src (maths)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @getLog2(i64 noundef %0) #1 {
  %2 = alloca i64, align 8
  %3 = alloca i16, align 2
  %4 = alloca i16, align 2
  store i64 %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 2, ptr %4) #2
  store i16 0, ptr %4, align 2, !tbaa !9
  %5 = load i64, ptr %2, align 8, !tbaa !5
  %6 = icmp ugt i64 %5, 65535
  br i1 %6, label %7, label %8

7:                                                ; preds = %1
  store i16 16, ptr %4, align 2, !tbaa !9
  br label %8

8:                                                ; preds = %7, %1
  %9 = load i64, ptr %2, align 8, !tbaa !5
  %10 = trunc i64 %9 to i16
  store i16 %10, ptr %3, align 2, !tbaa !9
  %11 = load i16, ptr %3, align 2, !tbaa !9
  %12 = zext i16 %11 to i32
  %13 = icmp sge i32 %12, 256
  br i1 %13, label %14, label %23

14:                                               ; preds = %8
  %15 = load i16, ptr %4, align 2, !tbaa !9
  %16 = zext i16 %15 to i32
  %17 = add nsw i32 %16, 8
  %18 = trunc i32 %17 to i16
  store i16 %18, ptr %4, align 2, !tbaa !9
  %19 = load i16, ptr %3, align 2, !tbaa !9
  %20 = zext i16 %19 to i32
  %21 = ashr i32 %20, 8
  %22 = trunc i32 %21 to i16
  store i16 %22, ptr %3, align 2, !tbaa !9
  br label %23

23:                                               ; preds = %14, %8
  %24 = load i16, ptr %3, align 2, !tbaa !9
  %25 = zext i16 %24 to i32
  %26 = icmp sge i32 %25, 16
  br i1 %26, label %27, label %36

27:                                               ; preds = %23
  %28 = load i16, ptr %4, align 2, !tbaa !9
  %29 = zext i16 %28 to i32
  %30 = add nsw i32 %29, 4
  %31 = trunc i32 %30 to i16
  store i16 %31, ptr %4, align 2, !tbaa !9
  %32 = load i16, ptr %3, align 2, !tbaa !9
  %33 = zext i16 %32 to i32
  %34 = ashr i32 %33, 4
  %35 = trunc i32 %34 to i16
  store i16 %35, ptr %3, align 2, !tbaa !9
  br label %36

36:                                               ; preds = %27, %23
  %37 = load i16, ptr %3, align 2, !tbaa !9
  %38 = zext i16 %37 to i32
  %39 = icmp sge i32 %38, 4
  br i1 %39, label %40, label %49

40:                                               ; preds = %36
  %41 = load i16, ptr %4, align 2, !tbaa !9
  %42 = zext i16 %41 to i32
  %43 = add nsw i32 %42, 2
  %44 = trunc i32 %43 to i16
  store i16 %44, ptr %4, align 2, !tbaa !9
  %45 = load i16, ptr %3, align 2, !tbaa !9
  %46 = zext i16 %45 to i32
  %47 = ashr i32 %46, 2
  %48 = trunc i32 %47 to i16
  store i16 %48, ptr %3, align 2, !tbaa !9
  br label %49

49:                                               ; preds = %40, %36
  %50 = load i16, ptr %4, align 2, !tbaa !9
  %51 = zext i16 %50 to i32
  %52 = load i16, ptr %3, align 2, !tbaa !9
  %53 = zext i16 %52 to i32
  %54 = ashr i32 %53, 1
  %55 = or i32 %51, %54
  %56 = trunc i32 %55 to i16
  call void @llvm.lifetime.end.p0(i64 2, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr %3) #2
  ret i16 %56
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local zeroext i16 @getLog2(i64 noundef %0) local_unnamed_addr #0 {
  %2 = icmp ugt i64 %0, 65535
  %spec.store.select = select i1 %2, i16 16, i16 0
  %3 = trunc i64 %0 to i16
  %4 = trunc i64 %0 to i32
  %5 = and i32 %4, 65535
  %6 = icmp ugt i32 %5, 255
  %7 = or disjoint i16 %spec.store.select, 8
  %8 = lshr i32 %5, 8
  %9 = trunc nuw nsw i32 %8 to i16
  %.013 = select i1 %6, i16 %9, i16 %3
  %.0 = select i1 %6, i16 %7, i16 %spec.store.select
  %10 = icmp ugt i16 %.013, 15
  %11 = or disjoint i16 %.0, 4
  %12 = lshr i16 %.013, 4
  %.114 = select i1 %10, i16 %12, i16 %.013
  %.1 = select i1 %10, i16 %11, i16 %.0
  %13 = icmp ugt i16 %.114, 3
  %14 = or disjoint i16 %.1, 2
  %15 = lshr i16 %.114, 2
  %.215 = select i1 %13, i16 %15, i16 %.114
  %.2 = select i1 %13, i16 %14, i16 %.1
  %16 = lshr i16 %.215, 1
  %17 = or i16 %16, %.2
  ret i16 %17
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass