; LLVM IR from HarshCasper/NeoAlgo :: C-Plus-Plus/cp/delete_peak_elements_in_maxHeap.ll (Z16downward_heapifyRSt6vectorIiSaIiEEi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z16downward_heapifyRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  %10 = trunc i64 %9 to i32
  store i32 %10, ptr %5, align 4, !tbaa !9
  %11 = load i32, ptr %4, align 4, !tbaa !9
  %12 = sext i32 %11 to i64
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #4
  %15 = udiv i64 %14, 2
  %16 = icmp uge i64 %12, %15
  br i1 %16, label %17, label %18

17:                                               ; preds = %2
  store i32 1, ptr %6, align 4
  br label %111

18:                                               ; preds = %2
  %19 = load i32, ptr %4, align 4, !tbaa !9
  %20 = mul nsw i32 %19, 2
  %21 = add nsw i32 %20, 1
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = icmp sge i32 %21, %22
  br i1 %23, label %24, label %25

24:                                               ; preds = %18
  store i32 1, ptr %6, align 4
  br label %111

25:                                               ; preds = %18
  %26 = load i32, ptr %4, align 4, !tbaa !9
  %27 = mul nsw i32 %26, 2
  %28 = add nsw i32 %27, 2
  %29 = load i32, ptr %5, align 4, !tbaa !9
  %30 = icmp sge i32 %28, %29
  br i1 %30, label %31, label %61

31:                                               ; preds = %25
  %32 = load ptr, ptr %3, align 8, !tbaa !5
  %33 = load i32, ptr %4, align 4, !tbaa !9
  %34 = mul nsw i32 %33, 2
  %35 = add nsw i32 %34, 1
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %36) #4
  %38 = load i32, ptr %37, align 4, !tbaa !9
  %39 = load ptr, ptr %3, align 8, !tbaa !5
  %40 = load i32, ptr %4, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %41) #4
  %43 = load i32, ptr %42, align 4, !tbaa !9
  %44 = icmp sgt i32 %38, %43
  br i1 %44, label %45, label %60

45:                                               ; preds = %31
  %46 = load ptr, ptr %3, align 8, !tbaa !5
  %47 = load i32, ptr %4, align 4, !tbaa !9
  %48 = mul nsw i32 %47, 2
  %49 = add nsw i32 %48, 1
  %50 = sext i32 %49 to i64
  %51 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %50) #4
  %52 = load ptr, ptr %3, align 8, !tbaa !5
  %53 = load i32, ptr %4, align 4, !tbaa !9
  %54 = sext i32 %53 to i64
  %55 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %54) #4
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %51, ptr noundef nonnull align 4 dereferenceable(4) %55) #4
  %56 = load ptr, ptr %3, align 8, !tbaa !5
  %57 = load i32, ptr %4, align 4, !tbaa !9
  %58 = mul nsw i32 %57, 2
  %59 = add nsw i32 %58, 1
  call void @_Z16downward_heapifyRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %56, i32 noundef %59)
  br label %60

60:                                               ; preds = %45, %31
  br label %110

61:                                               ; preds = %25
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %62 = load ptr, ptr %3, align 8, !tbaa !5
  %63 = load i32, ptr %4, align 4, !tbaa !9
  %64 = mul nsw i32 %63, 2
  %65 = add nsw i32 %64, 1
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %66) #4
  %68 = load i32, ptr %67, align 4, !tbaa !9
  %69 = load ptr, ptr %3, align 8, !tbaa !5
  %70 = load i32, ptr %4, align 4, !tbaa !9
  %71 = mul nsw i32 %70, 2
  %72 = add nsw i32 %71, 2
  %73 = sext i32 %72 to i64
  %74 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %69, i64 noundef %73) #4
  %75 = load i32, ptr %74, align 4, !tbaa !9
  %76 = icmp sgt i32 %68, %75
  br i1 %76, label %77, label %81

77:                                               ; preds = %61
  %78 = load i32, ptr %4, align 4, !tbaa !9
  %79 = mul nsw i32 %78, 2
  %80 = add nsw i32 %79, 1
  br label %85

81:                                               ; preds = %61
  %82 = load i32, ptr %4, align 4, !tbaa !9
  %83 = mul nsw i32 %82, 2
  %84 = add nsw i32 %83, 2
  br label %85

85:                                               ; preds = %81, %77
  %86 = phi i32 [ %80, %77 ], [ %84, %81 ]
  store i32 %86, ptr %7, align 4, !tbaa !9
  %87 = load ptr, ptr %3, align 8, !tbaa !5
  %88 = load i32, ptr %4, align 4, !tbaa !9
  %89 = sext i32 %88 to i64
  %90 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %87, i64 noundef %89) #4
  %91 = load i32, ptr %90, align 4, !tbaa !9
  %92 = load ptr, ptr %3, align 8, !tbaa !5
  %93 = load i32, ptr %7, align 4, !tbaa !9
  %94 = sext i32 %93 to i64
  %95 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %92, i64 noundef %94) #4
  %96 = load i32, ptr %95, align 4, !tbaa !9
  %97 = icmp slt i32 %91, %96
  br i1 %97, label %98, label %109

98:                                               ; preds = %85
  %99 = load ptr, ptr %3, align 8, !tbaa !5
  %100 = load i32, ptr %4, align 4, !tbaa !9
  %101 = sext i32 %100 to i64
  %102 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %99, i64 noundef %101) #4
  %103 = load ptr, ptr %3, align 8, !tbaa !5
  %104 = load i32, ptr %7, align 4, !tbaa !9
  %105 = sext i32 %104 to i64
  %106 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %103, i64 noundef %105) #4
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %102, ptr noundef nonnull align 4 dereferenceable(4) %106) #4
  %107 = load ptr, ptr %3, align 8, !tbaa !5
  %108 = load i32, ptr %7, align 4, !tbaa !9
  call void @_Z16downward_heapifyRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %107, i32 noundef %108)
  br label %109

109:                                              ; preds = %98, %85
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %110

110:                                              ; preds = %109, %60
  store i32 0, ptr %6, align 4
  br label %111

111:                                              ; preds = %110, %24, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  %112 = load i32, ptr %6, align 4
  switch i32 %112, label %114 [
    i32 0, label %113
    i32 1, label %113
  ]

113:                                              ; preds = %111, %111
  ret void

114:                                              ; preds = %111
  unreachable
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z16downward_heapifyRSt6vectorIiSaIiEEi(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %4 = sext i32 %1 to i64
  %5 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %6 = lshr i64 %5, 1
  %.not38 = icmp ugt i64 %6, %4
  br i1 %.not38, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %2, %tailrecurse.backedge
  %7 = phi i64 [ %.pre-phi, %tailrecurse.backedge ], [ %4, %2 ]
  %.in = phi i64 [ %22, %tailrecurse.backedge ], [ %3, %2 ]
  %.tr3739 = phi i32 [ %.tr37.be, %tailrecurse.backedge ], [ %1, %2 ]
  %8 = trunc i64 %.in to i32
  %9 = shl nsw i32 %.tr3739, 1
  %10 = or disjoint i32 %9, 1
  %.not35 = icmp slt i32 %10, %8
  br i1 %.not35, label %11, label %._crit_edge

11:                                               ; preds = %.lr.ph
  %12 = add nsw i32 %9, 2
  %.not36 = icmp slt i32 %12, %8
  %13 = sext i32 %10 to i64
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %13) #2
  %15 = load i32, ptr %14, align 4, !tbaa !5
  br i1 %.not36, label %25, label %16

16:                                               ; preds = %11
  %17 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %7) #2
  %18 = load i32, ptr %17, align 4, !tbaa !5
  %19 = icmp sgt i32 %15, %18
  br i1 %19, label %tailrecurse.backedge, label %._crit_edge

tailrecurse.backedge:                             ; preds = %16, %25
  %.sink44 = phi i64 [ %7, %25 ], [ %13, %16 ]
  %.sink43 = phi i64 [ %32, %25 ], [ %7, %16 ]
  %.pre-phi = phi i64 [ %32, %25 ], [ %13, %16 ]
  %.tr37.be = phi i32 [ %., %25 ], [ %10, %16 ]
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.sink44) #2
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.sink43) #2
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %20, ptr noundef nonnull align 4 dereferenceable(4) %21) #2
  %22 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %23 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %24 = lshr i64 %23, 1
  %.not = icmp ugt i64 %24, %.pre-phi
  br i1 %.not, label %.lr.ph, label %._crit_edge

25:                                               ; preds = %11
  %26 = sext i32 %12 to i64
  %27 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %26) #2
  %28 = load i32, ptr %27, align 4, !tbaa !5
  %29 = icmp sgt i32 %15, %28
  %. = select i1 %29, i32 %10, i32 %12
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %7) #2
  %31 = load i32, ptr %30, align 4, !tbaa !5
  %32 = sext i32 %. to i64
  %33 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %32) #2
  %34 = load i32, ptr %33, align 4, !tbaa !5
  %35 = icmp slt i32 %31, %34
  br i1 %35, label %tailrecurse.backedge, label %._crit_edge

._crit_edge:                                      ; preds = %tailrecurse.backedge, %.lr.ph, %25, %16, %2
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass