; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeHeight = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare hidden void @setTileMapDataColumn(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumn(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i32 noundef %6) #2 {
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  %13 = alloca i16, align 2
  %14 = alloca i32, align 4
  %15 = alloca i16, align 2
  %16 = alloca i16, align 2
  %17 = alloca i16, align 2
  store i32 %0, ptr %8, align 4, !tbaa !5
  store ptr %1, ptr %9, align 8, !tbaa !9
  store i16 %2, ptr %10, align 2, !tbaa !11
  store i16 %3, ptr %11, align 2, !tbaa !11
  store i16 %4, ptr %12, align 2, !tbaa !11
  store i16 %5, ptr %13, align 2, !tbaa !11
  store i32 %6, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %15) #3
  %18 = load i32, ptr %8, align 4, !tbaa !5
  %19 = icmp eq i32 %18, 2
  br i1 %19, label %20, label %21

20:                                               ; preds = %7
  br label %24

21:                                               ; preds = %7
  %22 = load i16, ptr @planeHeight, align 2, !tbaa !11
  %23 = zext i16 %22 to i32
  br label %24

24:                                               ; preds = %21, %20
  %25 = phi i32 [ 32, %20 ], [ %23, %21 ]
  %26 = trunc i32 %25 to i16
  store i16 %26, ptr %15, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %16) #3
  %27 = load i16, ptr %11, align 2, !tbaa !11
  %28 = zext i16 %27 to i32
  %29 = load i16, ptr %15, align 2, !tbaa !11
  %30 = zext i16 %29 to i32
  %31 = sub nsw i32 %30, 1
  %32 = and i32 %28, %31
  %33 = trunc i32 %32 to i16
  store i16 %33, ptr %16, align 2, !tbaa !11
  %34 = load i16, ptr %16, align 2, !tbaa !11
  %35 = zext i16 %34 to i32
  %36 = load i16, ptr %12, align 2, !tbaa !11
  %37 = zext i16 %36 to i32
  %38 = add nsw i32 %35, %37
  %39 = load i16, ptr %15, align 2, !tbaa !11
  %40 = zext i16 %39 to i32
  %41 = icmp sgt i32 %38, %40
  br i1 %41, label %42, label %71

42:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 2, ptr %17) #3
  %43 = load i16, ptr %15, align 2, !tbaa !11
  %44 = zext i16 %43 to i32
  %45 = load i16, ptr %16, align 2, !tbaa !11
  %46 = zext i16 %45 to i32
  %47 = sub nsw i32 %44, %46
  %48 = trunc i32 %47 to i16
  store i16 %48, ptr %17, align 2, !tbaa !11
  %49 = load i32, ptr %8, align 4, !tbaa !5
  %50 = load ptr, ptr %9, align 8, !tbaa !9
  %51 = load i16, ptr %10, align 2, !tbaa !11
  %52 = load i16, ptr %16, align 2, !tbaa !11
  %53 = load i16, ptr %17, align 2, !tbaa !11
  %54 = load i16, ptr %13, align 2, !tbaa !11
  %55 = load i32, ptr %14, align 4, !tbaa !5
  call void @setTileMapDataColumn(i32 noundef %49, ptr noundef %50, i16 noundef zeroext %51, i16 noundef zeroext %52, i16 noundef zeroext %53, i16 noundef zeroext %54, i32 noundef %55)
  %56 = load i32, ptr %8, align 4, !tbaa !5
  %57 = load ptr, ptr %9, align 8, !tbaa !9
  %58 = load i16, ptr %13, align 2, !tbaa !11
  %59 = load i16, ptr %17, align 2, !tbaa !11
  %60 = call i64 @mulu(i16 noundef zeroext %58, i16 noundef zeroext %59)
  %61 = getelementptr inbounds i16, ptr %57, i64 %60
  %62 = load i16, ptr %10, align 2, !tbaa !11
  %63 = load i16, ptr %12, align 2, !tbaa !11
  %64 = zext i16 %63 to i32
  %65 = load i16, ptr %17, align 2, !tbaa !11
  %66 = zext i16 %65 to i32
  %67 = sub nsw i32 %64, %66
  %68 = trunc i32 %67 to i16
  %69 = load i16, ptr %13, align 2, !tbaa !11
  %70 = load i32, ptr %14, align 4, !tbaa !5
  call void @setTileMapDataColumn(i32 noundef %56, ptr noundef %61, i16 noundef zeroext %62, i16 noundef zeroext 0, i16 noundef zeroext %68, i16 noundef zeroext %69, i32 noundef %70)
  call void @llvm.lifetime.end.p0(i64 2, ptr %17) #3
  br label %79

71:                                               ; preds = %24
  %72 = load i32, ptr %8, align 4, !tbaa !5
  %73 = load ptr, ptr %9, align 8, !tbaa !9
  %74 = load i16, ptr %10, align 2, !tbaa !11
  %75 = load i16, ptr %16, align 2, !tbaa !11
  %76 = load i16, ptr %12, align 2, !tbaa !11
  %77 = load i16, ptr %13, align 2, !tbaa !11
  %78 = load i32, ptr %14, align 4, !tbaa !5
  call void @setTileMapDataColumn(i32 noundef %72, ptr noundef %73, i16 noundef zeroext %74, i16 noundef zeroext %75, i16 noundef zeroext %76, i16 noundef zeroext %77, i32 noundef %78)
  br label %79

79:                                               ; preds = %71, %42
  call void @llvm.lifetime.end.p0(i64 2, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %15) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeHeight = external local_unnamed_addr global i16, align 2

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @setTileMapDataColumn(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumn(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i32 noundef %6) local_unnamed_addr #1 {
  %8 = icmp eq i32 %0, 2
  %9 = load i16, ptr @planeHeight, align 2
  %10 = zext i16 %9 to i32
  %11 = select i1 %8, i32 32, i32 %10
  %12 = trunc nuw i32 %11 to i16
  %13 = add i16 %12, -1
  %14 = and i16 %13, %3
  %15 = zext i16 %14 to i32
  %16 = zext i16 %4 to i32
  %17 = add nuw nsw i32 %15, %16
  %18 = icmp ugt i32 %17, %11
  br i1 %18, label %19, label %24

19:                                               ; preds = %7
  %20 = sub i16 %12, %14
  tail call void @setTileMapDataColumn(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %14, i16 noundef zeroext %20, i16 noundef zeroext %5, i32 noundef %6)
  %21 = tail call i64 @mulu(i16 noundef zeroext %5, i16 noundef zeroext %20) #2
  %22 = getelementptr inbounds i16, ptr %1, i64 %21
  %23 = sub i16 %4, %20
  tail call void @setTileMapDataColumn(i32 noundef %0, ptr noundef %22, i16 noundef zeroext %2, i16 noundef zeroext 0, i16 noundef zeroext %23, i16 noundef zeroext %5, i32 noundef %6)
  br label %25

24:                                               ; preds = %7
  tail call void @setTileMapDataColumn(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %14, i16 noundef zeroext %4, i16 noundef zeroext %5, i32 noundef %6)
  br label %25

25:                                               ; preds = %24, %19
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass