; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeWidth = external global i16, align 2
@planeHeight = external global i16, align 2
@windowWidth = external global i16, align 2

declare zeroext i8 @DMA_transfer(i32 noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @VDP_getPlaneAddress(i32 noundef, i16 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumnFast(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5) #2 {
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i16, align 2
  %14 = alloca i16, align 2
  %15 = alloca i16, align 2
  %16 = alloca i16, align 2
  %17 = alloca i16, align 2
  store i32 %0, ptr %7, align 4, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !9
  store i16 %2, ptr %9, align 2, !tbaa !11
  store i16 %3, ptr %10, align 2, !tbaa !11
  store i16 %4, ptr %11, align 2, !tbaa !11
  store i32 %5, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %13) #3
  %18 = load i32, ptr %7, align 4, !tbaa !5
  %19 = load i16, ptr %9, align 2, !tbaa !11
  %20 = load i16, ptr %10, align 2, !tbaa !11
  %21 = call zeroext i16 @VDP_getPlaneAddress(i32 noundef %18, i16 noundef zeroext %19, i16 noundef zeroext %20)
  store i16 %21, ptr %13, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %14) #3
  %22 = load i32, ptr %7, align 4, !tbaa !5
  %23 = icmp eq i32 %22, 2
  br i1 %23, label %24, label %27

24:                                               ; preds = %6
  %25 = load i16, ptr @windowWidth, align 2, !tbaa !11
  %26 = zext i16 %25 to i32
  br label %30

27:                                               ; preds = %6
  %28 = load i16, ptr @planeWidth, align 2, !tbaa !11
  %29 = zext i16 %28 to i32
  br label %30

30:                                               ; preds = %27, %24
  %31 = phi i32 [ %26, %24 ], [ %29, %27 ]
  %32 = trunc i32 %31 to i16
  store i16 %32, ptr %14, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %15) #3
  %33 = load i32, ptr %7, align 4, !tbaa !5
  %34 = icmp eq i32 %33, 2
  br i1 %34, label %35, label %36

35:                                               ; preds = %30
  br label %39

36:                                               ; preds = %30
  %37 = load i16, ptr @planeHeight, align 2, !tbaa !11
  %38 = zext i16 %37 to i32
  br label %39

39:                                               ; preds = %36, %35
  %40 = phi i32 [ 32, %35 ], [ %38, %36 ]
  %41 = trunc i32 %40 to i16
  store i16 %41, ptr %15, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %16) #3
  %42 = load i16, ptr %10, align 2, !tbaa !11
  %43 = zext i16 %42 to i32
  %44 = load i16, ptr %15, align 2, !tbaa !11
  %45 = zext i16 %44 to i32
  %46 = sub nsw i32 %45, 1
  %47 = and i32 %43, %46
  %48 = trunc i32 %47 to i16
  store i16 %48, ptr %16, align 2, !tbaa !11
  %49 = load i16, ptr %16, align 2, !tbaa !11
  %50 = zext i16 %49 to i32
  %51 = load i16, ptr %11, align 2, !tbaa !11
  %52 = zext i16 %51 to i32
  %53 = add nsw i32 %50, %52
  %54 = load i16, ptr %15, align 2, !tbaa !11
  %55 = zext i16 %54 to i32
  %56 = icmp sgt i32 %53, %55
  br i1 %56, label %57, label %93

57:                                               ; preds = %39
  call void @llvm.lifetime.start.p0(i64 2, ptr %17) #3
  %58 = load i16, ptr %15, align 2, !tbaa !11
  %59 = zext i16 %58 to i32
  %60 = load i16, ptr %16, align 2, !tbaa !11
  %61 = zext i16 %60 to i32
  %62 = sub nsw i32 %59, %61
  %63 = trunc i32 %62 to i16
  store i16 %63, ptr %17, align 2, !tbaa !11
  %64 = load i32, ptr %12, align 4, !tbaa !5
  %65 = load ptr, ptr %8, align 8, !tbaa !9
  %66 = load i16, ptr %13, align 2, !tbaa !11
  %67 = load i16, ptr %17, align 2, !tbaa !11
  %68 = load i16, ptr %14, align 2, !tbaa !11
  %69 = zext i16 %68 to i32
  %70 = mul nsw i32 %69, 2
  %71 = trunc i32 %70 to i16
  %72 = call zeroext i8 @DMA_transfer(i32 noundef %64, i8 noundef zeroext 0, ptr noundef %65, i16 noundef zeroext %66, i16 noundef zeroext %67, i16 noundef zeroext %71)
  %73 = load i32, ptr %12, align 4, !tbaa !5
  %74 = load ptr, ptr %8, align 8, !tbaa !9
  %75 = load i16, ptr %17, align 2, !tbaa !11
  %76 = zext i16 %75 to i32
  %77 = sext i32 %76 to i64
  %78 = getelementptr inbounds i16, ptr %74, i64 %77
  %79 = load i32, ptr %7, align 4, !tbaa !5
  %80 = load i16, ptr %9, align 2, !tbaa !11
  %81 = call zeroext i16 @VDP_getPlaneAddress(i32 noundef %79, i16 noundef zeroext %80, i16 noundef zeroext 0)
  %82 = load i16, ptr %11, align 2, !tbaa !11
  %83 = zext i16 %82 to i32
  %84 = load i16, ptr %17, align 2, !tbaa !11
  %85 = zext i16 %84 to i32
  %86 = sub nsw i32 %83, %85
  %87 = trunc i32 %86 to i16
  %88 = load i16, ptr %14, align 2, !tbaa !11
  %89 = zext i16 %88 to i32
  %90 = mul nsw i32 %89, 2
  %91 = trunc i32 %90 to i16
  %92 = call zeroext i8 @DMA_transfer(i32 noundef %73, i8 noundef zeroext 0, ptr noundef %78, i16 noundef zeroext %81, i16 noundef zeroext %87, i16 noundef zeroext %91)
  call void @llvm.lifetime.end.p0(i64 2, ptr %17) #3
  br label %103

93:                                               ; preds = %39
  %94 = load i32, ptr %12, align 4, !tbaa !5
  %95 = load ptr, ptr %8, align 8, !tbaa !9
  %96 = load i16, ptr %13, align 2, !tbaa !11
  %97 = load i16, ptr %11, align 2, !tbaa !11
  %98 = load i16, ptr %14, align 2, !tbaa !11
  %99 = zext i16 %98 to i32
  %100 = mul nsw i32 %99, 2
  %101 = trunc i32 %100 to i16
  %102 = call zeroext i8 @DMA_transfer(i32 noundef %94, i8 noundef zeroext 0, ptr noundef %95, i16 noundef zeroext %96, i16 noundef zeroext %97, i16 noundef zeroext %101)
  br label %103

103:                                              ; preds = %93, %57
  call void @llvm.lifetime.end.p0(i64 2, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %13) #3
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeWidth = external local_unnamed_addr global i16, align 2
@planeHeight = external local_unnamed_addr global i16, align 2
@windowWidth = external local_unnamed_addr global i16, align 2

declare zeroext i8 @DMA_transfer(i32 noundef, i8 noundef zeroext, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @VDP_getPlaneAddress(i32 noundef, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumnFast(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5) local_unnamed_addr #1 {
  %7 = tail call zeroext i16 @VDP_getPlaneAddress(i32 noundef %0, i16 noundef zeroext %2, i16 noundef zeroext %3)
  %8 = icmp eq i32 %0, 2
  %9 = load i16, ptr @windowWidth, align 2
  %10 = load i16, ptr @planeWidth, align 2
  %.v = select i1 %8, i16 %9, i16 %10
  %11 = load i16, ptr @planeHeight, align 2
  %12 = zext i16 %11 to i32
  %13 = select i1 %8, i32 32, i32 %12
  %14 = trunc nuw i32 %13 to i16
  %15 = add i16 %14, -1
  %16 = and i16 %15, %3
  %17 = zext i16 %16 to i32
  %18 = zext i16 %4 to i32
  %19 = add nuw nsw i32 %17, %18
  %20 = icmp ugt i32 %19, %13
  br i1 %20, label %21, label %30

21:                                               ; preds = %6
  %22 = sub i16 %14, %16
  %23 = shl i16 %.v, 1
  %24 = tail call zeroext i8 @DMA_transfer(i32 noundef %5, i8 noundef zeroext 0, ptr noundef %1, i16 noundef zeroext %7, i16 noundef zeroext %22, i16 noundef zeroext %23) #2
  %25 = zext i16 %22 to i64
  %26 = getelementptr inbounds i16, ptr %1, i64 %25
  %27 = tail call zeroext i16 @VDP_getPlaneAddress(i32 noundef %0, i16 noundef zeroext %2, i16 noundef zeroext 0)
  %28 = sub i16 %4, %22
  %29 = tail call zeroext i8 @DMA_transfer(i32 noundef %5, i8 noundef zeroext 0, ptr noundef %26, i16 noundef zeroext %27, i16 noundef zeroext %28, i16 noundef zeroext %23) #2
  br label %33

30:                                               ; preds = %6
  %31 = shl i16 %.v, 1
  %32 = tail call zeroext i8 @DMA_transfer(i32 noundef %5, i8 noundef zeroext 0, ptr noundef %1, i16 noundef zeroext %7, i16 noundef zeroext %4, i16 noundef zeroext %31) #2
  br label %33

33:                                               ; preds = %30, %21
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass