; LLVM IR from Stephane-D/SGDK :: src (dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @VDP_setAutoInc(i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doVRamFill(i16 noundef zeroext %0, i16 noundef zeroext %1, i8 noundef zeroext %2, i16 noundef signext %3) #2 {
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca i8, align 1
  %8 = alloca i16, align 2
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i16, align 2
  store i16 %0, ptr %5, align 2, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !5
  store i8 %2, ptr %7, align 1, !tbaa !9
  store i16 %3, ptr %8, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #3
  %12 = load i16, ptr %8, align 2, !tbaa !5
  %13 = sext i16 %12 to i32
  %14 = icmp ne i32 %13, -1
  br i1 %14, label %15, label %18

15:                                               ; preds = %4
  %16 = load i16, ptr %8, align 2, !tbaa !5
  %17 = trunc i16 %16 to i8
  call void @VDP_setAutoInc(i8 noundef zeroext %17)
  br label %18

18:                                               ; preds = %15, %4
  %19 = load i16, ptr %6, align 2, !tbaa !5
  %20 = icmp ne i16 %19, 0
  br i1 %20, label %21, label %49

21:                                               ; preds = %18
  %22 = load i16, ptr %5, align 2, !tbaa !5
  %23 = zext i16 %22 to i32
  %24 = and i32 %23, 1
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %37

26:                                               ; preds = %21
  %27 = load i16, ptr %6, align 2, !tbaa !5
  %28 = zext i16 %27 to i32
  %29 = icmp slt i32 %28, 3
  br i1 %29, label %30, label %31

30:                                               ; preds = %26
  store i16 1, ptr %11, align 2, !tbaa !5
  br label %36

31:                                               ; preds = %26
  %32 = load i16, ptr %6, align 2, !tbaa !5
  %33 = zext i16 %32 to i32
  %34 = sub nsw i32 %33, 2
  %35 = trunc i32 %34 to i16
  store i16 %35, ptr %11, align 2, !tbaa !5
  br label %36

36:                                               ; preds = %31, %30
  br label %48

37:                                               ; preds = %21
  %38 = load i16, ptr %6, align 2, !tbaa !5
  %39 = zext i16 %38 to i32
  %40 = icmp slt i32 %39, 2
  br i1 %40, label %41, label %42

41:                                               ; preds = %37
  store i16 1, ptr %11, align 2, !tbaa !5
  br label %47

42:                                               ; preds = %37
  %43 = load i16, ptr %6, align 2, !tbaa !5
  %44 = zext i16 %43 to i32
  %45 = sub nsw i32 %44, 1
  %46 = trunc i32 %45 to i16
  store i16 %46, ptr %11, align 2, !tbaa !5
  br label %47

47:                                               ; preds = %42, %41
  br label %48

48:                                               ; preds = %47, %36
  br label %51

49:                                               ; preds = %18
  %50 = load i16, ptr %6, align 2, !tbaa !5
  store i16 %50, ptr %11, align 2, !tbaa !5
  br label %51

51:                                               ; preds = %49, %48
  store ptr inttoptr (i64 12582916 to ptr), ptr %9, align 8, !tbaa !10
  %52 = load i16, ptr %11, align 2, !tbaa !5
  %53 = zext i16 %52 to i32
  %54 = and i32 %53, 255
  %55 = add nsw i32 37632, %54
  %56 = trunc i32 %55 to i16
  %57 = load ptr, ptr %9, align 8, !tbaa !10
  store volatile i16 %56, ptr %57, align 2, !tbaa !5
  %58 = load i16, ptr %11, align 2, !tbaa !5
  %59 = zext i16 %58 to i32
  %60 = ashr i32 %59, 8
  %61 = and i32 %60, 255
  %62 = add nsw i32 37888, %61
  %63 = trunc i32 %62 to i16
  %64 = load ptr, ptr %9, align 8, !tbaa !10
  store volatile i16 %63, ptr %64, align 2, !tbaa !5
  %65 = load ptr, ptr %9, align 8, !tbaa !10
  store volatile i16 -26752, ptr %65, align 2, !tbaa !5
  store ptr inttoptr (i64 12582916 to ptr), ptr %10, align 8, !tbaa !10
  %66 = load i16, ptr %5, align 2, !tbaa !5
  %67 = zext i16 %66 to i64
  %68 = and i64 %67, 16383
  %69 = add i64 16384, %68
  %70 = shl i64 %69, 16
  %71 = load i16, ptr %5, align 2, !tbaa !5
  %72 = zext i16 %71 to i64
  %73 = lshr i64 %72, 14
  %74 = or i64 %73, 128
  %75 = add i64 %70, %74
  %76 = load ptr, ptr %10, align 8, !tbaa !10
  store volatile i64 %75, ptr %76, align 8, !tbaa !12
  store ptr inttoptr (i64 12582912 to ptr), ptr %9, align 8, !tbaa !10
  %77 = load i8, ptr %7, align 1, !tbaa !9
  %78 = zext i8 %77 to i32
  %79 = load i8, ptr %7, align 1, !tbaa !9
  %80 = zext i8 %79 to i32
  %81 = shl i32 %80, 8
  %82 = or i32 %78, %81
  %83 = trunc i32 %82 to i16
  %84 = load ptr, ptr %9, align 8, !tbaa !10
  store volatile i16 %83, ptr %84, align 2, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @VDP_setAutoInc(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doVRamFill(i16 noundef zeroext %0, i16 noundef zeroext %1, i8 noundef zeroext %2, i16 noundef signext %3) local_unnamed_addr #1 {
  %.not = icmp eq i16 %3, -1
  br i1 %.not, label %7, label %5

5:                                                ; preds = %4
  %6 = trunc i16 %3 to i8
  tail call void @VDP_setAutoInc(i8 noundef zeroext %6) #2
  br label %7

7:                                                ; preds = %5, %4
  %.not22 = icmp eq i16 %1, 0
  br i1 %.not22, label %16, label %8

8:                                                ; preds = %7
  %9 = and i16 %0, 1
  %.not23 = icmp eq i16 %9, 0
  br i1 %.not23, label %13, label %10

10:                                               ; preds = %8
  %11 = icmp ult i16 %1, 3
  %12 = add i16 %1, -2
  %spec.select = select i1 %11, i16 1, i16 %12
  br label %16

13:                                               ; preds = %8
  %14 = icmp eq i16 %1, 1
  %15 = add i16 %1, -1
  %spec.select24 = select i1 %14, i16 1, i16 %15
  br label %16

16:                                               ; preds = %13, %10, %7
  %.0 = phi i16 [ 0, %7 ], [ %spec.select, %10 ], [ %spec.select24, %13 ]
  %17 = and i16 %.0, 255
  %18 = or disjoint i16 %17, -27904
  store volatile i16 %18, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %19 = lshr i16 %.0, 8
  %20 = or disjoint i16 %19, -27648
  store volatile i16 %20, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  store volatile i16 -26752, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %21 = zext i16 %0 to i64
  %22 = shl nuw nsw i64 %21, 16
  %23 = and i64 %22, 1073676288
  %24 = lshr i64 %21, 14
  %25 = or disjoint i64 %24, %23
  %26 = or disjoint i64 %25, 1073741952
  store volatile i64 %26, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !9
  %27 = zext i8 %2 to i16
  %28 = mul nuw i16 %27, 257
  store volatile i16 %28, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !5
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}


; Effective O3 passes: AggressiveInstCombinePass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass