; LLVM IR from Stephane-D/SGDK :: src (dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @VDP_setAutoInc(i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doVRamCopy(i16 noundef zeroext %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef signext %3) #2 {
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca i16, align 2
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  store i16 %0, ptr %5, align 2, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !5
  store i16 %2, ptr %7, align 2, !tbaa !5
  store i16 %3, ptr %8, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %11 = load i16, ptr %8, align 2, !tbaa !5
  %12 = sext i16 %11 to i32
  %13 = icmp ne i32 %12, -1
  br i1 %13, label %14, label %17

14:                                               ; preds = %4
  %15 = load i16, ptr %8, align 2, !tbaa !5
  %16 = trunc i16 %15 to i8
  call void @VDP_setAutoInc(i8 noundef zeroext %16)
  br label %17

17:                                               ; preds = %14, %4
  store ptr inttoptr (i64 12582916 to ptr), ptr %9, align 8, !tbaa !9
  %18 = load i16, ptr %7, align 2, !tbaa !5
  %19 = zext i16 %18 to i32
  %20 = and i32 %19, 255
  %21 = add nsw i32 37632, %20
  %22 = trunc i32 %21 to i16
  %23 = load ptr, ptr %9, align 8, !tbaa !9
  store volatile i16 %22, ptr %23, align 2, !tbaa !5
  %24 = load i16, ptr %7, align 2, !tbaa !5
  %25 = zext i16 %24 to i32
  %26 = ashr i32 %25, 8
  %27 = and i32 %26, 255
  %28 = add nsw i32 37888, %27
  %29 = trunc i32 %28 to i16
  %30 = load ptr, ptr %9, align 8, !tbaa !9
  store volatile i16 %29, ptr %30, align 2, !tbaa !5
  %31 = load i16, ptr %5, align 2, !tbaa !5
  %32 = zext i16 %31 to i32
  %33 = and i32 %32, 255
  %34 = add nsw i32 38144, %33
  %35 = trunc i32 %34 to i16
  %36 = load ptr, ptr %9, align 8, !tbaa !9
  store volatile i16 %35, ptr %36, align 2, !tbaa !5
  %37 = load i16, ptr %5, align 2, !tbaa !5
  %38 = zext i16 %37 to i32
  %39 = ashr i32 %38, 8
  %40 = and i32 %39, 255
  %41 = add nsw i32 38400, %40
  %42 = trunc i32 %41 to i16
  %43 = load ptr, ptr %9, align 8, !tbaa !9
  store volatile i16 %42, ptr %43, align 2, !tbaa !5
  %44 = load ptr, ptr %9, align 8, !tbaa !9
  store volatile i16 -26688, ptr %44, align 2, !tbaa !5
  store ptr inttoptr (i64 12582916 to ptr), ptr %10, align 8, !tbaa !9
  %45 = load i16, ptr %6, align 2, !tbaa !5
  %46 = zext i16 %45 to i64
  %47 = and i64 %46, 16383
  %48 = add i64 16384, %47
  %49 = shl i64 %48, 16
  %50 = load i16, ptr %6, align 2, !tbaa !5
  %51 = zext i16 %50 to i64
  %52 = lshr i64 %51, 14
  %53 = or i64 %52, 192
  %54 = add i64 %49, %53
  %55 = load ptr, ptr %10, align 8, !tbaa !9
  store volatile i64 %54, ptr %55, align 8, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @VDP_setAutoInc(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doVRamCopy(i16 noundef zeroext %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef signext %3) local_unnamed_addr #1 {
  %.not = icmp eq i16 %3, -1
  br i1 %.not, label %7, label %5

5:                                                ; preds = %4
  %6 = trunc i16 %3 to i8
  tail call void @VDP_setAutoInc(i8 noundef zeroext %6) #2
  br label %7

7:                                                ; preds = %5, %4
  %8 = and i16 %2, 255
  %9 = or disjoint i16 %8, -27904
  store volatile i16 %9, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %10 = lshr i16 %2, 8
  %11 = or disjoint i16 %10, -27648
  store volatile i16 %11, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %12 = and i16 %0, 255
  %13 = or disjoint i16 %12, -27392
  store volatile i16 %13, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %14 = lshr i16 %0, 8
  %15 = or disjoint i16 %14, -27136
  store volatile i16 %15, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  store volatile i16 -26688, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %16 = zext i16 %1 to i64
  %17 = shl nuw nsw i64 %16, 16
  %18 = and i64 %17, 1073676288
  %19 = lshr i64 %16, 14
  %20 = or disjoint i64 %19, %18
  %21 = or disjoint i64 %20, 1073742016
  store volatile i64 %21, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !9
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass