; LLVM IR from HarshCasper/NeoAlgo :: C-Plus-Plus/graphs (Connecting_Dots-Graphs_using_cpp)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z7connectRSt6vectorIS_IcSaIcEESaIS1_EEiiPPbiiiici(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef signext, i32 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z8hasCycleRSt6vectorIS_IcSaIcEESaIS1_EEii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2) #0 {
  %4 = alloca i1, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i8, align 1
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %15 = load i32, ptr %6, align 4, !tbaa !9
  %16 = sext i32 %15 to i64
  %17 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %16, i64 8)
  %18 = extractvalue { i64, i1 } %17, 1
  %19 = extractvalue { i64, i1 } %17, 0
  %20 = select i1 %18, i64 -1, i64 %19
  %21 = call noalias noundef nonnull ptr @_Znam(i64 noundef %20) #6
  store ptr %21, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %53, %3
  %23 = load i32, ptr %9, align 4, !tbaa !9
  %24 = load i32, ptr %6, align 4, !tbaa !9
  %25 = icmp slt i32 %23, %24
  br i1 %25, label %27, label %26

26:                                               ; preds = %22
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %56

27:                                               ; preds = %22
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = sext i32 %28 to i64
  %30 = call noalias noundef nonnull ptr @_Znam(i64 noundef %29) #6
  %31 = load ptr, ptr %8, align 8, !tbaa !5
  %32 = load i32, ptr %9, align 4, !tbaa !9
  %33 = sext i32 %32 to i64
  %34 = getelementptr inbounds ptr, ptr %31, i64 %33
  store ptr %30, ptr %34, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %35

35:                                               ; preds = %49, %27
  %36 = load i32, ptr %11, align 4, !tbaa !9
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = icmp slt i32 %36, %37
  br i1 %38, label %40, label %39

39:                                               ; preds = %35
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  br label %52

40:                                               ; preds = %35
  %41 = load ptr, ptr %8, align 8, !tbaa !5
  %42 = load i32, ptr %9, align 4, !tbaa !9
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds ptr, ptr %41, i64 %43
  %45 = load ptr, ptr %44, align 8, !tbaa !5
  %46 = load i32, ptr %11, align 4, !tbaa !9
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds i8, ptr %45, i64 %47
  store i8 0, ptr %48, align 1, !tbaa !11
  br label %49

49:                                               ; preds = %40
  %50 = load i32, ptr %11, align 4, !tbaa !9
  %51 = add nsw i32 %50, 1
  store i32 %51, ptr %11, align 4, !tbaa !9
  br label %35, !llvm.loop !13

52:                                               ; preds = %39
  br label %53

53:                                               ; preds = %52
  %54 = load i32, ptr %9, align 4, !tbaa !9
  %55 = add nsw i32 %54, 1
  store i32 %55, ptr %9, align 4, !tbaa !9
  br label %22, !llvm.loop !15

56:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %100, %56
  %58 = load i32, ptr %12, align 4, !tbaa !9
  %59 = load i32, ptr %6, align 4, !tbaa !9
  %60 = icmp slt i32 %58, %59
  br i1 %60, label %62, label %61

61:                                               ; preds = %57
  store i32 8, ptr %10, align 4
  br label %103

62:                                               ; preds = %57
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %63

63:                                               ; preds = %94, %62
  %64 = load i32, ptr %13, align 4, !tbaa !9
  %65 = load i32, ptr %7, align 4, !tbaa !9
  %66 = icmp slt i32 %64, %65
  br i1 %66, label %68, label %67

67:                                               ; preds = %63
  store i32 11, ptr %10, align 4
  br label %97

68:                                               ; preds = %63
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #5
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = load i32, ptr %6, align 4, !tbaa !9
  %71 = load i32, ptr %7, align 4, !tbaa !9
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = load i32, ptr %12, align 4, !tbaa !9
  %74 = load i32, ptr %13, align 4, !tbaa !9
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = load i32, ptr %13, align 4, !tbaa !9
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  %78 = load i32, ptr %12, align 4, !tbaa !9
  %79 = sext i32 %78 to i64
  %80 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %77, i64 noundef %79) #5
  %81 = load i32, ptr %13, align 4, !tbaa !9
  %82 = sext i32 %81 to i64
  %83 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %80, i64 noundef %82) #5
  %84 = load i8, ptr %83, align 1, !tbaa !16
  %85 = call noundef zeroext i1 @_Z7connectRSt6vectorIS_IcSaIcEESaIS1_EEiiPPbiiiici(ptr noundef nonnull align 8 dereferenceable(24) %69, i32 noundef %70, i32 noundef %71, ptr noundef %72, i32 noundef %73, i32 noundef %74, i32 noundef %75, i32 noundef %76, i8 noundef signext %84, i32 noundef 1)
  %86 = zext i1 %85 to i8
  store i8 %86, ptr %14, align 1, !tbaa !11
  %87 = load i8, ptr %14, align 1, !tbaa !11, !range !17, !noundef !18
  %88 = trunc i8 %87 to i1
  br i1 %88, label %89, label %90

89:                                               ; preds = %68
  store i1 true, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %91

90:                                               ; preds = %68
  store i32 0, ptr %10, align 4
  br label %91

91:                                               ; preds = %90, %89
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #5
  %92 = load i32, ptr %10, align 4
  switch i32 %92, label %97 [
    i32 0, label %93
  ]

93:                                               ; preds = %91
  br label %94

94:                                               ; preds = %93
  %95 = load i32, ptr %13, align 4, !tbaa !9
  %96 = add nsw i32 %95, 1
  store i32 %96, ptr %13, align 4, !tbaa !9
  br label %63, !llvm.loop !19

97:                                               ; preds = %91, %67
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  %98 = load i32, ptr %10, align 4
  switch i32 %98, label %103 [
    i32 11, label %99
  ]

99:                                               ; preds = %97
  br label %100

100:                                              ; preds = %99
  %101 = load i32, ptr %12, align 4, !tbaa !9
  %102 = add nsw i32 %101, 1
  store i32 %102, ptr %12, align 4, !tbaa !9
  br label %57, !llvm.loop !20

103:                                              ; preds = %97, %61
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  %104 = load i32, ptr %10, align 4
  switch i32 %104, label %106 [
    i32 8, label %105
  ]

105:                                              ; preds = %103
  store i1 false, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %106

106:                                              ; preds = %105, %103
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  %107 = load i1, ptr %4, align 1
  ret i1 %107
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #3

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = !{!7, !7, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}
!19 = distinct !{!19, !14}
!20 = distinct !{!20, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z7connectRSt6vectorIS_IcSaIcEESaIS1_EEiiPPbiiiici(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef, ptr noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, i8 noundef signext, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z8hasCycleRSt6vectorIS_IcSaIcEESaIS1_EEii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = zext i32 %1 to i64
  %5 = icmp slt i32 %1, 0
  %6 = shl nuw nsw i64 %4, 3
  %7 = select i1 %5, i64 -1, i64 %6
  %8 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %7) #4
  %9 = icmp sgt i32 %1, 0
  br i1 %9, label %.lr.ph55, label %.critedge47

.lr.ph55:                                         ; preds = %3
  %10 = sext i32 %2 to i64
  %11 = icmp sgt i32 %2, 0
  br i1 %11, label %.lr.ph.us.preheader, label %.lr.ph55.split

.lr.ph.us.preheader:                              ; preds = %.lr.ph55
  %12 = zext nneg i32 %2 to i64
  br label %.lr.ph.us

.lr.ph.us:                                        ; preds = %.lr.ph.us.preheader, %.lr.ph.us
  %indvars.iv71 = phi i64 [ 0, %.lr.ph.us.preheader ], [ %indvars.iv.next72, %.lr.ph.us ]
  %13 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %10) #4
  %14 = getelementptr inbounds ptr, ptr %8, i64 %indvars.iv71
  store ptr %13, ptr %14, align 8, !tbaa !5
  tail call void @llvm.memset.p0.i64(ptr nonnull align 1 %13, i8 0, i64 %12, i1 false), !tbaa !9
  %indvars.iv.next72 = add nuw nsw i64 %indvars.iv71, 1
  %exitcond75.not = icmp eq i64 %indvars.iv.next72, %4
  br i1 %exitcond75.not, label %.preheader48, label %.lr.ph.us, !llvm.loop !11

.preheader48:                                     ; preds = %.lr.ph55.split, %.lr.ph.us
  %.not56 = icmp sgt i32 %2, 0
  %or.cond = and i1 %9, %.not56
  br i1 %or.cond, label %.preheader.us.preheader, label %.critedge47

.preheader.us.preheader:                          ; preds = %.preheader48
  %15 = zext nneg i32 %1 to i64
  %wide.trip.count80 = zext nneg i32 %2 to i64
  br label %.preheader.us

.preheader.us:                                    ; preds = %.preheader.us.preheader, %..critedge_crit_edge.us
  %indvars.iv82 = phi i64 [ 0, %.preheader.us.preheader ], [ %indvars.iv.next83, %..critedge_crit_edge.us ]
  %.not4560.us = phi i1 [ true, %.preheader.us.preheader ], [ %.not45.us, %..critedge_crit_edge.us ]
  %16 = trunc nuw nsw i64 %indvars.iv82 to i32
  br label %18

17:                                               ; preds = %18
  %indvars.iv.next78 = add nuw nsw i64 %indvars.iv77, 1
  %exitcond81.not = icmp eq i64 %indvars.iv.next78, %wide.trip.count80
  br i1 %exitcond81.not, label %..critedge_crit_edge.us, label %18, !llvm.loop !13

18:                                               ; preds = %.preheader.us, %17
  %indvars.iv77 = phi i64 [ 0, %.preheader.us ], [ %indvars.iv.next78, %17 ]
  %19 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv82) #5
  %20 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %indvars.iv77) #5
  %21 = load i8, ptr %20, align 1, !tbaa !14
  %22 = trunc nuw nsw i64 %indvars.iv77 to i32
  %23 = tail call noundef zeroext i1 @_Z7connectRSt6vectorIS_IcSaIcEESaIS1_EEiiPPbiiiici(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull %8, i32 noundef %16, i32 noundef %22, i32 noundef %16, i32 noundef %22, i8 noundef signext %21, i32 noundef 1)
  br i1 %23, label %.critedge47, label %17

..critedge_crit_edge.us:                          ; preds = %17
  %indvars.iv.next83 = add nuw nsw i64 %indvars.iv82, 1
  %.not45.us = icmp ult i64 %indvars.iv.next83, %15
  %exitcond85.not = icmp eq i64 %indvars.iv.next83, %4
  br i1 %exitcond85.not, label %.critedge47, label %.preheader.us, !llvm.loop !15

.lr.ph55.split:                                   ; preds = %.lr.ph55, %.lr.ph55.split
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph55.split ], [ 0, %.lr.ph55 ]
  %24 = tail call noalias noundef nonnull ptr @_Znam(i64 noundef %10) #4
  %25 = getelementptr inbounds ptr, ptr %8, i64 %indvars.iv
  store ptr %24, ptr %25, align 8, !tbaa !5
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %4
  br i1 %exitcond.not, label %.preheader48, label %.lr.ph55.split, !llvm.loop !11

.critedge47:                                      ; preds = %..critedge_crit_edge.us, %18, %3, %.preheader48
  %.not4551 = phi i1 [ false, %.preheader48 ], [ false, %3 ], [ %.not4560.us, %18 ], [ %.not45.us, %..critedge_crit_edge.us ]
  ret i1 %.not4551
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = !{!7, !7, i64 0}
!15 = distinct !{!15, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopIdiomRecognizePass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass