; LLVM IR from xirc/cp-algorithm :: atcoder/abc007/D/main.ll (Z5queryl)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@DP = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5log10l(i64 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z5pow10i(i32 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5queryl(i64 noundef %0) #2 {
  %2 = alloca i64, align 8
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  %8 = load i64, ptr %3, align 8, !tbaa !5
  %9 = icmp eq i64 %8, 0
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store i64 0, ptr %2, align 8
  br label %59

11:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  %12 = load i64, ptr %3, align 8, !tbaa !5
  %13 = call noundef i32 @_Z5log10l(i64 noundef %12)
  store i32 %13, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  %14 = load i32, ptr %4, align 4, !tbaa !9
  %15 = call noundef i64 @_Z5pow10i(i32 noundef %14)
  store i64 %15, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %16 = load i64, ptr %3, align 8, !tbaa !5
  %17 = load i64, ptr %5, align 8, !tbaa !5
  %18 = sdiv i64 %16, %17
  store i64 %18, ptr %6, align 8, !tbaa !5
  %19 = load i64, ptr %6, align 8, !tbaa !5
  %20 = icmp eq i64 %19, 4
  br i1 %20, label %24, label %21

21:                                               ; preds = %11
  %22 = load i64, ptr %6, align 8, !tbaa !5
  %23 = icmp eq i64 %22, 9
  br i1 %23, label %24, label %45

24:                                               ; preds = %21, %11
  %25 = load i64, ptr %5, align 8, !tbaa !5
  %26 = icmp eq i64 %25, 1
  br i1 %26, label %27, label %32

27:                                               ; preds = %24
  %28 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef 0) #3
  %29 = load i64, ptr %6, align 8, !tbaa !5
  %30 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %29) #3
  %31 = load i64, ptr %30, align 8, !tbaa !5
  store i64 %31, ptr %2, align 8
  store i32 1, ptr %7, align 4
  br label %58

32:                                               ; preds = %24
  %33 = load i32, ptr %4, align 4, !tbaa !9
  %34 = sext i32 %33 to i64
  %35 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %34) #3
  %36 = load i64, ptr %6, align 8, !tbaa !5
  %37 = sub nsw i64 %36, 1
  %38 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %37) #3
  %39 = load i64, ptr %38, align 8, !tbaa !5
  %40 = load i64, ptr %3, align 8, !tbaa !5
  %41 = load i64, ptr %5, align 8, !tbaa !5
  %42 = srem i64 %40, %41
  %43 = add nsw i64 %39, %42
  %44 = add nsw i64 %43, 1
  store i64 %44, ptr %2, align 8
  store i32 1, ptr %7, align 4
  br label %58

45:                                               ; preds = %21
  %46 = load i32, ptr %4, align 4, !tbaa !9
  %47 = sext i32 %46 to i64
  %48 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %47) #3
  %49 = load i64, ptr %6, align 8, !tbaa !5
  %50 = sub nsw i64 %49, 1
  %51 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %50) #3
  %52 = load i64, ptr %51, align 8, !tbaa !5
  %53 = load i64, ptr %3, align 8, !tbaa !5
  %54 = load i64, ptr %5, align 8, !tbaa !5
  %55 = srem i64 %53, %54
  %56 = call noundef i64 @_Z5queryl(i64 noundef %55)
  %57 = add nsw i64 %52, %56
  store i64 %57, ptr %2, align 8
  store i32 1, ptr %7, align 4
  br label %58

58:                                               ; preds = %45, %32, %27
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  br label %59

59:                                               ; preds = %58, %10
  %60 = load i64, ptr %2, align 8
  ret i64 %60
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@DP = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5log10l(i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_Z5pow10i(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z5queryl(i64 noundef %0) local_unnamed_addr #0 {
  %2 = icmp eq i64 %0, 0
  br i1 %2, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %1, %tailrecurse
  %.tr28 = phi i64 [ %6, %tailrecurse ], [ %0, %1 ]
  %accumulator.tr27 = phi i64 [ %27, %tailrecurse ], [ 0, %1 ]
  %3 = tail call noundef i32 @_Z5log10l(i64 noundef %.tr28)
  %4 = tail call noundef i64 @_Z5pow10i(i32 noundef %3)
  %5 = sdiv i64 %.tr28, %4
  %6 = srem i64 %.tr28, %4
  switch i64 %5, label %tailrecurse [
    i64 9, label %7
    i64 4, label %7
  ]

7:                                                ; preds = %.lr.ph, %.lr.ph
  %8 = icmp eq i64 %4, 1
  br i1 %8, label %9, label %13

9:                                                ; preds = %7
  %10 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef 0) #1
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %5) #1
  %12 = load i64, ptr %11, align 8, !tbaa !5
  br label %.loopexit

13:                                               ; preds = %7
  %14 = sext i32 %3 to i64
  %15 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %14) #1
  %16 = add nsw i64 %5, -1
  %17 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %16) #1
  %18 = load i64, ptr %17, align 8, !tbaa !5
  %19 = srem i64 %.tr28, %4
  %20 = add i64 %18, 1
  %21 = add i64 %20, %19
  br label %.loopexit

tailrecurse:                                      ; preds = %.lr.ph
  %22 = sext i32 %3 to i64
  %23 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %22) #1
  %24 = add nsw i64 %5, -1
  %25 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %24) #1
  %26 = load i64, ptr %25, align 8, !tbaa !5
  %27 = add nsw i64 %26, %accumulator.tr27
  %28 = icmp eq i64 %6, 0
  br i1 %28, label %.loopexit, label %.lr.ph

.loopexit:                                        ; preds = %tailrecurse, %1, %9, %13
  %accumulator.tr24 = phi i64 [ %accumulator.tr27, %9 ], [ %accumulator.tr27, %13 ], [ 0, %1 ], [ %27, %tailrecurse ]
  %.1 = phi i64 [ %12, %9 ], [ %21, %13 ], [ 0, %1 ], [ 0, %tailrecurse ]
  %accumulator.ret.tr = add nsw i64 %.1, %accumulator.tr24
  ret i64 %accumulator.ret.tr
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: DivRemPairsPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass