; LLVM IR from Nigh/Basic-Compression-Library :: src (rice)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.rice_bitstream_t = type { ptr, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_InitBitstream(ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_NumBits(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Rice_Uncompress(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #1 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca %struct.rice_bitstream_t, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca [16 x i32], align 16
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.start.p0(i64 64, ptr %17) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #2
  %20 = load i32, ptr %10, align 4, !tbaa !9
  switch i32 %20, label %24 [
    i32 1, label %21
    i32 2, label %21
    i32 3, label %22
    i32 4, label %22
    i32 7, label %23
    i32 8, label %23
  ]

21:                                               ; preds = %5, %5
  store i32 8, ptr %15, align 4, !tbaa !9
  br label %25

22:                                               ; preds = %5, %5
  store i32 16, ptr %15, align 4, !tbaa !9
  br label %25

23:                                               ; preds = %5, %5
  store i32 32, ptr %15, align 4, !tbaa !9
  br label %25

24:                                               ; preds = %5
  store i32 1, ptr %19, align 4
  br label %115

25:                                               ; preds = %23, %22, %21
  %26 = load i32, ptr %9, align 4, !tbaa !9
  %27 = load i32, ptr %15, align 4, !tbaa !9
  %28 = lshr i32 %27, 3
  %29 = udiv i32 %26, %28
  store i32 %29, ptr %16, align 4, !tbaa !9
  %30 = load i32, ptr %16, align 4, !tbaa !9
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %33

32:                                               ; preds = %25
  store i32 1, ptr %19, align 4
  br label %115

33:                                               ; preds = %25
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = load i32, ptr %8, align 4, !tbaa !9
  call void @_Rice_InitBitstream(ptr noundef %11, ptr noundef %34, i32 noundef %35)
  %36 = load ptr, ptr %6, align 8, !tbaa !5
  %37 = getelementptr inbounds i8, ptr %36, i64 0
  %38 = load i8, ptr %37, align 1, !tbaa !11
  %39 = zext i8 %38 to i32
  store i32 %39, ptr %14, align 4, !tbaa !9
  %40 = getelementptr inbounds %struct.rice_bitstream_t, ptr %11, i32 0, i32 1
  store i32 8, ptr %40, align 8, !tbaa !12
  %41 = load i32, ptr %14, align 4, !tbaa !9
  %42 = icmp eq i32 %41, 0
  br i1 %42, label %43, label %71

43:                                               ; preds = %33
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %44

44:                                               ; preds = %67, %43
  %45 = load i32, ptr %12, align 4, !tbaa !9
  %46 = load i32, ptr %16, align 4, !tbaa !9
  %47 = icmp ult i32 %45, %46
  br i1 %47, label %48, label %70

48:                                               ; preds = %44
  store i32 0, ptr %13, align 4, !tbaa !9
  %49 = load i32, ptr %15, align 4, !tbaa !9
  %50 = sub i32 %49, 1
  store i32 %50, ptr %18, align 4, !tbaa !9
  br label %51

51:                                               ; preds = %59, %48
  %52 = load i32, ptr %18, align 4, !tbaa !9
  %53 = icmp sge i32 %52, 0
  br i1 %53, label %54, label %62

54:                                               ; preds = %51
  %55 = load i32, ptr %13, align 4, !tbaa !9
  %56 = shl i32 %55, 1
  %57 = call i32 @_Rice_ReadBit(ptr noundef %11)
  %58 = or i32 %56, %57
  store i32 %58, ptr %13, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %54
  %60 = load i32, ptr %18, align 4, !tbaa !9
  %61 = add nsw i32 %60, -1
  store i32 %61, ptr %18, align 4, !tbaa !9
  br label %51, !llvm.loop !14

62:                                               ; preds = %51
  %63 = load ptr, ptr %7, align 8, !tbaa !5
  %64 = load i32, ptr %12, align 4, !tbaa !9
  %65 = load i32, ptr %10, align 4, !tbaa !9
  %66 = load i32, ptr %13, align 4, !tbaa !9
  call void @_Rice_WriteWord(ptr noundef %63, i32 noundef %64, i32 noundef %65, i32 noundef %66)
  br label %67

67:                                               ; preds = %62
  %68 = load i32, ptr %12, align 4, !tbaa !9
  %69 = add i32 %68, 1
  store i32 %69, ptr %12, align 4, !tbaa !9
  br label %44, !llvm.loop !16

70:                                               ; preds = %44
  br label %114

71:                                               ; preds = %33
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %72

72:                                               ; preds = %110, %71
  %73 = load i32, ptr %12, align 4, !tbaa !9
  %74 = load i32, ptr %16, align 4, !tbaa !9
  %75 = icmp ult i32 %73, %74
  br i1 %75, label %76, label %113

76:                                               ; preds = %72
  %77 = load i32, ptr %12, align 4, !tbaa !9
  %78 = icmp uge i32 %77, 16
  br i1 %78, label %79, label %97

79:                                               ; preds = %76
  store i32 0, ptr %14, align 4, !tbaa !9
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %80

80:                                               ; preds = %90, %79
  %81 = load i32, ptr %18, align 4, !tbaa !9
  %82 = icmp slt i32 %81, 16
  br i1 %82, label %83, label %93

83:                                               ; preds = %80
  %84 = load i32, ptr %18, align 4, !tbaa !9
  %85 = sext i32 %84 to i64
  %86 = getelementptr inbounds [16 x i32], ptr %17, i64 0, i64 %85
  %87 = load i32, ptr %86, align 4, !tbaa !9
  %88 = load i32, ptr %14, align 4, !tbaa !9
  %89 = add i32 %88, %87
  store i32 %89, ptr %14, align 4, !tbaa !9
  br label %90

90:                                               ; preds = %83
  %91 = load i32, ptr %18, align 4, !tbaa !9
  %92 = add nsw i32 %91, 1
  store i32 %92, ptr %18, align 4, !tbaa !9
  br label %80, !llvm.loop !17

93:                                               ; preds = %80
  %94 = load i32, ptr %14, align 4, !tbaa !9
  %95 = add i32 %94, 8
  %96 = udiv i32 %95, 16
  store i32 %96, ptr %14, align 4, !tbaa !9
  br label %97

97:                                               ; preds = %93, %76
  %98 = load i32, ptr %14, align 4, !tbaa !9
  %99 = call i32 @_Rice_DecodeWord(i32 noundef %98, ptr noundef %11)
  store i32 %99, ptr %13, align 4, !tbaa !9
  %100 = load ptr, ptr %7, align 8, !tbaa !5
  %101 = load i32, ptr %12, align 4, !tbaa !9
  %102 = load i32, ptr %10, align 4, !tbaa !9
  %103 = load i32, ptr %13, align 4, !tbaa !9
  call void @_Rice_WriteWord(ptr noundef %100, i32 noundef %101, i32 noundef %102, i32 noundef %103)
  %104 = load i32, ptr %13, align 4, !tbaa !9
  %105 = call i32 @_Rice_NumBits(i32 noundef %104)
  %106 = load i32, ptr %12, align 4, !tbaa !9
  %107 = urem i32 %106, 16
  %108 = zext i32 %107 to i64
  %109 = getelementptr inbounds [16 x i32], ptr %17, i64 0, i64 %108
  store i32 %105, ptr %109, align 4, !tbaa !9
  br label %110

110:                                              ; preds = %97
  %111 = load i32, ptr %12, align 4, !tbaa !9
  %112 = add i32 %111, 1
  store i32 %112, ptr %12, align 4, !tbaa !9
  br label %72, !llvm.loop !18

113:                                              ; preds = %72
  br label %114

114:                                              ; preds = %113, %70
  store i32 0, ptr %19, align 4
  br label %115

115:                                              ; preds = %114, %32, %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #2
  call void @llvm.lifetime.end.p0(i64 64, ptr %17) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #2
  %116 = load i32, ptr %19, align 4
  switch i32 %116, label %118 [
    i32 0, label %117
    i32 1, label %117
  ]

117:                                              ; preds = %115, %115
  ret void

118:                                              ; preds = %115
  unreachable
}

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_ReadBit(ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_WriteWord(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_DecodeWord(i32 noundef, ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 8}
!13 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = distinct !{!17, !15}
!18 = distinct !{!18, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.rice_bitstream_t = type { ptr, i32, i32 }

@switch.table.Rice_Uncompress = private unnamed_addr constant [8 x i32] [i32 8, i32 8, i32 16, i32 16, i32 8, i32 8, i32 32, i32 32], align 4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_InitBitstream(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_NumBits(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Rice_Uncompress(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #1 {
  %6 = alloca %struct.rice_bitstream_t, align 8
  %7 = alloca [16 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #3
  call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %7) #3
  %switch.tableidx = add i32 %4, -1
  %8 = icmp ult i32 %switch.tableidx, 8
  br i1 %8, label %switch.hole_check, label %.loopexit

switch.hole_check:                                ; preds = %5
  %switch.maskindex = trunc nuw i32 %switch.tableidx to i8
  %switch.shifted = lshr i8 -49, %switch.maskindex
  %switch.lobit = trunc i8 %switch.shifted to i1
  br i1 %switch.lobit, label %switch.lookup, label %.loopexit

switch.lookup:                                    ; preds = %switch.hole_check
  %9 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.Rice_Uncompress, i64 0, i64 %9
  %switch.load = load i32, ptr %switch.gep, align 4
  %10 = lshr exact i32 %switch.load, 3
  %11 = udiv i32 %3, %10
  %12 = icmp ugt i32 %10, %3
  br i1 %12, label %.loopexit, label %13

13:                                               ; preds = %switch.lookup
  call void @_Rice_InitBitstream(ptr noundef nonnull %6, ptr noundef %0, i32 noundef %2)
  %14 = load i8, ptr %0, align 1, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %6, i64 8
  store i32 8, ptr %15, align 8, !tbaa !8
  %16 = icmp eq i8 %14, 0
  br i1 %16, label %.preheader.preheader, label %.lr.ph.preheader

.preheader.preheader:                             ; preds = %13
  %umax56 = call i32 @llvm.umax.i32(i32 %11, i32 1)
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %22
  %.03451 = phi i32 [ %23, %22 ], [ 0, %.preheader.preheader ]
  br label %17

17:                                               ; preds = %.preheader, %17
  %.0.in50 = phi i32 [ %switch.load, %.preheader ], [ %.0, %17 ]
  %.03949 = phi i32 [ 0, %.preheader ], [ %20, %17 ]
  %.0 = add nsw i32 %.0.in50, -1
  %18 = shl i32 %.03949, 1
  %19 = call i32 @_Rice_ReadBit(ptr noundef nonnull %6)
  %20 = or i32 %19, %18
  %21 = icmp sgt i32 %.0.in50, 1
  br i1 %21, label %17, label %22, !llvm.loop !12

22:                                               ; preds = %17
  call void @_Rice_WriteWord(ptr noundef %1, i32 noundef %.03451, i32 noundef %4, i32 noundef %20)
  %23 = add nuw i32 %.03451, 1
  %exitcond57.not = icmp eq i32 %23, %umax56
  br i1 %exitcond57.not, label %.loopexit, label %.preheader, !llvm.loop !14

.lr.ph.preheader:                                 ; preds = %13
  %24 = zext i8 %14 to i32
  %umax = call i32 @llvm.umax.i32(i32 %11, i32 1)
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %29
  %.13548 = phi i32 [ %35, %29 ], [ 0, %.lr.ph.preheader ]
  %.03747 = phi i32 [ %.2, %29 ], [ %24, %.lr.ph.preheader ]
  %25 = icmp ugt i32 %.13548, 15
  br i1 %25, label %.preheader43.preheader, label %29

.preheader43.preheader:                           ; preds = %.lr.ph
  %26 = load <16 x i32>, ptr %7, align 16, !tbaa !15
  %27 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %26)
  %op.rdx = add i32 %27, 8
  %28 = lshr i32 %op.rdx, 4
  br label %29

29:                                               ; preds = %.preheader43.preheader, %.lr.ph
  %.2 = phi i32 [ %28, %.preheader43.preheader ], [ %.03747, %.lr.ph ]
  %30 = call i32 @_Rice_DecodeWord(i32 noundef %.2, ptr noundef nonnull %6)
  call void @_Rice_WriteWord(ptr noundef %1, i32 noundef %.13548, i32 noundef %4, i32 noundef %30)
  %31 = call i32 @_Rice_NumBits(i32 noundef %30)
  %32 = and i32 %.13548, 15
  %33 = zext nneg i32 %32 to i64
  %34 = getelementptr inbounds [16 x i32], ptr %7, i64 0, i64 %33
  store i32 %31, ptr %34, align 4, !tbaa !15
  %35 = add nuw i32 %.13548, 1
  %exitcond.not = icmp eq i32 %35, %umax
  br i1 %exitcond.not, label %.loopexit, label %.lr.ph, !llvm.loop !16

.loopexit:                                        ; preds = %29, %22, %switch.hole_check, %5, %switch.lookup
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %7) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #3
  ret void
}

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_ReadBit(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_WriteWord(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_DecodeWord(i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !11, i64 8}
!9 = !{!"", !10, i64 0, !11, i64 8, !11, i64 12}
!10 = !{!"any pointer", !6, i64 0}
!11 = !{!"int", !6, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}
!15 = !{!11, !11, i64 0}
!16 = distinct !{!16, !13}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass