; LLVM IR from xirc/cp-algorithm :: aoj/ALDS1/ALDS1A/main.ll (Z5solvev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@A = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z4dumpv() #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5solvev() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  call void @_Z4dumpv()
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #3
  store i32 1, ptr %1, align 4, !tbaa !5
  br label %4

4:                                                ; preds = %47, %0
  %5 = load i32, ptr %1, align 4, !tbaa !5
  %6 = sext i32 %5 to i64
  %7 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @A) #3
  %8 = icmp ult i64 %6, %7
  br i1 %8, label %10, label %9

9:                                                ; preds = %4
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #3
  br label %50

10:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  %11 = load i32, ptr %1, align 4, !tbaa !5
  %12 = sext i32 %11 to i64
  %13 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %12) #3
  %14 = load i32, ptr %13, align 4, !tbaa !5
  store i32 %14, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  %15 = load i32, ptr %1, align 4, !tbaa !5
  %16 = sub nsw i32 %15, 1
  store i32 %16, ptr %3, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %38, %10
  %18 = load i32, ptr %3, align 4, !tbaa !5
  %19 = icmp sge i32 %18, 0
  br i1 %19, label %20, label %27

20:                                               ; preds = %17
  %21 = load i32, ptr %3, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %22) #3
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %25 = load i32, ptr %2, align 4, !tbaa !5
  %26 = icmp sgt i32 %24, %25
  br label %27

27:                                               ; preds = %20, %17
  %28 = phi i1 [ false, %17 ], [ %26, %20 ]
  br i1 %28, label %29, label %41

29:                                               ; preds = %27
  %30 = load i32, ptr %3, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %31) #3
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = load i32, ptr %3, align 4, !tbaa !5
  %35 = add nsw i32 %34, 1
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %36) #3
  store i32 %33, ptr %37, align 4, !tbaa !5
  br label %38

38:                                               ; preds = %29
  %39 = load i32, ptr %3, align 4, !tbaa !5
  %40 = add nsw i32 %39, -1
  store i32 %40, ptr %3, align 4, !tbaa !5
  br label %17, !llvm.loop !9

41:                                               ; preds = %27
  %42 = load i32, ptr %2, align 4, !tbaa !5
  %43 = load i32, ptr %3, align 4, !tbaa !5
  %44 = add nsw i32 %43, 1
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %45) #3
  store i32 %42, ptr %46, align 4, !tbaa !5
  call void @_Z4dumpv()
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #3
  br label %47

47:                                               ; preds = %41
  %48 = load i32, ptr %1, align 4, !tbaa !5
  %49 = add nsw i32 %48, 1
  store i32 %49, ptr %1, align 4, !tbaa !5
  br label %4, !llvm.loop !11

50:                                               ; preds = %9
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@A = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z4dumpv() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5solvev() local_unnamed_addr #0 {
  tail call void @_Z4dumpv()
  %1 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @A) #2
  %2 = icmp ugt i64 %1, 1
  br i1 %2, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.critedge, %0
  ret void

.lr.ph:                                           ; preds = %0, %.critedge
  %indvars.iv = phi i64 [ %indvars.iv.next, %.critedge ], [ 1, %0 ]
  %3 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv) #2
  %4 = load i32, ptr %3, align 4, !tbaa !5
  br label %5

5:                                                ; preds = %.lr.ph, %10
  %indvars.iv18 = phi i64 [ %indvars.iv, %.lr.ph ], [ %indvars.iv.next19, %10 ]
  %indvars.iv.next19 = add nsw i64 %indvars.iv18, -1
  %6 = and i64 %indvars.iv.next19, 4294967295
  %7 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %6) #2
  %8 = load i32, ptr %7, align 4, !tbaa !5
  %9 = icmp sgt i32 %8, %4
  br i1 %9, label %10, label %.critedge

10:                                               ; preds = %5
  %11 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %6) #2
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv18) #2
  store i32 %12, ptr %13, align 4, !tbaa !5
  %14 = icmp sgt i64 %indvars.iv18, 1
  br i1 %14, label %5, label %.critedge, !llvm.loop !9

.critedge:                                        ; preds = %10, %5
  %.0.in.lcssa = phi i64 [ 0, %10 ], [ %indvars.iv18, %5 ]
  %sext = shl i64 %.0.in.lcssa, 32
  %15 = ashr exact i64 %sext, 32
  %16 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %15) #2
  store i32 %4, ptr %16, align 4, !tbaa !5
  tail call void @_Z4dumpv()
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %17 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @A) #2
  %18 = icmp ugt i64 %17, %indvars.iv.next
  br i1 %18, label %.lr.ph, label %._crit_edge, !llvm.loop !11
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass