; LLVM IR from Nigh/Basic-Compression-Library :: src (rice)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.rice_bitstream_t = type { ptr, i32, i32 }

; Function Attrs: nounwind uwtable
define dso_local i32 @Rice_Compress(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %struct.rice_bitstream_t, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca [16 x i32], align 16
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.start.p0(i64 64, ptr %17) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #2
  %20 = load i32, ptr %9, align 4, !tbaa !9
  switch i32 %20, label %24 [
    i32 1, label %21
    i32 2, label %21
    i32 3, label %22
    i32 4, label %22
    i32 7, label %23
    i32 8, label %23
  ]

21:                                               ; preds = %4, %4
  store i32 8, ptr %15, align 4, !tbaa !9
  br label %25

22:                                               ; preds = %4, %4
  store i32 16, ptr %15, align 4, !tbaa !9
  br label %25

23:                                               ; preds = %4, %4
  store i32 32, ptr %15, align 4, !tbaa !9
  br label %25

24:                                               ; preds = %4
  store i32 0, ptr %5, align 4
  store i32 1, ptr %19, align 4
  br label %163

25:                                               ; preds = %23, %22, %21
  %26 = load i32, ptr %8, align 4, !tbaa !9
  %27 = load i32, ptr %15, align 4, !tbaa !9
  %28 = lshr i32 %27, 3
  %29 = udiv i32 %26, %28
  store i32 %29, ptr %16, align 4, !tbaa !9
  %30 = load i32, ptr %16, align 4, !tbaa !9
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %33

32:                                               ; preds = %25
  store i32 0, ptr %5, align 4
  store i32 1, ptr %19, align 4
  br label %163

33:                                               ; preds = %25
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = add i32 %35, 1
  call void @_Rice_InitBitstream(ptr noundef %10, ptr noundef %34, i32 noundef %36)
  store i32 0, ptr %13, align 4, !tbaa !9
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %37

37:                                               ; preds = %55, %33
  %38 = load i32, ptr %11, align 4, !tbaa !9
  %39 = icmp ult i32 %38, 16
  br i1 %39, label %40, label %44

40:                                               ; preds = %37
  %41 = load i32, ptr %11, align 4, !tbaa !9
  %42 = load i32, ptr %16, align 4, !tbaa !9
  %43 = icmp ult i32 %41, %42
  br label %44

44:                                               ; preds = %40, %37
  %45 = phi i1 [ false, %37 ], [ %43, %40 ]
  br i1 %45, label %46, label %58

46:                                               ; preds = %44
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = load i32, ptr %11, align 4, !tbaa !9
  %49 = load i32, ptr %9, align 4, !tbaa !9
  %50 = call i32 @_Rice_ReadWord(ptr noundef %47, i32 noundef %48, i32 noundef %49)
  %51 = call i32 @_Rice_NumBits(i32 noundef %50)
  store i32 %51, ptr %14, align 4, !tbaa !9
  %52 = load i32, ptr %14, align 4, !tbaa !9
  %53 = load i32, ptr %13, align 4, !tbaa !9
  %54 = add i32 %53, %52
  store i32 %54, ptr %13, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %46
  %56 = load i32, ptr %11, align 4, !tbaa !9
  %57 = add i32 %56, 1
  store i32 %57, ptr %11, align 4, !tbaa !9
  br label %37, !llvm.loop !11

58:                                               ; preds = %44
  %59 = load i32, ptr %13, align 4, !tbaa !9
  %60 = load i32, ptr %11, align 4, !tbaa !9
  %61 = lshr i32 %60, 1
  %62 = add i32 %59, %61
  %63 = load i32, ptr %11, align 4, !tbaa !9
  %64 = udiv i32 %62, %63
  store i32 %64, ptr %13, align 4, !tbaa !9
  %65 = load i32, ptr %13, align 4, !tbaa !9
  %66 = icmp eq i32 %65, 0
  br i1 %66, label %67, label %68

67:                                               ; preds = %58
  store i32 1, ptr %13, align 4, !tbaa !9
  br label %68

68:                                               ; preds = %67, %58
  %69 = load i32, ptr %13, align 4, !tbaa !9
  %70 = trunc i32 %69 to i8
  %71 = load ptr, ptr %7, align 8, !tbaa !5
  %72 = getelementptr inbounds i8, ptr %71, i64 0
  store i8 %70, ptr %72, align 1, !tbaa !13
  %73 = getelementptr inbounds %struct.rice_bitstream_t, ptr %10, i32 0, i32 1
  store i32 8, ptr %73, align 8, !tbaa !14
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %74

74:                                               ; preds = %120, %68
  %75 = load i32, ptr %11, align 4, !tbaa !9
  %76 = load i32, ptr %16, align 4, !tbaa !9
  %77 = icmp ult i32 %75, %76
  br i1 %77, label %78, label %84

78:                                               ; preds = %74
  %79 = getelementptr inbounds %struct.rice_bitstream_t, ptr %10, i32 0, i32 1
  %80 = load i32, ptr %79, align 8, !tbaa !14
  %81 = lshr i32 %80, 3
  %82 = load i32, ptr %8, align 4, !tbaa !9
  %83 = icmp ule i32 %81, %82
  br label %84

84:                                               ; preds = %78, %74
  %85 = phi i1 [ false, %74 ], [ %83, %78 ]
  br i1 %85, label %86, label %123

86:                                               ; preds = %84
  %87 = load i32, ptr %11, align 4, !tbaa !9
  %88 = icmp uge i32 %87, 16
  br i1 %88, label %89, label %107

89:                                               ; preds = %86
  store i32 0, ptr %13, align 4, !tbaa !9
  store i32 0, ptr %18, align 4, !tbaa !9
  br label %90

90:                                               ; preds = %100, %89
  %91 = load i32, ptr %18, align 4, !tbaa !9
  %92 = icmp slt i32 %91, 16
  br i1 %92, label %93, label %103

93:                                               ; preds = %90
  %94 = load i32, ptr %18, align 4, !tbaa !9
  %95 = sext i32 %94 to i64
  %96 = getelementptr inbounds [16 x i32], ptr %17, i64 0, i64 %95
  %97 = load i32, ptr %96, align 4, !tbaa !9
  %98 = load i32, ptr %13, align 4, !tbaa !9
  %99 = add i32 %98, %97
  store i32 %99, ptr %13, align 4, !tbaa !9
  br label %100

100:                                              ; preds = %93
  %101 = load i32, ptr %18, align 4, !tbaa !9
  %102 = add nsw i32 %101, 1
  store i32 %102, ptr %18, align 4, !tbaa !9
  br label %90, !llvm.loop !16

103:                                              ; preds = %90
  %104 = load i32, ptr %13, align 4, !tbaa !9
  %105 = add i32 %104, 8
  %106 = udiv i32 %105, 16
  store i32 %106, ptr %13, align 4, !tbaa !9
  br label %107

107:                                              ; preds = %103, %86
  %108 = load ptr, ptr %6, align 8, !tbaa !5
  %109 = load i32, ptr %11, align 4, !tbaa !9
  %110 = load i32, ptr %9, align 4, !tbaa !9
  %111 = call i32 @_Rice_ReadWord(ptr noundef %108, i32 noundef %109, i32 noundef %110)
  store i32 %111, ptr %12, align 4, !tbaa !9
  %112 = load i32, ptr %12, align 4, !tbaa !9
  %113 = load i32, ptr %13, align 4, !tbaa !9
  call void @_Rice_EncodeWord(i32 noundef %112, i32 noundef %113, ptr noundef %10)
  %114 = load i32, ptr %12, align 4, !tbaa !9
  %115 = call i32 @_Rice_NumBits(i32 noundef %114)
  %116 = load i32, ptr %11, align 4, !tbaa !9
  %117 = urem i32 %116, 16
  %118 = zext i32 %117 to i64
  %119 = getelementptr inbounds [16 x i32], ptr %17, i64 0, i64 %118
  store i32 %115, ptr %119, align 4, !tbaa !9
  br label %120

120:                                              ; preds = %107
  %121 = load i32, ptr %11, align 4, !tbaa !9
  %122 = add i32 %121, 1
  store i32 %122, ptr %11, align 4, !tbaa !9
  br label %74, !llvm.loop !17

123:                                              ; preds = %84
  %124 = load i32, ptr %11, align 4, !tbaa !9
  %125 = load i32, ptr %16, align 4, !tbaa !9
  %126 = icmp ult i32 %124, %125
  br i1 %126, label %127, label %158

127:                                              ; preds = %123
  %128 = load ptr, ptr %7, align 8, !tbaa !5
  %129 = getelementptr inbounds i8, ptr %128, i64 0
  store i8 0, ptr %129, align 1, !tbaa !13
  %130 = getelementptr inbounds %struct.rice_bitstream_t, ptr %10, i32 0, i32 1
  store i32 8, ptr %130, align 8, !tbaa !14
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %131

131:                                              ; preds = %154, %127
  %132 = load i32, ptr %11, align 4, !tbaa !9
  %133 = load i32, ptr %16, align 4, !tbaa !9
  %134 = icmp ult i32 %132, %133
  br i1 %134, label %135, label %157

135:                                              ; preds = %131
  %136 = load ptr, ptr %6, align 8, !tbaa !5
  %137 = load i32, ptr %11, align 4, !tbaa !9
  %138 = load i32, ptr %9, align 4, !tbaa !9
  %139 = call i32 @_Rice_ReadWord(ptr noundef %136, i32 noundef %137, i32 noundef %138)
  store i32 %139, ptr %12, align 4, !tbaa !9
  %140 = load i32, ptr %15, align 4, !tbaa !9
  %141 = sub i32 %140, 1
  store i32 %141, ptr %18, align 4, !tbaa !9
  br label %142

142:                                              ; preds = %150, %135
  %143 = load i32, ptr %18, align 4, !tbaa !9
  %144 = icmp sge i32 %143, 0
  br i1 %144, label %145, label %153

145:                                              ; preds = %142
  %146 = load i32, ptr %12, align 4, !tbaa !9
  %147 = load i32, ptr %18, align 4, !tbaa !9
  %148 = lshr i32 %146, %147
  %149 = and i32 %148, 1
  call void @_Rice_WriteBit(ptr noundef %10, i32 noundef %149)
  br label %150

150:                                              ; preds = %145
  %151 = load i32, ptr %18, align 4, !tbaa !9
  %152 = add nsw i32 %151, -1
  store i32 %152, ptr %18, align 4, !tbaa !9
  br label %142, !llvm.loop !18

153:                                              ; preds = %142
  br label %154

154:                                              ; preds = %153
  %155 = load i32, ptr %11, align 4, !tbaa !9
  %156 = add i32 %155, 1
  store i32 %156, ptr %11, align 4, !tbaa !9
  br label %131, !llvm.loop !19

157:                                              ; preds = %131
  br label %158

158:                                              ; preds = %157, %123
  %159 = getelementptr inbounds %struct.rice_bitstream_t, ptr %10, i32 0, i32 1
  %160 = load i32, ptr %159, align 8, !tbaa !14
  %161 = add i32 %160, 7
  %162 = lshr i32 %161, 3
  store i32 %162, ptr %5, align 4
  store i32 1, ptr %19, align 4
  br label %163

163:                                              ; preds = %158, %32, %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #2
  call void @llvm.lifetime.end.p0(i64 64, ptr %17) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 16, ptr %10) #2
  %164 = load i32, ptr %5, align 4
  ret i32 %164
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_InitBitstream(ptr noundef, ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_NumBits(i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_ReadWord(ptr noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_EncodeWord(i32 noundef, i32 noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_WriteBit(ptr noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !10, i64 8}
!15 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.rice_bitstream_t = type { ptr, i32, i32 }

@switch.table.Rice_Compress = private unnamed_addr constant [8 x i32] [i32 8, i32 8, i32 16, i32 16, i32 8, i32 8, i32 32, i32 32], align 4

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 536870912) i32 @Rice_Compress(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = alloca %struct.rice_bitstream_t, align 8
  %6 = alloca [16 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #3
  call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %6) #3
  %switch.tableidx = add i32 %3, -1
  %7 = icmp ult i32 %switch.tableidx, 8
  br i1 %7, label %switch.hole_check, label %48

switch.hole_check:                                ; preds = %4
  %switch.maskindex = trunc nuw i32 %switch.tableidx to i8
  %switch.shifted = lshr i8 -49, %switch.maskindex
  %switch.lobit = trunc i8 %switch.shifted to i1
  br i1 %switch.lobit, label %switch.lookup, label %48

switch.lookup:                                    ; preds = %switch.hole_check
  %8 = zext nneg i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.Rice_Compress, i64 0, i64 %8
  %switch.load = load i32, ptr %switch.gep, align 4
  %9 = lshr exact i32 %switch.load, 3
  %10 = udiv i32 %2, %9
  %11 = icmp ugt i32 %9, %2
  br i1 %11, label %48, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %switch.lookup
  %12 = add i32 %2, 1
  call void @_Rice_InitBitstream(ptr noundef nonnull %5, ptr noundef %1, i32 noundef %12)
  %invariant.umin = call i32 @llvm.umin.i32(i32 %10, i32 16)
  %umax = call i32 @llvm.umax.i32(i32 %invariant.umin, i32 1)
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %.05461 = phi i32 [ %16, %.lr.ph ], [ 0, %.lr.ph.preheader ]
  %.05660 = phi i32 [ %15, %.lr.ph ], [ 0, %.lr.ph.preheader ]
  %13 = call i32 @_Rice_ReadWord(ptr noundef %0, i32 noundef %.05461, i32 noundef %3)
  %14 = call i32 @_Rice_NumBits(i32 noundef %13)
  %15 = add i32 %14, %.05660
  %16 = add nuw nsw i32 %.05461, 1
  %exitcond.not = icmp eq i32 %16, %umax
  br i1 %exitcond.not, label %.lr.ph68.preheader, label %.lr.ph, !llvm.loop !5

.lr.ph68.preheader:                               ; preds = %.lr.ph
  %17 = lshr i32 %16, 1
  %18 = add i32 %17, %15
  %19 = udiv i32 %18, %16
  %.not = icmp ult i32 %.05461, %18
  %spec.store.select = select i1 %.not, i32 %19, i32 1
  %20 = trunc i32 %spec.store.select to i8
  store i8 %20, ptr %1, align 1, !tbaa !7
  %21 = getelementptr inbounds i8, ptr %5, i64 8
  store i32 8, ptr %21, align 8, !tbaa !10
  br label %.lr.ph68

.lr.ph68:                                         ; preds = %.lr.ph68.preheader, %26
  %.15566 = phi i32 [ %32, %26 ], [ 0, %.lr.ph68.preheader ]
  %.15765 = phi i32 [ %.3, %26 ], [ %spec.store.select, %.lr.ph68.preheader ]
  %22 = icmp ugt i32 %.15566, 15
  br i1 %22, label %.preheader.preheader, label %26

.preheader.preheader:                             ; preds = %.lr.ph68
  %23 = load <16 x i32>, ptr %6, align 16, !tbaa !14
  %24 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %23)
  %op.rdx = add i32 %24, 8
  %25 = lshr i32 %op.rdx, 4
  br label %26

26:                                               ; preds = %.preheader.preheader, %.lr.ph68
  %.3 = phi i32 [ %25, %.preheader.preheader ], [ %.15765, %.lr.ph68 ]
  %27 = call i32 @_Rice_ReadWord(ptr noundef %0, i32 noundef %.15566, i32 noundef %3)
  call void @_Rice_EncodeWord(i32 noundef %27, i32 noundef %.3, ptr noundef nonnull %5)
  %28 = call i32 @_Rice_NumBits(i32 noundef %27)
  %29 = and i32 %.15566, 15
  %30 = zext nneg i32 %29 to i64
  %31 = getelementptr inbounds [16 x i32], ptr %6, i64 0, i64 %30
  store i32 %28, ptr %31, align 4, !tbaa !14
  %32 = add nuw i32 %.15566, 1
  %33 = icmp ult i32 %32, %10
  %34 = load i32, ptr %21, align 8
  %35 = lshr i32 %34, 3
  %36 = icmp ule i32 %35, %2
  %37 = select i1 %33, i1 %36, i1 false
  br i1 %37, label %.lr.ph68, label %._crit_edge69, !llvm.loop !15

._crit_edge69:                                    ; preds = %26
  br i1 %33, label %.lr.ph74.preheader, label %.loopexit

.lr.ph74.preheader:                               ; preds = %._crit_edge69
  store i8 0, ptr %1, align 1, !tbaa !7
  store i32 8, ptr %21, align 8, !tbaa !10
  br label %.lr.ph74

.lr.ph74:                                         ; preds = %.lr.ph74.preheader, %43
  %.272 = phi i32 [ %44, %43 ], [ 0, %.lr.ph74.preheader ]
  %38 = call i32 @_Rice_ReadWord(ptr noundef %0, i32 noundef %.272, i32 noundef %3)
  br label %39

39:                                               ; preds = %.lr.ph74, %39
  %.1.in71 = phi i32 [ %switch.load, %.lr.ph74 ], [ %.1, %39 ]
  %.1 = add nsw i32 %.1.in71, -1
  %40 = lshr i32 %38, %.1
  %41 = and i32 %40, 1
  call void @_Rice_WriteBit(ptr noundef nonnull %5, i32 noundef %41)
  %42 = icmp sgt i32 %.1.in71, 1
  br i1 %42, label %39, label %43, !llvm.loop !16

43:                                               ; preds = %39
  %44 = add nuw i32 %.272, 1
  %exitcond82.not = icmp eq i32 %44, %10
  br i1 %exitcond82.not, label %.loopexit.loopexit, label %.lr.ph74, !llvm.loop !17

.loopexit.loopexit:                               ; preds = %43
  %.pre = load i32, ptr %21, align 8, !tbaa !10
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.loopexit, %._crit_edge69
  %45 = phi i32 [ %.pre, %.loopexit.loopexit ], [ %34, %._crit_edge69 ]
  %46 = add i32 %45, 7
  %47 = lshr i32 %46, 3
  br label %48

48:                                               ; preds = %switch.hole_check, %4, %switch.lookup, %.loopexit
  %.052 = phi i32 [ %47, %.loopexit ], [ 0, %4 ], [ 0, %switch.lookup ], [ 0, %switch.hole_check ]
  call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %6) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #3
  ret i32 %.052
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_InitBitstream(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_NumBits(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @_Rice_ReadWord(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_EncodeWord(i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @_Rice_WriteBit(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!11, !13, i64 8}
!11 = !{!"", !12, i64 0, !13, i64 8, !13, i64 12}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"int", !8, i64 0}
!14 = !{!13, !13, i64 0}
!15 = distinct !{!15, !6}
!16 = distinct !{!16, !6}
!17 = distinct !{!17, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass