; LLVM IR from xirc/cp-algorithm :: codeforces/GYM/102694/C/main.ll (Z10edge_countii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@M = external dso_local global i32, align 4
@parents = external dso_local global %"class.std::vector", align 8
@edges = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z11is_ancestorii(i32 noundef, i32 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z10edge_countii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  %9 = load i32, ptr %4, align 4, !tbaa !5
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = icmp eq i32 %9, %10
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  store i32 0, ptr %3, align 4
  br label %104

13:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %14 = load i32, ptr @M, align 4, !tbaa !5
  %15 = sub nsw i32 %14, 1
  store i32 %15, ptr %7, align 4, !tbaa !5
  br label %16

16:                                               ; preds = %75, %13
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = icmp sge i32 %17, 0
  br i1 %18, label %20, label %19

19:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  br label %78

20:                                               ; preds = %16
  %21 = load i32, ptr %5, align 4, !tbaa !5
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %23) #2
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %26) #2
  %28 = load i32, ptr %27, align 4, !tbaa !5
  %29 = call noundef zeroext i1 @_Z11is_ancestorii(i32 noundef %21, i32 noundef %28)
  br i1 %29, label %47, label %30

30:                                               ; preds = %20
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = sext i32 %31 to i64
  %33 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @edges, i64 noundef %32) #2
  %34 = load i32, ptr %7, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %35) #2
  %37 = load i32, ptr %36, align 4, !tbaa !5
  %38 = load i32, ptr %6, align 4, !tbaa !5
  %39 = add nsw i32 %38, %37
  store i32 %39, ptr %6, align 4, !tbaa !5
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %41) #2
  %43 = load i32, ptr %7, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %44) #2
  %46 = load i32, ptr %45, align 4, !tbaa !5
  store i32 %46, ptr %4, align 4, !tbaa !5
  br label %47

47:                                               ; preds = %30, %20
  %48 = load i32, ptr %4, align 4, !tbaa !5
  %49 = load i32, ptr %5, align 4, !tbaa !5
  %50 = sext i32 %49 to i64
  %51 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %50) #2
  %52 = load i32, ptr %7, align 4, !tbaa !5
  %53 = sext i32 %52 to i64
  %54 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef %53) #2
  %55 = load i32, ptr %54, align 4, !tbaa !5
  %56 = call noundef zeroext i1 @_Z11is_ancestorii(i32 noundef %48, i32 noundef %55)
  br i1 %56, label %74, label %57

57:                                               ; preds = %47
  %58 = load i32, ptr %5, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @edges, i64 noundef %59) #2
  %61 = load i32, ptr %7, align 4, !tbaa !5
  %62 = sext i32 %61 to i64
  %63 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %62) #2
  %64 = load i32, ptr %63, align 4, !tbaa !5
  %65 = load i32, ptr %6, align 4, !tbaa !5
  %66 = add nsw i32 %65, %64
  store i32 %66, ptr %6, align 4, !tbaa !5
  %67 = load i32, ptr %5, align 4, !tbaa !5
  %68 = sext i32 %67 to i64
  %69 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %68) #2
  %70 = load i32, ptr %7, align 4, !tbaa !5
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %69, i64 noundef %71) #2
  %73 = load i32, ptr %72, align 4, !tbaa !5
  store i32 %73, ptr %5, align 4, !tbaa !5
  br label %74

74:                                               ; preds = %57, %47
  br label %75

75:                                               ; preds = %74
  %76 = load i32, ptr %7, align 4, !tbaa !5
  %77 = add nsw i32 %76, -1
  store i32 %77, ptr %7, align 4, !tbaa !5
  br label %16, !llvm.loop !9

78:                                               ; preds = %19
  %79 = load i32, ptr %4, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %80) #2
  %82 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef 0) #2
  %83 = load i32, ptr %82, align 4, !tbaa !5
  %84 = load i32, ptr %5, align 4, !tbaa !5
  %85 = icmp eq i32 %83, %84
  br i1 %85, label %86, label %89

86:                                               ; preds = %78
  %87 = load i32, ptr %6, align 4, !tbaa !5
  %88 = add nsw i32 %87, 1
  store i32 %88, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %103

89:                                               ; preds = %78
  %90 = load i32, ptr %5, align 4, !tbaa !5
  %91 = sext i32 %90 to i64
  %92 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %91) #2
  %93 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %92, i64 noundef 0) #2
  %94 = load i32, ptr %93, align 4, !tbaa !5
  %95 = load i32, ptr %4, align 4, !tbaa !5
  %96 = icmp eq i32 %94, %95
  br i1 %96, label %97, label %100

97:                                               ; preds = %89
  %98 = load i32, ptr %6, align 4, !tbaa !5
  %99 = add nsw i32 %98, 1
  store i32 %99, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %103

100:                                              ; preds = %89
  %101 = load i32, ptr %6, align 4, !tbaa !5
  %102 = add nsw i32 %101, 2
  store i32 %102, ptr %3, align 4
  store i32 1, ptr %8, align 4
  br label %103

103:                                              ; preds = %100, %97, %86
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %104

104:                                              ; preds = %103, %12
  %105 = load i32, ptr %3, align 4
  ret i32 %105
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@M = external dso_local local_unnamed_addr global i32, align 4
@parents = external dso_local global %"class.std::vector", align 8
@edges = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z11is_ancestorii(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef range(i32 -2147483647, -2147483648) i32 @_Z10edge_countii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = icmp eq i32 %0, %1
  br i1 %3, label %54, label %4

4:                                                ; preds = %2
  %5 = load i32, ptr @M, align 4, !tbaa !5
  %6 = icmp sgt i32 %5, 0
  br i1 %6, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %4
  %7 = zext nneg i32 %5 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %40, %4
  %.031.lcssa = phi i32 [ %0, %4 ], [ %.132, %40 ]
  %.029.lcssa = phi i32 [ %1, %4 ], [ %.130, %40 ]
  %.028.lcssa = phi i32 [ 0, %4 ], [ %.2, %40 ]
  %8 = sext i32 %.031.lcssa to i64
  %9 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %8) #1
  %10 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef 0) #1
  %11 = load i32, ptr %10, align 4, !tbaa !5
  %12 = icmp eq i32 %11, %.029.lcssa
  br i1 %12, label %42, label %44

.lr.ph:                                           ; preds = %.lr.ph.preheader, %40
  %indvars.iv = phi i64 [ %7, %.lr.ph.preheader ], [ %indvars.iv.next, %40 ]
  %.02840 = phi i32 [ 0, %.lr.ph.preheader ], [ %.2, %40 ]
  %.02939 = phi i32 [ %1, %.lr.ph.preheader ], [ %.130, %40 ]
  %.03138 = phi i32 [ %0, %.lr.ph.preheader ], [ %.132, %40 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %13 = sext i32 %.03138 to i64
  %14 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %13) #1
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %indvars.iv.next) #1
  %16 = load i32, ptr %15, align 4, !tbaa !5
  %17 = tail call noundef zeroext i1 @_Z11is_ancestorii(i32 noundef %.02939, i32 noundef %16)
  br i1 %17, label %26, label %18

18:                                               ; preds = %.lr.ph
  %19 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @edges, i64 noundef %13) #1
  %20 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %indvars.iv.next) #1
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = add nsw i32 %21, %.02840
  %23 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %13) #1
  %24 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %indvars.iv.next) #1
  %25 = load i32, ptr %24, align 4, !tbaa !5
  br label %26

26:                                               ; preds = %18, %.lr.ph
  %.132 = phi i32 [ %.03138, %.lr.ph ], [ %25, %18 ]
  %.1 = phi i32 [ %.02840, %.lr.ph ], [ %22, %18 ]
  %27 = sext i32 %.02939 to i64
  %28 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %27) #1
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %indvars.iv.next) #1
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %31 = tail call noundef zeroext i1 @_Z11is_ancestorii(i32 noundef %.132, i32 noundef %30)
  br i1 %31, label %40, label %32

32:                                               ; preds = %26
  %33 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @edges, i64 noundef %27) #1
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %indvars.iv.next) #1
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = add nsw i32 %35, %.1
  %37 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %27) #1
  %38 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %indvars.iv.next) #1
  %39 = load i32, ptr %38, align 4, !tbaa !5
  br label %40

40:                                               ; preds = %26, %32
  %.130 = phi i32 [ %.02939, %26 ], [ %39, %32 ]
  %.2 = phi i32 [ %.1, %26 ], [ %36, %32 ]
  %41 = icmp ugt i64 %indvars.iv, 1
  br i1 %41, label %.lr.ph, label %._crit_edge, !llvm.loop !9

42:                                               ; preds = %._crit_edge
  %43 = add nsw i32 %.028.lcssa, 1
  br label %54

44:                                               ; preds = %._crit_edge
  %45 = sext i32 %.029.lcssa to i64
  %46 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @parents, i64 noundef %45) #1
  %47 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef 0) #1
  %48 = load i32, ptr %47, align 4, !tbaa !5
  %49 = icmp eq i32 %48, %.031.lcssa
  br i1 %49, label %50, label %52

50:                                               ; preds = %44
  %51 = add nsw i32 %.028.lcssa, 1
  br label %54

52:                                               ; preds = %44
  %53 = add nsw i32 %.028.lcssa, 2
  br label %54

54:                                               ; preds = %42, %50, %52, %2
  %.134 = phi i32 [ 0, %2 ], [ %43, %42 ], [ %51, %50 ], [ %53, %52 ]
  ret i32 %.134
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass