; LLVM IR from Stephane-D/SGDK :: src (dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Z80_releaseBus() #1

declare void @VDP_setAutoInc(i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: noinline nounwind uwtable
define dso_local void @DMA_doDmaFast(i8 noundef zeroext %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef signext %4) #2 {
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca [1 x i64], align 8
  %15 = alloca ptr, align 8
  %16 = alloca i8, align 1
  store i8 %0, ptr %6, align 1, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !8
  store i16 %2, ptr %8, align 2, !tbaa !10
  store i16 %3, ptr %9, align 2, !tbaa !10
  store i16 %4, ptr %10, align 2, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %16) #3
  %17 = load ptr, ptr %7, align 8, !tbaa !8
  %18 = ptrtoint ptr %17 to i64
  store i64 %18, ptr %13, align 8, !tbaa !12
  %19 = load i16, ptr %10, align 2, !tbaa !10
  %20 = sext i16 %19 to i32
  %21 = icmp ne i32 %20, -1
  br i1 %21, label %22, label %25

22:                                               ; preds = %5
  %23 = load i16, ptr %10, align 2, !tbaa !10
  %24 = trunc i16 %23 to i8
  call void @VDP_setAutoInc(i8 noundef zeroext %24)
  br label %25

25:                                               ; preds = %22, %5
  store ptr inttoptr (i64 12582916 to ptr), ptr %11, align 8, !tbaa !8
  %26 = load i16, ptr %9, align 2, !tbaa !10
  %27 = zext i16 %26 to i32
  %28 = and i32 %27, 255
  %29 = add nsw i32 37632, %28
  %30 = trunc i32 %29 to i16
  %31 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %30, ptr %31, align 2, !tbaa !10
  %32 = load i16, ptr %9, align 2, !tbaa !10
  %33 = zext i16 %32 to i32
  %34 = ashr i32 %33, 8
  %35 = and i32 %34, 255
  %36 = add nsw i32 37888, %35
  %37 = trunc i32 %36 to i16
  %38 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %37, ptr %38, align 2, !tbaa !10
  %39 = load i64, ptr %13, align 8, !tbaa !12
  %40 = lshr i64 %39, 1
  store i64 %40, ptr %13, align 8, !tbaa !12
  %41 = load i64, ptr %13, align 8, !tbaa !12
  %42 = and i64 %41, 255
  %43 = add i64 38144, %42
  %44 = trunc i64 %43 to i16
  %45 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %44, ptr %45, align 2, !tbaa !10
  %46 = load i64, ptr %13, align 8, !tbaa !12
  %47 = lshr i64 %46, 8
  store i64 %47, ptr %13, align 8, !tbaa !12
  %48 = load i64, ptr %13, align 8, !tbaa !12
  %49 = and i64 %48, 255
  %50 = add i64 38400, %49
  %51 = trunc i64 %50 to i16
  %52 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %51, ptr %52, align 2, !tbaa !10
  %53 = load i64, ptr %13, align 8, !tbaa !12
  %54 = lshr i64 %53, 8
  store i64 %54, ptr %13, align 8, !tbaa !12
  %55 = load i64, ptr %13, align 8, !tbaa !12
  %56 = and i64 %55, 127
  %57 = add i64 38656, %56
  %58 = trunc i64 %57 to i16
  %59 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %58, ptr %59, align 2, !tbaa !10
  %60 = load i8, ptr %6, align 1, !tbaa !5
  %61 = zext i8 %60 to i32
  switch i32 %61, label %62 [
    i32 0, label %63
    i32 1, label %74
    i32 2, label %81
  ]

62:                                               ; preds = %25
  br label %63

63:                                               ; preds = %62, %25
  %64 = load i16, ptr %8, align 2, !tbaa !10
  %65 = zext i16 %64 to i64
  %66 = and i64 %65, 16383
  %67 = add i64 16384, %66
  %68 = shl i64 %67, 16
  %69 = load i16, ptr %8, align 2, !tbaa !10
  %70 = zext i16 %69 to i64
  %71 = lshr i64 %70, 14
  %72 = or i64 %71, 128
  %73 = add i64 %68, %72
  store i64 %73, ptr %12, align 8, !tbaa !12
  br label %88

74:                                               ; preds = %25
  %75 = load i16, ptr %8, align 2, !tbaa !10
  %76 = zext i16 %75 to i64
  %77 = and i64 %76, 127
  %78 = add i64 49152, %77
  %79 = shl i64 %78, 16
  %80 = add i64 %79, 128
  store i64 %80, ptr %12, align 8, !tbaa !12
  br label %88

81:                                               ; preds = %25
  %82 = load i16, ptr %8, align 2, !tbaa !10
  %83 = zext i16 %82 to i64
  %84 = and i64 %83, 127
  %85 = add i64 16384, %84
  %86 = shl i64 %85, 16
  %87 = add i64 %86, 144
  store i64 %87, ptr %12, align 8, !tbaa !12
  br label %88

88:                                               ; preds = %81, %74, %63
  %89 = load i64, ptr %12, align 8, !tbaa !12
  %90 = getelementptr inbounds [1 x i64], ptr %14, i64 0, i64 0
  store volatile i64 %89, ptr %90, align 8, !tbaa !12
  %91 = getelementptr inbounds [1 x i64], ptr %14, i64 0, i64 0
  store ptr %91, ptr %15, align 8, !tbaa !8
  %92 = load ptr, ptr %15, align 8, !tbaa !8
  %93 = getelementptr inbounds i16, ptr %92, i32 1
  store ptr %93, ptr %15, align 8, !tbaa !8
  %94 = load i16, ptr %92, align 2, !tbaa !10
  %95 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %94, ptr %95, align 2, !tbaa !10
  %96 = call zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext 0)
  store i8 %96, ptr %16, align 1, !tbaa !5
  %97 = load ptr, ptr %15, align 8, !tbaa !8
  %98 = load i16, ptr %97, align 2, !tbaa !10
  %99 = load ptr, ptr %11, align 8, !tbaa !8
  store volatile i16 %98, ptr %99, align 2, !tbaa !10
  %100 = load i8, ptr %16, align 1, !tbaa !5
  %101 = icmp ne i8 %100, 0
  br i1 %101, label %103, label %102

102:                                              ; preds = %88
  call void @Z80_releaseBus()
  br label %103

103:                                              ; preds = %102, %88
  call void @llvm.lifetime.end.p0(i64 1, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  ret void
}

declare zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !6, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"long", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Z80_releaseBus() local_unnamed_addr #1

declare void @VDP_setAutoInc(i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: noinline nounwind uwtable
define dso_local void @DMA_doDmaFast(i8 noundef zeroext %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef signext %4) local_unnamed_addr #2 {
  %.sroa.0 = alloca i64, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %.sroa.0)
  %6 = ptrtoint ptr %1 to i64
  %.not = icmp eq i16 %4, -1
  br i1 %.not, label %9, label %7

7:                                                ; preds = %5
  %8 = trunc i16 %4 to i8
  tail call void @VDP_setAutoInc(i8 noundef zeroext %8) #3
  br label %9

9:                                                ; preds = %7, %5
  %10 = and i16 %3, 255
  %11 = or disjoint i16 %10, -27904
  store volatile i16 %11, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %12 = lshr i16 %3, 8
  %13 = or disjoint i16 %12, -27648
  store volatile i16 %13, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %14 = trunc i64 %6 to i16
  %15 = lshr i16 %14, 1
  %16 = and i16 %15, 255
  %17 = or disjoint i16 %16, -27392
  store volatile i16 %17, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %18 = lshr i64 %6, 9
  %19 = trunc i64 %18 to i16
  %20 = and i16 %19, 255
  %21 = or disjoint i16 %20, -27136
  store volatile i16 %21, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %22 = lshr i64 %6, 17
  %23 = trunc i64 %22 to i16
  %24 = and i16 %23, 127
  %25 = or disjoint i16 %24, -26880
  store volatile i16 %25, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  switch i8 %0, label %26 [
    i8 2, label %39
    i8 1, label %33
  ]

26:                                               ; preds = %9
  %27 = zext i16 %2 to i64
  %28 = shl nuw nsw i64 %27, 16
  %29 = and i64 %28, 1073676288
  %30 = lshr i64 %27, 14
  %31 = or disjoint i64 %30, %29
  %32 = or disjoint i64 %31, 1073741952
  br label %45

33:                                               ; preds = %9
  %34 = and i16 %2, 127
  %35 = or disjoint i16 %34, -16384
  %36 = zext i16 %35 to i64
  %37 = shl nuw nsw i64 %36, 16
  %38 = or disjoint i64 %37, 128
  br label %45

39:                                               ; preds = %9
  %40 = and i16 %2, 127
  %41 = or disjoint i16 %40, 16384
  %42 = zext nneg i16 %41 to i64
  %43 = shl nuw nsw i64 %42, 16
  %44 = or disjoint i64 %43, 144
  br label %45

45:                                               ; preds = %39, %33, %26
  %.0 = phi i64 [ %32, %26 ], [ %38, %33 ], [ %44, %39 ]
  store volatile i64 %.0, ptr %.sroa.0, align 8, !tbaa !9
  %46 = trunc i64 %.0 to i16
  store volatile i16 %46, ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %47 = tail call zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext 0) #3
  %.sroa.0.2.sroa_idx = getelementptr inbounds i8, ptr %.sroa.0, i64 2
  %.sroa.0.2..sroa.0.2..sroa.0.2..sroa.0.2..sroa.0.2. = load i16, ptr %.sroa.0.2.sroa_idx, align 2, !tbaa !5
  store volatile i16 %.sroa.0.2..sroa.0.2..sroa.0.2..sroa.0.2..sroa.0.2., ptr inttoptr (i64 12582916 to ptr), align 4, !tbaa !5
  %.not27 = icmp eq i8 %47, 0
  br i1 %.not27, label %48, label %49

48:                                               ; preds = %45
  tail call void @Z80_releaseBus() #3
  br label %49

49:                                               ; preds = %48, %45
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %.sroa.0)
  ret void
}

declare zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass