; LLVM IR from Stephane-D/SGDK :: src (ym2612)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: noinline nounwind uwtable
define dso_local void @YM2612_reset() #0 {
  %1 = alloca i16, align 2
  %2 = alloca i16, align 2
  %3 = alloca i16, align 2
  %4 = alloca i16, align 2
  call void @llvm.lifetime.start.p0(i64 2, ptr %1) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %2) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %3) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %4) #4
  %5 = call zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext 1)
  %6 = zext i8 %5 to i16
  store i16 %6, ptr %4, align 2, !tbaa !5
  call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 34)
  call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 39)
  call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 43)
  call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  store i16 0, ptr %1, align 2, !tbaa !5
  br label %7

7:                                                ; preds = %65, %0
  %8 = load i16, ptr %1, align 2, !tbaa !5
  %9 = zext i16 %8 to i32
  %10 = icmp slt i32 %9, 2
  br i1 %10, label %11, label %68

11:                                               ; preds = %7
  store i16 0, ptr %2, align 2, !tbaa !5
  br label %12

12:                                               ; preds = %61, %11
  %13 = load i16, ptr %2, align 2, !tbaa !5
  %14 = zext i16 %13 to i32
  %15 = icmp slt i32 %14, 3
  br i1 %15, label %16, label %64

16:                                               ; preds = %12
  store i16 0, ptr %3, align 2, !tbaa !5
  br label %17

17:                                               ; preds = %57, %16
  %18 = load i16, ptr %3, align 2, !tbaa !5
  %19 = zext i16 %18 to i32
  %20 = icmp slt i32 %19, 4
  br i1 %20, label %21, label %60

21:                                               ; preds = %17
  %22 = load i16, ptr %1, align 2, !tbaa !5
  %23 = load i16, ptr %2, align 2, !tbaa !5
  %24 = trunc i16 %23 to i8
  %25 = load i16, ptr %3, align 2, !tbaa !5
  %26 = trunc i16 %25 to i8
  call void @writeSlotReg(i16 noundef zeroext %22, i8 noundef zeroext %24, i8 noundef zeroext %26, i8 noundef zeroext 48, i8 noundef zeroext 0)
  %27 = load i16, ptr %1, align 2, !tbaa !5
  %28 = load i16, ptr %2, align 2, !tbaa !5
  %29 = trunc i16 %28 to i8
  %30 = load i16, ptr %3, align 2, !tbaa !5
  %31 = trunc i16 %30 to i8
  call void @writeSlotReg(i16 noundef zeroext %27, i8 noundef zeroext %29, i8 noundef zeroext %31, i8 noundef zeroext 64, i8 noundef zeroext 127)
  %32 = load i16, ptr %1, align 2, !tbaa !5
  %33 = load i16, ptr %2, align 2, !tbaa !5
  %34 = trunc i16 %33 to i8
  %35 = load i16, ptr %3, align 2, !tbaa !5
  %36 = trunc i16 %35 to i8
  call void @writeSlotReg(i16 noundef zeroext %32, i8 noundef zeroext %34, i8 noundef zeroext %36, i8 noundef zeroext 80, i8 noundef zeroext 0)
  %37 = load i16, ptr %1, align 2, !tbaa !5
  %38 = load i16, ptr %2, align 2, !tbaa !5
  %39 = trunc i16 %38 to i8
  %40 = load i16, ptr %3, align 2, !tbaa !5
  %41 = trunc i16 %40 to i8
  call void @writeSlotReg(i16 noundef zeroext %37, i8 noundef zeroext %39, i8 noundef zeroext %41, i8 noundef zeroext 96, i8 noundef zeroext 0)
  %42 = load i16, ptr %1, align 2, !tbaa !5
  %43 = load i16, ptr %2, align 2, !tbaa !5
  %44 = trunc i16 %43 to i8
  %45 = load i16, ptr %3, align 2, !tbaa !5
  %46 = trunc i16 %45 to i8
  call void @writeSlotReg(i16 noundef zeroext %42, i8 noundef zeroext %44, i8 noundef zeroext %46, i8 noundef zeroext 112, i8 noundef zeroext 0)
  %47 = load i16, ptr %1, align 2, !tbaa !5
  %48 = load i16, ptr %2, align 2, !tbaa !5
  %49 = trunc i16 %48 to i8
  %50 = load i16, ptr %3, align 2, !tbaa !5
  %51 = trunc i16 %50 to i8
  call void @writeSlotReg(i16 noundef zeroext %47, i8 noundef zeroext %49, i8 noundef zeroext %51, i8 noundef zeroext -128, i8 noundef zeroext -1)
  %52 = load i16, ptr %1, align 2, !tbaa !5
  %53 = load i16, ptr %2, align 2, !tbaa !5
  %54 = trunc i16 %53 to i8
  %55 = load i16, ptr %3, align 2, !tbaa !5
  %56 = trunc i16 %55 to i8
  call void @writeSlotReg(i16 noundef zeroext %52, i8 noundef zeroext %54, i8 noundef zeroext %56, i8 noundef zeroext -112, i8 noundef zeroext 0)
  br label %57

57:                                               ; preds = %21
  %58 = load i16, ptr %3, align 2, !tbaa !5
  %59 = add i16 %58, 1
  store i16 %59, ptr %3, align 2, !tbaa !5
  br label %17, !llvm.loop !9

60:                                               ; preds = %17
  br label %61

61:                                               ; preds = %60
  %62 = load i16, ptr %2, align 2, !tbaa !5
  %63 = add i16 %62, 1
  store i16 %63, ptr %2, align 2, !tbaa !5
  br label %12, !llvm.loop !11

64:                                               ; preds = %12
  br label %65

65:                                               ; preds = %64
  %66 = load i16, ptr %1, align 2, !tbaa !5
  %67 = add i16 %66, 1
  store i16 %67, ptr %1, align 2, !tbaa !5
  br label %7, !llvm.loop !12

68:                                               ; preds = %7
  store i16 0, ptr %1, align 2, !tbaa !5
  br label %69

69:                                               ; preds = %101, %68
  %70 = load i16, ptr %1, align 2, !tbaa !5
  %71 = zext i16 %70 to i32
  %72 = icmp slt i32 %71, 2
  br i1 %72, label %73, label %104

73:                                               ; preds = %69
  store i16 0, ptr %2, align 2, !tbaa !5
  br label %74

74:                                               ; preds = %97, %73
  %75 = load i16, ptr %2, align 2, !tbaa !5
  %76 = zext i16 %75 to i32
  %77 = icmp slt i32 %76, 3
  br i1 %77, label %78, label %100

78:                                               ; preds = %74
  %79 = load i16, ptr %1, align 2, !tbaa !5
  %80 = load i16, ptr %2, align 2, !tbaa !5
  %81 = trunc i16 %80 to i8
  call void @writeChannelReg(i16 noundef zeroext %79, i8 noundef zeroext %81, i8 noundef zeroext -96, i8 noundef zeroext 0)
  %82 = load i16, ptr %1, align 2, !tbaa !5
  %83 = load i16, ptr %2, align 2, !tbaa !5
  %84 = trunc i16 %83 to i8
  call void @writeChannelReg(i16 noundef zeroext %82, i8 noundef zeroext %84, i8 noundef zeroext -92, i8 noundef zeroext 0)
  %85 = load i16, ptr %1, align 2, !tbaa !5
  %86 = load i16, ptr %2, align 2, !tbaa !5
  %87 = trunc i16 %86 to i8
  call void @writeChannelReg(i16 noundef zeroext %85, i8 noundef zeroext %87, i8 noundef zeroext -88, i8 noundef zeroext 0)
  %88 = load i16, ptr %1, align 2, !tbaa !5
  %89 = load i16, ptr %2, align 2, !tbaa !5
  %90 = trunc i16 %89 to i8
  call void @writeChannelReg(i16 noundef zeroext %88, i8 noundef zeroext %90, i8 noundef zeroext -84, i8 noundef zeroext 0)
  %91 = load i16, ptr %1, align 2, !tbaa !5
  %92 = load i16, ptr %2, align 2, !tbaa !5
  %93 = trunc i16 %92 to i8
  call void @writeChannelReg(i16 noundef zeroext %91, i8 noundef zeroext %93, i8 noundef zeroext -80, i8 noundef zeroext 0)
  %94 = load i16, ptr %1, align 2, !tbaa !5
  %95 = load i16, ptr %2, align 2, !tbaa !5
  %96 = trunc i16 %95 to i8
  call void @writeChannelReg(i16 noundef zeroext %94, i8 noundef zeroext %96, i8 noundef zeroext -76, i8 noundef zeroext -64)
  br label %97

97:                                               ; preds = %78
  %98 = load i16, ptr %2, align 2, !tbaa !5
  %99 = add i16 %98, 1
  store i16 %99, ptr %2, align 2, !tbaa !5
  br label %74, !llvm.loop !13

100:                                              ; preds = %74
  br label %101

101:                                              ; preds = %100
  %102 = load i16, ptr %1, align 2, !tbaa !5
  %103 = add i16 %102, 1
  store i16 %103, ptr %1, align 2, !tbaa !5
  br label %69, !llvm.loop !14

104:                                              ; preds = %69
  call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 40)
  store i16 0, ptr %2, align 2, !tbaa !5
  br label %105

105:                                              ; preds = %118, %104
  %106 = load i16, ptr %2, align 2, !tbaa !5
  %107 = zext i16 %106 to i32
  %108 = icmp slt i32 %107, 3
  br i1 %108, label %109, label %121

109:                                              ; preds = %105
  %110 = load i16, ptr %2, align 2, !tbaa !5
  %111 = zext i16 %110 to i32
  %112 = or i32 0, %111
  %113 = trunc i32 %112 to i8
  call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext %113)
  %114 = load i16, ptr %2, align 2, !tbaa !5
  %115 = zext i16 %114 to i32
  %116 = or i32 4, %115
  %117 = trunc i32 %116 to i8
  call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext %117)
  br label %118

118:                                              ; preds = %109
  %119 = load i16, ptr %2, align 2, !tbaa !5
  %120 = add i16 %119, 1
  store i16 %120, ptr %2, align 2, !tbaa !5
  br label %105, !llvm.loop !15

121:                                              ; preds = %105
  %122 = load i16, ptr %4, align 2, !tbaa !5
  %123 = icmp ne i16 %122, 0
  br i1 %123, label %125, label %124

124:                                              ; preds = %121
  call void @Z80_releaseBus()
  br label %125

125:                                              ; preds = %124, %121
  call void @llvm.lifetime.end.p0(i64 2, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %3) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %2) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %1) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext) #2

; Function Attrs: nounwind uwtable
declare dso_local void @YM2612_write(i16 noundef zeroext, i8 noundef zeroext) #3

; Function Attrs: nounwind uwtable
declare hidden void @writeSlotReg(i16 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) #3

; Function Attrs: nounwind uwtable
declare hidden void @writeChannelReg(i16 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) #3

declare void @Z80_releaseBus() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: noinline nounwind uwtable
define dso_local void @YM2612_reset() local_unnamed_addr #0 {
  %1 = tail call zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext 1) #3
  tail call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 34)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  tail call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 39)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  tail call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 43)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  br label %.preheader54

.preheader54:                                     ; preds = %0, %5
  %2 = phi i1 [ true, %0 ], [ false, %5 ]
  %.057 = phi i16 [ 0, %0 ], [ 1, %5 ]
  br label %.preheader53

.preheader53:                                     ; preds = %.preheader54, %.preheader53
  %.04956 = phi i16 [ 0, %.preheader54 ], [ %4, %.preheader53 ]
  %3 = trunc nuw i16 %.04956 to i8
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext 48, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext 64, i8 noundef zeroext 127)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext 80, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext 96, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext 112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext -128, i8 noundef zeroext -1)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 0, i8 noundef zeroext -112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext 48, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext 64, i8 noundef zeroext 127)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext 80, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext 96, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext 112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext -128, i8 noundef zeroext -1)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 1, i8 noundef zeroext -112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext 48, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext 64, i8 noundef zeroext 127)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext 80, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext 96, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext 112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext -128, i8 noundef zeroext -1)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 2, i8 noundef zeroext -112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext 48, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext 64, i8 noundef zeroext 127)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext 80, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext 96, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext 112, i8 noundef zeroext 0)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext -128, i8 noundef zeroext -1)
  tail call void @writeSlotReg(i16 noundef zeroext %.057, i8 noundef zeroext %3, i8 noundef zeroext 3, i8 noundef zeroext -112, i8 noundef zeroext 0)
  %4 = add nuw nsw i16 %.04956, 1
  %exitcond.not = icmp eq i16 %4, 3
  br i1 %exitcond.not, label %5, label %.preheader53, !llvm.loop !5

5:                                                ; preds = %.preheader53
  br i1 %2, label %.preheader54, label %.preheader.preheader, !llvm.loop !7

.preheader.preheader:                             ; preds = %5
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 1, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 0, i8 noundef zeroext 2, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 0, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 1, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -96, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -92, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -88, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -84, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -80, i8 noundef zeroext 0)
  tail call void @writeChannelReg(i16 noundef zeroext 1, i8 noundef zeroext 2, i8 noundef zeroext -76, i8 noundef zeroext -64)
  tail call void @YM2612_write(i16 noundef zeroext 0, i8 noundef zeroext 40)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 0)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 4)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 1)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 5)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 2)
  tail call void @YM2612_write(i16 noundef zeroext 1, i8 noundef zeroext 6)
  %.not = icmp eq i8 %1, 0
  br i1 %.not, label %6, label %7

6:                                                ; preds = %.preheader.preheader
  tail call void @Z80_releaseBus() #3
  br label %7

7:                                                ; preds = %6, %.preheader.preheader
  ret void
}

declare zeroext i8 @Z80_getAndRequestBus(i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @YM2612_write(i16 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @writeSlotReg(i16 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @writeChannelReg(i16 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

declare void @Z80_releaseBus() local_unnamed_addr #1

attributes #0 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass