; LLVM IR from xirc/cp-algorithm :: atcoder/abc074/D/main.ll (Z5solvev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local global i32, align 4
@A = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z5solvev() #0 {
  %1 = alloca i64, align 8
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %11

11:                                               ; preds = %66, %0
  %12 = load i32, ptr %2, align 4, !tbaa !5
  %13 = load i32, ptr @N, align 4, !tbaa !5
  %14 = icmp slt i32 %12, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %11
  store i32 2, ptr %3, align 4
  br label %69

16:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %60, %16
  %18 = load i32, ptr %4, align 4, !tbaa !5
  %19 = load i32, ptr @N, align 4, !tbaa !5
  %20 = icmp slt i32 %18, %19
  br i1 %20, label %22, label %21

21:                                               ; preds = %17
  store i32 5, ptr %3, align 4
  br label %63

22:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %23

23:                                               ; preds = %54, %22
  %24 = load i32, ptr %5, align 4, !tbaa !5
  %25 = load i32, ptr @N, align 4, !tbaa !5
  %26 = icmp slt i32 %24, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %23
  store i32 8, ptr %3, align 4
  br label %57

28:                                               ; preds = %23
  %29 = load i32, ptr %4, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %30) #2
  %32 = load i32, ptr %2, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %33) #2
  %35 = load i64, ptr %34, align 8, !tbaa !9
  %36 = load i32, ptr %2, align 4, !tbaa !5
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %37) #2
  %39 = load i32, ptr %5, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %40) #2
  %42 = load i64, ptr %41, align 8, !tbaa !9
  %43 = add nsw i64 %35, %42
  %44 = load i32, ptr %4, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %45) #2
  %47 = load i32, ptr %5, align 4, !tbaa !5
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #2
  %50 = load i64, ptr %49, align 8, !tbaa !9
  %51 = icmp slt i64 %43, %50
  br i1 %51, label %52, label %53

52:                                               ; preds = %28
  store i64 -1, ptr %1, align 8
  store i32 1, ptr %3, align 4
  br label %57

53:                                               ; preds = %28
  br label %54

54:                                               ; preds = %53
  %55 = load i32, ptr %5, align 4, !tbaa !5
  %56 = add nsw i32 %55, 1
  store i32 %56, ptr %5, align 4, !tbaa !5
  br label %23, !llvm.loop !11

57:                                               ; preds = %52, %27
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  %58 = load i32, ptr %3, align 4
  switch i32 %58, label %63 [
    i32 8, label %59
  ]

59:                                               ; preds = %57
  br label %60

60:                                               ; preds = %59
  %61 = load i32, ptr %4, align 4, !tbaa !5
  %62 = add nsw i32 %61, 1
  store i32 %62, ptr %4, align 4, !tbaa !5
  br label %17, !llvm.loop !13

63:                                               ; preds = %57, %21
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  %64 = load i32, ptr %3, align 4
  switch i32 %64, label %69 [
    i32 5, label %65
  ]

65:                                               ; preds = %63
  br label %66

66:                                               ; preds = %65
  %67 = load i32, ptr %2, align 4, !tbaa !5
  %68 = add nsw i32 %67, 1
  store i32 %68, ptr %2, align 4, !tbaa !5
  br label %11, !llvm.loop !14

69:                                               ; preds = %63, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  %70 = load i32, ptr %3, align 4
  switch i32 %70, label %154 [
    i32 2, label %71
    i32 1, label %152
  ]

71:                                               ; preds = %69
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  store i64 0, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 0, ptr %7, align 4, !tbaa !5
  br label %72

72:                                               ; preds = %147, %71
  %73 = load i32, ptr %7, align 4, !tbaa !5
  %74 = load i32, ptr @N, align 4, !tbaa !5
  %75 = icmp slt i32 %73, %74
  br i1 %75, label %77, label %76

76:                                               ; preds = %72
  store i32 11, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  br label %150

77:                                               ; preds = %72
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %78 = load i32, ptr %7, align 4, !tbaa !5
  %79 = add nsw i32 %78, 1
  store i32 %79, ptr %8, align 4, !tbaa !5
  br label %80

80:                                               ; preds = %143, %77
  %81 = load i32, ptr %8, align 4, !tbaa !5
  %82 = load i32, ptr @N, align 4, !tbaa !5
  %83 = icmp slt i32 %81, %82
  br i1 %83, label %85, label %84

84:                                               ; preds = %80
  store i32 14, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  br label %146

85:                                               ; preds = %80
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #2
  store i8 1, ptr %9, align 1, !tbaa !15
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !5
  br label %86

86:                                               ; preds = %126, %85
  %87 = load i32, ptr %10, align 4, !tbaa !5
  %88 = load i32, ptr @N, align 4, !tbaa !5
  %89 = icmp slt i32 %87, %88
  br i1 %89, label %91, label %90

90:                                               ; preds = %86
  store i32 17, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  br label %129

91:                                               ; preds = %86
  %92 = load i32, ptr %7, align 4, !tbaa !5
  %93 = load i32, ptr %10, align 4, !tbaa !5
  %94 = icmp eq i32 %92, %93
  br i1 %94, label %99, label %95

95:                                               ; preds = %91
  %96 = load i32, ptr %8, align 4, !tbaa !5
  %97 = load i32, ptr %10, align 4, !tbaa !5
  %98 = icmp eq i32 %96, %97
  br i1 %98, label %99, label %100

99:                                               ; preds = %95, %91
  br label %126

100:                                              ; preds = %95
  %101 = load i32, ptr %7, align 4, !tbaa !5
  %102 = sext i32 %101 to i64
  %103 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %102) #2
  %104 = load i32, ptr %8, align 4, !tbaa !5
  %105 = sext i32 %104 to i64
  %106 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %103, i64 noundef %105) #2
  %107 = load i64, ptr %106, align 8, !tbaa !9
  %108 = load i32, ptr %7, align 4, !tbaa !5
  %109 = sext i32 %108 to i64
  %110 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %109) #2
  %111 = load i32, ptr %10, align 4, !tbaa !5
  %112 = sext i32 %111 to i64
  %113 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %110, i64 noundef %112) #2
  %114 = load i64, ptr %113, align 8, !tbaa !9
  %115 = load i32, ptr %10, align 4, !tbaa !5
  %116 = sext i32 %115 to i64
  %117 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %116) #2
  %118 = load i32, ptr %8, align 4, !tbaa !5
  %119 = sext i32 %118 to i64
  %120 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %117, i64 noundef %119) #2
  %121 = load i64, ptr %120, align 8, !tbaa !9
  %122 = add nsw i64 %114, %121
  %123 = icmp eq i64 %107, %122
  br i1 %123, label %124, label %125

124:                                              ; preds = %100
  store i8 0, ptr %9, align 1, !tbaa !15
  br label %125

125:                                              ; preds = %124, %100
  br label %126

126:                                              ; preds = %125, %99
  %127 = load i32, ptr %10, align 4, !tbaa !5
  %128 = add nsw i32 %127, 1
  store i32 %128, ptr %10, align 4, !tbaa !5
  br label %86, !llvm.loop !17

129:                                              ; preds = %90
  %130 = load i8, ptr %9, align 1, !tbaa !15, !range !18, !noundef !19
  %131 = trunc i8 %130 to i1
  br i1 %131, label %132, label %142

132:                                              ; preds = %129
  %133 = load i32, ptr %7, align 4, !tbaa !5
  %134 = sext i32 %133 to i64
  %135 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %134) #2
  %136 = load i32, ptr %8, align 4, !tbaa !5
  %137 = sext i32 %136 to i64
  %138 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %135, i64 noundef %137) #2
  %139 = load i64, ptr %138, align 8, !tbaa !9
  %140 = load i64, ptr %6, align 8, !tbaa !9
  %141 = add nsw i64 %140, %139
  store i64 %141, ptr %6, align 8, !tbaa !9
  br label %142

142:                                              ; preds = %132, %129
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #2
  br label %143

143:                                              ; preds = %142
  %144 = load i32, ptr %8, align 4, !tbaa !5
  %145 = add nsw i32 %144, 1
  store i32 %145, ptr %8, align 4, !tbaa !5
  br label %80, !llvm.loop !20

146:                                              ; preds = %84
  br label %147

147:                                              ; preds = %146
  %148 = load i32, ptr %7, align 4, !tbaa !5
  %149 = add nsw i32 %148, 1
  store i32 %149, ptr %7, align 4, !tbaa !5
  br label %72, !llvm.loop !21

150:                                              ; preds = %76
  %151 = load i64, ptr %6, align 8, !tbaa !9
  store i64 %151, ptr %1, align 8
  store i32 1, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  br label %152

152:                                              ; preds = %150, %69
  %153 = load i64, ptr %1, align 8
  ret i64 %153

154:                                              ; preds = %69
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = !{!16, !16, i64 0}
!16 = !{!"bool", !7, i64 0}
!17 = distinct !{!17, !12}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = distinct !{!20, !12}
!21 = distinct !{!21, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long long>, std::allocator<std::vector<long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local local_unnamed_addr global i32, align 4
@A = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z5solvev() local_unnamed_addr #0 {
  %1 = load i32, ptr @N, align 4, !tbaa !5
  %2 = icmp sgt i32 %1, 0
  br i1 %2, label %.preheader64, label %.thread57

.preheader64:                                     ; preds = %0, %._crit_edge68
  %3 = phi i32 [ %25, %._crit_edge68 ], [ %1, %0 ]
  %indvars.iv88 = phi i64 [ %indvars.iv.next89, %._crit_edge68 ], [ 0, %0 ]
  %4 = icmp sgt i32 %3, 0
  br i1 %4, label %.preheader62, label %._crit_edge68

.preheader61:                                     ; preds = %._crit_edge68
  %5 = icmp sgt i32 %25, 0
  br i1 %5, label %.lr.ph79, label %.thread57

.preheader62:                                     ; preds = %.preheader64, %._crit_edge
  %6 = phi i32 [ %22, %._crit_edge ], [ %3, %.preheader64 ]
  %7 = phi i32 [ %23, %._crit_edge ], [ %3, %.preheader64 ]
  %indvars.iv85 = phi i64 [ %indvars.iv.next86, %._crit_edge ], [ 0, %.preheader64 ]
  %.not65 = icmp sgt i32 %7, 0
  br i1 %.not65, label %.lr.ph, label %.preheader62.._crit_edge_crit_edge

.preheader62.._crit_edge_crit_edge:               ; preds = %.preheader62
  %.pre103 = sext i32 %7 to i64
  br label %._crit_edge

8:                                                ; preds = %.lr.ph
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %9 = load i32, ptr @N, align 4, !tbaa !5
  %10 = sext i32 %9 to i64
  %.not = icmp slt i64 %indvars.iv.next, %10
  br i1 %.not, label %.lr.ph, label %._crit_edge, !llvm.loop !9

.lr.ph:                                           ; preds = %.preheader62, %8
  %indvars.iv = phi i64 [ %indvars.iv.next, %8 ], [ 0, %.preheader62 ]
  %11 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv85) #1
  %12 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv88) #1
  %13 = load i64, ptr %12, align 8, !tbaa !11
  %14 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv88) #1
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %indvars.iv) #1
  %16 = load i64, ptr %15, align 8, !tbaa !11
  %17 = add nsw i64 %16, %13
  %18 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv85) #1
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %indvars.iv) #1
  %20 = load i64, ptr %19, align 8, !tbaa !11
  %21 = icmp slt i64 %17, %20
  br i1 %21, label %.thread57, label %8

._crit_edge:                                      ; preds = %8, %.preheader62.._crit_edge_crit_edge
  %.pre-phi104 = phi i64 [ %.pre103, %.preheader62.._crit_edge_crit_edge ], [ %10, %8 ]
  %22 = phi i32 [ %6, %.preheader62.._crit_edge_crit_edge ], [ %9, %8 ]
  %23 = phi i32 [ %7, %.preheader62.._crit_edge_crit_edge ], [ %9, %8 ]
  %indvars.iv.next86 = add nuw nsw i64 %indvars.iv85, 1
  %24 = icmp slt i64 %indvars.iv.next86, %.pre-phi104
  br i1 %24, label %.preheader62, label %._crit_edge68, !llvm.loop !13

._crit_edge68:                                    ; preds = %._crit_edge, %.preheader64
  %25 = phi i32 [ %3, %.preheader64 ], [ %22, %._crit_edge ]
  %indvars.iv.next89 = add nuw nsw i64 %indvars.iv88, 1
  %26 = sext i32 %25 to i64
  %27 = icmp slt i64 %indvars.iv.next89, %26
  br i1 %27, label %.preheader64, label %.preheader61, !llvm.loop !15

.loopexit.loopexit:                               ; preds = %63
  %.pre102 = sext i32 %64 to i64
  br label %.loopexit

.loopexit:                                        ; preds = %.loopexit.loopexit, %.lr.ph79
  %.pre-phi = phi i64 [ %.pre102, %.loopexit.loopexit ], [ %31, %.lr.ph79 ]
  %28 = phi i32 [ %64, %.loopexit.loopexit ], [ %30, %.lr.ph79 ]
  %.143.lcssa = phi i64 [ %.2, %.loopexit.loopexit ], [ %.04277, %.lr.ph79 ]
  %29 = icmp slt i64 %indvars.iv.next99, %.pre-phi
  %indvars.iv.next94 = add nuw nsw i64 %indvars.iv93, 1
  br i1 %29, label %.lr.ph79, label %.thread57, !llvm.loop !16

.lr.ph79:                                         ; preds = %.preheader61, %.loopexit
  %30 = phi i32 [ %28, %.loopexit ], [ %25, %.preheader61 ]
  %indvars.iv98 = phi i64 [ %indvars.iv.next99, %.loopexit ], [ 0, %.preheader61 ]
  %indvars.iv93 = phi i64 [ %indvars.iv.next94, %.loopexit ], [ 1, %.preheader61 ]
  %.04277 = phi i64 [ %.143.lcssa, %.loopexit ], [ 0, %.preheader61 ]
  %indvars.iv.next99 = add nuw nsw i64 %indvars.iv98, 1
  %31 = sext i32 %30 to i64
  %32 = icmp slt i64 %indvars.iv.next99, %31
  br i1 %32, label %.preheader, label %.loopexit

.preheader:                                       ; preds = %.lr.ph79, %63
  %33 = phi i32 [ %64, %63 ], [ %30, %.lr.ph79 ]
  %34 = phi i32 [ %65, %63 ], [ %30, %.lr.ph79 ]
  %indvars.iv95 = phi i64 [ %indvars.iv.next96, %63 ], [ %indvars.iv93, %.lr.ph79 ]
  %.14374 = phi i64 [ %.2, %63 ], [ %.04277, %.lr.ph79 ]
  %35 = icmp sgt i32 %34, 0
  br i1 %35, label %.lr.ph72, label %.critedge

._crit_edge73:                                    ; preds = %53
  br i1 %.1, label %.critedge, label %63

.lr.ph72:                                         ; preds = %.preheader, %53
  %36 = phi i32 [ %54, %53 ], [ %33, %.preheader ]
  %37 = phi i32 [ %55, %53 ], [ %34, %.preheader ]
  %38 = phi i32 [ %56, %53 ], [ %34, %.preheader ]
  %indvars.iv91 = phi i64 [ %indvars.iv.next92, %53 ], [ 0, %.preheader ]
  %.03970 = phi i1 [ %.1, %53 ], [ true, %.preheader ]
  %39 = icmp eq i64 %indvars.iv98, %indvars.iv91
  %40 = icmp eq i64 %indvars.iv95, %indvars.iv91
  %or.cond = or i1 %39, %40
  br i1 %or.cond, label %53, label %41

41:                                               ; preds = %.lr.ph72
  %42 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv98) #1
  %43 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %indvars.iv95) #1
  %44 = load i64, ptr %43, align 8, !tbaa !11
  %45 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv98) #1
  %46 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef %indvars.iv91) #1
  %47 = load i64, ptr %46, align 8, !tbaa !11
  %48 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv91) #1
  %49 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %indvars.iv95) #1
  %50 = load i64, ptr %49, align 8, !tbaa !11
  %51 = add nsw i64 %50, %47
  %52 = icmp ne i64 %44, %51
  %spec.select = select i1 %52, i1 %.03970, i1 false
  %.pre = load i32, ptr @N, align 4, !tbaa !5
  br label %53

53:                                               ; preds = %41, %.lr.ph72
  %54 = phi i32 [ %36, %.lr.ph72 ], [ %.pre, %41 ]
  %55 = phi i32 [ %37, %.lr.ph72 ], [ %.pre, %41 ]
  %56 = phi i32 [ %38, %.lr.ph72 ], [ %.pre, %41 ]
  %.1 = phi i1 [ %.03970, %.lr.ph72 ], [ %spec.select, %41 ]
  %indvars.iv.next92 = add nuw nsw i64 %indvars.iv91, 1
  %57 = sext i32 %56 to i64
  %58 = icmp slt i64 %indvars.iv.next92, %57
  br i1 %58, label %.lr.ph72, label %._crit_edge73, !llvm.loop !17

.critedge:                                        ; preds = %.preheader, %._crit_edge73
  %59 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %indvars.iv98) #1
  %60 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %59, i64 noundef %indvars.iv95) #1
  %61 = load i64, ptr %60, align 8, !tbaa !11
  %62 = add nsw i64 %61, %.14374
  %.pre101 = load i32, ptr @N, align 4, !tbaa !5
  br label %63

63:                                               ; preds = %.critedge, %._crit_edge73
  %64 = phi i32 [ %.pre101, %.critedge ], [ %54, %._crit_edge73 ]
  %65 = phi i32 [ %.pre101, %.critedge ], [ %55, %._crit_edge73 ]
  %.2 = phi i64 [ %62, %.critedge ], [ %.14374, %._crit_edge73 ]
  %indvars.iv.next96 = add nuw nsw i64 %indvars.iv95, 1
  %66 = trunc nuw i64 %indvars.iv.next96 to i32
  %67 = icmp sgt i32 %65, %66
  br i1 %67, label %.preheader, label %.loopexit.loopexit, !llvm.loop !18

.thread57:                                        ; preds = %.lr.ph, %.loopexit, %0, %.preheader61
  %.5 = phi i64 [ 0, %.preheader61 ], [ 0, %0 ], [ %.143.lcssa, %.loopexit ], [ -1, %.lr.ph ]
  ret i64 %.5
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IxSaIxEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = distinct !{!13, !10, !14}
!14 = !{!"llvm.loop.unswitch.partial.disable"}
!15 = distinct !{!15, !10, !14}
!16 = distinct !{!16, !10}
!17 = distinct !{!17, !10}
!18 = distinct !{!18, !10}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass