; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeWidth = external global i16, align 2
@windowWidth = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @VDP_getPlaneAddress(i32 noundef, i16 noundef zeroext, i16 noundef zeroext) #1

declare void @VDP_setAutoInc(i8 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local void @VDP_fillTileMapRectInc(i32 noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5) #1 {
  %7 = alloca i32, align 4
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca i16, align 2
  %16 = alloca i16, align 2
  %17 = alloca i16, align 2
  %18 = alloca i16, align 2
  %19 = alloca i16, align 2
  store i32 %0, ptr %7, align 4, !tbaa !5
  store i16 %1, ptr %8, align 2, !tbaa !9
  store i16 %2, ptr %9, align 2, !tbaa !9
  store i16 %3, ptr %10, align 2, !tbaa !9
  store i16 %4, ptr %11, align 2, !tbaa !9
  store i16 %5, ptr %12, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %15) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %16) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %17) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %18) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %19) #3
  call void @VDP_setAutoInc(i8 noundef zeroext 2)
  store ptr inttoptr (i64 12582916 to ptr), ptr %13, align 8, !tbaa !11
  store ptr inttoptr (i64 12582912 to ptr), ptr %14, align 8, !tbaa !11
  %20 = load i32, ptr %7, align 4, !tbaa !5
  %21 = load i16, ptr %9, align 2, !tbaa !9
  %22 = load i16, ptr %10, align 2, !tbaa !9
  %23 = call zeroext i16 @VDP_getPlaneAddress(i32 noundef %20, i16 noundef zeroext %21, i16 noundef zeroext %22)
  store i16 %23, ptr %15, align 2, !tbaa !9
  %24 = load i32, ptr %7, align 4, !tbaa !5
  %25 = icmp eq i32 %24, 2
  br i1 %25, label %26, label %29

26:                                               ; preds = %6
  %27 = load i16, ptr @windowWidth, align 2, !tbaa !9
  %28 = zext i16 %27 to i32
  br label %32

29:                                               ; preds = %6
  %30 = load i16, ptr @planeWidth, align 2, !tbaa !9
  %31 = zext i16 %30 to i32
  br label %32

32:                                               ; preds = %29, %26
  %33 = phi i32 [ %28, %26 ], [ %31, %29 ]
  %34 = trunc i32 %33 to i16
  store i16 %34, ptr %16, align 2, !tbaa !9
  %35 = load i16, ptr %8, align 2, !tbaa !9
  store i16 %35, ptr %17, align 2, !tbaa !9
  %36 = load i16, ptr %12, align 2, !tbaa !9
  store i16 %36, ptr %18, align 2, !tbaa !9
  br label %37

37:                                               ; preds = %62, %32
  %38 = load i16, ptr %18, align 2, !tbaa !9
  %39 = add i16 %38, -1
  store i16 %39, ptr %18, align 2, !tbaa !9
  %40 = icmp ne i16 %38, 0
  br i1 %40, label %41, label %70

41:                                               ; preds = %37
  %42 = load i16, ptr %15, align 2, !tbaa !9
  %43 = zext i16 %42 to i64
  %44 = and i64 %43, 16383
  %45 = add i64 16384, %44
  %46 = shl i64 %45, 16
  %47 = load i16, ptr %15, align 2, !tbaa !9
  %48 = zext i16 %47 to i64
  %49 = lshr i64 %48, 14
  %50 = or i64 %49, 0
  %51 = add i64 %46, %50
  %52 = load ptr, ptr %13, align 8, !tbaa !11
  store volatile i64 %51, ptr %52, align 8, !tbaa !13
  %53 = load i16, ptr %11, align 2, !tbaa !9
  store i16 %53, ptr %19, align 2, !tbaa !9
  br label %54

54:                                               ; preds = %58, %41
  %55 = load i16, ptr %19, align 2, !tbaa !9
  %56 = add i16 %55, -1
  store i16 %56, ptr %19, align 2, !tbaa !9
  %57 = icmp ne i16 %55, 0
  br i1 %57, label %58, label %62

58:                                               ; preds = %54
  %59 = load i16, ptr %17, align 2, !tbaa !9
  %60 = add i16 %59, 1
  store i16 %60, ptr %17, align 2, !tbaa !9
  %61 = load ptr, ptr %14, align 8, !tbaa !11
  store volatile i16 %59, ptr %61, align 2, !tbaa !9
  br label %54, !llvm.loop !15

62:                                               ; preds = %54
  %63 = load i16, ptr %16, align 2, !tbaa !9
  %64 = zext i16 %63 to i32
  %65 = mul nsw i32 %64, 2
  %66 = load i16, ptr %15, align 2, !tbaa !9
  %67 = zext i16 %66 to i32
  %68 = add nsw i32 %67, %65
  %69 = trunc i32 %68 to i16
  store i16 %69, ptr %15, align 2, !tbaa !9
  br label %37, !llvm.loop !17

70:                                               ; preds = %37
  call void @llvm.lifetime.end.p0(i64 2, ptr %19) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %18) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %17) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeWidth = external local_unnamed_addr global i16, align 2
@windowWidth = external local_unnamed_addr global i16, align 2

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @VDP_getPlaneAddress(i32 noundef, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

declare void @VDP_setAutoInc(i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @VDP_fillTileMapRectInc(i32 noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5) local_unnamed_addr #0 {
  tail call void @VDP_setAutoInc(i8 noundef zeroext 2) #2
  %7 = tail call zeroext i16 @VDP_getPlaneAddress(i32 noundef %0, i16 noundef zeroext %2, i16 noundef zeroext %3)
  %.not22 = icmp eq i16 %5, 0
  br i1 %.not22, label %._crit_edge27, label %.lr.ph26

.lr.ph26:                                         ; preds = %6
  %8 = add i16 %5, -1
  %9 = icmp eq i32 %0, 2
  %10 = load i16, ptr @windowWidth, align 2
  %11 = load i16, ptr @planeWidth, align 2
  %.v = select i1 %9, i16 %10, i16 %11
  %.not1819 = icmp eq i16 %4, 0
  %12 = shl i16 %.v, 1
  br i1 %.not1819, label %.lr.ph26.split.us.preheader, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %.lr.ph26
  %xtraiter = and i16 %4, 7
  %lcmp.mod.not = icmp eq i16 %xtraiter, 0
  %13 = icmp ult i16 %4, 8
  br label %.lr.ph

.lr.ph26.split.us.preheader:                      ; preds = %.lr.ph26
  %xtraiter32 = and i16 %5, 1
  %lcmp.mod33.not = icmp eq i16 %xtraiter32, 0
  br i1 %lcmp.mod33.not, label %.lr.ph26.split.us.prol.loopexit, label %.lr.ph26.split.us.prol

.lr.ph26.split.us.prol:                           ; preds = %.lr.ph26.split.us.preheader
  %14 = zext i16 %7 to i64
  %15 = shl nuw nsw i64 %14, 16
  %16 = and i64 %15, 1073676288
  %17 = lshr i64 %14, 14
  %18 = or disjoint i64 %17, %16
  %19 = or disjoint i64 %18, 1073741824
  store volatile i64 %19, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !5
  %20 = add i16 %7, %12
  %21 = add i16 %5, -2
  br label %.lr.ph26.split.us.prol.loopexit

.lr.ph26.split.us.prol.loopexit:                  ; preds = %.lr.ph26.split.us.prol, %.lr.ph26.split.us.preheader
  %.unr = phi i16 [ %8, %.lr.ph26.split.us.preheader ], [ %21, %.lr.ph26.split.us.prol ]
  %.01723.us.unr = phi i16 [ %7, %.lr.ph26.split.us.preheader ], [ %20, %.lr.ph26.split.us.prol ]
  %22 = icmp eq i16 %8, 0
  br i1 %22, label %._crit_edge27, label %.lr.ph26.split.us

.lr.ph26.split.us:                                ; preds = %.lr.ph26.split.us.prol.loopexit, %.lr.ph26.split.us
  %23 = phi i16 [ %38, %.lr.ph26.split.us ], [ %.unr, %.lr.ph26.split.us.prol.loopexit ]
  %.01723.us = phi i16 [ %37, %.lr.ph26.split.us ], [ %.01723.us.unr, %.lr.ph26.split.us.prol.loopexit ]
  %24 = zext i16 %.01723.us to i64
  %25 = shl nuw nsw i64 %24, 16
  %26 = and i64 %25, 1073676288
  %27 = lshr i64 %24, 14
  %28 = or disjoint i64 %27, %26
  %29 = or disjoint i64 %28, 1073741824
  store volatile i64 %29, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !5
  %30 = add i16 %.01723.us, %12
  %31 = zext i16 %30 to i64
  %32 = shl nuw nsw i64 %31, 16
  %33 = and i64 %32, 1073676288
  %34 = lshr i64 %31, 14
  %35 = or disjoint i64 %34, %33
  %36 = or disjoint i64 %35, 1073741824
  store volatile i64 %36, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !5
  %37 = add i16 %30, %12
  %38 = add i16 %23, -2
  %.not.us.1 = icmp eq i16 %23, 1
  br i1 %.not.us.1, label %._crit_edge27, label %.lr.ph26.split.us, !llvm.loop !9

.lr.ph:                                           ; preds = %.lr.ph.preheader, %._crit_edge
  %39 = phi i16 [ %58, %._crit_edge ], [ %8, %.lr.ph.preheader ]
  %.01624 = phi i16 [ %.lcssa, %._crit_edge ], [ %1, %.lr.ph.preheader ]
  %.01723 = phi i16 [ %57, %._crit_edge ], [ %7, %.lr.ph.preheader ]
  %40 = zext i16 %.01723 to i64
  %41 = shl nuw nsw i64 %40, 16
  %42 = and i64 %41, 1073676288
  %43 = lshr i64 %40, 14
  %44 = or disjoint i64 %43, %42
  %45 = or disjoint i64 %44, 1073741824
  store volatile i64 %45, ptr inttoptr (i64 12582916 to ptr), align 8, !tbaa !5
  br i1 %lcmp.mod.not, label %.prol.loopexit, label %.prol.preheader

.prol.preheader:                                  ; preds = %.lr.ph, %.prol.preheader
  %.021.prol = phi i16 [ %46, %.prol.preheader ], [ %4, %.lr.ph ]
  %.120.prol = phi i16 [ %47, %.prol.preheader ], [ %.01624, %.lr.ph ]
  %prol.iter = phi i16 [ %prol.iter.next, %.prol.preheader ], [ 0, %.lr.ph ]
  %46 = add i16 %.021.prol, -1
  %47 = add i16 %.120.prol, 1
  store volatile i16 %.120.prol, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %prol.iter.next = add i16 %prol.iter, 1
  %prol.iter.cmp.not = icmp eq i16 %prol.iter.next, %xtraiter
  br i1 %prol.iter.cmp.not, label %.prol.loopexit, label %.prol.preheader, !llvm.loop !13

.prol.loopexit:                                   ; preds = %.prol.preheader, %.lr.ph
  %.lcssa.unr = phi i16 [ poison, %.lr.ph ], [ %47, %.prol.preheader ]
  %.021.unr = phi i16 [ %4, %.lr.ph ], [ %46, %.prol.preheader ]
  %.120.unr = phi i16 [ %.01624, %.lr.ph ], [ %47, %.prol.preheader ]
  br i1 %13, label %._crit_edge, label %.lr.ph.new

.lr.ph.new:                                       ; preds = %.prol.loopexit, %.lr.ph.new
  %.021 = phi i16 [ %55, %.lr.ph.new ], [ %.021.unr, %.prol.loopexit ]
  %.120 = phi i16 [ %56, %.lr.ph.new ], [ %.120.unr, %.prol.loopexit ]
  %48 = add i16 %.120, 1
  store volatile i16 %.120, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %49 = add i16 %.120, 2
  store volatile i16 %48, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %50 = add i16 %.120, 3
  store volatile i16 %49, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %51 = add i16 %.120, 4
  store volatile i16 %50, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %52 = add i16 %.120, 5
  store volatile i16 %51, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %53 = add i16 %.120, 6
  store volatile i16 %52, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %54 = add i16 %.120, 7
  store volatile i16 %53, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %55 = add i16 %.021, -8
  %56 = add i16 %.120, 8
  store volatile i16 %54, ptr inttoptr (i64 12582912 to ptr), align 4194304, !tbaa !11
  %.not18.7 = icmp eq i16 %55, 0
  br i1 %.not18.7, label %._crit_edge, label %.lr.ph.new, !llvm.loop !15

._crit_edge:                                      ; preds = %.lr.ph.new, %.prol.loopexit
  %.lcssa = phi i16 [ %.lcssa.unr, %.prol.loopexit ], [ %56, %.lr.ph.new ]
  %57 = add i16 %.01723, %12
  %58 = add i16 %39, -1
  %.not = icmp eq i16 %39, 0
  br i1 %.not, label %._crit_edge27, label %.lr.ph, !llvm.loop !9

._crit_edge27:                                    ; preds = %._crit_edge, %.lr.ph26.split.us.prol.loopexit, %.lr.ph26.split.us, %6
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.unroll.disable"}
!15 = distinct !{!15, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass