; LLVM IR from marcinlos/iga-ads :: examples/tumor/vasculature (vasculature)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK5tumor4vasc11vasculature4blurERN3ads3lin6tensorIdLm2EEES6_id(ptr noundef nonnull align 8 dereferenceable(5352) %0, ptr noundef nonnull align 8 dereferenceable(32) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, i32 noundef %3, double noundef %4) #1 align 2 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca double, align 8
  %11 = alloca double, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca double, align 8
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  store double %4, ptr %10, align 8, !tbaa !11
  %18 = load ptr, ptr %6, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  %19 = load double, ptr %10, align 8, !tbaa !11
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = mul nsw i32 2, %20
  %22 = add nsw i32 %21, 1
  %23 = load i32, ptr %9, align 4, !tbaa !9
  %24 = mul nsw i32 2, %23
  %25 = add nsw i32 %24, 1
  %26 = mul nsw i32 %22, %25
  %27 = sitofp i32 %26 to double
  %28 = fdiv double %19, %27
  store double %28, ptr %11, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  %29 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %29, ptr %12, align 4, !tbaa !9
  br label %30

30:                                               ; preds = %96, %5
  %31 = load i32, ptr %12, align 4, !tbaa !9
  %32 = zext i32 %31 to i64
  %33 = load i32, ptr %9, align 4, !tbaa !9
  %34 = sext i32 %33 to i64
  %35 = sub i64 500, %34
  %36 = icmp ule i64 %32, %35
  br i1 %36, label %38, label %37

37:                                               ; preds = %30
  store i32 2, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %99

38:                                               ; preds = %30
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  %39 = load i32, ptr %9, align 4, !tbaa !9
  store i32 %39, ptr %14, align 4, !tbaa !9
  br label %40

40:                                               ; preds = %92, %38
  %41 = load i32, ptr %14, align 4, !tbaa !9
  %42 = zext i32 %41 to i64
  %43 = load i32, ptr %9, align 4, !tbaa !9
  %44 = sext i32 %43 to i64
  %45 = sub i64 500, %44
  %46 = icmp ule i64 %42, %45
  br i1 %46, label %48, label %47

47:                                               ; preds = %40
  store i32 5, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  br label %95

48:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #2
  store double 0.000000e+00, ptr %15, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  %49 = load i32, ptr %9, align 4, !tbaa !9
  %50 = sub nsw i32 0, %49
  store i32 %50, ptr %16, align 4, !tbaa !9
  br label %51

51:                                               ; preds = %80, %48
  %52 = load i32, ptr %16, align 4, !tbaa !9
  %53 = load i32, ptr %9, align 4, !tbaa !9
  %54 = icmp sle i32 %52, %53
  br i1 %54, label %56, label %55

55:                                               ; preds = %51
  store i32 8, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  br label %83

56:                                               ; preds = %51
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #2
  %57 = load i32, ptr %9, align 4, !tbaa !9
  %58 = sub nsw i32 0, %57
  store i32 %58, ptr %17, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %76, %56
  %60 = load i32, ptr %17, align 4, !tbaa !9
  %61 = load i32, ptr %9, align 4, !tbaa !9
  %62 = icmp sle i32 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  store i32 11, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #2
  br label %79

64:                                               ; preds = %59
  %65 = load ptr, ptr %7, align 8, !tbaa !5
  %66 = load i32, ptr %12, align 4, !tbaa !9
  %67 = load i32, ptr %16, align 4, !tbaa !9
  %68 = add i32 %66, %67
  %69 = load i32, ptr %14, align 4, !tbaa !9
  %70 = load i32, ptr %17, align 4, !tbaa !9
  %71 = add i32 %69, %70
  %72 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8) %65, i32 noundef %68, i32 noundef %71)
  %73 = load double, ptr %72, align 8, !tbaa !11
  %74 = load double, ptr %15, align 8, !tbaa !11
  %75 = fadd double %74, %73
  store double %75, ptr %15, align 8, !tbaa !11
  br label %76

76:                                               ; preds = %64
  %77 = load i32, ptr %17, align 4, !tbaa !9
  %78 = add nsw i32 %77, 1
  store i32 %78, ptr %17, align 4, !tbaa !9
  br label %59, !llvm.loop !13

79:                                               ; preds = %63
  br label %80

80:                                               ; preds = %79
  %81 = load i32, ptr %16, align 4, !tbaa !9
  %82 = add nsw i32 %81, 1
  store i32 %82, ptr %16, align 4, !tbaa !9
  br label %51, !llvm.loop !15

83:                                               ; preds = %55
  %84 = load double, ptr %11, align 8, !tbaa !11
  %85 = load double, ptr %15, align 8, !tbaa !11
  %86 = fmul double %85, %84
  store double %86, ptr %15, align 8, !tbaa !11
  %87 = load double, ptr %15, align 8, !tbaa !11
  %88 = load ptr, ptr %8, align 8, !tbaa !5
  %89 = load i32, ptr %12, align 4, !tbaa !9
  %90 = load i32, ptr %14, align 4, !tbaa !9
  %91 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8) %88, i32 noundef %89, i32 noundef %90)
  store double %87, ptr %91, align 8, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #2
  br label %92

92:                                               ; preds = %83
  %93 = load i32, ptr %14, align 4, !tbaa !9
  %94 = add i32 %93, 1
  store i32 %94, ptr %14, align 4, !tbaa !9
  br label %40, !llvm.loop !16

95:                                               ; preds = %47
  br label %96

96:                                               ; preds = %95
  %97 = load i32, ptr %12, align 4, !tbaa !9
  %98 = add i32 %97, 1
  store i32 %98, ptr %12, align 4, !tbaa !9
  br label %30, !llvm.loop !17

99:                                               ; preds = %37
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef, i32 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"double", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK5tumor4vasc11vasculature4blurERN3ads3lin6tensorIdLm2EEES6_id(ptr nocapture noundef nonnull readnone align 8 dereferenceable(5352) %0, ptr noundef nonnull align 8 dereferenceable(32) %1, ptr noundef nonnull align 8 dereferenceable(32) %2, i32 noundef %3, double noundef %4) local_unnamed_addr #0 align 2 {
  %6 = shl nsw i32 %3, 1
  %7 = or disjoint i32 %6, 1
  %8 = mul nsw i32 %7, %7
  %9 = uitofp nneg i32 %8 to double
  %10 = fdiv double %4, %9
  %11 = sext i32 %3 to i64
  %12 = sub nsw i64 500, %11
  %13 = zext i32 %3 to i64
  %.not52 = icmp ult i64 %12, %13
  br i1 %.not52, label %._crit_edge55, label %.preheader40.lr.ph.split

.preheader40.lr.ph.split:                         ; preds = %5
  %14 = sub nsw i32 0, %3
  %15 = fmul double %10, 0.000000e+00
  %.not3844 = icmp slt i32 %3, 0
  br i1 %.not3844, label %.preheader40.us56.preheader, label %.preheader40

.preheader40.us56.preheader:                      ; preds = %.preheader40.lr.ph.split
  %16 = trunc nuw i64 %12 to i32
  br label %.preheader40.us56

.preheader40.us56:                                ; preds = %.preheader40.us56.preheader, %._crit_edge51.split.us.us
  %.03453.us57 = phi i32 [ %20, %._crit_edge51.split.us.us ], [ %3, %.preheader40.us56.preheader ]
  br label %17

17:                                               ; preds = %17, %.preheader40.us56
  %.03350.us.us = phi i32 [ %3, %.preheader40.us56 ], [ %19, %17 ]
  %18 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %.03453.us57, i32 noundef %.03350.us.us)
  store double %15, ptr %18, align 8, !tbaa !5
  %19 = add i32 %.03350.us.us, 1
  %.not37.us.us = icmp ugt i32 %19, %16
  br i1 %.not37.us.us, label %._crit_edge51.split.us.us, label %17, !llvm.loop !9

._crit_edge51.split.us.us:                        ; preds = %17
  %20 = add i32 %.03453.us57, 1
  %.not.us58 = icmp ugt i32 %20, %16
  br i1 %.not.us58, label %._crit_edge55, label %.preheader40.us56, !llvm.loop !11

.preheader40:                                     ; preds = %.preheader40.lr.ph.split, %._crit_edge51.split
  %.03453 = phi i32 [ %21, %._crit_edge51.split ], [ %3, %.preheader40.lr.ph.split ]
  br label %.preheader.lr.ph

._crit_edge55:                                    ; preds = %._crit_edge51.split, %._crit_edge51.split.us.us, %5
  ret void

._crit_edge51.split:                              ; preds = %._crit_edge47.split
  %21 = add i32 %.03453, 1
  %22 = zext i32 %21 to i64
  %.not = icmp ult i64 %12, %22
  br i1 %.not, label %._crit_edge55, label %.preheader40, !llvm.loop !11

.preheader.lr.ph:                                 ; preds = %.preheader40, %._crit_edge47.split
  %.03350 = phi i32 [ %3, %.preheader40 ], [ %26, %._crit_edge47.split ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader.lr.ph, %._crit_edge
  %.03146 = phi i32 [ %14, %.preheader.lr.ph ], [ %28, %._crit_edge ]
  %.03245 = phi double [ 0.000000e+00, %.preheader.lr.ph ], [ %33, %._crit_edge ]
  %23 = add i32 %.03146, %.03453
  br label %29

._crit_edge47.split:                              ; preds = %._crit_edge
  %24 = fmul double %10, %33
  %25 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8) %2, i32 noundef %.03453, i32 noundef %.03350)
  store double %24, ptr %25, align 8, !tbaa !5
  %26 = add i32 %.03350, 1
  %27 = zext i32 %26 to i64
  %.not37 = icmp ult i64 %12, %27
  br i1 %.not37, label %._crit_edge51.split, label %.preheader.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %29
  %28 = add i32 %.03146, 1
  %exitcond61.not = icmp eq i32 %.03146, %3
  br i1 %exitcond61.not, label %._crit_edge47.split, label %.preheader, !llvm.loop !12

29:                                               ; preds = %.preheader, %29
  %.043 = phi i32 [ %14, %.preheader ], [ %34, %29 ]
  %.142 = phi double [ %.03245, %.preheader ], [ %33, %29 ]
  %30 = add i32 %.043, %.03350
  %31 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8) %1, i32 noundef %23, i32 noundef %30)
  %32 = load double, ptr %31, align 8, !tbaa !5
  %33 = fadd double %.142, %32
  %34 = add i32 %.043, 1
  %exitcond.not = icmp eq i32 %.043, %3
  br i1 %exitcond.not, label %._crit_edge, label %29, !llvm.loop !13
}

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZN3ads16multi_array_baseIdLm2ENS_3lin11tensor_baseIdLm2ENS1_6tensorIdLm2EEEEENS_16reverse_orderingEEclIJjjEEERdDpT_(ptr noundef nonnull align 4 dereferenceable(8), i32 noundef, i32 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass