; LLVM IR from gstonge/spreading_CR :: src/SpreadingProcess.ll (ZN3net16SpreadingProcessC2ERSt6vectorISt4pairIjjESaIS3_EEdddd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.net::SpreadingProcess" = type <{ %"class.net::StaticNetworkSIR", %"class.pcg_detail::engine", %"class.std::uniform_real_distribution", [100000 x double], %"class.std::vector", %"class.std::vector.5", %"class.std::vector.5", %"class.std::vector.45", i8, [7 x i8] }>
%"class.net::StaticNetworkSIR" = type { %"class.net::Network", double, double, double, double, i8, i8, i8, i8, [4 x i8], %"class.net::HashPropensity", i64, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.10", %"class.std::vector.5", %"class.net::BinaryTree", %"class.std::unordered_map.25", i64, i64 }
%"class.net::Network" = type { %"class.std::shared_ptr" }
%"class.std::shared_ptr" = type { %"class.std::__shared_ptr" }
%"class.std::__shared_ptr" = type { ptr, %"class.std::__shared_count" }
%"class.std::__shared_count" = type { ptr }
%"class.net::HashPropensity" = type <{ double, double, double, i8, [7 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<std::unordered_set<unsigned int>, std::allocator<std::unordered_set<unsigned int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::unordered_set<unsigned int>, std::allocator<std::unordered_set<unsigned int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::unordered_set<unsigned int>, std::allocator<std::unordered_set<unsigned int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::unordered_set<unsigned int>, std::allocator<std::unordered_set<unsigned int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.net::BinaryTree" = type { ptr, ptr, %"class.std::vector.15", %"class.std::unordered_map" }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<net::BinaryTreeNode *, std::allocator<net::BinaryTreeNode *>>::_Vector_impl" }
%"struct.std::_Vector_base<net::BinaryTreeNode *, std::allocator<net::BinaryTreeNode *>>::_Vector_impl" = type { %"struct.std::_Vector_base<net::BinaryTreeNode *, std::allocator<net::BinaryTreeNode *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<net::BinaryTreeNode *, std::allocator<net::BinaryTreeNode *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::unordered_map" = type { %"class.std::_Hashtable" }
%"class.std::_Hashtable" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"struct.std::__detail::_Hash_node_base" = type { ptr }
%"struct.std::__detail::_Prime_rehash_policy" = type { float, i64 }
%"class.std::unordered_map.25" = type { %"class.std::_Hashtable.26" }
%"class.std::_Hashtable.26" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"class.pcg_detail::engine" = type { %"class.pcg_detail::specific_stream", i64 }
%"class.pcg_detail::specific_stream" = type { i64 }
%"class.std::uniform_real_distribution" = type { %"struct.std::uniform_real_distribution<>::param_type" }
%"struct.std::uniform_real_distribution<>::param_type" = type { double, double }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.45" = type { %"struct.std::_Vector_base.46" }
%"struct.std::_Vector_base.46" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>, std::allocator<std::pair<unsigned int, unsigned int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3net16SpreadingProcessC2ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(800513) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, double noundef %2, double noundef %3, double noundef %4, double noundef %5) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca double, align 8
  %10 = alloca double, align 8
  %11 = alloca double, align 8
  %12 = alloca double, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store double %2, ptr %9, align 8, !tbaa !9
  store double %3, ptr %10, align 8, !tbaa !9
  store double %4, ptr %11, align 8, !tbaa !9
  store double %5, ptr %12, align 8, !tbaa !9
  %16 = load ptr, ptr %7, align 8
  %17 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 0
  %18 = load ptr, ptr %8, align 8, !tbaa !5
  %19 = load double, ptr %9, align 8, !tbaa !9
  %20 = load double, ptr %10, align 8, !tbaa !9
  %21 = load double, ptr %11, align 8, !tbaa !9
  %22 = load double, ptr %12, align 8, !tbaa !9
  call void @_ZN3net16StaticNetworkSIRC1ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(384) %17, ptr noundef nonnull align 8 dereferenceable(24) %18, double noundef %19, double noundef %20, double noundef %21, double noundef %22)
  %23 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 1
  invoke void @_ZN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEC2Em(ptr noundef nonnull align 8 dereferenceable(16) %23, i64 noundef 42)
          to label %24 unwind label %36

24:                                               ; preds = %6
  %25 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 2
  invoke void @_ZNSt25uniform_real_distributionIdEC2Edd(ptr noundef nonnull align 8 dereferenceable(16) %25, double noundef 0.000000e+00, double noundef 1.000000e+00)
          to label %26 unwind label %36

26:                                               ; preds = %24
  %27 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 4
  call void @llvm.memset.p0.i64(ptr align 8 %27, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIdSaIdEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %27) #7
  %28 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 5
  call void @llvm.memset.p0.i64(ptr align 8 %28, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %28) #7
  %29 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 6
  call void @llvm.memset.p0.i64(ptr align 8 %29, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %29) #7
  %30 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 7
  call void @llvm.memset.p0.i64(ptr align 8 %30, i8 0, i64 24, i1 false)
  call void @_ZNSt6vectorISt4pairIjjESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %30) #7
  %31 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 8
  store i8 0, ptr %31, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #7
  store i32 0, ptr %15, align 4, !tbaa !57
  br label %32

32:                                               ; preds = %51, %26
  %33 = load i32, ptr %15, align 4, !tbaa !57
  %34 = icmp ult i32 %33, 100000
  br i1 %34, label %40, label %35

35:                                               ; preds = %32
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #7
  br label %54

36:                                               ; preds = %24, %6
  %37 = landingpad { ptr, i32 }
          cleanup
  %38 = extractvalue { ptr, i32 } %37, 0
  store ptr %38, ptr %13, align 8
  %39 = extractvalue { ptr, i32 } %37, 1
  store i32 %39, ptr %14, align 4
  call void @_ZN3net16StaticNetworkSIRD2Ev(ptr noundef nonnull align 8 dereferenceable(384) %17) #7
  br label %55

40:                                               ; preds = %32
  %41 = load i32, ptr %15, align 4, !tbaa !57
  %42 = sitofp i32 %41 to double
  %43 = fadd double %42, 5.000000e-01
  %44 = fdiv double %43, 1.000000e+05
  %45 = call double @log(double noundef %44) #7
  %46 = fneg double %45
  %47 = getelementptr inbounds %"class.net::SpreadingProcess", ptr %16, i32 0, i32 3
  %48 = load i32, ptr %15, align 4, !tbaa !57
  %49 = sext i32 %48 to i64
  %50 = getelementptr inbounds [100000 x double], ptr %47, i64 0, i64 %49
  store double %46, ptr %50, align 8, !tbaa !9
  br label %51

51:                                               ; preds = %40
  %52 = load i32, ptr %15, align 4, !tbaa !57
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %15, align 4, !tbaa !57
  br label %32, !llvm.loop !59

54:                                               ; preds = %35
  ret void

55:                                               ; preds = %36
  %56 = load ptr, ptr %13, align 8
  %57 = load i32, ptr %14, align 4
  %58 = insertvalue { ptr, i32 } poison, ptr %56, 0
  %59 = insertvalue { ptr, i32 } %58, i32 %57, 1
  resume { ptr, i32 } %59
}

declare void @_ZN3net16StaticNetworkSIRC1ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(384), ptr noundef nonnull align 8 dereferenceable(24), double noundef, double noundef, double noundef, double noundef) unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEC2Em(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt25uniform_real_distributionIdEC2Edd(ptr noundef nonnull align 8 dereferenceable(16), double noundef, double noundef) unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt4pairIjjESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: nounwind
declare double @log(double noundef) #5

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3net16StaticNetworkSIRD2Ev(ptr noundef nonnull align 8 dereferenceable(384)) unnamed_addr #6 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !18, i64 800512}
!12 = !{!"_ZTSN3net16SpreadingProcessE", !13, i64 0, !49, i64 384, !51, i64 400, !7, i64 416, !21, i64 800416, !29, i64 800440, !29, i64 800464, !53, i64 800488, !18, i64 800512}
!13 = !{!"_ZTSN3net16StaticNetworkSIRE", !14, i64 0, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !18, i64 48, !18, i64 49, !18, i64 50, !18, i64 51, !19, i64 56, !20, i64 88, !21, i64 96, !25, i64 120, !29, i64 144, !33, i64 168, !29, i64 192, !37, i64 216, !47, i64 312, !20, i64 368, !20, i64 376}
!14 = !{!"_ZTSN3net7NetworkE", !15, i64 0}
!15 = !{!"_ZTSSt10shared_ptrISt6vectorIS0_IjSaIjEESaIS2_EEE", !16, i64 0}
!16 = !{!"_ZTSSt12__shared_ptrISt6vectorIS0_IjSaIjEESaIS2_EELN9__gnu_cxx12_Lock_policyE2EE", !6, i64 0, !17, i64 8}
!17 = !{!"_ZTSSt14__shared_countILN9__gnu_cxx12_Lock_policyE2EE", !6, i64 0}
!18 = !{!"bool", !7, i64 0}
!19 = !{!"_ZTSN3net14HashPropensityE", !10, i64 0, !10, i64 8, !10, i64 16, !18, i64 24}
!20 = !{!"long", !7, i64 0}
!21 = !{!"_ZTSSt6vectorIdSaIdEE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorImSaImEE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseImSaImEE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!"_ZTSSt6vectorIjSaIjEE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSN3net10BinaryTreeE", !6, i64 0, !6, i64 8, !38, i64 16, !42, i64 40}
!38 = !{!"_ZTSSt6vectorIPN3net14BinaryTreeNodeESaIS2_EE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"_ZTSSt13unordered_mapIPN3net14BinaryTreeNodeEjSt4hashIS2_ESt8equal_toIS2_ESaISt4pairIKS2_jEEE", !43, i64 0}
!43 = !{!"_ZTSSt10_HashtableIPN3net14BinaryTreeNodeESt4pairIKS2_jESaIS5_ENSt8__detail10_Select1stESt8equal_toIS2_ESt4hashIS2_ENS7_18_Mod_range_hashingENS7_20_Default_ranged_hashENS7_20_Prime_rehash_policyENS7_17_Hashtable_traitsILb0ELb0ELb1EEEE", !6, i64 0, !20, i64 8, !44, i64 16, !20, i64 24, !45, i64 32, !6, i64 48}
!44 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !6, i64 0}
!45 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !46, i64 0, !20, i64 8}
!46 = !{!"float", !7, i64 0}
!47 = !{!"_ZTSSt13unordered_mapImSt6vectorISt4pairIjdESaIS2_EESt4hashImESt8equal_toImESaIS1_IKmS4_EEE", !48, i64 0}
!48 = !{!"_ZTSSt10_HashtableImSt4pairIKmSt6vectorIS0_IjdESaIS3_EEESaIS6_ENSt8__detail10_Select1stESt8equal_toImESt4hashImENS8_18_Mod_range_hashingENS8_20_Default_ranged_hashENS8_20_Prime_rehash_policyENS8_17_Hashtable_traitsILb0ELb0ELb1EEEE", !6, i64 0, !20, i64 8, !44, i64 16, !20, i64 24, !45, i64 32, !6, i64 48}
!49 = !{!"_ZTSN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEE", !50, i64 0, !20, i64 8}
!50 = !{!"_ZTSN10pcg_detail15specific_streamImEE", !20, i64 0}
!51 = !{!"_ZTSSt25uniform_real_distributionIdE", !52, i64 0}
!52 = !{!"_ZTSNSt25uniform_real_distributionIdE10param_typeE", !10, i64 0, !10, i64 8}
!53 = !{!"_ZTSSt6vectorISt4pairIjjESaIS1_EE", !54, i64 0}
!54 = !{!"_ZTSSt12_Vector_baseISt4pairIjjESaIS1_EE", !55, i64 0}
!55 = !{!"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE12_Vector_implE", !56, i64 0}
!56 = !{!"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!57 = !{!58, !58, i64 0}
!58 = !{!"int", !7, i64 0}
!59 = distinct !{!59, !60}
!60 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3net16SpreadingProcessC2ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(800513) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, double noundef %2, double noundef %3, double noundef %4, double noundef %5) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN3net16StaticNetworkSIRC1ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(384) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, double noundef %2, double noundef %3, double noundef %4, double noundef %5)
  %7 = getelementptr inbounds i8, ptr %0, i64 384
  invoke void @_ZN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEC2Em(ptr noundef nonnull align 8 dereferenceable(16) %7, i64 noundef 42)
          to label %8 unwind label %18

8:                                                ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 400
  invoke void @_ZNSt25uniform_real_distributionIdEC2Edd(ptr noundef nonnull align 8 dereferenceable(16) %9, double noundef 0.000000e+00, double noundef 1.000000e+00)
          to label %10 unwind label %18

10:                                               ; preds = %8
  %11 = getelementptr inbounds i8, ptr %0, i64 800416
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %11, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIdSaIdEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  %12 = getelementptr inbounds i8, ptr %0, i64 800440
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %12, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #6
  %13 = getelementptr inbounds i8, ptr %0, i64 800464
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %13, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %13) #6
  %14 = getelementptr inbounds i8, ptr %0, i64 800488
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %14, i8 0, i64 24, i1 false)
  tail call void @_ZNSt6vectorISt4pairIjjESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %14) #6
  %15 = getelementptr inbounds i8, ptr %0, i64 800512
  store i8 0, ptr %15, align 8, !tbaa !5
  %16 = getelementptr inbounds i8, ptr %0, i64 416
  br label %20

17:                                               ; preds = %20
  ret void

18:                                               ; preds = %8, %6
  %19 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN3net16StaticNetworkSIRD2Ev(ptr noundef nonnull align 8 dereferenceable(384) %0) #6
  resume { ptr, i32 } %19

20:                                               ; preds = %10, %20
  %indvars.iv = phi i64 [ 0, %10 ], [ %indvars.iv.next, %20 ]
  %21 = trunc nuw nsw i64 %indvars.iv to i32
  %22 = uitofp nneg i32 %21 to double
  %23 = fadd double %22, 5.000000e-01
  %24 = fdiv double %23, 1.000000e+05
  %25 = tail call double @log(double noundef %24) #6
  %26 = fneg double %25
  %27 = getelementptr inbounds [100000 x double], ptr %16, i64 0, i64 %indvars.iv
  store double %26, ptr %27, align 8, !tbaa !55
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 100000
  br i1 %exitcond.not, label %17, label %20, !llvm.loop !56
}

declare void @_ZN3net16StaticNetworkSIRC1ERSt6vectorISt4pairIjjESaIS3_EEdddd(ptr noundef nonnull align 8 dereferenceable(384), ptr noundef nonnull align 8 dereferenceable(24), double noundef, double noundef, double noundef, double noundef) unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEC2Em(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt25uniform_real_distributionIdEC2Edd(ptr noundef nonnull align 8 dereferenceable(16), double noundef, double noundef) unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt4pairIjjESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @log(double noundef) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3net16StaticNetworkSIRD2Ev(ptr noundef nonnull align 8 dereferenceable(384)) unnamed_addr #5 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !16, i64 800512}
!6 = !{!"_ZTSN3net16SpreadingProcessE", !7, i64 0, !47, i64 384, !49, i64 400, !12, i64 416, !19, i64 800416, !27, i64 800440, !27, i64 800464, !51, i64 800488, !16, i64 800512}
!7 = !{!"_ZTSN3net16StaticNetworkSIRE", !8, i64 0, !15, i64 16, !15, i64 24, !15, i64 32, !15, i64 40, !16, i64 48, !16, i64 49, !16, i64 50, !16, i64 51, !17, i64 56, !18, i64 88, !19, i64 96, !23, i64 120, !27, i64 144, !31, i64 168, !27, i64 192, !35, i64 216, !45, i64 312, !18, i64 368, !18, i64 376}
!8 = !{!"_ZTSN3net7NetworkE", !9, i64 0}
!9 = !{!"_ZTSSt10shared_ptrISt6vectorIS0_IjSaIjEESaIS2_EEE", !10, i64 0}
!10 = !{!"_ZTSSt12__shared_ptrISt6vectorIS0_IjSaIjEESaIS2_EELN9__gnu_cxx12_Lock_policyE2EE", !11, i64 0, !14, i64 8}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt14__shared_countILN9__gnu_cxx12_Lock_policyE2EE", !11, i64 0}
!15 = !{!"double", !12, i64 0}
!16 = !{!"bool", !12, i64 0}
!17 = !{!"_ZTSN3net14HashPropensityE", !15, i64 0, !15, i64 8, !15, i64 16, !16, i64 24}
!18 = !{!"long", !12, i64 0}
!19 = !{!"_ZTSSt6vectorIdSaIdEE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!23 = !{!"_ZTSSt6vectorImSaImEE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseImSaImEE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!27 = !{!"_ZTSSt6vectorIjSaIjEE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!31 = !{!"_ZTSSt6vectorISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseISt13unordered_setIjSt4hashIjESt8equal_toIjESaIjEESaIS6_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!35 = !{!"_ZTSN3net10BinaryTreeE", !11, i64 0, !11, i64 8, !36, i64 16, !40, i64 40}
!36 = !{!"_ZTSSt6vectorIPN3net14BinaryTreeNodeESaIS2_EE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIPN3net14BinaryTreeNodeESaIS2_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!40 = !{!"_ZTSSt13unordered_mapIPN3net14BinaryTreeNodeEjSt4hashIS2_ESt8equal_toIS2_ESaISt4pairIKS2_jEEE", !41, i64 0}
!41 = !{!"_ZTSSt10_HashtableIPN3net14BinaryTreeNodeESt4pairIKS2_jESaIS5_ENSt8__detail10_Select1stESt8equal_toIS2_ESt4hashIS2_ENS7_18_Mod_range_hashingENS7_20_Default_ranged_hashENS7_20_Prime_rehash_policyENS7_17_Hashtable_traitsILb0ELb0ELb1EEEE", !11, i64 0, !18, i64 8, !42, i64 16, !18, i64 24, !43, i64 32, !11, i64 48}
!42 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !11, i64 0}
!43 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !44, i64 0, !18, i64 8}
!44 = !{!"float", !12, i64 0}
!45 = !{!"_ZTSSt13unordered_mapImSt6vectorISt4pairIjdESaIS2_EESt4hashImESt8equal_toImESaIS1_IKmS4_EEE", !46, i64 0}
!46 = !{!"_ZTSSt10_HashtableImSt4pairIKmSt6vectorIS0_IjdESaIS3_EEESaIS6_ENSt8__detail10_Select1stESt8equal_toImESt4hashImENS8_18_Mod_range_hashingENS8_20_Default_ranged_hashENS8_20_Prime_rehash_policyENS8_17_Hashtable_traitsILb0ELb0ELb1EEEE", !11, i64 0, !18, i64 8, !42, i64 16, !18, i64 24, !43, i64 32, !11, i64 48}
!47 = !{!"_ZTSN10pcg_detail6engineIjmNS_12xsh_rr_mixinIjmEELb1ENS_15specific_streamImEENS_18default_multiplierImEEEE", !48, i64 0, !18, i64 8}
!48 = !{!"_ZTSN10pcg_detail15specific_streamImEE", !18, i64 0}
!49 = !{!"_ZTSSt25uniform_real_distributionIdE", !50, i64 0}
!50 = !{!"_ZTSNSt25uniform_real_distributionIdE10param_typeE", !15, i64 0, !15, i64 8}
!51 = !{!"_ZTSSt6vectorISt4pairIjjESaIS1_EE", !52, i64 0}
!52 = !{!"_ZTSSt12_Vector_baseISt4pairIjjESaIS1_EE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE12_Vector_implE", !54, i64 0}
!54 = !{!"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!55 = !{!15, !15, i64 0}
!56 = distinct !{!56, !57}
!57 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass