; LLVM IR from xirc/cp-algorithm :: atcoder/abc115/D/main.ll (Z5solvev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local global i32, align 4
@X = external dso_local global i64, align 8
@M = external dso_local global %"class.std::vector", align 8
@B = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z5solvexx(i64 noundef, i64 noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5solvev() #0 {
  %1 = alloca i64, align 8
  %2 = alloca i64, align 8
  %3 = alloca i32, align 4
  %4 = load i32, ptr @N, align 4, !tbaa !5
  %5 = add nsw i32 %4, 1
  %6 = sext i32 %5 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr %1) #3
  store i64 0, ptr %1, align 8, !tbaa !9
  call void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %6, ptr noundef nonnull align 8 dereferenceable(8) %1)
  call void @llvm.lifetime.end.p0(i64 8, ptr %1) #3
  %7 = load i32, ptr @N, align 4, !tbaa !5
  %8 = add nsw i32 %7, 1
  %9 = sext i32 %8 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr %2) #3
  store i64 0, ptr %2, align 8, !tbaa !9
  call void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %9, ptr noundef nonnull align 8 dereferenceable(8) %2)
  call void @llvm.lifetime.end.p0(i64 8, ptr %2) #3
  %10 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef 0) #3
  store i64 1, ptr %10, align 8, !tbaa !9
  %11 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef 0) #3
  store i64 1, ptr %11, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 1, ptr %3, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %39, %0
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %14 = load i32, ptr @N, align 4, !tbaa !5
  %15 = add nsw i32 %14, 1
  %16 = icmp slt i32 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  br label %42

18:                                               ; preds = %12
  %19 = load i32, ptr %3, align 4, !tbaa !5
  %20 = sub nsw i32 %19, 1
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %21) #3
  %23 = load i64, ptr %22, align 8, !tbaa !9
  %24 = mul nsw i64 2, %23
  %25 = add nsw i64 %24, 3
  %26 = load i32, ptr %3, align 4, !tbaa !5
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %27) #3
  store i64 %25, ptr %28, align 8, !tbaa !9
  %29 = load i32, ptr %3, align 4, !tbaa !5
  %30 = sub nsw i32 %29, 1
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %31) #3
  %33 = load i64, ptr %32, align 8, !tbaa !9
  %34 = mul nsw i64 2, %33
  %35 = add nsw i64 %34, 1
  %36 = load i32, ptr %3, align 4, !tbaa !5
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %37) #3
  store i64 %35, ptr %38, align 8, !tbaa !9
  br label %39

39:                                               ; preds = %18
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %3, align 4, !tbaa !5
  br label %12, !llvm.loop !11

42:                                               ; preds = %17
  %43 = load i64, ptr @X, align 8, !tbaa !9
  %44 = load i32, ptr @N, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef i64 @_Z5solvexx(i64 noundef %43, i64 noundef %45)
  ret i64 %46
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 8 dereferenceable(8)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local local_unnamed_addr global i32, align 4
@X = external dso_local local_unnamed_addr global i64, align 8
@M = external dso_local global %"class.std::vector", align 8
@B = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_Z5solvexx(i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5solvev() local_unnamed_addr #0 {
  %1 = alloca i64, align 8
  %2 = alloca i64, align 8
  %3 = load i32, ptr @N, align 4, !tbaa !5
  %4 = add nsw i32 %3, 1
  %5 = sext i32 %4 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %1) #3
  store i64 0, ptr %1, align 8, !tbaa !9
  call void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %5, ptr noundef nonnull align 8 dereferenceable(8) %1)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %1) #3
  %6 = load i32, ptr @N, align 4, !tbaa !5
  %7 = add nsw i32 %6, 1
  %8 = sext i32 %7 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #3
  store i64 0, ptr %2, align 8, !tbaa !9
  call void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %8, ptr noundef nonnull align 8 dereferenceable(8) %2)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #3
  %9 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef 0) #3
  store i64 1, ptr %9, align 8, !tbaa !9
  %10 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef 0) #3
  store i64 1, ptr %10, align 8, !tbaa !9
  %11 = load i32, ptr @N, align 4, !tbaa !5
  %.not6 = icmp slt i32 %11, 1
  br i1 %.not6, label %.._crit_edge_crit_edge, label %.lr.ph

.._crit_edge_crit_edge:                           ; preds = %0
  %.pre = sext i32 %11 to i64
  br label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %.._crit_edge_crit_edge
  %.pre-phi = phi i64 [ %.pre, %.._crit_edge_crit_edge ], [ %26, %.lr.ph ]
  %12 = load i64, ptr @X, align 8, !tbaa !9
  %13 = call noundef i64 @_Z5solvexx(i64 noundef %12, i64 noundef %.pre-phi)
  ret i64 %13

.lr.ph:                                           ; preds = %0, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 1, %0 ]
  %14 = add nsw i64 %indvars.iv, -1
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %14) #3
  %16 = load i64, ptr %15, align 8, !tbaa !9
  %17 = shl nsw i64 %16, 1
  %18 = add nsw i64 %17, 3
  %19 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @M, i64 noundef %indvars.iv) #3
  store i64 %18, ptr %19, align 8, !tbaa !9
  %20 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %14) #3
  %21 = load i64, ptr %20, align 8, !tbaa !9
  %22 = shl nsw i64 %21, 1
  %23 = or disjoint i64 %22, 1
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @B, i64 noundef %indvars.iv) #3
  store i64 %23, ptr %24, align 8, !tbaa !9
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %25 = load i32, ptr @N, align 4, !tbaa !5
  %26 = sext i32 %25 to i64
  %.not.not = icmp slt i64 %indvars.iv, %26
  br i1 %.not.not, label %.lr.ph, label %._crit_edge, !llvm.loop !11
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIxSaIxEE6assignEmRKx(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: BDCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass