; LLVM IR from HarshCasper/NeoAlgo :: C-Plus-Plus/dp/townPlanning.ll (Z12countSetBitsi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z12countSetBitsi(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %5

5:                                                ; preds = %20, %1
  %6 = load i32, ptr %4, align 4, !tbaa !5
  %7 = sext i32 %6 to i64
  %8 = icmp ult i64 %7, 32
  br i1 %8, label %10, label %9

9:                                                ; preds = %5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  br label %23

10:                                               ; preds = %5
  %11 = load i32, ptr %2, align 4, !tbaa !5
  %12 = load i32, ptr %4, align 4, !tbaa !5
  %13 = shl i32 1, %12
  %14 = and i32 %11, %13
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %19

16:                                               ; preds = %10
  %17 = load i32, ptr %3, align 4, !tbaa !5
  %18 = add nsw i32 %17, 1
  store i32 %18, ptr %3, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %16, %10
  br label %20

20:                                               ; preds = %19
  %21 = load i32, ptr %4, align 4, !tbaa !5
  %22 = add nsw i32 %21, 1
  store i32 %22, ptr %4, align 4, !tbaa !5
  br label %5, !llvm.loop !9

23:                                               ; preds = %9
  %24 = load i32, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  ret i32 %24
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef i32 @_Z12countSetBitsi(i32 noundef %0) local_unnamed_addr #0 {
  %2 = and i32 %0, 1
  %3 = lshr i32 %0, 1
  %4 = and i32 %3, 1
  %spec.select.1 = add nuw nsw i32 %4, %2
  %5 = lshr i32 %0, 2
  %6 = and i32 %5, 1
  %spec.select.2 = add nuw nsw i32 %6, %spec.select.1
  %7 = lshr i32 %0, 3
  %8 = and i32 %7, 1
  %spec.select.3 = add nuw nsw i32 %8, %spec.select.2
  %9 = lshr i32 %0, 4
  %10 = and i32 %9, 1
  %spec.select.4 = add nuw nsw i32 %10, %spec.select.3
  %11 = lshr i32 %0, 5
  %12 = and i32 %11, 1
  %spec.select.5 = add nuw nsw i32 %12, %spec.select.4
  %13 = lshr i32 %0, 6
  %14 = and i32 %13, 1
  %spec.select.6 = add nuw nsw i32 %14, %spec.select.5
  %15 = lshr i32 %0, 7
  %16 = and i32 %15, 1
  %spec.select.7 = add nuw nsw i32 %16, %spec.select.6
  %17 = lshr i32 %0, 8
  %18 = and i32 %17, 1
  %spec.select.8 = add nuw nsw i32 %18, %spec.select.7
  %19 = lshr i32 %0, 9
  %20 = and i32 %19, 1
  %spec.select.9 = add nuw nsw i32 %20, %spec.select.8
  %21 = lshr i32 %0, 10
  %22 = and i32 %21, 1
  %spec.select.10 = add nuw nsw i32 %22, %spec.select.9
  %23 = lshr i32 %0, 11
  %24 = and i32 %23, 1
  %spec.select.11 = add nuw nsw i32 %24, %spec.select.10
  %25 = lshr i32 %0, 12
  %26 = and i32 %25, 1
  %spec.select.12 = add nuw nsw i32 %26, %spec.select.11
  %27 = lshr i32 %0, 13
  %28 = and i32 %27, 1
  %spec.select.13 = add nuw nsw i32 %28, %spec.select.12
  %29 = lshr i32 %0, 14
  %30 = and i32 %29, 1
  %spec.select.14 = add nuw nsw i32 %30, %spec.select.13
  %31 = lshr i32 %0, 15
  %32 = and i32 %31, 1
  %spec.select.15 = add nuw nsw i32 %32, %spec.select.14
  %33 = lshr i32 %0, 16
  %34 = and i32 %33, 1
  %spec.select.16 = add nuw nsw i32 %34, %spec.select.15
  %35 = lshr i32 %0, 17
  %36 = and i32 %35, 1
  %spec.select.17 = add nuw nsw i32 %36, %spec.select.16
  %37 = lshr i32 %0, 18
  %38 = and i32 %37, 1
  %spec.select.18 = add nuw nsw i32 %38, %spec.select.17
  %39 = lshr i32 %0, 19
  %40 = and i32 %39, 1
  %spec.select.19 = add nuw nsw i32 %40, %spec.select.18
  %41 = lshr i32 %0, 20
  %42 = and i32 %41, 1
  %spec.select.20 = add nuw nsw i32 %42, %spec.select.19
  %43 = lshr i32 %0, 21
  %44 = and i32 %43, 1
  %spec.select.21 = add nuw nsw i32 %44, %spec.select.20
  %45 = lshr i32 %0, 22
  %46 = and i32 %45, 1
  %spec.select.22 = add nuw nsw i32 %46, %spec.select.21
  %47 = lshr i32 %0, 23
  %48 = and i32 %47, 1
  %spec.select.23 = add nuw nsw i32 %48, %spec.select.22
  %49 = lshr i32 %0, 24
  %50 = and i32 %49, 1
  %spec.select.24 = add nuw nsw i32 %50, %spec.select.23
  %51 = lshr i32 %0, 25
  %52 = and i32 %51, 1
  %spec.select.25 = add nuw nsw i32 %52, %spec.select.24
  %53 = lshr i32 %0, 26
  %54 = and i32 %53, 1
  %spec.select.26 = add nuw nsw i32 %54, %spec.select.25
  %55 = lshr i32 %0, 27
  %56 = and i32 %55, 1
  %spec.select.27 = add nuw nsw i32 %56, %spec.select.26
  %57 = lshr i32 %0, 28
  %58 = and i32 %57, 1
  %spec.select.28 = add nuw nsw i32 %58, %spec.select.27
  %59 = lshr i32 %0, 29
  %60 = and i32 %59, 1
  %spec.select.29 = add nuw nsw i32 %60, %spec.select.28
  %61 = lshr i32 %0, 30
  %62 = and i32 %61, 1
  %spec.select.30 = add nuw nsw i32 %62, %spec.select.29
  %63 = lshr i32 %0, 31
  %spec.select.31 = add nuw nsw i32 %63, %spec.select.30
  ret i32 %spec.select.31
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LoopRotatePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass