; LLVM IR from xirc/cp-algorithm :: atcoder/abc156/D/main.ll (Z16init_combinationii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@factorial_inverse = external dso_local global %"class.std::vector", align 8
@inverse = external dso_local global %"class.std::vector", align 8
@combination = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z16init_combinationii(i32 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = add nsw i32 %10, 1
  %12 = sext i32 %11 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #3
  store i64 0, ptr %5, align 8, !tbaa !9
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %12, ptr noundef nonnull align 8 dereferenceable(8) %5)
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #3
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = add nsw i32 %13, 1
  %15 = sext i32 %14 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  store i64 0, ptr %6, align 8, !tbaa !9
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %15, ptr noundef nonnull align 8 dereferenceable(8) %6)
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %16 = load i32, ptr %4, align 4, !tbaa !5
  %17 = add nsw i32 %16, 1
  %18 = sext i32 %17 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store i64 0, ptr %7, align 8, !tbaa !9
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %18, ptr noundef nonnull align 8 dereferenceable(8) %7)
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  %19 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef 1) #3
  store i64 1, ptr %19, align 8, !tbaa !9
  %20 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef 0) #3
  store i64 1, ptr %20, align 8, !tbaa !9
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef 1) #3
  store i64 1, ptr %21, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 2, ptr %8, align 4, !tbaa !5
  br label %22

22:                                               ; preds = %57, %2
  %23 = load i32, ptr %8, align 4, !tbaa !5
  %24 = load i32, ptr %4, align 4, !tbaa !5
  %25 = add nsw i32 %24, 1
  %26 = icmp slt i32 %23, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %22
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %60

28:                                               ; preds = %22
  %29 = load i32, ptr %8, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = srem i64 1000000007, %30
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %31) #3
  %33 = load i64, ptr %32, align 8, !tbaa !9
  %34 = load i32, ptr %8, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = sdiv i64 1000000007, %35
  %37 = mul nsw i64 %33, %36
  %38 = srem i64 %37, 1000000007
  %39 = sub nsw i64 1000000007, %38
  %40 = load i32, ptr %8, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %41) #3
  store i64 %39, ptr %42, align 8, !tbaa !9
  %43 = load i32, ptr %8, align 4, !tbaa !5
  %44 = sub nsw i32 %43, 1
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %45) #3
  %47 = load i64, ptr %46, align 8, !tbaa !9
  %48 = load i32, ptr %8, align 4, !tbaa !5
  %49 = sext i32 %48 to i64
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %49) #3
  %51 = load i64, ptr %50, align 8, !tbaa !9
  %52 = mul nsw i64 %47, %51
  %53 = srem i64 %52, 1000000007
  %54 = load i32, ptr %8, align 4, !tbaa !5
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %55) #3
  store i64 %53, ptr %56, align 8, !tbaa !9
  br label %57

57:                                               ; preds = %28
  %58 = load i32, ptr %8, align 4, !tbaa !5
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %8, align 4, !tbaa !5
  br label %22, !llvm.loop !11

60:                                               ; preds = %27
  %61 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef 0) #3
  store i64 1, ptr %61, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 1, ptr %9, align 4, !tbaa !5
  br label %62

62:                                               ; preds = %90, %60
  %63 = load i32, ptr %9, align 4, !tbaa !5
  %64 = load i32, ptr %4, align 4, !tbaa !5
  %65 = add nsw i32 %64, 1
  %66 = icmp slt i32 %63, %65
  br i1 %66, label %68, label %67

67:                                               ; preds = %62
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %93

68:                                               ; preds = %62
  %69 = load i32, ptr %9, align 4, !tbaa !5
  %70 = sub nsw i32 %69, 1
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %71) #3
  %73 = load i64, ptr %72, align 8, !tbaa !9
  %74 = load i32, ptr %3, align 4, !tbaa !5
  %75 = load i32, ptr %9, align 4, !tbaa !5
  %76 = sub nsw i32 %74, %75
  %77 = add nsw i32 %76, 1
  %78 = sext i32 %77 to i64
  %79 = load i32, ptr %9, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %80) #3
  %82 = load i64, ptr %81, align 8, !tbaa !9
  %83 = mul nsw i64 %78, %82
  %84 = srem i64 %83, 1000000007
  %85 = mul nsw i64 %73, %84
  %86 = srem i64 %85, 1000000007
  %87 = load i32, ptr %9, align 4, !tbaa !5
  %88 = sext i32 %87 to i64
  %89 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %88) #3
  store i64 %86, ptr %89, align 8, !tbaa !9
  br label %90

90:                                               ; preds = %68
  %91 = load i32, ptr %9, align 4, !tbaa !5
  %92 = add nsw i32 %91, 1
  store i32 %92, ptr %9, align 4, !tbaa !5
  br label %62, !llvm.loop !13

93:                                               ; preds = %67
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long, std::allocator<long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@factorial_inverse = external dso_local global %"class.std::vector", align 8
@inverse = external dso_local global %"class.std::vector", align 8
@combination = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z16init_combinationii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = add i32 %1, 1
  %7 = sext i32 %6 to i64
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #3
  store i64 0, ptr %3, align 8, !tbaa !5
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %7, ptr noundef nonnull align 8 dereferenceable(8) %3)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #3
  store i64 0, ptr %4, align 8, !tbaa !5
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %7, ptr noundef nonnull align 8 dereferenceable(8) %4)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #3
  store i64 0, ptr %5, align 8, !tbaa !5
  call void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %7, ptr noundef nonnull align 8 dereferenceable(8) %5)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #3
  %8 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef 1) #3
  store i64 1, ptr %8, align 8, !tbaa !5
  %9 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef 0) #3
  store i64 1, ptr %9, align 8, !tbaa !5
  %10 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef 1) #3
  store i64 1, ptr %10, align 8, !tbaa !5
  %.not25 = icmp slt i32 %1, 2
  br i1 %.not25, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %2
  %wide.trip.count = zext i32 %6 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %2
  %11 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef 0) #3
  store i64 1, ptr %11, align 8, !tbaa !5
  %.not2227 = icmp slt i32 %1, 1
  br i1 %.not2227, label %._crit_edge31, label %.lr.ph30

.lr.ph30:                                         ; preds = %._crit_edge
  %12 = add i32 %0, 1
  %wide.trip.count36 = zext i32 %6 to i64
  br label %30

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i64 [ 2, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %13 = trunc nuw nsw i64 %indvars.iv to i32
  %14 = urem i32 1000000007, %13
  %.zext = zext nneg i32 %14 to i64
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %.zext) #3
  %16 = load i64, ptr %15, align 8, !tbaa !5
  %17 = udiv i32 1000000007, %13
  %.zext24 = zext nneg i32 %17 to i64
  %18 = mul nsw i64 %16, %.zext24
  %19 = srem i64 %18, 1000000007
  %20 = sub nsw i64 1000000007, %19
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %indvars.iv) #3
  store i64 %20, ptr %21, align 8, !tbaa !5
  %22 = add nsw i64 %indvars.iv, -1
  %23 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %22) #3
  %24 = load i64, ptr %23, align 8, !tbaa !5
  %25 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %indvars.iv) #3
  %26 = load i64, ptr %25, align 8, !tbaa !5
  %27 = mul nsw i64 %26, %24
  %28 = srem i64 %27, 1000000007
  %29 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @factorial_inverse, i64 noundef %indvars.iv) #3
  store i64 %28, ptr %29, align 8, !tbaa !5
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

._crit_edge31:                                    ; preds = %30, %._crit_edge
  ret void

30:                                               ; preds = %.lr.ph30, %30
  %indvars.iv33 = phi i64 [ 1, %.lr.ph30 ], [ %indvars.iv.next34, %30 ]
  %31 = add nsw i64 %indvars.iv33, -1
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %31) #3
  %33 = load i64, ptr %32, align 8, !tbaa !5
  %34 = trunc nuw nsw i64 %indvars.iv33 to i32
  %35 = sub i32 %12, %34
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @inverse, i64 noundef %indvars.iv33) #3
  %38 = load i64, ptr %37, align 8, !tbaa !5
  %39 = mul nsw i64 %38, %36
  %40 = srem i64 %39, 1000000007
  %41 = mul nsw i64 %40, %33
  %42 = srem i64 %41, 1000000007
  %43 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @combination, i64 noundef %indvars.iv33) #3
  store i64 %42, ptr %43, align 8, !tbaa !5
  %indvars.iv.next34 = add nuw nsw i64 %indvars.iv33, 1
  %exitcond37.not = icmp eq i64 %indvars.iv.next34, %wide.trip.count36
  br i1 %exitcond37.not, label %._crit_edge31, label %30, !llvm.loop !11
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIlSaIlEE6assignEmRKl(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass