; LLVM IR from xirc/cp-algorithm :: atcoder/abc128/C/main.ll (Z5solvev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::bitset" = type { %"struct.std::_Base_bitset" }
%"struct.std::_Base_bitset" = type { i64 }

@N = external dso_local global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z16is_all_turned_onRKSt6bitsetILm10EE(ptr noundef nonnull align 8 dereferenceable(8)) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z5solvev() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca %"class.std::bitset", align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  %5 = load i32, ptr @N, align 4, !tbaa !5
  %6 = shl i32 1, %5
  store i32 %6, ptr %1, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  store i32 0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %7

7:                                                ; preds = %20, %0
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = load i32, ptr %1, align 4, !tbaa !5
  %10 = icmp slt i32 %8, %9
  br i1 %10, label %12, label %11

11:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  br label %23

12:                                               ; preds = %7
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #2
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %14 = sext i32 %13 to i64
  call void @_ZNSt6bitsetILm10EEC2Ey(ptr noundef nonnull align 8 dereferenceable(8) %4, i64 noundef %14) #2
  %15 = call noundef zeroext i1 @_Z16is_all_turned_onRKSt6bitsetILm10EE(ptr noundef nonnull align 8 dereferenceable(8) %4)
  br i1 %15, label %16, label %19

16:                                               ; preds = %12
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = add nsw i32 %17, 1
  store i32 %18, ptr %2, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %16, %12
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #2
  br label %20

20:                                               ; preds = %19
  %21 = load i32, ptr %3, align 4, !tbaa !5
  %22 = add nsw i32 %21, 1
  store i32 %22, ptr %3, align 4, !tbaa !5
  br label %7, !llvm.loop !9

23:                                               ; preds = %11
  %24 = load i32, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret i32 %24
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6bitsetILm10EEC2Ey(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::bitset" = type { %"struct.std::_Base_bitset" }
%"struct.std::_Base_bitset" = type { i64 }

@N = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z16is_all_turned_onRKSt6bitsetILm10EE(ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z5solvev() local_unnamed_addr #0 {
  %1 = alloca %"class.std::bitset", align 8
  %2 = load i32, ptr @N, align 4, !tbaa !5
  %.not = icmp eq i32 %2, 31
  br i1 %.not, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %0
  %3 = shl nuw nsw i32 1, %2
  %wide.trip.count = zext nneg i32 %3 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %0
  %.06.lcssa = phi i32 [ 0, %0 ], [ %spec.select, %.lr.ph ]
  ret i32 %.06.lcssa

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %.067 = phi i32 [ 0, %.lr.ph.preheader ], [ %spec.select, %.lr.ph ]
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %1) #2
  call void @_ZNSt6bitsetILm10EEC2Ey(ptr noundef nonnull align 8 dereferenceable(8) %1, i64 noundef %indvars.iv) #2
  %4 = call noundef zeroext i1 @_Z16is_all_turned_onRKSt6bitsetILm10EE(ptr noundef nonnull align 8 dereferenceable(8) %1)
  %5 = zext i1 %4 to i32
  %spec.select = add nuw nsw i32 %.067, %5
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %1) #2
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6bitsetILm10EEC2Ey(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass