; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TileMap = type { i16, i16, i16, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @MEM_free(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local void @VDP_setTileMapDataRowEx(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) #2

declare ptr @unpackTileMap(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @VDP_setTileMapRowEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i32 noundef %7) #2 {
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i16, align 2
  %13 = alloca i16, align 2
  %14 = alloca i16, align 2
  %15 = alloca i16, align 2
  %16 = alloca i16, align 2
  %17 = alloca i32, align 4
  %18 = alloca i64, align 8
  %19 = alloca ptr, align 8
  %20 = alloca i32, align 4
  store i32 %0, ptr %10, align 4, !tbaa !5
  store ptr %1, ptr %11, align 8, !tbaa !9
  store i16 %2, ptr %12, align 2, !tbaa !11
  store i16 %3, ptr %13, align 2, !tbaa !11
  store i16 %4, ptr %14, align 2, !tbaa !11
  store i16 %5, ptr %15, align 2, !tbaa !11
  store i16 %6, ptr %16, align 2, !tbaa !11
  store i32 %7, ptr %17, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #3
  %21 = load i16, ptr %15, align 2, !tbaa !11
  %22 = load ptr, ptr %11, align 8, !tbaa !9
  %23 = getelementptr inbounds %struct.TileMap, ptr %22, i32 0, i32 1
  %24 = load i16, ptr %23, align 2, !tbaa !13
  %25 = call i64 @mulu(i16 noundef zeroext %21, i16 noundef zeroext %24)
  %26 = load i16, ptr %14, align 2, !tbaa !11
  %27 = zext i16 %26 to i64
  %28 = add i64 %25, %27
  store i64 %28, ptr %18, align 8, !tbaa !15
  %29 = load ptr, ptr %11, align 8, !tbaa !9
  %30 = getelementptr inbounds %struct.TileMap, ptr %29, i32 0, i32 0
  %31 = load i16, ptr %30, align 8, !tbaa !17
  %32 = zext i16 %31 to i32
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %56

34:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #3
  %35 = load ptr, ptr %11, align 8, !tbaa !9
  %36 = call ptr @unpackTileMap(ptr noundef %35, ptr noundef null)
  store ptr %36, ptr %19, align 8, !tbaa !9
  %37 = load ptr, ptr %19, align 8, !tbaa !9
  %38 = icmp eq ptr %37, null
  br i1 %38, label %39, label %40

39:                                               ; preds = %34
  store i8 0, ptr %9, align 1
  store i32 1, ptr %20, align 4
  br label %53

40:                                               ; preds = %34
  %41 = load i32, ptr %10, align 4, !tbaa !5
  %42 = load ptr, ptr %19, align 8, !tbaa !9
  %43 = getelementptr inbounds %struct.TileMap, ptr %42, i32 0, i32 3
  %44 = load ptr, ptr %43, align 8, !tbaa !18
  %45 = load i64, ptr %18, align 8, !tbaa !15
  %46 = getelementptr inbounds i16, ptr %44, i64 %45
  %47 = load i16, ptr %12, align 2, !tbaa !11
  %48 = load i16, ptr %13, align 2, !tbaa !11
  %49 = load i16, ptr %14, align 2, !tbaa !11
  %50 = load i16, ptr %16, align 2, !tbaa !11
  %51 = load i32, ptr %17, align 4, !tbaa !5
  call void @VDP_setTileMapDataRowEx(i32 noundef %41, ptr noundef %46, i16 noundef zeroext %47, i16 noundef zeroext %48, i16 noundef zeroext %49, i16 noundef zeroext %50, i32 noundef %51)
  %52 = load ptr, ptr %19, align 8, !tbaa !9
  call void @MEM_free(ptr noundef %52)
  store i32 0, ptr %20, align 4
  br label %53

53:                                               ; preds = %40, %39
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #3
  %54 = load i32, ptr %20, align 4
  switch i32 %54, label %69 [
    i32 0, label %55
  ]

55:                                               ; preds = %53
  br label %68

56:                                               ; preds = %8
  %57 = load i32, ptr %10, align 4, !tbaa !5
  %58 = load ptr, ptr %11, align 8, !tbaa !9
  %59 = getelementptr inbounds %struct.TileMap, ptr %58, i32 0, i32 3
  %60 = load ptr, ptr %59, align 8, !tbaa !18
  %61 = load i64, ptr %18, align 8, !tbaa !15
  %62 = getelementptr inbounds i16, ptr %60, i64 %61
  %63 = load i16, ptr %12, align 2, !tbaa !11
  %64 = load i16, ptr %13, align 2, !tbaa !11
  %65 = load i16, ptr %14, align 2, !tbaa !11
  %66 = load i16, ptr %16, align 2, !tbaa !11
  %67 = load i32, ptr %17, align 4, !tbaa !5
  call void @VDP_setTileMapDataRowEx(i32 noundef %57, ptr noundef %62, i16 noundef zeroext %63, i16 noundef zeroext %64, i16 noundef zeroext %65, i16 noundef zeroext %66, i32 noundef %67)
  br label %68

68:                                               ; preds = %56, %55
  store i8 1, ptr %9, align 1
  store i32 1, ptr %20, align 4
  br label %69

69:                                               ; preds = %68, %53
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #3
  %70 = load i8, ptr %9, align 1
  ret i8 %70
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !12, i64 2}
!14 = !{!"", !12, i64 0, !12, i64 2, !12, i64 4, !10, i64 8}
!15 = !{!16, !16, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!14, !12, i64 0}
!18 = !{!14, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @MEM_free(ptr noundef) local_unnamed_addr #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @VDP_setTileMapDataRowEx(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

declare ptr @unpackTileMap(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @VDP_setTileMapRowEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i32 noundef %7) local_unnamed_addr #1 {
  %9 = getelementptr inbounds i8, ptr %1, i64 2
  %10 = load i16, ptr %9, align 2, !tbaa !5
  %11 = tail call i64 @mulu(i16 noundef zeroext %5, i16 noundef zeroext %10) #2
  %12 = zext i16 %4 to i64
  %13 = add i64 %11, %12
  %14 = load i16, ptr %1, align 8, !tbaa !11
  %.not = icmp eq i16 %14, 0
  br i1 %.not, label %21, label %15

15:                                               ; preds = %8
  %16 = tail call ptr @unpackTileMap(ptr noundef nonnull %1, ptr noundef null) #2
  %.not26 = icmp eq ptr %16, null
  br i1 %.not26, label %.critedge, label %17

17:                                               ; preds = %15
  %18 = getelementptr inbounds i8, ptr %16, i64 8
  %19 = load ptr, ptr %18, align 8, !tbaa !12
  %20 = getelementptr inbounds i16, ptr %19, i64 %13
  tail call void @VDP_setTileMapDataRowEx(i32 noundef %0, ptr noundef %20, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %6, i32 noundef %7)
  tail call void @MEM_free(ptr noundef nonnull %16) #2
  br label %.critedge

21:                                               ; preds = %8
  %22 = getelementptr inbounds i8, ptr %1, i64 8
  %23 = load ptr, ptr %22, align 8, !tbaa !12
  %24 = getelementptr inbounds i16, ptr %23, i64 %13
  tail call void @VDP_setTileMapDataRowEx(i32 noundef %0, ptr noundef %24, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %6, i32 noundef %7)
  br label %.critedge

.critedge:                                        ; preds = %21, %17, %15
  %.1 = phi i8 [ 0, %15 ], [ 1, %17 ], [ 1, %21 ]
  ret i8 %.1
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 2}
!6 = !{!"", !7, i64 0, !7, i64 2, !7, i64 4, !10, i64 8}
!7 = !{!"short", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !7, i64 0}
!12 = !{!6, !10, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass