; LLVM IR from xirc/cp-algorithm :: atcoder/abc143/E/main.ll (Z5buildv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local global i32, align 4
@L = external dso_local global i32, align 4
@G = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6reducev() #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5buildv() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #3
  store i32 0, ptr %1, align 4, !tbaa !5
  br label %5

5:                                                ; preds = %17, %0
  %6 = load i32, ptr %1, align 4, !tbaa !5
  %7 = load i32, ptr @N, align 4, !tbaa !5
  %8 = icmp slt i32 %6, %7
  br i1 %8, label %10, label %9

9:                                                ; preds = %5
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #3
  br label %20

10:                                               ; preds = %5
  %11 = load i32, ptr %1, align 4, !tbaa !5
  %12 = sext i32 %11 to i64
  %13 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %12) #3
  %14 = load i32, ptr %1, align 4, !tbaa !5
  %15 = sext i32 %14 to i64
  %16 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %15) #3
  store i64 0, ptr %16, align 8, !tbaa !9
  br label %17

17:                                               ; preds = %10
  %18 = load i32, ptr %1, align 4, !tbaa !5
  %19 = add nsw i32 %18, 1
  store i32 %19, ptr %1, align 4, !tbaa !5
  br label %5, !llvm.loop !11

20:                                               ; preds = %9
  call void @_Z6reducev()
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %74, %20
  %22 = load i32, ptr %2, align 4, !tbaa !5
  %23 = load i32, ptr @N, align 4, !tbaa !5
  %24 = icmp slt i32 %22, %23
  br i1 %24, label %26, label %25

25:                                               ; preds = %21
  store i32 5, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #3
  br label %77

26:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %27

27:                                               ; preds = %70, %26
  %28 = load i32, ptr %4, align 4, !tbaa !5
  %29 = load i32, ptr @N, align 4, !tbaa !5
  %30 = icmp slt i32 %28, %29
  br i1 %30, label %32, label %31

31:                                               ; preds = %27
  store i32 8, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  br label %73

32:                                               ; preds = %27
  %33 = load i32, ptr %2, align 4, !tbaa !5
  %34 = load i32, ptr %4, align 4, !tbaa !5
  %35 = icmp eq i32 %33, %34
  br i1 %35, label %36, label %43

36:                                               ; preds = %32
  %37 = load i32, ptr %2, align 4, !tbaa !5
  %38 = sext i32 %37 to i64
  %39 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %38) #3
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %41) #3
  store i64 0, ptr %42, align 8, !tbaa !9
  br label %69

43:                                               ; preds = %32
  %44 = load i32, ptr %2, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %45) #3
  %47 = load i32, ptr %4, align 4, !tbaa !5
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #3
  %50 = load i64, ptr %49, align 8, !tbaa !9
  %51 = load i32, ptr @L, align 4, !tbaa !5
  %52 = sext i32 %51 to i64
  %53 = icmp sle i64 %50, %52
  br i1 %53, label %54, label %61

54:                                               ; preds = %43
  %55 = load i32, ptr %2, align 4, !tbaa !5
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %56) #3
  %58 = load i32, ptr %4, align 4, !tbaa !5
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %57, i64 noundef %59) #3
  store i64 1, ptr %60, align 8, !tbaa !9
  br label %68

61:                                               ; preds = %43
  %62 = load i32, ptr %2, align 4, !tbaa !5
  %63 = sext i32 %62 to i64
  %64 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %63) #3
  %65 = load i32, ptr %4, align 4, !tbaa !5
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %64, i64 noundef %66) #3
  store i64 10000000000000000, ptr %67, align 8, !tbaa !9
  br label %68

68:                                               ; preds = %61, %54
  br label %69

69:                                               ; preds = %68, %36
  br label %70

70:                                               ; preds = %69
  %71 = load i32, ptr %4, align 4, !tbaa !5
  %72 = add nsw i32 %71, 1
  store i32 %72, ptr %4, align 4, !tbaa !5
  br label %27, !llvm.loop !13

73:                                               ; preds = %31
  br label %74

74:                                               ; preds = %73
  %75 = load i32, ptr %2, align 4, !tbaa !5
  %76 = add nsw i32 %75, 1
  store i32 %76, ptr %2, align 4, !tbaa !5
  br label %21, !llvm.loop !14

77:                                               ; preds = %25
  call void @_Z6reducev()
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@N = external dso_local local_unnamed_addr global i32, align 4
@L = external dso_local local_unnamed_addr global i32, align 4
@G = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6reducev() local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5buildv() local_unnamed_addr #0 {
  %1 = load i32, ptr @N, align 4, !tbaa !5
  %2 = icmp sgt i32 %1, 0
  br i1 %2, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %0
  tail call void @_Z6reducev()
  %3 = load i32, ptr @N, align 4, !tbaa !5
  %4 = icmp sgt i32 %3, 0
  br i1 %4, label %.preheader, label %._crit_edge25

.lr.ph:                                           ; preds = %0, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
  %5 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %indvars.iv) #2
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %indvars.iv) #2
  store i64 0, ptr %6, align 8, !tbaa !9
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %7 = load i32, ptr @N, align 4, !tbaa !5
  %8 = sext i32 %7 to i64
  %9 = icmp slt i64 %indvars.iv.next, %8
  br i1 %9, label %.lr.ph, label %._crit_edge, !llvm.loop !11

.preheader:                                       ; preds = %._crit_edge, %._crit_edge23
  %10 = phi i32 [ %12, %._crit_edge23 ], [ %3, %._crit_edge ]
  %indvars.iv31 = phi i64 [ %indvars.iv.next32, %._crit_edge23 ], [ 0, %._crit_edge ]
  %11 = icmp sgt i32 %10, 0
  br i1 %11, label %.lr.ph22, label %.preheader.._crit_edge23_crit_edge

.preheader.._crit_edge23_crit_edge:               ; preds = %.preheader
  %.pre = sext i32 %10 to i64
  br label %._crit_edge23

._crit_edge25:                                    ; preds = %._crit_edge23, %._crit_edge
  tail call void @_Z6reducev()
  ret void

._crit_edge23:                                    ; preds = %27, %.preheader.._crit_edge23_crit_edge
  %.pre-phi = phi i64 [ %.pre, %.preheader.._crit_edge23_crit_edge ], [ %29, %27 ]
  %12 = phi i32 [ %10, %.preheader.._crit_edge23_crit_edge ], [ %28, %27 ]
  %indvars.iv.next32 = add nuw nsw i64 %indvars.iv31, 1
  %13 = icmp slt i64 %indvars.iv.next32, %.pre-phi
  br i1 %13, label %.preheader, label %._crit_edge25, !llvm.loop !13

.lr.ph22:                                         ; preds = %.preheader, %27
  %indvars.iv28 = phi i64 [ %indvars.iv.next29, %27 ], [ 0, %.preheader ]
  %14 = icmp eq i64 %indvars.iv31, %indvars.iv28
  %15 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %indvars.iv31) #2
  br i1 %14, label %16, label %18

16:                                               ; preds = %.lr.ph22
  %17 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %indvars.iv31) #2
  store i64 0, ptr %17, align 8, !tbaa !9
  br label %27

18:                                               ; preds = %.lr.ph22
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %indvars.iv28) #2
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = load i32, ptr @L, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %.not = icmp sgt i64 %20, %22
  %23 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %indvars.iv31) #2
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %indvars.iv28) #2
  br i1 %.not, label %26, label %25

25:                                               ; preds = %18
  store i64 1, ptr %24, align 8, !tbaa !9
  br label %27

26:                                               ; preds = %18
  store i64 10000000000000000, ptr %24, align 8, !tbaa !9
  br label %27

27:                                               ; preds = %16, %26, %25
  %indvars.iv.next29 = add nuw nsw i64 %indvars.iv28, 1
  %28 = load i32, ptr @N, align 4, !tbaa !5
  %29 = sext i32 %28 to i64
  %30 = icmp slt i64 %indvars.iv.next29, %29
  br i1 %30, label %.lr.ph22, label %._crit_edge23, !llvm.loop !15
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12, !14}
!14 = !{!"llvm.loop.unswitch.partial.disable"}
!15 = distinct !{!15, !12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SCCPPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass