; LLVM IR from xirc/cp-algorithm :: atcoder/abc037/D/main.ll (Z3dfsii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@H = external dso_local global i32, align 4
@W = external dso_local global i32, align 4
@A = external dso_local global %"class.std::vector", align 8
@DP = external dso_local global %"class.std::vector.0", align 8
@dy = external dso_local global %"class.std::vector.5", align 8
@dx = external dso_local global %"class.std::vector.5", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z3dfsii(i32 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = sext i32 %10 to i64
  %12 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %11) #3
  %13 = load i32, ptr %5, align 4, !tbaa !5
  %14 = sext i32 %13 to i64
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %14) #3
  %16 = load i64, ptr %15, align 8, !tbaa !9
  %17 = icmp sge i64 %16, 0
  br i1 %17, label %18, label %26

18:                                               ; preds = %2
  %19 = load i32, ptr %4, align 4, !tbaa !5
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %20) #3
  %22 = load i32, ptr %5, align 4, !tbaa !5
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #3
  %25 = load i64, ptr %24, align 8, !tbaa !9
  store i64 %25, ptr %3, align 8
  br label %116

26:                                               ; preds = %2
  %27 = load i32, ptr %4, align 4, !tbaa !5
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %28) #3
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #3
  store i64 1, ptr %32, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %33

33:                                               ; preds = %105, %26
  %34 = load i32, ptr %6, align 4, !tbaa !5
  %35 = icmp slt i32 %34, 4
  br i1 %35, label %37, label %36

36:                                               ; preds = %33
  store i32 2, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %108

37:                                               ; preds = %33
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %38 = load i32, ptr %4, align 4, !tbaa !5
  %39 = load i32, ptr %6, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dy, i64 noundef %40) #3
  %42 = load i32, ptr %41, align 4, !tbaa !5
  %43 = add nsw i32 %38, %42
  store i32 %43, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %44 = load i32, ptr %5, align 4, !tbaa !5
  %45 = load i32, ptr %6, align 4, !tbaa !5
  %46 = sext i32 %45 to i64
  %47 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dx, i64 noundef %46) #3
  %48 = load i32, ptr %47, align 4, !tbaa !5
  %49 = add nsw i32 %44, %48
  store i32 %49, ptr %9, align 4, !tbaa !5
  %50 = load i32, ptr %8, align 4, !tbaa !5
  %51 = icmp slt i32 %50, 0
  br i1 %51, label %56, label %52

52:                                               ; preds = %37
  %53 = load i32, ptr %8, align 4, !tbaa !5
  %54 = load i32, ptr @H, align 4, !tbaa !5
  %55 = icmp sge i32 %53, %54
  br i1 %55, label %56, label %57

56:                                               ; preds = %52, %37
  store i32 4, ptr %7, align 4
  br label %102

57:                                               ; preds = %52
  %58 = load i32, ptr %9, align 4, !tbaa !5
  %59 = icmp slt i32 %58, 0
  br i1 %59, label %64, label %60

60:                                               ; preds = %57
  %61 = load i32, ptr %9, align 4, !tbaa !5
  %62 = load i32, ptr @W, align 4, !tbaa !5
  %63 = icmp sge i32 %61, %62
  br i1 %63, label %64, label %65

64:                                               ; preds = %60, %57
  store i32 4, ptr %7, align 4
  br label %102

65:                                               ; preds = %60
  %66 = load i32, ptr %8, align 4, !tbaa !5
  %67 = sext i32 %66 to i64
  %68 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %67) #3
  %69 = load i32, ptr %9, align 4, !tbaa !5
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %70) #3
  %72 = load i32, ptr %71, align 4, !tbaa !5
  %73 = load i32, ptr %4, align 4, !tbaa !5
  %74 = sext i32 %73 to i64
  %75 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %74) #3
  %76 = load i32, ptr %5, align 4, !tbaa !5
  %77 = sext i32 %76 to i64
  %78 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %75, i64 noundef %77) #3
  %79 = load i32, ptr %78, align 4, !tbaa !5
  %80 = icmp slt i32 %72, %79
  br i1 %80, label %81, label %101

81:                                               ; preds = %65
  %82 = load i32, ptr %8, align 4, !tbaa !5
  %83 = load i32, ptr %9, align 4, !tbaa !5
  %84 = call noundef i64 @_Z3dfsii(i32 noundef %82, i32 noundef %83)
  %85 = load i32, ptr %4, align 4, !tbaa !5
  %86 = sext i32 %85 to i64
  %87 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %86) #3
  %88 = load i32, ptr %5, align 4, !tbaa !5
  %89 = sext i32 %88 to i64
  %90 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %87, i64 noundef %89) #3
  %91 = load i64, ptr %90, align 8, !tbaa !9
  %92 = add nsw i64 %91, %84
  store i64 %92, ptr %90, align 8, !tbaa !9
  %93 = load i32, ptr %4, align 4, !tbaa !5
  %94 = sext i32 %93 to i64
  %95 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %94) #3
  %96 = load i32, ptr %5, align 4, !tbaa !5
  %97 = sext i32 %96 to i64
  %98 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %95, i64 noundef %97) #3
  %99 = load i64, ptr %98, align 8, !tbaa !9
  %100 = srem i64 %99, 1000000007
  store i64 %100, ptr %98, align 8, !tbaa !9
  br label %101

101:                                              ; preds = %81, %65
  store i32 0, ptr %7, align 4
  br label %102

102:                                              ; preds = %101, %64, %56
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %103 = load i32, ptr %7, align 4
  switch i32 %103, label %118 [
    i32 0, label %104
    i32 4, label %105
  ]

104:                                              ; preds = %102
  br label %105

105:                                              ; preds = %104, %102
  %106 = load i32, ptr %6, align 4, !tbaa !5
  %107 = add nsw i32 %106, 1
  store i32 %107, ptr %6, align 4, !tbaa !5
  br label %33, !llvm.loop !11

108:                                              ; preds = %36
  %109 = load i32, ptr %4, align 4, !tbaa !5
  %110 = sext i32 %109 to i64
  %111 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %110) #3
  %112 = load i32, ptr %5, align 4, !tbaa !5
  %113 = sext i32 %112 to i64
  %114 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %111, i64 noundef %113) #3
  %115 = load i64, ptr %114, align 8, !tbaa !9
  store i64 %115, ptr %3, align 8
  br label %116

116:                                              ; preds = %108, %18
  %117 = load i64, ptr %3, align 8
  ret i64 %117

118:                                              ; preds = %102
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<long>, std::allocator<std::vector<long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@H = external dso_local local_unnamed_addr global i32, align 4
@W = external dso_local local_unnamed_addr global i32, align 4
@A = external dso_local global %"class.std::vector", align 8
@DP = external dso_local global %"class.std::vector.0", align 8
@dy = external dso_local global %"class.std::vector.5", align 8
@dx = external dso_local global %"class.std::vector.5", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z3dfsii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = sext i32 %0 to i64
  %4 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %5 = sext i32 %1 to i64
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %5) #1
  %7 = load i64, ptr %6, align 8, !tbaa !5
  %8 = icmp sgt i64 %7, -1
  %9 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %10 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %5) #1
  br i1 %8, label %142, label %11

11:                                               ; preds = %2
  store i64 1, ptr %10, align 8, !tbaa !5
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dy, i64 noundef 0) #1
  %13 = load i32, ptr %12, align 4, !tbaa !9
  %14 = add nsw i32 %13, %0
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dx, i64 noundef 0) #1
  %16 = load i32, ptr %15, align 4, !tbaa !9
  %17 = add nsw i32 %16, %1
  %18 = icmp sgt i32 %14, -1
  %19 = load i32, ptr @H, align 4
  %.not = icmp slt i32 %14, %19
  %or.cond = select i1 %18, i1 %.not, i1 false
  br i1 %or.cond, label %20, label %43

20:                                               ; preds = %11
  %21 = icmp sgt i32 %17, -1
  %22 = load i32, ptr @W, align 4
  %.not32 = icmp slt i32 %17, %22
  %or.cond33 = select i1 %21, i1 %.not32, i1 false
  br i1 %or.cond33, label %23, label %43

23:                                               ; preds = %20
  %24 = zext nneg i32 %14 to i64
  %25 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %24) #1
  %26 = zext nneg i32 %17 to i64
  %27 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %26) #1
  %28 = load i32, ptr %27, align 4, !tbaa !9
  %29 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %3) #1
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %5) #1
  %31 = load i32, ptr %30, align 4, !tbaa !9
  %32 = icmp slt i32 %28, %31
  br i1 %32, label %33, label %43

33:                                               ; preds = %23
  %34 = tail call noundef i64 @_Z3dfsii(i32 noundef %14, i32 noundef %17)
  %35 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %36 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %5) #1
  %37 = load i64, ptr %36, align 8, !tbaa !5
  %38 = add nsw i64 %37, %34
  store i64 %38, ptr %36, align 8, !tbaa !5
  %39 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %40 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %5) #1
  %41 = load i64, ptr %40, align 8, !tbaa !5
  %42 = srem i64 %41, 1000000007
  store i64 %42, ptr %40, align 8, !tbaa !5
  br label %43

43:                                               ; preds = %23, %33, %20, %11
  %44 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dy, i64 noundef 1) #1
  %45 = load i32, ptr %44, align 4, !tbaa !9
  %46 = add nsw i32 %45, %0
  %47 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dx, i64 noundef 1) #1
  %48 = load i32, ptr %47, align 4, !tbaa !9
  %49 = add nsw i32 %48, %1
  %50 = icmp sgt i32 %46, -1
  %51 = load i32, ptr @H, align 4
  %.not.1 = icmp slt i32 %46, %51
  %or.cond.1 = select i1 %50, i1 %.not.1, i1 false
  br i1 %or.cond.1, label %52, label %75

52:                                               ; preds = %43
  %53 = icmp sgt i32 %49, -1
  %54 = load i32, ptr @W, align 4
  %.not32.1 = icmp slt i32 %49, %54
  %or.cond33.1 = select i1 %53, i1 %.not32.1, i1 false
  br i1 %or.cond33.1, label %55, label %75

55:                                               ; preds = %52
  %56 = zext nneg i32 %46 to i64
  %57 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %56) #1
  %58 = zext nneg i32 %49 to i64
  %59 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %57, i64 noundef %58) #1
  %60 = load i32, ptr %59, align 4, !tbaa !9
  %61 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %3) #1
  %62 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %61, i64 noundef %5) #1
  %63 = load i32, ptr %62, align 4, !tbaa !9
  %64 = icmp slt i32 %60, %63
  br i1 %64, label %65, label %75

65:                                               ; preds = %55
  %66 = tail call noundef i64 @_Z3dfsii(i32 noundef %46, i32 noundef %49)
  %67 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %68 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %67, i64 noundef %5) #1
  %69 = load i64, ptr %68, align 8, !tbaa !5
  %70 = add nsw i64 %69, %66
  store i64 %70, ptr %68, align 8, !tbaa !5
  %71 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %72 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %71, i64 noundef %5) #1
  %73 = load i64, ptr %72, align 8, !tbaa !5
  %74 = srem i64 %73, 1000000007
  store i64 %74, ptr %72, align 8, !tbaa !5
  br label %75

75:                                               ; preds = %65, %55, %52, %43
  %76 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dy, i64 noundef 2) #1
  %77 = load i32, ptr %76, align 4, !tbaa !9
  %78 = add nsw i32 %77, %0
  %79 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dx, i64 noundef 2) #1
  %80 = load i32, ptr %79, align 4, !tbaa !9
  %81 = add nsw i32 %80, %1
  %82 = icmp sgt i32 %78, -1
  %83 = load i32, ptr @H, align 4
  %.not.2 = icmp slt i32 %78, %83
  %or.cond.2 = select i1 %82, i1 %.not.2, i1 false
  br i1 %or.cond.2, label %84, label %107

84:                                               ; preds = %75
  %85 = icmp sgt i32 %81, -1
  %86 = load i32, ptr @W, align 4
  %.not32.2 = icmp slt i32 %81, %86
  %or.cond33.2 = select i1 %85, i1 %.not32.2, i1 false
  br i1 %or.cond33.2, label %87, label %107

87:                                               ; preds = %84
  %88 = zext nneg i32 %78 to i64
  %89 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %88) #1
  %90 = zext nneg i32 %81 to i64
  %91 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %89, i64 noundef %90) #1
  %92 = load i32, ptr %91, align 4, !tbaa !9
  %93 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %3) #1
  %94 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %93, i64 noundef %5) #1
  %95 = load i32, ptr %94, align 4, !tbaa !9
  %96 = icmp slt i32 %92, %95
  br i1 %96, label %97, label %107

97:                                               ; preds = %87
  %98 = tail call noundef i64 @_Z3dfsii(i32 noundef %78, i32 noundef %81)
  %99 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %100 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %99, i64 noundef %5) #1
  %101 = load i64, ptr %100, align 8, !tbaa !5
  %102 = add nsw i64 %101, %98
  store i64 %102, ptr %100, align 8, !tbaa !5
  %103 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %104 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %103, i64 noundef %5) #1
  %105 = load i64, ptr %104, align 8, !tbaa !5
  %106 = srem i64 %105, 1000000007
  store i64 %106, ptr %104, align 8, !tbaa !5
  br label %107

107:                                              ; preds = %97, %87, %84, %75
  %108 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dy, i64 noundef 3) #1
  %109 = load i32, ptr %108, align 4, !tbaa !9
  %110 = add nsw i32 %109, %0
  %111 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @dx, i64 noundef 3) #1
  %112 = load i32, ptr %111, align 4, !tbaa !9
  %113 = add nsw i32 %112, %1
  %114 = icmp sgt i32 %110, -1
  %115 = load i32, ptr @H, align 4
  %.not.3 = icmp slt i32 %110, %115
  %or.cond.3 = select i1 %114, i1 %.not.3, i1 false
  br i1 %or.cond.3, label %116, label %139

116:                                              ; preds = %107
  %117 = icmp sgt i32 %113, -1
  %118 = load i32, ptr @W, align 4
  %.not32.3 = icmp slt i32 %113, %118
  %or.cond33.3 = select i1 %117, i1 %.not32.3, i1 false
  br i1 %or.cond33.3, label %119, label %139

119:                                              ; preds = %116
  %120 = zext nneg i32 %110 to i64
  %121 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %120) #1
  %122 = zext nneg i32 %113 to i64
  %123 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %121, i64 noundef %122) #1
  %124 = load i32, ptr %123, align 4, !tbaa !9
  %125 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @A, i64 noundef %3) #1
  %126 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %125, i64 noundef %5) #1
  %127 = load i32, ptr %126, align 4, !tbaa !9
  %128 = icmp slt i32 %124, %127
  br i1 %128, label %129, label %139

129:                                              ; preds = %119
  %130 = tail call noundef i64 @_Z3dfsii(i32 noundef %110, i32 noundef %113)
  %131 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %132 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %131, i64 noundef %5) #1
  %133 = load i64, ptr %132, align 8, !tbaa !5
  %134 = add nsw i64 %133, %130
  store i64 %134, ptr %132, align 8, !tbaa !5
  %135 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %136 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %135, i64 noundef %5) #1
  %137 = load i64, ptr %136, align 8, !tbaa !5
  %138 = srem i64 %137, 1000000007
  store i64 %138, ptr %136, align 8, !tbaa !5
  br label %139

139:                                              ; preds = %129, %119, %116, %107
  %140 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @DP, i64 noundef %3) #1
  %141 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %140, i64 noundef %5) #1
  br label %142

142:                                              ; preds = %2, %139
  %.0.in = phi ptr [ %141, %139 ], [ %10, %2 ]
  %.0 = load i64, ptr %.0.in, align 8, !tbaa !5
  ret i64 %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass