; LLVM IR from xirc/cp-algorithm :: aoj/ALDS1/ALDS13A/main.ll (Z9can_placeii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.std::_Bit_reference" = type { ptr, i64 }

@G = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z9can_placeii(i32 noundef %0, i32 noundef %1) #2 {
  %3 = alloca i1, align 1
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca %"struct.std::_Bit_reference", align 8
  %9 = alloca %"struct.std::_Bit_reference", align 8
  %10 = alloca %"struct.std::_Bit_reference", align 8
  %11 = alloca %"struct.std::_Bit_reference", align 8
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 -7, ptr %6, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %149, %2
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = icmp slt i32 %13, 8
  br i1 %14, label %16, label %15

15:                                               ; preds = %12
  store i32 2, ptr %7, align 4
  br label %152

16:                                               ; preds = %12
  %17 = load i32, ptr %5, align 4, !tbaa !5
  %18 = load i32, ptr %6, align 4, !tbaa !5
  %19 = add nsw i32 %17, %18
  %20 = icmp sge i32 %19, 0
  call void @llvm.lifetime.start.p0(i64 16, ptr %8) #3
  br i1 %20, label %21, label %40

21:                                               ; preds = %16
  %22 = load i32, ptr %5, align 4, !tbaa !5
  %23 = load i32, ptr %6, align 4, !tbaa !5
  %24 = add nsw i32 %22, %23
  %25 = icmp slt i32 %24, 8
  br i1 %25, label %26, label %40

26:                                               ; preds = %21
  %27 = load i32, ptr %4, align 4, !tbaa !5
  %28 = sext i32 %27 to i64
  %29 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %28) #3
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = load i32, ptr %6, align 4, !tbaa !5
  %32 = add nsw i32 %30, %31
  %33 = sext i32 %32 to i64
  %34 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %29, i64 noundef %33)
  %35 = getelementptr inbounds { ptr, i64 }, ptr %8, i32 0, i32 0
  %36 = extractvalue { ptr, i64 } %34, 0
  store ptr %36, ptr %35, align 8
  %37 = getelementptr inbounds { ptr, i64 }, ptr %8, i32 0, i32 1
  %38 = extractvalue { ptr, i64 } %34, 1
  store i64 %38, ptr %37, align 8
  %39 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %8) #3
  br label %40

40:                                               ; preds = %26, %21, %16
  %41 = phi i1 [ false, %21 ], [ false, %16 ], [ %39, %26 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr %8) #3
  br i1 %41, label %42, label %43

42:                                               ; preds = %40
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %152

43:                                               ; preds = %40
  %44 = load i32, ptr %4, align 4, !tbaa !5
  %45 = load i32, ptr %6, align 4, !tbaa !5
  %46 = add nsw i32 %44, %45
  %47 = icmp sge i32 %46, 0
  call void @llvm.lifetime.start.p0(i64 16, ptr %9) #3
  br i1 %47, label %48, label %67

48:                                               ; preds = %43
  %49 = load i32, ptr %4, align 4, !tbaa !5
  %50 = load i32, ptr %6, align 4, !tbaa !5
  %51 = add nsw i32 %49, %50
  %52 = icmp slt i32 %51, 8
  br i1 %52, label %53, label %67

53:                                               ; preds = %48
  %54 = load i32, ptr %4, align 4, !tbaa !5
  %55 = load i32, ptr %6, align 4, !tbaa !5
  %56 = add nsw i32 %54, %55
  %57 = sext i32 %56 to i64
  %58 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %57) #3
  %59 = load i32, ptr %5, align 4, !tbaa !5
  %60 = sext i32 %59 to i64
  %61 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %58, i64 noundef %60)
  %62 = getelementptr inbounds { ptr, i64 }, ptr %9, i32 0, i32 0
  %63 = extractvalue { ptr, i64 } %61, 0
  store ptr %63, ptr %62, align 8
  %64 = getelementptr inbounds { ptr, i64 }, ptr %9, i32 0, i32 1
  %65 = extractvalue { ptr, i64 } %61, 1
  store i64 %65, ptr %64, align 8
  %66 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %9) #3
  br label %67

67:                                               ; preds = %53, %48, %43
  %68 = phi i1 [ false, %48 ], [ false, %43 ], [ %66, %53 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr %9) #3
  br i1 %68, label %69, label %70

69:                                               ; preds = %67
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %152

70:                                               ; preds = %67
  %71 = load i32, ptr %5, align 4, !tbaa !5
  %72 = load i32, ptr %6, align 4, !tbaa !5
  %73 = add nsw i32 %71, %72
  %74 = icmp sge i32 %73, 0
  call void @llvm.lifetime.start.p0(i64 16, ptr %10) #3
  br i1 %74, label %75, label %106

75:                                               ; preds = %70
  %76 = load i32, ptr %5, align 4, !tbaa !5
  %77 = load i32, ptr %6, align 4, !tbaa !5
  %78 = add nsw i32 %76, %77
  %79 = icmp slt i32 %78, 8
  br i1 %79, label %80, label %106

80:                                               ; preds = %75
  %81 = load i32, ptr %4, align 4, !tbaa !5
  %82 = load i32, ptr %6, align 4, !tbaa !5
  %83 = add nsw i32 %81, %82
  %84 = icmp sge i32 %83, 0
  br i1 %84, label %85, label %106

85:                                               ; preds = %80
  %86 = load i32, ptr %4, align 4, !tbaa !5
  %87 = load i32, ptr %6, align 4, !tbaa !5
  %88 = add nsw i32 %86, %87
  %89 = icmp slt i32 %88, 8
  br i1 %89, label %90, label %106

90:                                               ; preds = %85
  %91 = load i32, ptr %4, align 4, !tbaa !5
  %92 = load i32, ptr %6, align 4, !tbaa !5
  %93 = add nsw i32 %91, %92
  %94 = sext i32 %93 to i64
  %95 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %94) #3
  %96 = load i32, ptr %5, align 4, !tbaa !5
  %97 = load i32, ptr %6, align 4, !tbaa !5
  %98 = add nsw i32 %96, %97
  %99 = sext i32 %98 to i64
  %100 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %95, i64 noundef %99)
  %101 = getelementptr inbounds { ptr, i64 }, ptr %10, i32 0, i32 0
  %102 = extractvalue { ptr, i64 } %100, 0
  store ptr %102, ptr %101, align 8
  %103 = getelementptr inbounds { ptr, i64 }, ptr %10, i32 0, i32 1
  %104 = extractvalue { ptr, i64 } %100, 1
  store i64 %104, ptr %103, align 8
  %105 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %10) #3
  br label %106

106:                                              ; preds = %90, %85, %80, %75, %70
  %107 = phi i1 [ false, %85 ], [ false, %80 ], [ false, %75 ], [ false, %70 ], [ %105, %90 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr %10) #3
  br i1 %107, label %108, label %109

108:                                              ; preds = %106
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %152

109:                                              ; preds = %106
  %110 = load i32, ptr %5, align 4, !tbaa !5
  %111 = load i32, ptr %6, align 4, !tbaa !5
  %112 = add nsw i32 %110, %111
  %113 = icmp sge i32 %112, 0
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #3
  br i1 %113, label %114, label %145

114:                                              ; preds = %109
  %115 = load i32, ptr %5, align 4, !tbaa !5
  %116 = load i32, ptr %6, align 4, !tbaa !5
  %117 = add nsw i32 %115, %116
  %118 = icmp slt i32 %117, 8
  br i1 %118, label %119, label %145

119:                                              ; preds = %114
  %120 = load i32, ptr %4, align 4, !tbaa !5
  %121 = load i32, ptr %6, align 4, !tbaa !5
  %122 = sub nsw i32 %120, %121
  %123 = icmp sge i32 %122, 0
  br i1 %123, label %124, label %145

124:                                              ; preds = %119
  %125 = load i32, ptr %4, align 4, !tbaa !5
  %126 = load i32, ptr %6, align 4, !tbaa !5
  %127 = sub nsw i32 %125, %126
  %128 = icmp slt i32 %127, 8
  br i1 %128, label %129, label %145

129:                                              ; preds = %124
  %130 = load i32, ptr %4, align 4, !tbaa !5
  %131 = load i32, ptr %6, align 4, !tbaa !5
  %132 = sub nsw i32 %130, %131
  %133 = sext i32 %132 to i64
  %134 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %133) #3
  %135 = load i32, ptr %5, align 4, !tbaa !5
  %136 = load i32, ptr %6, align 4, !tbaa !5
  %137 = add nsw i32 %135, %136
  %138 = sext i32 %137 to i64
  %139 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %134, i64 noundef %138)
  %140 = getelementptr inbounds { ptr, i64 }, ptr %11, i32 0, i32 0
  %141 = extractvalue { ptr, i64 } %139, 0
  store ptr %141, ptr %140, align 8
  %142 = getelementptr inbounds { ptr, i64 }, ptr %11, i32 0, i32 1
  %143 = extractvalue { ptr, i64 } %139, 1
  store i64 %143, ptr %142, align 8
  %144 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %11) #3
  br label %145

145:                                              ; preds = %129, %124, %119, %114, %109
  %146 = phi i1 [ false, %124 ], [ false, %119 ], [ false, %114 ], [ false, %109 ], [ %144, %129 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #3
  br i1 %146, label %147, label %148

147:                                              ; preds = %145
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %152

148:                                              ; preds = %145
  br label %149

149:                                              ; preds = %148
  %150 = load i32, ptr %6, align 4, !tbaa !5
  %151 = add nsw i32 %150, 1
  store i32 %151, ptr %6, align 4, !tbaa !5
  br label %12, !llvm.loop !9

152:                                              ; preds = %147, %108, %69, %42, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %153 = load i32, ptr %7, align 4
  switch i32 %153, label %157 [
    i32 2, label %154
    i32 1, label %155
  ]

154:                                              ; preds = %152
  store i1 true, ptr %3, align 1
  br label %155

155:                                              ; preds = %154, %152
  %156 = load i1, ptr %3, align 1
  ret i1 %156

157:                                              ; preds = %152
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<bool>, std::allocator<std::vector<bool>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.std::_Bit_reference" = type { ptr, i64 }

@G = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z9can_placeii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #2 {
  %3 = alloca %"struct.std::_Bit_reference", align 8
  %4 = alloca %"struct.std::_Bit_reference", align 8
  %5 = alloca %"struct.std::_Bit_reference", align 8
  %6 = alloca %"struct.std::_Bit_reference", align 8
  %7 = sext i32 %0 to i64
  %8 = getelementptr inbounds i8, ptr %3, i64 8
  %9 = sext i32 %1 to i64
  %10 = getelementptr inbounds i8, ptr %4, i64 8
  %11 = getelementptr inbounds i8, ptr %5, i64 8
  %12 = getelementptr inbounds i8, ptr %6, i64 8
  br label %13

13:                                               ; preds = %2, %53
  %14 = phi i1 [ false, %2 ], [ %55, %53 ]
  %.04759 = phi i32 [ -7, %2 ], [ %54, %53 ]
  %15 = add nsw i32 %.04759, %1
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) #3
  %or.cond = icmp ult i32 %15, 8
  br i1 %or.cond, label %16, label %.critedge

16:                                               ; preds = %13
  %17 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %7) #3
  %18 = zext nneg i32 %15 to i64
  %19 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %17, i64 noundef %18)
  %20 = extractvalue { ptr, i64 } %19, 0
  store ptr %20, ptr %3, align 8
  %21 = extractvalue { ptr, i64 } %19, 1
  store i64 %21, ptr %8, align 8
  %22 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %3) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  br i1 %22, label %56, label %23

.critedge:                                        ; preds = %13
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #3
  br label %23

23:                                               ; preds = %.critedge, %16
  %24 = add nsw i32 %.04759, %0
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #3
  %or.cond53 = icmp ult i32 %24, 8
  br i1 %or.cond53, label %25, label %.critedge2

25:                                               ; preds = %23
  %26 = zext nneg i32 %24 to i64
  %27 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %26) #3
  %28 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %27, i64 noundef %9)
  %29 = extractvalue { ptr, i64 } %28, 0
  store ptr %29, ptr %4, align 8
  %30 = extractvalue { ptr, i64 } %28, 1
  store i64 %30, ptr %10, align 8
  %31 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %4) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #3
  br i1 %31, label %56, label %32

.critedge2:                                       ; preds = %23
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #3
  br label %32

32:                                               ; preds = %.critedge2, %25
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #3
  %33 = or i32 %15, %24
  %or.cond55 = icmp ult i32 %33, 8
  br i1 %or.cond55, label %34, label %42

34:                                               ; preds = %32
  %35 = zext nneg i32 %24 to i64
  %36 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %35) #3
  %37 = zext nneg i32 %15 to i64
  %38 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %36, i64 noundef %37)
  %39 = extractvalue { ptr, i64 } %38, 0
  store ptr %39, ptr %5, align 8
  %40 = extractvalue { ptr, i64 } %38, 1
  store i64 %40, ptr %11, align 8
  %41 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %5) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #3
  br i1 %41, label %56, label %.thread

.thread:                                          ; preds = %34
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #3
  br label %43

42:                                               ; preds = %32
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #3
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #3
  br i1 %or.cond, label %43, label %.critedge6

43:                                               ; preds = %.thread, %42
  %44 = sub nsw i32 %0, %.04759
  %or.cond57 = icmp ult i32 %44, 8
  br i1 %or.cond57, label %45, label %.critedge6

45:                                               ; preds = %43
  %46 = zext nneg i32 %44 to i64
  %47 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNSt6vectorIS_IbSaIbEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @G, i64 noundef %46) #3
  %48 = zext nneg i32 %15 to i64
  %49 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %47, i64 noundef %48)
  %50 = extractvalue { ptr, i64 } %49, 0
  store ptr %50, ptr %6, align 8
  %51 = extractvalue { ptr, i64 } %49, 1
  store i64 %51, ptr %12, align 8
  %52 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %6) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #3
  br i1 %52, label %56, label %53

.critedge6:                                       ; preds = %42, %43
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #3
  br label %53

53:                                               ; preds = %45, %.critedge6
  %54 = add nsw i32 %.04759, 1
  %55 = icmp sgt i32 %.04759, 6
  %exitcond = icmp eq i32 %54, 8
  br i1 %exitcond, label %56, label %13, !llvm.loop !5

56:                                               ; preds = %45, %34, %25, %16, %53
  %.lcssa = phi i1 [ %14, %45 ], [ %14, %34 ], [ %14, %25 ], [ %14, %16 ], [ %55, %53 ]
  ret i1 %.lcssa
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,SROAPass,SimplifyCFGPass