; LLVM IR from Stephane-D/SGDK :: src (vdp_bg)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@windowWidth = external global i16, align 2
@planeWidth = external global i16, align 2
@planeHeight = external global i16, align 2
@maps_addr = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @VDP_clearTextBG(i32 noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i16 %1, ptr %6, align 2, !tbaa !9
  store i16 %2, ptr %7, align 2, !tbaa !9
  store i16 %3, ptr %8, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #3
  %13 = load i32, ptr %5, align 4, !tbaa !5
  %14 = icmp eq i32 %13, 2
  br i1 %14, label %15, label %18

15:                                               ; preds = %4
  %16 = load i16, ptr @windowWidth, align 2, !tbaa !9
  %17 = zext i16 %16 to i32
  br label %21

18:                                               ; preds = %4
  %19 = load i16, ptr @planeWidth, align 2, !tbaa !9
  %20 = zext i16 %19 to i32
  br label %21

21:                                               ; preds = %18, %15
  %22 = phi i32 [ %17, %15 ], [ %20, %18 ]
  %23 = trunc i32 %22 to i16
  store i16 %23, ptr %9, align 2, !tbaa !9
  %24 = load i32, ptr %5, align 4, !tbaa !5
  %25 = icmp eq i32 %24, 2
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  br label %30

27:                                               ; preds = %21
  %28 = load i16, ptr @planeHeight, align 2, !tbaa !9
  %29 = zext i16 %28 to i32
  br label %30

30:                                               ; preds = %27, %26
  %31 = phi i32 [ 32, %26 ], [ %29, %27 ]
  %32 = trunc i32 %31 to i16
  store i16 %32, ptr %10, align 2, !tbaa !9
  %33 = load i16, ptr %6, align 2, !tbaa !9
  %34 = zext i16 %33 to i32
  %35 = load i16, ptr %9, align 2, !tbaa !9
  %36 = zext i16 %35 to i32
  %37 = icmp sge i32 %34, %36
  br i1 %37, label %44, label %38

38:                                               ; preds = %30
  %39 = load i16, ptr %7, align 2, !tbaa !9
  %40 = zext i16 %39 to i32
  %41 = load i16, ptr %10, align 2, !tbaa !9
  %42 = zext i16 %41 to i32
  %43 = icmp sge i32 %40, %42
  br i1 %43, label %44, label %45

44:                                               ; preds = %38, %30
  store i32 1, ptr %12, align 4
  br label %72

45:                                               ; preds = %38
  %46 = load i16, ptr %8, align 2, !tbaa !9
  store i16 %46, ptr %11, align 2, !tbaa !9
  %47 = load i16, ptr %11, align 2, !tbaa !9
  %48 = zext i16 %47 to i32
  %49 = load i16, ptr %9, align 2, !tbaa !9
  %50 = zext i16 %49 to i32
  %51 = load i16, ptr %6, align 2, !tbaa !9
  %52 = zext i16 %51 to i32
  %53 = sub nsw i32 %50, %52
  %54 = icmp sgt i32 %48, %53
  br i1 %54, label %55, label %62

55:                                               ; preds = %45
  %56 = load i16, ptr %9, align 2, !tbaa !9
  %57 = zext i16 %56 to i32
  %58 = load i16, ptr %6, align 2, !tbaa !9
  %59 = zext i16 %58 to i32
  %60 = sub nsw i32 %57, %59
  %61 = trunc i32 %60 to i16
  store i16 %61, ptr %11, align 2, !tbaa !9
  br label %62

62:                                               ; preds = %55, %45
  %63 = load i32, ptr %5, align 4, !tbaa !5
  %64 = load i16, ptr @maps_addr, align 2, !tbaa !9
  %65 = zext i16 %64 to i32
  %66 = sdiv i32 %65, 32
  %67 = sub nsw i32 %66, 96
  %68 = trunc i32 %67 to i16
  %69 = load i16, ptr %6, align 2, !tbaa !9
  %70 = load i16, ptr %7, align 2, !tbaa !9
  %71 = load i16, ptr %11, align 2, !tbaa !9
  call void @VDP_fillTileMapRect(i32 noundef %63, i16 noundef zeroext %68, i16 noundef zeroext %69, i16 noundef zeroext %70, i16 noundef zeroext %71, i16 noundef zeroext 1)
  store i32 0, ptr %12, align 4
  br label %72

72:                                               ; preds = %62, %44
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #3
  %73 = load i32, ptr %12, align 4
  switch i32 %73, label %75 [
    i32 0, label %74
    i32 1, label %74
  ]

74:                                               ; preds = %72, %72
  ret void

75:                                               ; preds = %72
  unreachable
}

declare void @VDP_fillTileMapRect(i32 noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@windowWidth = external local_unnamed_addr global i16, align 2
@planeWidth = external local_unnamed_addr global i16, align 2
@planeHeight = external local_unnamed_addr global i16, align 2
@maps_addr = external local_unnamed_addr global i16, align 2

; Function Attrs: nounwind uwtable
define dso_local void @VDP_clearTextBG(i32 noundef %0, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %3) local_unnamed_addr #0 {
  %5 = icmp eq i32 %0, 2
  %6 = load i16, ptr @windowWidth, align 2
  %7 = load i16, ptr @planeWidth, align 2
  %.v = select i1 %5, i16 %6, i16 %7
  %8 = zext i16 %1 to i32
  %9 = zext i16 %.v to i32
  %.not = icmp ugt i16 %.v, %1
  br i1 %.not, label %10, label %23

10:                                               ; preds = %4
  %11 = load i16, ptr @planeHeight, align 2
  %12 = zext i16 %11 to i32
  %13 = zext i16 %2 to i32
  %14 = select i1 %5, i32 32, i32 %12
  %.not19 = icmp ugt i32 %14, %13
  br i1 %.not19, label %15, label %23

15:                                               ; preds = %10
  %16 = zext i16 %3 to i32
  %17 = sub nsw i32 %9, %8
  %18 = icmp slt i32 %17, %16
  %19 = trunc i32 %17 to i16
  %spec.select = select i1 %18, i16 %19, i16 %3
  %20 = load i16, ptr @maps_addr, align 2, !tbaa !5
  %21 = lshr i16 %20, 5
  %22 = add nsw i16 %21, -96
  tail call void @VDP_fillTileMapRect(i32 noundef %0, i16 noundef zeroext %22, i16 noundef zeroext %1, i16 noundef zeroext %2, i16 noundef zeroext %spec.select, i16 noundef zeroext 1) #2
  br label %23

23:                                               ; preds = %4, %10, %15
  ret void
}

declare void @VDP_fillTileMapRect(i32 noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass