; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TileMap = type { i16, i16, i16, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @MEM_free(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local void @VDP_setTileMapDataRow(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) #2

declare ptr @unpackTileMap(ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @VDP_setTileMapRow(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5) #2 {
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i16, align 2
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  %13 = alloca i32, align 4
  %14 = alloca i64, align 8
  %15 = alloca ptr, align 8
  %16 = alloca i32, align 4
  store i32 %0, ptr %8, align 4, !tbaa !5
  store ptr %1, ptr %9, align 8, !tbaa !9
  store i16 %2, ptr %10, align 2, !tbaa !11
  store i16 %3, ptr %11, align 2, !tbaa !11
  store i16 %4, ptr %12, align 2, !tbaa !11
  store i32 %5, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #3
  %17 = load i16, ptr %10, align 2, !tbaa !11
  %18 = load ptr, ptr %9, align 8, !tbaa !9
  %19 = getelementptr inbounds %struct.TileMap, ptr %18, i32 0, i32 1
  %20 = load i16, ptr %19, align 2, !tbaa !13
  %21 = call i64 @mulu(i16 noundef zeroext %17, i16 noundef zeroext %20)
  %22 = load i16, ptr %11, align 2, !tbaa !11
  %23 = zext i16 %22 to i64
  %24 = add i64 %21, %23
  store i64 %24, ptr %14, align 8, !tbaa !15
  %25 = load ptr, ptr %9, align 8, !tbaa !9
  %26 = getelementptr inbounds %struct.TileMap, ptr %25, i32 0, i32 0
  %27 = load i16, ptr %26, align 8, !tbaa !17
  %28 = zext i16 %27 to i32
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %51

30:                                               ; preds = %6
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  %31 = load ptr, ptr %9, align 8, !tbaa !9
  %32 = call ptr @unpackTileMap(ptr noundef %31, ptr noundef null)
  store ptr %32, ptr %15, align 8, !tbaa !9
  %33 = load ptr, ptr %15, align 8, !tbaa !9
  %34 = icmp eq ptr %33, null
  br i1 %34, label %35, label %36

35:                                               ; preds = %30
  store i8 0, ptr %7, align 1
  store i32 1, ptr %16, align 4
  br label %48

36:                                               ; preds = %30
  %37 = load i32, ptr %8, align 4, !tbaa !5
  %38 = load ptr, ptr %15, align 8, !tbaa !9
  %39 = getelementptr inbounds %struct.TileMap, ptr %38, i32 0, i32 3
  %40 = load ptr, ptr %39, align 8, !tbaa !18
  %41 = load i64, ptr %14, align 8, !tbaa !15
  %42 = getelementptr inbounds i16, ptr %40, i64 %41
  %43 = load i16, ptr %10, align 2, !tbaa !11
  %44 = load i16, ptr %11, align 2, !tbaa !11
  %45 = load i16, ptr %12, align 2, !tbaa !11
  %46 = load i32, ptr %13, align 4, !tbaa !5
  call void @VDP_setTileMapDataRow(i32 noundef %37, ptr noundef %42, i16 noundef zeroext %43, i16 noundef zeroext %44, i16 noundef zeroext %45, i32 noundef %46)
  %47 = load ptr, ptr %15, align 8, !tbaa !9
  call void @MEM_free(ptr noundef %47)
  store i32 0, ptr %16, align 4
  br label %48

48:                                               ; preds = %36, %35
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  %49 = load i32, ptr %16, align 4
  switch i32 %49, label %63 [
    i32 0, label %50
  ]

50:                                               ; preds = %48
  br label %62

51:                                               ; preds = %6
  %52 = load i32, ptr %8, align 4, !tbaa !5
  %53 = load ptr, ptr %9, align 8, !tbaa !9
  %54 = getelementptr inbounds %struct.TileMap, ptr %53, i32 0, i32 3
  %55 = load ptr, ptr %54, align 8, !tbaa !18
  %56 = load i64, ptr %14, align 8, !tbaa !15
  %57 = getelementptr inbounds i16, ptr %55, i64 %56
  %58 = load i16, ptr %10, align 2, !tbaa !11
  %59 = load i16, ptr %11, align 2, !tbaa !11
  %60 = load i16, ptr %12, align 2, !tbaa !11
  %61 = load i32, ptr %13, align 4, !tbaa !5
  call void @VDP_setTileMapDataRow(i32 noundef %52, ptr noundef %57, i16 noundef zeroext %58, i16 noundef zeroext %59, i16 noundef zeroext %60, i32 noundef %61)
  br label %62

62:                                               ; preds = %51, %50
  store i8 1, ptr %7, align 1
  store i32 1, ptr %16, align 4
  br label %63

63:                                               ; preds = %62, %48
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #3
  %64 = load i8, ptr %7, align 1
  ret i8 %64
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !12, i64 2}
!14 = !{!"", !12, i64 0, !12, i64 2, !12, i64 4, !10, i64 8}
!15 = !{!16, !16, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!14, !12, i64 0}
!18 = !{!14, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @MEM_free(ptr noundef) local_unnamed_addr #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @VDP_setTileMapDataRow(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

declare ptr @unpackTileMap(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @VDP_setTileMapRow(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5) local_unnamed_addr #1 {
  %7 = getelementptr inbounds i8, ptr %1, i64 2
  %8 = load i16, ptr %7, align 2, !tbaa !5
  %9 = tail call i64 @mulu(i16 noundef zeroext %2, i16 noundef zeroext %8) #2
  %10 = zext i16 %3 to i64
  %11 = add i64 %9, %10
  %12 = load i16, ptr %1, align 8, !tbaa !11
  %.not = icmp eq i16 %12, 0
  br i1 %.not, label %19, label %13

13:                                               ; preds = %6
  %14 = tail call ptr @unpackTileMap(ptr noundef nonnull %1, ptr noundef null) #2
  %.not24 = icmp eq ptr %14, null
  br i1 %.not24, label %.critedge, label %15

15:                                               ; preds = %13
  %16 = getelementptr inbounds i8, ptr %14, i64 8
  %17 = load ptr, ptr %16, align 8, !tbaa !12
  %18 = getelementptr inbounds i16, ptr %17, i64 %11
  tail call void @VDP_setTileMapDataRow(i32 noundef %0, ptr noundef %18, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5)
  tail call void @MEM_free(ptr noundef nonnull %14) #2
  br label %.critedge

19:                                               ; preds = %6
  %20 = getelementptr inbounds i8, ptr %1, i64 8
  %21 = load ptr, ptr %20, align 8, !tbaa !12
  %22 = getelementptr inbounds i16, ptr %21, i64 %11
  tail call void @VDP_setTileMapDataRow(i32 noundef %0, ptr noundef %22, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i32 noundef %5)
  br label %.critedge

.critedge:                                        ; preds = %19, %15, %13
  %.1 = phi i8 [ 0, %13 ], [ 1, %15 ], [ 1, %19 ]
  ret i8 %.1
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 2}
!6 = !{!"", !7, i64 0, !7, i64 2, !7, i64 4, !10, i64 8}
!7 = !{!"short", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !7, i64 0}
!12 = !{!6, !10, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass