; LLVM IR from Stephane-D/SGDK :: src (maths)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_abs(i16 noundef signext) #1

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_div(i16 noundef signext, i16 noundef signext) #1

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_atan(i16 noundef signext) #1

; Function Attrs: nounwind uwtable
define dso_local signext i16 @F16_atan2(i16 noundef signext %0, i16 noundef signext %1) #2 {
  %3 = alloca i16, align 2
  %4 = alloca i16, align 2
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  store i16 %0, ptr %4, align 2, !tbaa !5
  store i16 %1, ptr %5, align 2, !tbaa !5
  %7 = load i16, ptr %5, align 2, !tbaa !5
  %8 = sext i16 %7 to i32
  %9 = icmp eq i32 %8, 0
  br i1 %9, label %10, label %15

10:                                               ; preds = %2
  %11 = load i16, ptr %4, align 2, !tbaa !5
  %12 = sext i16 %11 to i32
  %13 = icmp eq i32 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %10
  store i16 0, ptr %3, align 2
  br label %87

15:                                               ; preds = %10, %2
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #3
  %16 = load i16, ptr %5, align 2, !tbaa !5
  %17 = call signext i16 @F16_abs(i16 noundef signext %16)
  %18 = sext i16 %17 to i32
  %19 = load i16, ptr %4, align 2, !tbaa !5
  %20 = call signext i16 @F16_abs(i16 noundef signext %19)
  %21 = sext i16 %20 to i32
  %22 = icmp sge i32 %18, %21
  br i1 %22, label %23, label %47

23:                                               ; preds = %15
  %24 = load i16, ptr %4, align 2, !tbaa !5
  %25 = load i16, ptr %5, align 2, !tbaa !5
  %26 = call signext i16 @F16_div(i16 noundef signext %24, i16 noundef signext %25)
  %27 = call signext i16 @F16_atan(i16 noundef signext %26)
  store i16 %27, ptr %6, align 2, !tbaa !5
  %28 = load i16, ptr %5, align 2, !tbaa !5
  %29 = sext i16 %28 to i32
  %30 = icmp slt i32 %29, 0
  br i1 %30, label %31, label %46

31:                                               ; preds = %23
  %32 = load i16, ptr %4, align 2, !tbaa !5
  %33 = sext i16 %32 to i32
  %34 = icmp sge i32 %33, 0
  br i1 %34, label %35, label %40

35:                                               ; preds = %31
  %36 = load i16, ptr %6, align 2, !tbaa !5
  %37 = sext i16 %36 to i32
  %38 = add nsw i32 %37, 11520
  %39 = trunc i32 %38 to i16
  store i16 %39, ptr %6, align 2, !tbaa !5
  br label %45

40:                                               ; preds = %31
  %41 = load i16, ptr %6, align 2, !tbaa !5
  %42 = sext i16 %41 to i32
  %43 = sub nsw i32 %42, 11520
  %44 = trunc i32 %43 to i16
  store i16 %44, ptr %6, align 2, !tbaa !5
  br label %45

45:                                               ; preds = %40, %35
  br label %46

46:                                               ; preds = %45, %23
  br label %66

47:                                               ; preds = %15
  %48 = load i16, ptr %5, align 2, !tbaa !5
  %49 = load i16, ptr %4, align 2, !tbaa !5
  %50 = call signext i16 @F16_div(i16 noundef signext %48, i16 noundef signext %49)
  %51 = call signext i16 @F16_atan(i16 noundef signext %50)
  store i16 %51, ptr %6, align 2, !tbaa !5
  %52 = load i16, ptr %4, align 2, !tbaa !5
  %53 = sext i16 %52 to i32
  %54 = icmp sgt i32 %53, 0
  br i1 %54, label %55, label %60

55:                                               ; preds = %47
  %56 = load i16, ptr %6, align 2, !tbaa !5
  %57 = sext i16 %56 to i32
  %58 = sub nsw i32 5760, %57
  %59 = trunc i32 %58 to i16
  store i16 %59, ptr %6, align 2, !tbaa !5
  br label %65

60:                                               ; preds = %47
  %61 = load i16, ptr %6, align 2, !tbaa !5
  %62 = sext i16 %61 to i32
  %63 = sub nsw i32 -5760, %62
  %64 = trunc i32 %63 to i16
  store i16 %64, ptr %6, align 2, !tbaa !5
  br label %65

65:                                               ; preds = %60, %55
  br label %66

66:                                               ; preds = %65, %46
  %67 = load i16, ptr %6, align 2, !tbaa !5
  %68 = sext i16 %67 to i32
  %69 = icmp slt i32 %68, 0
  br i1 %69, label %70, label %75

70:                                               ; preds = %66
  %71 = load i16, ptr %6, align 2, !tbaa !5
  %72 = sext i16 %71 to i32
  %73 = add nsw i32 %72, 23040
  %74 = trunc i32 %73 to i16
  store i16 %74, ptr %6, align 2, !tbaa !5
  br label %85

75:                                               ; preds = %66
  %76 = load i16, ptr %6, align 2, !tbaa !5
  %77 = sext i16 %76 to i32
  %78 = icmp sge i32 %77, 23040
  br i1 %78, label %79, label %84

79:                                               ; preds = %75
  %80 = load i16, ptr %6, align 2, !tbaa !5
  %81 = sext i16 %80 to i32
  %82 = sub nsw i32 %81, 23040
  %83 = trunc i32 %82 to i16
  store i16 %83, ptr %6, align 2, !tbaa !5
  br label %84

84:                                               ; preds = %79, %75
  br label %85

85:                                               ; preds = %84, %70
  %86 = load i16, ptr %6, align 2, !tbaa !5
  store i16 %86, ptr %3, align 2
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #3
  br label %87

87:                                               ; preds = %85, %14
  %88 = load i16, ptr %3, align 2
  ret i16 %88
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_abs(i16 noundef signext) local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_div(i16 noundef signext, i16 noundef signext) local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare dso_local signext i16 @F16_atan(i16 noundef signext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local signext i16 @F16_atan2(i16 noundef signext %0, i16 noundef signext %1) local_unnamed_addr #1 {
  %3 = or i16 %1, %0
  %or.cond = icmp eq i16 %3, 0
  br i1 %or.cond, label %31, label %4

4:                                                ; preds = %2
  %5 = tail call signext i16 @F16_abs(i16 noundef signext %1)
  %6 = tail call signext i16 @F16_abs(i16 noundef signext %0)
  %.not = icmp slt i16 %5, %6
  br i1 %.not, label %17, label %7

7:                                                ; preds = %4
  %8 = tail call signext i16 @F16_div(i16 noundef signext %0, i16 noundef signext %1)
  %9 = tail call signext i16 @F16_atan(i16 noundef signext %8)
  %10 = icmp slt i16 %1, 0
  br i1 %10, label %11, label %25

11:                                               ; preds = %7
  %12 = icmp sgt i16 %0, -1
  br i1 %12, label %13, label %15

13:                                               ; preds = %11
  %14 = add i16 %9, 11520
  br label %25

15:                                               ; preds = %11
  %16 = add i16 %9, -11520
  br label %25

17:                                               ; preds = %4
  %18 = tail call signext i16 @F16_div(i16 noundef signext %1, i16 noundef signext %0)
  %19 = tail call signext i16 @F16_atan(i16 noundef signext %18)
  %20 = icmp sgt i16 %0, 0
  br i1 %20, label %21, label %23

21:                                               ; preds = %17
  %22 = sub i16 5760, %19
  br label %25

23:                                               ; preds = %17
  %24 = sub i16 -5760, %19
  br label %25

25:                                               ; preds = %21, %23, %7, %15, %13
  %.0 = phi i16 [ %14, %13 ], [ %16, %15 ], [ %9, %7 ], [ %22, %21 ], [ %24, %23 ]
  %26 = icmp slt i16 %.0, 0
  br i1 %26, label %27, label %28

27:                                               ; preds = %25
  %narrow = add nsw i16 %.0, 23040
  br label %31

28:                                               ; preds = %25
  %29 = icmp ugt i16 %.0, 23039
  %30 = add nsw i16 %.0, -23040
  %spec.select = select i1 %29, i16 %30, i16 %.0
  br label %31

31:                                               ; preds = %28, %27, %2
  %.023 = phi i16 [ 0, %2 ], [ %narrow, %27 ], [ %spec.select, %28 ]
  ret i16 %.023
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass