; LLVM IR from Stephane-D/SGDK :: src (vdp_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeHeight = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare hidden void @setTileMapDataColumnEx(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumnEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i32 noundef %7) #2 {
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i16, align 2
  %12 = alloca i16, align 2
  %13 = alloca i16, align 2
  %14 = alloca i16, align 2
  %15 = alloca i16, align 2
  %16 = alloca i32, align 4
  %17 = alloca i16, align 2
  %18 = alloca i16, align 2
  %19 = alloca i16, align 2
  store i32 %0, ptr %9, align 4, !tbaa !5
  store ptr %1, ptr %10, align 8, !tbaa !9
  store i16 %2, ptr %11, align 2, !tbaa !11
  store i16 %3, ptr %12, align 2, !tbaa !11
  store i16 %4, ptr %13, align 2, !tbaa !11
  store i16 %5, ptr %14, align 2, !tbaa !11
  store i16 %6, ptr %15, align 2, !tbaa !11
  store i32 %7, ptr %16, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %17) #3
  %20 = load i32, ptr %9, align 4, !tbaa !5
  %21 = icmp eq i32 %20, 2
  br i1 %21, label %22, label %23

22:                                               ; preds = %8
  br label %26

23:                                               ; preds = %8
  %24 = load i16, ptr @planeHeight, align 2, !tbaa !11
  %25 = zext i16 %24 to i32
  br label %26

26:                                               ; preds = %23, %22
  %27 = phi i32 [ 32, %22 ], [ %25, %23 ]
  %28 = trunc i32 %27 to i16
  store i16 %28, ptr %17, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %18) #3
  %29 = load i16, ptr %13, align 2, !tbaa !11
  %30 = zext i16 %29 to i32
  %31 = load i16, ptr %17, align 2, !tbaa !11
  %32 = zext i16 %31 to i32
  %33 = sub nsw i32 %32, 1
  %34 = and i32 %30, %33
  %35 = trunc i32 %34 to i16
  store i16 %35, ptr %18, align 2, !tbaa !11
  %36 = load i16, ptr %18, align 2, !tbaa !11
  %37 = zext i16 %36 to i32
  %38 = load i16, ptr %14, align 2, !tbaa !11
  %39 = zext i16 %38 to i32
  %40 = add nsw i32 %37, %39
  %41 = load i16, ptr %17, align 2, !tbaa !11
  %42 = zext i16 %41 to i32
  %43 = icmp sgt i32 %40, %42
  br i1 %43, label %44, label %75

44:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 2, ptr %19) #3
  %45 = load i16, ptr %17, align 2, !tbaa !11
  %46 = zext i16 %45 to i32
  %47 = load i16, ptr %18, align 2, !tbaa !11
  %48 = zext i16 %47 to i32
  %49 = sub nsw i32 %46, %48
  %50 = trunc i32 %49 to i16
  store i16 %50, ptr %19, align 2, !tbaa !11
  %51 = load i32, ptr %9, align 4, !tbaa !5
  %52 = load ptr, ptr %10, align 8, !tbaa !9
  %53 = load i16, ptr %11, align 2, !tbaa !11
  %54 = load i16, ptr %12, align 2, !tbaa !11
  %55 = load i16, ptr %18, align 2, !tbaa !11
  %56 = load i16, ptr %19, align 2, !tbaa !11
  %57 = load i16, ptr %15, align 2, !tbaa !11
  %58 = load i32, ptr %16, align 4, !tbaa !5
  call void @setTileMapDataColumnEx(i32 noundef %51, ptr noundef %52, i16 noundef zeroext %53, i16 noundef zeroext %54, i16 noundef zeroext %55, i16 noundef zeroext %56, i16 noundef zeroext %57, i32 noundef %58)
  %59 = load i32, ptr %9, align 4, !tbaa !5
  %60 = load ptr, ptr %10, align 8, !tbaa !9
  %61 = load i16, ptr %15, align 2, !tbaa !11
  %62 = load i16, ptr %19, align 2, !tbaa !11
  %63 = call i64 @mulu(i16 noundef zeroext %61, i16 noundef zeroext %62)
  %64 = getelementptr inbounds i16, ptr %60, i64 %63
  %65 = load i16, ptr %11, align 2, !tbaa !11
  %66 = load i16, ptr %12, align 2, !tbaa !11
  %67 = load i16, ptr %14, align 2, !tbaa !11
  %68 = zext i16 %67 to i32
  %69 = load i16, ptr %19, align 2, !tbaa !11
  %70 = zext i16 %69 to i32
  %71 = sub nsw i32 %68, %70
  %72 = trunc i32 %71 to i16
  %73 = load i16, ptr %15, align 2, !tbaa !11
  %74 = load i32, ptr %16, align 4, !tbaa !5
  call void @setTileMapDataColumnEx(i32 noundef %59, ptr noundef %64, i16 noundef zeroext %65, i16 noundef zeroext %66, i16 noundef zeroext 0, i16 noundef zeroext %72, i16 noundef zeroext %73, i32 noundef %74)
  call void @llvm.lifetime.end.p0(i64 2, ptr %19) #3
  br label %84

75:                                               ; preds = %26
  %76 = load i32, ptr %9, align 4, !tbaa !5
  %77 = load ptr, ptr %10, align 8, !tbaa !9
  %78 = load i16, ptr %11, align 2, !tbaa !11
  %79 = load i16, ptr %12, align 2, !tbaa !11
  %80 = load i16, ptr %18, align 2, !tbaa !11
  %81 = load i16, ptr %14, align 2, !tbaa !11
  %82 = load i16, ptr %15, align 2, !tbaa !11
  %83 = load i32, ptr %16, align 4, !tbaa !5
  call void @setTileMapDataColumnEx(i32 noundef %76, ptr noundef %77, i16 noundef zeroext %78, i16 noundef zeroext %79, i16 noundef zeroext %80, i16 noundef zeroext %81, i16 noundef zeroext %82, i32 noundef %83)
  br label %84

84:                                               ; preds = %75, %44
  call void @llvm.lifetime.end.p0(i64 2, ptr %18) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %17) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@planeHeight = external local_unnamed_addr global i16, align 2

declare i64 @mulu(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @setTileMapDataColumnEx(i32 noundef, ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @VDP_setTileMapDataColumnEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %4, i16 noundef zeroext %5, i16 noundef zeroext %6, i32 noundef %7) local_unnamed_addr #1 {
  %9 = icmp eq i32 %0, 2
  %10 = load i16, ptr @planeHeight, align 2
  %11 = zext i16 %10 to i32
  %12 = select i1 %9, i32 32, i32 %11
  %13 = trunc nuw i32 %12 to i16
  %14 = add i16 %13, -1
  %15 = and i16 %14, %4
  %16 = zext i16 %15 to i32
  %17 = zext i16 %5 to i32
  %18 = add nuw nsw i32 %16, %17
  %19 = icmp ugt i32 %18, %12
  br i1 %19, label %20, label %25

20:                                               ; preds = %8
  %21 = sub i16 %13, %15
  tail call void @setTileMapDataColumnEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %15, i16 noundef zeroext %21, i16 noundef zeroext %6, i32 noundef %7)
  %22 = tail call i64 @mulu(i16 noundef zeroext %6, i16 noundef zeroext %21) #2
  %23 = getelementptr inbounds i16, ptr %1, i64 %22
  %24 = sub i16 %5, %21
  tail call void @setTileMapDataColumnEx(i32 noundef %0, ptr noundef %23, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext 0, i16 noundef zeroext %24, i16 noundef zeroext %6, i32 noundef %7)
  br label %26

25:                                               ; preds = %8
  tail call void @setTileMapDataColumnEx(i32 noundef %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef zeroext %15, i16 noundef zeroext %5, i16 noundef zeroext %6, i32 noundef %7)
  br label %26

26:                                               ; preds = %25, %20
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass