; LLVM IR from Stephane-D/SGDK :: sample/demo/bad-apple/src (tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@frontBuffer = external hidden global ptr, align 8
@baseTileInd = external hidden global i16, align 2
@ts_transfer.tileSrc = external hidden global ptr, align 8
@ts_transfer.tileInd = external hidden global i16, align 2
@ts_transfer.tileLeft = external hidden global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @ts_transfer(i16 noundef zeroext %0) #1 {
  %2 = alloca i8, align 1
  %3 = alloca i16, align 2
  %4 = alloca i16, align 2
  %5 = alloca i32, align 4
  store i16 %0, ptr %3, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 2, ptr %4) #3
  %6 = load i16, ptr %3, align 2, !tbaa !5
  %7 = icmp ne i16 %6, 0
  br i1 %7, label %8, label %15

8:                                                ; preds = %1
  %9 = load ptr, ptr @frontBuffer, align 8, !tbaa !9
  store ptr %9, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %10 = load i16, ptr @baseTileInd, align 2, !tbaa !5
  store i16 %10, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %11 = load i16, ptr %3, align 2, !tbaa !5
  %12 = zext i16 %11 to i32
  %13 = sub nsw i32 %12, 1
  %14 = trunc i32 %13 to i16
  store i16 %14, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  br label %15

15:                                               ; preds = %8, %1
  %16 = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  %17 = zext i16 %16 to i32
  %18 = icmp sgt i32 %17, 180
  br i1 %18, label %19, label %20

19:                                               ; preds = %15
  store i16 180, ptr %4, align 2, !tbaa !5
  br label %22

20:                                               ; preds = %15
  %21 = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  store i16 %21, ptr %4, align 2, !tbaa !5
  br label %22

22:                                               ; preds = %20, %19
  %23 = load i16, ptr %4, align 2, !tbaa !5
  %24 = icmp ne i16 %23, 0
  br i1 %24, label %25, label %47

25:                                               ; preds = %22
  %26 = load ptr, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %27 = load i16, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %28 = load i16, ptr %4, align 2, !tbaa !5
  call void @VDP_loadTileData(ptr noundef %26, i16 noundef zeroext %27, i16 noundef zeroext %28, i32 noundef 1)
  %29 = load i16, ptr %4, align 2, !tbaa !5
  %30 = zext i16 %29 to i32
  %31 = mul nsw i32 %30, 8
  %32 = load ptr, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %33 = sext i32 %31 to i64
  %34 = getelementptr inbounds i64, ptr %32, i64 %33
  store ptr %34, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %35 = load i16, ptr %4, align 2, !tbaa !5
  %36 = zext i16 %35 to i32
  %37 = load i16, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %38 = zext i16 %37 to i32
  %39 = add nsw i32 %38, %36
  %40 = trunc i32 %39 to i16
  store i16 %40, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %41 = load i16, ptr %4, align 2, !tbaa !5
  %42 = zext i16 %41 to i32
  %43 = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  %44 = zext i16 %43 to i32
  %45 = sub nsw i32 %44, %42
  %46 = trunc i32 %45 to i16
  store i16 %46, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  br label %47

47:                                               ; preds = %25, %22
  %48 = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  %49 = zext i16 %48 to i32
  %50 = icmp sgt i32 %49, 0
  br i1 %50, label %51, label %52

51:                                               ; preds = %47
  store i8 1, ptr %2, align 1
  store i32 1, ptr %5, align 4
  br label %59

52:                                               ; preds = %47
  %53 = load i16, ptr @baseTileInd, align 2, !tbaa !5
  %54 = zext i16 %53 to i32
  %55 = icmp eq i32 %54, 16
  br i1 %55, label %56, label %57

56:                                               ; preds = %52
  store i16 528, ptr @baseTileInd, align 2, !tbaa !5
  br label %58

57:                                               ; preds = %52
  store i16 16, ptr @baseTileInd, align 2, !tbaa !5
  br label %58

58:                                               ; preds = %57, %56
  store i8 0, ptr %2, align 1
  store i32 1, ptr %5, align 4
  br label %59

59:                                               ; preds = %58, %51
  call void @llvm.lifetime.end.p0(i64 2, ptr %4) #3
  %60 = load i8, ptr %2, align 1
  ret i8 %60
}

declare void @VDP_loadTileData(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@frontBuffer = external hidden local_unnamed_addr global ptr, align 8
@baseTileInd = external hidden local_unnamed_addr global i16, align 2
@ts_transfer.tileSrc = external hidden local_unnamed_addr global ptr, align 8
@ts_transfer.tileInd = external hidden local_unnamed_addr global i16, align 2
@ts_transfer.tileLeft = external hidden local_unnamed_addr global i16, align 2

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @ts_transfer(i16 noundef zeroext %0) local_unnamed_addr #0 {
  %.not = icmp eq i16 %0, 0
  br i1 %.not, label %._crit_edge, label %2

._crit_edge:                                      ; preds = %1
  %.pre = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  br label %6

2:                                                ; preds = %1
  %3 = load ptr, ptr @frontBuffer, align 8, !tbaa !9
  store ptr %3, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %4 = load i16, ptr @baseTileInd, align 2, !tbaa !5
  store i16 %4, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %5 = add i16 %0, -1
  store i16 %5, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  br label %6

6:                                                ; preds = %._crit_edge, %2
  %7 = phi i16 [ %.pre, %._crit_edge ], [ %5, %2 ]
  %.not10 = icmp eq i16 %7, 0
  br i1 %.not10, label %.critedge, label %8

8:                                                ; preds = %6
  %. = tail call i16 @llvm.umin.i16(i16 %7, i16 180)
  %9 = load ptr, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %10 = load i16, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  tail call void @VDP_loadTileData(ptr noundef %9, i16 noundef zeroext %10, i16 noundef zeroext %., i32 noundef 1) #3
  %11 = shl nuw nsw i16 %., 3
  %12 = load ptr, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %13 = zext nneg i16 %11 to i64
  %14 = getelementptr inbounds i64, ptr %12, i64 %13
  store ptr %14, ptr @ts_transfer.tileSrc, align 8, !tbaa !9
  %15 = load i16, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %16 = add i16 %15, %.
  store i16 %16, ptr @ts_transfer.tileInd, align 2, !tbaa !5
  %17 = load i16, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  %18 = sub i16 %17, %.
  store i16 %18, ptr @ts_transfer.tileLeft, align 2, !tbaa !5
  %19 = icmp eq i16 %17, %.
  br i1 %19, label %.critedge, label %22

.critedge:                                        ; preds = %6, %8
  %20 = load i16, ptr @baseTileInd, align 2, !tbaa !5
  %21 = icmp eq i16 %20, 16
  %.12 = select i1 %21, i16 528, i16 16
  store i16 %.12, ptr @baseTileInd, align 2, !tbaa !5
  br label %22

22:                                               ; preds = %8, %.critedge
  %.08 = phi i8 [ 0, %.critedge ], [ 1, %8 ]
  ret i8 %.08
}

declare void @VDP_loadTileData(ptr noundef, i16 noundef zeroext, i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.umin.i16(i16, i16) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass