; LLVM IR from Stephane-D/SGDK :: src (dma)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doCPUCopy(i8 noundef zeroext %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef signext %4) #1 {
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i64, align 8
  store i8 %0, ptr %6, align 1, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !8
  store i16 %2, ptr %8, align 2, !tbaa !10
  store i16 %3, ptr %9, align 2, !tbaa !10
  store i16 %4, ptr %10, align 2, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #3
  %12 = load i8, ptr %6, align 1, !tbaa !5
  %13 = zext i8 %12 to i32
  switch i32 %13, label %14 [
    i32 0, label %15
    i32 1, label %26
    i32 2, label %33
  ]

14:                                               ; preds = %5
  br label %15

15:                                               ; preds = %14, %5
  %16 = load i16, ptr %8, align 2, !tbaa !10
  %17 = zext i16 %16 to i64
  %18 = and i64 %17, 16383
  %19 = add i64 16384, %18
  %20 = shl i64 %19, 16
  %21 = load i16, ptr %8, align 2, !tbaa !10
  %22 = zext i16 %21 to i64
  %23 = lshr i64 %22, 14
  %24 = or i64 %23, 0
  %25 = add i64 %20, %24
  store i64 %25, ptr %11, align 8, !tbaa !12
  br label %40

26:                                               ; preds = %5
  %27 = load i16, ptr %8, align 2, !tbaa !10
  %28 = zext i16 %27 to i64
  %29 = and i64 %28, 127
  %30 = add i64 49152, %29
  %31 = shl i64 %30, 16
  %32 = add i64 %31, 0
  store i64 %32, ptr %11, align 8, !tbaa !12
  br label %40

33:                                               ; preds = %5
  %34 = load i16, ptr %8, align 2, !tbaa !10
  %35 = zext i16 %34 to i64
  %36 = and i64 %35, 127
  %37 = add i64 16384, %36
  %38 = shl i64 %37, 16
  %39 = add i64 %38, 16
  store i64 %39, ptr %11, align 8, !tbaa !12
  br label %40

40:                                               ; preds = %33, %26, %15
  %41 = load i64, ptr %11, align 8, !tbaa !12
  %42 = load ptr, ptr %7, align 8, !tbaa !8
  %43 = load i16, ptr %9, align 2, !tbaa !10
  %44 = load i16, ptr %10, align 2, !tbaa !10
  call void @DMA_doCPUCopyDirect(i64 noundef %41, ptr noundef %42, i16 noundef zeroext %43, i16 noundef signext %44)
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #3
  ret void
}

; Function Attrs: noinline nounwind uwtable
declare dso_local void @DMA_doCPUCopyDirect(i64 noundef, ptr noundef, i16 noundef zeroext, i16 noundef signext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !6, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"long", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @DMA_doCPUCopy(i8 noundef zeroext %0, ptr noundef %1, i16 noundef zeroext %2, i16 noundef zeroext %3, i16 noundef signext %4) local_unnamed_addr #0 {
  switch i8 %0, label %6 [
    i8 2, label %18
    i8 1, label %13
  ]

6:                                                ; preds = %5
  %7 = zext i16 %2 to i64
  %8 = shl nuw nsw i64 %7, 16
  %9 = and i64 %8, 1073676288
  %10 = lshr i64 %7, 14
  %11 = or disjoint i64 %10, %9
  %12 = or disjoint i64 %11, 1073741824
  br label %24

13:                                               ; preds = %5
  %14 = and i16 %2, 127
  %15 = or disjoint i16 %14, -16384
  %16 = zext i16 %15 to i64
  %17 = shl nuw nsw i64 %16, 16
  br label %24

18:                                               ; preds = %5
  %19 = and i16 %2, 127
  %20 = or disjoint i16 %19, 16384
  %21 = zext nneg i16 %20 to i64
  %22 = shl nuw nsw i64 %21, 16
  %23 = or disjoint i64 %22, 16
  br label %24

24:                                               ; preds = %18, %13, %6
  %.0 = phi i64 [ %12, %6 ], [ %17, %13 ], [ %23, %18 ]
  tail call void @DMA_doCPUCopyDirect(i64 noundef %.0, ptr noundef %1, i16 noundef zeroext %3, i16 noundef signext %4)
  ret void
}

; Function Attrs: noinline nounwind uwtable
declare dso_local void @DMA_doCPUCopyDirect(i64 noundef, ptr noundef, i16 noundef zeroext, i16 noundef signext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass