; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/uartps_v3 (SetOperMode)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XUartPs = type { %struct.XUartPs_Config, i32, i32, i32, %struct.XUartPsBuffer, %struct.XUartPsBuffer, ptr, ptr, i32, i8 }
%struct.XUartPs_Config = type { i16, i32, i32, i32 }
%struct.XUartPsBuffer = type { ptr, i32, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XUartPs_SetOperMode(ptr noundef %0, i8 noundef zeroext %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = icmp ne ptr %7, null
  br i1 %8, label %9, label %10

9:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %11

10:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 443)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 1, ptr %6, align 4
  br label %57

11:                                               ; preds = %9
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.XUartPs, ptr %12, i32 0, i32 2
  %14 = load i32, ptr %13, align 4, !tbaa !12
  %15 = icmp eq i32 %14, 286331153
  br i1 %15, label %16, label %17

16:                                               ; preds = %11
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %18

17:                                               ; preds = %11
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 444)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 1, ptr %6, align 4
  br label %57

18:                                               ; preds = %16
  %19 = load i8, ptr %4, align 1, !tbaa !9
  %20 = zext i8 %19 to i32
  %21 = icmp sle i32 %20, 3
  br i1 %21, label %22, label %23

22:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %24

23:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 445)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 1, ptr %6, align 4
  br label %57

24:                                               ; preds = %22
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.XUartPs, ptr %25, i32 0, i32 0
  %27 = getelementptr inbounds %struct.XUartPs_Config, ptr %26, i32 0, i32 1
  %28 = load i32, ptr %27, align 4, !tbaa !17
  %29 = add i32 %28, 4
  %30 = zext i32 %29 to i64
  %31 = call i32 @Xil_In32(i64 noundef %30)
  store i32 %31, ptr %5, align 4, !tbaa !10
  %32 = load i32, ptr %5, align 4, !tbaa !10
  %33 = and i32 %32, -769
  store i32 %33, ptr %5, align 4, !tbaa !10
  %34 = load i8, ptr %4, align 1, !tbaa !9
  %35 = zext i8 %34 to i32
  switch i32 %35, label %48 [
    i32 0, label %36
    i32 1, label %39
    i32 2, label %42
    i32 3, label %45
  ]

36:                                               ; preds = %24
  %37 = load i32, ptr %5, align 4, !tbaa !10
  %38 = or i32 %37, 0
  store i32 %38, ptr %5, align 4, !tbaa !10
  br label %49

39:                                               ; preds = %24
  %40 = load i32, ptr %5, align 4, !tbaa !10
  %41 = or i32 %40, 256
  store i32 %41, ptr %5, align 4, !tbaa !10
  br label %49

42:                                               ; preds = %24
  %43 = load i32, ptr %5, align 4, !tbaa !10
  %44 = or i32 %43, 512
  store i32 %44, ptr %5, align 4, !tbaa !10
  br label %49

45:                                               ; preds = %24
  %46 = load i32, ptr %5, align 4, !tbaa !10
  %47 = or i32 %46, 768
  store i32 %47, ptr %5, align 4, !tbaa !10
  br label %49

48:                                               ; preds = %24
  br label %49

49:                                               ; preds = %48, %45, %42, %39, %36
  %50 = load ptr, ptr %3, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XUartPs, ptr %50, i32 0, i32 0
  %52 = getelementptr inbounds %struct.XUartPs_Config, ptr %51, i32 0, i32 1
  %53 = load i32, ptr %52, align 4, !tbaa !17
  %54 = add i32 %53, 4
  %55 = zext i32 %54 to i64
  %56 = load i32, ptr %5, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %55, i32 noundef %56)
  store i32 0, ptr %6, align 4
  br label %57

57:                                               ; preds = %49, %23, %17, %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  %58 = load i32, ptr %6, align 4
  switch i32 %58, label %60 [
    i32 0, label %59
    i32 1, label %59
  ]

59:                                               ; preds = %57, %57
  ret void

60:                                               ; preds = %57
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 20}
!13 = !{!"", !14, i64 0, !11, i64 16, !11, i64 20, !11, i64 24, !16, i64 32, !16, i64 48, !6, i64 64, !6, i64 72, !11, i64 80, !7, i64 84}
!14 = !{!"", !15, i64 0, !11, i64 4, !11, i64 8, !11, i64 12}
!15 = !{!"short", !7, i64 0}
!16 = !{!"", !6, i64 0, !11, i64 8, !11, i64 12}
!17 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XUartPs_SetOperMode(ptr noundef readonly %0, i8 noundef zeroext %1) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 20
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %10

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 443) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

8:                                                ; preds = %3
  %9 = icmp ult i8 %1, 4
  br i1 %9, label %11, label %18

10:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 444) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 4
  %13 = load i32, ptr %12, align 4, !tbaa !15
  %14 = add i32 %13, 4
  %15 = zext i32 %14 to i64
  %16 = tail call i32 @Xil_In32(i64 noundef %15)
  %17 = and i32 %16, -769
  switch i8 %1, label %default.unreachable [
    i8 0, label %25
    i8 1, label %19
    i8 2, label %21
    i8 3, label %23
  ]

18:                                               ; preds = %8
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 445) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

19:                                               ; preds = %11
  %20 = or disjoint i32 %17, 256
  br label %25

21:                                               ; preds = %11
  %22 = or disjoint i32 %17, 512
  br label %25

23:                                               ; preds = %11
  %24 = or i32 %16, 768
  br label %25

default.unreachable:                              ; preds = %11
  unreachable

25:                                               ; preds = %11, %23, %21, %19
  %.0 = phi i32 [ %24, %23 ], [ %22, %21 ], [ %20, %19 ], [ %17, %11 ]
  %26 = load i32, ptr %12, align 4, !tbaa !15
  %27 = add i32 %26, 4
  %28 = zext i32 %27 to i64
  tail call void @Xil_Out32(i64 noundef %28, i32 noundef %.0)
  br label %29

29:                                               ; preds = %25, %18, %10, %7
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 20}
!10 = !{!"", !11, i64 0, !6, i64 16, !6, i64 20, !6, i64 24, !13, i64 32, !13, i64 48, !14, i64 64, !14, i64 72, !6, i64 80, !7, i64 84}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12}
!12 = !{!"short", !7, i64 0}
!13 = !{!"", !14, i64 0, !6, i64 8, !6, i64 12}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass