; LLVM IR from greensoftwarelab/Energy-Languages :: C/chameneos-redux/chameneosredux.gcc-5 (color_complement)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [108 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [2 x i8], align 1
@__PRETTY_FUNCTION__.color_complement = external hidden unnamed_addr constant [58 x i8], align 1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @color_complement(i32 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  %6 = load i32, ptr %4, align 4, !tbaa !5
  switch i32 %6, label %25 [
    i32 0, label %7
    i32 1, label %13
    i32 2, label %19
  ]

7:                                                ; preds = %2
  %8 = load i32, ptr %5, align 4, !tbaa !5
  switch i32 %8, label %12 [
    i32 0, label %9
    i32 1, label %10
    i32 2, label %11
  ]

9:                                                ; preds = %7
  store i32 0, ptr %3, align 4
  br label %26

10:                                               ; preds = %7
  store i32 2, ptr %3, align 4
  br label %26

11:                                               ; preds = %7
  store i32 1, ptr %3, align 4
  br label %26

12:                                               ; preds = %7
  br label %13

13:                                               ; preds = %12, %2
  %14 = load i32, ptr %5, align 4, !tbaa !5
  switch i32 %14, label %18 [
    i32 0, label %15
    i32 1, label %16
    i32 2, label %17
  ]

15:                                               ; preds = %13
  store i32 2, ptr %3, align 4
  br label %26

16:                                               ; preds = %13
  store i32 1, ptr %3, align 4
  br label %26

17:                                               ; preds = %13
  store i32 0, ptr %3, align 4
  br label %26

18:                                               ; preds = %13
  br label %19

19:                                               ; preds = %18, %2
  %20 = load i32, ptr %5, align 4, !tbaa !5
  switch i32 %20, label %24 [
    i32 0, label %21
    i32 1, label %22
    i32 2, label %23
  ]

21:                                               ; preds = %19
  store i32 1, ptr %3, align 4
  br label %26

22:                                               ; preds = %19
  store i32 0, ptr %3, align 4
  br label %26

23:                                               ; preds = %19
  store i32 2, ptr %3, align 4
  br label %26

24:                                               ; preds = %19
  br label %25

25:                                               ; preds = %24, %2
  call void @__assert_fail(ptr noundef @.str.5, ptr noundef @.str.1, i32 noundef 87, ptr noundef @__PRETTY_FUNCTION__.color_complement) #2
  unreachable

26:                                               ; preds = %23, %22, %21, %17, %16, %15, %11, %10, %9
  %27 = load i32, ptr %3, align 4
  ret i32 %27
}

attributes #0 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.1 = external hidden unnamed_addr constant [108 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [2 x i8], align 1
@__PRETTY_FUNCTION__.color_complement = external hidden unnamed_addr constant [58 x i8], align 1
@switch.table.color_complement = private unnamed_addr constant [3 x i32] [i32 0, i32 2, i32 1], align 4
@switch.table.color_complement.1 = private unnamed_addr constant [3 x i32] [i32 1, i32 0, i32 2], align 4

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 3) i32 @color_complement(i32 noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  switch i32 %0, label %9 [
    i32 0, label %3
    i32 1, label %5
    i32 2, label %7
  ]

3:                                                ; preds = %2
  %4 = icmp ult i32 %1, 3
  br i1 %4, label %switch.lookup, label %9

5:                                                ; preds = %2
  %6 = icmp ult i32 %1, 3
  br i1 %6, label %switch.lookup5, label %9

7:                                                ; preds = %2
  %8 = icmp ult i32 %1, 3
  br i1 %8, label %switch.lookup6, label %9

9:                                                ; preds = %7, %5, %3, %2
  tail call void @__assert_fail(ptr noundef nonnull @.str.5, ptr noundef nonnull @.str.1, i32 noundef 87, ptr noundef nonnull @__PRETTY_FUNCTION__.color_complement) #2
  unreachable

switch.lookup:                                    ; preds = %3
  %10 = zext nneg i32 %1 to i64
  %switch.gep = getelementptr inbounds [3 x i32], ptr @switch.table.color_complement, i64 0, i64 %10
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %12

switch.lookup5:                                   ; preds = %5
  %switch.offset = sub nsw i32 2, %1
  br label %12

switch.lookup6:                                   ; preds = %7
  %11 = zext nneg i32 %1 to i64
  %switch.gep7 = getelementptr inbounds [3 x i32], ptr @switch.table.color_complement.1, i64 0, i64 %11
  %switch.load8 = load i32, ptr %switch.gep7, align 4
  br label %12

12:                                               ; preds = %switch.lookup6, %switch.lookup5, %switch.lookup
  %.0 = phi i32 [ %switch.load, %switch.lookup ], [ %switch.offset, %switch.lookup5 ], [ %switch.load8, %switch.lookup6 ]
  ret i32 %.0
}

attributes #0 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass