; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (SetPriTrigTypeByDistAddr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_SetPriTrigTypeByDistAddr(i32 noundef %0, i32 noundef %1, i8 noundef zeroext %2, i8 noundef zeroext %3) #2 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i8 %2, ptr %7, align 1, !tbaa !9
  store i8 %3, ptr %8, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  %12 = load i8, ptr %7, align 1, !tbaa !9
  store i8 %12, ptr %10, align 1, !tbaa !9
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = icmp ult i32 %13, 95
  br i1 %14, label %15, label %16

15:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %17

16:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 479)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %11, align 4
  br label %96

17:                                               ; preds = %15
  %18 = load i8, ptr %8, align 1, !tbaa !9
  %19 = zext i8 %18 to i32
  %20 = icmp ule i32 %19, 3
  br i1 %20, label %21, label %22

21:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

22:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 480)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %11, align 4
  br label %96

23:                                               ; preds = %21
  %24 = load i8, ptr %10, align 1, !tbaa !9
  %25 = zext i8 %24 to i32
  %26 = icmp ule i32 %25, 248
  br i1 %26, label %27, label %28

27:                                               ; preds = %23
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

28:                                               ; preds = %23
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 481)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %11, align 4
  br label %96

29:                                               ; preds = %27
  %30 = load i32, ptr %5, align 4, !tbaa !5
  %31 = load i32, ptr %6, align 4, !tbaa !5
  %32 = udiv i32 %31, 4
  %33 = mul i32 %32, 4
  %34 = add i32 1024, %33
  %35 = add i32 %30, %34
  %36 = zext i32 %35 to i64
  %37 = call i32 @Xil_In32(i64 noundef %36)
  store i32 %37, ptr %9, align 4, !tbaa !5
  %38 = load i8, ptr %10, align 1, !tbaa !9
  %39 = zext i8 %38 to i32
  %40 = and i32 %39, 248
  %41 = trunc i32 %40 to i8
  store i8 %41, ptr %10, align 1, !tbaa !9
  %42 = load i32, ptr %6, align 4, !tbaa !5
  %43 = urem i32 %42, 4
  %44 = mul i32 %43, 8
  %45 = shl i32 255, %44
  %46 = xor i32 %45, -1
  %47 = load i32, ptr %9, align 4, !tbaa !5
  %48 = and i32 %47, %46
  store i32 %48, ptr %9, align 4, !tbaa !5
  %49 = load i8, ptr %10, align 1, !tbaa !9
  %50 = zext i8 %49 to i32
  %51 = load i32, ptr %6, align 4, !tbaa !5
  %52 = urem i32 %51, 4
  %53 = mul i32 %52, 8
  %54 = shl i32 %50, %53
  %55 = load i32, ptr %9, align 4, !tbaa !5
  %56 = or i32 %55, %54
  store i32 %56, ptr %9, align 4, !tbaa !5
  %57 = load i32, ptr %5, align 4, !tbaa !5
  %58 = load i32, ptr %6, align 4, !tbaa !5
  %59 = udiv i32 %58, 4
  %60 = mul i32 %59, 4
  %61 = add i32 1024, %60
  %62 = add i32 %57, %61
  %63 = zext i32 %62 to i64
  %64 = load i32, ptr %9, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %63, i32 noundef %64)
  %65 = load i32, ptr %5, align 4, !tbaa !5
  %66 = load i32, ptr %6, align 4, !tbaa !5
  %67 = udiv i32 %66, 16
  %68 = mul i32 %67, 4
  %69 = add i32 3072, %68
  %70 = add i32 %65, %69
  %71 = zext i32 %70 to i64
  %72 = call i32 @Xil_In32(i64 noundef %71)
  store i32 %72, ptr %9, align 4, !tbaa !5
  %73 = load i32, ptr %6, align 4, !tbaa !5
  %74 = urem i32 %73, 16
  %75 = mul i32 %74, 2
  %76 = shl i32 3, %75
  %77 = xor i32 %76, -1
  %78 = load i32, ptr %9, align 4, !tbaa !5
  %79 = and i32 %78, %77
  store i32 %79, ptr %9, align 4, !tbaa !5
  %80 = load i8, ptr %8, align 1, !tbaa !9
  %81 = zext i8 %80 to i32
  %82 = load i32, ptr %6, align 4, !tbaa !5
  %83 = urem i32 %82, 16
  %84 = mul i32 %83, 2
  %85 = shl i32 %81, %84
  %86 = load i32, ptr %9, align 4, !tbaa !5
  %87 = or i32 %86, %85
  store i32 %87, ptr %9, align 4, !tbaa !5
  %88 = load i32, ptr %5, align 4, !tbaa !5
  %89 = load i32, ptr %6, align 4, !tbaa !5
  %90 = udiv i32 %89, 16
  %91 = mul i32 %90, 4
  %92 = add i32 3072, %91
  %93 = add i32 %88, %92
  %94 = zext i32 %93 to i64
  %95 = load i32, ptr %9, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %94, i32 noundef %95)
  store i32 0, ptr %11, align 4
  br label %96

96:                                               ; preds = %29, %28, %22, %16
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %97 = load i32, ptr %11, align 4
  switch i32 %97, label %99 [
    i32 0, label %98
    i32 1, label %98
  ]

98:                                               ; preds = %96, %96
  ret void

99:                                               ; preds = %96
  unreachable
}

declare void @Xil_Assert(ptr noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_SetPriTrigTypeByDistAddr(i32 noundef %0, i32 noundef %1, i8 noundef zeroext %2, i8 noundef zeroext %3) local_unnamed_addr #1 {
  %5 = icmp ult i32 %1, 95
  br i1 %5, label %6, label %9

6:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = zext i8 %3 to i32
  %8 = icmp ult i8 %3, 4
  br i1 %8, label %10, label %12

9:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 479) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

10:                                               ; preds = %6
  %11 = icmp ult i8 %2, -7
  br i1 %11, label %13, label %41

12:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 480) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

13:                                               ; preds = %10
  %14 = and i32 %1, 124
  %15 = add i32 %0, 1024
  %16 = add i32 %15, %14
  %17 = zext i32 %16 to i64
  %18 = tail call i32 @Xil_In32(i64 noundef %17)
  %19 = and i8 %2, -8
  %20 = shl nuw nsw i32 %1, 3
  %21 = and i32 %20, 24
  %22 = shl nuw i32 255, %21
  %23 = xor i32 %22, -1
  %24 = and i32 %18, %23
  %25 = zext i8 %19 to i32
  %26 = shl nuw i32 %25, %21
  %27 = or i32 %24, %26
  tail call void @Xil_Out32(i64 noundef %17, i32 noundef %27)
  %28 = lshr i32 %1, 2
  %29 = and i32 %28, 28
  %30 = add i32 %0, 3072
  %31 = add i32 %30, %29
  %32 = zext i32 %31 to i64
  %33 = tail call i32 @Xil_In32(i64 noundef %32)
  %34 = shl nuw nsw i32 %1, 1
  %35 = and i32 %34, 30
  %36 = shl nuw i32 3, %35
  %37 = xor i32 %36, -1
  %38 = and i32 %33, %37
  %39 = shl nuw i32 %7, %35
  %40 = or i32 %38, %39
  tail call void @Xil_Out32(i64 noundef %32, i32 noundef %40)
  br label %42

41:                                               ; preds = %10
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 481) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %42

42:                                               ; preds = %13, %41, %12, %9
  ret void
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass