; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (SetIntrType)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [168 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_SetIntrType(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i8 %1, ptr %7, align 1, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !10
  store i32 %3, ptr %9, align 4, !tbaa !10
  store i32 %4, ptr %10, align 4, !tbaa !10
  %11 = load ptr, ptr %6, align 8, !tbaa !5
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %15

14:                                               ; preds = %5
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 421)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %66

15:                                               ; preds = %13
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.XGpioPs, ptr %16, i32 0, i32 1
  %18 = load i32, ptr %17, align 8, !tbaa !12
  %19 = icmp eq i32 %18, 286331153
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %22

21:                                               ; preds = %15
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 422)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %66

22:                                               ; preds = %20
  %23 = load i8, ptr %7, align 1, !tbaa !9
  %24 = zext i8 %23 to i32
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.XGpioPs, ptr %25, i32 0, i32 6
  %27 = load i8, ptr %26, align 8, !tbaa !16
  %28 = zext i8 %27 to i32
  %29 = icmp slt i32 %24, %28
  br i1 %29, label %30, label %31

30:                                               ; preds = %22
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %32

31:                                               ; preds = %22
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 423)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %66

32:                                               ; preds = %30
  %33 = load ptr, ptr %6, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.XGpioPs, ptr %33, i32 0, i32 0
  %35 = getelementptr inbounds %struct.XGpioPs_Config, ptr %34, i32 0, i32 1
  %36 = load i32, ptr %35, align 4, !tbaa !17
  %37 = load i8, ptr %7, align 1, !tbaa !9
  %38 = zext i8 %37 to i32
  %39 = mul i32 %38, 64
  %40 = add i32 %39, 540
  %41 = add i32 %36, %40
  %42 = zext i32 %41 to i64
  %43 = load i32, ptr %8, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %42, i32 noundef %43)
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.XGpioPs, ptr %44, i32 0, i32 0
  %46 = getelementptr inbounds %struct.XGpioPs_Config, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !17
  %48 = load i8, ptr %7, align 1, !tbaa !9
  %49 = zext i8 %48 to i32
  %50 = mul i32 %49, 64
  %51 = add i32 %50, 544
  %52 = add i32 %47, %51
  %53 = zext i32 %52 to i64
  %54 = load i32, ptr %9, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %53, i32 noundef %54)
  %55 = load ptr, ptr %6, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.XGpioPs, ptr %55, i32 0, i32 0
  %57 = getelementptr inbounds %struct.XGpioPs_Config, ptr %56, i32 0, i32 1
  %58 = load i32, ptr %57, align 4, !tbaa !17
  %59 = load i8, ptr %7, align 1, !tbaa !9
  %60 = zext i8 %59 to i32
  %61 = mul i32 %60, 64
  %62 = add i32 %61, 548
  %63 = add i32 %58, %62
  %64 = zext i32 %63 to i64
  %65 = load i32, ptr %10, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %64, i32 noundef %65)
  br label %66

66:                                               ; preds = %32, %31, %21, %14
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !14, i64 0, !11, i64 8, !6, i64 16, !6, i64 24, !11, i64 32, !11, i64 36, !7, i64 40}
!14 = !{!"", !15, i64 0, !11, i64 4}
!15 = !{!"short", !7, i64 0}
!16 = !{!13, !7, i64 40}
!17 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [168 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_SetIntrType(ptr noundef readonly %0, i8 noundef zeroext %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %15

10:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 421) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

11:                                               ; preds = %6
  %12 = getelementptr inbounds i8, ptr %0, i64 40
  %13 = load i8, ptr %12, align 8, !tbaa !14
  %14 = icmp ugt i8 %13, %1
  br i1 %14, label %16, label %32

15:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 422) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

16:                                               ; preds = %11
  %17 = zext i8 %1 to i32
  %18 = getelementptr inbounds i8, ptr %0, i64 4
  %19 = load i32, ptr %18, align 4, !tbaa !15
  %20 = shl nuw nsw i32 %17, 6
  %21 = add nuw nsw i32 %20, 540
  %22 = add i32 %21, %19
  %23 = zext i32 %22 to i64
  tail call void @Xil_Out32(i64 noundef %23, i32 noundef %2)
  %24 = load i32, ptr %18, align 4, !tbaa !15
  %25 = add nuw nsw i32 %20, 544
  %26 = add i32 %25, %24
  %27 = zext i32 %26 to i64
  tail call void @Xil_Out32(i64 noundef %27, i32 noundef %3)
  %28 = load i32, ptr %18, align 4, !tbaa !15
  %29 = add nuw nsw i32 %20, 548
  %30 = add i32 %29, %28
  %31 = zext i32 %30 to i64
  tail call void @Xil_Out32(i64 noundef %31, i32 noundef %4)
  br label %33

32:                                               ; preds = %11
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 423) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

33:                                               ; preds = %16, %32, %15, %10
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !7, i64 40}
!15 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass