; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (ClkFreq)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Change_ClkFreq(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i16, align 2
  %7 = alloca i16, align 2
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #4
  store i16 0, ptr %8, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = icmp ne ptr %13, null
  br i1 %14, label %15, label %16

15:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 676)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %219

17:                                               ; preds = %15
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XSdPs, ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 4, !tbaa !13
  %21 = icmp eq i32 %20, 286331153
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %24

23:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 677)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %219

24:                                               ; preds = %22
  %25 = load ptr, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.XSdPs, ptr %25, i32 0, i32 0
  %27 = getelementptr inbounds %struct.XSdPs_Config, ptr %26, i32 0, i32 1
  %28 = load i32, ptr %27, align 4, !tbaa !17
  %29 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %28, i8 noundef zeroext 44)
  store i16 %29, ptr %6, align 2, !tbaa !11
  %30 = load i16, ptr %6, align 2, !tbaa !11
  %31 = zext i16 %30 to i32
  %32 = and i32 %31, -6
  %33 = trunc i32 %32 to i16
  store i16 %33, ptr %6, align 2, !tbaa !11
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.XSdPs, ptr %34, i32 0, i32 0
  %36 = getelementptr inbounds %struct.XSdPs_Config, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !17
  %38 = load i16, ptr %6, align 2, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %37, i8 noundef zeroext 44, i16 noundef zeroext %38)
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.XSdPs, ptr %39, i32 0, i32 7
  %41 = load i8, ptr %40, align 2, !tbaa !18
  %42 = zext i8 %41 to i32
  %43 = icmp eq i32 %42, 2
  br i1 %43, label %44, label %74

44:                                               ; preds = %24
  store i16 1, ptr %7, align 2, !tbaa !11
  br label %45

45:                                               ; preds = %65, %44
  %46 = load i16, ptr %7, align 2, !tbaa !11
  %47 = zext i16 %46 to i32
  %48 = icmp ule i32 %47, 2046
  br i1 %48, label %49, label %68

49:                                               ; preds = %45
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XSdPs, ptr %50, i32 0, i32 0
  %52 = getelementptr inbounds %struct.XSdPs_Config, ptr %51, i32 0, i32 2
  %53 = load i32, ptr %52, align 8, !tbaa !19
  %54 = load i16, ptr %7, align 2, !tbaa !11
  %55 = zext i16 %54 to i32
  %56 = udiv i32 %53, %55
  %57 = load i32, ptr %5, align 4, !tbaa !9
  %58 = icmp ule i32 %56, %57
  br i1 %58, label %59, label %64

59:                                               ; preds = %49
  %60 = load i16, ptr %7, align 2, !tbaa !11
  %61 = zext i16 %60 to i32
  %62 = ashr i32 %61, 1
  %63 = trunc i32 %62 to i16
  store i16 %63, ptr %8, align 2, !tbaa !11
  br label %68

64:                                               ; preds = %49
  br label %65

65:                                               ; preds = %64
  %66 = load i16, ptr %7, align 2, !tbaa !11
  %67 = add i16 %66, 1
  store i16 %67, ptr %7, align 2, !tbaa !11
  br label %45, !llvm.loop !20

68:                                               ; preds = %59, %45
  %69 = load i16, ptr %7, align 2, !tbaa !11
  %70 = zext i16 %69 to i32
  %71 = icmp ugt i32 %70, 2046
  br i1 %71, label %72, label %73

72:                                               ; preds = %68
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %217

73:                                               ; preds = %68
  br label %105

74:                                               ; preds = %24
  store i16 1, ptr %7, align 2, !tbaa !11
  br label %75

75:                                               ; preds = %94, %74
  %76 = load i16, ptr %7, align 2, !tbaa !11
  %77 = zext i16 %76 to i32
  %78 = icmp ule i32 %77, 256
  br i1 %78, label %79, label %99

79:                                               ; preds = %75
  %80 = load ptr, ptr %4, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.XSdPs, ptr %80, i32 0, i32 0
  %82 = getelementptr inbounds %struct.XSdPs_Config, ptr %81, i32 0, i32 2
  %83 = load i32, ptr %82, align 8, !tbaa !19
  %84 = load i16, ptr %7, align 2, !tbaa !11
  %85 = zext i16 %84 to i32
  %86 = udiv i32 %83, %85
  %87 = load i32, ptr %5, align 4, !tbaa !9
  %88 = icmp ule i32 %86, %87
  br i1 %88, label %89, label %94

89:                                               ; preds = %79
  %90 = load i16, ptr %7, align 2, !tbaa !11
  %91 = zext i16 %90 to i32
  %92 = udiv i32 %91, 2
  %93 = trunc i32 %92 to i16
  store i16 %93, ptr %8, align 2, !tbaa !11
  br label %99

94:                                               ; preds = %79
  %95 = load i16, ptr %7, align 2, !tbaa !11
  %96 = zext i16 %95 to i32
  %97 = shl i32 %96, 1
  %98 = trunc i32 %97 to i16
  store i16 %98, ptr %7, align 2, !tbaa !11
  br label %75, !llvm.loop !22

99:                                               ; preds = %89, %75
  %100 = load i16, ptr %7, align 2, !tbaa !11
  %101 = zext i16 %100 to i32
  %102 = icmp ugt i32 %101, 256
  br i1 %102, label %103, label %104

103:                                              ; preds = %99
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %217

104:                                              ; preds = %99
  br label %105

105:                                              ; preds = %104, %73
  %106 = load ptr, ptr %4, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.XSdPs, ptr %106, i32 0, i32 7
  %108 = load i8, ptr %107, align 2, !tbaa !18
  %109 = zext i8 %108 to i32
  %110 = icmp eq i32 %109, 2
  br i1 %110, label %111, label %156

111:                                              ; preds = %105
  %112 = load ptr, ptr %4, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.XSdPs, ptr %112, i32 0, i32 0
  %114 = getelementptr inbounds %struct.XSdPs_Config, ptr %113, i32 0, i32 1
  %115 = load i32, ptr %114, align 4, !tbaa !17
  %116 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %115, i8 noundef zeroext 44)
  store i16 %116, ptr %6, align 2, !tbaa !11
  %117 = load i16, ptr %6, align 2, !tbaa !11
  %118 = zext i16 %117 to i32
  %119 = and i32 %118, -65473
  %120 = trunc i32 %119 to i16
  store i16 %120, ptr %6, align 2, !tbaa !11
  %121 = load i16, ptr %8, align 2, !tbaa !11
  %122 = zext i16 %121 to i32
  %123 = ashr i32 %122, 8
  %124 = trunc i32 %123 to i16
  store i16 %124, ptr %9, align 2, !tbaa !11
  %125 = load i16, ptr %9, align 2, !tbaa !11
  %126 = zext i16 %125 to i32
  %127 = shl i32 %126, 6
  %128 = trunc i32 %127 to i16
  store i16 %128, ptr %9, align 2, !tbaa !11
  %129 = load i16, ptr %9, align 2, !tbaa !11
  %130 = zext i16 %129 to i32
  %131 = and i32 %130, 192
  %132 = trunc i32 %131 to i16
  store i16 %132, ptr %9, align 2, !tbaa !11
  %133 = load i16, ptr %8, align 2, !tbaa !11
  %134 = zext i16 %133 to i32
  %135 = shl i32 %134, 8
  %136 = trunc i32 %135 to i16
  store i16 %136, ptr %8, align 2, !tbaa !11
  %137 = load i16, ptr %8, align 2, !tbaa !11
  %138 = zext i16 %137 to i32
  %139 = and i32 %138, 65280
  %140 = trunc i32 %139 to i16
  store i16 %140, ptr %8, align 2, !tbaa !11
  %141 = load i16, ptr %8, align 2, !tbaa !11
  %142 = zext i16 %141 to i32
  %143 = load i16, ptr %9, align 2, !tbaa !11
  %144 = zext i16 %143 to i32
  %145 = or i32 %142, %144
  %146 = or i32 %145, 1
  %147 = load i16, ptr %6, align 2, !tbaa !11
  %148 = zext i16 %147 to i32
  %149 = or i32 %148, %146
  %150 = trunc i32 %149 to i16
  store i16 %150, ptr %6, align 2, !tbaa !11
  %151 = load ptr, ptr %4, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.XSdPs, ptr %151, i32 0, i32 0
  %153 = getelementptr inbounds %struct.XSdPs_Config, ptr %152, i32 0, i32 1
  %154 = load i32, ptr %153, align 4, !tbaa !17
  %155 = load i16, ptr %6, align 2, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %154, i8 noundef zeroext 44, i16 noundef zeroext %155)
  br label %186

156:                                              ; preds = %105
  %157 = load ptr, ptr %4, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.XSdPs, ptr %157, i32 0, i32 0
  %159 = getelementptr inbounds %struct.XSdPs_Config, ptr %158, i32 0, i32 1
  %160 = load i32, ptr %159, align 4, !tbaa !17
  %161 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %160, i8 noundef zeroext 44)
  store i16 %161, ptr %6, align 2, !tbaa !11
  %162 = load i16, ptr %6, align 2, !tbaa !11
  %163 = zext i16 %162 to i32
  %164 = and i32 %163, -65281
  %165 = trunc i32 %164 to i16
  store i16 %165, ptr %6, align 2, !tbaa !11
  %166 = load i16, ptr %8, align 2, !tbaa !11
  %167 = zext i16 %166 to i32
  %168 = shl i32 %167, 8
  %169 = trunc i32 %168 to i16
  store i16 %169, ptr %8, align 2, !tbaa !11
  %170 = load i16, ptr %8, align 2, !tbaa !11
  %171 = zext i16 %170 to i32
  %172 = and i32 %171, 65280
  %173 = trunc i32 %172 to i16
  store i16 %173, ptr %8, align 2, !tbaa !11
  %174 = load i16, ptr %8, align 2, !tbaa !11
  %175 = zext i16 %174 to i32
  %176 = or i32 %175, 1
  %177 = load i16, ptr %6, align 2, !tbaa !11
  %178 = zext i16 %177 to i32
  %179 = or i32 %178, %176
  %180 = trunc i32 %179 to i16
  store i16 %180, ptr %6, align 2, !tbaa !11
  %181 = load ptr, ptr %4, align 8, !tbaa !5
  %182 = getelementptr inbounds %struct.XSdPs, ptr %181, i32 0, i32 0
  %183 = getelementptr inbounds %struct.XSdPs_Config, ptr %182, i32 0, i32 1
  %184 = load i32, ptr %183, align 4, !tbaa !17
  %185 = load i16, ptr %6, align 2, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %184, i8 noundef zeroext 44, i16 noundef zeroext %185)
  br label %186

186:                                              ; preds = %156, %111
  %187 = load ptr, ptr %4, align 8, !tbaa !5
  %188 = getelementptr inbounds %struct.XSdPs, ptr %187, i32 0, i32 0
  %189 = getelementptr inbounds %struct.XSdPs_Config, ptr %188, i32 0, i32 1
  %190 = load i32, ptr %189, align 4, !tbaa !17
  %191 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %190, i8 noundef zeroext 44)
  store i16 %191, ptr %11, align 2, !tbaa !11
  br label %192

192:                                              ; preds = %197, %186
  %193 = load i16, ptr %11, align 2, !tbaa !11
  %194 = zext i16 %193 to i32
  %195 = and i32 %194, 2
  %196 = icmp eq i32 %195, 0
  br i1 %196, label %197, label %203

197:                                              ; preds = %192
  %198 = load ptr, ptr %4, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.XSdPs, ptr %198, i32 0, i32 0
  %200 = getelementptr inbounds %struct.XSdPs_Config, ptr %199, i32 0, i32 1
  %201 = load i32, ptr %200, align 4, !tbaa !17
  %202 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %201, i8 noundef zeroext 44)
  store i16 %202, ptr %11, align 2, !tbaa !11
  br label %192, !llvm.loop !23

203:                                              ; preds = %192
  %204 = load ptr, ptr %4, align 8, !tbaa !5
  %205 = getelementptr inbounds %struct.XSdPs, ptr %204, i32 0, i32 0
  %206 = getelementptr inbounds %struct.XSdPs_Config, ptr %205, i32 0, i32 1
  %207 = load i32, ptr %206, align 4, !tbaa !17
  %208 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %207, i8 noundef zeroext 44)
  store i16 %208, ptr %6, align 2, !tbaa !11
  %209 = load ptr, ptr %4, align 8, !tbaa !5
  %210 = getelementptr inbounds %struct.XSdPs, ptr %209, i32 0, i32 0
  %211 = getelementptr inbounds %struct.XSdPs_Config, ptr %210, i32 0, i32 1
  %212 = load i32, ptr %211, align 4, !tbaa !17
  %213 = load i16, ptr %6, align 2, !tbaa !11
  %214 = zext i16 %213 to i32
  %215 = or i32 %214, 4
  %216 = trunc i32 %215 to i16
  call void @XSdPs_WriteReg16(i32 noundef %212, i8 noundef zeroext 44, i16 noundef zeroext %216)
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %217

217:                                              ; preds = %203, %103, %72
  %218 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %218, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %219

219:                                              ; preds = %217, %23, %16
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #4
  %220 = load i32, ptr %3, align 4
  ret i32 %220
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!14, !10, i64 36}
!14 = !{!"", !15, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !16, i64 512}
!15 = !{!"", !12, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!16 = !{!"long", !7, i64 0}
!17 = !{!14, !10, i64 4}
!18 = !{!14, !7, i64 54}
!19 = !{!14, !10, i64 8}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = distinct !{!22, !21}
!23 = distinct !{!23, !21}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Change_ClkFreq(ptr noundef readonly %0, i32 noundef %1) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 36
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %19

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 676) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %.thread

8:                                                ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 4
  %10 = load i32, ptr %9, align 4, !tbaa !15
  %11 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %10, i8 noundef zeroext 44)
  %12 = and i16 %11, -6
  %13 = load i32, ptr %9, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %13, i8 noundef zeroext 44, i16 noundef zeroext %12)
  %14 = getelementptr inbounds i8, ptr %0, i64 54
  %15 = load i8, ptr %14, align 2, !tbaa !16
  %16 = icmp eq i8 %15, 2
  %17 = getelementptr inbounds i8, ptr %0, i64 8
  %18 = load i32, ptr %17, align 8, !tbaa !17
  br i1 %16, label %.preheader, label %.preheader62

.preheader62:                                     ; preds = %8
  %.not57 = icmp ugt i32 %18, %1
  br i1 %.not57, label %24, label %.thread71

19:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 677) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %.thread

.preheader:                                       ; preds = %8, %23
  %indvars.iv = phi i32 [ %indvars.iv.next.2, %23 ], [ 1, %8 ]
  %20 = udiv i32 %18, %indvars.iv
  %.not58 = icmp ugt i32 %20, %1
  br i1 %.not58, label %.preheader.1, label %40

.preheader.1:                                     ; preds = %.preheader
  %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
  %21 = udiv i32 %18, %indvars.iv.next
  %.not58.1 = icmp ugt i32 %21, %1
  br i1 %.not58.1, label %.preheader.2, label %40

.preheader.2:                                     ; preds = %.preheader.1
  %indvars.iv.next.1 = add nuw nsw i32 %indvars.iv, 2
  %22 = udiv i32 %18, %indvars.iv.next.1
  %.not58.2 = icmp ugt i32 %22, %1
  br i1 %.not58.2, label %23, label %40

23:                                               ; preds = %.preheader.2
  %indvars.iv.next.2 = add nuw nsw i32 %indvars.iv, 3
  %exitcond.not.2 = icmp eq i32 %indvars.iv.next.2, 2047
  br i1 %exitcond.not.2, label %.thread, label %.preheader, !llvm.loop !18

24:                                               ; preds = %.preheader62
  %25 = lshr i32 %18, 1
  %.not57.1 = icmp ugt i32 %25, %1
  br i1 %.not57.1, label %26, label %.thread71

26:                                               ; preds = %24
  %27 = lshr i32 %18, 2
  %.not57.2 = icmp ugt i32 %27, %1
  br i1 %.not57.2, label %28, label %.thread71

28:                                               ; preds = %26
  %29 = lshr i32 %18, 3
  %.not57.3 = icmp ugt i32 %29, %1
  br i1 %.not57.3, label %30, label %.thread71

30:                                               ; preds = %28
  %31 = lshr i32 %18, 4
  %.not57.4 = icmp ugt i32 %31, %1
  br i1 %.not57.4, label %32, label %.thread71

32:                                               ; preds = %30
  %33 = lshr i32 %18, 5
  %.not57.5 = icmp ugt i32 %33, %1
  br i1 %.not57.5, label %34, label %.thread71

34:                                               ; preds = %32
  %35 = lshr i32 %18, 6
  %.not57.6 = icmp ugt i32 %35, %1
  br i1 %.not57.6, label %36, label %.thread71

36:                                               ; preds = %34
  %37 = lshr i32 %18, 7
  %.not57.7 = icmp ugt i32 %37, %1
  br i1 %.not57.7, label %38, label %.thread71

38:                                               ; preds = %36
  %39 = lshr i32 %18, 8
  %.not57.8 = icmp ugt i32 %39, %1
  br i1 %.not57.8, label %.thread, label %.thread71

40:                                               ; preds = %.preheader.2, %.preheader.1, %.preheader
  %indvars.iv.lcssa = phi i32 [ %indvars.iv, %.preheader ], [ %indvars.iv.next, %.preheader.1 ], [ %indvars.iv.next.1, %.preheader.2 ]
  %41 = trunc nuw nsw i32 %indvars.iv.lcssa to i16
  %42 = lshr i16 %41, 1
  br i1 %16, label %43, label %.thread71

43:                                               ; preds = %40
  %44 = load i32, ptr %9, align 4, !tbaa !15
  %45 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %44, i8 noundef zeroext 44)
  %46 = and i16 %45, 62
  %47 = lshr i16 %41, 3
  %48 = and i16 %47, 192
  %49 = shl i16 %42, 8
  %50 = or disjoint i16 %48, %49
  br label %55

.thread71:                                        ; preds = %38, %36, %34, %32, %30, %28, %26, %24, %.preheader62, %40
  %.273 = phi i16 [ %42, %40 ], [ 128, %38 ], [ 64, %36 ], [ 32, %34 ], [ 16, %32 ], [ 8, %30 ], [ 4, %28 ], [ 2, %26 ], [ 1, %24 ], [ 0, %.preheader62 ]
  %51 = load i32, ptr %9, align 4, !tbaa !15
  %52 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %51, i8 noundef zeroext 44)
  %53 = and i16 %52, 254
  %54 = shl i16 %.273, 8
  br label %55

55:                                               ; preds = %.thread71, %43
  %.sink77 = phi i16 [ %54, %.thread71 ], [ %50, %43 ]
  %.sink = phi i16 [ %53, %.thread71 ], [ %46, %43 ]
  %56 = or disjoint i16 %.sink77, 1
  %57 = or disjoint i16 %.sink, %56
  %58 = load i32, ptr %9, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %58, i8 noundef zeroext 44, i16 noundef zeroext %57)
  %59 = load i32, ptr %9, align 4, !tbaa !15
  %60 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %59, i8 noundef zeroext 44)
  %61 = and i16 %60, 2
  %62 = icmp eq i16 %61, 0
  br i1 %62, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %55, %.lr.ph
  %63 = load i32, ptr %9, align 4, !tbaa !15
  %64 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %63, i8 noundef zeroext 44)
  %65 = and i16 %64, 2
  %66 = icmp eq i16 %65, 0
  br i1 %66, label %.lr.ph, label %._crit_edge, !llvm.loop !20

._crit_edge:                                      ; preds = %.lr.ph, %55
  %67 = load i32, ptr %9, align 4, !tbaa !15
  %68 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %67, i8 noundef zeroext 44)
  %69 = load i32, ptr %9, align 4, !tbaa !15
  %70 = or i16 %68, 4
  tail call void @XSdPs_WriteReg16(i32 noundef %69, i8 noundef zeroext 44, i16 noundef zeroext %70)
  br label %.thread

.thread:                                          ; preds = %23, %38, %._crit_edge, %19, %7
  %.050 = phi i32 [ 0, %19 ], [ 0, %7 ], [ 0, %._crit_edge ], [ 1, %38 ], [ 1, %23 ]
  ret i32 %.050
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !13, i64 112, !7, i64 128, !14, i64 512}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!10, !6, i64 4}
!16 = !{!10, !7, i64 54}
!17 = !{!10, !6, i64 8}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = distinct !{!20, !19}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass