; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2 (CfgInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuWdt = type { %struct.XScuWdt_Config, i32, i32 }
%struct.XScuWdt_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XScuWdt_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 86)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

14:                                               ; preds = %12
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp ne ptr %15, null
  br i1 %16, label %17, label %18

17:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 87)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

19:                                               ; preds = %17
  %20 = load i32, ptr %7, align 4, !tbaa !9
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %23

22:                                               ; preds = %19
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %24

23:                                               ; preds = %19
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 88)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

24:                                               ; preds = %22
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.XScuWdt, ptr %25, i32 0, i32 2
  %27 = load i32, ptr %26, align 4, !tbaa !11
  %28 = icmp eq i32 %27, 572662306
  br i1 %28, label %29, label %30

29:                                               ; preds = %24
  store i32 5, ptr %8, align 4, !tbaa !9
  br label %59

30:                                               ; preds = %24
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.XScuWdt_Config, ptr %31, i32 0, i32 0
  %33 = load i16, ptr %32, align 4, !tbaa !15
  %34 = load ptr, ptr %5, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.XScuWdt, ptr %34, i32 0, i32 0
  %36 = getelementptr inbounds %struct.XScuWdt_Config, ptr %35, i32 0, i32 0
  store i16 %33, ptr %36, align 4, !tbaa !16
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XScuWdt, ptr %38, i32 0, i32 0
  %40 = getelementptr inbounds %struct.XScuWdt_Config, ptr %39, i32 0, i32 1
  store i32 %37, ptr %40, align 4, !tbaa !17
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.XScuWdt, ptr %41, i32 0, i32 2
  store i32 0, ptr %42, align 4, !tbaa !11
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.XScuWdt, ptr %43, i32 0, i32 0
  %45 = getelementptr inbounds %struct.XScuWdt_Config, ptr %44, i32 0, i32 1
  %46 = load i32, ptr %45, align 4, !tbaa !17
  %47 = add i32 %46, 8
  %48 = zext i32 %47 to i64
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XScuWdt, ptr %49, i32 0, i32 0
  %51 = getelementptr inbounds %struct.XScuWdt_Config, ptr %50, i32 0, i32 1
  %52 = load i32, ptr %51, align 4, !tbaa !17
  %53 = add i32 %52, 8
  %54 = zext i32 %53 to i64
  %55 = call i32 @Xil_In32(i64 noundef %54)
  %56 = or i32 %55, 8
  call void @Xil_Out32(i64 noundef %48, i32 noundef %56)
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.XScuWdt, ptr %57, i32 0, i32 1
  store i32 286331153, ptr %58, align 4, !tbaa !18
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %59

59:                                               ; preds = %30, %29
  %60 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %60, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %61

61:                                               ; preds = %59, %23, %18, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %62 = load i32, ptr %4, align 4
  ret i32 %62
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 12}
!12 = !{!"", !13, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}
!15 = !{!13, !14, i64 0}
!16 = !{!12, !14, i64 0}
!17 = !{!12, !10, i64 4}
!18 = !{!12, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 6) i32 @XScuWdt_CfgInitialize(ptr noundef %0, ptr noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %5, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not17 = icmp eq ptr %1, null
  br i1 %.not17, label %7, label %6

5:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 86) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %21

6:                                                ; preds = %4
  %.not18 = icmp eq i32 %2, 0
  br i1 %.not18, label %12, label %8

7:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 87) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %21

8:                                                ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 12
  %10 = load i32, ptr %9, align 4, !tbaa !9
  %11 = icmp eq i32 %10, 572662306
  br i1 %11, label %21, label %13

12:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 88) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %21

13:                                               ; preds = %8
  %14 = load i16, ptr %1, align 4, !tbaa !13
  store i16 %14, ptr %0, align 4, !tbaa !14
  %15 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 %2, ptr %15, align 4, !tbaa !15
  store i32 0, ptr %9, align 4, !tbaa !9
  %16 = add i32 %2, 8
  %17 = zext i32 %16 to i64
  %18 = tail call i32 @Xil_In32(i64 noundef %17)
  %19 = or i32 %18, 8
  tail call void @Xil_Out32(i64 noundef %17, i32 noundef %19)
  %20 = getelementptr inbounds i8, ptr %0, i64 8
  store i32 286331153, ptr %20, align 4, !tbaa !16
  br label %21

21:                                               ; preds = %13, %8, %12, %7, %5
  %.013 = phi i32 [ 0, %12 ], [ 0, %7 ], [ 0, %5 ], [ 0, %13 ], [ 5, %8 ]
  ret i32 %.013
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 12}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!11, !12, i64 0}
!14 = !{!10, !12, i64 0}
!15 = !{!10, !6, i64 4}
!16 = !{!10, !6, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass