; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (UnmapAllInterruptsFromCpuByDistAddr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_UnmapAllInterruptsFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca i8, align 1
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i8 %1, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %8 = load i8, ptr %4, align 1, !tbaa !9
  %9 = zext i8 %8 to i32
  %10 = shl i32 1, %9
  store i32 %10, ptr %7, align 4, !tbaa !5
  %11 = load i32, ptr %7, align 4, !tbaa !5
  %12 = shl i32 %11, 8
  %13 = load i32, ptr %7, align 4, !tbaa !5
  %14 = or i32 %13, %12
  store i32 %14, ptr %7, align 4, !tbaa !5
  %15 = load i32, ptr %7, align 4, !tbaa !5
  %16 = shl i32 %15, 16
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = or i32 %17, %16
  store i32 %18, ptr %7, align 4, !tbaa !5
  store i32 32, ptr %5, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %43, %2
  %20 = load i32, ptr %5, align 4, !tbaa !5
  %21 = icmp ult i32 %20, 95
  br i1 %21, label %22, label %46

22:                                               ; preds = %19
  %23 = load i32, ptr %3, align 4, !tbaa !5
  %24 = load i32, ptr %5, align 4, !tbaa !5
  %25 = udiv i32 %24, 4
  %26 = mul i32 %25, 4
  %27 = add i32 2048, %26
  %28 = add i32 %23, %27
  %29 = zext i32 %28 to i64
  %30 = call i32 @Xil_In32(i64 noundef %29)
  store i32 %30, ptr %6, align 4, !tbaa !5
  %31 = load i32, ptr %7, align 4, !tbaa !5
  %32 = xor i32 %31, -1
  %33 = load i32, ptr %6, align 4, !tbaa !5
  %34 = and i32 %33, %32
  store i32 %34, ptr %6, align 4, !tbaa !5
  %35 = load i32, ptr %3, align 4, !tbaa !5
  %36 = load i32, ptr %5, align 4, !tbaa !5
  %37 = udiv i32 %36, 4
  %38 = mul i32 %37, 4
  %39 = add i32 2048, %38
  %40 = add i32 %35, %39
  %41 = zext i32 %40 to i64
  %42 = load i32, ptr %6, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %41, i32 noundef %42)
  br label %43

43:                                               ; preds = %22
  %44 = load i32, ptr %5, align 4, !tbaa !5
  %45 = add i32 %44, 4
  store i32 %45, ptr %5, align 4, !tbaa !5
  br label %19, !llvm.loop !10

46:                                               ; preds = %19
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_UnmapAllInterruptsFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1) local_unnamed_addr #1 {
  %3 = zext nneg i8 %1 to i32
  %4 = shl i32 16843009, %3
  %5 = xor i32 %4, -1
  %6 = add i32 %0, 2080
  %7 = zext i32 %6 to i64
  %8 = tail call i32 @Xil_In32(i64 noundef %7)
  %9 = and i32 %8, %5
  tail call void @Xil_Out32(i64 noundef %7, i32 noundef %9)
  %10 = add i32 %0, 2084
  %11 = zext i32 %10 to i64
  %12 = tail call i32 @Xil_In32(i64 noundef %11)
  %13 = and i32 %12, %5
  tail call void @Xil_Out32(i64 noundef %11, i32 noundef %13)
  %14 = add i32 %0, 2088
  %15 = zext i32 %14 to i64
  %16 = tail call i32 @Xil_In32(i64 noundef %15)
  %17 = and i32 %16, %5
  tail call void @Xil_Out32(i64 noundef %15, i32 noundef %17)
  %18 = add i32 %0, 2092
  %19 = zext i32 %18 to i64
  %20 = tail call i32 @Xil_In32(i64 noundef %19)
  %21 = and i32 %20, %5
  tail call void @Xil_Out32(i64 noundef %19, i32 noundef %21)
  %22 = add i32 %0, 2096
  %23 = zext i32 %22 to i64
  %24 = tail call i32 @Xil_In32(i64 noundef %23)
  %25 = and i32 %24, %5
  tail call void @Xil_Out32(i64 noundef %23, i32 noundef %25)
  %26 = add i32 %0, 2100
  %27 = zext i32 %26 to i64
  %28 = tail call i32 @Xil_In32(i64 noundef %27)
  %29 = and i32 %28, %5
  tail call void @Xil_Out32(i64 noundef %27, i32 noundef %29)
  %30 = add i32 %0, 2104
  %31 = zext i32 %30 to i64
  %32 = tail call i32 @Xil_In32(i64 noundef %31)
  %33 = and i32 %32, %5
  tail call void @Xil_Out32(i64 noundef %31, i32 noundef %33)
  %34 = add i32 %0, 2108
  %35 = zext i32 %34 to i64
  %36 = tail call i32 @Xil_In32(i64 noundef %35)
  %37 = and i32 %36, %5
  tail call void @Xil_Out32(i64 noundef %35, i32 noundef %37)
  %38 = add i32 %0, 2112
  %39 = zext i32 %38 to i64
  %40 = tail call i32 @Xil_In32(i64 noundef %39)
  %41 = and i32 %40, %5
  tail call void @Xil_Out32(i64 noundef %39, i32 noundef %41)
  %42 = add i32 %0, 2116
  %43 = zext i32 %42 to i64
  %44 = tail call i32 @Xil_In32(i64 noundef %43)
  %45 = and i32 %44, %5
  tail call void @Xil_Out32(i64 noundef %43, i32 noundef %45)
  %46 = add i32 %0, 2120
  %47 = zext i32 %46 to i64
  %48 = tail call i32 @Xil_In32(i64 noundef %47)
  %49 = and i32 %48, %5
  tail call void @Xil_Out32(i64 noundef %47, i32 noundef %49)
  %50 = add i32 %0, 2124
  %51 = zext i32 %50 to i64
  %52 = tail call i32 @Xil_In32(i64 noundef %51)
  %53 = and i32 %52, %5
  tail call void @Xil_Out32(i64 noundef %51, i32 noundef %53)
  %54 = add i32 %0, 2128
  %55 = zext i32 %54 to i64
  %56 = tail call i32 @Xil_In32(i64 noundef %55)
  %57 = and i32 %56, %5
  tail call void @Xil_Out32(i64 noundef %55, i32 noundef %57)
  %58 = add i32 %0, 2132
  %59 = zext i32 %58 to i64
  %60 = tail call i32 @Xil_In32(i64 noundef %59)
  %61 = and i32 %60, %5
  tail call void @Xil_Out32(i64 noundef %59, i32 noundef %61)
  %62 = add i32 %0, 2136
  %63 = zext i32 %62 to i64
  %64 = tail call i32 @Xil_In32(i64 noundef %63)
  %65 = and i32 %64, %5
  tail call void @Xil_Out32(i64 noundef %63, i32 noundef %65)
  %66 = add i32 %0, 2140
  %67 = zext i32 %66 to i64
  %68 = tail call i32 @Xil_In32(i64 noundef %67)
  %69 = and i32 %68, %5
  tail call void @Xil_Out32(i64 noundef %67, i32 noundef %69)
  ret void
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass