; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (SetSeqAvgEnables)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }
%struct.XAdcPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XAdcPs_SetSeqAvgEnables(ptr noundef %0, i32 noundef %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  %7 = icmp ne ptr %6, null
  br i1 %7, label %8, label %9

8:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %10

9:                                                ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1123)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  br label %31

10:                                               ; preds = %8
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.XAdcPs, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 4, !tbaa !11
  %14 = icmp eq i32 %13, 286331153
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %10
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1124)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  br label %31

17:                                               ; preds = %15
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = call zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef %18)
  %20 = zext i8 %19 to i32
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 1, ptr %3, align 4
  br label %31

23:                                               ; preds = %17
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = and i32 %25, 32736
  call void @XAdcPs_WriteInternalReg(ptr noundef %24, i32 noundef 74, i32 noundef %26)
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = load i32, ptr %5, align 4, !tbaa !9
  %29 = lshr i32 %28, 16
  %30 = and i32 %29, 65535
  call void @XAdcPs_WriteInternalReg(ptr noundef %27, i32 noundef 75, i32 noundef %30)
  store i32 0, ptr %3, align 4
  br label %31

31:                                               ; preds = %23, %22, %16, %9
  %32 = load i32, ptr %3, align 4
  ret i32 %32
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XAdcPs_SetSeqAvgEnables(ptr noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %10

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1123) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %14

8:                                                ; preds = %3
  %9 = tail call zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef nonnull %0)
  %.not8 = icmp eq i8 %9, 0
  br i1 %.not8, label %11, label %14

10:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1124) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %14

11:                                               ; preds = %8
  %12 = and i32 %1, 32736
  tail call void @XAdcPs_WriteInternalReg(ptr noundef nonnull %0, i32 noundef 74, i32 noundef %12)
  %13 = lshr i32 %1, 16
  tail call void @XAdcPs_WriteInternalReg(ptr noundef nonnull %0, i32 noundef 75, i32 noundef %13)
  br label %14

14:                                               ; preds = %8, %11, %10, %7
  %.0 = phi i32 [ 0, %11 ], [ 0, %10 ], [ 0, %7 ], [ 1, %8 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass