; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000/src/ARINC653_PORT (interrupt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@INTERRUPT_VECTORTABLE = external dso_local global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicConfigPtr = external hidden global [2 x ptr], align 16
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @INTERRUPT_STARTUP() #0 {
  %1 = alloca i8, align 1
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @SPINLOCK_LOCK(ptr noundef @INTERRUPT_SPINLOCK)
  %7 = call i32 @CP15CoreIDGet()
  store i32 %7, ptr %2, align 4, !tbaa !5
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %8

8:                                                ; preds = %19, %0
  %9 = load i32, ptr %3, align 4, !tbaa !5
  %10 = icmp ult i32 %9, 95
  br i1 %10, label %11, label %22

11:                                               ; preds = %8
  %12 = load i32, ptr %2, align 4, !tbaa !5
  %13 = zext i32 %12 to i64
  %14 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %13
  %15 = load ptr, ptr %14, align 8, !tbaa !9
  %16 = load i32, ptr %3, align 4, !tbaa !5
  %17 = zext i32 %16 to i64
  %18 = getelementptr inbounds ptr, ptr %15, i64 %17
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %18, align 8, !tbaa !9
  br label %19

19:                                               ; preds = %11
  %20 = load i32, ptr %3, align 4, !tbaa !5
  %21 = add i32 %20, 1
  store i32 %21, ptr %3, align 4, !tbaa !5
  br label %8, !llvm.loop !11

22:                                               ; preds = %8
  %23 = load i32, ptr %2, align 4, !tbaa !5
  call void @XScuGic_SetCpuID(i32 noundef %23)
  %24 = call ptr @XScuGic_LookupConfig(i16 noundef zeroext 0)
  %25 = load i32, ptr %2, align 4, !tbaa !5
  %26 = zext i32 %25 to i64
  %27 = getelementptr inbounds [2 x ptr], ptr @XScuGicConfigPtr, i64 0, i64 %26
  store ptr %24, ptr %27, align 8, !tbaa !9
  %28 = load i32, ptr %2, align 4, !tbaa !5
  %29 = zext i32 %28 to i64
  %30 = getelementptr inbounds [2 x ptr], ptr @XScuGicConfigPtr, i64 0, i64 %29
  %31 = load ptr, ptr %30, align 8, !tbaa !9
  %32 = icmp eq ptr %31, null
  br i1 %32, label %33, label %34

33:                                               ; preds = %22
  br label %57

34:                                               ; preds = %22
  %35 = load i32, ptr %2, align 4, !tbaa !5
  %36 = zext i32 %35 to i64
  %37 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %36
  %38 = load i32, ptr %2, align 4, !tbaa !5
  %39 = zext i32 %38 to i64
  %40 = getelementptr inbounds [2 x ptr], ptr @XScuGicConfigPtr, i64 0, i64 %39
  %41 = load ptr, ptr %40, align 8, !tbaa !9
  %42 = load i32, ptr %2, align 4, !tbaa !5
  %43 = zext i32 %42 to i64
  %44 = getelementptr inbounds [2 x ptr], ptr @XScuGicConfigPtr, i64 0, i64 %43
  %45 = load ptr, ptr %44, align 8, !tbaa !9
  %46 = getelementptr inbounds %struct.XScuGic_Config, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !13
  %48 = call i32 @XScuGic_CfgInitialize(ptr noundef %37, ptr noundef %41, i32 noundef %47)
  %49 = sext i32 %48 to i64
  %50 = icmp ne i64 %49, 0
  br i1 %50, label %51, label %52

51:                                               ; preds = %34
  br label %57

52:                                               ; preds = %34
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  %53 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !16
  store i32 %53, ptr %4, align 4, !tbaa !5
  %54 = load i32, ptr %4, align 4, !tbaa !5
  store i32 %54, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %55 = load i32, ptr %5, align 4, !tbaa !5
  %56 = and i32 %55, -129
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %56) #3, !srcloc !17
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 1, ptr %1, align 1
  store i32 1, ptr %6, align 4
  br label %58

57:                                               ; preds = %51, %33
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 0, ptr %1, align 1
  store i32 1, ptr %6, align 4
  br label %58

58:                                               ; preds = %57, %52
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #3
  %59 = load i8, ptr %1, align 1
  ret i8 %59
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @SPINLOCK_LOCK(ptr noundef) #2

declare i32 @CP15CoreIDGet() #2

; Function Attrs: nounwind uwtable
declare hidden void @INTERRUPT_DEFAULTHANDLER() #0

declare void @XScuGic_SetCpuID(i32 noundef) #2

declare ptr @XScuGic_LookupConfig(i16 noundef zeroext) #2

declare i32 @XScuGic_CfgInitialize(ptr noundef, ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @SPINLOCK_UNLOCK(ptr noundef) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !6, i64 4}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}
!16 = !{i64 2147866361}
!17 = !{i64 2147866089}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }

@INTERRUPT_VECTORTABLE = external dso_local local_unnamed_addr global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicConfigPtr = external hidden local_unnamed_addr global [2 x ptr], align 16
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @INTERRUPT_STARTUP() local_unnamed_addr #0 {
  tail call void @SPINLOCK_LOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  %1 = tail call i32 @CP15CoreIDGet() #2
  %2 = zext i32 %1 to i64
  %3 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %2
  br label %4

4:                                                ; preds = %4, %0
  %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next.4, %4 ]
  %5 = load ptr, ptr %3, align 8, !tbaa !5
  %6 = getelementptr inbounds ptr, ptr %5, i64 %indvars.iv
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %6, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = getelementptr inbounds ptr, ptr %7, i64 %indvars.iv
  %9 = getelementptr inbounds i8, ptr %8, i64 8
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %9, align 8, !tbaa !5
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = getelementptr inbounds ptr, ptr %10, i64 %indvars.iv
  %12 = getelementptr inbounds i8, ptr %11, i64 16
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %12, align 8, !tbaa !5
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds ptr, ptr %13, i64 %indvars.iv
  %15 = getelementptr inbounds i8, ptr %14, i64 24
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %15, align 8, !tbaa !5
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds ptr, ptr %16, i64 %indvars.iv
  %18 = getelementptr inbounds i8, ptr %17, i64 32
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %18, align 8, !tbaa !5
  %indvars.iv.next.4 = add nuw nsw i64 %indvars.iv, 5
  %exitcond.not.4 = icmp eq i64 %indvars.iv.next.4, 95
  br i1 %exitcond.not.4, label %19, label %4, !llvm.loop !9

19:                                               ; preds = %4
  tail call void @XScuGic_SetCpuID(i32 noundef %1) #2
  %20 = tail call ptr @XScuGic_LookupConfig(i16 noundef zeroext 0) #2
  %21 = getelementptr inbounds [2 x ptr], ptr @XScuGicConfigPtr, i64 0, i64 %2
  store ptr %20, ptr %21, align 8, !tbaa !5
  %22 = icmp eq ptr %20, null
  br i1 %22, label %31, label %23

23:                                               ; preds = %19
  %24 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %2
  %25 = getelementptr inbounds i8, ptr %20, i64 4
  %26 = load i32, ptr %25, align 4, !tbaa !11
  %27 = tail call i32 @XScuGic_CfgInitialize(ptr noundef nonnull %24, ptr noundef nonnull %20, i32 noundef %26) #2
  %.not = icmp eq i32 %27, 0
  br i1 %.not, label %28, label %31

28:                                               ; preds = %23
  %29 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !15
  %30 = and i32 %29, -129
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %30) #2, !srcloc !16
  br label %31

31:                                               ; preds = %19, %23, %28
  %.0 = phi i8 [ 1, %28 ], [ 0, %23 ], [ 0, %19 ]
  tail call void @SPINLOCK_UNLOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  ret i8 %.0
}

declare void @SPINLOCK_LOCK(ptr noundef) local_unnamed_addr #1

declare i32 @CP15CoreIDGet() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @INTERRUPT_DEFAULTHANDLER() #0

declare void @XScuGic_SetCpuID(i32 noundef) local_unnamed_addr #1

declare ptr @XScuGic_LookupConfig(i16 noundef zeroext) local_unnamed_addr #1

declare i32 @XScuGic_CfgInitialize(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #1

declare void @SPINLOCK_UNLOCK(ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !14, i64 4}
!12 = !{!"", !13, i64 0, !14, i64 4, !14, i64 8, !7, i64 16}
!13 = !{!"short", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{i64 2147866361}
!16 = !{i64 2147866089}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass