; LLVM IR from MakeContributions/DSA :: algorithms/CPlusPlus/Dynamic-Programming (matrix-chain-multiplication)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull align 8 dereferenceable(24) %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  %13 = load i32, ptr %7, align 4, !tbaa !9
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = icmp sge i32 %13, %14
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 0, ptr %5, align 4
  br label %93

17:                                               ; preds = %4
  %18 = load ptr, ptr %9, align 8, !tbaa !5
  %19 = load i32, ptr %7, align 4, !tbaa !9
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %20) #3
  %22 = load i32, ptr %8, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #3
  %25 = load i32, ptr %24, align 4, !tbaa !9
  %26 = icmp ne i32 %25, -1
  br i1 %26, label %27, label %36

27:                                               ; preds = %17
  %28 = load ptr, ptr %9, align 8, !tbaa !5
  %29 = load i32, ptr %7, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30) #3
  %32 = load i32, ptr %8, align 4, !tbaa !9
  %33 = sext i32 %32 to i64
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %33) #3
  %35 = load i32, ptr %34, align 4, !tbaa !9
  store i32 %35, ptr %5, align 4
  br label %93

36:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 2147483647, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %37 = load i32, ptr %7, align 4, !tbaa !9
  store i32 %37, ptr %11, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %81, %36
  %39 = load i32, ptr %11, align 4, !tbaa !9
  %40 = load i32, ptr %8, align 4, !tbaa !9
  %41 = icmp slt i32 %39, %40
  br i1 %41, label %43, label %42

42:                                               ; preds = %38
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %84

43:                                               ; preds = %38
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = load i32, ptr %11, align 4, !tbaa !9
  %47 = load ptr, ptr %9, align 8, !tbaa !5
  %48 = call noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %44, i32 noundef %45, i32 noundef %46, ptr noundef nonnull align 8 dereferenceable(24) %47)
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = load i32, ptr %11, align 4, !tbaa !9
  %51 = add nsw i32 %50, 1
  %52 = load i32, ptr %8, align 4, !tbaa !9
  %53 = load ptr, ptr %9, align 8, !tbaa !5
  %54 = call noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %49, i32 noundef %51, i32 noundef %52, ptr noundef nonnull align 8 dereferenceable(24) %53)
  %55 = add nsw i32 %48, %54
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = load i32, ptr %7, align 4, !tbaa !9
  %58 = sub nsw i32 %57, 1
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %56, i64 noundef %59) #3
  %61 = load i32, ptr %60, align 4, !tbaa !9
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = load i32, ptr %11, align 4, !tbaa !9
  %64 = sext i32 %63 to i64
  %65 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %64) #3
  %66 = load i32, ptr %65, align 4, !tbaa !9
  %67 = mul nsw i32 %61, %66
  %68 = load ptr, ptr %6, align 8, !tbaa !5
  %69 = load i32, ptr %8, align 4, !tbaa !9
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %70) #3
  %72 = load i32, ptr %71, align 4, !tbaa !9
  %73 = mul nsw i32 %67, %72
  %74 = add nsw i32 %55, %73
  store i32 %74, ptr %12, align 4, !tbaa !9
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = load i32, ptr %10, align 4, !tbaa !9
  %77 = icmp slt i32 %75, %76
  br i1 %77, label %78, label %80

78:                                               ; preds = %43
  %79 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %79, ptr %10, align 4, !tbaa !9
  br label %80

80:                                               ; preds = %78, %43
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %81

81:                                               ; preds = %80
  %82 = load i32, ptr %11, align 4, !tbaa !9
  %83 = add nsw i32 %82, 1
  store i32 %83, ptr %11, align 4, !tbaa !9
  br label %38, !llvm.loop !11

84:                                               ; preds = %42
  %85 = load i32, ptr %10, align 4, !tbaa !9
  %86 = load ptr, ptr %9, align 8, !tbaa !5
  %87 = load i32, ptr %7, align 4, !tbaa !9
  %88 = sext i32 %87 to i64
  %89 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %86, i64 noundef %88) #3
  %90 = load i32, ptr %8, align 4, !tbaa !9
  %91 = sext i32 %90 to i64
  %92 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %89, i64 noundef %91) #3
  store i32 %85, ptr %92, align 4, !tbaa !9
  store i32 %85, ptr %5, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %93

93:                                               ; preds = %84, %27, %16
  %94 = load i32, ptr %5, align 4
  ret i32 %94
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull align 8 dereferenceable(24) %3) local_unnamed_addr #0 {
  %.not = icmp slt i32 %1, %2
  br i1 %.not, label %5, label %34

5:                                                ; preds = %4
  %6 = sext i32 %1 to i64
  %7 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %6) #2
  %8 = sext i32 %2 to i64
  %9 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %8) #2
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %.not38 = icmp eq i32 %10, -1
  br i1 %.not38, label %.lr.ph, label %13

.lr.ph:                                           ; preds = %5
  %11 = add nsw i32 %1, -1
  %12 = sext i32 %11 to i64
  br label %19

13:                                               ; preds = %5
  %14 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %6) #2
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %8) #2
  %16 = load i32, ptr %15, align 4, !tbaa !5
  br label %34

._crit_edge:                                      ; preds = %19
  %17 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %6) #2
  %18 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %8) #2
  store i32 %spec.select, ptr %18, align 4, !tbaa !5
  br label %34

19:                                               ; preds = %.lr.ph, %19
  %indvars.iv = phi i64 [ %6, %.lr.ph ], [ %indvars.iv.next, %19 ]
  %.03439 = phi i32 [ 2147483647, %.lr.ph ], [ %spec.select, %19 ]
  %20 = trunc nsw i64 %indvars.iv to i32
  %21 = tail call noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %20, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %22 = trunc i64 %indvars.iv.next to i32
  %23 = tail call noundef i32 @_Z16matrixChainMultiRSt6vectorIiSaIiEEiiRS_IS1_SaIS1_EE(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %22, i32 noundef %2, ptr noundef nonnull align 8 dereferenceable(24) %3)
  %24 = add nsw i32 %23, %21
  %25 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %12) #2
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %27 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %indvars.iv) #2
  %28 = load i32, ptr %27, align 4, !tbaa !5
  %29 = mul nsw i32 %28, %26
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %8) #2
  %31 = load i32, ptr %30, align 4, !tbaa !5
  %32 = mul nsw i32 %29, %31
  %33 = add nsw i32 %24, %32
  %spec.select = tail call i32 @llvm.smin.i32(i32 %33, i32 %.03439)
  %exitcond.not = icmp eq i32 %22, %2
  br i1 %exitcond.not, label %._crit_edge, label %19, !llvm.loop !9

34:                                               ; preds = %4, %._crit_edge, %13
  %.0 = phi i32 [ %16, %13 ], [ %spec.select, %._crit_edge ], [ 0, %4 ]
  ret i32 %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smin.i32(i32, i32) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass