; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/qspips_v3 (LqspiRead)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XQspiPs = type { %struct.XQspiPs_Config, i32, ptr, ptr, i32, i32, i32, ptr, ptr, i32 }
%struct.XQspiPs_Config = type { i16, i32, i32, i8 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @XQspiPs_LqspiRead(ptr noundef %0, ptr noundef %1, i32 noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 0, ptr %10, align 4, !tbaa !9
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %15

14:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %16

15:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1068)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %66

16:                                               ; preds = %14
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %20

19:                                               ; preds = %16
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %21

20:                                               ; preds = %16
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1069)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %66

21:                                               ; preds = %19
  %22 = load i32, ptr %9, align 4, !tbaa !9
  %23 = icmp ugt i32 %22, 0
  br i1 %23, label %24, label %25

24:                                               ; preds = %21
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %26

25:                                               ; preds = %21
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1070)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %66

26:                                               ; preds = %24
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.XQspiPs, ptr %27, i32 0, i32 1
  %29 = load i32, ptr %28, align 8, !tbaa !11
  %30 = icmp eq i32 %29, 286331153
  br i1 %30, label %31, label %32

31:                                               ; preds = %26
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %33

32:                                               ; preds = %26
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1071)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %66

33:                                               ; preds = %31
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.XQspiPs, ptr %34, i32 0, i32 0
  %36 = getelementptr inbounds %struct.XQspiPs_Config, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !15
  %38 = add i32 %37, 20
  %39 = zext i32 %38 to i64
  call void @Xil_Out32(i64 noundef %39, i32 noundef 1)
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.XQspiPs, ptr %40, i32 0, i32 0
  %42 = getelementptr inbounds %struct.XQspiPs_Config, ptr %41, i32 0, i32 1
  %43 = load i32, ptr %42, align 4, !tbaa !15
  %44 = add i32 %43, 160
  %45 = zext i32 %44 to i64
  %46 = call i32 @Xil_In32(i64 noundef %45)
  %47 = and i32 %46, -2147483648
  %48 = icmp ne i32 %47, 0
  br i1 %48, label %49, label %57

49:                                               ; preds = %33
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = load i32, ptr %8, align 4, !tbaa !9
  %52 = add i32 -67108864, %51
  %53 = zext i32 %52 to i64
  %54 = inttoptr i64 %53 to ptr
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = zext i32 %55 to i64
  call void @llvm.memcpy.p0.p0.i64(ptr align 1 %50, ptr align 1 %54, i64 %56, i1 false)
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %58

57:                                               ; preds = %33
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %57, %49
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.XQspiPs, ptr %59, i32 0, i32 0
  %61 = getelementptr inbounds %struct.XQspiPs_Config, ptr %60, i32 0, i32 1
  %62 = load i32, ptr %61, align 4, !tbaa !15
  %63 = add i32 %62, 20
  %64 = zext i32 %63 to i64
  call void @Xil_Out32(i64 noundef %64, i32 noundef 0)
  %65 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %65, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %66

66:                                               ; preds = %58, %32, %25, %20, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  %67 = load i32, ptr %5, align 4
  ret i32 %67
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !13, i64 0, !10, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !10, i64 48, !6, i64 56, !6, i64 64, !10, i64 72}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !7, i64 12}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XQspiPs_LqspiRead(ptr noundef readonly %0, ptr noundef writeonly %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not15 = icmp eq ptr %1, null
  br i1 %.not15, label %8, label %7

6:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1068) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

7:                                                ; preds = %5
  %.not16 = icmp eq i32 %3, 0
  br i1 %.not16, label %13, label %9

8:                                                ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1069) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

9:                                                ; preds = %7
  %10 = getelementptr inbounds i8, ptr %0, i64 16
  %11 = load i32, ptr %10, align 8, !tbaa !9
  %12 = icmp eq i32 %11, 286331153
  br i1 %12, label %14, label %23

13:                                               ; preds = %7
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1070) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

14:                                               ; preds = %9
  %15 = getelementptr inbounds i8, ptr %0, i64 4
  %16 = load i32, ptr %15, align 4, !tbaa !14
  %17 = add i32 %16, 20
  %18 = zext i32 %17 to i64
  tail call void @Xil_Out32(i64 noundef %18, i32 noundef 1)
  %19 = load i32, ptr %15, align 4, !tbaa !14
  %20 = add i32 %19, 160
  %21 = zext i32 %20 to i64
  %22 = tail call i32 @Xil_In32(i64 noundef %21)
  %.not17 = icmp sgt i32 %22, -1
  br i1 %.not17, label %29, label %24

23:                                               ; preds = %9
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1071) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %33

24:                                               ; preds = %14
  %25 = add i32 %2, -67108864
  %26 = zext i32 %25 to i64
  %27 = inttoptr i64 %26 to ptr
  %28 = zext i32 %3 to i64
  tail call void @llvm.memcpy.p0.p0.i64(ptr nonnull align 1 %1, ptr align 1 %27, i64 %28, i1 false)
  br label %29

29:                                               ; preds = %14, %24
  %.0 = phi i32 [ 0, %24 ], [ 1, %14 ]
  %30 = load i32, ptr %15, align 4, !tbaa !14
  %31 = add i32 %30, 20
  %32 = zext i32 %31 to i64
  tail call void @Xil_Out32(i64 noundef %32, i32 noundef 0)
  br label %33

33:                                               ; preds = %29, %23, %13, %8, %6
  %.011 = phi i32 [ %.0, %29 ], [ 0, %23 ], [ 0, %13 ], [ 0, %8 ], [ 0, %6 ]
  ret i32 %.011
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 16}
!10 = !{!"", !11, i64 0, !6, i64 16, !13, i64 24, !13, i64 32, !6, i64 40, !6, i64 44, !6, i64 48, !13, i64 56, !13, i64 64, !6, i64 72}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !7, i64 12}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass