; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (ExtCsd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Set_Mmc_ExtCsd(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %7 = load ptr, ptr %3, align 8, !tbaa !5
  %8 = load i32, ptr %4, align 4, !tbaa !9
  %9 = call i32 @XSdPs_CmdTransfer(ptr noundef %7, i32 noundef 1536, i32 noundef %8, i32 noundef 0)
  store i32 %9, ptr %5, align 4, !tbaa !9
  %10 = load i32, ptr %5, align 4, !tbaa !9
  %11 = sext i32 %10 to i64
  %12 = icmp ne i64 %11, 0
  br i1 %12, label %13, label %14

13:                                               ; preds = %2
  store i32 1, ptr %5, align 4, !tbaa !9
  br label %40

14:                                               ; preds = %2
  br label %15

15:                                               ; preds = %31, %14
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.XSdPs, ptr %16, i32 0, i32 0
  %18 = getelementptr inbounds %struct.XSdPs_Config, ptr %17, i32 0, i32 1
  %19 = load i32, ptr %18, align 4, !tbaa !11
  %20 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %19, i8 noundef zeroext 48)
  %21 = zext i16 %20 to i32
  store i32 %21, ptr %6, align 4, !tbaa !9
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = and i32 %22, 32768
  %24 = icmp ne i32 %23, 0
  br i1 %24, label %25, label %30

25:                                               ; preds = %15
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XSdPs, ptr %26, i32 0, i32 0
  %28 = getelementptr inbounds %struct.XSdPs_Config, ptr %27, i32 0, i32 1
  %29 = load i32, ptr %28, align 4, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %29, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  store i32 1, ptr %5, align 4, !tbaa !9
  br label %40

30:                                               ; preds = %15
  br label %31

31:                                               ; preds = %30
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = and i32 %32, 2
  %34 = icmp eq i32 %33, 0
  br i1 %34, label %15, label %35, !llvm.loop !16

35:                                               ; preds = %31
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.XSdPs, ptr %36, i32 0, i32 0
  %38 = getelementptr inbounds %struct.XSdPs_Config, ptr %37, i32 0, i32 1
  %39 = load i32, ptr %38, align 4, !tbaa !11
  call void @XSdPs_WriteReg16(i32 noundef %39, i8 noundef zeroext 48, i16 noundef zeroext 2)
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %40

40:                                               ; preds = %35, %25, %13
  %41 = load i32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret i32 %41
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !15, i64 512}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Set_Mmc_ExtCsd(ptr noundef %0, i32 noundef %1) local_unnamed_addr #2 {
  %3 = tail call i32 @XSdPs_CmdTransfer(ptr noundef %0, i32 noundef 1536, i32 noundef %1, i32 noundef 0) #3
  %.not = icmp eq i32 %3, 0
  br i1 %.not, label %.preheader, label %15

.preheader:                                       ; preds = %2
  %4 = getelementptr inbounds i8, ptr %0, i64 4
  br label %5

5:                                                ; preds = %.preheader, %10
  %6 = load i32, ptr %4, align 4, !tbaa !5
  %7 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %6, i8 noundef zeroext 48)
  %.not8 = icmp sgt i16 %7, -1
  br i1 %.not8, label %10, label %8

8:                                                ; preds = %5
  %9 = load i32, ptr %4, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %9, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %15

10:                                               ; preds = %5
  %11 = and i16 %7, 2
  %12 = icmp eq i16 %11, 0
  br i1 %12, label %5, label %13, !llvm.loop !14

13:                                               ; preds = %10
  %14 = load i32, ptr %4, align 4, !tbaa !5
  tail call void @XSdPs_WriteReg16(i32 noundef %14, i8 noundef zeroext 48, i16 noundef zeroext 2)
  br label %15

15:                                               ; preds = %2, %13, %8
  %.0 = phi i32 [ 1, %8 ], [ 0, %13 ], [ 1, %2 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 4}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !12, i64 112, !9, i64 128, !13, i64 512}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"any pointer", !9, i64 0}
!13 = !{!"long", !9, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopSimplifyPass,SROAPass,SimplifyCFGPass,TailCallElimPass