; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (SetPriorityTriggerType)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_SetPriorityTriggerType(ptr noundef %0, i32 noundef %1, i8 noundef zeroext %2, i8 noundef zeroext %3) #3 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i8 %2, ptr %7, align 1, !tbaa !11
  store i8 %3, ptr %8, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  %12 = load i8, ptr %7, align 1, !tbaa !11
  store i8 %12, ptr %10, align 1, !tbaa !11
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = icmp ne ptr %13, null
  br i1 %14, label %15, label %16

15:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 717)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %11, align 4
  br label %124

17:                                               ; preds = %15
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XScuGic, ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 8, !tbaa !12
  %21 = icmp eq i32 %20, 286331153
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %24

23:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 718)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %11, align 4
  br label %124

24:                                               ; preds = %22
  %25 = load i32, ptr %6, align 4, !tbaa !9
  %26 = icmp ult i32 %25, 95
  br i1 %26, label %27, label %28

27:                                               ; preds = %24
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %29

28:                                               ; preds = %24
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 719)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %11, align 4
  br label %124

29:                                               ; preds = %27
  %30 = load i8, ptr %8, align 1, !tbaa !11
  %31 = zext i8 %30 to i32
  %32 = icmp sle i32 %31, 3
  br i1 %32, label %33, label %34

33:                                               ; preds = %29
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %35

34:                                               ; preds = %29
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 720)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %11, align 4
  br label %124

35:                                               ; preds = %33
  %36 = load i8, ptr %10, align 1, !tbaa !11
  %37 = zext i8 %36 to i32
  %38 = icmp sle i32 %37, 248
  br i1 %38, label %39, label %40

39:                                               ; preds = %35
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %41

40:                                               ; preds = %35
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 721)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %11, align 4
  br label %124

41:                                               ; preds = %39
  %42 = load ptr, ptr %5, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.XScuGic, ptr %42, i32 0, i32 0
  %44 = load ptr, ptr %43, align 8, !tbaa !14
  %45 = getelementptr inbounds %struct.XScuGic_Config, ptr %44, i32 0, i32 2
  %46 = load i32, ptr %45, align 8, !tbaa !15
  %47 = load i32, ptr %6, align 4, !tbaa !9
  %48 = udiv i32 %47, 4
  %49 = mul i32 %48, 4
  %50 = add i32 1024, %49
  %51 = add i32 %46, %50
  %52 = zext i32 %51 to i64
  %53 = call i32 @Xil_In32(i64 noundef %52)
  store i32 %53, ptr %9, align 4, !tbaa !9
  %54 = load i8, ptr %10, align 1, !tbaa !11
  %55 = zext i8 %54 to i32
  %56 = and i32 %55, 248
  %57 = trunc i32 %56 to i8
  store i8 %57, ptr %10, align 1, !tbaa !11
  %58 = load i32, ptr %6, align 4, !tbaa !9
  %59 = urem i32 %58, 4
  %60 = mul i32 %59, 8
  %61 = shl i32 255, %60
  %62 = xor i32 %61, -1
  %63 = load i32, ptr %9, align 4, !tbaa !9
  %64 = and i32 %63, %62
  store i32 %64, ptr %9, align 4, !tbaa !9
  %65 = load i8, ptr %10, align 1, !tbaa !11
  %66 = zext i8 %65 to i32
  %67 = load i32, ptr %6, align 4, !tbaa !9
  %68 = urem i32 %67, 4
  %69 = mul i32 %68, 8
  %70 = shl i32 %66, %69
  %71 = load i32, ptr %9, align 4, !tbaa !9
  %72 = or i32 %71, %70
  store i32 %72, ptr %9, align 4, !tbaa !9
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.XScuGic, ptr %73, i32 0, i32 0
  %75 = load ptr, ptr %74, align 8, !tbaa !14
  %76 = getelementptr inbounds %struct.XScuGic_Config, ptr %75, i32 0, i32 2
  %77 = load i32, ptr %76, align 8, !tbaa !15
  %78 = load i32, ptr %6, align 4, !tbaa !9
  %79 = udiv i32 %78, 4
  %80 = mul i32 %79, 4
  %81 = add i32 1024, %80
  %82 = add i32 %77, %81
  %83 = zext i32 %82 to i64
  %84 = load i32, ptr %9, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %83, i32 noundef %84)
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.XScuGic, ptr %85, i32 0, i32 0
  %87 = load ptr, ptr %86, align 8, !tbaa !14
  %88 = getelementptr inbounds %struct.XScuGic_Config, ptr %87, i32 0, i32 2
  %89 = load i32, ptr %88, align 8, !tbaa !15
  %90 = load i32, ptr %6, align 4, !tbaa !9
  %91 = udiv i32 %90, 16
  %92 = mul i32 %91, 4
  %93 = add i32 3072, %92
  %94 = add i32 %89, %93
  %95 = zext i32 %94 to i64
  %96 = call i32 @Xil_In32(i64 noundef %95)
  store i32 %96, ptr %9, align 4, !tbaa !9
  %97 = load i32, ptr %6, align 4, !tbaa !9
  %98 = urem i32 %97, 16
  %99 = mul i32 %98, 2
  %100 = shl i32 3, %99
  %101 = xor i32 %100, -1
  %102 = load i32, ptr %9, align 4, !tbaa !9
  %103 = and i32 %102, %101
  store i32 %103, ptr %9, align 4, !tbaa !9
  %104 = load i8, ptr %8, align 1, !tbaa !11
  %105 = zext i8 %104 to i32
  %106 = load i32, ptr %6, align 4, !tbaa !9
  %107 = urem i32 %106, 16
  %108 = mul i32 %107, 2
  %109 = shl i32 %105, %108
  %110 = load i32, ptr %9, align 4, !tbaa !9
  %111 = or i32 %110, %109
  store i32 %111, ptr %9, align 4, !tbaa !9
  %112 = load ptr, ptr %5, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.XScuGic, ptr %112, i32 0, i32 0
  %114 = load ptr, ptr %113, align 8, !tbaa !14
  %115 = getelementptr inbounds %struct.XScuGic_Config, ptr %114, i32 0, i32 2
  %116 = load i32, ptr %115, align 8, !tbaa !15
  %117 = load i32, ptr %6, align 4, !tbaa !9
  %118 = udiv i32 %117, 16
  %119 = mul i32 %118, 4
  %120 = add i32 3072, %119
  %121 = add i32 %116, %120
  %122 = zext i32 %121 to i64
  %123 = load i32, ptr %9, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %122, i32 noundef %123)
  store i32 0, ptr %11, align 4
  br label %124

124:                                              ; preds = %41, %40, %34, %28, %23, %16
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %125 = load i32, ptr %11, align 4
  switch i32 %125, label %127 [
    i32 0, label %126
    i32 1, label %126
  ]

126:                                              ; preds = %124, %124
  ret void

127:                                              ; preds = %124
  unreachable
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 8}
!13 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!14 = !{!13, !6, i64 0}
!15 = !{!16, !10, i64 8}
!16 = !{!"", !17, i64 0, !10, i64 4, !10, i64 8, !7, i64 16}
!17 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_SetPriorityTriggerType(ptr noundef readonly %0, i32 noundef %1, i8 noundef zeroext %2, i8 noundef zeroext %3) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load i32, ptr %6, align 8, !tbaa !9
  %8 = icmp eq i32 %7, 286331153
  br i1 %8, label %10, label %12

9:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 717) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %65

10:                                               ; preds = %5
  %11 = icmp ult i32 %1, 95
  br i1 %11, label %13, label %16

12:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 718) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %65

13:                                               ; preds = %10
  %14 = zext i8 %3 to i32
  %15 = icmp ult i8 %3, 4
  br i1 %15, label %17, label %19

16:                                               ; preds = %10
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 719) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %65

17:                                               ; preds = %13
  %18 = icmp ult i8 %2, -7
  br i1 %18, label %20, label %64

19:                                               ; preds = %13
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 720) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %65

20:                                               ; preds = %17
  %21 = load ptr, ptr %0, align 8, !tbaa !12
  %22 = getelementptr inbounds i8, ptr %21, i64 8
  %23 = load i32, ptr %22, align 8, !tbaa !13
  %24 = and i32 %1, 124
  %25 = or disjoint i32 %24, 1024
  %26 = add i32 %23, %25
  %27 = zext i32 %26 to i64
  %28 = tail call i32 @Xil_In32(i64 noundef %27)
  %29 = and i8 %2, -8
  %30 = shl nuw nsw i32 %1, 3
  %31 = and i32 %30, 24
  %32 = shl nuw i32 255, %31
  %33 = xor i32 %32, -1
  %34 = and i32 %28, %33
  %35 = zext i8 %29 to i32
  %36 = shl nuw i32 %35, %31
  %37 = or i32 %34, %36
  %38 = load ptr, ptr %0, align 8, !tbaa !12
  %39 = getelementptr inbounds i8, ptr %38, i64 8
  %40 = load i32, ptr %39, align 8, !tbaa !13
  %41 = add i32 %40, %25
  %42 = zext i32 %41 to i64
  tail call void @Xil_Out32(i64 noundef %42, i32 noundef %37)
  %43 = load ptr, ptr %0, align 8, !tbaa !12
  %44 = getelementptr inbounds i8, ptr %43, i64 8
  %45 = load i32, ptr %44, align 8, !tbaa !13
  %46 = lshr i32 %1, 2
  %47 = and i32 %46, 28
  %48 = or disjoint i32 %47, 3072
  %49 = add i32 %45, %48
  %50 = zext i32 %49 to i64
  %51 = tail call i32 @Xil_In32(i64 noundef %50)
  %52 = shl nuw nsw i32 %1, 1
  %53 = and i32 %52, 30
  %54 = shl nuw i32 3, %53
  %55 = xor i32 %54, -1
  %56 = and i32 %51, %55
  %57 = shl nuw i32 %14, %53
  %58 = or i32 %56, %57
  %59 = load ptr, ptr %0, align 8, !tbaa !12
  %60 = getelementptr inbounds i8, ptr %59, i64 8
  %61 = load i32, ptr %60, align 8, !tbaa !13
  %62 = add i32 %61, %48
  %63 = zext i32 %62 to i64
  tail call void @Xil_Out32(i64 noundef %63, i32 noundef %58)
  br label %65

64:                                               ; preds = %17
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 721) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %65

65:                                               ; preds = %20, %64, %19, %16, %12, %9
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass