; LLVM IR from thekyria/elabtsaot2 :: emulator_hw/hardware_model (emulatorhw)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.elabtsaot::EmulatorHw" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<elabtsaot::Slice, std::allocator<elabtsaot::Slice>>::_Vector_impl" }
%"struct.std::_Vector_base<elabtsaot::Slice, std::allocator<elabtsaot::Slice>>::_Vector_impl" = type { %"struct.std::_Vector_base<elabtsaot::Slice, std::allocator<elabtsaot::Slice>>::_Vector_impl_data" }
%"struct.std::_Vector_base<elabtsaot::Slice, std::allocator<elabtsaot::Slice>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.elabtsaot::Slice" = type <{ %"class.elabtsaot::SliceAnalog", %"class.elabtsaot::SliceDigital", i32, [4 x i8] }>
%"class.elabtsaot::SliceAnalog" = type { double, double, %"class.elabtsaot::DAC", %"class.elabtsaot::DAC", %"class.std::vector.0" }
%"class.elabtsaot::DAC" = type <{ double, double, i32, i32, i32, [4 x i8], double, double, double, double, i32, [4 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<elabtsaot::Atom>, std::allocator<std::vector<elabtsaot::Atom>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<elabtsaot::Atom>, std::allocator<std::vector<elabtsaot::Atom>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<elabtsaot::Atom>, std::allocator<std::vector<elabtsaot::Atom>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<elabtsaot::Atom>, std::allocator<std::vector<elabtsaot::Atom>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.elabtsaot::SliceDigital" = type { %"class.elabtsaot::GPFPQPipeline", %"class.elabtsaot::GPFSlackPipeline", %"class.elabtsaot::TDGeneratorPipeline", %"class.elabtsaot::TDConstZLoadPipeline", %"class.elabtsaot::TDConstILoadPipeline", %"class.elabtsaot::TDConstPLoadPipeline", [4 x [6 x i32]], [4 x [6 x double]], [4 x [6 x double]] }
%"class.elabtsaot::GPFPQPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.15", %"class.std::vector.15" }
%"class.elabtsaot::Pipeline" = type { ptr, %"class.std::vector.5", i64, i64, i64, i64, %"class.std::vector.10" }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<std::complex<double>, std::allocator<std::complex<double>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::complex<double>, std::allocator<std::complex<double>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::complex<double>, std::allocator<std::complex<double>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::complex<double>, std::allocator<std::complex<double>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.elabtsaot::GPFSlackPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.15" }
%"class.elabtsaot::TDGeneratorPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.20", %"class.std::vector.15", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20", %"class.std::vector.20" }
%"class.std::vector.20" = type { %"struct.std::_Vector_base.21" }
%"struct.std::_Vector_base.21" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.elabtsaot::TDConstZLoadPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.15", %"class.std::vector.15" }
%"class.elabtsaot::TDConstILoadPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.15" }
%"class.elabtsaot::TDConstPLoadPipeline" = type { %"class.elabtsaot::Pipeline", %"class.std::vector.15", %"class.std::vector.15" }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN9elabtsaot5SliceESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(1676) ptr @_ZNSt6vectorIN9elabtsaot5SliceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

declare noundef i32 @_ZN9elabtsaot3DAC7set_outEdPdb(ptr noundef nonnull align 8 dereferenceable(68), double noundef, ptr noundef, i1 noundef zeroext) #2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN9elabtsaot10EmulatorHw24set_imag_voltage_ref_outEd(ptr noundef nonnull align 8 dereferenceable(24) %0, double noundef %1) #3 align 2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca double, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store double %1, ptr %5, align 8, !tbaa !9
  %9 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !11
  br label %10

10:                                               ; preds = %37, %2
  %11 = load i64, ptr %6, align 8, !tbaa !11
  %12 = getelementptr inbounds %"class.elabtsaot::EmulatorHw", ptr %9, i32 0, i32 0
  %13 = call noundef i64 @_ZNKSt6vectorIN9elabtsaot5SliceESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %14 = icmp ne i64 %11, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %10
  store i32 2, ptr %7, align 4
  br label %40

16:                                               ; preds = %10
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %17 = getelementptr inbounds %"class.elabtsaot::EmulatorHw", ptr %9, i32 0, i32 0
  %18 = load i64, ptr %6, align 8, !tbaa !11
  %19 = call noundef nonnull align 8 dereferenceable(1676) ptr @_ZNSt6vectorIN9elabtsaot5SliceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %18) #4
  %20 = getelementptr inbounds %"struct.elabtsaot::Slice", ptr %19, i32 0, i32 0
  %21 = getelementptr inbounds %"class.elabtsaot::SliceAnalog", ptr %20, i32 0, i32 3
  %22 = load double, ptr %5, align 8, !tbaa !9
  %23 = call noundef i32 @_ZN9elabtsaot3DAC7set_outEdPdb(ptr noundef nonnull align 8 dereferenceable(68) %21, double noundef %22, ptr noundef null, i1 noundef zeroext true)
  store i32 %23, ptr %8, align 4, !tbaa !13
  %24 = load i32, ptr %8, align 4, !tbaa !13
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %33

26:                                               ; preds = %16
  %27 = load i64, ptr %6, align 8, !tbaa !11
  %28 = load i32, ptr %8, align 4, !tbaa !13
  %29 = shl i32 %28, 3
  %30 = sext i32 %29 to i64
  %31 = or i64 %27, %30
  %32 = trunc i64 %31 to i32
  store i32 %32, ptr %3, align 4
  store i32 1, ptr %7, align 4
  br label %34

33:                                               ; preds = %16
  store i32 0, ptr %7, align 4
  br label %34

34:                                               ; preds = %33, %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %35 = load i32, ptr %7, align 4
  switch i32 %35, label %40 [
    i32 0, label %36
  ]

36:                                               ; preds = %34
  br label %37

37:                                               ; preds = %36
  %38 = load i64, ptr %6, align 8, !tbaa !11
  %39 = add i64 %38, 1
  store i64 %39, ptr %6, align 8, !tbaa !11
  br label %10, !llvm.loop !15

40:                                               ; preds = %34, %15
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  %41 = load i32, ptr %7, align 4
  switch i32 %41, label %45 [
    i32 2, label %42
    i32 1, label %43
  ]

42:                                               ; preds = %40
  store i32 0, ptr %3, align 4
  br label %43

43:                                               ; preds = %42, %40
  %44 = load i32, ptr %3, align 4
  ret i32 %44

45:                                               ; preds = %40
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN9elabtsaot5SliceESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(1676) ptr @_ZNSt6vectorIN9elabtsaot5SliceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

declare noundef i32 @_ZN9elabtsaot3DAC7set_outEdPdb(ptr noundef nonnull align 8 dereferenceable(68), double noundef, ptr noundef, i1 noundef zeroext) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN9elabtsaot10EmulatorHw24set_imag_voltage_ref_outEd(ptr noundef nonnull align 8 dereferenceable(24) %0, double noundef %1) local_unnamed_addr #2 align 2 {
  %3 = tail call noundef i64 @_ZNKSt6vectorIN9elabtsaot5SliceESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %.not19 = icmp eq i64 %3, 0
  br i1 %.not19, label %.split.loop.exit, label %.lr.ph

.lr.ph:                                           ; preds = %2, %7
  %.01220 = phi i64 [ %8, %7 ], [ 0, %2 ]
  %4 = tail call noundef nonnull align 8 dereferenceable(1676) ptr @_ZNSt6vectorIN9elabtsaot5SliceESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.01220) #3
  %5 = getelementptr inbounds i8, ptr %4, i64 88
  %6 = tail call noundef i32 @_ZN9elabtsaot3DAC7set_outEdPdb(ptr noundef nonnull align 8 dereferenceable(68) %5, double noundef %1, ptr noundef null, i1 noundef zeroext true)
  %.not14 = icmp eq i32 %6, 0
  br i1 %.not14, label %7, label %.split.loop.exit15

7:                                                ; preds = %.lr.ph
  %8 = add i64 %.01220, 1
  %9 = tail call noundef i64 @_ZNKSt6vectorIN9elabtsaot5SliceESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %.not = icmp eq i64 %8, %9
  br i1 %.not, label %.split.loop.exit, label %.lr.ph, !llvm.loop !5

.split.loop.exit15:                               ; preds = %.lr.ph
  %10 = shl i32 %6, 3
  %11 = trunc i64 %.01220 to i32
  %12 = or i32 %10, %11
  br label %.split.loop.exit

.split.loop.exit:                                 ; preds = %7, %2, %.split.loop.exit15
  %spec.select = phi i32 [ %12, %.split.loop.exit15 ], [ 0, %2 ], [ 0, %7 ]
  ret i32 %spec.select
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass