; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/devcfg_v3 (SelfTest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XDcfg = type { %struct.XDcfg_Config, i32, i32, ptr, ptr }
%struct.XDcfg_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XDcfg_SelfTest(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %12

11:                                               ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 89)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %33

12:                                               ; preds = %10
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.XDcfg, ptr %13, i32 0, i32 1
  %15 = load i32, ptr %14, align 8, !tbaa !11
  %16 = icmp eq i32 %15, 286331153
  br i1 %16, label %17, label %18

17:                                               ; preds = %12
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %12
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 90)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %33

19:                                               ; preds = %17
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = call i32 @XDcfg_GetControlRegister(ptr noundef %20)
  store i32 %21, ptr %4, align 4, !tbaa !9
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  call void @XDcfg_SetControlRegister(ptr noundef %22, i32 noundef 16)
  %23 = load ptr, ptr %3, align 8, !tbaa !5
  %24 = call i32 @XDcfg_GetControlRegister(ptr noundef %23)
  store i32 %24, ptr %5, align 4, !tbaa !9
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = and i32 %25, 16
  %27 = icmp ne i32 %26, 16
  br i1 %27, label %28, label %29

28:                                               ; preds = %19
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %28, %19
  %30 = load ptr, ptr %3, align 8, !tbaa !5
  %31 = load i32, ptr %4, align 4, !tbaa !9
  call void @XDcfg_SetControlRegister(ptr noundef %30, i32 noundef %31)
  %32 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %32, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %33

33:                                               ; preds = %29, %18, %11
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %34 = load i32, ptr %2, align 4
  ret i32 %34
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

declare i32 @XDcfg_GetControlRegister(ptr noundef) #2

declare void @XDcfg_SetControlRegister(ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8, !10, i64 12, !6, i64 16, !6, i64 24}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XDcfg_SelfTest(ptr noundef %0) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %2

2:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !9
  %5 = icmp eq i32 %4, 286331153
  br i1 %5, label %7, label %11

6:                                                ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 89) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %12

7:                                                ; preds = %2
  %8 = tail call i32 @XDcfg_GetControlRegister(ptr noundef nonnull %0) #2
  tail call void @XDcfg_SetControlRegister(ptr noundef nonnull %0, i32 noundef 16) #2
  %9 = tail call i32 @XDcfg_GetControlRegister(ptr noundef nonnull %0) #2
  %10 = lshr i32 %9, 4
  %.lobit = and i32 %10, 1
  %spec.select = xor i32 %.lobit, 1
  tail call void @XDcfg_SetControlRegister(ptr noundef nonnull %0, i32 noundef %8) #2
  br label %12

11:                                               ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 90) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %7, %11, %6
  %.09 = phi i32 [ %spec.select, %7 ], [ 0, %11 ], [ 0, %6 ]
  ret i32 %.09
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

declare i32 @XDcfg_GetControlRegister(ptr noundef) local_unnamed_addr #1

declare void @XDcfg_SetControlRegister(ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12, !13, i64 16, !13, i64 24}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}


; Effective O3 passes: DSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass