; LLVM IR from lesialin/ImageSignalProcessing_C :: src/isp_eeh.ll (Z7isp_eehPhPa)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.isp_config_t = type <{ i32, i32, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.blc_cfg_t, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.awb_gain_t, [12 x float], %"class.std::__cxx11::basic_string", float, [12 x float], %struct.nlm_cfg_t, i8, %struct.bnf_cfg_t, [15 x i16], %struct.eeh_cfg_t, %struct.fcs_cfg_t, %struct.hsc_cfg_t, %struct.bcc_cfg_t, [4 x i8] }>
%struct.blc_cfg_t = type { i16, i16, i16, i16, float, float }
%struct.awb_gain_t = type { float, float, float, float }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%struct.nlm_cfg_t = type { i8, i8, i8 }
%struct.bnf_cfg_t = type { [25 x i16], [4 x i16], [3 x i16] }
%struct.eeh_cfg_t = type { i16, i16, i16, i16, i16, i16 }
%struct.fcs_cfg_t = type { i8, i8 }
%struct.hsc_cfg_t = type { i8, float }
%struct.bcc_cfg_t = type { i8, float }

@g_isp_config = external global %struct.isp_config_t, align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef signext i8 @_Z5emluts(i16 noundef signext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z15create_edge_mapPhPa(ptr noundef, ptr noundef) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z7isp_eehPhPa(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i16, align 2
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 3, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 5, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %15 = load i32, ptr %5, align 4, !tbaa !9
  %16 = ashr i32 %15, 1
  store i32 %16, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %17 = load i32, ptr %6, align 4, !tbaa !9
  %18 = ashr i32 %17, 1
  store i32 %18, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #2
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_Z15create_edge_mapPhPa(ptr noundef %19, ptr noundef %20)
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %109, %2
  %22 = load i32, ptr %12, align 4, !tbaa !9
  %23 = load i32, ptr getelementptr inbounds (%struct.isp_config_t, ptr @g_isp_config, i32 0, i32 1), align 4, !tbaa !11
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = sub i32 %23, %24
  %26 = icmp ult i32 %22, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %21
  store i32 2, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %112

28:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %105, %28
  %30 = load i32, ptr %14, align 4, !tbaa !9
  %31 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = sub i32 %31, %32
  %34 = icmp ult i32 %30, %33
  br i1 %34, label %36, label %35

35:                                               ; preds = %29
  store i32 5, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  br label %108

36:                                               ; preds = %29
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = load i32, ptr %12, align 4, !tbaa !9
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = add nsw i32 %38, %39
  %41 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %42 = mul i32 %40, %41
  %43 = load i32, ptr %14, align 4, !tbaa !9
  %44 = load i32, ptr %8, align 4, !tbaa !9
  %45 = add nsw i32 %43, %44
  %46 = add i32 %42, %45
  %47 = zext i32 %46 to i64
  %48 = getelementptr inbounds i8, ptr %37, i64 %47
  %49 = load i8, ptr %48, align 1, !tbaa !27
  store i8 %49, ptr %9, align 1, !tbaa !27
  %50 = load i8, ptr %9, align 1, !tbaa !27
  %51 = sext i8 %50 to i16
  %52 = call noundef signext i8 @_Z5emluts(i16 noundef signext %51)
  store i8 %52, ptr %10, align 1, !tbaa !27
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = load i32, ptr %12, align 4, !tbaa !9
  %55 = load i32, ptr %7, align 4, !tbaa !9
  %56 = add nsw i32 %54, %55
  %57 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %58 = mul i32 %56, %57
  %59 = load i32, ptr %14, align 4, !tbaa !9
  %60 = load i32, ptr %8, align 4, !tbaa !9
  %61 = add nsw i32 %59, %60
  %62 = add i32 %58, %61
  %63 = zext i32 %62 to i64
  %64 = getelementptr inbounds i8, ptr %53, i64 %63
  %65 = load i8, ptr %64, align 1, !tbaa !27
  %66 = zext i8 %65 to i32
  %67 = load i8, ptr %10, align 1, !tbaa !27
  %68 = sext i8 %67 to i32
  %69 = add nsw i32 %66, %68
  %70 = trunc i32 %69 to i16
  store i16 %70, ptr %11, align 2, !tbaa !28
  %71 = load i16, ptr %11, align 2, !tbaa !28
  %72 = sext i16 %71 to i32
  %73 = icmp sgt i32 %72, 255
  br i1 %73, label %74, label %75

74:                                               ; preds = %36
  br label %78

75:                                               ; preds = %36
  %76 = load i16, ptr %11, align 2, !tbaa !28
  %77 = sext i16 %76 to i32
  br label %78

78:                                               ; preds = %75, %74
  %79 = phi i32 [ 255, %74 ], [ %77, %75 ]
  %80 = trunc i32 %79 to i16
  store i16 %80, ptr %11, align 2, !tbaa !28
  %81 = load i16, ptr %11, align 2, !tbaa !28
  %82 = sext i16 %81 to i32
  %83 = icmp slt i32 %82, 0
  br i1 %83, label %84, label %85

84:                                               ; preds = %78
  br label %88

85:                                               ; preds = %78
  %86 = load i16, ptr %11, align 2, !tbaa !28
  %87 = sext i16 %86 to i32
  br label %88

88:                                               ; preds = %85, %84
  %89 = phi i32 [ 0, %84 ], [ %87, %85 ]
  %90 = trunc i32 %89 to i16
  store i16 %90, ptr %11, align 2, !tbaa !28
  %91 = load i16, ptr %11, align 2, !tbaa !28
  %92 = trunc i16 %91 to i8
  %93 = load ptr, ptr %3, align 8, !tbaa !5
  %94 = load i32, ptr %12, align 4, !tbaa !9
  %95 = load i32, ptr %7, align 4, !tbaa !9
  %96 = add nsw i32 %94, %95
  %97 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %98 = mul i32 %96, %97
  %99 = load i32, ptr %14, align 4, !tbaa !9
  %100 = load i32, ptr %8, align 4, !tbaa !9
  %101 = add nsw i32 %99, %100
  %102 = add i32 %98, %101
  %103 = zext i32 %102 to i64
  %104 = getelementptr inbounds i8, ptr %93, i64 %103
  store i8 %92, ptr %104, align 1, !tbaa !27
  br label %105

105:                                              ; preds = %88
  %106 = load i32, ptr %14, align 4, !tbaa !9
  %107 = add nsw i32 %106, 1
  store i32 %107, ptr %14, align 4, !tbaa !9
  br label %29, !llvm.loop !29

108:                                              ; preds = %35
  br label %109

109:                                              ; preds = %108
  %110 = load i32, ptr %12, align 4, !tbaa !9
  %111 = add nsw i32 %110, 1
  store i32 %111, ptr %12, align 4, !tbaa !9
  br label %21, !llvm.loop !31

112:                                              ; preds = %27
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"_ZTS12isp_config_t", !10, i64 0, !10, i64 4, !13, i64 8, !14, i64 16, !17, i64 48, !13, i64 64, !14, i64 72, !19, i64 104, !7, i64 120, !14, i64 168, !18, i64 200, !7, i64 204, !20, i64 252, !21, i64 256, !7, i64 320, !22, i64 350, !23, i64 362, !24, i64 364, !25, i64 372}
!13 = !{!"short", !7, i64 0}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !15, i64 0, !16, i64 8, !7, i64 16}
!15 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!"_ZTS9blc_cfg_t", !13, i64 0, !13, i64 2, !13, i64 4, !13, i64 6, !18, i64 8, !18, i64 12}
!18 = !{!"float", !7, i64 0}
!19 = !{!"_ZTS10awb_gain_t", !18, i64 0, !18, i64 4, !18, i64 8, !18, i64 12}
!20 = !{!"_ZTS9nlm_cfg_t", !7, i64 0, !7, i64 1, !7, i64 2}
!21 = !{!"_ZTS9bnf_cfg_t", !7, i64 0, !7, i64 50, !7, i64 58}
!22 = !{!"_ZTS9eeh_cfg_t", !13, i64 0, !13, i64 2, !13, i64 4, !13, i64 6, !13, i64 8, !13, i64 10}
!23 = !{!"_ZTS9fcs_cfg_t", !7, i64 0, !7, i64 1}
!24 = !{!"_ZTS9hsc_cfg_t", !7, i64 0, !18, i64 4}
!25 = !{!"_ZTS9bcc_cfg_t", !7, i64 0, !18, i64 4}
!26 = !{!12, !10, i64 0}
!27 = !{!7, !7, i64 0}
!28 = !{!13, !13, i64 0}
!29 = distinct !{!29, !30}
!30 = !{!"llvm.loop.mustprogress"}
!31 = distinct !{!31, !30}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.isp_config_t = type <{ i32, i32, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.blc_cfg_t, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.awb_gain_t, [12 x float], %"class.std::__cxx11::basic_string", float, [12 x float], %struct.nlm_cfg_t, i8, %struct.bnf_cfg_t, [15 x i16], %struct.eeh_cfg_t, %struct.fcs_cfg_t, %struct.hsc_cfg_t, %struct.bcc_cfg_t, [4 x i8] }>
%struct.blc_cfg_t = type { i16, i16, i16, i16, float, float }
%struct.awb_gain_t = type { float, float, float, float }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%struct.nlm_cfg_t = type { i8, i8, i8 }
%struct.bnf_cfg_t = type { [25 x i16], [4 x i16], [3 x i16] }
%struct.eeh_cfg_t = type { i16, i16, i16, i16, i16, i16 }
%struct.fcs_cfg_t = type { i8, i8 }
%struct.hsc_cfg_t = type { i8, float }
%struct.bcc_cfg_t = type { i8, float }

@g_isp_config = external local_unnamed_addr global %struct.isp_config_t, align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef signext i8 @_Z5emluts(i16 noundef signext) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z15create_edge_mapPhPa(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z7isp_eehPhPa(ptr noundef %0, ptr noundef %1) local_unnamed_addr #0 {
  tail call void @_Z15create_edge_mapPhPa(ptr noundef %0, ptr noundef %1)
  %3 = load i32, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 4), align 4, !tbaa !5
  %.not = icmp eq i32 %3, 3
  br i1 %.not, label %._crit_edge34, label %.preheader.preheader

.preheader.preheader:                             ; preds = %2
  %.pre = load i32, ptr @g_isp_config, align 8, !tbaa !24
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %._crit_edge
  %4 = phi i32 [ %6, %._crit_edge ], [ %3, %.preheader.preheader ]
  %5 = phi i32 [ %7, %._crit_edge ], [ %.pre, %.preheader.preheader ]
  %.03133 = phi i32 [ %.pre37, %._crit_edge ], [ 0, %.preheader.preheader ]
  %.not35 = icmp eq i32 %5, 5
  %.pre37 = add nuw nsw i32 %.03133, 1
  br i1 %.not35, label %._crit_edge, label %.lr.ph

._crit_edge34:                                    ; preds = %._crit_edge, %2
  ret void

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %.pre36 = load i32, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 4), align 4, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %.preheader, %._crit_edge.loopexit
  %6 = phi i32 [ %.pre36, %._crit_edge.loopexit ], [ %4, %.preheader ]
  %7 = phi i32 [ %32, %._crit_edge.loopexit ], [ 5, %.preheader ]
  %8 = add i32 %6, -3
  %9 = icmp ult i32 %.pre37, %8
  br i1 %9, label %.preheader, label %._crit_edge34, !llvm.loop !25

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %10 = phi i32 [ %32, %.lr.ph ], [ %5, %.preheader ]
  %.032 = phi i32 [ %31, %.lr.ph ], [ 0, %.preheader ]
  %11 = mul i32 %10, %.pre37
  %12 = add nuw nsw i32 %.032, 2
  %13 = add i32 %11, %12
  %14 = zext i32 %13 to i64
  %15 = getelementptr inbounds i8, ptr %1, i64 %14
  %16 = load i8, ptr %15, align 1, !tbaa !27
  %17 = sext i8 %16 to i16
  %18 = tail call noundef signext i8 @_Z5emluts(i16 noundef signext %17)
  %19 = load i32, ptr @g_isp_config, align 8, !tbaa !24
  %20 = mul i32 %19, %.pre37
  %21 = add i32 %20, %12
  %22 = zext i32 %21 to i64
  %23 = getelementptr inbounds i8, ptr %0, i64 %22
  %24 = load i8, ptr %23, align 1, !tbaa !27
  %25 = zext i8 %24 to i32
  %26 = sext i8 %18 to i32
  %27 = add nsw i32 %25, %26
  %28 = tail call i32 @llvm.smin.i32(i32 %27, i32 255)
  %29 = tail call i32 @llvm.smax.i32(i32 %28, i32 0)
  %30 = trunc nuw i32 %29 to i8
  store i8 %30, ptr %23, align 1, !tbaa !27
  %31 = add nuw nsw i32 %.032, 1
  %32 = load i32, ptr @g_isp_config, align 8, !tbaa !24
  %33 = add i32 %32, -5
  %34 = icmp ult i32 %31, %33
  br i1 %34, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !28
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smin.i32(i32, i32) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smax.i32(i32, i32) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTS12isp_config_t", !7, i64 0, !7, i64 4, !10, i64 8, !11, i64 16, !15, i64 48, !10, i64 64, !11, i64 72, !17, i64 104, !8, i64 120, !11, i64 168, !16, i64 200, !8, i64 204, !18, i64 252, !19, i64 256, !8, i64 320, !20, i64 350, !21, i64 362, !22, i64 364, !23, i64 372}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"short", !8, i64 0}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !14, i64 8, !8, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!13 = !{!"any pointer", !8, i64 0}
!14 = !{!"long", !8, i64 0}
!15 = !{!"_ZTS9blc_cfg_t", !10, i64 0, !10, i64 2, !10, i64 4, !10, i64 6, !16, i64 8, !16, i64 12}
!16 = !{!"float", !8, i64 0}
!17 = !{!"_ZTS10awb_gain_t", !16, i64 0, !16, i64 4, !16, i64 8, !16, i64 12}
!18 = !{!"_ZTS9nlm_cfg_t", !8, i64 0, !8, i64 1, !8, i64 2}
!19 = !{!"_ZTS9bnf_cfg_t", !8, i64 0, !8, i64 50, !8, i64 58}
!20 = !{!"_ZTS9eeh_cfg_t", !10, i64 0, !10, i64 2, !10, i64 4, !10, i64 6, !10, i64 8, !10, i64 10}
!21 = !{!"_ZTS9fcs_cfg_t", !8, i64 0, !8, i64 1}
!22 = !{!"_ZTS9hsc_cfg_t", !8, i64 0, !16, i64 4}
!23 = !{!"_ZTS9bcc_cfg_t", !8, i64 0, !16, i64 4}
!24 = !{!6, !7, i64 0}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.mustprogress"}
!27 = !{!8, !8, i64 0}
!28 = distinct !{!28, !26}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass