; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (SetSingleChParams)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }
%struct.XAdcPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XAdcPs_SetSingleChParams(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i8 %1, ptr %8, align 1, !tbaa !9
  store i32 %2, ptr %9, align 4, !tbaa !10
  store i32 %3, ptr %10, align 4, !tbaa !10
  store i32 %4, ptr %11, align 4, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %14 = load ptr, ptr %7, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %18

17:                                               ; preds = %5
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 586)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

18:                                               ; preds = %16
  %19 = load ptr, ptr %7, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.XAdcPs, ptr %19, i32 0, i32 1
  %21 = load i32, ptr %20, align 4, !tbaa !12
  %22 = icmp eq i32 %21, 286331153
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %25

24:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 587)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

25:                                               ; preds = %23
  %26 = load i8, ptr %8, align 1, !tbaa !9
  %27 = zext i8 %26 to i32
  %28 = icmp sle i32 %27, 6
  br i1 %28, label %41, label %29

29:                                               ; preds = %25
  %30 = load i8, ptr %8, align 1, !tbaa !9
  %31 = zext i8 %30 to i32
  %32 = icmp eq i32 %31, 8
  br i1 %32, label %41, label %33

33:                                               ; preds = %29
  %34 = load i8, ptr %8, align 1, !tbaa !9
  %35 = zext i8 %34 to i32
  %36 = icmp sge i32 %35, 13
  br i1 %36, label %37, label %42

37:                                               ; preds = %33
  %38 = load i8, ptr %8, align 1, !tbaa !9
  %39 = zext i8 %38 to i32
  %40 = icmp sle i32 %39, 31
  br i1 %40, label %41, label %42

41:                                               ; preds = %37, %29, %25
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %43

42:                                               ; preds = %37, %33
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 591)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

43:                                               ; preds = %41
  %44 = load i32, ptr %9, align 4, !tbaa !10
  %45 = icmp eq i32 %44, 1
  br i1 %45, label %49, label %46

46:                                               ; preds = %43
  %47 = load i32, ptr %9, align 4, !tbaa !10
  %48 = icmp eq i32 %47, 0
  br i1 %48, label %49, label %50

49:                                               ; preds = %46, %43
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %51

50:                                               ; preds = %46
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 593)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

51:                                               ; preds = %49
  %52 = load i32, ptr %10, align 4, !tbaa !10
  %53 = icmp eq i32 %52, 1
  br i1 %53, label %57, label %54

54:                                               ; preds = %51
  %55 = load i32, ptr %10, align 4, !tbaa !10
  %56 = icmp eq i32 %55, 0
  br i1 %56, label %57, label %58

57:                                               ; preds = %54, %51
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %59

58:                                               ; preds = %54
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 594)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

59:                                               ; preds = %57
  %60 = load i32, ptr %11, align 4, !tbaa !10
  %61 = icmp eq i32 %60, 1
  br i1 %61, label %65, label %62

62:                                               ; preds = %59
  %63 = load i32, ptr %11, align 4, !tbaa !10
  %64 = icmp eq i32 %63, 0
  br i1 %64, label %65, label %66

65:                                               ; preds = %62, %59
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %67

66:                                               ; preds = %62
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 596)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

67:                                               ; preds = %65
  %68 = load ptr, ptr %7, align 8, !tbaa !5
  %69 = call zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef %68)
  %70 = zext i8 %69 to i32
  %71 = icmp ne i32 %70, 3
  br i1 %71, label %72, label %73

72:                                               ; preds = %67
  store i32 1, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

73:                                               ; preds = %67
  %74 = load ptr, ptr %7, align 8, !tbaa !5
  %75 = call i32 @XAdcPs_ReadInternalReg(ptr noundef %74, i32 noundef 64)
  %76 = and i32 %75, 12288
  store i32 %76, ptr %12, align 4, !tbaa !10
  %77 = load i32, ptr %9, align 4, !tbaa !10
  %78 = icmp eq i32 %77, 1
  br i1 %78, label %79, label %96

79:                                               ; preds = %73
  %80 = load i8, ptr %8, align 1, !tbaa !9
  %81 = zext i8 %80 to i32
  %82 = icmp sge i32 %81, 16
  br i1 %82, label %83, label %87

83:                                               ; preds = %79
  %84 = load i8, ptr %8, align 1, !tbaa !9
  %85 = zext i8 %84 to i32
  %86 = icmp sle i32 %85, 31
  br i1 %86, label %91, label %87

87:                                               ; preds = %83, %79
  %88 = load i8, ptr %8, align 1, !tbaa !9
  %89 = zext i8 %88 to i32
  %90 = icmp eq i32 %89, 3
  br i1 %90, label %91, label %94

91:                                               ; preds = %87, %83
  %92 = load i32, ptr %12, align 4, !tbaa !10
  %93 = or i32 %92, 256
  store i32 %93, ptr %12, align 4, !tbaa !10
  br label %95

94:                                               ; preds = %87
  store i32 1, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

95:                                               ; preds = %91
  br label %96

96:                                               ; preds = %95, %73
  %97 = load i32, ptr %11, align 4, !tbaa !10
  %98 = icmp eq i32 %97, 1
  br i1 %98, label %99, label %116

99:                                               ; preds = %96
  %100 = load i8, ptr %8, align 1, !tbaa !9
  %101 = zext i8 %100 to i32
  %102 = icmp sge i32 %101, 16
  br i1 %102, label %103, label %107

103:                                              ; preds = %99
  %104 = load i8, ptr %8, align 1, !tbaa !9
  %105 = zext i8 %104 to i32
  %106 = icmp sle i32 %105, 31
  br i1 %106, label %111, label %107

107:                                              ; preds = %103, %99
  %108 = load i8, ptr %8, align 1, !tbaa !9
  %109 = zext i8 %108 to i32
  %110 = icmp eq i32 %109, 3
  br i1 %110, label %111, label %114

111:                                              ; preds = %107, %103
  %112 = load i32, ptr %12, align 4, !tbaa !10
  %113 = or i32 %112, 1024
  store i32 %113, ptr %12, align 4, !tbaa !10
  br label %115

114:                                              ; preds = %107
  store i32 1, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

115:                                              ; preds = %111
  br label %116

116:                                              ; preds = %115, %96
  %117 = load i32, ptr %10, align 4, !tbaa !10
  %118 = icmp eq i32 %117, 1
  br i1 %118, label %119, label %122

119:                                              ; preds = %116
  %120 = load i32, ptr %12, align 4, !tbaa !10
  %121 = or i32 %120, 512
  store i32 %121, ptr %12, align 4, !tbaa !10
  br label %122

122:                                              ; preds = %119, %116
  %123 = load i8, ptr %8, align 1, !tbaa !9
  %124 = zext i8 %123 to i32
  %125 = and i32 %124, 31
  %126 = load i32, ptr %12, align 4, !tbaa !10
  %127 = or i32 %126, %125
  store i32 %127, ptr %12, align 4, !tbaa !10
  %128 = load ptr, ptr %7, align 8, !tbaa !5
  %129 = load i32, ptr %12, align 4, !tbaa !10
  call void @XAdcPs_WriteInternalReg(ptr noundef %128, i32 noundef 64, i32 noundef %129)
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %130

130:                                              ; preds = %122, %114, %94, %72, %66, %58, %50, %42, %24, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  %131 = load i32, ptr %6, align 4
  ret i32 %131
}

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !14, i64 0, !11, i64 8}
!14 = !{!"", !15, i64 0, !11, i64 4}
!15 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XAdcPs_SetSingleChParams(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = load i32, ptr %7, align 4, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %12

10:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 586) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

11:                                               ; preds = %6
  switch i8 %1, label %13 [
    i8 8, label %15
    i8 6, label %15
    i8 5, label %15
    i8 4, label %15
    i8 3, label %15
    i8 2, label %15
    i8 1, label %15
    i8 0, label %15
  ]

12:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 587) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

13:                                               ; preds = %11
  %14 = add i8 %1, -13
  %or.cond5 = icmp ult i8 %14, 19
  br i1 %or.cond5, label %15, label %17

15:                                               ; preds = %11, %11, %11, %11, %11, %11, %11, %11, %13
  %16 = icmp eq i32 %2, 1
  %or.cond7 = icmp ult i32 %2, 2
  br i1 %or.cond7, label %18, label %20

17:                                               ; preds = %13
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 591) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

18:                                               ; preds = %15
  %19 = icmp eq i32 %3, 1
  %or.cond9 = icmp ult i32 %3, 2
  br i1 %or.cond9, label %21, label %23

20:                                               ; preds = %15
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 593) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

21:                                               ; preds = %18
  %22 = icmp eq i32 %4, 1
  %or.cond11 = icmp ult i32 %4, 2
  br i1 %or.cond11, label %24, label %26

23:                                               ; preds = %18
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 594) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

24:                                               ; preds = %21
  %25 = tail call zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef nonnull %0)
  %.not56 = icmp eq i8 %25, 3
  br i1 %.not56, label %27, label %45

26:                                               ; preds = %21
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 596) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

27:                                               ; preds = %24
  %28 = tail call i32 @XAdcPs_ReadInternalReg(ptr noundef nonnull %0, i32 noundef 64)
  %29 = and i32 %28, 12288
  br i1 %16, label %30, label %35

30:                                               ; preds = %27
  %31 = and i8 %1, -16
  %or.cond14 = icmp eq i8 %31, 16
  %32 = icmp eq i8 %1, 3
  %or.cond17 = or i1 %32, %or.cond14
  br i1 %or.cond17, label %33, label %45

33:                                               ; preds = %30
  %34 = or disjoint i32 %29, 256
  br label %35

35:                                               ; preds = %33, %27
  %.0 = phi i32 [ %34, %33 ], [ %29, %27 ]
  br i1 %22, label %36, label %41

36:                                               ; preds = %35
  %37 = and i8 %1, -16
  %or.cond20 = icmp eq i8 %37, 16
  %38 = icmp eq i8 %1, 3
  %or.cond23 = or i1 %38, %or.cond20
  br i1 %or.cond23, label %39, label %45

39:                                               ; preds = %36
  %40 = or i32 %.0, 1024
  br label %41

41:                                               ; preds = %39, %35
  %.1 = phi i32 [ %40, %39 ], [ %.0, %35 ]
  %42 = or i32 %.1, 512
  %spec.select = select i1 %19, i32 %42, i32 %.1
  %43 = zext nneg i8 %1 to i32
  %44 = or i32 %spec.select, %43
  tail call void @XAdcPs_WriteInternalReg(ptr noundef nonnull %0, i32 noundef 64, i32 noundef %44)
  br label %45

45:                                               ; preds = %36, %30, %24, %41, %26, %23, %20, %17, %12, %10
  %.053 = phi i32 [ 0, %41 ], [ 0, %26 ], [ 0, %23 ], [ 0, %20 ], [ 0, %17 ], [ 0, %12 ], [ 0, %10 ], [ 1, %24 ], [ 1, %30 ], [ 1, %36 ]
  ret i32 %.053
}

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef) local_unnamed_addr #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass