; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (BusWidth)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1
@TransferMode = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Get_BusWidth(ptr noundef %0, ptr noundef %1) #3 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %15

14:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %16

15:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 179)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %105

16:                                               ; preds = %14
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.XSdPs, ptr %17, i32 0, i32 1
  %19 = load i32, ptr %18, align 4, !tbaa !11
  %20 = icmp eq i32 %19, 286331153
  br i1 %20, label %21, label %22

21:                                               ; preds = %16
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %23

22:                                               ; preds = %16
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 180)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %105

23:                                               ; preds = %21
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %24

24:                                               ; preds = %32, %23
  %25 = load i32, ptr %10, align 4, !tbaa !9
  %26 = icmp slt i32 %25, 8
  br i1 %26, label %27, label %35

27:                                               ; preds = %24
  %28 = load ptr, ptr %5, align 8, !tbaa !5
  %29 = load i32, ptr %10, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = getelementptr inbounds i8, ptr %28, i64 %30
  store i8 0, ptr %31, align 1, !tbaa !16
  br label %32

32:                                               ; preds = %27
  %33 = load i32, ptr %10, align 4, !tbaa !9
  %34 = add nsw i32 %33, 1
  store i32 %34, ptr %10, align 4, !tbaa !9
  br label %24, !llvm.loop !17

35:                                               ; preds = %24
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.XSdPs, ptr %37, i32 0, i32 12
  %39 = load i32, ptr %38, align 16, !tbaa !19
  %40 = call i32 @XSdPs_CmdTransfer(ptr noundef %36, i32 noundef 14080, i32 noundef %39, i32 noundef 0)
  store i32 %40, ptr %6, align 4, !tbaa !9
  %41 = load i32, ptr %6, align 4, !tbaa !9
  %42 = sext i32 %41 to i64
  %43 = icmp ne i64 %42, 0
  br i1 %43, label %44, label %45

44:                                               ; preds = %35
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %103

45:                                               ; preds = %35
  store i16 1, ptr %8, align 2, !tbaa !20
  store i16 8, ptr %9, align 2, !tbaa !20
  %46 = load i16, ptr %9, align 2, !tbaa !20
  %47 = zext i16 %46 to i32
  %48 = and i32 %47, 4095
  %49 = trunc i32 %48 to i16
  store i16 %49, ptr %9, align 2, !tbaa !20
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XSdPs, ptr %50, i32 0, i32 0
  %52 = getelementptr inbounds %struct.XSdPs_Config, ptr %51, i32 0, i32 1
  %53 = load i32, ptr %52, align 4, !tbaa !21
  %54 = load i16, ptr %9, align 2, !tbaa !20
  call void @XSdPs_WriteReg16(i32 noundef %53, i8 noundef zeroext 4, i16 noundef zeroext %54)
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  %56 = load i16, ptr %8, align 2, !tbaa !20
  %57 = zext i16 %56 to i32
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  call void @XSdPs_SetupADMA2DescTbl(ptr noundef %55, i32 noundef %57, ptr noundef %58)
  store i16 17, ptr @TransferMode, align 2, !tbaa !20
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.XSdPs, ptr %59, i32 0, i32 0
  %61 = getelementptr inbounds %struct.XSdPs_Config, ptr %60, i32 0, i32 8
  %62 = load i8, ptr %61, align 32, !tbaa !22
  %63 = zext i8 %62 to i32
  %64 = icmp eq i32 %63, 0
  br i1 %64, label %65, label %68

65:                                               ; preds = %45
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = ptrtoint ptr %66 to i64
  call void @Xil_DCacheInvalidateRange(i64 noundef %67, i32 noundef 8)
  br label %68

68:                                               ; preds = %65, %45
  %69 = load ptr, ptr %4, align 8, !tbaa !5
  %70 = load i16, ptr %8, align 2, !tbaa !20
  %71 = zext i16 %70 to i32
  %72 = call i32 @XSdPs_CmdTransfer(ptr noundef %69, i32 noundef 45824, i32 noundef 0, i32 noundef %71)
  store i32 %72, ptr %6, align 4, !tbaa !9
  %73 = load i32, ptr %6, align 4, !tbaa !9
  %74 = sext i32 %73 to i64
  %75 = icmp ne i64 %74, 0
  br i1 %75, label %76, label %77

76:                                               ; preds = %68
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %103

77:                                               ; preds = %68
  br label %78

78:                                               ; preds = %94, %77
  %79 = load ptr, ptr %4, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.XSdPs, ptr %79, i32 0, i32 0
  %81 = getelementptr inbounds %struct.XSdPs_Config, ptr %80, i32 0, i32 1
  %82 = load i32, ptr %81, align 4, !tbaa !21
  %83 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %82, i8 noundef zeroext 48)
  %84 = zext i16 %83 to i32
  store i32 %84, ptr %7, align 4, !tbaa !9
  %85 = load i32, ptr %7, align 4, !tbaa !9
  %86 = and i32 %85, 32768
  %87 = icmp ne i32 %86, 0
  br i1 %87, label %88, label %93

88:                                               ; preds = %78
  %89 = load ptr, ptr %4, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.XSdPs, ptr %89, i32 0, i32 0
  %91 = getelementptr inbounds %struct.XSdPs_Config, ptr %90, i32 0, i32 1
  %92 = load i32, ptr %91, align 4, !tbaa !21
  call void @XSdPs_WriteReg16(i32 noundef %92, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %103

93:                                               ; preds = %78
  br label %94

94:                                               ; preds = %93
  %95 = load i32, ptr %7, align 4, !tbaa !9
  %96 = and i32 %95, 2
  %97 = icmp eq i32 %96, 0
  br i1 %97, label %78, label %98, !llvm.loop !23

98:                                               ; preds = %94
  %99 = load ptr, ptr %4, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.XSdPs, ptr %99, i32 0, i32 0
  %101 = getelementptr inbounds %struct.XSdPs_Config, ptr %100, i32 0, i32 1
  %102 = load i32, ptr %101, align 4, !tbaa !21
  call void @XSdPs_WriteReg16(i32 noundef %102, i8 noundef zeroext 48, i16 noundef zeroext 2)
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %103

103:                                              ; preds = %98, %88, %76, %44
  %104 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %104, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %105

105:                                              ; preds = %103, %22, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %106 = load i32, ptr %3, align 4
  ret i32 %106
}

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) #1

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !15, i64 512}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!7, !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!12, !10, i64 80}
!20 = !{!14, !14, i64 0}
!21 = !{!12, !10, i64 4}
!22 = !{!12, !7, i64 32}
!23 = distinct !{!23, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1
@TransferMode = external local_unnamed_addr global i16, align 2

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Get_BusWidth(ptr noundef %0, ptr noundef %1) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 36
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %12

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 179) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %32

8:                                                ; preds = %3
  store i64 0, ptr %1, align 1
  %9 = getelementptr inbounds i8, ptr %0, i64 80
  %10 = load i32, ptr %9, align 16, !tbaa !15
  %11 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 14080, i32 noundef %10, i32 noundef 0) #3
  %.not29 = icmp eq i32 %11, 0
  br i1 %.not29, label %13, label %32

12:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 180) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %32

13:                                               ; preds = %8
  %14 = getelementptr inbounds i8, ptr %0, i64 4
  %15 = load i32, ptr %14, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %15, i8 noundef zeroext 4, i16 noundef zeroext 8)
  tail call void @XSdPs_SetupADMA2DescTbl(ptr noundef nonnull %0, i32 noundef 1, ptr noundef nonnull %1) #3
  store i16 17, ptr @TransferMode, align 2, !tbaa !17
  %16 = getelementptr inbounds i8, ptr %0, i64 32
  %17 = load i8, ptr %16, align 32, !tbaa !18
  %18 = icmp eq i8 %17, 0
  br i1 %18, label %19, label %21

19:                                               ; preds = %13
  %20 = ptrtoint ptr %1 to i64
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %20, i32 noundef 8) #3
  br label %21

21:                                               ; preds = %19, %13
  %22 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 45824, i32 noundef 0, i32 noundef 1) #3
  %.not30 = icmp eq i32 %22, 0
  br i1 %.not30, label %.preheader, label %32

.preheader:                                       ; preds = %21, %27
  %23 = load i32, ptr %14, align 4, !tbaa !16
  %24 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %23, i8 noundef zeroext 48)
  %.not31 = icmp sgt i16 %24, -1
  br i1 %.not31, label %27, label %25

25:                                               ; preds = %.preheader
  %26 = load i32, ptr %14, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %26, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %32

27:                                               ; preds = %.preheader
  %28 = and i16 %24, 2
  %29 = icmp eq i16 %28, 0
  br i1 %29, label %.preheader, label %30, !llvm.loop !19

30:                                               ; preds = %27
  %31 = load i32, ptr %14, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %31, i8 noundef zeroext 48, i16 noundef zeroext 2)
  br label %32

32:                                               ; preds = %25, %30, %8, %21, %12, %7
  %.026 = phi i32 [ 0, %12 ], [ 0, %7 ], [ 1, %25 ], [ 0, %30 ], [ 1, %8 ], [ 1, %21 ]
  ret i32 %.026
}

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #0

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !13, i64 112, !7, i64 128, !14, i64 512}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!10, !6, i64 80}
!16 = !{!10, !6, i64 4}
!17 = !{!12, !12, i64 0}
!18 = !{!10, !7, i64 32}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopIdiomRecognizePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass