; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (GetPriTrigTypeByDistAddr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_GetPriTrigTypeByDistAddr(i32 noundef %0, i32 noundef %1, ptr noundef %2, ptr noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load i32, ptr %6, align 4, !tbaa !5
  %12 = icmp ult i32 %11, 95
  br i1 %12, label %13, label %14

13:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %15

14:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 550)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %10, align 4
  br label %60

15:                                               ; preds = %13
  %16 = load ptr, ptr %7, align 8, !tbaa !9
  %17 = icmp ne ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %15
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

19:                                               ; preds = %15
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 551)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %10, align 4
  br label %60

20:                                               ; preds = %18
  %21 = load ptr, ptr %8, align 8, !tbaa !9
  %22 = icmp ne ptr %21, null
  br i1 %22, label %23, label %24

23:                                               ; preds = %20
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %25

24:                                               ; preds = %20
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 552)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %10, align 4
  br label %60

25:                                               ; preds = %23
  %26 = load i32, ptr %5, align 4, !tbaa !5
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = udiv i32 %27, 4
  %29 = mul i32 %28, 4
  %30 = add i32 1024, %29
  %31 = add i32 %26, %30
  %32 = zext i32 %31 to i64
  %33 = call i32 @Xil_In32(i64 noundef %32)
  store i32 %33, ptr %9, align 4, !tbaa !5
  %34 = load i32, ptr %9, align 4, !tbaa !5
  %35 = load i32, ptr %6, align 4, !tbaa !5
  %36 = urem i32 %35, 4
  %37 = mul i32 %36, 8
  %38 = lshr i32 %34, %37
  store i32 %38, ptr %9, align 4, !tbaa !5
  %39 = load i32, ptr %9, align 4, !tbaa !5
  %40 = and i32 %39, 255
  %41 = trunc i32 %40 to i8
  %42 = load ptr, ptr %7, align 8, !tbaa !9
  store i8 %41, ptr %42, align 1, !tbaa !11
  %43 = load i32, ptr %5, align 4, !tbaa !5
  %44 = load i32, ptr %6, align 4, !tbaa !5
  %45 = udiv i32 %44, 16
  %46 = mul i32 %45, 4
  %47 = add i32 3072, %46
  %48 = add i32 %43, %47
  %49 = zext i32 %48 to i64
  %50 = call i32 @Xil_In32(i64 noundef %49)
  store i32 %50, ptr %9, align 4, !tbaa !5
  %51 = load i32, ptr %9, align 4, !tbaa !5
  %52 = load i32, ptr %6, align 4, !tbaa !5
  %53 = urem i32 %52, 16
  %54 = mul i32 %53, 2
  %55 = lshr i32 %51, %54
  store i32 %55, ptr %9, align 4, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !5
  %57 = and i32 %56, 3
  %58 = trunc i32 %57 to i8
  %59 = load ptr, ptr %8, align 8, !tbaa !9
  store i8 %58, ptr %59, align 1, !tbaa !11
  store i32 0, ptr %10, align 4
  br label %60

60:                                               ; preds = %25, %24, %19, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %61 = load i32, ptr %10, align 4
  switch i32 %61, label %63 [
    i32 0, label %62
    i32 1, label %62
  ]

62:                                               ; preds = %60, %60
  ret void

63:                                               ; preds = %60
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_GetPriTrigTypeByDistAddr(i32 noundef %0, i32 noundef %1, ptr noundef writeonly %2, ptr noundef writeonly %3) local_unnamed_addr #2 {
  %5 = icmp ult i32 %1, 95
  br i1 %5, label %6, label %7

6:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not = icmp eq ptr %2, null
  br i1 %.not, label %9, label %8

7:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 550) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %32

8:                                                ; preds = %6
  %.not16 = icmp eq ptr %3, null
  br i1 %.not16, label %31, label %10

9:                                                ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 551) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %32

10:                                               ; preds = %8
  %11 = and i32 %1, 124
  %12 = add i32 %0, 1024
  %13 = add i32 %12, %11
  %14 = zext i32 %13 to i64
  %15 = tail call i32 @Xil_In32(i64 noundef %14)
  %16 = shl nuw nsw i32 %1, 3
  %17 = and i32 %16, 24
  %18 = lshr i32 %15, %17
  %19 = trunc i32 %18 to i8
  store i8 %19, ptr %2, align 1, !tbaa !9
  %20 = lshr i32 %1, 2
  %21 = and i32 %20, 28
  %22 = add i32 %0, 3072
  %23 = add i32 %22, %21
  %24 = zext i32 %23 to i64
  %25 = tail call i32 @Xil_In32(i64 noundef %24)
  %26 = shl nuw nsw i32 %1, 1
  %27 = and i32 %26, 30
  %28 = lshr i32 %25, %27
  %29 = trunc i32 %28 to i8
  %30 = and i8 %29, 3
  store i8 %30, ptr %3, align 1, !tbaa !9
  br label %32

31:                                               ; preds = %8
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 552) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %32

32:                                               ; preds = %10, %31, %9, %7
  ret void
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass