; LLVM IR from CactiLab/Sherloc-Cortex-M-CFVD :: Sherloc_runtime/evaluation/src/qrduino (qrtest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@strinbuf = external global ptr, align 8
@__const.verify_benchmark_qrduino.expected = external hidden unnamed_addr constant [22 x i32], align 16

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @verify_benchmark_qrduino(i32 noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca [22 x i32], align 16
  %6 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 88, ptr %5) #3
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %5, ptr align 16 @__const.verify_benchmark_qrduino.expected, i64 88, i1 false)
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %7

7:                                                ; preds = %24, %1
  %8 = load i32, ptr %4, align 4, !tbaa !5
  %9 = icmp slt i32 %8, 22
  br i1 %9, label %10, label %27

10:                                               ; preds = %7
  %11 = load ptr, ptr @strinbuf, align 8, !tbaa !9
  %12 = load i32, ptr %4, align 4, !tbaa !5
  %13 = sext i32 %12 to i64
  %14 = getelementptr inbounds i8, ptr %11, i64 %13
  %15 = load i8, ptr %14, align 1, !tbaa !11
  %16 = zext i8 %15 to i32
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = sext i32 %17 to i64
  %19 = getelementptr inbounds [22 x i32], ptr %5, i64 0, i64 %18
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = icmp ne i32 %16, %20
  br i1 %21, label %22, label %23

22:                                               ; preds = %10
  store i32 0, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %28

23:                                               ; preds = %10
  br label %24

24:                                               ; preds = %23
  %25 = load i32, ptr %4, align 4, !tbaa !5
  %26 = add nsw i32 %25, 1
  store i32 %26, ptr %4, align 4, !tbaa !5
  br label %7, !llvm.loop !12

27:                                               ; preds = %7
  store i32 1, ptr %2, align 4
  store i32 1, ptr %6, align 4
  br label %28

28:                                               ; preds = %27, %22
  call void @llvm.lifetime.end.p0(i64 88, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %29 = load i32, ptr %2, align 4
  ret i32 %29
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@strinbuf = external local_unnamed_addr global ptr, align 8
@__const.verify_benchmark_qrduino.expected = external hidden unnamed_addr constant [22 x i32], align 16

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(read, inaccessiblemem: none) uwtable
define dso_local range(i32 0, 2) i32 @verify_benchmark_qrduino(i32 noundef %0) local_unnamed_addr #0 {
  %2 = load ptr, ptr @strinbuf, align 8, !tbaa !5
  %3 = load i8, ptr %2, align 1, !tbaa !9
  %4 = zext i8 %3 to i32
  %5 = load i32, ptr @__const.verify_benchmark_qrduino.expected, align 16, !tbaa !10
  %.not = icmp eq i32 %5, %4
  br i1 %.not, label %6, label %111

6:                                                ; preds = %1
  %7 = getelementptr inbounds i8, ptr %2, i64 1
  %8 = load i8, ptr %7, align 1, !tbaa !9
  %9 = zext i8 %8 to i32
  %10 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 4), align 4, !tbaa !10
  %.not.1 = icmp eq i32 %10, %9
  br i1 %.not.1, label %11, label %111

11:                                               ; preds = %6
  %12 = getelementptr inbounds i8, ptr %2, i64 2
  %13 = load i8, ptr %12, align 1, !tbaa !9
  %14 = zext i8 %13 to i32
  %15 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 8), align 8, !tbaa !10
  %.not.2 = icmp eq i32 %15, %14
  br i1 %.not.2, label %16, label %111

16:                                               ; preds = %11
  %17 = getelementptr inbounds i8, ptr %2, i64 3
  %18 = load i8, ptr %17, align 1, !tbaa !9
  %19 = zext i8 %18 to i32
  %20 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 12), align 4, !tbaa !10
  %.not.3 = icmp eq i32 %20, %19
  br i1 %.not.3, label %21, label %111

21:                                               ; preds = %16
  %22 = getelementptr inbounds i8, ptr %2, i64 4
  %23 = load i8, ptr %22, align 1, !tbaa !9
  %24 = zext i8 %23 to i32
  %25 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 16), align 16, !tbaa !10
  %.not.4 = icmp eq i32 %25, %24
  br i1 %.not.4, label %26, label %111

26:                                               ; preds = %21
  %27 = getelementptr inbounds i8, ptr %2, i64 5
  %28 = load i8, ptr %27, align 1, !tbaa !9
  %29 = zext i8 %28 to i32
  %30 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 20), align 4, !tbaa !10
  %.not.5 = icmp eq i32 %30, %29
  br i1 %.not.5, label %31, label %111

31:                                               ; preds = %26
  %32 = getelementptr inbounds i8, ptr %2, i64 6
  %33 = load i8, ptr %32, align 1, !tbaa !9
  %34 = zext i8 %33 to i32
  %35 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 24), align 8, !tbaa !10
  %.not.6 = icmp eq i32 %35, %34
  br i1 %.not.6, label %36, label %111

36:                                               ; preds = %31
  %37 = getelementptr inbounds i8, ptr %2, i64 7
  %38 = load i8, ptr %37, align 1, !tbaa !9
  %39 = zext i8 %38 to i32
  %40 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 28), align 4, !tbaa !10
  %.not.7 = icmp eq i32 %40, %39
  br i1 %.not.7, label %41, label %111

41:                                               ; preds = %36
  %42 = getelementptr inbounds i8, ptr %2, i64 8
  %43 = load i8, ptr %42, align 1, !tbaa !9
  %44 = zext i8 %43 to i32
  %45 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 32), align 16, !tbaa !10
  %.not.8 = icmp eq i32 %45, %44
  br i1 %.not.8, label %46, label %111

46:                                               ; preds = %41
  %47 = getelementptr inbounds i8, ptr %2, i64 9
  %48 = load i8, ptr %47, align 1, !tbaa !9
  %49 = zext i8 %48 to i32
  %50 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 36), align 4, !tbaa !10
  %.not.9 = icmp eq i32 %50, %49
  br i1 %.not.9, label %51, label %111

51:                                               ; preds = %46
  %52 = getelementptr inbounds i8, ptr %2, i64 10
  %53 = load i8, ptr %52, align 1, !tbaa !9
  %54 = zext i8 %53 to i32
  %55 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 40), align 8, !tbaa !10
  %.not.10 = icmp eq i32 %55, %54
  br i1 %.not.10, label %56, label %111

56:                                               ; preds = %51
  %57 = getelementptr inbounds i8, ptr %2, i64 11
  %58 = load i8, ptr %57, align 1, !tbaa !9
  %59 = zext i8 %58 to i32
  %60 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 44), align 4, !tbaa !10
  %.not.11 = icmp eq i32 %60, %59
  br i1 %.not.11, label %61, label %111

61:                                               ; preds = %56
  %62 = getelementptr inbounds i8, ptr %2, i64 12
  %63 = load i8, ptr %62, align 1, !tbaa !9
  %64 = zext i8 %63 to i32
  %65 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 48), align 16, !tbaa !10
  %.not.12 = icmp eq i32 %65, %64
  br i1 %.not.12, label %66, label %111

66:                                               ; preds = %61
  %67 = getelementptr inbounds i8, ptr %2, i64 13
  %68 = load i8, ptr %67, align 1, !tbaa !9
  %69 = zext i8 %68 to i32
  %70 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 52), align 4, !tbaa !10
  %.not.13 = icmp eq i32 %70, %69
  br i1 %.not.13, label %71, label %111

71:                                               ; preds = %66
  %72 = getelementptr inbounds i8, ptr %2, i64 14
  %73 = load i8, ptr %72, align 1, !tbaa !9
  %74 = zext i8 %73 to i32
  %75 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 56), align 8, !tbaa !10
  %.not.14 = icmp eq i32 %75, %74
  br i1 %.not.14, label %76, label %111

76:                                               ; preds = %71
  %77 = getelementptr inbounds i8, ptr %2, i64 15
  %78 = load i8, ptr %77, align 1, !tbaa !9
  %79 = zext i8 %78 to i32
  %80 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 60), align 4, !tbaa !10
  %.not.15 = icmp eq i32 %80, %79
  br i1 %.not.15, label %81, label %111

81:                                               ; preds = %76
  %82 = getelementptr inbounds i8, ptr %2, i64 16
  %83 = load i8, ptr %82, align 1, !tbaa !9
  %84 = zext i8 %83 to i32
  %85 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 64), align 16, !tbaa !10
  %.not.16 = icmp eq i32 %85, %84
  br i1 %.not.16, label %86, label %111

86:                                               ; preds = %81
  %87 = getelementptr inbounds i8, ptr %2, i64 17
  %88 = load i8, ptr %87, align 1, !tbaa !9
  %89 = zext i8 %88 to i32
  %90 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 68), align 4, !tbaa !10
  %.not.17 = icmp eq i32 %90, %89
  br i1 %.not.17, label %91, label %111

91:                                               ; preds = %86
  %92 = getelementptr inbounds i8, ptr %2, i64 18
  %93 = load i8, ptr %92, align 1, !tbaa !9
  %94 = zext i8 %93 to i32
  %95 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 72), align 8, !tbaa !10
  %.not.18 = icmp eq i32 %95, %94
  br i1 %.not.18, label %96, label %111

96:                                               ; preds = %91
  %97 = getelementptr inbounds i8, ptr %2, i64 19
  %98 = load i8, ptr %97, align 1, !tbaa !9
  %99 = zext i8 %98 to i32
  %100 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 76), align 4, !tbaa !10
  %.not.19 = icmp eq i32 %100, %99
  br i1 %.not.19, label %101, label %111

101:                                              ; preds = %96
  %102 = getelementptr inbounds i8, ptr %2, i64 20
  %103 = load i8, ptr %102, align 1, !tbaa !9
  %104 = zext i8 %103 to i32
  %105 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 80), align 16, !tbaa !10
  %.not.20 = icmp eq i32 %105, %104
  br i1 %.not.20, label %106, label %111

106:                                              ; preds = %101
  %107 = getelementptr inbounds i8, ptr %2, i64 21
  %108 = load i8, ptr %107, align 1, !tbaa !9
  %109 = zext i8 %108 to i32
  %110 = load i32, ptr getelementptr inbounds (i8, ptr @__const.verify_benchmark_qrduino.expected, i64 84), align 4, !tbaa !10
  %.not.21 = icmp eq i32 %110, %109
  %spec.select = zext i1 %.not.21 to i32
  br label %111

111:                                              ; preds = %106, %101, %96, %91, %86, %81, %76, %71, %66, %61, %56, %51, %46, %41, %36, %31, %26, %21, %16, %11, %6, %1
  %.05 = phi i32 [ 0, %1 ], [ 0, %6 ], [ 0, %11 ], [ 0, %16 ], [ 0, %21 ], [ 0, %26 ], [ 0, %31 ], [ 0, %36 ], [ 0, %41 ], [ 0, %46 ], [ 0, %51 ], [ 0, %56 ], [ 0, %61 ], [ 0, %66 ], [ 0, %71 ], [ 0, %76 ], [ 0, %81 ], [ 0, %86 ], [ 0, %91 ], [ 0, %96 ], [ 0, %101 ], [ %spec.select, %106 ]
  ret i32 %.05
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(read, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass