; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (L1DCacheInvalidate)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L1DCacheInvalidate() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  store i32 0, ptr %16, align 4, !tbaa !5
  %22 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  store i32 %22, ptr %16, align 4, !tbaa !5
  %23 = load i32, ptr %16, align 4, !tbaa !5
  store i32 %23, ptr %17, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  %24 = load i32, ptr %17, align 4, !tbaa !5
  store i32 %24, ptr %11, align 4, !tbaa !5
  %25 = load i32, ptr %11, align 4, !tbaa !5
  %26 = or i32 %25, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %26) #2, !srcloc !10
  store i32 ptrtoint (ptr @_stack_end to i32), ptr %13, align 4, !tbaa !5
  store i32 ptrtoint (ptr @__undef_stack to i32), ptr %12, align 4, !tbaa !5
  %27 = load i32, ptr %12, align 4, !tbaa !5
  %28 = load i32, ptr %13, align 4, !tbaa !5
  %29 = sub i32 %27, %28
  store i32 %29, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #2
  store i32 0, ptr %18, align 4, !tbaa !5
  %30 = call i32 asm sideeffect "mrc p15, 0, $0,  c1,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !11
  store i32 %30, ptr %18, align 4, !tbaa !5
  %31 = load i32, ptr %18, align 4, !tbaa !5
  store i32 %31, ptr %19, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #2
  %32 = load i32, ptr %19, align 4, !tbaa !5
  store i32 %32, ptr %15, align 4, !tbaa !5
  %33 = load i32, ptr %15, align 4, !tbaa !5
  %34 = and i32 %33, 4
  %35 = icmp ne i32 %34, 0
  br i1 %35, label %36, label %40

36:                                               ; preds = %0
  %37 = load i32, ptr %13, align 4, !tbaa !5
  %38 = zext i32 %37 to i64
  %39 = load i32, ptr %14, align 4, !tbaa !5
  call void @Xil_DCacheFlushRange(i64 noundef %38, i32 noundef %39)
  br label %40

40:                                               ; preds = %36, %0
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #2, !srcloc !12
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #2
  store i32 0, ptr %20, align 4, !tbaa !5
  %41 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !13
  store i32 %41, ptr %20, align 4, !tbaa !5
  %42 = load i32, ptr %20, align 4, !tbaa !5
  store i32 %42, ptr %21, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #2
  %43 = load i32, ptr %21, align 4, !tbaa !5
  store i32 %43, ptr %1, align 4, !tbaa !5
  %44 = load i32, ptr %1, align 4, !tbaa !5
  %45 = lshr i32 %44, 13
  %46 = and i32 %45, 511
  store i32 %46, ptr %3, align 4, !tbaa !5
  %47 = load i32, ptr %3, align 4, !tbaa !5
  %48 = add i32 %47, 1
  store i32 %48, ptr %3, align 4, !tbaa !5
  %49 = load i32, ptr %3, align 4, !tbaa !5
  %50 = mul i32 %49, 128
  store i32 %50, ptr %3, align 4, !tbaa !5
  %51 = load i32, ptr %1, align 4, !tbaa !5
  %52 = and i32 %51, 1023
  %53 = lshr i32 %52, 3
  store i32 %53, ptr %5, align 4, !tbaa !5
  %54 = load i32, ptr %5, align 4, !tbaa !5
  %55 = add i32 %54, 1
  store i32 %55, ptr %5, align 4, !tbaa !5
  %56 = load i32, ptr %1, align 4, !tbaa !5
  %57 = and i32 %56, 7
  %58 = add i32 %57, 4
  store i32 %58, ptr %4, align 4, !tbaa !5
  %59 = load i32, ptr %3, align 4, !tbaa !5
  %60 = load i32, ptr %5, align 4, !tbaa !5
  %61 = udiv i32 %59, %60
  store i32 %61, ptr %10, align 4, !tbaa !5
  %62 = load i32, ptr %4, align 4, !tbaa !5
  %63 = shl i32 1, %62
  %64 = load i32, ptr %10, align 4, !tbaa !5
  %65 = udiv i32 %64, %63
  store i32 %65, ptr %10, align 4, !tbaa !5
  store i32 0, ptr %6, align 4, !tbaa !5
  store i32 0, ptr %8, align 4, !tbaa !5
  store i32 0, ptr %7, align 4, !tbaa !5
  br label %66

66:                                               ; preds = %90, %40
  %67 = load i32, ptr %7, align 4, !tbaa !5
  %68 = load i32, ptr %5, align 4, !tbaa !5
  %69 = icmp ult i32 %67, %68
  br i1 %69, label %70, label %93

70:                                               ; preds = %66
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %71

71:                                               ; preds = %84, %70
  %72 = load i32, ptr %9, align 4, !tbaa !5
  %73 = load i32, ptr %10, align 4, !tbaa !5
  %74 = icmp ult i32 %72, %73
  br i1 %74, label %75, label %87

75:                                               ; preds = %71
  %76 = load i32, ptr %6, align 4, !tbaa !5
  %77 = load i32, ptr %8, align 4, !tbaa !5
  %78 = or i32 %76, %77
  store i32 %78, ptr %2, align 4, !tbaa !5
  %79 = load i32, ptr %2, align 4, !tbaa !5
  call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 2", "r,~{dirflag},~{fpsr},~{flags}"(i32 %79) #2, !srcloc !14
  %80 = load i32, ptr %4, align 4, !tbaa !5
  %81 = shl i32 1, %80
  %82 = load i32, ptr %8, align 4, !tbaa !5
  %83 = add i32 %82, %81
  store i32 %83, ptr %8, align 4, !tbaa !5
  br label %84

84:                                               ; preds = %75
  %85 = load i32, ptr %9, align 4, !tbaa !5
  %86 = add i32 %85, 1
  store i32 %86, ptr %9, align 4, !tbaa !5
  br label %71, !llvm.loop !15

87:                                               ; preds = %71
  store i32 0, ptr %8, align 4, !tbaa !5
  %88 = load i32, ptr %6, align 4, !tbaa !5
  %89 = add i32 %88, 1073741824
  store i32 %89, ptr %6, align 4, !tbaa !5
  br label %90

90:                                               ; preds = %87
  %91 = load i32, ptr %7, align 4, !tbaa !5
  %92 = add i32 %91, 1
  store i32 %92, ptr %7, align 4, !tbaa !5
  br label %66, !llvm.loop !17

93:                                               ; preds = %66
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !18
  %94 = load i32, ptr %11, align 4, !tbaa !5
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %94) #2, !srcloc !19
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 2147863204}
!10 = !{i64 2147863300}
!11 = !{i64 2147863415}
!12 = !{i64 2147863569}
!13 = !{i64 2147863715}
!14 = !{i64 2147863851}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}
!18 = !{i64 2147863961}
!19 = !{i64 2147864011}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L1DCacheInvalidate() local_unnamed_addr #0 {
  %1 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !5
  %2 = or i32 %1, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %2) #1, !srcloc !6
  %3 = tail call i32 asm sideeffect "mrc p15, 0, $0,  c1,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !7
  %4 = and i32 %3, 4
  %.not = icmp eq i32 %4, 0
  br i1 %.not, label %7, label %5

5:                                                ; preds = %0
  %6 = zext i32 ptrtoint (ptr @_stack_end to i32) to i64
  tail call void @Xil_DCacheFlushRange(i64 noundef %6, i32 noundef sub (i32 ptrtoint (ptr @__undef_stack to i32), i32 ptrtoint (ptr @_stack_end to i32)))
  br label %7

7:                                                ; preds = %5, %0
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #1, !srcloc !8
  %8 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  %9 = lshr i32 %8, 6
  %10 = and i32 %9, 65408
  %11 = add nuw nsw i32 %10, 128
  %12 = lshr i32 %8, 3
  %13 = and i32 %12, 127
  %14 = add nuw nsw i32 %13, 1
  %15 = and i32 %8, 7
  %16 = udiv i32 %11, %14
  %17 = shl nuw nsw i32 16, %15
  %18 = add nuw nsw i32 %15, 4
  %19 = lshr i32 %16, %18
  %.not45 = icmp eq i32 %19, 0
  br i1 %.not45, label %.split44.us, label %.preheader.us

.preheader.us:                                    ; preds = %7, %._crit_edge.us
  %.042.us = phi i32 [ %24, %._crit_edge.us ], [ 0, %7 ]
  %.03541.us = phi i32 [ %25, %._crit_edge.us ], [ 0, %7 ]
  br label %20

20:                                               ; preds = %.preheader.us, %20
  %.140.us = phi i32 [ 0, %.preheader.us ], [ %22, %20 ]
  %.03739.us = phi i32 [ 0, %.preheader.us ], [ %23, %20 ]
  %21 = or i32 %.140.us, %.042.us
  tail call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 2", "r,~{dirflag},~{fpsr},~{flags}"(i32 %21) #1, !srcloc !10
  %22 = add nuw nsw i32 %.140.us, %17
  %23 = add nuw nsw i32 %.03739.us, 1
  %exitcond.not = icmp eq i32 %23, %19
  br i1 %exitcond.not, label %._crit_edge.us, label %20, !llvm.loop !11

._crit_edge.us:                                   ; preds = %20
  %24 = add i32 %.042.us, 1073741824
  %25 = add nuw nsw i32 %.03541.us, 1
  %exitcond47.not = icmp eq i32 %.03541.us, %13
  br i1 %exitcond47.not, label %.split44.us, label %.preheader.us, !llvm.loop !13

.split44.us:                                      ; preds = %._crit_edge.us, %7
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !14
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %1) #1, !srcloc !15
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147863204}
!6 = !{i64 2147863300}
!7 = !{i64 2147863415}
!8 = !{i64 2147863569}
!9 = !{i64 2147863715}
!10 = !{i64 2147863851}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = !{i64 2147863961}
!15 = !{i64 2147864011}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass