; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (CfgInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XGpioPs_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %15

14:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 100)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %84

15:                                               ; preds = %13
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = icmp ne ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %15
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %20

19:                                               ; preds = %15
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 101)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %84

20:                                               ; preds = %18
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %24

23:                                               ; preds = %20
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %25

24:                                               ; preds = %20
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 102)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %84

25:                                               ; preds = %23
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XGpioPs, ptr %26, i32 0, i32 1
  store i32 0, ptr %27, align 8, !tbaa !11
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.XGpioPs, ptr %29, i32 0, i32 0
  %31 = getelementptr inbounds %struct.XGpioPs_Config, ptr %30, i32 0, i32 1
  store i32 %28, ptr %31, align 4, !tbaa !15
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.XGpioPs_Config, ptr %32, i32 0, i32 0
  %34 = load i16, ptr %33, align 4, !tbaa !16
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.XGpioPs, ptr %35, i32 0, i32 0
  %37 = getelementptr inbounds %struct.XGpioPs_Config, ptr %36, i32 0, i32 0
  store i16 %34, ptr %37, align 8, !tbaa !17
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XGpioPs, ptr %38, i32 0, i32 2
  store ptr @StubHandler, ptr %39, align 8, !tbaa !18
  %40 = call i32 @XGetPlatform_Info()
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.XGpioPs, ptr %41, i32 0, i32 4
  store i32 %40, ptr %42, align 8, !tbaa !19
  %43 = load ptr, ptr %5, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.XGpioPs, ptr %43, i32 0, i32 4
  %45 = load i32, ptr %44, align 8, !tbaa !19
  %46 = icmp eq i32 %45, 1
  br i1 %46, label %47, label %52

47:                                               ; preds = %25
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.XGpioPs, ptr %48, i32 0, i32 5
  store i32 174, ptr %49, align 4, !tbaa !20
  %50 = load ptr, ptr %5, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XGpioPs, ptr %50, i32 0, i32 6
  store i8 6, ptr %51, align 8, !tbaa !21
  br label %57

52:                                               ; preds = %25
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.XGpioPs, ptr %53, i32 0, i32 5
  store i32 118, ptr %54, align 4, !tbaa !20
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.XGpioPs, ptr %55, i32 0, i32 6
  store i8 4, ptr %56, align 8, !tbaa !21
  br label %57

57:                                               ; preds = %52, %47
  store i8 0, ptr %9, align 1, !tbaa !22
  br label %58

58:                                               ; preds = %77, %57
  %59 = load i8, ptr %9, align 1, !tbaa !22
  %60 = zext i8 %59 to i32
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.XGpioPs, ptr %61, i32 0, i32 6
  %63 = load i8, ptr %62, align 8, !tbaa !21
  %64 = zext i8 %63 to i32
  %65 = icmp slt i32 %60, %64
  br i1 %65, label %66, label %80

66:                                               ; preds = %58
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.XGpioPs, ptr %67, i32 0, i32 0
  %69 = getelementptr inbounds %struct.XGpioPs_Config, ptr %68, i32 0, i32 1
  %70 = load i32, ptr %69, align 4, !tbaa !15
  %71 = load i8, ptr %9, align 1, !tbaa !22
  %72 = zext i8 %71 to i32
  %73 = mul i32 %72, 64
  %74 = add i32 %73, 532
  %75 = add i32 %70, %74
  %76 = zext i32 %75 to i64
  call void @Xil_Out32(i64 noundef %76, i32 noundef -1)
  br label %77

77:                                               ; preds = %66
  %78 = load i8, ptr %9, align 1, !tbaa !22
  %79 = add i8 %78, 1
  store i8 %79, ptr %9, align 1, !tbaa !22
  br label %58, !llvm.loop !23

80:                                               ; preds = %58
  %81 = load ptr, ptr %5, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.XGpioPs, ptr %81, i32 0, i32 1
  store i32 286331153, ptr %82, align 8, !tbaa !11
  %83 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %83, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %84

84:                                               ; preds = %80, %24, %19, %14
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %85 = load i32, ptr %4, align 4
  ret i32 %85
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

declare void @StubHandler(ptr noundef, i32 noundef, i32 noundef) #2

declare i32 @XGetPlatform_Info() #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8, !6, i64 16, !6, i64 24, !10, i64 32, !10, i64 36, !7, i64 40}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !10, i64 4}
!16 = !{!13, !14, i64 0}
!17 = !{!12, !14, i64 0}
!18 = !{!12, !6, i64 16}
!19 = !{!12, !10, i64 32}
!20 = !{!12, !10, i64 36}
!21 = !{!12, !7, i64 40}
!22 = !{!7, !7, i64 0}
!23 = distinct !{!23, !24}
!24 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @XGpioPs_CfgInitialize(ptr noundef %0, ptr noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %5, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not27 = icmp eq ptr %1, null
  br i1 %.not27, label %7, label %6

5:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 100) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %26

6:                                                ; preds = %4
  %.not28 = icmp eq i32 %2, 0
  br i1 %.not28, label %17, label %.lr.ph.preheader

7:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 101) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %26

.lr.ph.preheader:                                 ; preds = %6
  %8 = getelementptr inbounds i8, ptr %0, i64 8
  store i32 0, ptr %8, align 8, !tbaa !9
  %9 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 %2, ptr %9, align 4, !tbaa !14
  %10 = load i16, ptr %1, align 4, !tbaa !15
  store i16 %10, ptr %0, align 8, !tbaa !16
  %11 = getelementptr inbounds i8, ptr %0, i64 16
  store ptr @StubHandler, ptr %11, align 8, !tbaa !17
  %12 = tail call i32 @XGetPlatform_Info() #3
  %13 = getelementptr inbounds i8, ptr %0, i64 32
  store i32 %12, ptr %13, align 8, !tbaa !18
  %14 = icmp eq i32 %12, 1
  %spec.select = select i1 %14, i32 174, i32 118
  %spec.select33 = select i1 %14, i8 6, i8 4
  %15 = getelementptr inbounds i8, ptr %0, i64 36
  store i32 %spec.select, ptr %15, align 4
  %16 = getelementptr inbounds i8, ptr %0, i64 40
  store i8 %spec.select33, ptr %16, align 8
  br label %.lr.ph

17:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 102) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %26

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i32 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %18 = load i32, ptr %9, align 4, !tbaa !14
  %19 = shl nuw nsw i32 %indvars.iv, 6
  %20 = add nuw nsw i32 %19, 532
  %21 = add i32 %20, %18
  %22 = zext i32 %21 to i64
  tail call void @Xil_Out32(i64 noundef %22, i32 noundef -1)
  %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
  %23 = load i8, ptr %16, align 8, !tbaa !19
  %24 = zext i8 %23 to i32
  %25 = icmp ult i32 %indvars.iv.next, %24
  br i1 %25, label %.lr.ph, label %._crit_edge, !llvm.loop !20

._crit_edge:                                      ; preds = %.lr.ph
  store i32 286331153, ptr %8, align 8, !tbaa !9
  br label %26

26:                                               ; preds = %._crit_edge, %17, %7, %5
  ret i32 0
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

declare void @StubHandler(ptr noundef, i32 noundef, i32 noundef) #1

declare i32 @XGetPlatform_Info() local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !6, i64 4}
!15 = !{!11, !12, i64 0}
!16 = !{!10, !12, i64 0}
!17 = !{!10, !13, i64 16}
!18 = !{!10, !6, i64 32}
!19 = !{!10, !7, i64 40}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,MergedLoadStoreMotionPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass