; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (WritePin)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_WritePin(ptr noundef %0, i32 noundef %1, i32 noundef %2) #3 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %13 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %13, ptr %11, align 4, !tbaa !9
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %18

17:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 266)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %12, align 4
  br label %71

18:                                               ; preds = %16
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.XGpioPs, ptr %19, i32 0, i32 1
  %21 = load i32, ptr %20, align 8, !tbaa !11
  %22 = icmp eq i32 %21, 286331153
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %25

24:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 267)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %12, align 4
  br label %71

25:                                               ; preds = %23
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.XGpioPs, ptr %27, i32 0, i32 5
  %29 = load i32, ptr %28, align 4, !tbaa !15
  %30 = icmp ult i32 %26, %29
  br i1 %30, label %31, label %32

31:                                               ; preds = %25
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %33

32:                                               ; preds = %25
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 268)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %12, align 4
  br label %71

33:                                               ; preds = %31
  %34 = load i32, ptr %5, align 4, !tbaa !9
  %35 = trunc i32 %34 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %35, ptr noundef %9, ptr noundef %10)
  %36 = load i8, ptr %10, align 1, !tbaa !16
  %37 = zext i8 %36 to i32
  %38 = icmp ugt i32 %37, 15
  br i1 %38, label %39, label %44

39:                                               ; preds = %33
  %40 = load i8, ptr %10, align 1, !tbaa !16
  %41 = zext i8 %40 to i32
  %42 = sub nsw i32 %41, 16
  %43 = trunc i32 %42 to i8
  store i8 %43, ptr %10, align 1, !tbaa !16
  store i32 4, ptr %7, align 4, !tbaa !9
  br label %45

44:                                               ; preds = %33
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %45

45:                                               ; preds = %44, %39
  %46 = load i32, ptr %11, align 4, !tbaa !9
  %47 = and i32 %46, 1
  store i32 %47, ptr %11, align 4, !tbaa !9
  %48 = load i8, ptr %10, align 1, !tbaa !16
  %49 = zext i8 %48 to i32
  %50 = add i32 %49, 16
  %51 = shl i32 1, %50
  %52 = xor i32 %51, -1
  %53 = load i32, ptr %11, align 4, !tbaa !9
  %54 = load i8, ptr %10, align 1, !tbaa !16
  %55 = zext i8 %54 to i32
  %56 = shl i32 %53, %55
  %57 = or i32 %56, -65536
  %58 = and i32 %52, %57
  store i32 %58, ptr %8, align 4, !tbaa !9
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.XGpioPs, ptr %59, i32 0, i32 0
  %61 = getelementptr inbounds %struct.XGpioPs_Config, ptr %60, i32 0, i32 1
  %62 = load i32, ptr %61, align 4, !tbaa !17
  %63 = load i8, ptr %9, align 1, !tbaa !16
  %64 = zext i8 %63 to i32
  %65 = mul i32 %64, 8
  %66 = load i32, ptr %7, align 4, !tbaa !9
  %67 = add i32 %65, %66
  %68 = add i32 %62, %67
  %69 = zext i32 %68 to i64
  %70 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %69, i32 noundef %70)
  store i32 0, ptr %12, align 4
  br label %71

71:                                               ; preds = %45, %32, %24, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  %72 = load i32, ptr %12, align 4
  switch i32 %72, label %74 [
    i32 0, label %73
    i32 1, label %73
  ]

73:                                               ; preds = %71, %71
  ret void

74:                                               ; preds = %71
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8, !6, i64 16, !6, i64 24, !10, i64 32, !10, i64 36, !7, i64 40}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !10, i64 36}
!16 = !{!7, !7, i64 0}
!17 = !{!12, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_WritePin(ptr noundef readonly %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #3 {
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #4
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %15

10:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 266) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %40

11:                                               ; preds = %6
  %12 = getelementptr inbounds i8, ptr %0, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !14
  %14 = icmp ugt i32 %13, %1
  br i1 %14, label %16, label %20

15:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 267) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %40

16:                                               ; preds = %11
  %17 = trunc i32 %1 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %17, ptr noundef nonnull %4, ptr noundef nonnull %5)
  %18 = load i8, ptr %5, align 1, !tbaa !15
  %19 = icmp ugt i8 %18, 15
  br i1 %19, label %21, label %23

20:                                               ; preds = %11
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 268) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %40

21:                                               ; preds = %16
  %22 = add i8 %18, -16
  store i8 %22, ptr %5, align 1, !tbaa !15
  br label %23

23:                                               ; preds = %16, %21
  %24 = phi i8 [ %22, %21 ], [ %18, %16 ]
  %.0 = phi i32 [ 4, %21 ], [ 0, %16 ]
  %25 = and i32 %2, 1
  %26 = zext i8 %24 to i32
  %27 = shl nuw i32 65536, %26
  %28 = xor i32 %27, -1
  %29 = shl nuw i32 %25, %26
  %30 = or i32 %29, -65536
  %31 = and i32 %30, %28
  %32 = getelementptr inbounds i8, ptr %0, i64 4
  %33 = load i32, ptr %32, align 4, !tbaa !16
  %34 = load i8, ptr %4, align 1, !tbaa !15
  %35 = zext i8 %34 to i32
  %36 = shl nuw nsw i32 %35, 3
  %37 = add i32 %33, %.0
  %38 = add i32 %37, %36
  %39 = zext i32 %38 to i64
  call void @Xil_Out32(i64 noundef %39, i32 noundef %31)
  br label %40

40:                                               ; preds = %23, %20, %15, %10
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #4
  ret void
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !6, i64 36}
!15 = !{!7, !7, i64 0}
!16 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass