; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (GetSequencerMode)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }
%struct.XAdcPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @XAdcPs_GetSequencerMode(ptr noundef %0) #1 {
  %2 = alloca i8, align 1
  %3 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %4 = load ptr, ptr %3, align 8, !tbaa !5
  %5 = icmp ne ptr %4, null
  br i1 %5, label %6, label %7

6:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %8

7:                                                ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 915)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i8 0, ptr %2, align 1
  br label %21

8:                                                ; preds = %6
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.XAdcPs, ptr %9, i32 0, i32 1
  %11 = load i32, ptr %10, align 4, !tbaa !11
  %12 = icmp eq i32 %11, 286331153
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %15

14:                                               ; preds = %8
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 916)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i8 0, ptr %2, align 1
  br label %21

15:                                               ; preds = %13
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = call i32 @XAdcPs_ReadInternalReg(ptr noundef %16, i32 noundef 65)
  %18 = and i32 %17, 61440
  %19 = lshr i32 %18, 12
  %20 = trunc i32 %19 to i8
  store i8 %20, ptr %2, align 1
  br label %21

21:                                               ; preds = %15, %14, %7
  %22 = load i8, ptr %2, align 1
  ret i8 %22
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 16) i8 @XAdcPs_GetSequencerMode(ptr noundef %0) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %2

2:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 4, !tbaa !9
  %5 = icmp eq i32 %4, 286331153
  br i1 %5, label %7, label %12

6:                                                ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 915) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %13

7:                                                ; preds = %2
  %8 = tail call i32 @XAdcPs_ReadInternalReg(ptr noundef nonnull %0, i32 noundef 65)
  %9 = lshr i32 %8, 12
  %10 = trunc i32 %9 to i8
  %11 = and i8 %10, 15
  br label %13

12:                                               ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 916) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %7, %12, %6
  %.0 = phi i8 [ %11, %7 ], [ 0, %12 ], [ 0, %6 ]
  ret i8 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass