; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/qspips_v3 (SetDelays)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XQspiPs = type { %struct.XQspiPs_Config, i32, ptr, ptr, i32, i32, i32, ptr, ptr, i32 }
%struct.XQspiPs_Config = type { i16, i32, i32, i8 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XQspiPs_SetDelays(ptr noundef %0, i8 noundef zeroext %1, i8 noundef zeroext %2, i8 noundef zeroext %3, i8 noundef zeroext %4) #3 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i8 %1, ptr %8, align 1, !tbaa !9
  store i8 %2, ptr %9, align 1, !tbaa !9
  store i8 %3, ptr %10, align 1, !tbaa !9
  store i8 %4, ptr %11, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %14 = load ptr, ptr %7, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %18

17:                                               ; preds = %5
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 359)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %56

18:                                               ; preds = %16
  %19 = load ptr, ptr %7, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.XQspiPs, ptr %19, i32 0, i32 1
  %21 = load i32, ptr %20, align 8, !tbaa !12
  %22 = icmp eq i32 %21, 286331153
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %25

24:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 360)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %56

25:                                               ; preds = %23
  %26 = load ptr, ptr %7, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XQspiPs, ptr %26, i32 0, i32 6
  %28 = load i32, ptr %27, align 8, !tbaa !16
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %25
  store i32 21, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %56

31:                                               ; preds = %25
  %32 = load i8, ptr %8, align 1, !tbaa !9
  %33 = zext i8 %32 to i32
  %34 = shl i32 %33, 24
  store i32 %34, ptr %12, align 4, !tbaa !10
  %35 = load i8, ptr %9, align 1, !tbaa !9
  %36 = zext i8 %35 to i32
  %37 = shl i32 %36, 16
  %38 = load i32, ptr %12, align 4, !tbaa !10
  %39 = or i32 %38, %37
  store i32 %39, ptr %12, align 4, !tbaa !10
  %40 = load i8, ptr %10, align 1, !tbaa !9
  %41 = zext i8 %40 to i32
  %42 = shl i32 %41, 8
  %43 = load i32, ptr %12, align 4, !tbaa !10
  %44 = or i32 %43, %42
  store i32 %44, ptr %12, align 4, !tbaa !10
  %45 = load i8, ptr %11, align 1, !tbaa !9
  %46 = zext i8 %45 to i32
  %47 = load i32, ptr %12, align 4, !tbaa !10
  %48 = or i32 %47, %46
  store i32 %48, ptr %12, align 4, !tbaa !10
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XQspiPs, ptr %49, i32 0, i32 0
  %51 = getelementptr inbounds %struct.XQspiPs_Config, ptr %50, i32 0, i32 1
  %52 = load i32, ptr %51, align 4, !tbaa !17
  %53 = add i32 %52, 24
  %54 = zext i32 %53 to i64
  %55 = load i32, ptr %12, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %54, i32 noundef %55)
  store i32 0, ptr %6, align 4
  store i32 1, ptr %13, align 4
  br label %56

56:                                               ; preds = %31, %30, %24, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  %57 = load i32, ptr %6, align 4
  ret i32 %57
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 16}
!13 = !{!"", !14, i64 0, !11, i64 16, !6, i64 24, !6, i64 32, !11, i64 40, !11, i64 44, !11, i64 48, !6, i64 56, !6, i64 64, !11, i64 72}
!14 = !{!"", !15, i64 0, !11, i64 4, !11, i64 8, !7, i64 12}
!15 = !{!"short", !7, i64 0}
!16 = !{!13, !11, i64 48}
!17 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [171 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 22) i32 @XQspiPs_SetDelays(ptr noundef readonly %0, i8 noundef zeroext %1, i8 noundef zeroext %2, i8 noundef zeroext %3, i8 noundef zeroext %4) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 16
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %14

10:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 359) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %30

11:                                               ; preds = %6
  %12 = getelementptr inbounds i8, ptr %0, i64 48
  %13 = load i32, ptr %12, align 8, !tbaa !14
  %.not13 = icmp eq i32 %13, 0
  br i1 %.not13, label %15, label %30

14:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 360) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %30

15:                                               ; preds = %11
  %16 = zext i8 %1 to i32
  %17 = shl nuw i32 %16, 24
  %18 = zext i8 %2 to i32
  %19 = shl nuw nsw i32 %18, 16
  %20 = or disjoint i32 %19, %17
  %21 = zext i8 %3 to i32
  %22 = shl nuw nsw i32 %21, 8
  %23 = or disjoint i32 %20, %22
  %24 = zext i8 %4 to i32
  %25 = or disjoint i32 %23, %24
  %26 = getelementptr inbounds i8, ptr %0, i64 4
  %27 = load i32, ptr %26, align 4, !tbaa !15
  %28 = add i32 %27, 24
  %29 = zext i32 %28 to i64
  tail call void @Xil_Out32(i64 noundef %29, i32 noundef %25)
  br label %30

30:                                               ; preds = %11, %15, %14, %10
  %.0 = phi i32 [ 0, %15 ], [ 0, %14 ], [ 0, %10 ], [ 21, %11 ]
  ret i32 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 16}
!10 = !{!"", !11, i64 0, !6, i64 16, !13, i64 24, !13, i64 32, !6, i64 40, !6, i64 44, !6, i64 48, !13, i64 56, !13, i64 64, !6, i64 72}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !7, i64 12}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !6, i64 48}
!15 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass