; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (L2CacheInvalidate)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L2CacheInvalidate() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 ptrtoint (ptr @_stack_end to i32), ptr %2, align 4, !tbaa !5
  store i32 ptrtoint (ptr @__undef_stack to i32), ptr %1, align 4, !tbaa !5
  %6 = load i32, ptr %1, align 4, !tbaa !5
  %7 = load i32, ptr %2, align 4, !tbaa !5
  %8 = sub i32 %6, %7
  store i32 %8, ptr %3, align 4, !tbaa !5
  %9 = call i32 @Xil_In32(i64 noundef 4176486656)
  store i32 %9, ptr %4, align 4, !tbaa !5
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = and i32 %10, 1
  %12 = icmp ne i32 %11, 0
  br i1 %12, label %13, label %17

13:                                               ; preds = %0
  %14 = load i32, ptr %2, align 4, !tbaa !5
  %15 = zext i32 %14 to i64
  %16 = load i32, ptr %3, align 4, !tbaa !5
  call void @Xil_DCacheFlushRange(i64 noundef %15, i32 noundef %16)
  br label %17

17:                                               ; preds = %13, %0
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @Xil_Out32(i64 noundef 4176488316, i32 noundef 65535)
  %18 = call i32 @Xil_In32(i64 noundef 4176488316)
  %19 = and i32 %18, 65535
  store i32 %19, ptr %5, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %23, %17
  %21 = load i32, ptr %5, align 4, !tbaa !5
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %26

23:                                               ; preds = %20
  %24 = call i32 @Xil_In32(i64 noundef 4176488316)
  %25 = and i32 %24, 65535
  store i32 %25, ptr %5, align 4, !tbaa !5
  br label %20, !llvm.loop !9

26:                                               ; preds = %20
  call void @Xil_L2CacheSync()
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #3
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() #2

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{i64 2147869392}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_stack_end = external global i32, align 4
@__undef_stack = external global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L2CacheInvalidate() local_unnamed_addr #0 {
  %1 = tail call i32 @Xil_In32(i64 noundef 4176486656)
  %2 = and i32 %1, 1
  %.not = icmp eq i32 %2, 0
  br i1 %.not, label %5, label %3

3:                                                ; preds = %0
  %4 = zext i32 ptrtoint (ptr @_stack_end to i32) to i64
  tail call void @Xil_DCacheFlushRange(i64 noundef %4, i32 noundef sub (i32 ptrtoint (ptr @__undef_stack to i32), i32 ptrtoint (ptr @_stack_end to i32)))
  br label %5

5:                                                ; preds = %3, %0
  tail call void @Xil_Out32(i64 noundef 4176488316, i32 noundef 65535)
  %6 = tail call i32 @Xil_In32(i64 noundef 4176488316)
  %.07 = and i32 %6, 65535
  %.not68 = icmp eq i32 %.07, 0
  br i1 %.not68, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %5, %.lr.ph
  %7 = tail call i32 @Xil_In32(i64 noundef 4176488316)
  %.0 = and i32 %7, 65535
  %.not6 = icmp eq i32 %.0, 0
  br i1 %.not6, label %._crit_edge, label %.lr.ph, !llvm.loop !5

._crit_edge:                                      ; preds = %.lr.ph, %5
  tail call void @Xil_L2CacheSync()
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !7
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{i64 2147869392}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass