; LLVM IR from GCY/wxECGAnalyzer :: embedded/stm32f407 - 360Hz/src/stm32f4/algorithm (HC_Chen_detect)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@ecg_buff = external hidden global [10 x float], align 16
@ecg_buff_WR_idx = external hidden global i32, align 4
@sample = external hidden global i32, align 4
@number_iter = external hidden global i32, align 4
@ecg_buff_RD_idx = external hidden global i32, align 4
@hp_sum = external hidden global float, align 4
@hp_buff = external hidden global [55 x float], align 16
@hp_buff_WR_idx = external hidden global i32, align 4
@hp_buff_RD_idx = external hidden global i32, align 4
@lp_sum = external hidden global float, align 4
@next_eval_pt = external hidden global float, align 4
@treshold = external hidden global float, align 4
@triggered = external hidden global i8, align 1
@trig_time = external hidden global i32, align 4
@win_max = external hidden global float, align 4
@last_qrs_point = external hidden global i32, align 4
@win_idx = external hidden global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local zeroext i1 @HC_Chen_detect(float noundef %0) #0 {
  %2 = alloca i1, align 1
  %3 = alloca float, align 4
  %4 = alloca i32, align 4
  %5 = alloca float, align 4
  %6 = alloca float, align 4
  %7 = alloca i32, align 4
  %8 = alloca float, align 4
  %9 = alloca float, align 4
  store float %0, ptr %3, align 4, !tbaa !5
  %10 = load float, ptr %3, align 4, !tbaa !5
  %11 = load i32, ptr @ecg_buff_WR_idx, align 4, !tbaa !9
  %12 = add nsw i32 %11, 1
  store i32 %12, ptr @ecg_buff_WR_idx, align 4, !tbaa !9
  %13 = sext i32 %11 to i64
  %14 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %13
  store float %10, ptr %14, align 4, !tbaa !5
  %15 = load i32, ptr @ecg_buff_WR_idx, align 4, !tbaa !9
  store i32 %15, ptr @sample, align 4, !tbaa !9
  %16 = load i32, ptr @ecg_buff_WR_idx, align 4, !tbaa !9
  %17 = srem i32 %16, 10
  store i32 %17, ptr @ecg_buff_WR_idx, align 4, !tbaa !9
  %18 = load i32, ptr @number_iter, align 4, !tbaa !9
  %19 = icmp slt i32 %18, 9
  br i1 %19, label %20, label %30

20:                                               ; preds = %1
  %21 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %22
  %24 = load float, ptr %23, align 4, !tbaa !5
  %25 = load float, ptr @hp_sum, align 4, !tbaa !5
  %26 = fadd float %25, %24
  store float %26, ptr @hp_sum, align 4, !tbaa !5
  %27 = load i32, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %28 = sext i32 %27 to i64
  %29 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %28
  store float 0.000000e+00, ptr %29, align 4, !tbaa !5
  br label %71

30:                                               ; preds = %1
  %31 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %32 = sext i32 %31 to i64
  %33 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %32
  %34 = load float, ptr %33, align 4, !tbaa !5
  %35 = load float, ptr @hp_sum, align 4, !tbaa !5
  %36 = fadd float %35, %34
  store float %36, ptr @hp_sum, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  %37 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %38 = sub nsw i32 %37, 9
  store i32 %38, ptr %4, align 4, !tbaa !9
  %39 = load i32, ptr %4, align 4, !tbaa !9
  %40 = icmp slt i32 %39, 0
  br i1 %40, label %41, label %44

41:                                               ; preds = %30
  %42 = load i32, ptr %4, align 4, !tbaa !9
  %43 = add nsw i32 %42, 10
  store i32 %43, ptr %4, align 4, !tbaa !9
  br label %44

44:                                               ; preds = %41, %30
  %45 = load i32, ptr %4, align 4, !tbaa !9
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %46
  %48 = load float, ptr %47, align 4, !tbaa !5
  %49 = load float, ptr @hp_sum, align 4, !tbaa !5
  %50 = fsub float %49, %48
  store float %50, ptr @hp_sum, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  store float 0.000000e+00, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  store float 0.000000e+00, ptr %6, align 4, !tbaa !5
  %51 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %52 = sub nsw i32 %51, 5
  store i32 %52, ptr %4, align 4, !tbaa !9
  %53 = load i32, ptr %4, align 4, !tbaa !9
  %54 = icmp slt i32 %53, 0
  br i1 %54, label %55, label %58

55:                                               ; preds = %44
  %56 = load i32, ptr %4, align 4, !tbaa !9
  %57 = add nsw i32 %56, 10
  store i32 %57, ptr %4, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %55, %44
  %59 = load i32, ptr %4, align 4, !tbaa !9
  %60 = sext i32 %59 to i64
  %61 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %60
  %62 = load float, ptr %61, align 4, !tbaa !5
  store float %62, ptr %6, align 4, !tbaa !5
  %63 = load float, ptr @hp_sum, align 4, !tbaa !5
  %64 = fmul float 0x3FBC71C720000000, %63
  store float %64, ptr %5, align 4, !tbaa !5
  %65 = load float, ptr %6, align 4, !tbaa !5
  %66 = load float, ptr %5, align 4, !tbaa !5
  %67 = fsub float %65, %66
  %68 = load i32, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %69 = sext i32 %68 to i64
  %70 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %69
  store float %67, ptr %70, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  br label %71

71:                                               ; preds = %58, %20
  %72 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %73 = add nsw i32 %72, 1
  store i32 %73, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %74 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %75 = srem i32 %74, 10
  store i32 %75, ptr @ecg_buff_RD_idx, align 4, !tbaa !9
  %76 = load i32, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %77 = add nsw i32 %76, 1
  store i32 %77, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %78 = load i32, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %79 = srem i32 %78, 55
  store i32 %79, ptr @hp_buff_WR_idx, align 4, !tbaa !9
  %80 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %81 = sext i32 %80 to i64
  %82 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %81
  %83 = load float, ptr %82, align 4, !tbaa !5
  %84 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %85 = sext i32 %84 to i64
  %86 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %85
  %87 = load float, ptr %86, align 4, !tbaa !5
  %88 = load float, ptr @lp_sum, align 4, !tbaa !5
  %89 = call float @llvm.fmuladd.f32(float %83, float %87, float %88)
  store float %89, ptr @lp_sum, align 4, !tbaa !5
  %90 = load i32, ptr @number_iter, align 4, !tbaa !9
  %91 = icmp slt i32 %90, 54
  br i1 %91, label %92, label %93

92:                                               ; preds = %71
  store float 0.000000e+00, ptr @next_eval_pt, align 4, !tbaa !5
  br label %114

93:                                               ; preds = %71
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %94 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %95 = sub nsw i32 %94, 54
  store i32 %95, ptr %7, align 4, !tbaa !9
  %96 = load i32, ptr %7, align 4, !tbaa !9
  %97 = icmp slt i32 %96, 0
  br i1 %97, label %98, label %101

98:                                               ; preds = %93
  %99 = load i32, ptr %7, align 4, !tbaa !9
  %100 = add nsw i32 %99, 55
  store i32 %100, ptr %7, align 4, !tbaa !9
  br label %101

101:                                              ; preds = %98, %93
  %102 = load i32, ptr %7, align 4, !tbaa !9
  %103 = sext i32 %102 to i64
  %104 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %103
  %105 = load float, ptr %104, align 4, !tbaa !5
  %106 = load i32, ptr %7, align 4, !tbaa !9
  %107 = sext i32 %106 to i64
  %108 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %107
  %109 = load float, ptr %108, align 4, !tbaa !5
  %110 = load float, ptr @lp_sum, align 4, !tbaa !5
  %111 = fneg float %105
  %112 = call float @llvm.fmuladd.f32(float %111, float %109, float %110)
  store float %112, ptr @lp_sum, align 4, !tbaa !5
  %113 = load float, ptr @lp_sum, align 4, !tbaa !5
  store float %113, ptr @next_eval_pt, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %114

114:                                              ; preds = %101, %92
  %115 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %116 = add nsw i32 %115, 1
  store i32 %116, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %117 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %118 = srem i32 %117, 55
  store i32 %118, ptr @hp_buff_RD_idx, align 4, !tbaa !9
  %119 = load i32, ptr @number_iter, align 4, !tbaa !9
  %120 = icmp ult i32 %119, 360
  br i1 %120, label %121, label %130

121:                                              ; preds = %114
  %122 = load float, ptr @next_eval_pt, align 4, !tbaa !5
  %123 = load float, ptr @treshold, align 4, !tbaa !5
  %124 = fcmp ogt float %122, %123
  br i1 %124, label %125, label %127

125:                                              ; preds = %121
  %126 = load float, ptr @next_eval_pt, align 4, !tbaa !5
  store float %126, ptr @treshold, align 4, !tbaa !5
  br label %127

127:                                              ; preds = %125, %121
  %128 = load i32, ptr @number_iter, align 4, !tbaa !9
  %129 = add nsw i32 %128, 1
  store i32 %129, ptr @number_iter, align 4, !tbaa !9
  br label %130

130:                                              ; preds = %127, %114
  %131 = load i8, ptr @triggered, align 1, !tbaa !11, !range !13, !noundef !14
  %132 = trunc i8 %131 to i1
  br i1 %132, label %133, label %140

133:                                              ; preds = %130
  %134 = load i32, ptr @trig_time, align 4, !tbaa !9
  %135 = add nsw i32 %134, 1
  store i32 %135, ptr @trig_time, align 4, !tbaa !9
  %136 = load i32, ptr @trig_time, align 4, !tbaa !9
  %137 = icmp sge i32 %136, 180
  br i1 %137, label %138, label %139

138:                                              ; preds = %133
  store i8 0, ptr @triggered, align 1, !tbaa !11
  store i32 0, ptr @trig_time, align 4, !tbaa !9
  br label %139

139:                                              ; preds = %138, %133
  br label %140

140:                                              ; preds = %139, %130
  %141 = load float, ptr @next_eval_pt, align 4, !tbaa !5
  %142 = load float, ptr @win_max, align 4, !tbaa !5
  %143 = fcmp ogt float %141, %142
  br i1 %143, label %144, label %146

144:                                              ; preds = %140
  %145 = load float, ptr @next_eval_pt, align 4, !tbaa !5
  store float %145, ptr @win_max, align 4, !tbaa !5
  br label %146

146:                                              ; preds = %144, %140
  %147 = load float, ptr @next_eval_pt, align 4, !tbaa !5
  %148 = load float, ptr @treshold, align 4, !tbaa !5
  %149 = fcmp ogt float %147, %148
  br i1 %149, label %150, label %155

150:                                              ; preds = %146
  %151 = load i8, ptr @triggered, align 1, !tbaa !11, !range !13, !noundef !14
  %152 = trunc i8 %151 to i1
  br i1 %152, label %155, label %153

153:                                              ; preds = %150
  %154 = load i32, ptr @sample, align 4, !tbaa !9
  store i32 %154, ptr @last_qrs_point, align 4, !tbaa !9
  store i8 1, ptr @triggered, align 1, !tbaa !11
  store i1 true, ptr %2, align 1
  br label %175

155:                                              ; preds = %150, %146
  br label %156

156:                                              ; preds = %155
  %157 = load i32, ptr @win_idx, align 4, !tbaa !9
  %158 = add nsw i32 %157, 1
  store i32 %158, ptr @win_idx, align 4, !tbaa !9
  %159 = icmp uge i32 %157, 360
  br i1 %159, label %160, label %174

160:                                              ; preds = %156
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store float 0x3FC6666680000000, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %161 = call i32 @rand() #4
  %162 = sitofp i32 %161 to float
  %163 = fdiv float %162, 0x41E0000000000000
  %164 = call float @llvm.fmuladd.f32(float %163, float 0x3FB70A3D80000000, float 0x3F847AE140000000)
  store float %164, ptr %9, align 4, !tbaa !5
  %165 = load float, ptr %9, align 4, !tbaa !5
  %166 = load float, ptr %8, align 4, !tbaa !5
  %167 = fmul float %165, %166
  %168 = load float, ptr @win_max, align 4, !tbaa !5
  %169 = load float, ptr %9, align 4, !tbaa !5
  %170 = fsub float 1.000000e+00, %169
  %171 = load float, ptr @treshold, align 4, !tbaa !5
  %172 = fmul float %170, %171
  %173 = call float @llvm.fmuladd.f32(float %167, float %168, float %172)
  store float %173, ptr @treshold, align 4, !tbaa !5
  store i32 0, ptr @win_idx, align 4, !tbaa !9
  store float -1.000000e+07, ptr @win_max, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %174

174:                                              ; preds = %160, %156
  store i1 false, ptr %2, align 1
  br label %175

175:                                              ; preds = %174, %153
  %176 = load i1, ptr %2, align 1
  ret i1 %176
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #2

; Function Attrs: nounwind
declare i32 @rand() #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_Bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@ecg_buff = external hidden local_unnamed_addr global [10 x float], align 16
@ecg_buff_WR_idx = external hidden local_unnamed_addr global i32, align 4
@sample = external hidden local_unnamed_addr global i32, align 4
@number_iter = external hidden local_unnamed_addr global i32, align 4
@ecg_buff_RD_idx = external hidden local_unnamed_addr global i32, align 4
@hp_sum = external hidden local_unnamed_addr global float, align 4
@hp_buff = external hidden local_unnamed_addr global [55 x float], align 16
@hp_buff_WR_idx = external hidden local_unnamed_addr global i32, align 4
@hp_buff_RD_idx = external hidden local_unnamed_addr global i32, align 4
@lp_sum = external hidden local_unnamed_addr global float, align 4
@next_eval_pt = external hidden local_unnamed_addr global float, align 4
@treshold = external hidden local_unnamed_addr global float, align 4
@triggered = external hidden local_unnamed_addr global i8, align 1
@trig_time = external hidden local_unnamed_addr global i32, align 4
@win_max = external hidden local_unnamed_addr global float, align 4
@last_qrs_point = external hidden local_unnamed_addr global i32, align 4
@win_idx = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local noundef zeroext i1 @HC_Chen_detect(float noundef %0) local_unnamed_addr #0 {
  %2 = load i32, ptr @ecg_buff_WR_idx, align 4, !tbaa !5
  %3 = add nsw i32 %2, 1
  %4 = sext i32 %2 to i64
  %5 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %4
  store float %0, ptr %5, align 4, !tbaa !9
  store i32 %3, ptr @sample, align 4, !tbaa !5
  %6 = srem i32 %3, 10
  store i32 %6, ptr @ecg_buff_WR_idx, align 4, !tbaa !5
  %7 = load i32, ptr @number_iter, align 4, !tbaa !5
  %8 = icmp slt i32 %7, 9
  %9 = load i32, ptr @ecg_buff_RD_idx, align 4, !tbaa !5
  %10 = sext i32 %9 to i64
  %11 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %10
  %12 = load float, ptr %11, align 4, !tbaa !9
  %13 = load float, ptr @hp_sum, align 4, !tbaa !9
  %14 = fadd float %12, %13
  br i1 %8, label %27, label %15

15:                                               ; preds = %1
  %16 = icmp slt i32 %9, 9
  %spec.select.v = select i1 %16, i32 1, i32 -9
  %spec.select = add nsw i32 %spec.select.v, %9
  %17 = sext i32 %spec.select to i64
  %18 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %17
  %19 = load float, ptr %18, align 4, !tbaa !9
  %20 = fsub float %14, %19
  %21 = icmp slt i32 %9, 5
  %.1.v = select i1 %21, i32 5, i32 -5
  %.1 = add nsw i32 %.1.v, %9
  %22 = sext i32 %.1 to i64
  %23 = getelementptr inbounds [10 x float], ptr @ecg_buff, i64 0, i64 %22
  %24 = load float, ptr %23, align 4, !tbaa !9
  %25 = fmul float %20, 0x3FBC71C720000000
  %26 = fsub float %24, %25
  br label %27

27:                                               ; preds = %1, %15
  %.sink27 = phi float [ %26, %15 ], [ 0.000000e+00, %1 ]
  %.sink = phi float [ %20, %15 ], [ %14, %1 ]
  %28 = load i32, ptr @hp_buff_WR_idx, align 4, !tbaa !5
  %29 = sext i32 %28 to i64
  %30 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %29
  store float %.sink27, ptr %30, align 4, !tbaa !9
  store float %.sink, ptr @hp_sum, align 4
  %31 = add nsw i32 %9, 1
  %32 = srem i32 %31, 10
  store i32 %32, ptr @ecg_buff_RD_idx, align 4, !tbaa !5
  %33 = add nsw i32 %28, 1
  %34 = srem i32 %33, 55
  store i32 %34, ptr @hp_buff_WR_idx, align 4, !tbaa !5
  %35 = load i32, ptr @hp_buff_RD_idx, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %36
  %38 = load float, ptr %37, align 4, !tbaa !9
  %39 = load float, ptr @lp_sum, align 4, !tbaa !9
  %40 = tail call float @llvm.fmuladd.f32(float %38, float %38, float %39)
  store float %40, ptr @lp_sum, align 4, !tbaa !9
  %41 = icmp slt i32 %7, 54
  br i1 %41, label %49, label %42

42:                                               ; preds = %27
  %43 = icmp slt i32 %35, 54
  %spec.select26.v = select i1 %43, i32 1, i32 -54
  %spec.select26 = add nsw i32 %spec.select26.v, %35
  %44 = sext i32 %spec.select26 to i64
  %45 = getelementptr inbounds [55 x float], ptr @hp_buff, i64 0, i64 %44
  %46 = load float, ptr %45, align 4, !tbaa !9
  %47 = fneg float %46
  %48 = tail call float @llvm.fmuladd.f32(float %47, float %46, float %40)
  store float %48, ptr @lp_sum, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %27, %42
  %storemerge = phi float [ %48, %42 ], [ 0.000000e+00, %27 ]
  store float %storemerge, ptr @next_eval_pt, align 4, !tbaa !9
  %50 = add nsw i32 %35, 1
  %51 = srem i32 %50, 55
  store i32 %51, ptr @hp_buff_RD_idx, align 4, !tbaa !5
  %52 = icmp ult i32 %7, 360
  br i1 %52, label %53, label %59

53:                                               ; preds = %49
  %54 = load float, ptr @treshold, align 4, !tbaa !9
  %55 = fcmp ogt float %storemerge, %54
  br i1 %55, label %56, label %57

56:                                               ; preds = %53
  store float %storemerge, ptr @treshold, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %56, %53
  %58 = add nuw nsw i32 %7, 1
  store i32 %58, ptr @number_iter, align 4, !tbaa !5
  br label %59

59:                                               ; preds = %57, %49
  %60 = load i8, ptr @triggered, align 1, !tbaa !11, !range !13, !noundef !14
  %61 = trunc nuw i8 %60 to i1
  br i1 %61, label %62, label %67

62:                                               ; preds = %59
  %63 = load i32, ptr @trig_time, align 4, !tbaa !5
  %64 = add nsw i32 %63, 1
  store i32 %64, ptr @trig_time, align 4, !tbaa !5
  %65 = icmp sgt i32 %63, 178
  br i1 %65, label %66, label %67

66:                                               ; preds = %62
  store i8 0, ptr @triggered, align 1, !tbaa !11
  store i32 0, ptr @trig_time, align 4, !tbaa !5
  br label %67

67:                                               ; preds = %62, %66, %59
  %68 = phi i8 [ %60, %62 ], [ 0, %66 ], [ %60, %59 ]
  %69 = load float, ptr @win_max, align 4, !tbaa !9
  %70 = fcmp ogt float %storemerge, %69
  br i1 %70, label %71, label %72

71:                                               ; preds = %67
  store float %storemerge, ptr @win_max, align 4, !tbaa !9
  br label %72

72:                                               ; preds = %71, %67
  %73 = load float, ptr @treshold, align 4, !tbaa !9
  %74 = fcmp ogt float %storemerge, %73
  br i1 %74, label %75, label %78

75:                                               ; preds = %72
  %76 = trunc nuw i8 %68 to i1
  br i1 %76, label %78, label %77

77:                                               ; preds = %75
  store i32 %3, ptr @last_qrs_point, align 4, !tbaa !5
  store i8 1, ptr @triggered, align 1, !tbaa !11
  br label %93

78:                                               ; preds = %72, %75
  %79 = load i32, ptr @win_idx, align 4, !tbaa !5
  %80 = add nsw i32 %79, 1
  store i32 %80, ptr @win_idx, align 4, !tbaa !5
  %81 = icmp ugt i32 %79, 359
  br i1 %81, label %82, label %93

82:                                               ; preds = %78
  %83 = tail call i32 @rand() #3
  %84 = sitofp i32 %83 to float
  %85 = fmul float %84, 0x3E00000000000000
  %86 = tail call float @llvm.fmuladd.f32(float %85, float 0x3FB70A3D80000000, float 0x3F847AE140000000)
  %87 = fmul float %86, 0x3FC6666680000000
  %88 = load float, ptr @win_max, align 4, !tbaa !9
  %89 = fsub float 1.000000e+00, %86
  %90 = load float, ptr @treshold, align 4, !tbaa !9
  %91 = fmul float %90, %89
  %92 = tail call float @llvm.fmuladd.f32(float %87, float %88, float %91)
  store float %92, ptr @treshold, align 4, !tbaa !9
  store i32 0, ptr @win_idx, align 4, !tbaa !5
  store float -1.000000e+07, ptr @win_max, align 4, !tbaa !9
  br label %93

93:                                               ; preds = %78, %82, %77
  %.0 = phi i1 [ true, %77 ], [ false, %82 ], [ false, %78 ]
  ret i1 %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #1

; Function Attrs: nounwind
declare i32 @rand() local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"float", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_Bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,MergedLoadStoreMotionPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass