; LLVM IR from greensoftwarelab/Energy-Languages :: RAPL (rapl)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@pp1_before = external dso_local global double, align 8
@dram_before = external dso_local global double, align 8
@cpu_model = external dso_local global i32, align 4
@energy_units = external dso_local global double, align 8
@time_units = external dso_local global double, align 8
@package_before = external dso_local global double, align 8
@pp0_before = external dso_local global double, align 8

; Function Attrs: nounwind uwtable
declare dso_local i32 @open_msr(i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local i64 @read_msr(i32 noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @rapl_before(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca double, align 8
  %8 = alloca i32, align 4
  %9 = alloca double, align 8
  %10 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  %11 = load i32, ptr %4, align 4, !tbaa !9
  %12 = call i32 @open_msr(i32 noundef %11)
  store i32 %12, ptr %5, align 4, !tbaa !9
  %13 = load i32, ptr %5, align 4, !tbaa !9
  %14 = call i64 @read_msr(i32 noundef %13, i32 noundef 1553)
  store i64 %14, ptr %6, align 8, !tbaa !11
  %15 = load i64, ptr %6, align 8, !tbaa !11
  %16 = sitofp i64 %15 to double
  %17 = load double, ptr @energy_units, align 8, !tbaa !13
  %18 = fmul double %16, %17
  store double %18, ptr @package_before, align 8, !tbaa !13
  %19 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %20 = icmp eq i32 %19, 45
  br i1 %20, label %24, label %21

21:                                               ; preds = %2
  %22 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %23 = icmp eq i32 %22, 62
  br i1 %23, label %24, label %31

24:                                               ; preds = %21, %2
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = call i64 @read_msr(i32 noundef %25, i32 noundef 1555)
  store i64 %26, ptr %6, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  %27 = load i64, ptr %6, align 8, !tbaa !11
  %28 = sitofp i64 %27 to double
  %29 = load double, ptr @time_units, align 8, !tbaa !13
  %30 = fmul double %28, %29
  store double %30, ptr %7, align 8, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  br label %31

31:                                               ; preds = %24, %21
  %32 = load i32, ptr %5, align 4, !tbaa !9
  %33 = call i64 @read_msr(i32 noundef %32, i32 noundef 1593)
  store i64 %33, ptr %6, align 8, !tbaa !11
  %34 = load i64, ptr %6, align 8, !tbaa !11
  %35 = sitofp i64 %34 to double
  %36 = load double, ptr @energy_units, align 8, !tbaa !13
  %37 = fmul double %35, %36
  store double %37, ptr @pp0_before, align 8, !tbaa !13
  %38 = load i32, ptr %5, align 4, !tbaa !9
  %39 = call i64 @read_msr(i32 noundef %38, i32 noundef 1594)
  store i64 %39, ptr %6, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %40 = load i64, ptr %6, align 8, !tbaa !11
  %41 = trunc i64 %40 to i32
  %42 = and i32 %41, 31
  store i32 %42, ptr %8, align 4, !tbaa !9
  %43 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %44 = icmp eq i32 %43, 45
  br i1 %44, label %48, label %45

45:                                               ; preds = %31
  %46 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %47 = icmp eq i32 %46, 62
  br i1 %47, label %48, label %55

48:                                               ; preds = %45, %31
  %49 = load i32, ptr %5, align 4, !tbaa !9
  %50 = call i64 @read_msr(i32 noundef %49, i32 noundef 1595)
  store i64 %50, ptr %6, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  %51 = load i64, ptr %6, align 8, !tbaa !11
  %52 = sitofp i64 %51 to double
  %53 = load double, ptr @time_units, align 8, !tbaa !13
  %54 = fmul double %52, %53
  store double %54, ptr %9, align 8, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  br label %55

55:                                               ; preds = %48, %45
  %56 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %57 = icmp eq i32 %56, 42
  br i1 %57, label %64, label %58

58:                                               ; preds = %55
  %59 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %60 = icmp eq i32 %59, 58
  br i1 %60, label %64, label %61

61:                                               ; preds = %58
  %62 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 60
  br i1 %63, label %64, label %76

64:                                               ; preds = %61, %58, %55
  %65 = load i32, ptr %5, align 4, !tbaa !9
  %66 = call i64 @read_msr(i32 noundef %65, i32 noundef 1601)
  store i64 %66, ptr %6, align 8, !tbaa !11
  %67 = load i64, ptr %6, align 8, !tbaa !11
  %68 = sitofp i64 %67 to double
  %69 = load double, ptr @energy_units, align 8, !tbaa !13
  %70 = fmul double %68, %69
  store double %70, ptr @pp1_before, align 8, !tbaa !13
  %71 = load i32, ptr %5, align 4, !tbaa !9
  %72 = call i64 @read_msr(i32 noundef %71, i32 noundef 1602)
  store i64 %72, ptr %6, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  %73 = load i64, ptr %6, align 8, !tbaa !11
  %74 = trunc i64 %73 to i32
  %75 = and i32 %74, 31
  store i32 %75, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  br label %76

76:                                               ; preds = %64, %61
  %77 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %78 = icmp eq i32 %77, 45
  br i1 %78, label %85, label %79

79:                                               ; preds = %76
  %80 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %81 = icmp eq i32 %80, 62
  br i1 %81, label %85, label %82

82:                                               ; preds = %79
  %83 = load i32, ptr @cpu_model, align 4, !tbaa !9
  %84 = icmp eq i32 %83, 60
  br i1 %84, label %85, label %92

85:                                               ; preds = %82, %79, %76
  %86 = load i32, ptr %5, align 4, !tbaa !9
  %87 = call i64 @read_msr(i32 noundef %86, i32 noundef 1561)
  store i64 %87, ptr %6, align 8, !tbaa !11
  %88 = load i64, ptr %6, align 8, !tbaa !11
  %89 = sitofp i64 %88 to double
  %90 = load double, ptr @energy_units, align 8, !tbaa !13
  %91 = fmul double %89, %90
  store double %91, ptr @dram_before, align 8, !tbaa !13
  br label %92

92:                                               ; preds = %85, %82
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"double", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@pp1_before = external dso_local local_unnamed_addr global double, align 8
@dram_before = external dso_local local_unnamed_addr global double, align 8
@cpu_model = external dso_local local_unnamed_addr global i32, align 4
@energy_units = external dso_local local_unnamed_addr global double, align 8
@package_before = external dso_local local_unnamed_addr global double, align 8
@pp0_before = external dso_local local_unnamed_addr global double, align 8

; Function Attrs: nounwind uwtable
declare dso_local i32 @open_msr(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @read_msr(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @rapl_before(ptr nocapture noundef readnone %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = tail call i32 @open_msr(i32 noundef %1)
  %4 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1553)
  %5 = sitofp i64 %4 to double
  %6 = load double, ptr @energy_units, align 8, !tbaa !5
  %7 = fmul double %6, %5
  store double %7, ptr @package_before, align 8, !tbaa !5
  %8 = load i32, ptr @cpu_model, align 4
  switch i32 %8, label %11 [
    i32 62, label %9
    i32 45, label %9
  ]

9:                                                ; preds = %2, %2
  %10 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1555)
  br label %11

11:                                               ; preds = %2, %9
  %12 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1593)
  %13 = sitofp i64 %12 to double
  %14 = load double, ptr @energy_units, align 8, !tbaa !5
  %15 = fmul double %14, %13
  store double %15, ptr @pp0_before, align 8, !tbaa !5
  %16 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1594)
  %17 = load i32, ptr @cpu_model, align 4
  switch i32 %17, label %20 [
    i32 62, label %18
    i32 45, label %18
  ]

18:                                               ; preds = %11, %11
  %19 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1595)
  %.pr = load i32, ptr @cpu_model, align 4
  br label %20

20:                                               ; preds = %11, %18
  %21 = phi i32 [ %17, %11 ], [ %.pr, %18 ]
  switch i32 %21, label %28 [
    i32 60, label %22
    i32 58, label %22
    i32 42, label %22
  ]

22:                                               ; preds = %20, %20, %20
  %23 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1601)
  %24 = sitofp i64 %23 to double
  %25 = load double, ptr @energy_units, align 8, !tbaa !5
  %26 = fmul double %25, %24
  store double %26, ptr @pp1_before, align 8, !tbaa !5
  %27 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1602)
  %.pre = load i32, ptr @cpu_model, align 4
  br label %28

28:                                               ; preds = %20, %22
  %29 = phi i32 [ %21, %20 ], [ %.pre, %22 ]
  switch i32 %29, label %35 [
    i32 62, label %30
    i32 60, label %30
    i32 45, label %30
  ]

30:                                               ; preds = %28, %28, %28
  %31 = tail call i64 @read_msr(i32 noundef %3, i32 noundef 1561)
  %32 = sitofp i64 %31 to double
  %33 = load double, ptr @energy_units, align 8, !tbaa !5
  %34 = fmul double %33, %32
  store double %34, ptr @dram_before, align 8, !tbaa !5
  br label %35

35:                                               ; preds = %28, %30
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass