; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (Start)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XDmaPs_Cmd = type { %struct.XDmaPs_ChanCtrl, %struct.XDmaPs_BD, ptr, i32, ptr, i32, i32, i32, i32 }
%struct.XDmaPs_ChanCtrl = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.XDmaPs_BD = type { i32, i32, i32 }
%struct.XDmaPs = type { %struct.XDmaPs_Config, i32, i32, ptr, ptr, [8 x %struct.XDmaPs_ChannelData] }
%struct.XDmaPs_Config = type { i16, i32 }
%struct.XDmaPs_ChannelData = type { i32, i32, [2 x %struct.XDmaPs_ProgBuf], ptr, ptr, ptr, ptr, i32 }
%struct.XDmaPs_ProgBuf = type { [128 x i8], i32, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [161 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XDmaPs_GenDmaProg(ptr noundef, i32 noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @XDmaPs_Start(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  store i32 0, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %18

17:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1464)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %162

18:                                               ; preds = %16
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  %20 = icmp ne ptr %19, null
  br i1 %20, label %21, label %22

21:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %23

22:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1465)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %162

23:                                               ; preds = %21
  %24 = load ptr, ptr %8, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %24, i32 0, i32 6
  store i32 1, ptr %25, align 4, !tbaa !11
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = call i32 @XDmaPs_IsActive(ptr noundef %26, i32 noundef %27)
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %31

30:                                               ; preds = %23
  store i32 21, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %162

31:                                               ; preds = %23
  %32 = load ptr, ptr %8, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %32, i32 0, i32 2
  %34 = load ptr, ptr %33, align 8, !tbaa !15
  %35 = icmp ne ptr %34, null
  br i1 %35, label %50, label %36

36:                                               ; preds = %31
  %37 = load ptr, ptr %8, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %37, i32 0, i32 4
  %39 = load ptr, ptr %38, align 8, !tbaa !16
  %40 = icmp ne ptr %39, null
  br i1 %40, label %50, label %41

41:                                               ; preds = %36
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  %43 = load i32, ptr %7, align 4, !tbaa !9
  %44 = load ptr, ptr %8, align 8, !tbaa !5
  %45 = call i32 @XDmaPs_GenDmaProg(ptr noundef %42, i32 noundef %43, ptr noundef %44)
  store i32 %45, ptr %10, align 4, !tbaa !9
  %46 = load i32, ptr %10, align 4, !tbaa !9
  %47 = icmp ne i32 %46, 0
  br i1 %47, label %48, label %49

48:                                               ; preds = %41
  store i32 1, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %162

49:                                               ; preds = %41
  br label %50

50:                                               ; preds = %49, %36, %31
  %51 = load i32, ptr %9, align 4, !tbaa !9
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.XDmaPs, ptr %52, i32 0, i32 5
  %54 = load i32, ptr %7, align 4, !tbaa !9
  %55 = zext i32 %54 to i64
  %56 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %53, i64 0, i64 %55
  %57 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %56, i32 0, i32 7
  store i32 %51, ptr %57, align 8, !tbaa !17
  %58 = load ptr, ptr %8, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %58, i32 0, i32 2
  %60 = load ptr, ptr %59, align 8, !tbaa !15
  %61 = icmp ne ptr %60, null
  br i1 %61, label %62, label %67

62:                                               ; preds = %50
  %63 = load ptr, ptr %8, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %63, i32 0, i32 2
  %65 = load ptr, ptr %64, align 8, !tbaa !15
  %66 = ptrtoint ptr %65 to i32
  store i32 %66, ptr %11, align 4, !tbaa !9
  br label %78

67:                                               ; preds = %50
  %68 = load ptr, ptr %8, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %68, i32 0, i32 4
  %70 = load ptr, ptr %69, align 8, !tbaa !16
  %71 = icmp ne ptr %70, null
  br i1 %71, label %72, label %77

72:                                               ; preds = %67
  %73 = load ptr, ptr %8, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %73, i32 0, i32 4
  %75 = load ptr, ptr %74, align 8, !tbaa !16
  %76 = ptrtoint ptr %75 to i32
  store i32 %76, ptr %11, align 4, !tbaa !9
  br label %77

77:                                               ; preds = %72, %67
  br label %78

78:                                               ; preds = %77, %62
  %79 = load i32, ptr %11, align 4, !tbaa !9
  %80 = icmp ne i32 %79, 0
  br i1 %80, label %81, label %153

81:                                               ; preds = %78
  %82 = load ptr, ptr %6, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.XDmaPs, ptr %82, i32 0, i32 0
  %84 = getelementptr inbounds %struct.XDmaPs_Config, ptr %83, i32 0, i32 1
  %85 = load i32, ptr %84, align 4, !tbaa !19
  %86 = add i32 %85, 32
  %87 = zext i32 %86 to i64
  %88 = call i32 @Xil_In32(i64 noundef %87)
  store i32 %88, ptr %12, align 4, !tbaa !9
  %89 = load i32, ptr %7, align 4, !tbaa !9
  %90 = shl i32 1, %89
  %91 = load i32, ptr %12, align 4, !tbaa !9
  %92 = or i32 %91, %90
  store i32 %92, ptr %12, align 4, !tbaa !9
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.XDmaPs, ptr %93, i32 0, i32 0
  %95 = getelementptr inbounds %struct.XDmaPs_Config, ptr %94, i32 0, i32 1
  %96 = load i32, ptr %95, align 4, !tbaa !19
  %97 = add i32 %96, 32
  %98 = zext i32 %97 to i64
  %99 = load i32, ptr %12, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %98, i32 noundef %99)
  %100 = load ptr, ptr %6, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.XDmaPs, ptr %100, i32 0, i32 0
  %102 = getelementptr inbounds %struct.XDmaPs_Config, ptr %101, i32 0, i32 1
  %103 = load i32, ptr %102, align 4, !tbaa !19
  %104 = add i32 %103, 32
  %105 = zext i32 %104 to i64
  %106 = call i32 @Xil_In32(i64 noundef %105)
  store i32 %106, ptr %12, align 4, !tbaa !9
  %107 = load ptr, ptr %8, align 8, !tbaa !5
  %108 = load ptr, ptr %6, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.XDmaPs, ptr %108, i32 0, i32 5
  %110 = load i32, ptr %7, align 4, !tbaa !9
  %111 = zext i32 %110 to i64
  %112 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %109, i64 0, i64 %111
  %113 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %112, i32 0, i32 5
  store ptr %107, ptr %113, align 8, !tbaa !23
  %114 = load ptr, ptr %8, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %114, i32 0, i32 0
  %116 = getelementptr inbounds %struct.XDmaPs_ChanCtrl, ptr %115, i32 0, i32 10
  %117 = load i32, ptr %116, align 8, !tbaa !24
  %118 = icmp ne i32 %117, 0
  br i1 %118, label %119, label %129

119:                                              ; preds = %81
  %120 = load ptr, ptr %8, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %120, i32 0, i32 1
  %122 = getelementptr inbounds %struct.XDmaPs_BD, ptr %121, i32 0, i32 0
  %123 = load i32, ptr %122, align 4, !tbaa !25
  %124 = zext i32 %123 to i64
  %125 = load ptr, ptr %8, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %125, i32 0, i32 1
  %127 = getelementptr inbounds %struct.XDmaPs_BD, ptr %126, i32 0, i32 2
  %128 = load i32, ptr %127, align 4, !tbaa !26
  call void @Xil_DCacheFlushRange(i64 noundef %124, i32 noundef %128)
  br label %129

129:                                              ; preds = %119, %81
  %130 = load ptr, ptr %8, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %130, i32 0, i32 0
  %132 = getelementptr inbounds %struct.XDmaPs_ChanCtrl, ptr %131, i32 0, i32 5
  %133 = load i32, ptr %132, align 4, !tbaa !27
  %134 = icmp ne i32 %133, 0
  br i1 %134, label %135, label %145

135:                                              ; preds = %129
  %136 = load ptr, ptr %8, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %136, i32 0, i32 1
  %138 = getelementptr inbounds %struct.XDmaPs_BD, ptr %137, i32 0, i32 1
  %139 = load i32, ptr %138, align 4, !tbaa !28
  %140 = zext i32 %139 to i64
  %141 = load ptr, ptr %8, align 8, !tbaa !5
  %142 = getelementptr inbounds %struct.XDmaPs_Cmd, ptr %141, i32 0, i32 1
  %143 = getelementptr inbounds %struct.XDmaPs_BD, ptr %142, i32 0, i32 2
  %144 = load i32, ptr %143, align 4, !tbaa !26
  call void @Xil_DCacheInvalidateRange(i64 noundef %140, i32 noundef %144)
  br label %145

145:                                              ; preds = %135, %129
  %146 = load ptr, ptr %6, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.XDmaPs, ptr %146, i32 0, i32 0
  %148 = getelementptr inbounds %struct.XDmaPs_Config, ptr %147, i32 0, i32 1
  %149 = load i32, ptr %148, align 4, !tbaa !19
  %150 = load i32, ptr %7, align 4, !tbaa !9
  %151 = load i32, ptr %11, align 4, !tbaa !9
  %152 = call i32 @XDmaPs_Exec_DMAGO(i32 noundef %149, i32 noundef %150, i32 noundef %151)
  store i32 %152, ptr %10, align 4, !tbaa !9
  br label %160

153:                                              ; preds = %78
  %154 = load ptr, ptr %6, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.XDmaPs, ptr %154, i32 0, i32 5
  %156 = load i32, ptr %7, align 4, !tbaa !9
  %157 = zext i32 %156 to i64
  %158 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %155, i64 0, i64 %157
  %159 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %158, i32 0, i32 5
  store ptr null, ptr %159, align 8, !tbaa !23
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %160

160:                                              ; preds = %153, %145
  %161 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %161, ptr %5, align 4
  store i32 1, ptr %13, align 4
  br label %162

162:                                              ; preds = %160, %48, %30, %22, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %163 = load i32, ptr %5, align 4
  ret i32 %163
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @XDmaPs_IsActive(ptr noundef, i32 noundef) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #1

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @XDmaPs_Exec_DMAGO(i32 noundef, i32 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 84}
!12 = !{!"", !13, i64 0, !14, i64 44, !6, i64 56, !10, i64 64, !6, i64 72, !10, i64 80, !10, i64 84, !10, i64 88, !10, i64 92}
!13 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40}
!14 = !{!"", !10, i64 0, !10, i64 4, !10, i64 8}
!15 = !{!12, !6, i64 56}
!16 = !{!12, !6, i64 72}
!17 = !{!18, !10, i64 312}
!18 = !{!"", !10, i64 0, !10, i64 4, !7, i64 8, !6, i64 280, !6, i64 288, !6, i64 296, !6, i64 304, !10, i64 312}
!19 = !{!20, !10, i64 4}
!20 = !{!"", !21, i64 0, !10, i64 8, !10, i64 12, !6, i64 16, !6, i64 24, !7, i64 32}
!21 = !{!"", !22, i64 0, !10, i64 4}
!22 = !{!"short", !7, i64 0}
!23 = !{!18, !6, i64 296}
!24 = !{!12, !10, i64 40}
!25 = !{!12, !10, i64 44}
!26 = !{!12, !10, i64 52}
!27 = !{!12, !10, i64 20}
!28 = !{!12, !10, i64 48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XDmaPs_ChannelData = type { i32, i32, [2 x %struct.XDmaPs_ProgBuf], ptr, ptr, ptr, ptr, i32 }
%struct.XDmaPs_ProgBuf = type { [128 x i8], i32, i32 }

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [161 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @XDmaPs_GenDmaProg(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XDmaPs_Start(ptr noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not46 = icmp eq ptr %2, null
  br i1 %.not46, label %10, label %7

6:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1464) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %75

7:                                                ; preds = %5
  %8 = getelementptr inbounds i8, ptr %2, i64 84
  store i32 1, ptr %8, align 4, !tbaa !9
  %9 = tail call i32 @XDmaPs_IsActive(ptr noundef nonnull %0, i32 noundef %1)
  %.not47 = icmp eq i32 %9, 0
  br i1 %.not47, label %11, label %75

10:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1465) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %75

11:                                               ; preds = %7
  %12 = getelementptr inbounds i8, ptr %2, i64 56
  %13 = load ptr, ptr %12, align 8, !tbaa !14
  %.not48 = icmp eq ptr %13, null
  br i1 %.not48, label %18, label %.thread

.thread:                                          ; preds = %11
  %14 = getelementptr inbounds i8, ptr %0, i64 32
  %15 = zext i32 %1 to i64
  %16 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %14, i64 0, i64 %15
  %17 = getelementptr inbounds i8, ptr %16, i64 312
  store i32 %3, ptr %17, align 8, !tbaa !15
  br label %35

18:                                               ; preds = %11
  %19 = getelementptr inbounds i8, ptr %2, i64 72
  %20 = load ptr, ptr %19, align 8, !tbaa !17
  %.not49 = icmp eq ptr %20, null
  br i1 %.not49, label %25, label %.thread61

.thread61:                                        ; preds = %18
  %21 = getelementptr inbounds i8, ptr %0, i64 32
  %22 = zext i32 %1 to i64
  %23 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %21, i64 0, i64 %22
  %24 = getelementptr inbounds i8, ptr %23, i64 312
  store i32 %3, ptr %24, align 8, !tbaa !15
  br label %32

25:                                               ; preds = %18
  %26 = tail call i32 @XDmaPs_GenDmaProg(ptr noundef nonnull %0, i32 noundef %1, ptr noundef nonnull %2)
  %.not50 = icmp eq i32 %26, 0
  br i1 %.not50, label %27, label %75

27:                                               ; preds = %25
  %.pr.pre = load ptr, ptr %12, align 8, !tbaa !14
  %28 = getelementptr inbounds i8, ptr %0, i64 32
  %29 = zext i32 %1 to i64
  %30 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %28, i64 0, i64 %29
  %31 = getelementptr inbounds i8, ptr %30, i64 312
  store i32 %3, ptr %31, align 8, !tbaa !15
  %.not51 = icmp eq ptr %.pr.pre, null
  br i1 %.not51, label %32, label %35

32:                                               ; preds = %.thread61, %27
  %33 = phi ptr [ %23, %.thread61 ], [ %30, %27 ]
  %34 = load ptr, ptr %19, align 8, !tbaa !17
  %.not52 = icmp eq ptr %34, null
  br i1 %.not52, label %.thread57, label %35

35:                                               ; preds = %32, %27, %.thread
  %36 = phi ptr [ %16, %.thread ], [ %30, %27 ], [ %33, %32 ]
  %.040.in.in = phi ptr [ %13, %.thread ], [ %.pr.pre, %27 ], [ %34, %32 ]
  %.040.in = ptrtoint ptr %.040.in.in to i64
  %.040 = trunc i64 %.040.in to i32
  %.not53 = icmp eq i32 %.040, 0
  br i1 %.not53, label %.thread57, label %37

37:                                               ; preds = %35
  %38 = getelementptr inbounds i8, ptr %0, i64 4
  %39 = load i32, ptr %38, align 4, !tbaa !18
  %40 = add i32 %39, 32
  %41 = zext i32 %40 to i64
  %42 = tail call i32 @Xil_In32(i64 noundef %41)
  %43 = shl nuw i32 1, %1
  %44 = or i32 %42, %43
  %45 = load i32, ptr %38, align 4, !tbaa !18
  %46 = add i32 %45, 32
  %47 = zext i32 %46 to i64
  tail call void @Xil_Out32(i64 noundef %47, i32 noundef %44)
  %48 = load i32, ptr %38, align 4, !tbaa !18
  %49 = add i32 %48, 32
  %50 = zext i32 %49 to i64
  %51 = tail call i32 @Xil_In32(i64 noundef %50)
  %52 = getelementptr inbounds i8, ptr %36, i64 296
  store ptr %2, ptr %52, align 8, !tbaa !22
  %53 = getelementptr inbounds i8, ptr %2, i64 40
  %54 = load i32, ptr %53, align 8, !tbaa !23
  %.not54 = icmp eq i32 %54, 0
  br i1 %.not54, label %61, label %55

55:                                               ; preds = %37
  %56 = getelementptr inbounds i8, ptr %2, i64 44
  %57 = load i32, ptr %56, align 4, !tbaa !24
  %58 = zext i32 %57 to i64
  %59 = getelementptr inbounds i8, ptr %2, i64 52
  %60 = load i32, ptr %59, align 4, !tbaa !25
  tail call void @Xil_DCacheFlushRange(i64 noundef %58, i32 noundef %60) #3
  br label %61

61:                                               ; preds = %55, %37
  %62 = getelementptr inbounds i8, ptr %2, i64 20
  %63 = load i32, ptr %62, align 4, !tbaa !26
  %.not55 = icmp eq i32 %63, 0
  br i1 %.not55, label %70, label %64

64:                                               ; preds = %61
  %65 = getelementptr inbounds i8, ptr %2, i64 48
  %66 = load i32, ptr %65, align 4, !tbaa !27
  %67 = zext i32 %66 to i64
  %68 = getelementptr inbounds i8, ptr %2, i64 52
  %69 = load i32, ptr %68, align 4, !tbaa !25
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %67, i32 noundef %69) #3
  br label %70

70:                                               ; preds = %64, %61
  %71 = load i32, ptr %38, align 4, !tbaa !18
  %72 = tail call i32 @XDmaPs_Exec_DMAGO(i32 noundef %71, i32 noundef %1, i32 noundef %.040)
  br label %75

.thread57:                                        ; preds = %32, %35
  %73 = phi ptr [ %36, %35 ], [ %33, %32 ]
  %74 = getelementptr inbounds i8, ptr %73, i64 296
  store ptr null, ptr %74, align 8, !tbaa !22
  br label %75

75:                                               ; preds = %70, %.thread57, %25, %7, %10, %6
  %.0 = phi i32 [ 0, %10 ], [ 0, %6 ], [ 21, %7 ], [ 1, %25 ], [ %72, %70 ], [ 1, %.thread57 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @XDmaPs_IsActive(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #0

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @XDmaPs_Exec_DMAGO(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 84}
!10 = !{!"", !11, i64 0, !12, i64 44, !13, i64 56, !6, i64 64, !13, i64 72, !6, i64 80, !6, i64 84, !6, i64 88, !6, i64 92}
!11 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !6, i64 32, !6, i64 36, !6, i64 40}
!12 = !{!"", !6, i64 0, !6, i64 4, !6, i64 8}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !13, i64 56}
!15 = !{!16, !6, i64 312}
!16 = !{!"", !6, i64 0, !6, i64 4, !7, i64 8, !13, i64 280, !13, i64 288, !13, i64 296, !13, i64 304, !6, i64 312}
!17 = !{!10, !13, i64 72}
!18 = !{!19, !6, i64 4}
!19 = !{!"", !20, i64 0, !6, i64 8, !6, i64 12, !13, i64 16, !13, i64 24, !7, i64 32}
!20 = !{!"", !21, i64 0, !6, i64 4}
!21 = !{!"short", !7, i64 0}
!22 = !{!16, !13, i64 296}
!23 = !{!10, !6, i64 40}
!24 = !{!10, !6, i64 44}
!25 = !{!10, !6, i64 52}
!26 = !{!10, !6, i64 20}
!27 = !{!10, !6, i64 48}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass