; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (L1DCacheFlush)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L1DCacheFlush() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !5
  %16 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  store i32 %16, ptr %12, align 4, !tbaa !5
  %17 = load i32, ptr %12, align 4, !tbaa !5
  store i32 %17, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  %18 = load i32, ptr %13, align 4, !tbaa !5
  store i32 %18, ptr %11, align 4, !tbaa !5
  %19 = load i32, ptr %11, align 4, !tbaa !5
  %20 = or i32 %19, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %20) #2, !srcloc !10
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #2, !srcloc !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  store i32 0, ptr %14, align 4, !tbaa !5
  %21 = call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !12
  store i32 %21, ptr %14, align 4, !tbaa !5
  %22 = load i32, ptr %14, align 4, !tbaa !5
  store i32 %22, ptr %15, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  %23 = load i32, ptr %15, align 4, !tbaa !5
  store i32 %23, ptr %1, align 4, !tbaa !5
  %24 = load i32, ptr %1, align 4, !tbaa !5
  %25 = lshr i32 %24, 13
  %26 = and i32 %25, 511
  store i32 %26, ptr %3, align 4, !tbaa !5
  %27 = load i32, ptr %3, align 4, !tbaa !5
  %28 = add i32 %27, 1
  store i32 %28, ptr %3, align 4, !tbaa !5
  %29 = load i32, ptr %3, align 4, !tbaa !5
  %30 = mul i32 %29, 128
  store i32 %30, ptr %3, align 4, !tbaa !5
  %31 = load i32, ptr %1, align 4, !tbaa !5
  %32 = and i32 %31, 1023
  %33 = lshr i32 %32, 3
  store i32 %33, ptr %5, align 4, !tbaa !5
  %34 = load i32, ptr %5, align 4, !tbaa !5
  %35 = add i32 %34, 1
  store i32 %35, ptr %5, align 4, !tbaa !5
  %36 = load i32, ptr %1, align 4, !tbaa !5
  %37 = and i32 %36, 7
  %38 = add i32 %37, 4
  store i32 %38, ptr %4, align 4, !tbaa !5
  %39 = load i32, ptr %3, align 4, !tbaa !5
  %40 = load i32, ptr %5, align 4, !tbaa !5
  %41 = udiv i32 %39, %40
  store i32 %41, ptr %10, align 4, !tbaa !5
  %42 = load i32, ptr %4, align 4, !tbaa !5
  %43 = shl i32 1, %42
  %44 = load i32, ptr %10, align 4, !tbaa !5
  %45 = udiv i32 %44, %43
  store i32 %45, ptr %10, align 4, !tbaa !5
  store i32 0, ptr %6, align 4, !tbaa !5
  store i32 0, ptr %8, align 4, !tbaa !5
  store i32 0, ptr %7, align 4, !tbaa !5
  br label %46

46:                                               ; preds = %70, %0
  %47 = load i32, ptr %7, align 4, !tbaa !5
  %48 = load i32, ptr %5, align 4, !tbaa !5
  %49 = icmp ult i32 %47, %48
  br i1 %49, label %50, label %73

50:                                               ; preds = %46
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %51

51:                                               ; preds = %64, %50
  %52 = load i32, ptr %9, align 4, !tbaa !5
  %53 = load i32, ptr %10, align 4, !tbaa !5
  %54 = icmp ult i32 %52, %53
  br i1 %54, label %55, label %67

55:                                               ; preds = %51
  %56 = load i32, ptr %6, align 4, !tbaa !5
  %57 = load i32, ptr %8, align 4, !tbaa !5
  %58 = or i32 %56, %57
  store i32 %58, ptr %2, align 4, !tbaa !5
  %59 = load i32, ptr %2, align 4, !tbaa !5
  call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 2", "r,~{dirflag},~{fpsr},~{flags}"(i32 %59) #2, !srcloc !13
  %60 = load i32, ptr %4, align 4, !tbaa !5
  %61 = shl i32 1, %60
  %62 = load i32, ptr %8, align 4, !tbaa !5
  %63 = add i32 %62, %61
  store i32 %63, ptr %8, align 4, !tbaa !5
  br label %64

64:                                               ; preds = %55
  %65 = load i32, ptr %9, align 4, !tbaa !5
  %66 = add i32 %65, 1
  store i32 %66, ptr %9, align 4, !tbaa !5
  br label %51, !llvm.loop !14

67:                                               ; preds = %51
  store i32 0, ptr %8, align 4, !tbaa !5
  %68 = load i32, ptr %6, align 4, !tbaa !5
  %69 = add i32 %68, 1073741824
  store i32 %69, ptr %6, align 4, !tbaa !5
  br label %70

70:                                               ; preds = %67
  %71 = load i32, ptr %7, align 4, !tbaa !5
  %72 = add i32 %71, 1
  store i32 %72, ptr %7, align 4, !tbaa !5
  br label %46, !llvm.loop !16

73:                                               ; preds = %46
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !17
  %74 = load i32, ptr %11, align 4, !tbaa !5
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %74) #2, !srcloc !18
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 2147864986}
!10 = !{i64 2147865082}
!11 = !{i64 2147865172}
!12 = !{i64 2147865317}
!13 = !{i64 2147865453}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}
!17 = !{i64 2147865569}
!18 = !{i64 2147865619}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @Xil_L1DCacheFlush() local_unnamed_addr #0 {
  %1 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !5
  %2 = or i32 %1, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %2) #1, !srcloc !6
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #1, !srcloc !7
  %3 = tail call i32 asm sideeffect "mrc p15, 1, $0,  c0,  c0, 0\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !8
  %4 = lshr i32 %3, 6
  %5 = and i32 %4, 65408
  %6 = add nuw nsw i32 %5, 128
  %7 = lshr i32 %3, 3
  %8 = and i32 %7, 127
  %9 = add nuw nsw i32 %8, 1
  %10 = and i32 %3, 7
  %11 = udiv i32 %6, %9
  %12 = shl nuw nsw i32 16, %10
  %13 = add nuw nsw i32 %10, 4
  %14 = lshr i32 %11, %13
  %.not37 = icmp eq i32 %14, 0
  br i1 %.not37, label %.split36.us, label %.preheader.us

.preheader.us:                                    ; preds = %0, %._crit_edge.us
  %.034.us = phi i32 [ %19, %._crit_edge.us ], [ 0, %0 ]
  %.02833.us = phi i32 [ %20, %._crit_edge.us ], [ 0, %0 ]
  br label %15

15:                                               ; preds = %.preheader.us, %15
  %.132.us = phi i32 [ 0, %.preheader.us ], [ %17, %15 ]
  %.03031.us = phi i32 [ 0, %.preheader.us ], [ %18, %15 ]
  %16 = or i32 %.132.us, %.034.us
  tail call void asm sideeffect "mcr p15, 0, $0,  c7, c14, 2", "r,~{dirflag},~{fpsr},~{flags}"(i32 %16) #1, !srcloc !9
  %17 = add nuw nsw i32 %.132.us, %12
  %18 = add nuw nsw i32 %.03031.us, 1
  %exitcond.not = icmp eq i32 %18, %14
  br i1 %exitcond.not, label %._crit_edge.us, label %15, !llvm.loop !10

._crit_edge.us:                                   ; preds = %15
  %19 = add i32 %.034.us, 1073741824
  %20 = add nuw nsw i32 %.02833.us, 1
  %exitcond39.not = icmp eq i32 %.02833.us, %8
  br i1 %exitcond39.not, label %.split36.us, label %.preheader.us, !llvm.loop !12

.split36.us:                                      ; preds = %._crit_edge.us, %0
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !13
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %1) #1, !srcloc !14
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147864986}
!6 = !{i64 2147865082}
!7 = !{i64 2147865172}
!8 = !{i64 2147865317}
!9 = !{i64 2147865453}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}
!13 = !{i64 2147865569}
!14 = !{i64 2147865619}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass