; LLVM IR from lesialin/ImageSignalProcessing_C :: src/isp_eeh.ll (Z15create_edge_mapPhPa)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.isp_config_t = type <{ i32, i32, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.blc_cfg_t, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.awb_gain_t, [12 x float], %"class.std::__cxx11::basic_string", float, [12 x float], %struct.nlm_cfg_t, i8, %struct.bnf_cfg_t, [15 x i16], %struct.eeh_cfg_t, %struct.fcs_cfg_t, %struct.hsc_cfg_t, %struct.bcc_cfg_t, [4 x i8] }>
%struct.blc_cfg_t = type { i16, i16, i16, i16, float, float }
%struct.awb_gain_t = type { float, float, float, float }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%struct.nlm_cfg_t = type { i8, i8, i8 }
%struct.bnf_cfg_t = type { [25 x i16], [4 x i16], [3 x i16] }
%struct.eeh_cfg_t = type { i16, i16, i16, i16, i16, i16 }
%struct.fcs_cfg_t = type { i8, i8 }
%struct.hsc_cfg_t = type { i8, float }
%struct.bcc_cfg_t = type { i8, float }

@g_isp_config = external global %struct.isp_config_t, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z15create_edge_mapPhPa(ptr noundef %0, ptr noundef %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 3, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 5, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %17 = load i32, ptr %5, align 4, !tbaa !9
  %18 = ashr i32 %17, 1
  store i32 %18, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %19 = load i32, ptr %6, align 4, !tbaa !9
  %20 = ashr i32 %19, 1
  store i32 %20, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %107, %2
  %22 = load i32, ptr %12, align 4, !tbaa !9
  %23 = load i32, ptr getelementptr inbounds (%struct.isp_config_t, ptr @g_isp_config, i32 0, i32 1), align 4, !tbaa !11
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = sub i32 %23, %24
  %26 = icmp ult i32 %22, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %21
  store i32 2, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %110

28:                                               ; preds = %21
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %103, %28
  %30 = load i32, ptr %14, align 4, !tbaa !9
  %31 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = sub i32 %31, %32
  %34 = icmp ult i32 %30, %33
  br i1 %34, label %36, label %35

35:                                               ; preds = %29
  store i32 5, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  br label %106

36:                                               ; preds = %29
  store i16 0, ptr %10, align 2, !tbaa !27
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  store i32 0, ptr %15, align 4, !tbaa !9
  br label %37

37:                                               ; preds = %82, %36
  %38 = load i32, ptr %15, align 4, !tbaa !9
  %39 = load i32, ptr %5, align 4, !tbaa !9
  %40 = icmp slt i32 %38, %39
  br i1 %40, label %42, label %41

41:                                               ; preds = %37
  store i32 8, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  br label %85

42:                                               ; preds = %37
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %43

43:                                               ; preds = %78, %42
  %44 = load i32, ptr %16, align 4, !tbaa !9
  %45 = load i32, ptr %6, align 4, !tbaa !9
  %46 = icmp slt i32 %44, %45
  br i1 %46, label %48, label %47

47:                                               ; preds = %43
  store i32 11, ptr %13, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  br label %81

48:                                               ; preds = %43
  %49 = load i32, ptr %15, align 4, !tbaa !9
  %50 = load i32, ptr %6, align 4, !tbaa !9
  %51 = mul nsw i32 %49, %50
  %52 = load i32, ptr %16, align 4, !tbaa !9
  %53 = add nsw i32 %51, %52
  %54 = sext i32 %53 to i64
  %55 = getelementptr inbounds [15 x i16], ptr getelementptr inbounds (%struct.isp_config_t, ptr @g_isp_config, i32 0, i32 17), i64 0, i64 %54
  %56 = load i16, ptr %55, align 2, !tbaa !27
  %57 = sext i16 %56 to i32
  %58 = load ptr, ptr %3, align 8, !tbaa !5
  %59 = load i32, ptr %12, align 4, !tbaa !9
  %60 = load i32, ptr %15, align 4, !tbaa !9
  %61 = add nsw i32 %59, %60
  %62 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %63 = mul i32 %61, %62
  %64 = load i32, ptr %14, align 4, !tbaa !9
  %65 = load i32, ptr %16, align 4, !tbaa !9
  %66 = add nsw i32 %64, %65
  %67 = add i32 %63, %66
  %68 = zext i32 %67 to i64
  %69 = getelementptr inbounds i8, ptr %58, i64 %68
  %70 = load i8, ptr %69, align 1, !tbaa !28
  %71 = zext i8 %70 to i16
  %72 = sext i16 %71 to i32
  %73 = mul nsw i32 %57, %72
  %74 = load i16, ptr %10, align 2, !tbaa !27
  %75 = sext i16 %74 to i32
  %76 = add nsw i32 %75, %73
  %77 = trunc i32 %76 to i16
  store i16 %77, ptr %10, align 2, !tbaa !27
  br label %78

78:                                               ; preds = %48
  %79 = load i32, ptr %16, align 4, !tbaa !9
  %80 = add nsw i32 %79, 1
  store i32 %80, ptr %16, align 4, !tbaa !9
  br label %43, !llvm.loop !29

81:                                               ; preds = %47
  br label %82

82:                                               ; preds = %81
  %83 = load i32, ptr %15, align 4, !tbaa !9
  %84 = add nsw i32 %83, 1
  store i32 %84, ptr %15, align 4, !tbaa !9
  br label %37, !llvm.loop !31

85:                                               ; preds = %41
  %86 = load i16, ptr %10, align 2, !tbaa !27
  %87 = sext i16 %86 to i32
  %88 = ashr i32 %87, 3
  %89 = trunc i32 %88 to i8
  store i8 %89, ptr %11, align 1, !tbaa !28
  %90 = load i8, ptr %11, align 1, !tbaa !28
  %91 = load ptr, ptr %4, align 8, !tbaa !5
  %92 = load i32, ptr %12, align 4, !tbaa !9
  %93 = load i32, ptr %7, align 4, !tbaa !9
  %94 = add nsw i32 %92, %93
  %95 = load i32, ptr @g_isp_config, align 8, !tbaa !26
  %96 = mul i32 %94, %95
  %97 = load i32, ptr %14, align 4, !tbaa !9
  %98 = load i32, ptr %8, align 4, !tbaa !9
  %99 = add nsw i32 %97, %98
  %100 = add i32 %96, %99
  %101 = zext i32 %100 to i64
  %102 = getelementptr inbounds i8, ptr %91, i64 %101
  store i8 %90, ptr %102, align 1, !tbaa !28
  br label %103

103:                                              ; preds = %85
  %104 = load i32, ptr %14, align 4, !tbaa !9
  %105 = add nsw i32 %104, 1
  store i32 %105, ptr %14, align 4, !tbaa !9
  br label %29, !llvm.loop !32

106:                                              ; preds = %35
  br label %107

107:                                              ; preds = %106
  %108 = load i32, ptr %12, align 4, !tbaa !9
  %109 = add nsw i32 %108, 1
  store i32 %109, ptr %12, align 4, !tbaa !9
  br label %21, !llvm.loop !33

110:                                              ; preds = %27
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"_ZTS12isp_config_t", !10, i64 0, !10, i64 4, !13, i64 8, !14, i64 16, !17, i64 48, !13, i64 64, !14, i64 72, !19, i64 104, !7, i64 120, !14, i64 168, !18, i64 200, !7, i64 204, !20, i64 252, !21, i64 256, !7, i64 320, !22, i64 350, !23, i64 362, !24, i64 364, !25, i64 372}
!13 = !{!"short", !7, i64 0}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !15, i64 0, !16, i64 8, !7, i64 16}
!15 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!16 = !{!"long", !7, i64 0}
!17 = !{!"_ZTS9blc_cfg_t", !13, i64 0, !13, i64 2, !13, i64 4, !13, i64 6, !18, i64 8, !18, i64 12}
!18 = !{!"float", !7, i64 0}
!19 = !{!"_ZTS10awb_gain_t", !18, i64 0, !18, i64 4, !18, i64 8, !18, i64 12}
!20 = !{!"_ZTS9nlm_cfg_t", !7, i64 0, !7, i64 1, !7, i64 2}
!21 = !{!"_ZTS9bnf_cfg_t", !7, i64 0, !7, i64 50, !7, i64 58}
!22 = !{!"_ZTS9eeh_cfg_t", !13, i64 0, !13, i64 2, !13, i64 4, !13, i64 6, !13, i64 8, !13, i64 10}
!23 = !{!"_ZTS9fcs_cfg_t", !7, i64 0, !7, i64 1}
!24 = !{!"_ZTS9hsc_cfg_t", !7, i64 0, !18, i64 4}
!25 = !{!"_ZTS9bcc_cfg_t", !7, i64 0, !18, i64 4}
!26 = !{!12, !10, i64 0}
!27 = !{!13, !13, i64 0}
!28 = !{!7, !7, i64 0}
!29 = distinct !{!29, !30}
!30 = !{!"llvm.loop.mustprogress"}
!31 = distinct !{!31, !30}
!32 = distinct !{!32, !30}
!33 = distinct !{!33, !30}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.isp_config_t = type <{ i32, i32, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.blc_cfg_t, i16, [6 x i8], %"class.std::__cxx11::basic_string", %struct.awb_gain_t, [12 x float], %"class.std::__cxx11::basic_string", float, [12 x float], %struct.nlm_cfg_t, i8, %struct.bnf_cfg_t, [15 x i16], %struct.eeh_cfg_t, %struct.fcs_cfg_t, %struct.hsc_cfg_t, %struct.bcc_cfg_t, [4 x i8] }>
%struct.blc_cfg_t = type { i16, i16, i16, i16, float, float }
%struct.awb_gain_t = type { float, float, float, float }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%struct.nlm_cfg_t = type { i8, i8, i8 }
%struct.bnf_cfg_t = type { [25 x i16], [4 x i16], [3 x i16] }
%struct.eeh_cfg_t = type { i16, i16, i16, i16, i16, i16 }
%struct.fcs_cfg_t = type { i8, i8 }
%struct.hsc_cfg_t = type { i8, float }
%struct.bcc_cfg_t = type { i8, float }

@g_isp_config = external local_unnamed_addr global %struct.isp_config_t, align 8

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable
define dso_local void @_Z15create_edge_mapPhPa(ptr nocapture noundef readonly %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = load i32, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 4), align 4, !tbaa !5
  %.not = icmp eq i32 %3, 3
  br i1 %.not, label %._crit_edge41, label %.preheader34.preheader

.preheader34.preheader:                           ; preds = %2
  %.pre = load i32, ptr @g_isp_config, align 8, !tbaa !24
  br label %.preheader34

.preheader34:                                     ; preds = %.preheader34.preheader, %._crit_edge
  %4 = phi i32 [ %3, %.preheader34.preheader ], [ %113, %._crit_edge ]
  %5 = phi i32 [ %.pre, %.preheader34.preheader ], [ %114, %._crit_edge ]
  %indvars.iv = phi i64 [ 0, %.preheader34.preheader ], [ %.pre45, %._crit_edge ]
  %.not42 = icmp eq i32 %5, 5
  %.pre45 = add nuw nsw i64 %indvars.iv, 1
  br i1 %.not42, label %._crit_edge, label %.preheader33.lr.ph

.preheader33.lr.ph:                               ; preds = %.preheader34
  %6 = trunc nuw nsw i64 %indvars.iv to i32
  %7 = trunc nuw nsw i64 %.pre45 to i32
  %8 = trunc i64 %indvars.iv to i32
  %9 = add i32 %8, 2
  br label %.preheader33

._crit_edge41:                                    ; preds = %._crit_edge, %2
  ret void

.preheader33:                                     ; preds = %.preheader33.lr.ph, %.preheader33
  %10 = phi i32 [ %5, %.preheader33.lr.ph ], [ %110, %.preheader33 ]
  %.03039 = phi i32 [ 0, %.preheader33.lr.ph ], [ %109, %.preheader33 ]
  %11 = mul i32 %10, %6
  %12 = add i32 %11, %.03039
  %13 = zext i32 %12 to i64
  %14 = getelementptr inbounds i8, ptr %0, i64 %13
  %15 = load i8, ptr %14, align 1, !tbaa !25
  %16 = add i32 %12, 1
  %17 = zext i32 %16 to i64
  %18 = getelementptr inbounds i8, ptr %0, i64 %17
  %19 = load i8, ptr %18, align 1, !tbaa !25
  %20 = add i32 %12, 2
  %21 = zext i32 %20 to i64
  %22 = getelementptr inbounds i8, ptr %0, i64 %21
  %23 = load i8, ptr %22, align 1, !tbaa !25
  %24 = add i32 %12, 3
  %25 = zext i32 %24 to i64
  %26 = getelementptr inbounds i8, ptr %0, i64 %25
  %27 = load i8, ptr %26, align 1, !tbaa !25
  %28 = add i32 %12, 4
  %29 = zext i32 %28 to i64
  %30 = getelementptr inbounds i8, ptr %0, i64 %29
  %31 = load i8, ptr %30, align 1, !tbaa !25
  %32 = mul i32 %10, %7
  %33 = add i32 %32, %.03039
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds i8, ptr %0, i64 %34
  %36 = load i8, ptr %35, align 1, !tbaa !25
  %37 = add i32 %33, 1
  %38 = zext i32 %37 to i64
  %39 = getelementptr inbounds i8, ptr %0, i64 %38
  %40 = load i8, ptr %39, align 1, !tbaa !25
  %41 = add i32 %33, 2
  %42 = zext i32 %41 to i64
  %43 = getelementptr inbounds i8, ptr %0, i64 %42
  %44 = load i8, ptr %43, align 1, !tbaa !25
  %45 = load <8 x i16>, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 320), align 8, !tbaa !26
  %46 = insertelement <8 x i8> poison, i8 %15, i64 0
  %47 = insertelement <8 x i8> %46, i8 %19, i64 1
  %48 = insertelement <8 x i8> %47, i8 %23, i64 2
  %49 = insertelement <8 x i8> %48, i8 %27, i64 3
  %50 = insertelement <8 x i8> %49, i8 %31, i64 4
  %51 = insertelement <8 x i8> %50, i8 %36, i64 5
  %52 = insertelement <8 x i8> %51, i8 %40, i64 6
  %53 = insertelement <8 x i8> %52, i8 %44, i64 7
  %54 = zext <8 x i8> %53 to <8 x i16>
  %55 = mul <8 x i16> %45, %54
  %56 = add i32 %33, 3
  %57 = zext i32 %56 to i64
  %58 = getelementptr inbounds i8, ptr %0, i64 %57
  %59 = load i8, ptr %58, align 1, !tbaa !25
  %60 = add i32 %33, 4
  %61 = zext i32 %60 to i64
  %62 = getelementptr inbounds i8, ptr %0, i64 %61
  %63 = load i8, ptr %62, align 1, !tbaa !25
  %64 = mul i32 %9, %10
  %65 = add i32 %64, %.03039
  %66 = zext i32 %65 to i64
  %67 = getelementptr inbounds i8, ptr %0, i64 %66
  %68 = load i8, ptr %67, align 1, !tbaa !25
  %69 = add i32 %65, 1
  %70 = zext i32 %69 to i64
  %71 = getelementptr inbounds i8, ptr %0, i64 %70
  %72 = load i8, ptr %71, align 1, !tbaa !25
  %73 = load <4 x i16>, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 336), align 8, !tbaa !26
  %74 = insertelement <4 x i8> poison, i8 %59, i64 0
  %75 = insertelement <4 x i8> %74, i8 %63, i64 1
  %76 = insertelement <4 x i8> %75, i8 %68, i64 2
  %77 = insertelement <4 x i8> %76, i8 %72, i64 3
  %78 = zext <4 x i8> %77 to <4 x i16>
  %79 = mul <4 x i16> %73, %78
  %80 = load i16, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 344), align 8, !tbaa !26
  %81 = add i32 %65, 2
  %82 = zext i32 %81 to i64
  %83 = getelementptr inbounds i8, ptr %0, i64 %82
  %84 = load i8, ptr %83, align 1, !tbaa !25
  %85 = zext i8 %84 to i16
  %86 = mul i16 %80, %85
  %87 = load i16, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 346), align 2, !tbaa !26
  %88 = add i32 %65, 3
  %89 = zext i32 %88 to i64
  %90 = getelementptr inbounds i8, ptr %0, i64 %89
  %91 = load i8, ptr %90, align 1, !tbaa !25
  %92 = zext i8 %91 to i16
  %93 = mul i16 %87, %92
  %94 = load i16, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 348), align 4, !tbaa !26
  %95 = add i32 %65, 4
  %96 = zext i32 %95 to i64
  %97 = getelementptr inbounds i8, ptr %0, i64 %96
  %98 = load i8, ptr %97, align 1, !tbaa !25
  %99 = zext i8 %98 to i16
  %100 = mul i16 %94, %99
  %101 = tail call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %55)
  %102 = tail call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %79)
  %op.rdx = add i16 %101, %102
  %op.rdx46 = add i16 %op.rdx, %86
  %op.rdx47 = add i16 %93, %100
  %op.rdx48 = add i16 %op.rdx46, %op.rdx47
  %103 = lshr i16 %op.rdx48, 3
  %104 = trunc i16 %103 to i8
  %105 = add nuw nsw i32 %.03039, 2
  %106 = add i32 %105, %32
  %107 = zext i32 %106 to i64
  %108 = getelementptr inbounds i8, ptr %1, i64 %107
  store i8 %104, ptr %108, align 1, !tbaa !25
  %109 = add nuw nsw i32 %.03039, 1
  %110 = load i32, ptr @g_isp_config, align 8, !tbaa !24
  %111 = add i32 %110, -5
  %112 = icmp ult i32 %109, %111
  br i1 %112, label %.preheader33, label %._crit_edge.loopexit, !llvm.loop !27

._crit_edge.loopexit:                             ; preds = %.preheader33
  %.pre44 = load i32, ptr getelementptr inbounds (i8, ptr @g_isp_config, i64 4), align 4, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %.preheader34, %._crit_edge.loopexit
  %113 = phi i32 [ %.pre44, %._crit_edge.loopexit ], [ %4, %.preheader34 ]
  %114 = phi i32 [ %110, %._crit_edge.loopexit ], [ 5, %.preheader34 ]
  %115 = add i32 %113, -3
  %116 = zext i32 %115 to i64
  %117 = icmp ult i64 %.pre45, %116
  br i1 %117, label %.preheader34, label %._crit_edge41, !llvm.loop !29
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTS12isp_config_t", !7, i64 0, !7, i64 4, !10, i64 8, !11, i64 16, !15, i64 48, !10, i64 64, !11, i64 72, !17, i64 104, !8, i64 120, !11, i64 168, !16, i64 200, !8, i64 204, !18, i64 252, !19, i64 256, !8, i64 320, !20, i64 350, !21, i64 362, !22, i64 364, !23, i64 372}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"short", !8, i64 0}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !14, i64 8, !8, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!13 = !{!"any pointer", !8, i64 0}
!14 = !{!"long", !8, i64 0}
!15 = !{!"_ZTS9blc_cfg_t", !10, i64 0, !10, i64 2, !10, i64 4, !10, i64 6, !16, i64 8, !16, i64 12}
!16 = !{!"float", !8, i64 0}
!17 = !{!"_ZTS10awb_gain_t", !16, i64 0, !16, i64 4, !16, i64 8, !16, i64 12}
!18 = !{!"_ZTS9nlm_cfg_t", !8, i64 0, !8, i64 1, !8, i64 2}
!19 = !{!"_ZTS9bnf_cfg_t", !8, i64 0, !8, i64 50, !8, i64 58}
!20 = !{!"_ZTS9eeh_cfg_t", !10, i64 0, !10, i64 2, !10, i64 4, !10, i64 6, !10, i64 8, !10, i64 10}
!21 = !{!"_ZTS9fcs_cfg_t", !8, i64 0, !8, i64 1}
!22 = !{!"_ZTS9hsc_cfg_t", !8, i64 0, !16, i64 4}
!23 = !{!"_ZTS9bcc_cfg_t", !8, i64 0, !16, i64 4}
!24 = !{!6, !7, i64 0}
!25 = !{!8, !8, i64 0}
!26 = !{!10, !10, i64 0}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = distinct !{!29, !28}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass