; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000/src/ARINC653_PORT (interrupt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }

@INTERRUPT_VECTORTABLE = external dso_local global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @SPINLOCK_LOCK(ptr noundef) #1

declare i32 @CP15CoreIDGet() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @SPINLOCK_UNLOCK(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @INTERRUPT_REGISTER(i32 noundef %0, ptr noundef %1) #2 {
  %3 = alloca i8, align 1
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @SPINLOCK_LOCK(ptr noundef @INTERRUPT_SPINLOCK)
  %8 = call i32 @CP15CoreIDGet()
  store i32 %8, ptr %6, align 4, !tbaa !5
  %9 = load i32, ptr %6, align 4, !tbaa !5
  %10 = icmp uge i32 %9, 2
  br i1 %10, label %11, label %12

11:                                               ; preds = %2
  br label %29

12:                                               ; preds = %2
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = icmp uge i32 %13, 95
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  br label %29

16:                                               ; preds = %12
  %17 = load ptr, ptr %5, align 8, !tbaa !9
  %18 = load i32, ptr %6, align 4, !tbaa !5
  %19 = zext i32 %18 to i64
  %20 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %19
  %21 = load ptr, ptr %20, align 8, !tbaa !9
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = zext i32 %22 to i64
  %24 = getelementptr inbounds ptr, ptr %21, i64 %23
  store ptr %17, ptr %24, align 8, !tbaa !9
  %25 = load i32, ptr %6, align 4, !tbaa !5
  %26 = zext i32 %25 to i64
  %27 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %26
  %28 = load i32, ptr %4, align 4, !tbaa !5
  call void @XScuGic_Enable(ptr noundef %27, i32 noundef %28)
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 1, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %30

29:                                               ; preds = %15, %11
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 0, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %30

30:                                               ; preds = %29, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %31 = load i8, ptr %3, align 1
  ret i8 %31
}

declare void @XScuGic_Enable(ptr noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }

@INTERRUPT_VECTORTABLE = external dso_local local_unnamed_addr global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

declare void @SPINLOCK_LOCK(ptr noundef) local_unnamed_addr #0

declare i32 @CP15CoreIDGet() local_unnamed_addr #0

declare void @SPINLOCK_UNLOCK(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @INTERRUPT_REGISTER(i32 noundef %0, ptr noundef %1) local_unnamed_addr #1 {
  tail call void @SPINLOCK_LOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  %3 = tail call i32 @CP15CoreIDGet() #2
  %4 = icmp ugt i32 %3, 1
  %5 = icmp ugt i32 %0, 94
  %or.cond = or i1 %5, %4
  br i1 %or.cond, label %13, label %6

6:                                                ; preds = %2
  %7 = zext nneg i32 %3 to i64
  %8 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %7
  %9 = load ptr, ptr %8, align 8, !tbaa !5
  %10 = zext nneg i32 %0 to i64
  %11 = getelementptr inbounds ptr, ptr %9, i64 %10
  store ptr %1, ptr %11, align 8, !tbaa !5
  %12 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %7
  tail call void @XScuGic_Enable(ptr noundef nonnull %12, i32 noundef %0) #2
  br label %13

13:                                               ; preds = %2, %6
  %.0 = phi i8 [ 1, %6 ], [ 0, %2 ]
  tail call void @SPINLOCK_UNLOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  ret i8 %.0
}

declare void @XScuGic_Enable(ptr noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass