; LLVM IR from VeloxChem/VeloxChem :: src/math/Dense4DTensor.ll (ZN14CDense4DTensor3rowEiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.CDense4DTensor = type { i32, i32, i32, i32, %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorIdSaIdEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZN14CDense4DTensor3rowEiii(ptr noundef nonnull align 8 dereferenceable(40) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #0 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  %10 = load ptr, ptr %6, align 8
  %11 = load i32, ptr %7, align 4, !tbaa !9
  %12 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 0
  %13 = load i32, ptr %12, align 8, !tbaa !11
  %14 = icmp slt i32 %11, %13
  br i1 %14, label %15, label %55

15:                                               ; preds = %4
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 1
  %18 = load i32, ptr %17, align 4, !tbaa !17
  %19 = icmp slt i32 %16, %18
  br i1 %19, label %20, label %55

20:                                               ; preds = %15
  %21 = load i32, ptr %9, align 4, !tbaa !9
  %22 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 2
  %23 = load i32, ptr %22, align 8, !tbaa !18
  %24 = icmp slt i32 %21, %23
  br i1 %24, label %25, label %55

25:                                               ; preds = %20
  %26 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 4
  %27 = call noundef ptr @_ZNSt6vectorIdSaIdEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #1
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 1
  %30 = load i32, ptr %29, align 4, !tbaa !17
  %31 = mul nsw i32 %28, %30
  %32 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 2
  %33 = load i32, ptr %32, align 8, !tbaa !18
  %34 = mul nsw i32 %31, %33
  %35 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 3
  %36 = load i32, ptr %35, align 4, !tbaa !19
  %37 = mul nsw i32 %34, %36
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds double, ptr %27, i64 %38
  %40 = load i32, ptr %8, align 4, !tbaa !9
  %41 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 2
  %42 = load i32, ptr %41, align 8, !tbaa !18
  %43 = mul nsw i32 %40, %42
  %44 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 3
  %45 = load i32, ptr %44, align 4, !tbaa !19
  %46 = mul nsw i32 %43, %45
  %47 = sext i32 %46 to i64
  %48 = getelementptr inbounds double, ptr %39, i64 %47
  %49 = load i32, ptr %9, align 4, !tbaa !9
  %50 = getelementptr inbounds %class.CDense4DTensor, ptr %10, i32 0, i32 3
  %51 = load i32, ptr %50, align 4, !tbaa !19
  %52 = mul nsw i32 %49, %51
  %53 = sext i32 %52 to i64
  %54 = getelementptr inbounds double, ptr %48, i64 %53
  store ptr %54, ptr %5, align 8
  br label %56

55:                                               ; preds = %20, %15, %4
  store ptr null, ptr %5, align 8
  br label %56

56:                                               ; preds = %55, %25
  %57 = load ptr, ptr %5, align 8
  ret ptr %57
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTS14CDense4DTensor", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !13, i64 16}
!13 = !{!"_ZTSSt6vectorIdSaIdEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!12, !10, i64 4}
!18 = !{!12, !10, i64 8}
!19 = !{!12, !10, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorIdSaIdEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZN14CDense4DTensor3rowEiii(ptr noundef nonnull align 8 dereferenceable(40) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 align 2 {
  %5 = load i32, ptr %0, align 8, !tbaa !5
  %6 = icmp sgt i32 %5, %1
  br i1 %6, label %7, label %33

7:                                                ; preds = %4
  %8 = getelementptr inbounds i8, ptr %0, i64 4
  %9 = load i32, ptr %8, align 4, !tbaa !15
  %10 = icmp sgt i32 %9, %2
  br i1 %10, label %11, label %33

11:                                               ; preds = %7
  %12 = getelementptr inbounds i8, ptr %0, i64 8
  %13 = load i32, ptr %12, align 8, !tbaa !16
  %14 = icmp sgt i32 %13, %3
  br i1 %14, label %15, label %33

15:                                               ; preds = %11
  %16 = getelementptr inbounds i8, ptr %0, i64 16
  %17 = tail call noundef ptr @_ZNSt6vectorIdSaIdEE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #1
  %18 = load i32, ptr %8, align 4, !tbaa !15
  %19 = load i32, ptr %12, align 8, !tbaa !16
  %20 = getelementptr inbounds i8, ptr %0, i64 12
  %21 = load i32, ptr %20, align 4, !tbaa !17
  %22 = mul i32 %21, %19
  %23 = mul i32 %22, %1
  %24 = mul i32 %23, %18
  %25 = sext i32 %24 to i64
  %26 = getelementptr inbounds double, ptr %17, i64 %25
  %27 = mul i32 %22, %2
  %28 = sext i32 %27 to i64
  %29 = getelementptr inbounds double, ptr %26, i64 %28
  %30 = mul nsw i32 %21, %3
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds double, ptr %29, i64 %31
  br label %33

33:                                               ; preds = %4, %7, %11, %15
  %.0 = phi ptr [ %32, %15 ], [ null, %11 ], [ null, %7 ], [ null, %4 ]
  ret ptr %.0
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS14CDense4DTensor", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !10, i64 16}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIdSaIdEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!6, !7, i64 4}
!16 = !{!6, !7, i64 8}
!17 = !{!6, !7, i64 12}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass