; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (TestIO16)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [170 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @Xil_TestIO16(ptr noundef %0, i32 noundef %1, i16 noundef zeroext %2, i32 noundef %3, i32 noundef %4) #1 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca i16, align 2
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !9
  store i16 %2, ptr %9, align 2, !tbaa !11
  store i32 %3, ptr %10, align 4, !tbaa !9
  store i32 %4, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %13) #4
  store i16 0, ptr %13, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  %16 = load ptr, ptr %7, align 8, !tbaa !5
  store ptr %16, ptr %12, align 8, !tbaa !5
  %17 = load ptr, ptr %12, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %20

19:                                               ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %21

20:                                               ; preds = %5
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 160)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %6, align 4
  store i32 1, ptr %15, align 4
  br label %99

21:                                               ; preds = %19
  store i32 0, ptr %14, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %95, %21
  %23 = load i32, ptr %14, align 4, !tbaa !9
  %24 = load i32, ptr %8, align 4, !tbaa !9
  %25 = icmp slt i32 %23, %24
  br i1 %25, label %26, label %98

26:                                               ; preds = %22
  %27 = load i32, ptr %10, align 4, !tbaa !9
  switch i32 %27, label %36 [
    i32 1, label %28
    i32 2, label %32
  ]

28:                                               ; preds = %26
  %29 = load ptr, ptr %12, align 8, !tbaa !5
  %30 = ptrtoint ptr %29 to i64
  %31 = load i16, ptr %9, align 2, !tbaa !11
  call void @Xil_Out16(i64 noundef %30, i16 noundef zeroext %31)
  br label %40

32:                                               ; preds = %26
  %33 = load ptr, ptr %12, align 8, !tbaa !5
  %34 = ptrtoint ptr %33 to i64
  %35 = load i16, ptr %9, align 2, !tbaa !11
  call void @Xil_Out16BE(i64 noundef %34, i16 noundef zeroext %35)
  br label %40

36:                                               ; preds = %26
  %37 = load ptr, ptr %12, align 8, !tbaa !5
  %38 = ptrtoint ptr %37 to i64
  %39 = load i16, ptr %9, align 2, !tbaa !11
  call void @Xil_Out16(i64 noundef %38, i16 noundef zeroext %39)
  br label %40

40:                                               ; preds = %36, %32, %28
  %41 = load ptr, ptr %12, align 8, !tbaa !5
  %42 = ptrtoint ptr %41 to i64
  %43 = call zeroext i16 @Xil_In16(i64 noundef %42)
  store i16 %43, ptr %13, align 2, !tbaa !11
  %44 = load i32, ptr %10, align 4, !tbaa !9
  %45 = icmp ne i32 %44, 0
  br i1 %45, label %46, label %52

46:                                               ; preds = %40
  %47 = load i32, ptr %11, align 4, !tbaa !9
  %48 = icmp ne i32 %47, 0
  br i1 %48, label %49, label %52

49:                                               ; preds = %46
  %50 = load i16, ptr %13, align 2, !tbaa !11
  %51 = call zeroext i16 @Swap16(i16 noundef zeroext %50)
  store i16 %51, ptr %13, align 2, !tbaa !11
  br label %52

52:                                               ; preds = %49, %46, %40
  %53 = load i16, ptr %9, align 2, !tbaa !11
  %54 = zext i16 %53 to i32
  %55 = load i16, ptr %13, align 2, !tbaa !11
  %56 = zext i16 %55 to i32
  %57 = icmp ne i32 %54, %56
  br i1 %57, label %58, label %59

58:                                               ; preds = %52
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %15, align 4
  br label %99

59:                                               ; preds = %52
  %60 = load ptr, ptr %12, align 8, !tbaa !5
  %61 = ptrtoint ptr %60 to i64
  %62 = load i16, ptr %9, align 2, !tbaa !11
  call void @Xil_Out16(i64 noundef %61, i16 noundef zeroext %62)
  %63 = load i32, ptr %10, align 4, !tbaa !9
  switch i32 %63, label %72 [
    i32 1, label %64
    i32 2, label %68
  ]

64:                                               ; preds = %59
  %65 = load ptr, ptr %12, align 8, !tbaa !5
  %66 = ptrtoint ptr %65 to i64
  %67 = call zeroext i16 @Xil_In16(i64 noundef %66)
  store i16 %67, ptr %13, align 2, !tbaa !11
  br label %76

68:                                               ; preds = %59
  %69 = load ptr, ptr %12, align 8, !tbaa !5
  %70 = ptrtoint ptr %69 to i64
  %71 = call zeroext i16 @Xil_In16BE(i64 noundef %70)
  store i16 %71, ptr %13, align 2, !tbaa !11
  br label %76

72:                                               ; preds = %59
  %73 = load ptr, ptr %12, align 8, !tbaa !5
  %74 = ptrtoint ptr %73 to i64
  %75 = call zeroext i16 @Xil_In16(i64 noundef %74)
  store i16 %75, ptr %13, align 2, !tbaa !11
  br label %76

76:                                               ; preds = %72, %68, %64
  %77 = load i32, ptr %10, align 4, !tbaa !9
  %78 = icmp ne i32 %77, 0
  br i1 %78, label %79, label %85

79:                                               ; preds = %76
  %80 = load i32, ptr %11, align 4, !tbaa !9
  %81 = icmp ne i32 %80, 0
  br i1 %81, label %82, label %85

82:                                               ; preds = %79
  %83 = load i16, ptr %13, align 2, !tbaa !11
  %84 = call zeroext i16 @Swap16(i16 noundef zeroext %83)
  store i16 %84, ptr %13, align 2, !tbaa !11
  br label %85

85:                                               ; preds = %82, %79, %76
  %86 = load i16, ptr %9, align 2, !tbaa !11
  %87 = zext i16 %86 to i32
  %88 = load i16, ptr %13, align 2, !tbaa !11
  %89 = zext i16 %88 to i32
  %90 = icmp ne i32 %87, %89
  br i1 %90, label %91, label %92

91:                                               ; preds = %85
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %15, align 4
  br label %99

92:                                               ; preds = %85
  %93 = load ptr, ptr %12, align 8, !tbaa !5
  %94 = getelementptr inbounds i16, ptr %93, i64 2
  store ptr %94, ptr %12, align 8, !tbaa !5
  br label %95

95:                                               ; preds = %92
  %96 = load i32, ptr %14, align 4, !tbaa !9
  %97 = add nsw i32 %96, 1
  store i32 %97, ptr %14, align 4, !tbaa !9
  br label %22, !llvm.loop !13

98:                                               ; preds = %22
  store i32 0, ptr %6, align 4
  store i32 1, ptr %15, align 4
  br label %99

99:                                               ; preds = %98, %91, %58, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  %100 = load i32, ptr %6, align 4
  ret i32 %100
}

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out16(i64 noundef, i16 noundef zeroext) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out16BE(i64 noundef, i16 noundef zeroext) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @Xil_In16(i64 noundef) #3

; Function Attrs: nounwind uwtable
declare hidden zeroext i16 @Swap16(i16 noundef zeroext) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @Xil_In16BE(i64 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [170 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @Xil_TestIO16(ptr noundef %0, i32 noundef %1, i16 noundef zeroext %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %43, label %6

6:                                                ; preds = %5
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = icmp sgt i32 %1, 0
  br i1 %7, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %6
  %8 = icmp ne i32 %3, 0
  %9 = icmp ne i32 %4, 0
  %or.cond = and i1 %8, %9
  br i1 %or.cond, label %.lr.ph.split.us, label %.lr.ph.split

.lr.ph.split.us:                                  ; preds = %.lr.ph, %26
  %.041.us = phi i32 [ %28, %26 ], [ 0, %.lr.ph ]
  %.03440.us = phi ptr [ %27, %26 ], [ %0, %.lr.ph ]
  %10 = ptrtoint ptr %.03440.us to i64
  switch i32 %3, label %13 [
    i32 1, label %12
    i32 2, label %11
  ]

11:                                               ; preds = %.lr.ph.split.us
  tail call void @Xil_Out16BE(i64 noundef %10, i16 noundef zeroext %2)
  br label %14

12:                                               ; preds = %.lr.ph.split.us
  tail call void @Xil_Out16(i64 noundef %10, i16 noundef zeroext %2)
  br label %14

13:                                               ; preds = %.lr.ph.split.us
  tail call void @Xil_Out16(i64 noundef %10, i16 noundef zeroext %2)
  br label %14

14:                                               ; preds = %13, %12, %11
  %15 = tail call zeroext i16 @Xil_In16(i64 noundef %10)
  %16 = tail call zeroext i16 @Swap16(i16 noundef zeroext %15)
  %.not38.us = icmp eq i16 %16, %2
  br i1 %.not38.us, label %17, label %.loopexit

17:                                               ; preds = %14
  tail call void @Xil_Out16(i64 noundef %10, i16 noundef zeroext %2)
  switch i32 %3, label %22 [
    i32 1, label %20
    i32 2, label %18
  ]

18:                                               ; preds = %17
  %19 = tail call zeroext i16 @Xil_In16BE(i64 noundef %10)
  br label %24

20:                                               ; preds = %17
  %21 = tail call zeroext i16 @Xil_In16(i64 noundef %10)
  br label %24

22:                                               ; preds = %17
  %23 = tail call zeroext i16 @Xil_In16(i64 noundef %10)
  br label %24

24:                                               ; preds = %22, %20, %18
  %.1.us = phi i16 [ %23, %22 ], [ %19, %18 ], [ %21, %20 ]
  %25 = tail call zeroext i16 @Swap16(i16 noundef zeroext %.1.us)
  %.not39.us = icmp eq i16 %25, %2
  br i1 %.not39.us, label %26, label %.loopexit

26:                                               ; preds = %24
  %27 = getelementptr inbounds i8, ptr %.03440.us, i64 4
  %28 = add nuw nsw i32 %.041.us, 1
  %exitcond79.not = icmp eq i32 %28, %1
  br i1 %exitcond79.not, label %.loopexit, label %.lr.ph.split.us, !llvm.loop !9

.lr.ph.split:                                     ; preds = %.lr.ph
  switch i32 %3, label %.lr.ph.split.split [
    i32 1, label %.lr.ph.split.split.us
    i32 2, label %.lr.ph.split.split.us59
  ]

.lr.ph.split.split.us:                            ; preds = %.lr.ph.split, %33
  %.041.us48 = phi i32 [ %35, %33 ], [ 0, %.lr.ph.split ]
  %.03440.us49 = phi ptr [ %34, %33 ], [ %0, %.lr.ph.split ]
  %29 = ptrtoint ptr %.03440.us49 to i64
  tail call void @Xil_Out16(i64 noundef %29, i16 noundef zeroext %2)
  %30 = tail call zeroext i16 @Xil_In16(i64 noundef %29)
  %.not38.us50 = icmp eq i16 %30, %2
  br i1 %.not38.us50, label %31, label %.loopexit

31:                                               ; preds = %.lr.ph.split.split.us
  tail call void @Xil_Out16(i64 noundef %29, i16 noundef zeroext %2)
  %32 = tail call zeroext i16 @Xil_In16(i64 noundef %29)
  %.not39.us52 = icmp eq i16 %32, %2
  br i1 %.not39.us52, label %33, label %.loopexit

33:                                               ; preds = %31
  %34 = getelementptr inbounds i8, ptr %.03440.us49, i64 4
  %35 = add nuw nsw i32 %.041.us48, 1
  %exitcond77.not = icmp eq i32 %35, %1
  br i1 %exitcond77.not, label %.loopexit, label %.lr.ph.split.split.us, !llvm.loop !9

.lr.ph.split.split.us59:                          ; preds = %.lr.ph.split, %40
  %.041.us60 = phi i32 [ %42, %40 ], [ 0, %.lr.ph.split ]
  %.03440.us61 = phi ptr [ %41, %40 ], [ %0, %.lr.ph.split ]
  %36 = ptrtoint ptr %.03440.us61 to i64
  tail call void @Xil_Out16BE(i64 noundef %36, i16 noundef zeroext %2)
  %37 = tail call zeroext i16 @Xil_In16(i64 noundef %36)
  %.not38.us62 = icmp eq i16 %37, %2
  br i1 %.not38.us62, label %38, label %.loopexit

38:                                               ; preds = %.lr.ph.split.split.us59
  tail call void @Xil_Out16(i64 noundef %36, i16 noundef zeroext %2)
  %39 = tail call zeroext i16 @Xil_In16BE(i64 noundef %36)
  %.not39.us64 = icmp eq i16 %39, %2
  br i1 %.not39.us64, label %40, label %.loopexit

40:                                               ; preds = %38
  %41 = getelementptr inbounds i8, ptr %.03440.us61, i64 4
  %42 = add nuw nsw i32 %.041.us60, 1
  %exitcond.not = icmp eq i32 %42, %1
  br i1 %exitcond.not, label %.loopexit, label %.lr.ph.split.split.us59, !llvm.loop !9

43:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 160) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %.loopexit

.lr.ph.split.split:                               ; preds = %.lr.ph.split, %54
  %.041 = phi i32 [ %56, %54 ], [ 0, %.lr.ph.split ]
  %.03440 = phi ptr [ %55, %54 ], [ %0, %.lr.ph.split ]
  %44 = ptrtoint ptr %.03440 to i64
  tail call void @Xil_Out16(i64 noundef %44, i16 noundef zeroext %2)
  %45 = tail call zeroext i16 @Xil_In16(i64 noundef %44)
  %.not38 = icmp eq i16 %45, %2
  br i1 %.not38, label %46, label %.loopexit

46:                                               ; preds = %.lr.ph.split.split
  tail call void @Xil_Out16(i64 noundef %44, i16 noundef zeroext %2)
  switch i32 %3, label %51 [
    i32 1, label %47
    i32 2, label %49
  ]

47:                                               ; preds = %46
  %48 = tail call zeroext i16 @Xil_In16(i64 noundef %44)
  br label %53

49:                                               ; preds = %46
  %50 = tail call zeroext i16 @Xil_In16BE(i64 noundef %44)
  br label %53

51:                                               ; preds = %46
  %52 = tail call zeroext i16 @Xil_In16(i64 noundef %44)
  br label %53

53:                                               ; preds = %51, %49, %47
  %.1 = phi i16 [ %52, %51 ], [ %50, %49 ], [ %48, %47 ]
  %.not39 = icmp eq i16 %.1, %2
  br i1 %.not39, label %54, label %.loopexit

54:                                               ; preds = %53
  %55 = getelementptr inbounds i8, ptr %.03440, i64 4
  %56 = add nuw nsw i32 %.041, 1
  %exitcond78.not = icmp eq i32 %56, %1
  br i1 %exitcond78.not, label %.loopexit, label %.lr.ph.split.split, !llvm.loop !9

.loopexit:                                        ; preds = %.lr.ph.split.split.us59, %38, %40, %.lr.ph.split.split.us, %31, %33, %.lr.ph.split.split, %53, %54, %14, %24, %26, %6, %43
  %.035 = phi i32 [ 0, %43 ], [ 0, %6 ], [ -1, %14 ], [ -1, %24 ], [ 0, %26 ], [ -1, %.lr.ph.split.split ], [ -1, %53 ], [ 0, %54 ], [ -1, %.lr.ph.split.split.us ], [ -1, %31 ], [ 0, %33 ], [ -1, %.lr.ph.split.split.us59 ], [ -1, %38 ], [ 0, %40 ]
  ret i32 %.035
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out16(i64 noundef, i16 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out16BE(i64 noundef, i16 noundef zeroext) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @Xil_In16(i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden zeroext i16 @Swap16(i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @Xil_In16BE(i64 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass