; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (InterruptUnmapFromCpuByDistAddr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_InterruptUnmapFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1, i32 noundef %2) #3 {
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  %10 = load i32, ptr %6, align 4, !tbaa !5
  %11 = icmp ult i32 %10, 95
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %14

13:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 602)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  store i32 1, ptr %9, align 4
  br label %44

14:                                               ; preds = %12
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = load i32, ptr %6, align 4, !tbaa !5
  %17 = udiv i32 %16, 4
  %18 = mul i32 %17, 4
  %19 = add i32 2048, %18
  %20 = add i32 %15, %19
  %21 = zext i32 %20 to i64
  %22 = call i32 @Xil_In32(i64 noundef %21)
  store i32 %22, ptr %7, align 4, !tbaa !5
  %23 = load i32, ptr %6, align 4, !tbaa !5
  %24 = urem i32 %23, 4
  %25 = mul i32 %24, 8
  %26 = load i8, ptr %5, align 1, !tbaa !9
  %27 = zext i8 %26 to i32
  %28 = add i32 %25, %27
  %29 = trunc i32 %28 to i8
  store i8 %29, ptr %8, align 1, !tbaa !9
  %30 = load i8, ptr %8, align 1, !tbaa !9
  %31 = zext i8 %30 to i32
  %32 = shl i32 1, %31
  %33 = xor i32 %32, -1
  %34 = load i32, ptr %7, align 4, !tbaa !5
  %35 = and i32 %34, %33
  store i32 %35, ptr %7, align 4, !tbaa !5
  %36 = load i32, ptr %4, align 4, !tbaa !5
  %37 = load i32, ptr %6, align 4, !tbaa !5
  %38 = udiv i32 %37, 4
  %39 = mul i32 %38, 4
  %40 = add i32 2048, %39
  %41 = add i32 %36, %40
  %42 = zext i32 %41 to i64
  %43 = load i32, ptr %7, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %42, i32 noundef %43)
  store i32 0, ptr %9, align 4
  br label %44

44:                                               ; preds = %14, %13
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  %45 = load i32, ptr %9, align 4
  switch i32 %45, label %47 [
    i32 0, label %46
    i32 1, label %46
  ]

46:                                               ; preds = %44, %44
  ret void

47:                                               ; preds = %44
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #0

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_InterruptUnmapFromCpuByDistAddr(i32 noundef %0, i8 noundef zeroext %1, i32 noundef %2) local_unnamed_addr #2 {
  %4 = icmp ult i32 %2, 95
  br i1 %4, label %5, label %18

5:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = and i32 %2, 124
  %7 = add i32 %0, 2048
  %8 = add i32 %7, %6
  %9 = zext i32 %8 to i64
  %10 = tail call i32 @Xil_In32(i64 noundef %9)
  %.tr = trunc nuw i32 %2 to i8
  %11 = shl i8 %.tr, 3
  %12 = and i8 %11, 24
  %13 = add i8 %12, %1
  %14 = zext nneg i8 %13 to i32
  %15 = shl nuw i32 1, %14
  %16 = xor i32 %15, -1
  %17 = and i32 %10, %16
  tail call void @Xil_Out32(i64 noundef %9, i32 noundef %17)
  br label %19

18:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 602) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %5, %18
  ret void
}

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass