; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (SelfTest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [173 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XScuGic_SelfTest(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %12

11:                                               ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 95)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %50

12:                                               ; preds = %10
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.XScuGic, ptr %13, i32 0, i32 1
  %15 = load i32, ptr %14, align 8, !tbaa !11
  %16 = icmp eq i32 %15, 286331153
  br i1 %16, label %17, label %18

17:                                               ; preds = %12
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %12
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 96)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %50

19:                                               ; preds = %17
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %40, %19
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = icmp ule i32 %21, 3
  br i1 %22, label %23, label %43

23:                                               ; preds = %20
  %24 = load ptr, ptr %3, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XScuGic, ptr %24, i32 0, i32 0
  %26 = load ptr, ptr %25, align 8, !tbaa !13
  %27 = getelementptr inbounds %struct.XScuGic_Config, ptr %26, i32 0, i32 2
  %28 = load i32, ptr %27, align 8, !tbaa !14
  %29 = load i32, ptr %5, align 4, !tbaa !9
  %30 = mul i32 %29, 4
  %31 = add i32 4080, %30
  %32 = add i32 %28, %31
  %33 = zext i32 %32 to i64
  %34 = call i32 @Xil_In32(i64 noundef %33)
  %35 = load i32, ptr %5, align 4, !tbaa !9
  %36 = mul i32 %35, 8
  %37 = shl i32 %34, %36
  %38 = load i32, ptr %4, align 4, !tbaa !9
  %39 = or i32 %38, %37
  store i32 %39, ptr %4, align 4, !tbaa !9
  br label %40

40:                                               ; preds = %23
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = add i32 %41, 1
  store i32 %42, ptr %5, align 4, !tbaa !9
  br label %20, !llvm.loop !17

43:                                               ; preds = %20
  %44 = load i32, ptr %4, align 4, !tbaa !9
  %45 = icmp ne i32 -1325010931, %44
  br i1 %45, label %46, label %47

46:                                               ; preds = %43
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %48

47:                                               ; preds = %43
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %47, %46
  %49 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %49, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %50

50:                                               ; preds = %48, %18, %11
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %51 = load i32, ptr %2, align 4
  ret i32 %51
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!12, !6, i64 0}
!14 = !{!15, !10, i64 8}
!15 = !{!"", !16, i64 0, !10, i64 4, !10, i64 8, !7, i64 16}
!16 = !{!"short", !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [173 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XScuGic_SelfTest(ptr noundef readonly %0) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %2

2:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !9
  %5 = icmp eq i32 %4, 286331153
  br i1 %5, label %7, label %38

6:                                                ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 95) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %39

7:                                                ; preds = %2
  %8 = load ptr, ptr %0, align 8, !tbaa !12
  %9 = getelementptr inbounds i8, ptr %8, i64 8
  %10 = load i32, ptr %9, align 8, !tbaa !13
  %11 = add i32 %10, 4080
  %12 = zext i32 %11 to i64
  %13 = tail call i32 @Xil_In32(i64 noundef %12)
  %14 = load ptr, ptr %0, align 8, !tbaa !12
  %15 = getelementptr inbounds i8, ptr %14, i64 8
  %16 = load i32, ptr %15, align 8, !tbaa !13
  %17 = add i32 %16, 4084
  %18 = zext i32 %17 to i64
  %19 = tail call i32 @Xil_In32(i64 noundef %18)
  %20 = shl i32 %19, 8
  %21 = or i32 %20, %13
  %22 = load ptr, ptr %0, align 8, !tbaa !12
  %23 = getelementptr inbounds i8, ptr %22, i64 8
  %24 = load i32, ptr %23, align 8, !tbaa !13
  %25 = add i32 %24, 4088
  %26 = zext i32 %25 to i64
  %27 = tail call i32 @Xil_In32(i64 noundef %26)
  %28 = shl i32 %27, 16
  %29 = or i32 %28, %21
  %30 = load ptr, ptr %0, align 8, !tbaa !12
  %31 = getelementptr inbounds i8, ptr %30, i64 8
  %32 = load i32, ptr %31, align 8, !tbaa !13
  %33 = add i32 %32, 4092
  %34 = zext i32 %33 to i64
  %35 = tail call i32 @Xil_In32(i64 noundef %34)
  %36 = shl i32 %35, 24
  %37 = or i32 %36, %29
  %.not14 = icmp ne i32 %37, -1325010931
  %. = zext i1 %.not14 to i32
  br label %39

38:                                               ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 96) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %39

39:                                               ; preds = %7, %38, %6
  %.012 = phi i32 [ %., %7 ], [ 0, %38 ], [ 0, %6 ]
  ret i32 %.012
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LoopRotatePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass