; LLVM IR from CactiLab/Sherloc-Cortex-M-CFVD :: Sherloc_runtime/freertos (queue)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @xQueueGenericCreate(i64 noundef %0, i64 noundef %1, i8 noundef zeroext %2) #1 section "privileged_functions" {
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca ptr, align 8
  store i64 %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !5
  store i8 %2, ptr %6, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  store ptr null, ptr %7, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  %10 = load i64, ptr %4, align 8, !tbaa !5
  %11 = icmp ugt i64 %10, 0
  br i1 %11, label %12, label %42

12:                                               ; preds = %3
  %13 = load i64, ptr %4, align 8, !tbaa !5
  %14 = udiv i64 -1, %13
  %15 = load i64, ptr %5, align 8, !tbaa !5
  %16 = icmp uge i64 %14, %15
  br i1 %16, label %17, label %42

17:                                               ; preds = %12
  %18 = load i64, ptr %4, align 8, !tbaa !5
  %19 = load i64, ptr %5, align 8, !tbaa !5
  %20 = mul i64 %18, %19
  %21 = icmp uge i64 -169, %20
  br i1 %21, label %22, label %42

22:                                               ; preds = %17
  %23 = load i64, ptr %4, align 8, !tbaa !5
  %24 = load i64, ptr %5, align 8, !tbaa !5
  %25 = mul i64 %23, %24
  store i64 %25, ptr %8, align 8, !tbaa !5
  %26 = load i64, ptr %8, align 8, !tbaa !5
  %27 = add i64 168, %26
  %28 = call ptr @pvPortMalloc(i64 noundef %27)
  store ptr %28, ptr %7, align 8, !tbaa !10
  %29 = load ptr, ptr %7, align 8, !tbaa !10
  %30 = icmp ne ptr %29, null
  br i1 %30, label %31, label %40

31:                                               ; preds = %22
  %32 = load ptr, ptr %7, align 8, !tbaa !10
  store ptr %32, ptr %9, align 8, !tbaa !10
  %33 = load ptr, ptr %9, align 8, !tbaa !10
  %34 = getelementptr inbounds i8, ptr %33, i64 168
  store ptr %34, ptr %9, align 8, !tbaa !10
  %35 = load i64, ptr %4, align 8, !tbaa !5
  %36 = load i64, ptr %5, align 8, !tbaa !5
  %37 = load ptr, ptr %9, align 8, !tbaa !10
  %38 = load i8, ptr %6, align 1, !tbaa !9
  %39 = load ptr, ptr %7, align 8, !tbaa !10
  call void @prvInitialiseNewQueue(i64 noundef %35, i64 noundef %36, ptr noundef %37, i8 noundef zeroext %38, ptr noundef %39)
  br label %41

40:                                               ; preds = %22
  br label %41

41:                                               ; preds = %40, %31
  br label %48

42:                                               ; preds = %17, %12, %3
  %43 = load ptr, ptr %7, align 8, !tbaa !10
  %44 = icmp eq ptr %43, null
  br i1 %44, label %45, label %47

45:                                               ; preds = %42
  call void asm sideeffect " cpsid i ", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !12
  br label %46

46:                                               ; preds = %46, %45
  br label %46

47:                                               ; preds = %42
  br label %48

48:                                               ; preds = %47, %41
  %49 = load ptr, ptr %7, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret ptr %49
}

declare ptr @pvPortMalloc(i64 noundef) #2 section "privileged_functions"

; Function Attrs: nounwind uwtable
declare hidden void @prvInitialiseNewQueue(i64 noundef, i64 noundef, ptr noundef, i8 noundef zeroext, ptr noundef) #1 section "privileged_functions"

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{i64 2148318225}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local ptr @xQueueGenericCreate(i64 noundef %0, i64 noundef %1, i8 noundef zeroext %2) local_unnamed_addr #0 section "privileged_functions" {
  %.not = icmp eq i64 %0, 0
  br i1 %.not, label %13, label %4

4:                                                ; preds = %3
  %mul = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %0, i64 %1)
  %mul.ov = extractvalue { i64, i1 } %mul, 1
  br i1 %mul.ov, label %13, label %5

5:                                                ; preds = %4
  %6 = mul i64 %1, %0
  %7 = icmp ult i64 %6, -168
  br i1 %7, label %8, label %13

8:                                                ; preds = %5
  %9 = add nuw i64 %6, 168
  %10 = tail call ptr @pvPortMalloc(i64 noundef %9) #3
  %.not22 = icmp eq ptr %10, null
  br i1 %.not22, label %15, label %11

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %10, i64 168
  tail call void @prvInitialiseNewQueue(i64 noundef %0, i64 noundef %1, ptr noundef nonnull %12, i8 noundef zeroext %2, ptr noundef nonnull %10)
  br label %15

13:                                               ; preds = %3, %4, %5
  tail call void asm sideeffect " cpsid i ", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !5
  br label %14

14:                                               ; preds = %14, %13
  br label %14

15:                                               ; preds = %11, %8
  ret ptr %10
}

declare ptr @pvPortMalloc(i64 noundef) local_unnamed_addr #1 section "privileged_functions"

; Function Attrs: nounwind uwtable
declare hidden void @prvInitialiseNewQueue(i64 noundef, i64 noundef, ptr noundef, i8 noundef zeroext, ptr noundef) local_unnamed_addr #0 section "privileged_functions"

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2148318225}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass