; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (SetMuxMode)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }
%struct.XAdcPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XAdcPs_SetMuxMode(ptr noundef %0, i32 noundef %1, i8 noundef zeroext %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i8 %2, ptr %6, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = icmp ne ptr %9, null
  br i1 %10, label %11, label %12

11:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %13

12:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1648)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %45

13:                                               ; preds = %11
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.XAdcPs, ptr %14, i32 0, i32 1
  %16 = load i32, ptr %15, align 4, !tbaa !12
  %17 = icmp eq i32 %16, 286331153
  br i1 %17, label %18, label %19

18:                                               ; preds = %13
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %20

19:                                               ; preds = %13
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1649)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %45

20:                                               ; preds = %18
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %26, label %23

23:                                               ; preds = %20
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %23, %20
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %28

27:                                               ; preds = %23
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1650)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %8, align 4
  br label %45

28:                                               ; preds = %26
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  %30 = call i32 @XAdcPs_ReadInternalReg(ptr noundef %29, i32 noundef 64)
  %31 = and i32 %30, -2049
  store i32 %31, ptr %7, align 4, !tbaa !9
  %32 = load i32, ptr %5, align 4, !tbaa !9
  %33 = icmp eq i32 %32, 1
  br i1 %33, label %34, label %42

34:                                               ; preds = %28
  %35 = load i32, ptr %7, align 4, !tbaa !9
  %36 = or i32 %35, 2048
  store i32 %36, ptr %7, align 4, !tbaa !9
  %37 = load i8, ptr %6, align 1, !tbaa !11
  %38 = zext i8 %37 to i32
  %39 = and i32 %38, 31
  %40 = load i32, ptr %7, align 4, !tbaa !9
  %41 = or i32 %40, %39
  store i32 %41, ptr %7, align 4, !tbaa !9
  br label %42

42:                                               ; preds = %34, %28
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !9
  call void @XAdcPs_WriteInternalReg(ptr noundef %43, i32 noundef 64, i32 noundef %44)
  store i32 0, ptr %8, align 4
  br label %45

45:                                               ; preds = %42, %27, %19, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  %46 = load i32, ptr %8, align 4
  switch i32 %46, label %48 [
    i32 0, label %47
    i32 1, label %47
  ]

47:                                               ; preds = %45, %45
  ret void

48:                                               ; preds = %45
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 8}
!13 = !{!"", !14, i64 0, !10, i64 8}
!14 = !{!"", !15, i64 0, !10, i64 4}
!15 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @XAdcPs_WriteInternalReg(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XAdcPs_SetMuxMode(ptr noundef %0, i32 noundef %1, i8 noundef zeroext %2) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %8, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = load i32, ptr %5, align 4, !tbaa !9
  %7 = icmp eq i32 %6, 286331153
  br i1 %7, label %9, label %10

8:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1648) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

9:                                                ; preds = %4
  %or.cond = icmp ult i32 %1, 2
  br i1 %or.cond, label %11, label %19

10:                                               ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1649) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

11:                                               ; preds = %9
  %12 = icmp eq i32 %1, 1
  %13 = tail call i32 @XAdcPs_ReadInternalReg(ptr noundef nonnull %0, i32 noundef 64)
  %14 = and i32 %13, -2049
  %15 = and i8 %2, 31
  %16 = zext nneg i8 %15 to i32
  %17 = or i32 %13, %16
  %18 = or i32 %17, 2048
  %.0 = select i1 %12, i32 %18, i32 %14
  tail call void @XAdcPs_WriteInternalReg(ptr noundef nonnull %0, i32 noundef 64, i32 noundef %.0)
  br label %20

19:                                               ; preds = %9
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1650) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %11, %19, %10, %8
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass