; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (ResetHw)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @XDmaPs_ResetHw(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %6 = load i32, ptr %2, align 4, !tbaa !5
  %7 = add i32 %6, 32
  %8 = zext i32 %7 to i64
  call void @Xil_Out32(i64 noundef %8, i32 noundef 0)
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = add i32 %9, 44
  %11 = zext i32 %10 to i64
  call void @Xil_Out32(i64 noundef %11, i32 noundef 255)
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %47, %1
  %13 = load i32, ptr %5, align 4, !tbaa !5
  %14 = icmp ult i32 %13, 8
  br i1 %14, label %15, label %50

15:                                               ; preds = %12
  br label %16

16:                                               ; preds = %28, %15
  %17 = load i32, ptr %2, align 4, !tbaa !5
  %18 = add i32 %17, 3328
  %19 = zext i32 %18 to i64
  %20 = call i32 @Xil_In32(i64 noundef %19)
  %21 = and i32 %20, 1
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %26

23:                                               ; preds = %16
  %24 = load i32, ptr %4, align 4, !tbaa !5
  %25 = icmp ult i32 %24, 4000
  br label %26

26:                                               ; preds = %23, %16
  %27 = phi i1 [ false, %16 ], [ %25, %23 ]
  br i1 %27, label %28, label %31

28:                                               ; preds = %26
  %29 = load i32, ptr %4, align 4, !tbaa !5
  %30 = add i32 %29, 1
  store i32 %30, ptr %4, align 4, !tbaa !5
  br label %16, !llvm.loop !9

31:                                               ; preds = %26
  %32 = load i32, ptr %5, align 4, !tbaa !5
  %33 = and i32 %32, 7
  %34 = shl i32 %33, 8
  %35 = or i32 65536, %34
  %36 = or i32 %35, 1
  store i32 %36, ptr %3, align 4, !tbaa !5
  %37 = load i32, ptr %2, align 4, !tbaa !5
  %38 = add i32 %37, 3336
  %39 = zext i32 %38 to i64
  %40 = load i32, ptr %3, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %39, i32 noundef %40)
  %41 = load i32, ptr %2, align 4, !tbaa !5
  %42 = add i32 %41, 3340
  %43 = zext i32 %42 to i64
  call void @Xil_Out32(i64 noundef %43, i32 noundef 0)
  %44 = load i32, ptr %2, align 4, !tbaa !5
  %45 = add i32 %44, 3332
  %46 = zext i32 %45 to i64
  call void @Xil_Out32(i64 noundef %46, i32 noundef 0)
  br label %47

47:                                               ; preds = %31
  %48 = load i32, ptr %5, align 4, !tbaa !5
  %49 = add i32 %48, 1
  store i32 %49, ptr %5, align 4, !tbaa !5
  br label %12, !llvm.loop !11

50:                                               ; preds = %12
  store i32 65536, ptr %3, align 4, !tbaa !5
  %51 = load i32, ptr %2, align 4, !tbaa !5
  %52 = add i32 %51, 3336
  %53 = zext i32 %52 to i64
  %54 = load i32, ptr %3, align 4, !tbaa !5
  call void @Xil_Out32(i64 noundef %53, i32 noundef %54)
  %55 = load i32, ptr %2, align 4, !tbaa !5
  %56 = add i32 %55, 3340
  %57 = zext i32 %56 to i64
  call void @Xil_Out32(i64 noundef %57, i32 noundef 0)
  %58 = load i32, ptr %2, align 4, !tbaa !5
  %59 = add i32 %58, 3332
  %60 = zext i32 %59 to i64
  call void @Xil_Out32(i64 noundef %60, i32 noundef 0)
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @XDmaPs_ResetHw(i32 noundef %0) local_unnamed_addr #0 {
.preheader:
  %1 = add i32 %0, 32
  %2 = zext i32 %1 to i64
  tail call void @Xil_Out32(i64 noundef %2, i32 noundef 0)
  %3 = add i32 %0, 44
  %4 = zext i32 %3 to i64
  tail call void @Xil_Out32(i64 noundef %4, i32 noundef 255)
  %5 = add i32 %0, 3328
  %6 = zext i32 %5 to i64
  %7 = add i32 %0, 3336
  %8 = zext i32 %7 to i64
  %9 = add i32 %0, 3340
  %10 = zext i32 %9 to i64
  %11 = add i32 %0, 3332
  %12 = zext i32 %11 to i64
  br label %13

13:                                               ; preds = %13, %.preheader
  %.1 = phi i32 [ %19, %13 ], [ 0, %.preheader ]
  %14 = tail call i32 @Xil_In32(i64 noundef %6)
  %15 = and i32 %14, 1
  %16 = icmp ne i32 %15, 0
  %17 = icmp ult i32 %.1, 4000
  %18 = select i1 %16, i1 %17, i1 false
  %19 = add nuw nsw i32 %.1, 1
  br i1 %18, label %13, label %.preheader.1, !llvm.loop !5

.preheader.1:                                     ; preds = %13
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 65537)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %20

20:                                               ; preds = %20, %.preheader.1
  %.1.1 = phi i32 [ %26, %20 ], [ %.1, %.preheader.1 ]
  %21 = tail call i32 @Xil_In32(i64 noundef %6)
  %22 = and i32 %21, 1
  %23 = icmp ne i32 %22, 0
  %24 = icmp ult i32 %.1.1, 4000
  %25 = select i1 %23, i1 %24, i1 false
  %26 = add nuw nsw i32 %.1.1, 1
  br i1 %25, label %20, label %.preheader.2, !llvm.loop !5

.preheader.2:                                     ; preds = %20
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 65793)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %27

27:                                               ; preds = %27, %.preheader.2
  %.1.2 = phi i32 [ %33, %27 ], [ %.1.1, %.preheader.2 ]
  %28 = tail call i32 @Xil_In32(i64 noundef %6)
  %29 = and i32 %28, 1
  %30 = icmp ne i32 %29, 0
  %31 = icmp ult i32 %.1.2, 4000
  %32 = select i1 %30, i1 %31, i1 false
  %33 = add nuw nsw i32 %.1.2, 1
  br i1 %32, label %27, label %.preheader.3, !llvm.loop !5

.preheader.3:                                     ; preds = %27
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 66049)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %34

34:                                               ; preds = %34, %.preheader.3
  %.1.3 = phi i32 [ %40, %34 ], [ %.1.2, %.preheader.3 ]
  %35 = tail call i32 @Xil_In32(i64 noundef %6)
  %36 = and i32 %35, 1
  %37 = icmp ne i32 %36, 0
  %38 = icmp ult i32 %.1.3, 4000
  %39 = select i1 %37, i1 %38, i1 false
  %40 = add nuw nsw i32 %.1.3, 1
  br i1 %39, label %34, label %.preheader.4, !llvm.loop !5

.preheader.4:                                     ; preds = %34
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 66305)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %41

41:                                               ; preds = %41, %.preheader.4
  %.1.4 = phi i32 [ %47, %41 ], [ %.1.3, %.preheader.4 ]
  %42 = tail call i32 @Xil_In32(i64 noundef %6)
  %43 = and i32 %42, 1
  %44 = icmp ne i32 %43, 0
  %45 = icmp ult i32 %.1.4, 4000
  %46 = select i1 %44, i1 %45, i1 false
  %47 = add nuw nsw i32 %.1.4, 1
  br i1 %46, label %41, label %.preheader.5, !llvm.loop !5

.preheader.5:                                     ; preds = %41
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 66561)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %48

48:                                               ; preds = %48, %.preheader.5
  %.1.5 = phi i32 [ %54, %48 ], [ %.1.4, %.preheader.5 ]
  %49 = tail call i32 @Xil_In32(i64 noundef %6)
  %50 = and i32 %49, 1
  %51 = icmp ne i32 %50, 0
  %52 = icmp ult i32 %.1.5, 4000
  %53 = select i1 %51, i1 %52, i1 false
  %54 = add nuw nsw i32 %.1.5, 1
  br i1 %53, label %48, label %.preheader.6, !llvm.loop !5

.preheader.6:                                     ; preds = %48
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 66817)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %55

55:                                               ; preds = %55, %.preheader.6
  %.1.6 = phi i32 [ %61, %55 ], [ %.1.5, %.preheader.6 ]
  %56 = tail call i32 @Xil_In32(i64 noundef %6)
  %57 = and i32 %56, 1
  %58 = icmp ne i32 %57, 0
  %59 = icmp ult i32 %.1.6, 4000
  %60 = select i1 %58, i1 %59, i1 false
  %61 = add nuw nsw i32 %.1.6, 1
  br i1 %60, label %55, label %.preheader.7, !llvm.loop !5

.preheader.7:                                     ; preds = %55
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 67073)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  br label %62

62:                                               ; preds = %62, %.preheader.7
  %.1.7 = phi i32 [ %68, %62 ], [ %.1.6, %.preheader.7 ]
  %63 = tail call i32 @Xil_In32(i64 noundef %6)
  %64 = and i32 %63, 1
  %65 = icmp ne i32 %64, 0
  %66 = icmp ult i32 %.1.7, 4000
  %67 = select i1 %65, i1 %66, i1 false
  %68 = add nuw nsw i32 %.1.7, 1
  br i1 %67, label %62, label %69, !llvm.loop !5

69:                                               ; preds = %62
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 67329)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %8, i32 noundef 65536)
  tail call void @Xil_Out32(i64 noundef %10, i32 noundef 0)
  tail call void @Xil_Out32(i64 noundef %12, i32 noundef 0)
  ret void
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass