; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (WritePolled)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

@TransferMode = external dso_local global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #2

declare i32 @XSdPs_SetBlkSize(ptr noundef, i16 noundef zeroext) #3

; Function Attrs: nounwind uwtable
declare dso_local void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_WritePolled(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.XSdPs, ptr %12, i32 0, i32 7
  %14 = load i8, ptr %13, align 2, !tbaa !11
  %15 = zext i8 %14 to i32
  %16 = icmp ne i32 %15, 2
  br i1 %16, label %23, label %17

17:                                               ; preds = %4
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XSdPs, ptr %18, i32 0, i32 2
  %20 = load i32, ptr %19, align 8, !tbaa !16
  %21 = and i32 %20, -1073741824
  %22 = icmp ne i32 %21, 1073741824
  br i1 %22, label %23, label %43

23:                                               ; preds = %17, %4
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XSdPs, ptr %24, i32 0, i32 0
  %26 = getelementptr inbounds %struct.XSdPs_Config, ptr %25, i32 0, i32 3
  %27 = load i32, ptr %26, align 4, !tbaa !17
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %29, label %42

29:                                               ; preds = %23
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.XSdPs, ptr %30, i32 0, i32 0
  %32 = getelementptr inbounds %struct.XSdPs_Config, ptr %31, i32 0, i32 1
  %33 = load i32, ptr %32, align 4, !tbaa !18
  %34 = add i32 %33, 36
  %35 = zext i32 %34 to i64
  %36 = call i32 @Xil_In32(i64 noundef %35)
  store i32 %36, ptr %10, align 4, !tbaa !9
  %37 = load i32, ptr %10, align 4, !tbaa !9
  %38 = and i32 %37, 65536
  %39 = icmp eq i32 %38, 0
  br i1 %39, label %40, label %41

40:                                               ; preds = %29
  store i32 1, ptr %9, align 4, !tbaa !9
  br label %133

41:                                               ; preds = %29
  br label %42

42:                                               ; preds = %41, %23
  br label %43

43:                                               ; preds = %42, %17
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.XSdPs, ptr %44, i32 0, i32 0
  %46 = getelementptr inbounds %struct.XSdPs_Config, ptr %45, i32 0, i32 1
  %47 = load i32, ptr %46, align 4, !tbaa !18
  %48 = add i32 %47, 4
  %49 = zext i32 %48 to i64
  %50 = call i32 @Xil_In32(i64 noundef %49)
  %51 = icmp ne i32 %50, 512
  br i1 %51, label %52, label %60

52:                                               ; preds = %43
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = call i32 @XSdPs_SetBlkSize(ptr noundef %53, i16 noundef zeroext 512)
  store i32 %54, ptr %9, align 4, !tbaa !9
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = sext i32 %55 to i64
  %57 = icmp ne i64 %56, 0
  br i1 %57, label %58, label %59

58:                                               ; preds = %52
  store i32 1, ptr %9, align 4, !tbaa !9
  br label %133

59:                                               ; preds = %52
  br label %60

60:                                               ; preds = %59, %43
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.XSdPs, ptr %61, i32 0, i32 20
  %63 = load i64, ptr %62, align 32, !tbaa !19
  %64 = icmp uge i64 %63, 4294967296
  br i1 %64, label %65, label %68

65:                                               ; preds = %60
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = load i32, ptr %7, align 4, !tbaa !9
  call void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef %66, i32 noundef %67)
  br label %84

68:                                               ; preds = %60
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = load i32, ptr %7, align 4, !tbaa !9
  %71 = load ptr, ptr %8, align 8, !tbaa !5
  call void @XSdPs_SetupADMA2DescTbl(ptr noundef %69, i32 noundef %70, ptr noundef %71)
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.XSdPs, ptr %72, i32 0, i32 0
  %74 = getelementptr inbounds %struct.XSdPs_Config, ptr %73, i32 0, i32 8
  %75 = load i8, ptr %74, align 32, !tbaa !20
  %76 = zext i8 %75 to i32
  %77 = icmp eq i32 %76, 0
  br i1 %77, label %78, label %83

78:                                               ; preds = %68
  %79 = load ptr, ptr %8, align 8, !tbaa !5
  %80 = ptrtoint ptr %79 to i64
  %81 = load i32, ptr %7, align 4, !tbaa !9
  %82 = mul i32 %81, 512
  call void @Xil_DCacheFlushRange(i64 noundef %80, i32 noundef %82)
  br label %83

83:                                               ; preds = %78, %68
  br label %84

84:                                               ; preds = %83, %65
  %85 = load i32, ptr %7, align 4, !tbaa !9
  %86 = icmp eq i32 %85, 1
  br i1 %86, label %87, label %97

87:                                               ; preds = %84
  store i16 3, ptr @TransferMode, align 2, !tbaa !21
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  %89 = load i32, ptr %6, align 4, !tbaa !9
  %90 = load i32, ptr %7, align 4, !tbaa !9
  %91 = call i32 @XSdPs_CmdTransfer(ptr noundef %88, i32 noundef 6144, i32 noundef %89, i32 noundef %90)
  store i32 %91, ptr %9, align 4, !tbaa !9
  %92 = load i32, ptr %9, align 4, !tbaa !9
  %93 = sext i32 %92 to i64
  %94 = icmp ne i64 %93, 0
  br i1 %94, label %95, label %96

95:                                               ; preds = %87
  store i32 1, ptr %9, align 4, !tbaa !9
  br label %133

96:                                               ; preds = %87
  br label %107

97:                                               ; preds = %84
  store i16 39, ptr @TransferMode, align 2, !tbaa !21
  %98 = load ptr, ptr %5, align 8, !tbaa !5
  %99 = load i32, ptr %6, align 4, !tbaa !9
  %100 = load i32, ptr %7, align 4, !tbaa !9
  %101 = call i32 @XSdPs_CmdTransfer(ptr noundef %98, i32 noundef 6400, i32 noundef %99, i32 noundef %100)
  store i32 %101, ptr %9, align 4, !tbaa !9
  %102 = load i32, ptr %9, align 4, !tbaa !9
  %103 = sext i32 %102 to i64
  %104 = icmp ne i64 %103, 0
  br i1 %104, label %105, label %106

105:                                              ; preds = %97
  store i32 1, ptr %9, align 4, !tbaa !9
  br label %133

106:                                              ; preds = %97
  br label %107

107:                                              ; preds = %106, %96
  br label %108

108:                                              ; preds = %124, %107
  %109 = load ptr, ptr %5, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.XSdPs, ptr %109, i32 0, i32 0
  %111 = getelementptr inbounds %struct.XSdPs_Config, ptr %110, i32 0, i32 1
  %112 = load i32, ptr %111, align 4, !tbaa !18
  %113 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %112, i8 noundef zeroext 48)
  %114 = zext i16 %113 to i32
  store i32 %114, ptr %11, align 4, !tbaa !9
  %115 = load i32, ptr %11, align 4, !tbaa !9
  %116 = and i32 %115, 32768
  %117 = icmp ne i32 %116, 0
  br i1 %117, label %118, label %123

118:                                              ; preds = %108
  %119 = load ptr, ptr %5, align 8, !tbaa !5
  %120 = getelementptr inbounds %struct.XSdPs, ptr %119, i32 0, i32 0
  %121 = getelementptr inbounds %struct.XSdPs_Config, ptr %120, i32 0, i32 1
  %122 = load i32, ptr %121, align 4, !tbaa !18
  call void @XSdPs_WriteReg16(i32 noundef %122, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  store i32 1, ptr %9, align 4, !tbaa !9
  br label %133

123:                                              ; preds = %108
  br label %124

124:                                              ; preds = %123
  %125 = load i32, ptr %11, align 4, !tbaa !9
  %126 = and i32 %125, 2
  %127 = icmp eq i32 %126, 0
  br i1 %127, label %108, label %128, !llvm.loop !22

128:                                              ; preds = %124
  %129 = load ptr, ptr %5, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.XSdPs, ptr %129, i32 0, i32 0
  %131 = getelementptr inbounds %struct.XSdPs_Config, ptr %130, i32 0, i32 1
  %132 = load i32, ptr %131, align 4, !tbaa !18
  call void @XSdPs_WriteReg16(i32 noundef %132, i8 noundef zeroext 48, i16 noundef zeroext 2)
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %133

133:                                              ; preds = %128, %118, %105, %95, %58, %40
  %134 = load i32, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  ret i32 %134
}

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 54}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !15, i64 512}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !10, i64 40}
!17 = !{!12, !10, i64 12}
!18 = !{!12, !10, i64 4}
!19 = !{!12, !15, i64 512}
!20 = !{!12, !7, i64 32}
!21 = !{!14, !14, i64 0}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@TransferMode = external dso_local local_unnamed_addr global i16, align 2

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare i32 @XSdPs_SetBlkSize(ptr noundef, i16 noundef zeroext) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_WritePolled(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) local_unnamed_addr #1 {
  %5 = getelementptr inbounds i8, ptr %0, i64 54
  %6 = load i8, ptr %5, align 2, !tbaa !5
  %.not = icmp eq i8 %6, 2
  br i1 %.not, label %7, label %11

7:                                                ; preds = %4
  %8 = getelementptr inbounds i8, ptr %0, i64 40
  %9 = load i32, ptr %8, align 8, !tbaa !14
  %10 = and i32 %9, -1073741824
  %.not32 = icmp eq i32 %10, 1073741824
  br i1 %.not32, label %22, label %11

11:                                               ; preds = %7, %4
  %12 = getelementptr inbounds i8, ptr %0, i64 12
  %13 = load i32, ptr %12, align 4, !tbaa !15
  %.not33 = icmp eq i32 %13, 0
  br i1 %.not33, label %22, label %14

14:                                               ; preds = %11
  %15 = getelementptr inbounds i8, ptr %0, i64 4
  %16 = load i32, ptr %15, align 4, !tbaa !16
  %17 = add i32 %16, 36
  %18 = zext i32 %17 to i64
  %19 = tail call i32 @Xil_In32(i64 noundef %18)
  %20 = and i32 %19, 65536
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %58, label %22

22:                                               ; preds = %11, %14, %7
  %23 = getelementptr inbounds i8, ptr %0, i64 4
  %24 = load i32, ptr %23, align 4, !tbaa !16
  %25 = add i32 %24, 4
  %26 = zext i32 %25 to i64
  %27 = tail call i32 @Xil_In32(i64 noundef %26)
  %.not34 = icmp eq i32 %27, 512
  br i1 %.not34, label %30, label %28

28:                                               ; preds = %22
  %29 = tail call i32 @XSdPs_SetBlkSize(ptr noundef nonnull %0, i16 noundef zeroext 512) #3
  %.not35 = icmp eq i32 %29, 0
  br i1 %.not35, label %30, label %58

30:                                               ; preds = %28, %22
  %31 = getelementptr inbounds i8, ptr %0, i64 512
  %32 = load i64, ptr %31, align 32, !tbaa !17
  %33 = icmp ugt i64 %32, 4294967295
  br i1 %33, label %34, label %35

34:                                               ; preds = %30
  tail call void @XSdPs_SetupADMA2DescTbl64Bit(ptr noundef nonnull %0, i32 noundef %2)
  br label %42

35:                                               ; preds = %30
  tail call void @XSdPs_SetupADMA2DescTbl(ptr noundef nonnull %0, i32 noundef %2, ptr noundef %3)
  %36 = getelementptr inbounds i8, ptr %0, i64 32
  %37 = load i8, ptr %36, align 32, !tbaa !18
  %38 = icmp eq i8 %37, 0
  br i1 %38, label %39, label %42

39:                                               ; preds = %35
  %40 = ptrtoint ptr %3 to i64
  %41 = shl i32 %2, 9
  tail call void @Xil_DCacheFlushRange(i64 noundef %40, i32 noundef %41) #3
  br label %42

42:                                               ; preds = %35, %39, %34
  %43 = icmp eq i32 %2, 1
  br i1 %43, label %44, label %46

44:                                               ; preds = %42
  store i16 3, ptr @TransferMode, align 2, !tbaa !19
  %45 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 6144, i32 noundef %1, i32 noundef 1)
  %.not37 = icmp eq i32 %45, 0
  br i1 %.not37, label %.preheader, label %58

46:                                               ; preds = %42
  store i16 39, ptr @TransferMode, align 2, !tbaa !19
  %47 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 6400, i32 noundef %1, i32 noundef %2)
  %.not36 = icmp eq i32 %47, 0
  br i1 %.not36, label %.preheader, label %58

.preheader:                                       ; preds = %46, %44
  br label %48

48:                                               ; preds = %.preheader, %53
  %49 = load i32, ptr %23, align 4, !tbaa !16
  %50 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %49, i8 noundef zeroext 48)
  %.not38 = icmp sgt i16 %50, -1
  br i1 %.not38, label %53, label %51

51:                                               ; preds = %48
  %52 = load i32, ptr %23, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %52, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %58

53:                                               ; preds = %48
  %54 = and i16 %50, 2
  %55 = icmp eq i16 %54, 0
  br i1 %55, label %48, label %56, !llvm.loop !20

56:                                               ; preds = %53
  %57 = load i32, ptr %23, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %57, i8 noundef zeroext 48, i16 noundef zeroext 2)
  br label %58

58:                                               ; preds = %46, %44, %28, %14, %56, %51
  %.0 = phi i32 [ 1, %51 ], [ 0, %56 ], [ 1, %14 ], [ 1, %28 ], [ 1, %44 ], [ 1, %46 ]
  ret i32 %.0
}

declare void @Xil_DCacheFlushRange(i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 54}
!6 = !{!"", !7, i64 0, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !9, i64 52, !9, i64 53, !9, i64 54, !9, i64 55, !11, i64 56, !9, i64 60, !9, i64 64, !11, i64 80, !9, i64 84, !11, i64 100, !11, i64 104, !11, i64 108, !12, i64 112, !9, i64 128, !13, i64 512}
!7 = !{!"", !8, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !11, i64 16, !11, i64 20, !11, i64 24, !11, i64 28, !9, i64 32}
!8 = !{!"short", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"any pointer", !9, i64 0}
!13 = !{!"long", !9, i64 0}
!14 = !{!6, !11, i64 40}
!15 = !{!6, !11, i64 12}
!16 = !{!6, !11, i64 4}
!17 = !{!6, !13, i64 512}
!18 = !{!6, !9, i64 32}
!19 = !{!8, !8, i64 0}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass