; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (CfgInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs_Config = type { i16, i32 }
%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XAdcPs_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 110)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %56

14:                                               ; preds = %12
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp ne ptr %15, null
  br i1 %16, label %17, label %18

17:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 111)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %56

19:                                               ; preds = %17
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.XAdcPs_Config, ptr %20, i32 0, i32 0
  %22 = load i16, ptr %21, align 4, !tbaa !11
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.XAdcPs, ptr %23, i32 0, i32 0
  %25 = getelementptr inbounds %struct.XAdcPs_Config, ptr %24, i32 0, i32 0
  store i16 %22, ptr %25, align 4, !tbaa !14
  %26 = load i32, ptr %7, align 4, !tbaa !9
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.XAdcPs, ptr %27, i32 0, i32 0
  %29 = getelementptr inbounds %struct.XAdcPs_Config, ptr %28, i32 0, i32 1
  store i32 %26, ptr %29, align 4, !tbaa !16
  call void @Xil_Out32(i64 noundef 4160778292, i32 noundef 1971052301)
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.XAdcPs, ptr %30, i32 0, i32 0
  %32 = getelementptr inbounds %struct.XAdcPs_Config, ptr %31, i32 0, i32 1
  %33 = load i32, ptr %32, align 4, !tbaa !16
  %34 = add i32 %33, 0
  %35 = zext i32 %34 to i64
  %36 = call i32 @Xil_In32(i64 noundef %35)
  store i32 %36, ptr %8, align 4, !tbaa !9
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = or i32 %37, -2147483648
  %39 = or i32 %38, 15728640
  %40 = or i32 %39, 983040
  store i32 %40, ptr %8, align 4, !tbaa !9
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.XAdcPs, ptr %41, i32 0, i32 0
  %43 = getelementptr inbounds %struct.XAdcPs_Config, ptr %42, i32 0, i32 1
  %44 = load i32, ptr %43, align 4, !tbaa !16
  %45 = add i32 %44, 0
  %46 = zext i32 %45 to i64
  %47 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %46, i32 noundef %47)
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.XAdcPs, ptr %48, i32 0, i32 0
  %50 = getelementptr inbounds %struct.XAdcPs_Config, ptr %49, i32 0, i32 1
  %51 = load i32, ptr %50, align 4, !tbaa !16
  %52 = add i32 %51, 24
  %53 = zext i32 %52 to i64
  call void @Xil_Out32(i64 noundef %53, i32 noundef 0)
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.XAdcPs, ptr %54, i32 0, i32 1
  store i32 286331153, ptr %55, align 4, !tbaa !17
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %56

56:                                               ; preds = %19, %18, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %57 = load i32, ptr %4, align 4
  ret i32 %57
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"", !13, i64 0, !10, i64 4}
!13 = !{!"short", !7, i64 0}
!14 = !{!15, !13, i64 0}
!15 = !{!"", !12, i64 0, !10, i64 8}
!16 = !{!15, !10, i64 4}
!17 = !{!15, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @XAdcPs_CfgInitialize(ptr noundef %0, ptr noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %5, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not13 = icmp eq ptr %1, null
  br i1 %.not13, label %19, label %6

5:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 110) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

6:                                                ; preds = %4
  %7 = load i16, ptr %1, align 4, !tbaa !9
  store i16 %7, ptr %0, align 4, !tbaa !12
  %8 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 %2, ptr %8, align 4, !tbaa !14
  tail call void @Xil_Out32(i64 noundef 4160778292, i32 noundef 1971052301)
  %9 = load i32, ptr %8, align 4, !tbaa !14
  %10 = zext i32 %9 to i64
  %11 = tail call i32 @Xil_In32(i64 noundef %10)
  %12 = or i32 %11, -2130771968
  %13 = load i32, ptr %8, align 4, !tbaa !14
  %14 = zext i32 %13 to i64
  tail call void @Xil_Out32(i64 noundef %14, i32 noundef %12)
  %15 = load i32, ptr %8, align 4, !tbaa !14
  %16 = add i32 %15, 24
  %17 = zext i32 %16 to i64
  tail call void @Xil_Out32(i64 noundef %17, i32 noundef 0)
  %18 = getelementptr inbounds i8, ptr %0, i64 8
  store i32 286331153, ptr %18, align 4, !tbaa !15
  br label %20

19:                                               ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 111) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %6, %19, %5
  ret i32 0
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !6, i64 4}
!11 = !{!"short", !7, i64 0}
!12 = !{!13, !11, i64 0}
!13 = !{!"", !10, i64 0, !6, i64 8}
!14 = !{!13, !6, i64 4}
!15 = !{!13, !6, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass