; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (CfgInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@CpuId = external hidden global i32, align 4
@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XScuGic_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load i32, ptr @CpuId, align 4, !tbaa !9
  %12 = add i32 %11, 1
  store i32 %12, ptr %9, align 4, !tbaa !9
  %13 = load i32, ptr %7, align 4, !tbaa !9
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %18

17:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 380)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %78

18:                                               ; preds = %16
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = icmp ne ptr %19, null
  br i1 %20, label %21, label %22

21:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %23

22:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 381)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %78

23:                                               ; preds = %21
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XScuGic, ptr %24, i32 0, i32 1
  %26 = load i32, ptr %25, align 8, !tbaa !11
  %27 = icmp ne i32 %26, 286331153
  br i1 %27, label %28, label %77

28:                                               ; preds = %23
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.XScuGic, ptr %29, i32 0, i32 1
  store i32 0, ptr %30, align 8, !tbaa !11
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = load ptr, ptr %5, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.XScuGic, ptr %32, i32 0, i32 0
  store ptr %31, ptr %33, align 8, !tbaa !13
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %34

34:                                               ; preds = %67, %28
  %35 = load i32, ptr %8, align 4, !tbaa !9
  %36 = icmp ult i32 %35, 95
  br i1 %36, label %37, label %70

37:                                               ; preds = %34
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XScuGic, ptr %38, i32 0, i32 0
  %40 = load ptr, ptr %39, align 8, !tbaa !13
  %41 = getelementptr inbounds %struct.XScuGic_Config, ptr %40, i32 0, i32 3
  %42 = load i32, ptr %8, align 4, !tbaa !9
  %43 = zext i32 %42 to i64
  %44 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %41, i64 0, i64 %43
  %45 = getelementptr inbounds %struct.XScuGic_VectorTableEntry, ptr %44, i32 0, i32 0
  %46 = load ptr, ptr %45, align 8, !tbaa !14
  %47 = icmp eq ptr %46, null
  br i1 %47, label %48, label %57

48:                                               ; preds = %37
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XScuGic, ptr %49, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !13
  %52 = getelementptr inbounds %struct.XScuGic_Config, ptr %51, i32 0, i32 3
  %53 = load i32, ptr %8, align 4, !tbaa !9
  %54 = zext i32 %53 to i64
  %55 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %52, i64 0, i64 %54
  %56 = getelementptr inbounds %struct.XScuGic_VectorTableEntry, ptr %55, i32 0, i32 0
  store ptr @StubHandler, ptr %56, align 8, !tbaa !14
  br label %57

57:                                               ; preds = %48, %37
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.XScuGic, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !13
  %62 = getelementptr inbounds %struct.XScuGic_Config, ptr %61, i32 0, i32 3
  %63 = load i32, ptr %8, align 4, !tbaa !9
  %64 = zext i32 %63 to i64
  %65 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %62, i64 0, i64 %64
  %66 = getelementptr inbounds %struct.XScuGic_VectorTableEntry, ptr %65, i32 0, i32 1
  store ptr %58, ptr %66, align 8, !tbaa !16
  br label %67

67:                                               ; preds = %57
  %68 = load i32, ptr %8, align 4, !tbaa !9
  %69 = add i32 %68, 1
  store i32 %69, ptr %8, align 4, !tbaa !9
  br label %34, !llvm.loop !17

70:                                               ; preds = %34
  %71 = load ptr, ptr %5, align 8, !tbaa !5
  call void @XScuGic_Stop(ptr noundef %71)
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = load i32, ptr %9, align 4, !tbaa !9
  call void @DistributorInit(ptr noundef %72, i32 noundef %73)
  %74 = load ptr, ptr %5, align 8, !tbaa !5
  call void @CPUInitialize(ptr noundef %74)
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.XScuGic, ptr %75, i32 0, i32 1
  store i32 286331153, ptr %76, align 8, !tbaa !11
  br label %77

77:                                               ; preds = %70, %23
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %78

78:                                               ; preds = %77, %22, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %79 = load i32, ptr %4, align 4
  ret i32 %79
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @StubHandler(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XScuGic_Stop(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @DistributorInit(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
declare hidden void @CPUInitialize(ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!12, !6, i64 0}
!14 = !{!15, !6, i64 0}
!15 = !{!"", !6, i64 0, !6, i64 8}
!16 = !{!15, !6, i64 8}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@CpuId = external hidden local_unnamed_addr global i32, align 4
@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @XScuGic_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = load i32, ptr @CpuId, align 4, !tbaa !5
  %5 = add i32 %4, 1
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %6

6:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not23 = icmp eq ptr %1, null
  br i1 %.not23, label %11, label %8

7:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 380) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

8:                                                ; preds = %6
  %9 = getelementptr inbounds i8, ptr %0, i64 8
  %10 = load i32, ptr %9, align 8, !tbaa !9
  %.not24 = icmp eq i32 %10, 286331153
  br i1 %.not24, label %29, label %12

11:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 381) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %29

12:                                               ; preds = %8
  store i32 0, ptr %9, align 8, !tbaa !9
  store ptr %1, ptr %0, align 8, !tbaa !12
  %13 = getelementptr inbounds i8, ptr %1, i64 16
  br label %14

14:                                               ; preds = %26, %12
  %indvars.iv = phi i64 [ 0, %12 ], [ %indvars.iv.next.1, %26 ]
  %15 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %13, i64 0, i64 %indvars.iv
  %16 = load ptr, ptr %15, align 8, !tbaa !13
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %14
  store ptr @StubHandler, ptr %15, align 8, !tbaa !13
  br label %19

19:                                               ; preds = %18, %14
  %20 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %13, i64 0, i64 %indvars.iv, i32 1
  store ptr %0, ptr %20, align 8, !tbaa !15
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv, 94
  br i1 %exitcond.not, label %28, label %21, !llvm.loop !16

21:                                               ; preds = %19
  %22 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %13, i64 0, i64 %indvars.iv.next
  %23 = load ptr, ptr %22, align 8, !tbaa !13
  %24 = icmp eq ptr %23, null
  br i1 %24, label %25, label %26

25:                                               ; preds = %21
  store ptr @StubHandler, ptr %22, align 8, !tbaa !13
  br label %26

26:                                               ; preds = %25, %21
  %27 = getelementptr inbounds [95 x %struct.XScuGic_VectorTableEntry], ptr %13, i64 0, i64 %indvars.iv.next, i32 1
  store ptr %0, ptr %27, align 8, !tbaa !15
  %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
  br label %14

28:                                               ; preds = %19
  tail call void @XScuGic_Stop(ptr noundef nonnull %0)
  tail call void @DistributorInit(ptr noundef nonnull %0, i32 noundef %5)
  tail call void @CPUInitialize(ptr noundef nonnull %0)
  store i32 286331153, ptr %9, align 8, !tbaa !9
  br label %29

29:                                               ; preds = %8, %28, %11, %7
  ret i32 0
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @StubHandler(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local void @XScuGic_Stop(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @DistributorInit(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @CPUInitialize(ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !11, i64 0}
!14 = !{!"", !11, i64 0, !11, i64 8}
!15 = !{!14, !11, i64 8}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass