; LLVM IR from gokcehan/pns :: generators/netgen-bcjl-patched (random)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@saved_seed = external hidden global i64, align 8

; Function Attrs: nounwind uwtable
define dso_local i64 @randomr(i64 noundef %0, i64 noundef %1) #0 {
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  store i64 %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  %9 = load i64, ptr @saved_seed, align 8, !tbaa !5
  %10 = ashr i64 %9, 16
  %11 = mul nsw i64 16807, %10
  store i64 %11, ptr %6, align 8, !tbaa !5
  %12 = load i64, ptr @saved_seed, align 8, !tbaa !5
  %13 = and i64 %12, 65535
  %14 = mul nsw i64 16807, %13
  store i64 %14, ptr %7, align 8, !tbaa !5
  %15 = load i64, ptr %7, align 8, !tbaa !5
  %16 = ashr i64 %15, 16
  %17 = load i64, ptr %6, align 8, !tbaa !5
  %18 = add nsw i64 %17, %16
  store i64 %18, ptr %6, align 8, !tbaa !5
  %19 = load i64, ptr %7, align 8, !tbaa !5
  %20 = and i64 %19, 65535
  store i64 %20, ptr %7, align 8, !tbaa !5
  %21 = load i64, ptr %6, align 8, !tbaa !5
  %22 = ashr i64 %21, 15
  %23 = load i64, ptr %7, align 8, !tbaa !5
  %24 = add nsw i64 %23, %22
  store i64 %24, ptr %7, align 8, !tbaa !5
  %25 = load i64, ptr %6, align 8, !tbaa !5
  %26 = and i64 %25, 32767
  store i64 %26, ptr %6, align 8, !tbaa !5
  %27 = load i64, ptr %7, align 8, !tbaa !5
  %28 = sub nsw i64 %27, 2147483647
  store i64 %28, ptr %7, align 8, !tbaa !5
  %29 = load i64, ptr %6, align 8, !tbaa !5
  %30 = shl i64 %29, 16
  %31 = load i64, ptr %7, align 8, !tbaa !5
  %32 = add nsw i64 %30, %31
  store i64 %32, ptr @saved_seed, align 8, !tbaa !5
  %33 = icmp slt i64 %32, 0
  br i1 %33, label %34, label %37

34:                                               ; preds = %2
  %35 = load i64, ptr @saved_seed, align 8, !tbaa !5
  %36 = add nsw i64 %35, 2147483647
  store i64 %36, ptr @saved_seed, align 8, !tbaa !5
  br label %37

37:                                               ; preds = %34, %2
  %38 = load i64, ptr %5, align 8, !tbaa !5
  %39 = load i64, ptr %4, align 8, !tbaa !5
  %40 = icmp sle i64 %38, %39
  br i1 %40, label %41, label %43

41:                                               ; preds = %37
  %42 = load i64, ptr %5, align 8, !tbaa !5
  store i64 %42, ptr %3, align 8
  store i32 1, ptr %8, align 4
  br label %52

43:                                               ; preds = %37
  %44 = load i64, ptr %4, align 8, !tbaa !5
  %45 = load i64, ptr @saved_seed, align 8, !tbaa !5
  %46 = load i64, ptr %5, align 8, !tbaa !5
  %47 = load i64, ptr %4, align 8, !tbaa !5
  %48 = sub nsw i64 %46, %47
  %49 = add nsw i64 %48, 1
  %50 = srem i64 %45, %49
  %51 = add nsw i64 %44, %50
  store i64 %51, ptr %3, align 8
  store i32 1, ptr %8, align 4
  br label %52

52:                                               ; preds = %43, %41
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  %53 = load i64, ptr %3, align 8
  ret i64 %53
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@saved_seed = external hidden local_unnamed_addr global i64, align 8

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) uwtable
define dso_local i64 @randomr(i64 noundef %0, i64 noundef %1) local_unnamed_addr #0 {
  %3 = load i64, ptr @saved_seed, align 8, !tbaa !5
  %4 = ashr i64 %3, 16
  %5 = mul nsw i64 %4, 16807
  %6 = and i64 %3, 65535
  %7 = mul nuw nsw i64 %6, 16807
  %8 = lshr i64 %7, 16
  %9 = add nsw i64 %8, %5
  %10 = and i64 %7, 65535
  %11 = ashr i64 %9, 15
  %12 = add nsw i64 %11, %10
  %13 = shl i64 %9, 16
  %14 = and i64 %13, 2147418112
  %15 = add nsw i64 %14, %12
  %16 = add nsw i64 %15, -2147483647
  %17 = icmp slt i64 %15, 2147483647
  %spec.select = select i1 %17, i64 %15, i64 %16
  store i64 %spec.select, ptr @saved_seed, align 8, !tbaa !5
  %.not = icmp sgt i64 %1, %0
  br i1 %.not, label %18, label %22

18:                                               ; preds = %2
  %reass.sub = sub i64 %1, %0
  %19 = add i64 %reass.sub, 1
  %20 = srem i64 %spec.select, %19
  %21 = add nsw i64 %20, %0
  br label %22

22:                                               ; preds = %2, %18
  %.0 = phi i64 [ %21, %18 ], [ %1, %2 ]
  ret i64 %.0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass