; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (GetPriorityTriggerType)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_GetPriorityTriggerType(ptr noundef %0, i32 noundef %1, ptr noundef %2, ptr noundef %3) #3 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = icmp ne ptr %11, null
  br i1 %12, label %13, label %14

13:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %15

14:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 791)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %80

15:                                               ; preds = %13
  %16 = load ptr, ptr %5, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.XScuGic, ptr %16, i32 0, i32 1
  %18 = load i32, ptr %17, align 8, !tbaa !11
  %19 = icmp eq i32 %18, 286331153
  br i1 %19, label %20, label %21

20:                                               ; preds = %15
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %22

21:                                               ; preds = %15
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 792)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %80

22:                                               ; preds = %20
  %23 = load i32, ptr %6, align 4, !tbaa !9
  %24 = icmp ult i32 %23, 95
  br i1 %24, label %25, label %26

25:                                               ; preds = %22
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %27

26:                                               ; preds = %22
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 793)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %80

27:                                               ; preds = %25
  %28 = load ptr, ptr %7, align 8, !tbaa !5
  %29 = icmp ne ptr %28, null
  br i1 %29, label %30, label %31

30:                                               ; preds = %27
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %32

31:                                               ; preds = %27
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 794)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %80

32:                                               ; preds = %30
  %33 = load ptr, ptr %8, align 8, !tbaa !5
  %34 = icmp ne ptr %33, null
  br i1 %34, label %35, label %36

35:                                               ; preds = %32
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %37

36:                                               ; preds = %32
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 795)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 1, ptr %10, align 4
  br label %80

37:                                               ; preds = %35
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.XScuGic, ptr %38, i32 0, i32 0
  %40 = load ptr, ptr %39, align 8, !tbaa !13
  %41 = getelementptr inbounds %struct.XScuGic_Config, ptr %40, i32 0, i32 2
  %42 = load i32, ptr %41, align 8, !tbaa !14
  %43 = load i32, ptr %6, align 4, !tbaa !9
  %44 = udiv i32 %43, 4
  %45 = mul i32 %44, 4
  %46 = add i32 1024, %45
  %47 = add i32 %42, %46
  %48 = zext i32 %47 to i64
  %49 = call i32 @Xil_In32(i64 noundef %48)
  store i32 %49, ptr %9, align 4, !tbaa !9
  %50 = load i32, ptr %9, align 4, !tbaa !9
  %51 = load i32, ptr %6, align 4, !tbaa !9
  %52 = urem i32 %51, 4
  %53 = mul i32 %52, 8
  %54 = lshr i32 %50, %53
  store i32 %54, ptr %9, align 4, !tbaa !9
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = and i32 %55, 255
  %57 = trunc i32 %56 to i8
  %58 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 %57, ptr %58, align 1, !tbaa !17
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.XScuGic, ptr %59, i32 0, i32 0
  %61 = load ptr, ptr %60, align 8, !tbaa !13
  %62 = getelementptr inbounds %struct.XScuGic_Config, ptr %61, i32 0, i32 2
  %63 = load i32, ptr %62, align 8, !tbaa !14
  %64 = load i32, ptr %6, align 4, !tbaa !9
  %65 = udiv i32 %64, 16
  %66 = mul i32 %65, 4
  %67 = add i32 3072, %66
  %68 = add i32 %63, %67
  %69 = zext i32 %68 to i64
  %70 = call i32 @Xil_In32(i64 noundef %69)
  store i32 %70, ptr %9, align 4, !tbaa !9
  %71 = load i32, ptr %9, align 4, !tbaa !9
  %72 = load i32, ptr %6, align 4, !tbaa !9
  %73 = urem i32 %72, 16
  %74 = mul i32 %73, 2
  %75 = lshr i32 %71, %74
  store i32 %75, ptr %9, align 4, !tbaa !9
  %76 = load i32, ptr %9, align 4, !tbaa !9
  %77 = and i32 %76, 3
  %78 = trunc i32 %77 to i8
  %79 = load ptr, ptr %8, align 8, !tbaa !5
  store i8 %78, ptr %79, align 1, !tbaa !17
  store i32 0, ptr %10, align 4
  br label %80

80:                                               ; preds = %37, %36, %31, %26, %21, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  %81 = load i32, ptr %10, align 4
  switch i32 %81, label %83 [
    i32 0, label %82
    i32 1, label %82
  ]

82:                                               ; preds = %80, %80
  ret void

83:                                               ; preds = %80
  unreachable
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!12, !6, i64 0}
!14 = !{!15, !10, i64 8}
!15 = !{!"", !16, i64 0, !10, i64 4, !10, i64 8, !7, i64 16}
!16 = !{!"short", !7, i64 0}
!17 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XScuGic_GetPriorityTriggerType(ptr noundef readonly %0, i32 noundef %1, ptr noundef writeonly %2, ptr noundef writeonly %3) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load i32, ptr %6, align 8, !tbaa !9
  %8 = icmp eq i32 %7, 286331153
  br i1 %8, label %10, label %12

9:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 791) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

10:                                               ; preds = %5
  %11 = icmp ult i32 %1, 95
  br i1 %11, label %13, label %14

12:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 792) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

13:                                               ; preds = %10
  %.not19 = icmp eq ptr %2, null
  br i1 %.not19, label %16, label %15

14:                                               ; preds = %10
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 793) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

15:                                               ; preds = %13
  %.not20 = icmp eq ptr %3, null
  br i1 %.not20, label %44, label %17

16:                                               ; preds = %13
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 794) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

17:                                               ; preds = %15
  %18 = load ptr, ptr %0, align 8, !tbaa !12
  %19 = getelementptr inbounds i8, ptr %18, i64 8
  %20 = load i32, ptr %19, align 8, !tbaa !13
  %21 = and i32 %1, 124
  %22 = or disjoint i32 %21, 1024
  %23 = add i32 %22, %20
  %24 = zext i32 %23 to i64
  %25 = tail call i32 @Xil_In32(i64 noundef %24)
  %26 = shl nuw nsw i32 %1, 3
  %27 = and i32 %26, 24
  %28 = lshr i32 %25, %27
  %29 = trunc i32 %28 to i8
  store i8 %29, ptr %2, align 1, !tbaa !16
  %30 = load ptr, ptr %0, align 8, !tbaa !12
  %31 = getelementptr inbounds i8, ptr %30, i64 8
  %32 = load i32, ptr %31, align 8, !tbaa !13
  %33 = lshr i32 %1, 2
  %34 = and i32 %33, 28
  %35 = or disjoint i32 %34, 3072
  %36 = add i32 %35, %32
  %37 = zext i32 %36 to i64
  %38 = tail call i32 @Xil_In32(i64 noundef %37)
  %39 = shl nuw nsw i32 %1, 1
  %40 = and i32 %39, 30
  %41 = lshr i32 %38, %40
  %42 = trunc i32 %41 to i8
  %43 = and i8 %42, 3
  store i8 %43, ptr %3, align 1, !tbaa !16
  br label %45

44:                                               ; preds = %15
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 795) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %45

45:                                               ; preds = %17, %44, %16, %14, %12, %9
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}
!16 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass