; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/xadcps_v2 (GetAlarmThreshold)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XAdcPs = type { %struct.XAdcPs_Config, i32 }
%struct.XAdcPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @XAdcPs_GetAlarmThreshold(ptr noundef %0, i8 noundef zeroext %1) #2 {
  %3 = alloca i16, align 2
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = icmp ne ptr %8, null
  br i1 %9, label %10, label %11

10:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %12

11:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1445)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i16 0, ptr %3, align 2
  store i32 1, ptr %7, align 4
  br label %33

12:                                               ; preds = %10
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.XAdcPs, ptr %13, i32 0, i32 1
  %15 = load i32, ptr %14, align 4, !tbaa !12
  %16 = icmp eq i32 %15, 286331153
  br i1 %16, label %17, label %18

17:                                               ; preds = %12
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %19

18:                                               ; preds = %12
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1446)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i16 0, ptr %3, align 2
  store i32 1, ptr %7, align 4
  br label %33

19:                                               ; preds = %17
  %20 = load i8, ptr %5, align 1, !tbaa !9
  %21 = zext i8 %20 to i32
  %22 = icmp sle i32 %21, 15
  br i1 %22, label %23, label %24

23:                                               ; preds = %19
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %25

24:                                               ; preds = %19
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1447)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i16 0, ptr %3, align 2
  store i32 1, ptr %7, align 4
  br label %33

25:                                               ; preds = %23
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = load i8, ptr %5, align 1, !tbaa !9
  %28 = zext i8 %27 to i32
  %29 = add nsw i32 80, %28
  %30 = call i32 @XAdcPs_ReadInternalReg(ptr noundef %26, i32 noundef %29)
  store i32 %30, ptr %6, align 4, !tbaa !10
  %31 = load i32, ptr %6, align 4, !tbaa !10
  %32 = trunc i32 %31 to i16
  store i16 %32, ptr %3, align 2
  store i32 1, ptr %7, align 4
  br label %33

33:                                               ; preds = %25, %24, %18, %11
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %34 = load i16, ptr %3, align 2
  ret i16 %34
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !14, i64 0, !11, i64 8}
!14 = !{!"", !15, i64 0, !11, i64 4}
!15 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [162 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @XAdcPs_ReadInternalReg(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @XAdcPs_GetAlarmThreshold(ptr noundef %0, i8 noundef zeroext %1) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %10

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1445) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %17

8:                                                ; preds = %3
  %9 = icmp ult i8 %1, 16
  br i1 %9, label %11, label %16

10:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1446) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %17

11:                                               ; preds = %8
  %12 = or disjoint i8 %1, 80
  %13 = zext nneg i8 %12 to i32
  %14 = tail call i32 @XAdcPs_ReadInternalReg(ptr noundef nonnull %0, i32 noundef %13)
  %15 = trunc i32 %14 to i16
  br label %17

16:                                               ; preds = %8
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1447) #2
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %17

17:                                               ; preds = %11, %16, %10, %7
  %.0 = phi i16 [ %15, %11 ], [ 0, %16 ], [ 0, %10 ], [ 0, %7 ]
  ret i16 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass