; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (Read)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XGpioPs_Read(ptr noundef %0, i8 noundef zeroext %1) #1 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  %7 = icmp ne ptr %6, null
  br i1 %7, label %8, label %9

8:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %10

9:                                                ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 171)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %3, align 4
  br label %39

10:                                               ; preds = %8
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.XGpioPs, ptr %11, i32 0, i32 1
  %13 = load i32, ptr %12, align 8, !tbaa !12
  %14 = icmp eq i32 %13, 286331153
  br i1 %14, label %15, label %16

15:                                               ; preds = %10
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %17

16:                                               ; preds = %10
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 172)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %3, align 4
  br label %39

17:                                               ; preds = %15
  %18 = load i8, ptr %5, align 1, !tbaa !9
  %19 = zext i8 %18 to i32
  %20 = load ptr, ptr %4, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.XGpioPs, ptr %20, i32 0, i32 6
  %22 = load i8, ptr %21, align 8, !tbaa !16
  %23 = zext i8 %22 to i32
  %24 = icmp slt i32 %19, %23
  br i1 %24, label %25, label %26

25:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %27

26:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 173)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  store i32 0, ptr %3, align 4
  br label %39

27:                                               ; preds = %25
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.XGpioPs, ptr %28, i32 0, i32 0
  %30 = getelementptr inbounds %struct.XGpioPs_Config, ptr %29, i32 0, i32 1
  %31 = load i32, ptr %30, align 4, !tbaa !17
  %32 = load i8, ptr %5, align 1, !tbaa !9
  %33 = zext i8 %32 to i32
  %34 = mul i32 %33, 4
  %35 = add i32 %34, 96
  %36 = add i32 %31, %35
  %37 = zext i32 %36 to i64
  %38 = call i32 @Xil_In32(i64 noundef %37)
  store i32 %38, ptr %3, align 4
  br label %39

39:                                               ; preds = %27, %26, %16, %9
  %40 = load i32, ptr %3, align 4
  ret i32 %40
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !14, i64 0, !11, i64 8, !6, i64 16, !6, i64 24, !11, i64 32, !11, i64 36, !7, i64 40}
!14 = !{!"", !15, i64 0, !11, i64 4}
!15 = !{!"short", !7, i64 0}
!16 = !{!13, !7, i64 40}
!17 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XGpioPs_Read(ptr noundef readonly %0, i8 noundef zeroext %1) local_unnamed_addr #1 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 8
  %5 = load i32, ptr %4, align 8, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %12

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 171) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

8:                                                ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 40
  %10 = load i8, ptr %9, align 8, !tbaa !14
  %11 = icmp ugt i8 %10, %1
  br i1 %11, label %13, label %22

12:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 172) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

13:                                               ; preds = %8
  %14 = zext i8 %1 to i32
  %15 = getelementptr inbounds i8, ptr %0, i64 4
  %16 = load i32, ptr %15, align 4, !tbaa !15
  %17 = shl nuw nsw i32 %14, 2
  %18 = add nuw nsw i32 %17, 96
  %19 = add i32 %18, %16
  %20 = zext i32 %19 to i64
  %21 = tail call i32 @Xil_In32(i64 noundef %20)
  br label %23

22:                                               ; preds = %8
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 173) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

23:                                               ; preds = %13, %22, %12, %7
  %.0 = phi i32 [ %21, %13 ], [ 0, %22 ], [ 0, %12 ], [ 0, %7 ]
  ret i32 %.0
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !7, i64 40}
!15 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass