; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (CmdTransfer)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [159 x i8], align 1
@TransferMode = external dso_local global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg8(i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_CmdTransfer(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #3 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp ne ptr %15, null
  br i1 %16, label %17, label %18

17:                                               ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %4
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1105)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %162

19:                                               ; preds = %17
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.XSdPs, ptr %20, i32 0, i32 1
  %22 = load i32, ptr %21, align 4, !tbaa !11
  %23 = icmp eq i32 %22, 286331153
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %26

25:                                               ; preds = %19
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 1106)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %162

26:                                               ; preds = %24
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.XSdPs, ptr %27, i32 0, i32 0
  %29 = getelementptr inbounds %struct.XSdPs_Config, ptr %28, i32 0, i32 1
  %30 = load i32, ptr %29, align 4, !tbaa !16
  %31 = add i32 %30, 36
  %32 = zext i32 %31 to i64
  %33 = call i32 @Xil_In32(i64 noundef %32)
  store i32 %33, ptr %10, align 4, !tbaa !9
  %34 = load i32, ptr %10, align 4, !tbaa !9
  %35 = and i32 %34, 1
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %37, label %38

37:                                               ; preds = %26
  store i32 1, ptr %13, align 4, !tbaa !9
  br label %160

38:                                               ; preds = %26
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.XSdPs, ptr %39, i32 0, i32 0
  %41 = getelementptr inbounds %struct.XSdPs_Config, ptr %40, i32 0, i32 1
  %42 = load i32, ptr %41, align 4, !tbaa !16
  %43 = load i32, ptr %9, align 4, !tbaa !9
  %44 = trunc i32 %43 to i16
  call void @XSdPs_WriteReg16(i32 noundef %42, i8 noundef zeroext 6, i16 noundef zeroext %44)
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.XSdPs, ptr %45, i32 0, i32 0
  %47 = getelementptr inbounds %struct.XSdPs_Config, ptr %46, i32 0, i32 1
  %48 = load i32, ptr %47, align 4, !tbaa !16
  call void @XSdPs_WriteReg8(i32 noundef %48, i8 noundef zeroext 46, i8 noundef zeroext 14)
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XSdPs, ptr %49, i32 0, i32 0
  %51 = getelementptr inbounds %struct.XSdPs_Config, ptr %50, i32 0, i32 1
  %52 = load i32, ptr %51, align 4, !tbaa !16
  %53 = add i32 %52, 8
  %54 = zext i32 %53 to i64
  %55 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %54, i32 noundef %55)
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.XSdPs, ptr %56, i32 0, i32 0
  %58 = getelementptr inbounds %struct.XSdPs_Config, ptr %57, i32 0, i32 1
  %59 = load i32, ptr %58, align 4, !tbaa !16
  call void @XSdPs_WriteReg16(i32 noundef %59, i8 noundef zeroext 48, i16 noundef zeroext -1)
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.XSdPs, ptr %60, i32 0, i32 0
  %62 = getelementptr inbounds %struct.XSdPs_Config, ptr %61, i32 0, i32 1
  %63 = load i32, ptr %62, align 4, !tbaa !16
  call void @XSdPs_WriteReg16(i32 noundef %63, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  %65 = load i32, ptr %7, align 4, !tbaa !9
  %66 = call i32 @XSdPs_FrameCmd(ptr noundef %64, i32 noundef %65)
  store i32 %66, ptr %11, align 4, !tbaa !9
  %67 = load i32, ptr %11, align 4, !tbaa !9
  %68 = and i32 %67, 16383
  store i32 %68, ptr %11, align 4, !tbaa !9
  %69 = load i32, ptr %7, align 4, !tbaa !9
  %70 = icmp ne i32 %69, 5376
  br i1 %70, label %71, label %91

71:                                               ; preds = %38
  %72 = load i32, ptr %7, align 4, !tbaa !9
  %73 = icmp ne i32 %72, 4864
  br i1 %73, label %74, label %91

74:                                               ; preds = %71
  %75 = load ptr, ptr %6, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.XSdPs, ptr %75, i32 0, i32 0
  %77 = getelementptr inbounds %struct.XSdPs_Config, ptr %76, i32 0, i32 1
  %78 = load i32, ptr %77, align 4, !tbaa !16
  %79 = add i32 %78, 36
  %80 = zext i32 %79 to i64
  %81 = call i32 @Xil_In32(i64 noundef %80)
  store i32 %81, ptr %10, align 4, !tbaa !9
  %82 = load i32, ptr %10, align 4, !tbaa !9
  %83 = and i32 %82, 2
  %84 = icmp ne i32 %83, 0
  br i1 %84, label %85, label %90

85:                                               ; preds = %74
  %86 = load i32, ptr %11, align 4, !tbaa !9
  %87 = and i32 %86, 32
  %88 = icmp ne i32 %87, 0
  br i1 %88, label %89, label %90

89:                                               ; preds = %85
  store i32 1, ptr %13, align 4, !tbaa !9
  br label %160

90:                                               ; preds = %85, %74
  br label %91

91:                                               ; preds = %90, %71, %38
  %92 = load ptr, ptr %6, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.XSdPs, ptr %92, i32 0, i32 0
  %94 = getelementptr inbounds %struct.XSdPs_Config, ptr %93, i32 0, i32 1
  %95 = load i32, ptr %94, align 4, !tbaa !16
  %96 = add i32 %95, 12
  %97 = zext i32 %96 to i64
  %98 = load i32, ptr %11, align 4, !tbaa !9
  %99 = shl i32 %98, 16
  %100 = load i16, ptr @TransferMode, align 2, !tbaa !17
  %101 = zext i16 %100 to i32
  %102 = or i32 %99, %101
  call void @Xil_Out32(i64 noundef %97, i32 noundef %102)
  br label %103

103:                                              ; preds = %151, %91
  %104 = load ptr, ptr %6, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.XSdPs, ptr %104, i32 0, i32 0
  %106 = getelementptr inbounds %struct.XSdPs_Config, ptr %105, i32 0, i32 1
  %107 = load i32, ptr %106, align 4, !tbaa !16
  %108 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %107, i8 noundef zeroext 48)
  %109 = zext i16 %108 to i32
  store i32 %109, ptr %12, align 4, !tbaa !9
  %110 = load i32, ptr %7, align 4, !tbaa !9
  %111 = icmp eq i32 %110, 5376
  br i1 %111, label %115, label %112

112:                                              ; preds = %103
  %113 = load i32, ptr %7, align 4, !tbaa !9
  %114 = icmp eq i32 %113, 4864
  br i1 %114, label %115, label %130

115:                                              ; preds = %112, %103
  %116 = load ptr, ptr %6, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.XSdPs, ptr %116, i32 0, i32 0
  %118 = getelementptr inbounds %struct.XSdPs_Config, ptr %117, i32 0, i32 1
  %119 = load i32, ptr %118, align 4, !tbaa !16
  %120 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %119, i8 noundef zeroext 48)
  %121 = zext i16 %120 to i32
  %122 = and i32 %121, 32
  %123 = icmp ne i32 %122, 0
  br i1 %123, label %124, label %129

124:                                              ; preds = %115
  %125 = load ptr, ptr %6, align 8, !tbaa !5
  %126 = getelementptr inbounds %struct.XSdPs, ptr %125, i32 0, i32 0
  %127 = getelementptr inbounds %struct.XSdPs_Config, ptr %126, i32 0, i32 1
  %128 = load i32, ptr %127, align 4, !tbaa !16
  call void @XSdPs_WriteReg16(i32 noundef %128, i8 noundef zeroext 48, i16 noundef zeroext 32)
  br label %155

129:                                              ; preds = %115
  br label %130

130:                                              ; preds = %129, %112
  %131 = load i32, ptr %12, align 4, !tbaa !9
  %132 = and i32 %131, 32768
  %133 = icmp ne i32 %132, 0
  br i1 %133, label %134, label %150

134:                                              ; preds = %130
  %135 = load ptr, ptr %6, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.XSdPs, ptr %135, i32 0, i32 0
  %137 = getelementptr inbounds %struct.XSdPs_Config, ptr %136, i32 0, i32 1
  %138 = load i32, ptr %137, align 4, !tbaa !16
  %139 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %138, i8 noundef zeroext 50)
  %140 = zext i16 %139 to i32
  store i32 %140, ptr %13, align 4, !tbaa !9
  %141 = load i32, ptr %13, align 4, !tbaa !9
  %142 = and i32 %141, -2
  %143 = icmp eq i32 %142, 0
  br i1 %143, label %144, label %145

144:                                              ; preds = %134
  store i32 2, ptr %13, align 4, !tbaa !9
  br label %145

145:                                              ; preds = %144, %134
  %146 = load ptr, ptr %6, align 8, !tbaa !5
  %147 = getelementptr inbounds %struct.XSdPs, ptr %146, i32 0, i32 0
  %148 = getelementptr inbounds %struct.XSdPs_Config, ptr %147, i32 0, i32 1
  %149 = load i32, ptr %148, align 4, !tbaa !16
  call void @XSdPs_WriteReg16(i32 noundef %149, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %160

150:                                              ; preds = %130
  br label %151

151:                                              ; preds = %150
  %152 = load i32, ptr %12, align 4, !tbaa !9
  %153 = and i32 %152, 1
  %154 = icmp eq i32 %153, 0
  br i1 %154, label %103, label %155, !llvm.loop !18

155:                                              ; preds = %151, %124
  %156 = load ptr, ptr %6, align 8, !tbaa !5
  %157 = getelementptr inbounds %struct.XSdPs, ptr %156, i32 0, i32 0
  %158 = getelementptr inbounds %struct.XSdPs_Config, ptr %157, i32 0, i32 1
  %159 = load i32, ptr %158, align 4, !tbaa !16
  call void @XSdPs_WriteReg16(i32 noundef %159, i8 noundef zeroext 48, i16 noundef zeroext 1)
  store i32 0, ptr %13, align 4, !tbaa !9
  br label %160

160:                                              ; preds = %155, %145, %89, %37
  %161 = load i32, ptr %13, align 4, !tbaa !9
  store i32 %161, ptr %5, align 4
  store i32 1, ptr %14, align 4
  br label %162

162:                                              ; preds = %160, %25, %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  %163 = load i32, ptr %5, align 4
  ret i32 %163
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_FrameCmd(ptr noundef, i32 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !15, i64 512}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!12, !10, i64 4}
!17 = !{!14, !14, i64 0}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [159 x i8], align 1
@TransferMode = external dso_local local_unnamed_addr global i16, align 2

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg8(i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 65536) i32 @XSdPs_CmdTransfer(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %4
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 36
  %7 = load i32, ptr %6, align 4, !tbaa !9
  %8 = icmp eq i32 %7, 286331153
  br i1 %8, label %10, label %17

9:                                                ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1105) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %64

10:                                               ; preds = %5
  %11 = getelementptr inbounds i8, ptr %0, i64 4
  %12 = load i32, ptr %11, align 4, !tbaa !15
  %13 = add i32 %12, 36
  %14 = zext i32 %13 to i64
  %15 = tail call i32 @Xil_In32(i64 noundef %14)
  %16 = and i32 %15, 1
  %.not38 = icmp eq i32 %16, 0
  br i1 %.not38, label %18, label %64

17:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 1106) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %64

18:                                               ; preds = %10
  %19 = load i32, ptr %11, align 4, !tbaa !15
  %20 = trunc i32 %3 to i16
  tail call void @XSdPs_WriteReg16(i32 noundef %19, i8 noundef zeroext 6, i16 noundef zeroext %20)
  %21 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg8(i32 noundef %21, i8 noundef zeroext 46, i8 noundef zeroext 14)
  %22 = load i32, ptr %11, align 4, !tbaa !15
  %23 = add i32 %22, 8
  %24 = zext i32 %23 to i64
  tail call void @Xil_Out32(i64 noundef %24, i32 noundef %2)
  %25 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %25, i8 noundef zeroext 48, i16 noundef zeroext -1)
  %26 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %26, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  %27 = tail call i32 @XSdPs_FrameCmd(ptr noundef nonnull %0, i32 noundef %1)
  switch i32 %1, label %28 [
    i32 5376, label %35
    i32 4864, label %35
  ]

28:                                               ; preds = %18
  %29 = load i32, ptr %11, align 4, !tbaa !15
  %30 = add i32 %29, 36
  %31 = zext i32 %30 to i64
  %32 = tail call i32 @Xil_In32(i64 noundef %31)
  %33 = and i32 %32, 2
  %.not39 = icmp eq i32 %33, 0
  %34 = and i32 %27, 32
  %.not40 = icmp eq i32 %34, 0
  %or.cond = select i1 %.not39, i1 true, i1 %.not40
  br i1 %or.cond, label %35, label %64

35:                                               ; preds = %18, %18, %28
  %36 = load i32, ptr %11, align 4, !tbaa !15
  %37 = add i32 %36, 12
  %38 = zext i32 %37 to i64
  %39 = shl i32 %27, 16
  %40 = and i32 %39, 1073676288
  %41 = load i16, ptr @TransferMode, align 2, !tbaa !16
  %42 = zext i16 %41 to i32
  %43 = or disjoint i32 %40, %42
  tail call void @Xil_Out32(i64 noundef %38, i32 noundef %43)
  switch i32 %1, label %.split [
    i32 5376, label %.split.us.preheader
    i32 4864, label %.split.us.preheader
  ]

.split.us.preheader:                              ; preds = %35, %35
  br label %.split.us

.split.us:                                        ; preds = %.split.us.preheader, %50
  %44 = load i32, ptr %11, align 4, !tbaa !15
  %45 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %44, i8 noundef zeroext 48)
  %46 = load i32, ptr %11, align 4, !tbaa !15
  %47 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %46, i8 noundef zeroext 48)
  %48 = and i16 %47, 32
  %.not41.us = icmp eq i16 %48, 0
  br i1 %.not41.us, label %49, label %.split44.us

49:                                               ; preds = %.split.us
  %.not42.us = icmp sgt i16 %45, -1
  br i1 %.not42.us, label %50, label %.split46.us

50:                                               ; preds = %49
  %51 = and i16 %45, 1
  %52 = icmp eq i16 %51, 0
  br i1 %52, label %.split.us, label %.loopexit, !llvm.loop !17

.split:                                           ; preds = %35, %60
  %53 = load i32, ptr %11, align 4, !tbaa !15
  %54 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %53, i8 noundef zeroext 48)
  %.not42 = icmp sgt i16 %54, -1
  br i1 %.not42, label %60, label %.split46.us

.split44.us:                                      ; preds = %.split.us
  %55 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %55, i8 noundef zeroext 48, i16 noundef zeroext 32)
  br label %.loopexit

.split46.us:                                      ; preds = %49, %.split
  %56 = load i32, ptr %11, align 4, !tbaa !15
  %57 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %56, i8 noundef zeroext 50)
  %58 = tail call i16 @llvm.umax.i16(i16 %57, i16 2)
  %spec.store.select = zext i16 %58 to i32
  %59 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %59, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %64

60:                                               ; preds = %.split
  %61 = and i16 %54, 1
  %62 = icmp eq i16 %61, 0
  br i1 %62, label %.split, label %.loopexit, !llvm.loop !17

.loopexit:                                        ; preds = %50, %60, %.split44.us
  %63 = load i32, ptr %11, align 4, !tbaa !15
  tail call void @XSdPs_WriteReg16(i32 noundef %63, i8 noundef zeroext 48, i16 noundef zeroext 1)
  br label %64

64:                                               ; preds = %.split46.us, %.loopexit, %10, %28, %17, %9
  %.036 = phi i32 [ 0, %17 ], [ 0, %9 ], [ 0, %.loopexit ], [ %spec.store.select, %.split46.us ], [ 1, %10 ], [ 1, %28 ]
  ret i32 %.036
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @XSdPs_FrameCmd(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.umax.i16(i16, i16) #3

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !13, i64 112, !7, i64 128, !14, i64 512}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!10, !6, i64 4}
!16 = !{!12, !12, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass