; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2 (SelfTest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuWdt = type { %struct.XScuWdt_Config, i32, i32 }
%struct.XScuWdt_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XScuWdt_SelfTest(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  %10 = icmp ne ptr %9, null
  br i1 %10, label %11, label %12

11:                                               ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %13

12:                                               ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 91)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %8, align 4
  br label %84

13:                                               ; preds = %11
  %14 = load ptr, ptr %3, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.XScuWdt, ptr %14, i32 0, i32 1
  %16 = load i32, ptr %15, align 4, !tbaa !11
  %17 = icmp eq i32 %16, 286331153
  br i1 %17, label %18, label %19

18:                                               ; preds = %13
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %20

19:                                               ; preds = %13
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 92)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %8, align 4
  br label %84

20:                                               ; preds = %18
  %21 = load ptr, ptr %3, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.XScuWdt, ptr %21, i32 0, i32 0
  %23 = getelementptr inbounds %struct.XScuWdt_Config, ptr %22, i32 0, i32 1
  %24 = load i32, ptr %23, align 4, !tbaa !15
  %25 = add i32 %24, 8
  %26 = zext i32 %25 to i64
  %27 = call i32 @Xil_In32(i64 noundef %26)
  store i32 %27, ptr %6, align 4, !tbaa !9
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.XScuWdt, ptr %28, i32 0, i32 0
  %30 = getelementptr inbounds %struct.XScuWdt_Config, ptr %29, i32 0, i32 1
  %31 = load i32, ptr %30, align 4, !tbaa !15
  %32 = add i32 %31, 8
  %33 = zext i32 %32 to i64
  %34 = load i32, ptr %6, align 4, !tbaa !9
  %35 = and i32 %34, -2
  call void @Xil_Out32(i64 noundef %33, i32 noundef %35)
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.XScuWdt, ptr %36, i32 0, i32 0
  %38 = getelementptr inbounds %struct.XScuWdt_Config, ptr %37, i32 0, i32 1
  %39 = load i32, ptr %38, align 4, !tbaa !15
  %40 = add i32 %39, 0
  %41 = zext i32 %40 to i64
  %42 = call i32 @Xil_In32(i64 noundef %41)
  store i32 %42, ptr %7, align 4, !tbaa !9
  %43 = load ptr, ptr %3, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.XScuWdt, ptr %43, i32 0, i32 0
  %45 = getelementptr inbounds %struct.XScuWdt_Config, ptr %44, i32 0, i32 1
  %46 = load i32, ptr %45, align 4, !tbaa !15
  %47 = add i32 %46, 0
  %48 = zext i32 %47 to i64
  call void @Xil_Out32(i64 noundef %48, i32 noundef -1)
  %49 = load ptr, ptr %3, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.XScuWdt, ptr %49, i32 0, i32 0
  %51 = getelementptr inbounds %struct.XScuWdt_Config, ptr %50, i32 0, i32 1
  %52 = load i32, ptr %51, align 4, !tbaa !15
  %53 = add i32 %52, 8
  %54 = zext i32 %53 to i64
  %55 = load i32, ptr %6, align 4, !tbaa !9
  %56 = or i32 %55, 1
  call void @Xil_Out32(i64 noundef %54, i32 noundef %56)
  %57 = load ptr, ptr %3, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.XScuWdt, ptr %57, i32 0, i32 0
  %59 = getelementptr inbounds %struct.XScuWdt_Config, ptr %58, i32 0, i32 1
  %60 = load i32, ptr %59, align 4, !tbaa !15
  %61 = add i32 %60, 4
  %62 = zext i32 %61 to i64
  %63 = call i32 @Xil_In32(i64 noundef %62)
  store i32 %63, ptr %5, align 4, !tbaa !9
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.XScuWdt, ptr %64, i32 0, i32 0
  %66 = getelementptr inbounds %struct.XScuWdt_Config, ptr %65, i32 0, i32 1
  %67 = load i32, ptr %66, align 4, !tbaa !15
  %68 = add i32 %67, 0
  %69 = zext i32 %68 to i64
  %70 = load i32, ptr %7, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %69, i32 noundef %70)
  %71 = load ptr, ptr %3, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.XScuWdt, ptr %71, i32 0, i32 0
  %73 = getelementptr inbounds %struct.XScuWdt_Config, ptr %72, i32 0, i32 1
  %74 = load i32, ptr %73, align 4, !tbaa !15
  %75 = add i32 %74, 8
  %76 = zext i32 %75 to i64
  %77 = load i32, ptr %6, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %76, i32 noundef %77)
  %78 = load i32, ptr %5, align 4, !tbaa !9
  %79 = icmp eq i32 %78, -1
  br i1 %79, label %80, label %81

80:                                               ; preds = %20
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %82

81:                                               ; preds = %20
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %82

82:                                               ; preds = %81, %80
  %83 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %83, ptr %2, align 4
  store i32 1, ptr %8, align 4
  br label %84

84:                                               ; preds = %82, %19, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  %85 = load i32, ptr %2, align 4
  ret i32 %85
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XScuWdt_SelfTest(ptr noundef readonly %0) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %6, label %2

2:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 4, !tbaa !9
  %5 = icmp eq i32 %4, 286331153
  br i1 %5, label %7, label %36

6:                                                ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 91) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %37

7:                                                ; preds = %2
  %8 = getelementptr inbounds i8, ptr %0, i64 4
  %9 = load i32, ptr %8, align 4, !tbaa !13
  %10 = add i32 %9, 8
  %11 = zext i32 %10 to i64
  %12 = tail call i32 @Xil_In32(i64 noundef %11)
  %13 = load i32, ptr %8, align 4, !tbaa !13
  %14 = add i32 %13, 8
  %15 = zext i32 %14 to i64
  %16 = and i32 %12, -2
  tail call void @Xil_Out32(i64 noundef %15, i32 noundef %16)
  %17 = load i32, ptr %8, align 4, !tbaa !13
  %18 = zext i32 %17 to i64
  %19 = tail call i32 @Xil_In32(i64 noundef %18)
  %20 = load i32, ptr %8, align 4, !tbaa !13
  %21 = zext i32 %20 to i64
  tail call void @Xil_Out32(i64 noundef %21, i32 noundef -1)
  %22 = load i32, ptr %8, align 4, !tbaa !13
  %23 = add i32 %22, 8
  %24 = zext i32 %23 to i64
  %25 = or i32 %12, 1
  tail call void @Xil_Out32(i64 noundef %24, i32 noundef %25)
  %26 = load i32, ptr %8, align 4, !tbaa !13
  %27 = add i32 %26, 4
  %28 = zext i32 %27 to i64
  %29 = tail call i32 @Xil_In32(i64 noundef %28)
  %30 = load i32, ptr %8, align 4, !tbaa !13
  %31 = zext i32 %30 to i64
  tail call void @Xil_Out32(i64 noundef %31, i32 noundef %19)
  %32 = load i32, ptr %8, align 4, !tbaa !13
  %33 = add i32 %32, 8
  %34 = zext i32 %33 to i64
  tail call void @Xil_Out32(i64 noundef %34, i32 noundef %12)
  %35 = icmp eq i32 %29, -1
  %. = zext i1 %35 to i32
  br label %37

36:                                               ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 92) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %37

37:                                               ; preds = %7, %36, %6
  %.0 = phi i32 [ %., %7 ], [ 0, %36 ], [ 0, %6 ]
  ret i32 %.0
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass