; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (CfgInitialize)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XDmaPs_Config = type { i16, i32 }
%struct.XDmaPs = type { %struct.XDmaPs_Config, i32, i32, ptr, ptr, [8 x %struct.XDmaPs_ChannelData] }
%struct.XDmaPs_ChannelData = type { i32, i32, [2 x %struct.XDmaPs_ProgBuf], ptr, ptr, ptr, ptr, i32 }
%struct.XDmaPs_ProgBuf = type { [128 x i8], i32, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [161 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XDmaPs_CfgInitialize(ptr noundef %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #5
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %18

17:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 159)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %82

18:                                               ; preds = %16
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = icmp ne ptr %19, null
  br i1 %20, label %21, label %22

21:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %23

22:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 160)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %82

23:                                               ; preds = %21
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.XDmaPs_Config, ptr %24, i32 0, i32 0
  %26 = load i16, ptr %25, align 4, !tbaa !11
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.XDmaPs, ptr %27, i32 0, i32 0
  %29 = getelementptr inbounds %struct.XDmaPs_Config, ptr %28, i32 0, i32 0
  store i16 %26, ptr %29, align 8, !tbaa !14
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.XDmaPs, ptr %31, i32 0, i32 0
  %33 = getelementptr inbounds %struct.XDmaPs_Config, ptr %32, i32 0, i32 1
  store i32 %30, ptr %33, align 4, !tbaa !16
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = add i32 %34, 3588
  %36 = zext i32 %35 to i64
  %37 = call i32 @Xil_In32(i64 noundef %36)
  store i32 %37, ptr %10, align 4, !tbaa !9
  %38 = load i32, ptr %10, align 4, !tbaa !9
  %39 = and i32 %38, 7
  store i32 %39, ptr %9, align 4, !tbaa !9
  %40 = load i32, ptr %9, align 4, !tbaa !9
  %41 = icmp ult i32 %40, 2
  br i1 %41, label %45, label %42

42:                                               ; preds = %23
  %43 = load i32, ptr %9, align 4, !tbaa !9
  %44 = icmp ugt i32 %43, 5
  br i1 %44, label %45, label %46

45:                                               ; preds = %42, %23
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %49

46:                                               ; preds = %42
  %47 = load i32, ptr %9, align 4, !tbaa !9
  %48 = shl i32 1, %47
  store i32 %48, ptr %9, align 4, !tbaa !9
  br label %49

49:                                               ; preds = %46, %45
  %50 = load i32, ptr %9, align 4, !tbaa !9
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.XDmaPs, ptr %51, i32 0, i32 2
  store i32 %50, ptr %52, align 4, !tbaa !17
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.XDmaPs, ptr %53, i32 0, i32 5
  %55 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %54, i64 0, i64 0
  call void @llvm.memset.p0.i64(ptr align 8 %55, i8 0, i64 2560, i1 false)
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %56

56:                                               ; preds = %75, %49
  %57 = load i32, ptr %11, align 4, !tbaa !9
  %58 = icmp ult i32 %57, 8
  br i1 %58, label %59, label %78

59:                                               ; preds = %56
  %60 = load ptr, ptr %5, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.XDmaPs, ptr %60, i32 0, i32 5
  %62 = getelementptr inbounds [8 x %struct.XDmaPs_ChannelData], ptr %61, i64 0, i64 0
  %63 = load i32, ptr %11, align 4, !tbaa !9
  %64 = zext i32 %63 to i64
  %65 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %62, i64 %64
  store ptr %65, ptr %12, align 8, !tbaa !5
  %66 = load i32, ptr %11, align 4, !tbaa !9
  %67 = load ptr, ptr %12, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %67, i32 0, i32 1
  store i32 %66, ptr %68, align 4, !tbaa !18
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.XDmaPs_Config, ptr %69, i32 0, i32 0
  %71 = load i16, ptr %70, align 4, !tbaa !11
  %72 = zext i16 %71 to i32
  %73 = load ptr, ptr %12, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.XDmaPs_ChannelData, ptr %73, i32 0, i32 0
  store i32 %72, ptr %74, align 8, !tbaa !20
  br label %75

75:                                               ; preds = %59
  %76 = load i32, ptr %11, align 4, !tbaa !9
  %77 = add i32 %76, 1
  store i32 %77, ptr %11, align 4, !tbaa !9
  br label %56, !llvm.loop !21

78:                                               ; preds = %56
  %79 = load ptr, ptr %5, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.XDmaPs, ptr %79, i32 0, i32 1
  store i32 1, ptr %80, align 8, !tbaa !23
  %81 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %81, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %82

82:                                               ; preds = %78, %22, %17
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  %83 = load i32, ptr %4, align 4
  ret i32 %83
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #3

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 0}
!12 = !{!"", !13, i64 0, !10, i64 4}
!13 = !{!"short", !7, i64 0}
!14 = !{!15, !13, i64 0}
!15 = !{!"", !12, i64 0, !10, i64 8, !10, i64 12, !6, i64 16, !6, i64 24, !7, i64 32}
!16 = !{!15, !10, i64 4}
!17 = !{!15, !10, i64 12}
!18 = !{!19, !10, i64 4}
!19 = !{!"", !10, i64 0, !10, i64 4, !7, i64 8, !6, i64 280, !6, i64 288, !6, i64 296, !6, i64 304, !10, i64 312}
!20 = !{!19, !10, i64 0}
!21 = distinct !{!21, !22}
!22 = !{!"llvm.loop.mustprogress"}
!23 = !{!15, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [161 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @XDmaPs_CfgInitialize(ptr noundef writeonly %0, ptr noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %5, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %.not29 = icmp eq ptr %1, null
  br i1 %.not29, label %34, label %6

5:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 159) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %35

6:                                                ; preds = %4
  %7 = load i16, ptr %1, align 4, !tbaa !9
  store i16 %7, ptr %0, align 8, !tbaa !12
  %8 = getelementptr inbounds i8, ptr %0, i64 4
  store i32 %2, ptr %8, align 4, !tbaa !15
  %9 = add i32 %2, 3588
  %10 = zext i32 %9 to i64
  %11 = tail call i32 @Xil_In32(i64 noundef %10)
  %12 = and i32 %11, 7
  %13 = add nsw i32 %12, -6
  %or.cond = icmp ult i32 %13, -4
  %14 = shl nuw nsw i32 1, %12
  %.026 = select i1 %or.cond, i32 0, i32 %14
  %15 = getelementptr inbounds i8, ptr %0, i64 12
  store i32 %.026, ptr %15, align 4, !tbaa !16
  %16 = getelementptr inbounds i8, ptr %0, i64 32
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(2560) %16, i8 0, i64 2560, i1 false)
  %17 = load i16, ptr %1, align 4, !tbaa !9
  %18 = zext i16 %17 to i32
  store i32 %18, ptr %16, align 8, !tbaa !17
  %19 = getelementptr inbounds i8, ptr %0, i64 352
  %20 = getelementptr inbounds i8, ptr %0, i64 356
  store i32 1, ptr %20, align 4, !tbaa !19
  store i32 %18, ptr %19, align 8, !tbaa !17
  %21 = getelementptr inbounds i8, ptr %0, i64 672
  %22 = getelementptr inbounds i8, ptr %0, i64 676
  store i32 2, ptr %22, align 4, !tbaa !19
  store i32 %18, ptr %21, align 8, !tbaa !17
  %23 = getelementptr inbounds i8, ptr %0, i64 992
  %24 = getelementptr inbounds i8, ptr %0, i64 996
  store i32 3, ptr %24, align 4, !tbaa !19
  store i32 %18, ptr %23, align 8, !tbaa !17
  %25 = getelementptr inbounds i8, ptr %0, i64 1312
  %26 = getelementptr inbounds i8, ptr %0, i64 1316
  store i32 4, ptr %26, align 4, !tbaa !19
  store i32 %18, ptr %25, align 8, !tbaa !17
  %27 = getelementptr inbounds i8, ptr %0, i64 1632
  %28 = getelementptr inbounds i8, ptr %0, i64 1636
  store i32 5, ptr %28, align 4, !tbaa !19
  store i32 %18, ptr %27, align 8, !tbaa !17
  %29 = getelementptr inbounds i8, ptr %0, i64 1952
  %30 = getelementptr inbounds i8, ptr %0, i64 1956
  store i32 6, ptr %30, align 4, !tbaa !19
  store i32 %18, ptr %29, align 8, !tbaa !17
  %31 = getelementptr inbounds i8, ptr %0, i64 2272
  %32 = getelementptr inbounds i8, ptr %0, i64 2276
  store i32 7, ptr %32, align 4, !tbaa !19
  store i32 %18, ptr %31, align 8, !tbaa !17
  %33 = getelementptr inbounds i8, ptr %0, i64 8
  store i32 1, ptr %33, align 8, !tbaa !20
  br label %35

34:                                               ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 160) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %35

35:                                               ; preds = %6, %34, %5
  ret i32 0
}

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"", !11, i64 0, !6, i64 4}
!11 = !{!"short", !7, i64 0}
!12 = !{!13, !11, i64 0}
!13 = !{!"", !10, i64 0, !6, i64 8, !6, i64 12, !14, i64 16, !14, i64 24, !7, i64 32}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!13, !6, i64 4}
!16 = !{!13, !6, i64 12}
!17 = !{!18, !6, i64 0}
!18 = !{!"", !6, i64 0, !6, i64 4, !7, i64 8, !14, i64 280, !14, i64 288, !14, i64 296, !14, i64 304, !6, i64 312}
!19 = !{!18, !6, i64 4}
!20 = !{!13, !6, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass