; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/scugic_v3 (SoftwareIntr)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }
%struct.XScuGic_Config = type { i16, i32, i32, [95 x %struct.XScuGic_VectorTableEntry] }
%struct.XScuGic_VectorTableEntry = type { ptr, ptr }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XScuGic_SoftwareIntr(ptr noundef %0, i32 noundef %1, i32 noundef %2) #3 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 634)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

14:                                               ; preds = %12
  %15 = load ptr, ptr %5, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.XScuGic, ptr %15, i32 0, i32 1
  %17 = load i32, ptr %16, align 8, !tbaa !11
  %18 = icmp eq i32 %17, 286331153
  br i1 %18, label %19, label %20

19:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %21

20:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 635)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

21:                                               ; preds = %19
  %22 = load i32, ptr %6, align 4, !tbaa !9
  %23 = icmp ule i32 %22, 15
  br i1 %23, label %24, label %25

24:                                               ; preds = %21
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %26

25:                                               ; preds = %21
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 636)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

26:                                               ; preds = %24
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = icmp ule i32 %27, 255
  br i1 %28, label %29, label %30

29:                                               ; preds = %26
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %31

30:                                               ; preds = %26
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 637)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

31:                                               ; preds = %29
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = shl i32 %32, 16
  %34 = load i32, ptr %6, align 4, !tbaa !9
  %35 = or i32 %33, %34
  %36 = and i32 %35, 16711695
  store i32 %36, ptr %8, align 4, !tbaa !9
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.XScuGic, ptr %37, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !13
  %40 = getelementptr inbounds %struct.XScuGic_Config, ptr %39, i32 0, i32 2
  %41 = load i32, ptr %40, align 8, !tbaa !14
  %42 = add i32 %41, 3840
  %43 = zext i32 %42 to i64
  %44 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_Out32(i64 noundef %43, i32 noundef %44)
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %45

45:                                               ; preds = %31, %30, %25, %20, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  %46 = load i32, ptr %4, align 4
  ret i32 %46
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !6, i64 0, !10, i64 8, !10, i64 12}
!13 = !{!12, !6, i64 0}
!14 = !{!15, !10, i64 8}
!15 = !{!"", !16, i64 0, !10, i64 4, !10, i64 8, !7, i64 16}
!16 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [164 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @XScuGic_SoftwareIntr(ptr noundef readonly %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %8, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = load i32, ptr %5, align 8, !tbaa !9
  %7 = icmp eq i32 %6, 286331153
  br i1 %7, label %9, label %11

8:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 634) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %24

9:                                                ; preds = %4
  %10 = icmp ult i32 %1, 16
  br i1 %10, label %12, label %14

11:                                               ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 635) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %24

12:                                               ; preds = %9
  %13 = icmp ult i32 %2, 256
  br i1 %13, label %15, label %23

14:                                               ; preds = %9
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 636) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %24

15:                                               ; preds = %12
  %16 = shl nuw nsw i32 %2, 16
  %17 = or disjoint i32 %16, %1
  %18 = load ptr, ptr %0, align 8, !tbaa !12
  %19 = getelementptr inbounds i8, ptr %18, i64 8
  %20 = load i32, ptr %19, align 8, !tbaa !13
  %21 = add i32 %20, 3840
  %22 = zext i32 %21 to i64
  tail call void @Xil_Out32(i64 noundef %22, i32 noundef %17)
  br label %24

23:                                               ; preds = %12
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 637) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %15, %23, %14, %11, %8
  ret i32 0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !6, i64 12}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{!14, !6, i64 8}
!14 = !{!"", !15, i64 0, !6, i64 4, !6, i64 8, !7, i64 16}
!15 = !{!"short", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass