; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (GetIntrTypePin)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [168 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @XGpioPs_GetIntrTypePin(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca i8, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #4
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = icmp ne ptr %13, null
  br i1 %14, label %15, label %16

15:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 592)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i8 0, ptr %3, align 1
  store i32 1, ptr %12, align 4
  br label %128

17:                                               ; preds = %15
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XGpioPs, ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 8, !tbaa !11
  %21 = icmp eq i32 %20, 286331153
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %24

23:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 593)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i8 0, ptr %3, align 1
  store i32 1, ptr %12, align 4
  br label %128

24:                                               ; preds = %22
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.XGpioPs, ptr %26, i32 0, i32 5
  %28 = load i32, ptr %27, align 4, !tbaa !15
  %29 = icmp ult i32 %25, %28
  br i1 %29, label %30, label %31

30:                                               ; preds = %24
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %32

31:                                               ; preds = %24
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 594)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i8 0, ptr %3, align 1
  store i32 1, ptr %12, align 4
  br label %128

32:                                               ; preds = %30
  %33 = load i32, ptr %5, align 4, !tbaa !9
  %34 = trunc i32 %33 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %34, ptr noundef %9, ptr noundef %10)
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.XGpioPs, ptr %35, i32 0, i32 0
  %37 = getelementptr inbounds %struct.XGpioPs_Config, ptr %36, i32 0, i32 1
  %38 = load i32, ptr %37, align 4, !tbaa !16
  %39 = load i8, ptr %9, align 1, !tbaa !17
  %40 = zext i8 %39 to i32
  %41 = mul i32 %40, 64
  %42 = add i32 %41, 540
  %43 = add i32 %38, %42
  %44 = zext i32 %43 to i64
  %45 = call i32 @Xil_In32(i64 noundef %44)
  %46 = load i8, ptr %10, align 1, !tbaa !17
  %47 = zext i8 %46 to i32
  %48 = shl i32 1, %47
  %49 = and i32 %45, %48
  store i32 %49, ptr %6, align 4, !tbaa !9
  %50 = load i32, ptr %6, align 4, !tbaa !9
  %51 = load i8, ptr %10, align 1, !tbaa !17
  %52 = zext i8 %51 to i32
  %53 = shl i32 1, %52
  %54 = icmp eq i32 %50, %53
  br i1 %54, label %55, label %102

55:                                               ; preds = %32
  %56 = load ptr, ptr %4, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.XGpioPs, ptr %56, i32 0, i32 0
  %58 = getelementptr inbounds %struct.XGpioPs_Config, ptr %57, i32 0, i32 1
  %59 = load i32, ptr %58, align 4, !tbaa !16
  %60 = load i8, ptr %9, align 1, !tbaa !17
  %61 = zext i8 %60 to i32
  %62 = mul i32 %61, 64
  %63 = add i32 %62, 548
  %64 = add i32 %59, %63
  %65 = zext i32 %64 to i64
  %66 = call i32 @Xil_In32(i64 noundef %65)
  %67 = load i8, ptr %10, align 1, !tbaa !17
  %68 = zext i8 %67 to i32
  %69 = shl i32 1, %68
  %70 = and i32 %66, %69
  store i32 %70, ptr %8, align 4, !tbaa !9
  %71 = load ptr, ptr %4, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.XGpioPs, ptr %71, i32 0, i32 0
  %73 = getelementptr inbounds %struct.XGpioPs_Config, ptr %72, i32 0, i32 1
  %74 = load i32, ptr %73, align 4, !tbaa !16
  %75 = load i8, ptr %9, align 1, !tbaa !17
  %76 = zext i8 %75 to i32
  %77 = mul i32 %76, 64
  %78 = add i32 %77, 544
  %79 = add i32 %74, %78
  %80 = zext i32 %79 to i64
  %81 = call i32 @Xil_In32(i64 noundef %80)
  %82 = load i8, ptr %10, align 1, !tbaa !17
  %83 = zext i8 %82 to i32
  %84 = shl i32 1, %83
  %85 = and i32 %81, %84
  store i32 %85, ptr %7, align 4, !tbaa !9
  %86 = load i32, ptr %8, align 4, !tbaa !9
  %87 = load i8, ptr %10, align 1, !tbaa !17
  %88 = zext i8 %87 to i32
  %89 = shl i32 1, %88
  %90 = icmp eq i32 %86, %89
  br i1 %90, label %91, label %92

91:                                               ; preds = %55
  store i8 2, ptr %11, align 1, !tbaa !17
  br label %101

92:                                               ; preds = %55
  %93 = load i32, ptr %7, align 4, !tbaa !9
  %94 = load i8, ptr %10, align 1, !tbaa !17
  %95 = zext i8 %94 to i32
  %96 = shl i32 1, %95
  %97 = icmp eq i32 %93, %96
  br i1 %97, label %98, label %99

98:                                               ; preds = %92
  store i8 0, ptr %11, align 1, !tbaa !17
  br label %100

99:                                               ; preds = %92
  store i8 1, ptr %11, align 1, !tbaa !17
  br label %100

100:                                              ; preds = %99, %98
  br label %101

101:                                              ; preds = %100, %91
  br label %126

102:                                              ; preds = %32
  %103 = load ptr, ptr %4, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.XGpioPs, ptr %103, i32 0, i32 0
  %105 = getelementptr inbounds %struct.XGpioPs_Config, ptr %104, i32 0, i32 1
  %106 = load i32, ptr %105, align 4, !tbaa !16
  %107 = load i8, ptr %9, align 1, !tbaa !17
  %108 = zext i8 %107 to i32
  %109 = mul i32 %108, 64
  %110 = add i32 %109, 544
  %111 = add i32 %106, %110
  %112 = zext i32 %111 to i64
  %113 = call i32 @Xil_In32(i64 noundef %112)
  %114 = load i8, ptr %10, align 1, !tbaa !17
  %115 = zext i8 %114 to i32
  %116 = shl i32 1, %115
  %117 = and i32 %113, %116
  store i32 %117, ptr %7, align 4, !tbaa !9
  %118 = load i32, ptr %7, align 4, !tbaa !9
  %119 = load i8, ptr %10, align 1, !tbaa !17
  %120 = zext i8 %119 to i32
  %121 = shl i32 1, %120
  %122 = icmp eq i32 %118, %121
  br i1 %122, label %123, label %124

123:                                              ; preds = %102
  store i8 3, ptr %11, align 1, !tbaa !17
  br label %125

124:                                              ; preds = %102
  store i8 4, ptr %11, align 1, !tbaa !17
  br label %125

125:                                              ; preds = %124, %123
  br label %126

126:                                              ; preds = %125, %101
  %127 = load i8, ptr %11, align 1, !tbaa !17
  store i8 %127, ptr %3, align 1
  store i32 1, ptr %12, align 4
  br label %128

128:                                              ; preds = %126, %31, %23, %16
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %129 = load i8, ptr %3, align 1
  ret i8 %129
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 8}
!12 = !{!"", !13, i64 0, !10, i64 8, !6, i64 16, !6, i64 24, !10, i64 32, !10, i64 36, !7, i64 40}
!13 = !{!"", !14, i64 0, !10, i64 4}
!14 = !{!"short", !7, i64 0}
!15 = !{!12, !10, i64 36}
!16 = !{!12, !10, i64 4}
!17 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [168 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @XGpioPs_GetBankPin(i8 noundef zeroext, ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @Xil_In32(i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 5) i8 @XGpioPs_GetIntrTypePin(ptr noundef readonly %0, i32 noundef %1) local_unnamed_addr #3 {
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #4
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %9, label %5

5:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load i32, ptr %6, align 8, !tbaa !9
  %8 = icmp eq i32 %7, 286331153
  br i1 %8, label %10, label %14

9:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 592) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %67

10:                                               ; preds = %5
  %11 = getelementptr inbounds i8, ptr %0, i64 36
  %12 = load i32, ptr %11, align 4, !tbaa !14
  %13 = icmp ugt i32 %12, %1
  br i1 %13, label %15, label %34

14:                                               ; preds = %5
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 593) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %67

15:                                               ; preds = %10
  %16 = trunc i32 %1 to i8
  call void @XGpioPs_GetBankPin(i8 noundef zeroext %16, ptr noundef nonnull %3, ptr noundef nonnull %4) #4
  %17 = getelementptr inbounds i8, ptr %0, i64 4
  %18 = load i32, ptr %17, align 4, !tbaa !15
  %19 = load i8, ptr %3, align 1, !tbaa !16
  %20 = zext i8 %19 to i32
  %21 = shl nuw nsw i32 %20, 6
  %22 = add i32 %18, 540
  %23 = add i32 %22, %21
  %24 = zext i32 %23 to i64
  %25 = call i32 @Xil_In32(i64 noundef %24)
  %26 = load i8, ptr %4, align 1, !tbaa !16
  %27 = zext nneg i8 %26 to i32
  %28 = shl nuw i32 1, %27
  %29 = and i32 %28, %25
  %.not18 = icmp eq i32 %29, 0
  %30 = load i32, ptr %17, align 4, !tbaa !15
  %31 = load i8, ptr %3, align 1, !tbaa !16
  %32 = zext i8 %31 to i32
  %33 = shl nuw nsw i32 %32, 6
  br i1 %.not18, label %58, label %35

34:                                               ; preds = %10
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 594) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %67

35:                                               ; preds = %15
  %36 = add i32 %30, 548
  %37 = add i32 %36, %33
  %38 = zext i32 %37 to i64
  %39 = call i32 @Xil_In32(i64 noundef %38)
  %40 = load i8, ptr %4, align 1, !tbaa !16
  %41 = zext nneg i8 %40 to i32
  %42 = shl nuw i32 1, %41
  %43 = and i32 %42, %39
  %44 = load i32, ptr %17, align 4, !tbaa !15
  %45 = load i8, ptr %3, align 1, !tbaa !16
  %46 = zext i8 %45 to i32
  %47 = shl nuw nsw i32 %46, 6
  %48 = add i32 %44, 544
  %49 = add i32 %48, %47
  %50 = zext i32 %49 to i64
  %51 = call i32 @Xil_In32(i64 noundef %50)
  %52 = load i8, ptr %4, align 1, !tbaa !16
  %53 = zext nneg i8 %52 to i32
  %54 = shl nuw i32 1, %53
  %55 = icmp eq i32 %43, %54
  br i1 %55, label %67, label %56

56:                                               ; preds = %35
  %57 = and i32 %54, %51
  %.not20 = icmp eq i32 %57, 0
  %. = zext i1 %.not20 to i8
  br label %67

58:                                               ; preds = %15
  %59 = add i32 %30, 544
  %60 = add i32 %59, %33
  %61 = zext i32 %60 to i64
  %62 = call i32 @Xil_In32(i64 noundef %61)
  %63 = load i8, ptr %4, align 1, !tbaa !16
  %64 = zext nneg i8 %63 to i32
  %65 = shl nuw i32 1, %64
  %66 = and i32 %65, %62
  %.not19 = icmp eq i32 %66, 0
  %.21 = select i1 %.not19, i8 4, i8 3
  br label %67

67:                                               ; preds = %35, %56, %58, %34, %14, %9
  %.014 = phi i8 [ 0, %34 ], [ 0, %14 ], [ 0, %9 ], [ 2, %35 ], [ %., %56 ], [ %.21, %58 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #4
  ret i8 %.014
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !6, i64 36}
!15 = !{!10, !6, i64 4}
!16 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass