; LLVM IR from jorgemf/c-evolutionary-library :: src/NeuralNet.ll (ZN9NeuralNet9getOutputEPdS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.NeuralNet = type { ptr, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.0", ptr, %"class.std::vector.5", ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<InputNeuron *, std::allocator<InputNeuron *>>::_Vector_impl" }
%"struct.std::_Vector_base<InputNeuron *, std::allocator<InputNeuron *>>::_Vector_impl" = type { %"struct.std::_Vector_base<InputNeuron *, std::allocator<InputNeuron *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<InputNeuron *, std::allocator<InputNeuron *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<Neuron *, std::allocator<Neuron *>>::_Vector_impl" }
%"struct.std::_Vector_base<Neuron *, std::allocator<Neuron *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Neuron *, std::allocator<Neuron *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Neuron *, std::allocator<Neuron *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl" = type { %"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Connection *, std::allocator<Connection *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11InputNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9NeuralNet9getOutputEPdS0_(ptr noundef nonnull align 8 dereferenceable(128) %0, ptr noundef %1, ptr noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %15 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %16 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 2
  %17 = call noundef i64 @_ZNKSt6vectorIP11InputNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %16) #4
  %18 = trunc i64 %17 to i32
  store i32 %18, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %19 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 4
  %20 = call noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %19) #4
  %21 = trunc i64 %20 to i32
  store i32 %21, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %22 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 3
  %23 = call noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %22) #4
  %24 = trunc i64 %23 to i32
  store i32 %24, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  store i32 1, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %25 = load i32, ptr %10, align 4, !tbaa !9
  %26 = load i32, ptr %7, align 4, !tbaa !9
  %27 = add nsw i32 %25, %26
  %28 = load i32, ptr %8, align 4, !tbaa !9
  %29 = add nsw i32 %27, %28
  %30 = load i32, ptr %9, align 4, !tbaa !9
  %31 = add nsw i32 %29, %30
  store i32 %31, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %32

32:                                               ; preds = %51, %3
  %33 = load i32, ptr %12, align 4, !tbaa !9
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = icmp slt i32 %33, %34
  br i1 %35, label %36, label %54

36:                                               ; preds = %32
  %37 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 7
  %38 = load ptr, ptr %37, align 8, !tbaa !11
  %39 = load i32, ptr %12, align 4, !tbaa !9
  %40 = load i32, ptr %10, align 4, !tbaa !9
  %41 = add nsw i32 %39, %40
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds ptr, ptr %38, i64 %42
  %44 = load ptr, ptr %43, align 8, !tbaa !5
  store ptr %44, ptr %13, align 8, !tbaa !5
  %45 = load ptr, ptr %13, align 8, !tbaa !5
  %46 = load ptr, ptr %5, align 8, !tbaa !5
  %47 = load i32, ptr %12, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = getelementptr inbounds double, ptr %46, i64 %48
  %50 = load double, ptr %49, align 8, !tbaa !25
  call void @_ZN11InputNeuron8setInputEd(ptr noundef nonnull align 8 dereferenceable(80) %45, double noundef %50)
  br label %51

51:                                               ; preds = %36
  %52 = load i32, ptr %12, align 4, !tbaa !9
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %12, align 4, !tbaa !9
  br label %32, !llvm.loop !27

54:                                               ; preds = %32
  %55 = load i32, ptr %10, align 4, !tbaa !9
  %56 = load i32, ptr %7, align 4, !tbaa !9
  %57 = add nsw i32 %55, %56
  store i32 %57, ptr %12, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %72, %54
  %59 = load i32, ptr %12, align 4, !tbaa !9
  %60 = load i32, ptr %11, align 4, !tbaa !9
  %61 = icmp slt i32 %59, %60
  br i1 %61, label %62, label %75

62:                                               ; preds = %58
  %63 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 7
  %64 = load ptr, ptr %63, align 8, !tbaa !11
  %65 = load i32, ptr %12, align 4, !tbaa !9
  %66 = sext i32 %65 to i64
  %67 = getelementptr inbounds ptr, ptr %64, i64 %66
  %68 = load ptr, ptr %67, align 8, !tbaa !5
  %69 = load ptr, ptr %68, align 8, !tbaa !29
  %70 = getelementptr inbounds ptr, ptr %69, i64 6
  %71 = load ptr, ptr %70, align 8
  call void %71(ptr noundef nonnull align 8 dereferenceable(80) %68)
  br label %72

72:                                               ; preds = %62
  %73 = load i32, ptr %12, align 4, !tbaa !9
  %74 = add nsw i32 %73, 1
  store i32 %74, ptr %12, align 4, !tbaa !9
  br label %58, !llvm.loop !31

75:                                               ; preds = %58
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %76

76:                                               ; preds = %102, %75
  %77 = load i32, ptr %12, align 4, !tbaa !9
  %78 = load i32, ptr %8, align 4, !tbaa !9
  %79 = icmp slt i32 %77, %78
  br i1 %79, label %80, label %105

80:                                               ; preds = %76
  %81 = getelementptr inbounds %class.NeuralNet, ptr %15, i32 0, i32 7
  %82 = load ptr, ptr %81, align 8, !tbaa !11
  %83 = load i32, ptr %12, align 4, !tbaa !9
  %84 = load i32, ptr %10, align 4, !tbaa !9
  %85 = add nsw i32 %83, %84
  %86 = load i32, ptr %7, align 4, !tbaa !9
  %87 = add nsw i32 %85, %86
  %88 = load i32, ptr %9, align 4, !tbaa !9
  %89 = add nsw i32 %87, %88
  %90 = sext i32 %89 to i64
  %91 = getelementptr inbounds ptr, ptr %82, i64 %90
  %92 = load ptr, ptr %91, align 8, !tbaa !5
  store ptr %92, ptr %14, align 8, !tbaa !5
  %93 = load ptr, ptr %14, align 8, !tbaa !5
  %94 = load ptr, ptr %93, align 8, !tbaa !29
  %95 = getelementptr inbounds ptr, ptr %94, i64 4
  %96 = load ptr, ptr %95, align 8
  %97 = call noundef double %96(ptr noundef nonnull align 8 dereferenceable(80) %93)
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  %99 = load i32, ptr %12, align 4, !tbaa !9
  %100 = sext i32 %99 to i64
  %101 = getelementptr inbounds double, ptr %98, i64 %100
  store double %97, ptr %101, align 8, !tbaa !25
  br label %102

102:                                              ; preds = %80
  %103 = load i32, ptr %12, align 4, !tbaa !9
  %104 = add nsw i32 %103, 1
  store i32 %104, ptr %12, align 4, !tbaa !9
  br label %76, !llvm.loop !32

105:                                              ; preds = %76
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  ret void
}

declare void @_ZN11InputNeuron8setInputEd(ptr noundef nonnull align 8 dereferenceable(80), double noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 120}
!12 = !{!"_ZTS9NeuralNet", !10, i64 8, !13, i64 16, !17, i64 40, !17, i64 64, !6, i64 88, !21, i64 96, !6, i64 120}
!13 = !{!"_ZTSSt6vectorIP11InputNeuronSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIP11InputNeuronSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP11InputNeuronSaIS1_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP11InputNeuronSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIP6NeuronSaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIP6NeuronSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIP6NeuronSaIS1_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP6NeuronSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!26, !26, i64 0}
!26 = !{!"double", !7, i64 0}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = !{!30, !30, i64 0}
!30 = !{!"vtable pointer", !8, i64 0}
!31 = distinct !{!31, !28}
!32 = distinct !{!32, !28}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP11InputNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9NeuralNet9getOutputEPdS0_(ptr noundef nonnull align 8 dereferenceable(128) %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 16
  %5 = tail call noundef i64 @_ZNKSt6vectorIP11InputNeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %6 = trunc i64 %5 to i32
  %7 = getelementptr inbounds i8, ptr %0, i64 64
  %8 = tail call noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  %9 = trunc i64 %8 to i32
  %10 = getelementptr inbounds i8, ptr %0, i64 40
  %11 = tail call noundef i64 @_ZNKSt6vectorIP6NeuronSaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #3
  %12 = trunc i64 %11 to i32
  %13 = add i32 %6, 1
  %14 = add nsw i32 %13, %9
  %15 = add nsw i32 %14, %12
  %16 = icmp sgt i32 %6, 0
  br i1 %16, label %.lr.ph, label %.preheader29

.lr.ph:                                           ; preds = %3
  %17 = getelementptr inbounds i8, ptr %0, i64 120
  %wide.trip.count = and i64 %5, 2147483647
  br label %24

.preheader29:                                     ; preds = %24, %3
  %18 = icmp slt i32 %13, %15
  br i1 %18, label %.lr.ph32, label %.preheader

.lr.ph32:                                         ; preds = %.preheader29
  %19 = getelementptr inbounds i8, ptr %0, i64 120
  %20 = sext i32 %13 to i64
  %21 = add i32 %9, %12
  %22 = add i32 %21, %6
  %23 = add i32 %22, 1
  br label %33

24:                                               ; preds = %.lr.ph, %24
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %24 ]
  %25 = load ptr, ptr %17, align 8, !tbaa !5
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %26 = getelementptr inbounds ptr, ptr %25, i64 %indvars.iv.next
  %27 = load ptr, ptr %26, align 8, !tbaa !23
  %28 = getelementptr inbounds double, ptr %1, i64 %indvars.iv
  %29 = load double, ptr %28, align 8, !tbaa !24
  tail call void @_ZN11InputNeuron8setInputEd(ptr noundef nonnull align 8 dereferenceable(80) %27, double noundef %29)
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.preheader29, label %24, !llvm.loop !26

.preheader:                                       ; preds = %33, %.preheader29
  %30 = icmp sgt i32 %9, 0
  br i1 %30, label %.lr.ph34, label %._crit_edge

.lr.ph34:                                         ; preds = %.preheader
  %31 = getelementptr inbounds i8, ptr %0, i64 120
  %32 = add i64 %11, %5
  %wide.trip.count43 = and i64 %8, 2147483647
  br label %40

33:                                               ; preds = %.lr.ph32, %33
  %indvars.iv36 = phi i64 [ %20, %.lr.ph32 ], [ %indvars.iv.next37, %33 ]
  %34 = load ptr, ptr %19, align 8, !tbaa !5
  %35 = getelementptr inbounds ptr, ptr %34, i64 %indvars.iv36
  %36 = load ptr, ptr %35, align 8, !tbaa !23
  %37 = load ptr, ptr %36, align 8, !tbaa !28
  %38 = getelementptr inbounds i8, ptr %37, i64 48
  %39 = load ptr, ptr %38, align 8
  tail call void %39(ptr noundef nonnull align 8 dereferenceable(80) %36)
  %indvars.iv.next37 = add nsw i64 %indvars.iv36, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next37 to i32
  %exitcond39.not = icmp eq i32 %23, %lftr.wideiv
  br i1 %exitcond39.not, label %.preheader, label %33, !llvm.loop !30

40:                                               ; preds = %.lr.ph34, %40
  %indvars.iv40 = phi i64 [ 0, %.lr.ph34 ], [ %indvars.iv.next41, %40 ]
  %41 = load ptr, ptr %31, align 8, !tbaa !5
  %indvars.iv.next41 = add nuw nsw i64 %indvars.iv40, 1
  %42 = add i64 %32, %indvars.iv.next41
  %sext = shl i64 %42, 32
  %43 = ashr exact i64 %sext, 29
  %44 = getelementptr inbounds i8, ptr %41, i64 %43
  %45 = load ptr, ptr %44, align 8, !tbaa !23
  %46 = load ptr, ptr %45, align 8, !tbaa !28
  %47 = getelementptr inbounds i8, ptr %46, i64 32
  %48 = load ptr, ptr %47, align 8
  %49 = tail call noundef double %48(ptr noundef nonnull align 8 dereferenceable(80) %45)
  %50 = getelementptr inbounds double, ptr %2, i64 %indvars.iv40
  store double %49, ptr %50, align 8, !tbaa !24
  %exitcond44.not = icmp eq i64 %indvars.iv.next41, %wide.trip.count43
  br i1 %exitcond44.not, label %._crit_edge, label %40, !llvm.loop !31

._crit_edge:                                      ; preds = %40, %.preheader
  ret void
}

declare void @_ZN11InputNeuron8setInputEd(ptr noundef nonnull align 8 dereferenceable(80), double noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 120}
!6 = !{!"_ZTS9NeuralNet", !7, i64 8, !10, i64 16, !15, i64 40, !15, i64 64, !14, i64 88, !19, i64 96, !14, i64 120}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIP11InputNeuronSaIS1_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIP11InputNeuronSaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIP11InputNeuronSaIS1_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIP11InputNeuronSaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"_ZTSSt6vectorIP6NeuronSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIP6NeuronSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP6NeuronSaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP6NeuronSaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"_ZTSSt6vectorIP10ConnectionSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIP10ConnectionSaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIP10ConnectionSaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!23 = !{!14, !14, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"double", !8, i64 0}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!29, !29, i64 0}
!29 = !{!"vtable pointer", !9, i64 0}
!30 = distinct !{!30, !27}
!31 = distinct !{!31, !27}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass