; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/qspips_v3 (SelfTest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XQspiPs = type { %struct.XQspiPs_Config, i32, ptr, ptr, i32, i32, i32, ptr, ptr, i32 }
%struct.XQspiPs_Config = type { i16, i32, i32, i8 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XQspiPs_SelfTest(ptr noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %13

12:                                               ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %14

13:                                               ; preds = %1
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 93)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

14:                                               ; preds = %12
  %15 = load ptr, ptr %3, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.XQspiPs, ptr %15, i32 0, i32 1
  %17 = load i32, ptr %16, align 8, !tbaa !11
  %18 = icmp eq i32 %17, 286331153
  br i1 %18, label %19, label %20

19:                                               ; preds = %14
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %21

20:                                               ; preds = %14
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 94)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

21:                                               ; preds = %19
  %22 = load ptr, ptr %3, align 8, !tbaa !5
  call void @XQspiPs_Reset(ptr noundef %22)
  store i8 90, ptr %5, align 1, !tbaa !15
  store i8 -91, ptr %6, align 1, !tbaa !15
  store i8 -86, ptr %7, align 1, !tbaa !15
  store i8 85, ptr %8, align 1, !tbaa !15
  %23 = load ptr, ptr %3, align 8, !tbaa !5
  %24 = load i8, ptr %5, align 1, !tbaa !15
  %25 = load i8, ptr %6, align 1, !tbaa !15
  %26 = load i8, ptr %7, align 1, !tbaa !15
  %27 = load i8, ptr %8, align 1, !tbaa !15
  %28 = call i32 @XQspiPs_SetDelays(ptr noundef %23, i8 noundef zeroext %24, i8 noundef zeroext %25, i8 noundef zeroext %26, i8 noundef zeroext %27)
  store i32 %28, ptr %4, align 4, !tbaa !9
  %29 = load i32, ptr %4, align 4, !tbaa !9
  %30 = sext i32 %29 to i64
  %31 = icmp ne i64 %30, 0
  br i1 %31, label %32, label %34

32:                                               ; preds = %21
  %33 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %33, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

34:                                               ; preds = %21
  %35 = load ptr, ptr %3, align 8, !tbaa !5
  call void @XQspiPs_GetDelays(ptr noundef %35, ptr noundef %5, ptr noundef %6, ptr noundef %7, ptr noundef %8)
  %36 = load i8, ptr %5, align 1, !tbaa !15
  %37 = zext i8 %36 to i32
  %38 = icmp ne i32 90, %37
  br i1 %38, label %51, label %39

39:                                               ; preds = %34
  %40 = load i8, ptr %6, align 1, !tbaa !15
  %41 = zext i8 %40 to i32
  %42 = icmp ne i32 165, %41
  br i1 %42, label %51, label %43

43:                                               ; preds = %39
  %44 = load i8, ptr %7, align 1, !tbaa !15
  %45 = zext i8 %44 to i32
  %46 = icmp ne i32 170, %45
  br i1 %46, label %51, label %47

47:                                               ; preds = %43
  %48 = load i8, ptr %8, align 1, !tbaa !15
  %49 = zext i8 %48 to i32
  %50 = icmp ne i32 85, %49
  br i1 %50, label %51, label %52

51:                                               ; preds = %47, %43, %39, %34
  store i32 14, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

52:                                               ; preds = %47
  %53 = load ptr, ptr %3, align 8, !tbaa !5
  %54 = call i32 @XQspiPs_SetDelays(ptr noundef %53, i8 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext 0)
  store i32 %54, ptr %4, align 4, !tbaa !9
  %55 = load i32, ptr %4, align 4, !tbaa !9
  %56 = sext i32 %55 to i64
  %57 = icmp ne i64 %56, 0
  br i1 %57, label %58, label %60

58:                                               ; preds = %52
  %59 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %59, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

60:                                               ; preds = %52
  %61 = load ptr, ptr %3, align 8, !tbaa !5
  call void @XQspiPs_Reset(ptr noundef %61)
  store i32 0, ptr %2, align 4
  store i32 1, ptr %9, align 4
  br label %62

62:                                               ; preds = %60, %58, %51, %32, %20, %13
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %63 = load i32, ptr %2, align 4
  ret i32 %63
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) #2

declare void @XQspiPs_Reset(ptr noundef) #2

declare i32 @XQspiPs_SetDelays(ptr noundef, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) #2

declare void @XQspiPs_GetDelays(ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 16}
!12 = !{!"", !13, i64 0, !10, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 44, !10, i64 48, !6, i64 56, !6, i64 64, !10, i64 72}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !7, i64 12}
!14 = !{!"short", !7, i64 0}
!15 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [172 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local i32 @XQspiPs_SelfTest(ptr noundef %0) local_unnamed_addr #0 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #3
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %10, label %6

6:                                                ; preds = %1
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 16
  %8 = load i32, ptr %7, align 8, !tbaa !9
  %9 = icmp eq i32 %8, 286331153
  br i1 %9, label %11, label %13

10:                                               ; preds = %1
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 93) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %26

11:                                               ; preds = %6
  tail call void @XQspiPs_Reset(ptr noundef nonnull %0) #3
  store i8 90, ptr %2, align 1, !tbaa !14
  store i8 -91, ptr %3, align 1, !tbaa !14
  store i8 -86, ptr %4, align 1, !tbaa !14
  store i8 85, ptr %5, align 1, !tbaa !14
  %12 = tail call i32 @XQspiPs_SetDelays(ptr noundef nonnull %0, i8 noundef zeroext 90, i8 noundef zeroext -91, i8 noundef zeroext -86, i8 noundef zeroext 85) #3
  %.not20 = icmp eq i32 %12, 0
  br i1 %.not20, label %14, label %26

13:                                               ; preds = %6
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 94) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %26

14:                                               ; preds = %11
  call void @XQspiPs_GetDelays(ptr noundef nonnull %0, ptr noundef nonnull %2, ptr noundef nonnull %3, ptr noundef nonnull %4, ptr noundef nonnull %5) #3
  %15 = load i8, ptr %2, align 1, !tbaa !14
  %16 = icmp ne i8 %15, 90
  %17 = load i8, ptr %3, align 1
  %18 = icmp ne i8 %17, -91
  %or.cond = select i1 %16, i1 true, i1 %18
  %19 = load i8, ptr %4, align 1
  %20 = icmp ne i8 %19, -86
  %or.cond5 = select i1 %or.cond, i1 true, i1 %20
  %21 = load i8, ptr %5, align 1
  %22 = icmp ne i8 %21, 85
  %or.cond8 = select i1 %or.cond5, i1 true, i1 %22
  br i1 %or.cond8, label %26, label %23

23:                                               ; preds = %14
  %24 = call i32 @XQspiPs_SetDelays(ptr noundef nonnull %0, i8 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext 0, i8 noundef zeroext 0) #3
  %.not21 = icmp eq i32 %24, 0
  br i1 %.not21, label %25, label %26

25:                                               ; preds = %23
  call void @XQspiPs_Reset(ptr noundef nonnull %0) #3
  br label %26

26:                                               ; preds = %23, %14, %11, %25, %13, %10
  %.0 = phi i32 [ 0, %25 ], [ 0, %13 ], [ 0, %10 ], [ %12, %11 ], [ 14, %14 ], [ %24, %23 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  ret i32 %.0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #2

declare void @XQspiPs_Reset(ptr noundef) local_unnamed_addr #2

declare i32 @XQspiPs_SetDelays(ptr noundef, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #2

declare void @XQspiPs_GetDelays(ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 16}
!10 = !{!"", !11, i64 0, !6, i64 16, !13, i64 24, !13, i64 32, !6, i64 40, !6, i64 44, !6, i64 48, !13, i64 56, !13, i64 64, !6, i64 72}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !7, i64 12}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!7, !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass