; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/sdps_v3_6 (ExtCsd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XSdPs = type { %struct.XSdPs_Config, i32, i32, i32, i32, i8, i8, i8, i8, i32, i8, [4 x i32], i32, [4 x i32], i32, i32, i32, ptr, [8 x i8], [32 x %struct.XSdPs_Adma2Descriptor], i64, [24 x i8] }
%struct.XSdPs_Config = type { i16, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.XSdPs_Adma2Descriptor = type <{ i16, i16, i64 }>

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1
@TransferMode = external global i16, align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @Xil_Assert(ptr noundef, i32 noundef) #1

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) #1

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @XSdPs_Get_Mmc_ExtCsd(ptr noundef %0, ptr noundef %1) #3 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i16, align 2
  %10 = alloca i16, align 2
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = icmp ne ptr %13, null
  br i1 %14, label %15, label %16

15:                                               ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %2
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 841)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %95

17:                                               ; preds = %15
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.XSdPs, ptr %18, i32 0, i32 1
  %20 = load i32, ptr %19, align 4, !tbaa !11
  %21 = icmp eq i32 %20, 286331153
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !9
  br label %24

23:                                               ; preds = %17
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 842)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !9
  store i32 0, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %95

24:                                               ; preds = %22
  store i32 0, ptr %11, align 4, !tbaa !9
  br label %25

25:                                               ; preds = %33, %24
  %26 = load i32, ptr %11, align 4, !tbaa !9
  %27 = icmp slt i32 %26, 512
  br i1 %27, label %28, label %36

28:                                               ; preds = %25
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = load i32, ptr %11, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds i8, ptr %29, i64 %31
  store i8 0, ptr %32, align 1, !tbaa !16
  br label %33

33:                                               ; preds = %28
  %34 = load i32, ptr %11, align 4, !tbaa !9
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %11, align 4, !tbaa !9
  br label %25, !llvm.loop !17

36:                                               ; preds = %25
  store i16 1, ptr %9, align 2, !tbaa !19
  store i16 512, ptr %10, align 2, !tbaa !19
  %37 = load i16, ptr %10, align 2, !tbaa !19
  %38 = zext i16 %37 to i32
  %39 = and i32 %38, 4095
  %40 = trunc i32 %39 to i16
  store i16 %40, ptr %10, align 2, !tbaa !19
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.XSdPs, ptr %41, i32 0, i32 0
  %43 = getelementptr inbounds %struct.XSdPs_Config, ptr %42, i32 0, i32 1
  %44 = load i32, ptr %43, align 4, !tbaa !20
  %45 = load i16, ptr %10, align 2, !tbaa !19
  call void @XSdPs_WriteReg16(i32 noundef %44, i8 noundef zeroext 4, i16 noundef zeroext %45)
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = load i16, ptr %9, align 2, !tbaa !19
  %48 = zext i16 %47 to i32
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  call void @XSdPs_SetupADMA2DescTbl(ptr noundef %46, i32 noundef %48, ptr noundef %49)
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.XSdPs, ptr %50, i32 0, i32 0
  %52 = getelementptr inbounds %struct.XSdPs_Config, ptr %51, i32 0, i32 8
  %53 = load i8, ptr %52, align 32, !tbaa !21
  %54 = zext i8 %53 to i32
  %55 = icmp eq i32 %54, 0
  br i1 %55, label %56, label %59

56:                                               ; preds = %36
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = ptrtoint ptr %57 to i64
  call void @Xil_DCacheInvalidateRange(i64 noundef %58, i32 noundef 512)
  br label %59

59:                                               ; preds = %56, %36
  store i16 17, ptr @TransferMode, align 2, !tbaa !19
  %60 = load ptr, ptr %4, align 8, !tbaa !5
  %61 = load i32, ptr %8, align 4, !tbaa !9
  %62 = call i32 @XSdPs_CmdTransfer(ptr noundef %60, i32 noundef 2048, i32 noundef %61, i32 noundef 1)
  store i32 %62, ptr %6, align 4, !tbaa !9
  %63 = load i32, ptr %6, align 4, !tbaa !9
  %64 = sext i32 %63 to i64
  %65 = icmp ne i64 %64, 0
  br i1 %65, label %66, label %67

66:                                               ; preds = %59
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %93

67:                                               ; preds = %59
  br label %68

68:                                               ; preds = %84, %67
  %69 = load ptr, ptr %4, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.XSdPs, ptr %69, i32 0, i32 0
  %71 = getelementptr inbounds %struct.XSdPs_Config, ptr %70, i32 0, i32 1
  %72 = load i32, ptr %71, align 4, !tbaa !20
  %73 = call zeroext i16 @XSdPs_ReadReg16(i32 noundef %72, i8 noundef zeroext 48)
  %74 = zext i16 %73 to i32
  store i32 %74, ptr %7, align 4, !tbaa !9
  %75 = load i32, ptr %7, align 4, !tbaa !9
  %76 = and i32 %75, 32768
  %77 = icmp ne i32 %76, 0
  br i1 %77, label %78, label %83

78:                                               ; preds = %68
  %79 = load ptr, ptr %4, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.XSdPs, ptr %79, i32 0, i32 0
  %81 = getelementptr inbounds %struct.XSdPs_Config, ptr %80, i32 0, i32 1
  %82 = load i32, ptr %81, align 4, !tbaa !20
  call void @XSdPs_WriteReg16(i32 noundef %82, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  store i32 1, ptr %6, align 4, !tbaa !9
  br label %93

83:                                               ; preds = %68
  br label %84

84:                                               ; preds = %83
  %85 = load i32, ptr %7, align 4, !tbaa !9
  %86 = and i32 %85, 2
  %87 = icmp eq i32 %86, 0
  br i1 %87, label %68, label %88, !llvm.loop !22

88:                                               ; preds = %84
  %89 = load ptr, ptr %4, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.XSdPs, ptr %89, i32 0, i32 0
  %91 = getelementptr inbounds %struct.XSdPs_Config, ptr %90, i32 0, i32 1
  %92 = load i32, ptr %91, align 4, !tbaa !20
  call void @XSdPs_WriteReg16(i32 noundef %92, i8 noundef zeroext 48, i16 noundef zeroext 2)
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %93

93:                                               ; preds = %88, %78, %66
  %94 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %94, ptr %3, align 4
  store i32 1, ptr %12, align 4
  br label %95

95:                                               ; preds = %93, %23, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %96 = load i32, ptr %3, align 4
  ret i32 %96
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"", !13, i64 0, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !10, i64 56, !7, i64 60, !7, i64 64, !10, i64 80, !7, i64 84, !10, i64 100, !10, i64 104, !10, i64 108, !6, i64 112, !7, i64 128, !15, i64 512}
!13 = !{!"", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !7, i64 32}
!14 = !{!"short", !7, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!7, !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{!14, !14, i64 0}
!20 = !{!12, !10, i64 4}
!21 = !{!12, !7, i64 32}
!22 = distinct !{!22, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [167 x i8], align 1
@TransferMode = external local_unnamed_addr global i16, align 2

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

declare i32 @XSdPs_CmdTransfer(ptr noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @XSdPs_WriteReg16(i32 noundef, i8 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #1

declare void @XSdPs_SetupADMA2DescTbl(ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #0

declare void @Xil_DCacheInvalidateRange(i64 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden zeroext i16 @XSdPs_ReadReg16(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @XSdPs_Get_Mmc_ExtCsd(ptr noundef %0, ptr noundef %1) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %7, label %3

3:                                                ; preds = %2
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 36
  %5 = load i32, ptr %4, align 4, !tbaa !9
  %6 = icmp eq i32 %5, 286331153
  br i1 %6, label %8, label %14

7:                                                ; preds = %2
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 841) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %28

8:                                                ; preds = %3
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 1 dereferenceable(512) %1, i8 0, i64 512, i1 false), !tbaa !15
  %9 = getelementptr inbounds i8, ptr %0, i64 4
  %10 = load i32, ptr %9, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %10, i8 noundef zeroext 4, i16 noundef zeroext 512)
  tail call void @XSdPs_SetupADMA2DescTbl(ptr noundef nonnull %0, i32 noundef 1, ptr noundef %1) #4
  %11 = getelementptr inbounds i8, ptr %0, i64 32
  %12 = load i8, ptr %11, align 32, !tbaa !17
  %13 = icmp eq i8 %12, 0
  br i1 %13, label %15, label %17

14:                                               ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 842) #4
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %28

15:                                               ; preds = %8
  %16 = ptrtoint ptr %1 to i64
  tail call void @Xil_DCacheInvalidateRange(i64 noundef %16, i32 noundef 512) #4
  br label %17

17:                                               ; preds = %15, %8
  store i16 17, ptr @TransferMode, align 2, !tbaa !18
  %18 = tail call i32 @XSdPs_CmdTransfer(ptr noundef nonnull %0, i32 noundef 2048, i32 noundef 0, i32 noundef 1) #4
  %.not26 = icmp eq i32 %18, 0
  br i1 %.not26, label %.preheader, label %28

.preheader:                                       ; preds = %17, %23
  %19 = load i32, ptr %9, align 4, !tbaa !16
  %20 = tail call zeroext i16 @XSdPs_ReadReg16(i32 noundef %19, i8 noundef zeroext 48)
  %.not27 = icmp sgt i16 %20, -1
  br i1 %.not27, label %23, label %21

21:                                               ; preds = %.preheader
  %22 = load i32, ptr %9, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %22, i8 noundef zeroext 50, i16 noundef zeroext -3073)
  br label %28

23:                                               ; preds = %.preheader
  %24 = and i16 %20, 2
  %25 = icmp eq i16 %24, 0
  br i1 %25, label %.preheader, label %26, !llvm.loop !19

26:                                               ; preds = %23
  %27 = load i32, ptr %9, align 4, !tbaa !16
  tail call void @XSdPs_WriteReg16(i32 noundef %27, i8 noundef zeroext 48, i16 noundef zeroext 2)
  br label %28

28:                                               ; preds = %21, %26, %17, %14, %7
  %.023 = phi i32 [ 0, %14 ], [ 0, %7 ], [ 1, %21 ], [ 0, %26 ], [ 1, %17 ]
  ret i32 %.023
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 36}
!10 = !{!"", !11, i64 0, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !7, i64 52, !7, i64 53, !7, i64 54, !7, i64 55, !6, i64 56, !7, i64 60, !7, i64 64, !6, i64 80, !7, i64 84, !6, i64 100, !6, i64 104, !6, i64 108, !13, i64 112, !7, i64 128, !14, i64 512}
!11 = !{!"", !12, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20, !6, i64 24, !6, i64 28, !7, i64 32}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!7, !7, i64 0}
!16 = !{!10, !6, i64 4}
!17 = !{!10, !7, i64 32}
!18 = !{!12, !12, i64 0}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopIdiomRecognizePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass