; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000/src/ARINC653_PORT (interrupt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }

@INTERRUPT_VECTORTABLE = external dso_local global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @SPINLOCK_LOCK(ptr noundef) #1

declare i32 @CP15CoreIDGet() #1

; Function Attrs: nounwind uwtable
declare hidden void @INTERRUPT_DEFAULTHANDLER() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @SPINLOCK_UNLOCK(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @INTERRUPT_UNREGISTER(i32 noundef %0) #2 {
  %2 = alloca i8, align 1
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  call void @SPINLOCK_LOCK(ptr noundef @INTERRUPT_SPINLOCK)
  %8 = call i32 @CP15CoreIDGet()
  store i32 %8, ptr %4, align 4, !tbaa !5
  %9 = load i32, ptr %4, align 4, !tbaa !5
  %10 = icmp uge i32 %9, 2
  br i1 %10, label %11, label %12

11:                                               ; preds = %1
  br label %51

12:                                               ; preds = %1
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %14 = icmp uge i32 %13, 95
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  br label %51

16:                                               ; preds = %12
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = zext i32 %17 to i64
  %19 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %18
  %20 = load ptr, ptr %19, align 8, !tbaa !9
  %21 = load i32, ptr %3, align 4, !tbaa !5
  %22 = zext i32 %21 to i64
  %23 = getelementptr inbounds ptr, ptr %20, i64 %22
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %23, align 8, !tbaa !9
  store i8 1, ptr %6, align 1, !tbaa !11
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %39, %16
  %25 = load i32, ptr %5, align 4, !tbaa !5
  %26 = icmp ult i32 %25, 2
  br i1 %26, label %27, label %42

27:                                               ; preds = %24
  %28 = load i32, ptr %4, align 4, !tbaa !5
  %29 = zext i32 %28 to i64
  %30 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %29
  %31 = load ptr, ptr %30, align 8, !tbaa !9
  %32 = load i32, ptr %3, align 4, !tbaa !5
  %33 = zext i32 %32 to i64
  %34 = getelementptr inbounds ptr, ptr %31, i64 %33
  %35 = load ptr, ptr %34, align 8, !tbaa !9
  %36 = icmp ne ptr %35, @INTERRUPT_DEFAULTHANDLER
  br i1 %36, label %37, label %38

37:                                               ; preds = %27
  store i8 0, ptr %6, align 1, !tbaa !11
  br label %38

38:                                               ; preds = %37, %27
  br label %39

39:                                               ; preds = %38
  %40 = load i32, ptr %5, align 4, !tbaa !5
  %41 = add i32 %40, 1
  store i32 %41, ptr %5, align 4, !tbaa !5
  br label %24, !llvm.loop !12

42:                                               ; preds = %24
  %43 = load i8, ptr %6, align 1, !tbaa !11
  %44 = icmp ne i8 %43, 0
  br i1 %44, label %45, label %50

45:                                               ; preds = %42
  %46 = load i32, ptr %4, align 4, !tbaa !5
  %47 = zext i32 %46 to i64
  %48 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %47
  %49 = load i32, ptr %3, align 4, !tbaa !5
  call void @XScuGic_Disable(ptr noundef %48, i32 noundef %49)
  br label %50

50:                                               ; preds = %45, %42
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 1, ptr %2, align 1
  store i32 1, ptr %7, align 4
  br label %52

51:                                               ; preds = %15, %11
  call void @SPINLOCK_UNLOCK(ptr noundef @INTERRUPT_SPINLOCK)
  store i8 0, ptr %2, align 1
  store i32 1, ptr %7, align 4
  br label %52

52:                                               ; preds = %51, %50
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  %53 = load i8, ptr %2, align 1
  ret i8 %53
}

declare void @XScuGic_Disable(ptr noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XScuGic = type { ptr, i32, i32 }

@INTERRUPT_VECTORTABLE = external dso_local local_unnamed_addr global [2 x ptr], align 16
@INTERRUPT_SPINLOCK = external hidden global i32, align 4
@XScuGicInst = external hidden global [2 x %struct.XScuGic], align 16

declare void @SPINLOCK_LOCK(ptr noundef) local_unnamed_addr #0

declare i32 @CP15CoreIDGet() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @INTERRUPT_DEFAULTHANDLER() #1

declare void @SPINLOCK_UNLOCK(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @INTERRUPT_UNREGISTER(i32 noundef %0) local_unnamed_addr #1 {
  tail call void @SPINLOCK_LOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  %2 = tail call i32 @CP15CoreIDGet() #2
  %3 = icmp ugt i32 %2, 1
  %4 = icmp ugt i32 %0, 94
  %or.cond = or i1 %4, %3
  br i1 %or.cond, label %15, label %.split21.us

.split21.us:                                      ; preds = %1
  %5 = zext nneg i32 %2 to i64
  %6 = getelementptr inbounds [2 x ptr], ptr @INTERRUPT_VECTORTABLE, i64 0, i64 %5
  %7 = load ptr, ptr %6, align 8, !tbaa !5
  %8 = zext nneg i32 %0 to i64
  %9 = getelementptr inbounds ptr, ptr %7, i64 %8
  store ptr @INTERRUPT_DEFAULTHANDLER, ptr %9, align 8, !tbaa !5
  %10 = load ptr, ptr %6, align 8, !tbaa !5
  %11 = getelementptr inbounds ptr, ptr %10, i64 %8
  %12 = load ptr, ptr %11, align 8, !tbaa !5
  %.fr = freeze ptr %12
  %.not17.not = icmp eq ptr %.fr, @INTERRUPT_DEFAULTHANDLER
  br i1 %.not17.not, label %13, label %15

13:                                               ; preds = %.split21.us
  %14 = getelementptr inbounds [2 x %struct.XScuGic], ptr @XScuGicInst, i64 0, i64 %5
  tail call void @XScuGic_Disable(ptr noundef nonnull %14, i32 noundef %0) #2
  br label %15

15:                                               ; preds = %1, %.split21.us, %13
  %.014 = phi i8 [ 1, %13 ], [ 1, %.split21.us ], [ 0, %1 ]
  tail call void @SPINLOCK_UNLOCK(ptr noundef nonnull @INTERRUPT_SPINLOCK) #2
  ret i8 %.014
}

declare void @XScuGic_Disable(ptr noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: ADCEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass