; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc/gpiops_v3 (Write)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.XGpioPs = type { %struct.XGpioPs_Config, i32, ptr, ptr, i32, i32, i8 }
%struct.XGpioPs_Config = type { i16, i32 }

@Xil_AssertStatus = external global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_Write(ptr noundef %0, i8 noundef zeroext %1, i32 noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i8 %1, ptr %5, align 1, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !10
  %7 = load ptr, ptr %4, align 8, !tbaa !5
  %8 = icmp ne ptr %7, null
  br i1 %8, label %9, label %10

9:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %11

10:                                               ; preds = %3
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 232)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %40

11:                                               ; preds = %9
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.XGpioPs, ptr %12, i32 0, i32 1
  %14 = load i32, ptr %13, align 8, !tbaa !12
  %15 = icmp eq i32 %14, 286331153
  br i1 %15, label %16, label %17

16:                                               ; preds = %11
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %18

17:                                               ; preds = %11
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 233)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %40

18:                                               ; preds = %16
  %19 = load i8, ptr %5, align 1, !tbaa !9
  %20 = zext i8 %19 to i32
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.XGpioPs, ptr %21, i32 0, i32 6
  %23 = load i8, ptr %22, align 8, !tbaa !16
  %24 = zext i8 %23 to i32
  %25 = icmp slt i32 %20, %24
  br i1 %25, label %26, label %27

26:                                               ; preds = %18
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %28

27:                                               ; preds = %18
  call void @Xil_Assert(ptr noundef @.str, i32 noundef 234)
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !10
  br label %40

28:                                               ; preds = %26
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.XGpioPs, ptr %29, i32 0, i32 0
  %31 = getelementptr inbounds %struct.XGpioPs_Config, ptr %30, i32 0, i32 1
  %32 = load i32, ptr %31, align 4, !tbaa !17
  %33 = load i8, ptr %5, align 1, !tbaa !9
  %34 = zext i8 %33 to i32
  %35 = mul i32 %34, 4
  %36 = add i32 %35, 64
  %37 = add i32 %32, %36
  %38 = zext i32 %37 to i64
  %39 = load i32, ptr %6, align 4, !tbaa !10
  call void @Xil_Out32(i64 noundef %38, i32 noundef %39)
  br label %40

40:                                               ; preds = %28, %27, %17, %10
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 8}
!13 = !{!"", !14, i64 0, !11, i64 8, !6, i64 16, !6, i64 24, !11, i64 32, !11, i64 36, !7, i64 40}
!14 = !{!"", !15, i64 0, !11, i64 4}
!15 = !{!"short", !7, i64 0}
!16 = !{!13, !7, i64 40}
!17 = !{!13, !11, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@Xil_AssertStatus = external local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [163 x i8], align 1

declare void @Xil_Assert(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_Out32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @XGpioPs_Write(ptr noundef readonly %0, i8 noundef zeroext %1, i32 noundef %2) local_unnamed_addr #2 {
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %8, label %4

4:                                                ; preds = %3
  store i32 0, ptr @Xil_AssertStatus, align 4, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = load i32, ptr %5, align 8, !tbaa !9
  %7 = icmp eq i32 %6, 286331153
  br i1 %7, label %9, label %13

8:                                                ; preds = %3
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 232) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

9:                                                ; preds = %4
  %10 = getelementptr inbounds i8, ptr %0, i64 40
  %11 = load i8, ptr %10, align 8, !tbaa !14
  %12 = icmp ugt i8 %11, %1
  br i1 %12, label %14, label %22

13:                                               ; preds = %4
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 233) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

14:                                               ; preds = %9
  %15 = zext i8 %1 to i32
  %16 = getelementptr inbounds i8, ptr %0, i64 4
  %17 = load i32, ptr %16, align 4, !tbaa !15
  %18 = shl nuw nsw i32 %15, 2
  %19 = add nuw nsw i32 %18, 64
  %20 = add i32 %19, %17
  %21 = zext i32 %20 to i64
  tail call void @Xil_Out32(i64 noundef %21, i32 noundef %2)
  br label %23

22:                                               ; preds = %9
  tail call void @Xil_Assert(ptr noundef nonnull @.str, i32 noundef 234) #3
  store i32 1, ptr @Xil_AssertStatus, align 4, !tbaa !5
  br label %23

23:                                               ; preds = %14, %22, %13, %8
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 8}
!10 = !{!"", !11, i64 0, !6, i64 8, !13, i64 16, !13, i64 24, !6, i64 32, !6, i64 36, !7, i64 40}
!11 = !{!"", !12, i64 0, !6, i64 4}
!12 = !{!"short", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!10, !7, i64 40}
!15 = !{!10, !6, i64 4}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass