; LLVM IR from lfarcaro/ARINC653_ARMV7A_Z7000 :: ARINC653_ARMV7A_Z7000.sw/ARINC653_ARMV7A_Z7000_bsp/ps7_cortexa9_0/libsrc (DCacheInvalidateRange)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidateRange(i64 noundef %0, i32 noundef %1) #1 {
  %3 = alloca i64, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %13 = load i64, ptr %3, align 8, !tbaa !5
  %14 = trunc i64 %13 to i32
  store i32 %14, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  store ptr inttoptr (i64 4176488304 to ptr), ptr %10, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !9
  %15 = call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !13
  store i32 %15, ptr %11, align 4, !tbaa !9
  %16 = load i32, ptr %11, align 4, !tbaa !9
  store i32 %16, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  %17 = load i32, ptr %12, align 4, !tbaa !9
  store i32 %17, ptr %9, align 4, !tbaa !9
  %18 = load i32, ptr %9, align 4, !tbaa !9
  %19 = or i32 %18, 192
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %19) #3, !srcloc !14
  %20 = load i32, ptr %4, align 4, !tbaa !9
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %58

22:                                               ; preds = %2
  %23 = load i32, ptr %7, align 4, !tbaa !9
  %24 = load i32, ptr %4, align 4, !tbaa !9
  %25 = add i32 %23, %24
  store i32 %25, ptr %6, align 4, !tbaa !9
  %26 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %26, ptr %8, align 4, !tbaa !9
  call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #3, !srcloc !15
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = and i32 %27, 31
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %37

30:                                               ; preds = %22
  %31 = load i32, ptr %7, align 4, !tbaa !9
  %32 = and i32 %31, -32
  store i32 %32, ptr %7, align 4, !tbaa !9
  %33 = load i32, ptr %7, align 4, !tbaa !9
  call void @Xil_L1DCacheFlushLine(i32 noundef %33)
  call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  %34 = load i32, ptr %7, align 4, !tbaa !9
  call void @Xil_L2CacheFlushLine(i32 noundef %34)
  call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  call void @Xil_L2CacheSync()
  %35 = load i32, ptr %7, align 4, !tbaa !9
  %36 = add i32 %35, 32
  store i32 %36, ptr %7, align 4, !tbaa !9
  br label %37

37:                                               ; preds = %30, %22
  %38 = load i32, ptr %8, align 4, !tbaa !9
  %39 = and i32 %38, 31
  %40 = icmp ne i32 %39, 0
  br i1 %40, label %41, label %46

41:                                               ; preds = %37
  %42 = load i32, ptr %8, align 4, !tbaa !9
  %43 = and i32 %42, -32
  store i32 %43, ptr %8, align 4, !tbaa !9
  %44 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_L1DCacheFlushLine(i32 noundef %44)
  call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  %45 = load i32, ptr %8, align 4, !tbaa !9
  call void @Xil_L2CacheFlushLine(i32 noundef %45)
  call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  call void @Xil_L2CacheSync()
  br label %46

46:                                               ; preds = %41, %37
  br label %47

47:                                               ; preds = %51, %46
  %48 = load i32, ptr %7, align 4, !tbaa !9
  %49 = load i32, ptr %8, align 4, !tbaa !9
  %50 = icmp ult i32 %48, %49
  br i1 %50, label %51, label %57

51:                                               ; preds = %47
  %52 = load i32, ptr %7, align 4, !tbaa !9
  %53 = load ptr, ptr %10, align 8, !tbaa !11
  store volatile i32 %52, ptr %53, align 4, !tbaa !9
  call void @Xil_L2CacheSync()
  %54 = load i32, ptr %7, align 4, !tbaa !9
  call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %54) #3, !srcloc !16
  %55 = load i32, ptr %7, align 4, !tbaa !9
  %56 = add i32 %55, 32
  store i32 %56, ptr %7, align 4, !tbaa !9
  br label %47, !llvm.loop !17

57:                                               ; preds = %47
  br label %58

58:                                               ; preds = %57, %2
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !19
  %59 = load i32, ptr %9, align 4, !tbaa !9
  call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %59) #3, !srcloc !20
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_L1DCacheFlushLine(i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2WriteDebugCtrl(i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_L2CacheFlushLine(i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{i64 2147859446}
!14 = !{i64 2147859542}
!15 = !{i64 2147859632}
!16 = !{i64 2147859747}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = !{i64 2147859864}
!20 = !{i64 2147859914}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @Xil_DCacheInvalidateRange(i64 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = trunc i64 %0 to i32
  %4 = tail call i32 asm sideeffect "mrs\09$0, cpsr\0A", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !5
  %5 = or i32 %4, 192
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %5) #2, !srcloc !6
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %.loopexit, label %6

6:                                                ; preds = %2
  %7 = add i32 %3, %1
  tail call void asm sideeffect "mcr p15, 2, $0,  c0,  c0, 0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 0) #2, !srcloc !7
  %8 = and i32 %3, 31
  %.not25 = icmp eq i32 %8, 0
  br i1 %.not25, label %12, label %9

9:                                                ; preds = %6
  %10 = and i32 %3, -32
  tail call void @Xil_L1DCacheFlushLine(i32 noundef %10)
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  tail call void @Xil_L2CacheFlushLine(i32 noundef %10)
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  tail call void @Xil_L2CacheSync()
  %11 = add i32 %10, 32
  br label %12

12:                                               ; preds = %9, %6
  %.0 = phi i32 [ %11, %9 ], [ %3, %6 ]
  %13 = and i32 %7, 31
  %.not26 = icmp eq i32 %13, 0
  br i1 %.not26, label %16, label %14

14:                                               ; preds = %12
  %15 = and i32 %7, -32
  tail call void @Xil_L1DCacheFlushLine(i32 noundef %15)
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 3)
  tail call void @Xil_L2CacheFlushLine(i32 noundef %15)
  tail call void @Xil_L2WriteDebugCtrl(i32 noundef 0)
  tail call void @Xil_L2CacheSync()
  br label %16

16:                                               ; preds = %14, %12
  %.023 = phi i32 [ %15, %14 ], [ %7, %12 ]
  %17 = icmp ult i32 %.0, %.023
  br i1 %17, label %.lr.ph, label %.loopexit

.lr.ph:                                           ; preds = %16, %.lr.ph
  %.127 = phi i32 [ %18, %.lr.ph ], [ %.0, %16 ]
  store volatile i32 %.127, ptr inttoptr (i64 4176488304 to ptr), align 16, !tbaa !8
  tail call void @Xil_L2CacheSync()
  tail call void asm sideeffect "mcr p15, 0, $0,  c7,  c6, 1", "r,~{dirflag},~{fpsr},~{flags}"(i32 %.127) #2, !srcloc !12
  %18 = add i32 %.127, 32
  %19 = icmp ult i32 %18, %.023
  br i1 %19, label %.lr.ph, label %.loopexit, !llvm.loop !13

.loopexit:                                        ; preds = %.lr.ph, %16, %2
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !15
  tail call void asm sideeffect "msr\09cpsr,$0\0A", "r,~{dirflag},~{fpsr},~{flags}"(i32 %4) #2, !srcloc !16
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_L1DCacheFlushLine(i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2WriteDebugCtrl(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @Xil_L2CacheFlushLine(i32 noundef) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @Xil_L2CacheSync() local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 2147859446}
!6 = !{i64 2147859542}
!7 = !{i64 2147859632}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C/C++ TBAA"}
!12 = !{i64 2147859747}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = !{i64 2147859864}
!16 = !{i64 2147859914}


; Effective O3 passes: GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass