; LLVM IR from alenic/realGA :: src/realga.ll (ZN6RealGAC2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.RealGA = type { ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.0", %"class.std::vector.0", %class.RealGAOptions, ptr, %"class.std::vector", float, i32, ptr, ptr, ptr, i32, float }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealGAOptions = type { i64, i64, %"class.std::vector", %"class.std::vector", i32, i32, float, i8, i32, i32, float, i32, i32, i32, float, float, float, float }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTV6RealGA = external dso_local unnamed_addr constant { [3 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296) %0) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %5 = load ptr, ptr %2, align 8
  store ptr getelementptr inbounds inrange(-16, 8) ({ [3 x ptr] }, ptr @_ZTV6RealGA, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  %6 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 1
  call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %7 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 2
  call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  %8 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 3
  call void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #3
  %9 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 4
  call void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  %10 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 5
  invoke void @_ZN13RealGAOptionsC1Ev(ptr noundef nonnull align 8 dereferenceable(120) %10)
          to label %11 unwind label %19

11:                                               ; preds = %1
  %12 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 7
  call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #3
  %13 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 6
  store ptr null, ptr %13, align 8, !tbaa !11
  %14 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 13
  store i32 0, ptr %14, align 8, !tbaa !30
  %15 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 10
  store ptr null, ptr %15, align 8, !tbaa !31
  %16 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 11
  store ptr null, ptr %16, align 8, !tbaa !32
  %17 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 12
  store ptr null, ptr %17, align 8, !tbaa !33
  %18 = getelementptr inbounds %class.RealGA, ptr %5, i32 0, i32 14
  store float 1.000000e+00, ptr %18, align 4, !tbaa !34
  ret void

19:                                               ; preds = %1
  %20 = landingpad { ptr, i32 }
          cleanup
  %21 = extractvalue { ptr, i32 } %20, 0
  store ptr %21, ptr %3, align 8
  %22 = extractvalue { ptr, i32 } %20, 1
  store i32 %22, ptr %4, align 4
  call void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %9) #3
  call void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #3
  call void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %7) #3
  call void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  br label %23

23:                                               ; preds = %19
  %24 = load ptr, ptr %3, align 8
  %25 = load i32, ptr %4, align 4
  %26 = insertvalue { ptr, i32 } poison, ptr %24, 0
  %27 = insertvalue { ptr, i32 } %26, i32 %25, 1
  resume { ptr, i32 } %27
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN13RealGAOptionsC1Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !6, i64 224}
!12 = !{!"_ZTS6RealGA", !13, i64 8, !13, i64 32, !17, i64 56, !17, i64 80, !21, i64 104, !6, i64 224, !13, i64 232, !25, i64 256, !23, i64 260, !6, i64 264, !6, i64 272, !6, i64 280, !23, i64 288, !25, i64 292}
!13 = !{!"_ZTSSt6vectorIfSaIfEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTS13RealGAOptions", !22, i64 0, !22, i64 8, !13, i64 16, !13, i64 40, !23, i64 64, !24, i64 68, !25, i64 72, !26, i64 76, !27, i64 80, !23, i64 84, !25, i64 88, !28, i64 92, !23, i64 96, !29, i64 100, !25, i64 104, !25, i64 108, !25, i64 112, !25, i64 116}
!22 = !{!"long", !7, i64 0}
!23 = !{!"int", !7, i64 0}
!24 = !{!"_ZTS11VerboseType", !7, i64 0}
!25 = !{!"float", !7, i64 0}
!26 = !{!"bool", !7, i64 0}
!27 = !{!"_ZTS13SelectionType", !7, i64 0}
!28 = !{!"_ZTS13CrossoverType", !7, i64 0}
!29 = !{!"_ZTS12MutationType", !7, i64 0}
!30 = !{!12, !23, i64 288}
!31 = !{!12, !6, i64 264}
!32 = !{!12, !6, i64 272}
!33 = !{!12, !6, i64 280}
!34 = !{!12, !25, i64 292}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV6RealGA = external dso_local unnamed_addr constant { [3 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296) %0) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  store ptr getelementptr inbounds inrange(-16, 8) (i8, ptr @_ZTV6RealGA, i64 16), ptr %0, align 8, !tbaa !5
  %2 = getelementptr inbounds i8, ptr %0, i64 8
  tail call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  %3 = getelementptr inbounds i8, ptr %0, i64 32
  tail call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  %4 = getelementptr inbounds i8, ptr %0, i64 56
  tail call void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  %5 = getelementptr inbounds i8, ptr %0, i64 80
  tail call void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #4
  %6 = getelementptr inbounds i8, ptr %0, i64 104
  invoke void @_ZN13RealGAOptionsC1Ev(ptr noundef nonnull align 8 dereferenceable(120) %6)
          to label %7 unwind label %12

7:                                                ; preds = %1
  %8 = getelementptr inbounds i8, ptr %0, i64 232
  tail call void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  %9 = getelementptr inbounds i8, ptr %0, i64 224
  store ptr null, ptr %9, align 8, !tbaa !8
  %10 = getelementptr inbounds i8, ptr %0, i64 264
  %11 = getelementptr inbounds i8, ptr %0, i64 292
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(28) %10, i8 0, i64 28, i1 false)
  store float 1.000000e+00, ptr %11, align 4, !tbaa !29
  ret void

12:                                               ; preds = %1
  %13 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #4
  tail call void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #4
  tail call void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %3) #4
  tail call void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #4
  resume { ptr, i32 } %13
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfSaIfEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI14RealChromosomeSaIS0_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

declare void @_ZN13RealGAOptionsC1Ev(ptr noundef nonnull align 8 dereferenceable(120)) unnamed_addr #2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI14RealChromosomeSaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIfSaIfEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !14, i64 224}
!9 = !{!"_ZTS6RealGA", !10, i64 8, !10, i64 32, !16, i64 56, !16, i64 80, !20, i64 104, !14, i64 224, !10, i64 232, !24, i64 256, !22, i64 260, !14, i64 264, !14, i64 272, !14, i64 280, !22, i64 288, !24, i64 292}
!10 = !{!"_ZTSSt6vectorIfSaIfEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !15, i64 0}
!15 = !{!"omnipotent char", !7, i64 0}
!16 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!20 = !{!"_ZTS13RealGAOptions", !21, i64 0, !21, i64 8, !10, i64 16, !10, i64 40, !22, i64 64, !23, i64 68, !24, i64 72, !25, i64 76, !26, i64 80, !22, i64 84, !24, i64 88, !27, i64 92, !22, i64 96, !28, i64 100, !24, i64 104, !24, i64 108, !24, i64 112, !24, i64 116}
!21 = !{!"long", !15, i64 0}
!22 = !{!"int", !15, i64 0}
!23 = !{!"_ZTS11VerboseType", !15, i64 0}
!24 = !{!"float", !15, i64 0}
!25 = !{!"bool", !15, i64 0}
!26 = !{!"_ZTS13SelectionType", !15, i64 0}
!27 = !{!"_ZTS13CrossoverType", !15, i64 0}
!28 = !{!"_ZTS12MutationType", !15, i64 0}
!29 = !{!9, !24, i64 292}


; Effective O3 passes: EarlyCSEPass,InstCombinePass,MemCpyOptPass,SROAPass,SimplifyCFGPass,TailCallElimPass