; LLVM IR from mickypaganini/SSI2016-jet-clustering :: spartyjet-4.0.2_mac/External/fastjet-3.0.0/plugins/SISCone/siscone/siscone/are_c651b72d (ZN7siscone5CareaC2Ev)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.siscone::Carea" = type { %"class.siscone::Csiscone.base", i32, double, double, double, double, double, %"class.std::vector.40" }
%"class.siscone::Csiscone.base" = type <{ %"class.siscone::Cstable_cones", %"class.siscone::Csplit_merge.base", [7 x i8], %"class.std::vector.35", i8 }>
%"class.siscone::Cstable_cones" = type { %"class.siscone::Cvicinity", %"class.std::vector.0", ptr, i32, double, double, %"class.siscone::Cmomentum", ptr, ptr, i32, i32, %"class.siscone::Cmomentum", %"class.std::vector.15", %"class.std::vector.20", double }
%"class.siscone::Cvicinity" = type { ptr, double, double, double, double, double, double, i32, %"class.std::vector.0", %"class.std::vector.5", ptr, %"class.std::vector.10", i32, double, double }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.siscone::Cmomentum" = type <{ double, double, double, double, double, double, i32, i32, %"class.siscone::Creference", [4 x i8] }>
%"class.siscone::Creference" = type { [3 x i32] }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.20" = type { %"struct.std::_Vector_base.21" }
%"struct.std::_Vector_base.21" = type { %"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.siscone::Csplit_merge.base" = type <{ i32, [4 x i8], %"class.std::vector.0", %"class.std::vector.25", i32, [4 x i8], %"class.std::vector.0", %"class.std::vector.0", i32, [4 x i8], double, %"class.std::vector.30", ptr, i32, i8, [3 x i8], %"class.siscone::Csplit_merge_ptcomparison", double, double, %"class.std::auto_ptr", double, i8 }>
%"class.std::vector.25" = type { %"struct.std::_Vector_base.26" }
%"struct.std::_Vector_base.26" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.30" = type { %"struct.std::_Vector_base.31" }
%"struct.std::_Vector_base.31" = type { %"struct.std::_Vector_base<siscone::Cjet, std::allocator<siscone::Cjet>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cjet, std::allocator<siscone::Cjet>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cjet, std::allocator<siscone::Cjet>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cjet, std::allocator<siscone::Cjet>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.siscone::Csplit_merge_ptcomparison" = type <{ ptr, ptr, i32, [4 x i8] }>
%"class.std::auto_ptr" = type { ptr }
%"class.std::vector.35" = type { %"struct.std::_Vector_base.36" }
%"struct.std::_Vector_base.36" = type { %"struct.std::_Vector_base<std::vector<siscone::Cmomentum>, std::allocator<std::vector<siscone::Cmomentum>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<siscone::Cmomentum>, std::allocator<std::vector<siscone::Cmomentum>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<siscone::Cmomentum>, std::allocator<std::vector<siscone::Cmomentum>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<siscone::Cmomentum>, std::allocator<std::vector<siscone::Cmomentum>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.40" = type { %"struct.std::_Vector_base.41" }
%"struct.std::_Vector_base.41" = type { %"struct.std::_Vector_base<siscone::Cjet_area, std::allocator<siscone::Cjet_area>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cjet_area, std::allocator<siscone::Cjet_area>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cjet_area, std::allocator<siscone::Cjet_area>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cjet_area, std::allocator<siscone::Cjet_area>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7siscone5CareaC2Ev(ptr noundef nonnull align 8 dereferenceable(776) %0) unnamed_addr #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  call void @_ZN7siscone8CsisconeC2Ev(ptr noundef nonnull align 8 dereferenceable(705) %3)
  %4 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 7
  call void @_ZNSt6vectorIN7siscone9Cjet_areaESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %5 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 1
  store i32 60, ptr %5, align 4, !tbaa !9
  %6 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 2
  store double 6.000000e+00, ptr %6, align 8, !tbaa !59
  %7 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 3
  store double 5.000000e-01, ptr %7, align 8, !tbaa !60
  %8 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 4
  store double 1.000000e-100, ptr %8, align 8, !tbaa !61
  %9 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 5
  store double 5.000000e-02, ptr %9, align 8, !tbaa !62
  %10 = getelementptr inbounds %"class.siscone::Carea", ptr %3, i32 0, i32 6
  store double 0x2D404BD984990E6F, ptr %10, align 8, !tbaa !63
  ret void
}

declare void @_ZN7siscone8CsisconeC2Ev(ptr noundef nonnull align 8 dereferenceable(705)) unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN7siscone9Cjet_areaESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !15, i64 708}
!10 = !{!"_ZTSN7siscone5CareaE", !11, i64 0, !15, i64 708, !14, i64 712, !14, i64 720, !14, i64 728, !14, i64 736, !14, i64 744, !55, i64 752}
!11 = !{!"_ZTSN7siscone8CsisconeE", !12, i64 0, !38, i64 448, !51, i64 680, !47, i64 704}
!12 = !{!"_ZTSN7siscone13Cstable_conesE", !13, i64 0, !16, i64 168, !6, i64 192, !15, i64 200, !14, i64 208, !14, i64 216, !28, i64 224, !6, i64 296, !6, i64 304, !15, i64 312, !15, i64 316, !28, i64 320, !30, i64 392, !34, i64 416, !14, i64 440}
!13 = !{!"_ZTSN7siscone9CvicinityE", !6, i64 0, !14, i64 8, !14, i64 16, !14, i64 24, !14, i64 32, !14, i64 40, !14, i64 48, !15, i64 56, !16, i64 64, !20, i64 88, !6, i64 112, !24, i64 120, !15, i64 144, !14, i64 152, !14, i64 160}
!14 = !{!"double", !7, i64 0}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIN7siscone9CmomentumESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIN7siscone19Cvicinity_inclusionESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!"_ZTSSt6vectorIPN7siscone13Cvicinity_elmESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!28 = !{!"_ZTSN7siscone9CmomentumE", !14, i64 0, !14, i64 8, !14, i64 16, !14, i64 24, !14, i64 32, !14, i64 40, !15, i64 48, !15, i64 52, !29, i64 56}
!29 = !{!"_ZTSN7siscone10CreferenceE", !7, i64 0}
!30 = !{!"_ZTSSt6vectorIPN7siscone9CmomentumESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!34 = !{!"_ZTSSt6vectorISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSN7siscone12Csplit_mergeE", !15, i64 0, !16, i64 8, !39, i64 32, !15, i64 56, !16, i64 64, !16, i64 88, !15, i64 112, !14, i64 120, !43, i64 128, !6, i64 152, !15, i64 160, !47, i64 164, !48, i64 168, !14, i64 192, !14, i64 200, !50, i64 208, !14, i64 216, !47, i64 224}
!39 = !{!"_ZTSSt6vectorIdSaIdEE", !40, i64 0}
!40 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !42, i64 0}
!42 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!43 = !{!"_ZTSSt6vectorIN7siscone4CjetESaIS1_EE", !44, i64 0}
!44 = !{!"_ZTSSt12_Vector_baseIN7siscone4CjetESaIS1_EE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIN7siscone4CjetESaIS1_EE12_Vector_implE", !46, i64 0}
!46 = !{!"_ZTSNSt12_Vector_baseIN7siscone4CjetESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!47 = !{!"bool", !7, i64 0}
!48 = !{!"_ZTSN7siscone25Csplit_merge_ptcomparisonE", !6, i64 0, !6, i64 8, !49, i64 16}
!49 = !{!"_ZTSN7siscone18Esplit_merge_scaleE", !7, i64 0}
!50 = !{!"_ZTSSt8auto_ptrISt8multisetIN7siscone4CjetENS1_25Csplit_merge_ptcomparisonESaIS2_EEE", !6, i64 0}
!51 = !{!"_ZTSSt6vectorIS_IN7siscone9CmomentumESaIS1_EESaIS3_EE", !52, i64 0}
!52 = !{!"_ZTSSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE12_Vector_implE", !54, i64 0}
!54 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!55 = !{!"_ZTSSt6vectorIN7siscone9Cjet_areaESaIS1_EE", !56, i64 0}
!56 = !{!"_ZTSSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE", !57, i64 0}
!57 = !{!"_ZTSNSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE12_Vector_implE", !58, i64 0}
!58 = !{!"_ZTSNSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!59 = !{!10, !14, i64 712}
!60 = !{!10, !14, i64 720}
!61 = !{!10, !14, i64 728}
!62 = !{!10, !14, i64 736}
!63 = !{!10, !14, i64 744}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7siscone5CareaC2Ev(ptr noundef nonnull align 8 dereferenceable(776) %0) unnamed_addr #0 align 2 {
  tail call void @_ZN7siscone8CsisconeC2Ev(ptr noundef nonnull align 8 dereferenceable(705) %0)
  %2 = getelementptr inbounds i8, ptr %0, i64 752
  tail call void @_ZNSt6vectorIN7siscone9Cjet_areaESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #3
  %3 = getelementptr inbounds i8, ptr %0, i64 708
  store i32 60, ptr %3, align 4, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %0, i64 712
  store <2 x double> <double 6.000000e+00, double 5.000000e-01>, ptr %4, align 8, !tbaa !58
  %5 = getelementptr inbounds i8, ptr %0, i64 728
  store <2 x double> <double 1.000000e-100, double 5.000000e-02>, ptr %5, align 8, !tbaa !58
  %6 = getelementptr inbounds i8, ptr %0, i64 744
  store double 0x2D404BD984990E6F, ptr %6, align 8, !tbaa !59
  ret void
}

declare void @_ZN7siscone8CsisconeC2Ev(ptr noundef nonnull align 8 dereferenceable(705)) unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIN7siscone9Cjet_areaESaIS1_EEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 708}
!6 = !{!"_ZTSN7siscone5CareaE", !7, i64 0, !14, i64 708, !13, i64 712, !13, i64 720, !13, i64 728, !13, i64 736, !13, i64 744, !54, i64 752}
!7 = !{!"_ZTSN7siscone8CsisconeE", !8, i64 0, !37, i64 448, !50, i64 680, !46, i64 704}
!8 = !{!"_ZTSN7siscone13Cstable_conesE", !9, i64 0, !15, i64 168, !10, i64 192, !14, i64 200, !13, i64 208, !13, i64 216, !27, i64 224, !10, i64 296, !10, i64 304, !14, i64 312, !14, i64 316, !27, i64 320, !29, i64 392, !33, i64 416, !13, i64 440}
!9 = !{!"_ZTSN7siscone9CvicinityE", !10, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !13, i64 48, !14, i64 56, !15, i64 64, !19, i64 88, !10, i64 112, !23, i64 120, !14, i64 144, !13, i64 152, !13, i64 160}
!10 = !{!"any pointer", !11, i64 0}
!11 = !{!"omnipotent char", !12, i64 0}
!12 = !{!"Simple C++ TBAA"}
!13 = !{!"double", !11, i64 0}
!14 = !{!"int", !11, i64 0}
!15 = !{!"_ZTSSt6vectorIN7siscone9CmomentumESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!19 = !{!"_ZTSSt6vectorIN7siscone19Cvicinity_inclusionESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7siscone13Cvicinity_elmESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!27 = !{!"_ZTSN7siscone9CmomentumE", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !13, i64 40, !14, i64 48, !14, i64 52, !28, i64 56}
!28 = !{!"_ZTSN7siscone10CreferenceE", !11, i64 0}
!29 = !{!"_ZTSSt6vectorIPN7siscone9CmomentumESaIS2_EE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!33 = !{!"_ZTSSt6vectorISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!37 = !{!"_ZTSN7siscone12Csplit_mergeE", !14, i64 0, !15, i64 8, !38, i64 32, !14, i64 56, !15, i64 64, !15, i64 88, !14, i64 112, !13, i64 120, !42, i64 128, !10, i64 152, !14, i64 160, !46, i64 164, !47, i64 168, !13, i64 192, !13, i64 200, !49, i64 208, !13, i64 216, !46, i64 224}
!38 = !{!"_ZTSSt6vectorIdSaIdEE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!42 = !{!"_ZTSSt6vectorIN7siscone4CjetESaIS1_EE", !43, i64 0}
!43 = !{!"_ZTSSt12_Vector_baseIN7siscone4CjetESaIS1_EE", !44, i64 0}
!44 = !{!"_ZTSNSt12_Vector_baseIN7siscone4CjetESaIS1_EE12_Vector_implE", !45, i64 0}
!45 = !{!"_ZTSNSt12_Vector_baseIN7siscone4CjetESaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!46 = !{!"bool", !11, i64 0}
!47 = !{!"_ZTSN7siscone25Csplit_merge_ptcomparisonE", !10, i64 0, !10, i64 8, !48, i64 16}
!48 = !{!"_ZTSN7siscone18Esplit_merge_scaleE", !11, i64 0}
!49 = !{!"_ZTSSt8auto_ptrISt8multisetIN7siscone4CjetENS1_25Csplit_merge_ptcomparisonESaIS2_EEE", !10, i64 0}
!50 = !{!"_ZTSSt6vectorIS_IN7siscone9CmomentumESaIS1_EESaIS3_EE", !51, i64 0}
!51 = !{!"_ZTSSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE", !52, i64 0}
!52 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE12_Vector_implE", !53, i64 0}
!53 = !{!"_ZTSNSt12_Vector_baseISt6vectorIN7siscone9CmomentumESaIS2_EESaIS4_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!54 = !{!"_ZTSSt6vectorIN7siscone9Cjet_areaESaIS1_EE", !55, i64 0}
!55 = !{!"_ZTSSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE", !56, i64 0}
!56 = !{!"_ZTSNSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE12_Vector_implE", !57, i64 0}
!57 = !{!"_ZTSNSt12_Vector_baseIN7siscone9Cjet_areaESaIS1_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!58 = !{!13, !13, i64 0}
!59 = !{!6, !13, i64 744}


; Effective O3 passes: InstCombinePass,SLPVectorizerPass,SROAPass,TailCallElimPass