; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (ulTaskGenericNotifyTake)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [32 x i8], i64, i64, [1 x i32], [1 x i8] }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortEnterCritical() #1

declare void @vPortExitCritical() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

; Function Attrs: nounwind uwtable
declare hidden void @prvAddCurrentTaskToDelayedList(i32 noundef, i64 noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i32 @ulTaskGenericNotifyTake(i64 noundef %0, i64 noundef %1, i32 noundef %2) #3 {
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i64 %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %8 = load i64, ptr %4, align 8, !tbaa !5
  %9 = icmp ult i64 %8, 1
  %10 = zext i1 %9 to i32
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %12, label %14

12:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %13

13:                                               ; preds = %13, %12
  br label %13

14:                                               ; preds = %3
  call void @vPortEnterCritical()
  %15 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %16 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %15, i32 0, i32 8
  %17 = load i64, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds [1 x i32], ptr %16, i64 0, i64 %17
  %19 = load volatile i32, ptr %18, align 4, !tbaa !9
  %20 = zext i32 %19 to i64
  %21 = icmp eq i64 %20, 0
  br i1 %21, label %22, label %33

22:                                               ; preds = %14
  %23 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %24 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %23, i32 0, i32 9
  %25 = load i64, ptr %4, align 8, !tbaa !5
  %26 = getelementptr inbounds [1 x i8], ptr %24, i64 0, i64 %25
  store volatile i8 1, ptr %26, align 1, !tbaa !13
  %27 = load i32, ptr %6, align 4, !tbaa !9
  %28 = icmp ugt i32 %27, 0
  br i1 %28, label %29, label %31

29:                                               ; preds = %22
  %30 = load i32, ptr %6, align 4, !tbaa !9
  call void @prvAddCurrentTaskToDelayedList(i32 noundef %30, i64 noundef 1)
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !14
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !15
  br label %32

31:                                               ; preds = %22
  br label %32

32:                                               ; preds = %31, %29
  br label %34

33:                                               ; preds = %14
  br label %34

34:                                               ; preds = %33, %32
  call void @vPortExitCritical()
  call void @vPortEnterCritical()
  %35 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %36 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %35, i32 0, i32 8
  %37 = load i64, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds [1 x i32], ptr %36, i64 0, i64 %37
  %39 = load volatile i32, ptr %38, align 4, !tbaa !9
  store i32 %39, ptr %7, align 4, !tbaa !9
  %40 = load i32, ptr %7, align 4, !tbaa !9
  %41 = zext i32 %40 to i64
  %42 = icmp ne i64 %41, 0
  br i1 %42, label %43, label %59

43:                                               ; preds = %34
  %44 = load i64, ptr %5, align 8, !tbaa !5
  %45 = icmp ne i64 %44, 0
  br i1 %45, label %46, label %51

46:                                               ; preds = %43
  %47 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %48 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %47, i32 0, i32 8
  %49 = load i64, ptr %4, align 8, !tbaa !5
  %50 = getelementptr inbounds [1 x i32], ptr %48, i64 0, i64 %49
  store volatile i32 0, ptr %50, align 4, !tbaa !9
  br label %58

51:                                               ; preds = %43
  %52 = load i32, ptr %7, align 4, !tbaa !9
  %53 = sub i32 %52, 1
  %54 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %55 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %54, i32 0, i32 8
  %56 = load i64, ptr %4, align 8, !tbaa !5
  %57 = getelementptr inbounds [1 x i32], ptr %55, i64 0, i64 %56
  store volatile i32 %53, ptr %57, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %51, %46
  br label %60

59:                                               ; preds = %34
  br label %60

60:                                               ; preds = %59, %58
  %61 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %62 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %61, i32 0, i32 9
  %63 = load i64, ptr %4, align 8, !tbaa !5
  %64 = getelementptr inbounds [1 x i8], ptr %62, i64 0, i64 %63
  store volatile i8 0, ptr %64, align 1, !tbaa !13
  call void @vPortExitCritical()
  %65 = load i32, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  ret i32 %65
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{i64 2148455248}
!15 = !{i64 2148455317}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@pxCurrentTCB = external dso_local global ptr, align 8

declare void @vPortEnterCritical() local_unnamed_addr #0

declare void @vPortExitCritical() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @prvAddCurrentTaskToDelayedList(i32 noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @ulTaskGenericNotifyTake(i64 noundef %0, i64 noundef %1, i32 noundef %2) local_unnamed_addr #2 {
  %.not = icmp eq i64 %0, 0
  br i1 %.not, label %6, label %4

4:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %5

5:                                                ; preds = %5, %4
  br label %5

6:                                                ; preds = %3
  tail call void @vPortEnterCritical() #3
  %7 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %7, i64 152
  %9 = load volatile i32, ptr %8, align 4, !tbaa !9
  %10 = icmp eq i32 %9, 0
  br i1 %10, label %11, label %15

11:                                               ; preds = %6
  %12 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %12, i64 156
  store volatile i8 1, ptr %13, align 1, !tbaa !11
  %.not13 = icmp eq i32 %2, 0
  br i1 %.not13, label %15, label %14

14:                                               ; preds = %11
  tail call void @prvAddCurrentTaskToDelayedList(i32 noundef %2, i64 noundef 1)
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !12
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !13
  br label %15

15:                                               ; preds = %6, %14, %11
  tail call void @vPortExitCritical() #3
  tail call void @vPortEnterCritical() #3
  %16 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %16, i64 152
  %18 = load volatile i32, ptr %17, align 4, !tbaa !9
  %.not14 = icmp eq i32 %18, 0
  br i1 %.not14, label %22, label %.sink.split

.sink.split:                                      ; preds = %15
  %.not15 = icmp eq i64 %1, 0
  %19 = add i32 %18, -1
  %.sink = select i1 %.not15, i32 %19, i32 0
  %20 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %20, i64 152
  store volatile i32 %.sink, ptr %21, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %.sink.split, %15
  %23 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %24 = getelementptr inbounds i8, ptr %23, i64 156
  store volatile i8 0, ptr %24, align 1, !tbaa !11
  tail call void @vPortExitCritical() #3
  ret i32 %18
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{i64 2148455248}
!13 = !{i64 2148455317}


; Effective O3 passes: GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass