; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueueSemaphoreTake)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }
%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.SemaphoreData = type { ptr, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare void @vPortEnterCritical() #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

declare void @vPortExitCritical() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueSemaphoreTake(ptr noundef %0, i32 noundef %1) #3 {
  %3 = alloca i64, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca %struct.xTIME_OUT, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i32, align 4
  %12 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 16, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %13, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  store i64 0, ptr %9, align 8, !tbaa !11
  %14 = load ptr, ptr %8, align 8, !tbaa !5
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %18

16:                                               ; preds = %2
  call void @vPortRaiseBASEPRI()
  br label %17

17:                                               ; preds = %17, %16
  br label %17

18:                                               ; preds = %2
  %19 = load ptr, ptr %8, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.QueueDefinition, ptr %19, i32 0, i32 7
  %21 = load i64, ptr %20, align 8, !tbaa !13
  %22 = icmp eq i64 %21, 0
  %23 = zext i1 %22 to i32
  %24 = icmp eq i32 %23, 0
  br i1 %24, label %25, label %27

25:                                               ; preds = %18
  call void @vPortRaiseBASEPRI()
  br label %26

26:                                               ; preds = %26, %25
  br label %26

27:                                               ; preds = %18
  %28 = call i64 @xTaskGetSchedulerState()
  %29 = icmp eq i64 %28, 0
  br i1 %29, label %30, label %33

30:                                               ; preds = %27
  %31 = load i32, ptr %5, align 4, !tbaa !9
  %32 = icmp ne i32 %31, 0
  br label %33

33:                                               ; preds = %30, %27
  %34 = phi i1 [ false, %27 ], [ %32, %30 ]
  %35 = xor i1 %34, true
  %36 = zext i1 %35 to i32
  %37 = icmp eq i32 %36, 0
  br i1 %37, label %38, label %40

38:                                               ; preds = %33
  call void @vPortRaiseBASEPRI()
  br label %39

39:                                               ; preds = %39, %38
  br label %39

40:                                               ; preds = %33
  br label %41

41:                                               ; preds = %173, %40
  call void @vPortEnterCritical()
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  %42 = load ptr, ptr %8, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.QueueDefinition, ptr %42, i32 0, i32 5
  %44 = load volatile i64, ptr %43, align 8, !tbaa !17
  store i64 %44, ptr %10, align 8, !tbaa !11
  %45 = load i64, ptr %10, align 8, !tbaa !11
  %46 = icmp ugt i64 %45, 0
  br i1 %46, label %47, label %81

47:                                               ; preds = %41
  %48 = load i64, ptr %10, align 8, !tbaa !11
  %49 = sub i64 %48, 1
  %50 = load ptr, ptr %8, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.QueueDefinition, ptr %50, i32 0, i32 5
  store volatile i64 %49, ptr %51, align 8, !tbaa !17
  %52 = load ptr, ptr %8, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.QueueDefinition, ptr %52, i32 0, i32 0
  %54 = load ptr, ptr %53, align 8, !tbaa !18
  %55 = icmp eq ptr %54, null
  br i1 %55, label %56, label %61

56:                                               ; preds = %47
  %57 = call ptr @pvTaskIncrementMutexHeldCount()
  %58 = load ptr, ptr %8, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.QueueDefinition, ptr %58, i32 0, i32 2
  %60 = getelementptr inbounds %struct.SemaphoreData, ptr %59, i32 0, i32 0
  store ptr %57, ptr %60, align 8, !tbaa !19
  br label %62

61:                                               ; preds = %47
  br label %62

62:                                               ; preds = %61, %56
  %63 = load ptr, ptr %8, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.QueueDefinition, ptr %63, i32 0, i32 3
  %65 = getelementptr inbounds %struct.xLIST, ptr %64, i32 0, i32 0
  %66 = load volatile i64, ptr %65, align 8, !tbaa !20
  %67 = icmp eq i64 %66, 0
  %68 = zext i1 %67 to i64
  %69 = select i1 %67, i64 1, i64 0
  %70 = icmp eq i64 %69, 0
  br i1 %70, label %71, label %79

71:                                               ; preds = %62
  %72 = load ptr, ptr %8, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.QueueDefinition, ptr %72, i32 0, i32 3
  %74 = call i64 @xTaskRemoveFromEventList(ptr noundef %73)
  %75 = icmp ne i64 %74, 0
  br i1 %75, label %76, label %77

76:                                               ; preds = %71
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !22
  br label %78

77:                                               ; preds = %71
  br label %78

78:                                               ; preds = %77, %76
  br label %80

79:                                               ; preds = %62
  br label %80

80:                                               ; preds = %79, %78
  call void @vPortExitCritical()
  store i64 1, ptr %3, align 8
  store i32 1, ptr %11, align 4
  br label %100

81:                                               ; preds = %41
  %82 = load i32, ptr %5, align 4, !tbaa !9
  %83 = icmp eq i32 %82, 0
  br i1 %83, label %84, label %92

84:                                               ; preds = %81
  %85 = load i64, ptr %9, align 8, !tbaa !11
  %86 = icmp eq i64 %85, 0
  %87 = zext i1 %86 to i32
  %88 = icmp eq i32 %87, 0
  br i1 %88, label %89, label %91

89:                                               ; preds = %84
  call void @vPortRaiseBASEPRI()
  br label %90

90:                                               ; preds = %90, %89
  br label %90

91:                                               ; preds = %84
  call void @vPortExitCritical()
  store i64 0, ptr %3, align 8
  store i32 1, ptr %11, align 4
  br label %100

92:                                               ; preds = %81
  %93 = load i64, ptr %6, align 8, !tbaa !11
  %94 = icmp eq i64 %93, 0
  br i1 %94, label %95, label %96

95:                                               ; preds = %92
  call void @vTaskInternalSetTimeOutState(ptr noundef %7)
  store i64 1, ptr %6, align 8, !tbaa !11
  br label %97

96:                                               ; preds = %92
  br label %97

97:                                               ; preds = %96, %95
  br label %98

98:                                               ; preds = %97
  br label %99

99:                                               ; preds = %98
  store i32 0, ptr %11, align 4
  br label %100

100:                                              ; preds = %99, %91, %80
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  %101 = load i32, ptr %11, align 4
  switch i32 %101, label %174 [
    i32 0, label %102
  ]

102:                                              ; preds = %100
  call void @vPortExitCritical()
  call void @vTaskSuspendAll()
  call void @vPortEnterCritical()
  %103 = load ptr, ptr %8, align 8, !tbaa !5
  %104 = getelementptr inbounds %struct.QueueDefinition, ptr %103, i32 0, i32 8
  %105 = load volatile i8, ptr %104, align 8, !tbaa !23
  %106 = sext i8 %105 to i32
  %107 = icmp eq i32 %106, -1
  br i1 %107, label %108, label %111

108:                                              ; preds = %102
  %109 = load ptr, ptr %8, align 8, !tbaa !5
  %110 = getelementptr inbounds %struct.QueueDefinition, ptr %109, i32 0, i32 8
  store volatile i8 0, ptr %110, align 8, !tbaa !23
  br label %111

111:                                              ; preds = %108, %102
  %112 = load ptr, ptr %8, align 8, !tbaa !5
  %113 = getelementptr inbounds %struct.QueueDefinition, ptr %112, i32 0, i32 9
  %114 = load volatile i8, ptr %113, align 1, !tbaa !24
  %115 = sext i8 %114 to i32
  %116 = icmp eq i32 %115, -1
  br i1 %116, label %117, label %120

117:                                              ; preds = %111
  %118 = load ptr, ptr %8, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.QueueDefinition, ptr %118, i32 0, i32 9
  store volatile i8 0, ptr %119, align 1, !tbaa !24
  br label %120

120:                                              ; preds = %117, %111
  call void @vPortExitCritical()
  %121 = call i64 @xTaskCheckForTimeOut(ptr noundef %7, ptr noundef %5)
  %122 = icmp eq i64 %121, 0
  br i1 %122, label %123, label %153

123:                                              ; preds = %120
  %124 = load ptr, ptr %8, align 8, !tbaa !5
  %125 = call i64 @prvIsQueueEmpty(ptr noundef %124)
  %126 = icmp ne i64 %125, 0
  br i1 %126, label %127, label %149

127:                                              ; preds = %123
  %128 = load ptr, ptr %8, align 8, !tbaa !5
  %129 = getelementptr inbounds %struct.QueueDefinition, ptr %128, i32 0, i32 0
  %130 = load ptr, ptr %129, align 8, !tbaa !18
  %131 = icmp eq ptr %130, null
  br i1 %131, label %132, label %138

132:                                              ; preds = %127
  call void @vPortEnterCritical()
  %133 = load ptr, ptr %8, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.QueueDefinition, ptr %133, i32 0, i32 2
  %135 = getelementptr inbounds %struct.SemaphoreData, ptr %134, i32 0, i32 0
  %136 = load ptr, ptr %135, align 8, !tbaa !19
  %137 = call i64 @xTaskPriorityInherit(ptr noundef %136)
  store i64 %137, ptr %9, align 8, !tbaa !11
  call void @vPortExitCritical()
  br label %139

138:                                              ; preds = %127
  br label %139

139:                                              ; preds = %138, %132
  %140 = load ptr, ptr %8, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.QueueDefinition, ptr %140, i32 0, i32 4
  %142 = load i32, ptr %5, align 4, !tbaa !9
  call void @vTaskPlaceOnEventList(ptr noundef %141, i32 noundef %142)
  %143 = load ptr, ptr %8, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %143)
  %144 = call i64 @xTaskResumeAll()
  %145 = icmp eq i64 %144, 0
  br i1 %145, label %146, label %147

146:                                              ; preds = %139
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !25
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !26
  br label %148

147:                                              ; preds = %139
  br label %148

148:                                              ; preds = %147, %146
  br label %152

149:                                              ; preds = %123
  %150 = load ptr, ptr %8, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %150)
  %151 = call i64 @xTaskResumeAll()
  br label %152

152:                                              ; preds = %149, %148
  br label %173

153:                                              ; preds = %120
  %154 = load ptr, ptr %8, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %154)
  %155 = call i64 @xTaskResumeAll()
  %156 = load ptr, ptr %8, align 8, !tbaa !5
  %157 = call i64 @prvIsQueueEmpty(ptr noundef %156)
  %158 = icmp ne i64 %157, 0
  br i1 %158, label %159, label %171

159:                                              ; preds = %153
  %160 = load i64, ptr %9, align 8, !tbaa !11
  %161 = icmp ne i64 %160, 0
  br i1 %161, label %162, label %170

162:                                              ; preds = %159
  call void @vPortEnterCritical()
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %163 = load ptr, ptr %8, align 8, !tbaa !5
  %164 = call i64 @prvGetDisinheritPriorityAfterTimeout(ptr noundef %163)
  store i64 %164, ptr %12, align 8, !tbaa !11
  %165 = load ptr, ptr %8, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.QueueDefinition, ptr %165, i32 0, i32 2
  %167 = getelementptr inbounds %struct.SemaphoreData, ptr %166, i32 0, i32 0
  %168 = load ptr, ptr %167, align 8, !tbaa !19
  %169 = load i64, ptr %12, align 8, !tbaa !11
  call void @vTaskPriorityDisinheritAfterTimeout(ptr noundef %168, i64 noundef %169)
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @vPortExitCritical()
  br label %170

170:                                              ; preds = %162, %159
  store i64 0, ptr %3, align 8
  store i32 1, ptr %11, align 4
  br label %174

171:                                              ; preds = %153
  br label %172

172:                                              ; preds = %171
  br label %173

173:                                              ; preds = %172, %152
  br label %41

174:                                              ; preds = %170, %100
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  %175 = load i64, ptr %3, align 8
  ret i64 %175
}

declare i64 @xTaskGetSchedulerState() #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) #2

declare void @vTaskSuspendAll() #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) #3

declare i64 @xTaskResumeAll() #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) #3

declare ptr @pvTaskIncrementMutexHeldCount() #2

declare i64 @xTaskPriorityInherit(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvGetDisinheritPriorityAfterTimeout(ptr noundef) #3

declare void @vTaskPriorityDisinheritAfterTimeout(ptr noundef, i64 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 128}
!14 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !15, i64 32, !15, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!14, !12, i64 112}
!18 = !{!14, !6, i64 0}
!19 = !{!7, !7, i64 0}
!20 = !{!14, !12, i64 32}
!21 = !{i64 2148269322}
!22 = !{i64 2148269391}
!23 = !{!14, !7, i64 136}
!24 = !{!14, !7, i64 137}
!25 = !{i64 2148271349}
!26 = !{i64 2148271418}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortEnterCritical() local_unnamed_addr #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #2

declare void @vPortExitCritical() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @xQueueSemaphoreTake(ptr noundef %0, i32 noundef %1) local_unnamed_addr #3 {
  %3 = alloca i32, align 4
  %4 = alloca %struct.xTIME_OUT, align 8
  store i32 %1, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #4
  %5 = icmp eq ptr %0, null
  br i1 %5, label %6, label %8

6:                                                ; preds = %2
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %2
  %9 = getelementptr inbounds i8, ptr %0, i64 128
  %10 = load i64, ptr %9, align 8, !tbaa !9
  %.not = icmp eq i64 %10, 0
  br i1 %.not, label %13, label %11

11:                                               ; preds = %8
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

13:                                               ; preds = %8
  %14 = tail call i64 @xTaskGetSchedulerState() #4
  %15 = icmp eq i64 %14, 0
  %16 = icmp ne i32 %1, 0
  %17 = and i1 %15, %16
  br i1 %17, label %57, label %.preheader

.preheader:                                       ; preds = %13
  tail call void @vPortEnterCritical() #4
  %18 = getelementptr inbounds i8, ptr %0, i64 112
  %19 = load volatile i64, ptr %18, align 8, !tbaa !15
  %.not3958 = icmp eq i64 %19, 0
  br i1 %.not3958, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %.preheader
  %20 = getelementptr inbounds i8, ptr %0, i64 136
  %21 = getelementptr inbounds i8, ptr %0, i64 137
  %22 = getelementptr inbounds i8, ptr %0, i64 16
  %23 = getelementptr inbounds i8, ptr %0, i64 72
  %24 = load i32, ptr %3, align 4, !tbaa !5
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %.thread67.sink.split, label %26

26:                                               ; preds = %.lr.ph
  call void @vTaskInternalSetTimeOutState(ptr noundef nonnull %4) #4
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %27 = load volatile i8, ptr %20, align 8, !tbaa !16
  %28 = icmp eq i8 %27, -1
  br i1 %28, label %29, label %30

29:                                               ; preds = %26
  store volatile i8 0, ptr %20, align 8, !tbaa !16
  br label %30

30:                                               ; preds = %29, %26
  %31 = load volatile i8, ptr %21, align 1, !tbaa !17
  %32 = icmp eq i8 %31, -1
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  store volatile i8 0, ptr %21, align 1, !tbaa !17
  br label %34

34:                                               ; preds = %33, %30
  call void @vPortExitCritical() #4
  %35 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %4, ptr noundef nonnull %3) #4
  %36 = icmp eq i64 %35, 0
  br i1 %36, label %40, label %37

37:                                               ; preds = %34
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %38 = call i64 @xTaskResumeAll() #4
  %39 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not43.peel = icmp eq i64 %39, 0
  br i1 %.not43.peel, label %55, label %.thread67

40:                                               ; preds = %34
  %41 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not45.peel = icmp eq i64 %41, 0
  br i1 %.not45.peel, label %53, label %42

42:                                               ; preds = %40
  %43 = load ptr, ptr %0, align 8, !tbaa !18
  %44 = icmp eq ptr %43, null
  br i1 %44, label %45, label %48

45:                                               ; preds = %42
  call void @vPortEnterCritical() #4
  %46 = load ptr, ptr %22, align 8, !tbaa !19
  %47 = call i64 @xTaskPriorityInherit(ptr noundef %46) #4
  call void @vPortExitCritical() #4
  br label %48

48:                                               ; preds = %45, %42
  %.135.peel = phi i64 [ %47, %45 ], [ 0, %42 ]
  %49 = load i32, ptr %3, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %23, i32 noundef %49) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %50 = call i64 @xTaskResumeAll() #4
  %51 = icmp eq i64 %50, 0
  br i1 %51, label %52, label %55

52:                                               ; preds = %48
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  br label %55

53:                                               ; preds = %40
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %54 = call i64 @xTaskResumeAll() #4
  br label %55

55:                                               ; preds = %53, %52, %48, %37
  %.236.peel = phi i64 [ %.135.peel, %52 ], [ %.135.peel, %48 ], [ 0, %53 ], [ 0, %37 ]
  call void @vPortEnterCritical() #4
  %56 = load volatile i64, ptr %18, align 8, !tbaa !15
  %.not39.peel = icmp eq i64 %56, 0
  br i1 %.not39.peel, label %.peel.next, label %._crit_edge

57:                                               ; preds = %13
  tail call void @vPortRaiseBASEPRI()
  br label %58

58:                                               ; preds = %58, %57
  br label %58

._crit_edge:                                      ; preds = %111, %55, %.preheader
  %.lcssa = phi i64 [ %19, %.preheader ], [ %56, %55 ], [ %112, %111 ]
  %59 = add i64 %.lcssa, -1
  store volatile i64 %59, ptr %18, align 8, !tbaa !15
  %60 = load ptr, ptr %0, align 8, !tbaa !18
  %61 = icmp eq ptr %60, null
  br i1 %61, label %62, label %65

62:                                               ; preds = %._crit_edge
  %63 = call ptr @pvTaskIncrementMutexHeldCount() #4
  %64 = getelementptr inbounds i8, ptr %0, i64 16
  store ptr %63, ptr %64, align 8, !tbaa !19
  br label %65

65:                                               ; preds = %._crit_edge, %62
  %66 = getelementptr inbounds i8, ptr %0, i64 32
  %67 = load volatile i64, ptr %66, align 8, !tbaa !22
  %.not41 = icmp eq i64 %67, 0
  br i1 %.not41, label %.thread67.sink.split, label %68

68:                                               ; preds = %65
  %69 = call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %66) #4
  %.not42 = icmp eq i64 %69, 0
  br i1 %.not42, label %.thread67.sink.split, label %70

70:                                               ; preds = %68
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !23
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !24
  br label %.thread67.sink.split

.peel.next:                                       ; preds = %55, %111
  %.03459 = phi i64 [ %.236, %111 ], [ %.236.peel, %55 ]
  %71 = load i32, ptr %3, align 4, !tbaa !5
  %72 = icmp eq i32 %71, 0
  br i1 %72, label %73, label %77

73:                                               ; preds = %.peel.next
  %74 = icmp eq i64 %.03459, 0
  br i1 %74, label %.thread67.sink.split, label %75

75:                                               ; preds = %73
  call void @vPortRaiseBASEPRI()
  br label %76

76:                                               ; preds = %76, %75
  br label %76

77:                                               ; preds = %.peel.next
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %78 = load volatile i8, ptr %20, align 8, !tbaa !16
  %79 = icmp eq i8 %78, -1
  br i1 %79, label %80, label %81

80:                                               ; preds = %77
  store volatile i8 0, ptr %20, align 8, !tbaa !16
  br label %81

81:                                               ; preds = %80, %77
  %82 = load volatile i8, ptr %21, align 1, !tbaa !17
  %83 = icmp eq i8 %82, -1
  br i1 %83, label %84, label %85

84:                                               ; preds = %81
  store volatile i8 0, ptr %21, align 1, !tbaa !17
  br label %85

85:                                               ; preds = %84, %81
  call void @vPortExitCritical() #4
  %86 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %4, ptr noundef nonnull %3) #4
  %87 = icmp eq i64 %86, 0
  br i1 %87, label %88, label %103

88:                                               ; preds = %85
  %89 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not45 = icmp eq i64 %89, 0
  br i1 %.not45, label %101, label %90

90:                                               ; preds = %88
  %91 = load ptr, ptr %0, align 8, !tbaa !18
  %92 = icmp eq ptr %91, null
  br i1 %92, label %93, label %96

93:                                               ; preds = %90
  call void @vPortEnterCritical() #4
  %94 = load ptr, ptr %22, align 8, !tbaa !19
  %95 = call i64 @xTaskPriorityInherit(ptr noundef %94) #4
  call void @vPortExitCritical() #4
  br label %96

96:                                               ; preds = %90, %93
  %.135 = phi i64 [ %95, %93 ], [ %.03459, %90 ]
  %97 = load i32, ptr %3, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %23, i32 noundef %97) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %98 = call i64 @xTaskResumeAll() #4
  %99 = icmp eq i64 %98, 0
  br i1 %99, label %100, label %111

100:                                              ; preds = %96
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  br label %111

101:                                              ; preds = %88
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %102 = call i64 @xTaskResumeAll() #4
  br label %111

103:                                              ; preds = %85
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %104 = call i64 @xTaskResumeAll() #4
  %105 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not43 = icmp eq i64 %105, 0
  br i1 %.not43, label %111, label %106

106:                                              ; preds = %103
  %107 = icmp eq i64 %.03459, 0
  br i1 %107, label %.thread67, label %108

108:                                              ; preds = %106
  call void @vPortEnterCritical() #4
  %109 = call i64 @prvGetDisinheritPriorityAfterTimeout(ptr noundef nonnull %0)
  %110 = load ptr, ptr %22, align 8, !tbaa !19
  call void @vTaskPriorityDisinheritAfterTimeout(ptr noundef %110, i64 noundef %109) #4
  br label %.thread67.sink.split

111:                                              ; preds = %103, %101, %96, %100
  %.236 = phi i64 [ %.135, %100 ], [ %.135, %96 ], [ %.03459, %101 ], [ %.03459, %103 ]
  call void @vPortEnterCritical() #4
  %112 = load volatile i64, ptr %18, align 8, !tbaa !15
  %.not39 = icmp eq i64 %112, 0
  br i1 %.not39, label %.peel.next, label %._crit_edge, !llvm.loop !25

.thread67.sink.split:                             ; preds = %73, %.lr.ph, %68, %70, %65, %108
  %.2.ph = phi i64 [ 0, %108 ], [ 1, %65 ], [ 1, %70 ], [ 1, %68 ], [ 0, %.lr.ph ], [ 0, %73 ]
  call void @vPortExitCritical() #4
  br label %.thread67

.thread67:                                        ; preds = %.thread67.sink.split, %37, %106
  %.2 = phi i64 [ 0, %106 ], [ 0, %37 ], [ %.2.ph, %.thread67.sink.split ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  ret i64 %.2
}

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) local_unnamed_addr #2

declare void @vTaskSuspendAll() local_unnamed_addr #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) local_unnamed_addr #3

declare i64 @xTaskResumeAll() local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) local_unnamed_addr #3

declare ptr @pvTaskIncrementMutexHeldCount() local_unnamed_addr #2

declare i64 @xTaskPriorityInherit(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvGetDisinheritPriorityAfterTimeout(ptr noundef) local_unnamed_addr #3

declare void @vTaskPriorityDisinheritAfterTimeout(ptr noundef, i64 noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !13, i64 128}
!10 = !{!"QueueDefinition", !11, i64 0, !11, i64 8, !7, i64 16, !12, i64 32, !12, i64 72, !13, i64 112, !13, i64 120, !13, i64 128, !7, i64 136, !7, i64 137}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"xLIST", !13, i64 0, !11, i64 8, !14, i64 16}
!13 = !{!"long", !7, i64 0}
!14 = !{!"xMINI_LIST_ITEM", !6, i64 0, !11, i64 8, !11, i64 16}
!15 = !{!10, !13, i64 112}
!16 = !{!10, !7, i64 136}
!17 = !{!10, !7, i64 137}
!18 = !{!10, !11, i64 0}
!19 = !{!7, !7, i64 0}
!20 = !{i64 2148271349}
!21 = !{i64 2148271418}
!22 = !{!10, !13, i64 32}
!23 = !{i64 2148269322}
!24 = !{i64 2148269391}
!25 = distinct !{!25, !26}
!26 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopFullUnrollPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass