; LLVM IR from Bousk/Net :: NetworkLib/src/UDP/AckHandler.ll (ZNK5Bousk7Network3UDP10AckHandler7isAckedEt)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Bousk::Network::UDP::AckHandler" = type <{ i64, i64, %"class.std::vector", i16, i8, [5 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned short, std::allocator<unsigned short>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5Bousk5Utils15IsSequenceNewerEtt(i16 noundef zeroext, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN5Bousk5Utils12SequenceDiffEtt(i16 noundef zeroext, i16 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5Bousk5Utils6HasBitEmh(i64 noundef, i8 noundef zeroext) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK5Bousk7Network3UDP10AckHandler7isAckedEt(ptr noundef nonnull align 8 dereferenceable(43) %0, i16 noundef zeroext %1) #2 align 2 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i16 %1, ptr %5, align 2, !tbaa !9
  %9 = load ptr, ptr %4, align 8
  %10 = load i16, ptr %5, align 2, !tbaa !9
  %11 = zext i16 %10 to i32
  %12 = getelementptr inbounds %"class.Bousk::Network::UDP::AckHandler", ptr %9, i32 0, i32 3
  %13 = load i16, ptr %12, align 8, !tbaa !11
  %14 = zext i16 %13 to i32
  %15 = icmp eq i32 %11, %14
  br i1 %15, label %16, label %17

16:                                               ; preds = %2
  store i1 true, ptr %3, align 1
  br label %42

17:                                               ; preds = %2
  %18 = load i16, ptr %5, align 2, !tbaa !9
  %19 = getelementptr inbounds %"class.Bousk::Network::UDP::AckHandler", ptr %9, i32 0, i32 3
  %20 = load i16, ptr %19, align 8, !tbaa !11
  %21 = call noundef zeroext i1 @_ZN5Bousk5Utils15IsSequenceNewerEtt(i16 noundef zeroext %18, i16 noundef zeroext %20)
  br i1 %21, label %22, label %23

22:                                               ; preds = %17
  store i1 false, ptr %3, align 1
  br label %42

23:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #3
  %24 = getelementptr inbounds %"class.Bousk::Network::UDP::AckHandler", ptr %9, i32 0, i32 3
  %25 = load i16, ptr %24, align 8, !tbaa !11
  %26 = load i16, ptr %5, align 2, !tbaa !9
  %27 = call noundef zeroext i16 @_ZN5Bousk5Utils12SequenceDiffEtt(i16 noundef zeroext %25, i16 noundef zeroext %26)
  store i16 %27, ptr %6, align 2, !tbaa !9
  %28 = load i16, ptr %6, align 2, !tbaa !9
  %29 = zext i16 %28 to i32
  %30 = icmp sgt i32 %29, 64
  br i1 %30, label %31, label %32

31:                                               ; preds = %23
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %41

32:                                               ; preds = %23
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  %33 = load i16, ptr %6, align 2, !tbaa !9
  %34 = zext i16 %33 to i32
  %35 = sub nsw i32 %34, 1
  %36 = trunc i32 %35 to i8
  store i8 %36, ptr %8, align 1, !tbaa !19
  %37 = getelementptr inbounds %"class.Bousk::Network::UDP::AckHandler", ptr %9, i32 0, i32 0
  %38 = load i64, ptr %37, align 8, !tbaa !20
  %39 = load i8, ptr %8, align 1, !tbaa !19
  %40 = call noundef zeroext i1 @_ZN5Bousk5Utils6HasBitEmh(i64 noundef %38, i8 noundef zeroext %39)
  store i1 %40, ptr %3, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  br label %41

41:                                               ; preds = %32, %31
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #3
  br label %42

42:                                               ; preds = %41, %22, %16
  %43 = load i1, ptr %3, align 1
  ret i1 %43
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !10, i64 40}
!12 = !{!"_ZTSN5Bousk7Network3UDP10AckHandlerE", !13, i64 0, !13, i64 8, !14, i64 16, !10, i64 40, !18, i64 42}
!13 = !{!"long", !7, i64 0}
!14 = !{!"_ZTSSt6vectorItSaItEE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseItSaItEE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseItSaItEE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseItSaItEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"bool", !7, i64 0}
!19 = !{!7, !7, i64 0}
!20 = !{!12, !13, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5Bousk5Utils15IsSequenceNewerEtt(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN5Bousk5Utils12SequenceDiffEtt(i16 noundef zeroext, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN5Bousk5Utils6HasBitEmh(i64 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZNK5Bousk7Network3UDP10AckHandler7isAckedEt(ptr nocapture noundef nonnull readonly align 8 dereferenceable(43) %0, i16 noundef zeroext %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 40
  %4 = load i16, ptr %3, align 8, !tbaa !5
  %5 = icmp eq i16 %4, %1
  br i1 %5, label %17, label %6

6:                                                ; preds = %2
  %7 = tail call noundef zeroext i1 @_ZN5Bousk5Utils15IsSequenceNewerEtt(i16 noundef zeroext %1, i16 noundef zeroext %4)
  br i1 %7, label %17, label %8

8:                                                ; preds = %6
  %9 = load i16, ptr %3, align 8, !tbaa !5
  %10 = tail call noundef zeroext i16 @_ZN5Bousk5Utils12SequenceDiffEtt(i16 noundef zeroext %9, i16 noundef zeroext %1)
  %11 = icmp ugt i16 %10, 64
  br i1 %11, label %17, label %12

12:                                               ; preds = %8
  %13 = trunc nuw i16 %10 to i8
  %14 = add nsw i8 %13, -1
  %15 = load i64, ptr %0, align 8, !tbaa !17
  %16 = tail call noundef zeroext i1 @_ZN5Bousk5Utils6HasBitEmh(i64 noundef %15, i8 noundef zeroext %14)
  br label %17

17:                                               ; preds = %12, %8, %6, %2
  %.1 = phi i1 [ true, %2 ], [ false, %6 ], [ %16, %12 ], [ false, %8 ]
  ret i1 %.1
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !15, i64 40}
!6 = !{!"_ZTSN5Bousk7Network3UDP10AckHandlerE", !7, i64 0, !7, i64 8, !10, i64 16, !15, i64 40, !16, i64 42}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorItSaItEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseItSaItEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseItSaItEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseItSaItEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"short", !8, i64 0}
!16 = !{!"bool", !8, i64 0}
!17 = !{!6, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass