; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueuePeek)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }
%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare void @vPortEnterCritical() #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

declare void @vPortExitCritical() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xTaskGetSchedulerState() #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) #2

declare void @vTaskSuspendAll() #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) #3

declare i64 @xTaskResumeAll() #2

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueuePeek(ptr noundef %0, ptr noundef %1, i32 noundef %2) #3 {
  %4 = alloca i64, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca %struct.xTIME_OUT, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  store i64 0, ptr %8, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %14, ptr %11, align 8, !tbaa !5
  %15 = load ptr, ptr %11, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %19

17:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %18

18:                                               ; preds = %18, %17
  br label %18

19:                                               ; preds = %3
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = icmp eq ptr %20, null
  br i1 %21, label %22, label %27

22:                                               ; preds = %19
  %23 = load ptr, ptr %11, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.QueueDefinition, ptr %23, i32 0, i32 7
  %25 = load i64, ptr %24, align 8, !tbaa !13
  %26 = icmp ne i64 %25, 0
  br label %27

27:                                               ; preds = %22, %19
  %28 = phi i1 [ false, %19 ], [ %26, %22 ]
  %29 = xor i1 %28, true
  %30 = zext i1 %29 to i32
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %34

32:                                               ; preds = %27
  call void @vPortRaiseBASEPRI()
  br label %33

33:                                               ; preds = %33, %32
  br label %33

34:                                               ; preds = %27
  %35 = call i64 @xTaskGetSchedulerState()
  %36 = icmp eq i64 %35, 0
  br i1 %36, label %37, label %40

37:                                               ; preds = %34
  %38 = load i32, ptr %7, align 4, !tbaa !9
  %39 = icmp ne i32 %38, 0
  br label %40

40:                                               ; preds = %37, %34
  %41 = phi i1 [ false, %34 ], [ %39, %37 ]
  %42 = xor i1 %41, true
  %43 = zext i1 %42 to i32
  %44 = icmp eq i32 %43, 0
  br i1 %44, label %45, label %47

45:                                               ; preds = %40
  call void @vPortRaiseBASEPRI()
  br label %46

46:                                               ; preds = %46, %45
  br label %46

47:                                               ; preds = %40
  br label %48

48:                                               ; preds = %145, %47
  call void @vPortEnterCritical()
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %49 = load ptr, ptr %11, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.QueueDefinition, ptr %49, i32 0, i32 5
  %51 = load volatile i64, ptr %50, align 8, !tbaa !17
  store i64 %51, ptr %12, align 8, !tbaa !11
  %52 = load i64, ptr %12, align 8, !tbaa !11
  %53 = icmp ugt i64 %52, 0
  br i1 %53, label %54, label %83

54:                                               ; preds = %48
  %55 = load ptr, ptr %11, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.QueueDefinition, ptr %55, i32 0, i32 2
  %57 = getelementptr inbounds %struct.QueuePointers, ptr %56, i32 0, i32 1
  %58 = load ptr, ptr %57, align 8, !tbaa !18
  store ptr %58, ptr %10, align 8, !tbaa !5
  %59 = load ptr, ptr %11, align 8, !tbaa !5
  %60 = load ptr, ptr %6, align 8, !tbaa !5
  call void @prvCopyDataFromQueue(ptr noundef %59, ptr noundef %60)
  %61 = load ptr, ptr %10, align 8, !tbaa !5
  %62 = load ptr, ptr %11, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.QueueDefinition, ptr %62, i32 0, i32 2
  %64 = getelementptr inbounds %struct.QueuePointers, ptr %63, i32 0, i32 1
  store ptr %61, ptr %64, align 8, !tbaa !18
  %65 = load ptr, ptr %11, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.QueueDefinition, ptr %65, i32 0, i32 4
  %67 = getelementptr inbounds %struct.xLIST, ptr %66, i32 0, i32 0
  %68 = load volatile i64, ptr %67, align 8, !tbaa !19
  %69 = icmp eq i64 %68, 0
  %70 = zext i1 %69 to i64
  %71 = select i1 %69, i64 1, i64 0
  %72 = icmp eq i64 %71, 0
  br i1 %72, label %73, label %81

73:                                               ; preds = %54
  %74 = load ptr, ptr %11, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.QueueDefinition, ptr %74, i32 0, i32 4
  %76 = call i64 @xTaskRemoveFromEventList(ptr noundef %75)
  %77 = icmp ne i64 %76, 0
  br i1 %77, label %78, label %79

78:                                               ; preds = %73
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  br label %80

79:                                               ; preds = %73
  br label %80

80:                                               ; preds = %79, %78
  br label %82

81:                                               ; preds = %54
  br label %82

82:                                               ; preds = %81, %80
  call void @vPortExitCritical()
  store i64 1, ptr %4, align 8
  store i32 1, ptr %13, align 4
  br label %95

83:                                               ; preds = %48
  %84 = load i32, ptr %7, align 4, !tbaa !9
  %85 = icmp eq i32 %84, 0
  br i1 %85, label %86, label %87

86:                                               ; preds = %83
  call void @vPortExitCritical()
  store i64 0, ptr %4, align 8
  store i32 1, ptr %13, align 4
  br label %95

87:                                               ; preds = %83
  %88 = load i64, ptr %8, align 8, !tbaa !11
  %89 = icmp eq i64 %88, 0
  br i1 %89, label %90, label %91

90:                                               ; preds = %87
  call void @vTaskInternalSetTimeOutState(ptr noundef %9)
  store i64 1, ptr %8, align 8, !tbaa !11
  br label %92

91:                                               ; preds = %87
  br label %92

92:                                               ; preds = %91, %90
  br label %93

93:                                               ; preds = %92
  br label %94

94:                                               ; preds = %93
  store i32 0, ptr %13, align 4
  br label %95

95:                                               ; preds = %94, %86, %82
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  %96 = load i32, ptr %13, align 4
  switch i32 %96, label %146 [
    i32 0, label %97
  ]

97:                                               ; preds = %95
  call void @vPortExitCritical()
  call void @vTaskSuspendAll()
  call void @vPortEnterCritical()
  %98 = load ptr, ptr %11, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.QueueDefinition, ptr %98, i32 0, i32 8
  %100 = load volatile i8, ptr %99, align 8, !tbaa !22
  %101 = sext i8 %100 to i32
  %102 = icmp eq i32 %101, -1
  br i1 %102, label %103, label %106

103:                                              ; preds = %97
  %104 = load ptr, ptr %11, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.QueueDefinition, ptr %104, i32 0, i32 8
  store volatile i8 0, ptr %105, align 8, !tbaa !22
  br label %106

106:                                              ; preds = %103, %97
  %107 = load ptr, ptr %11, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.QueueDefinition, ptr %107, i32 0, i32 9
  %109 = load volatile i8, ptr %108, align 1, !tbaa !23
  %110 = sext i8 %109 to i32
  %111 = icmp eq i32 %110, -1
  br i1 %111, label %112, label %115

112:                                              ; preds = %106
  %113 = load ptr, ptr %11, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.QueueDefinition, ptr %113, i32 0, i32 9
  store volatile i8 0, ptr %114, align 1, !tbaa !23
  br label %115

115:                                              ; preds = %112, %106
  call void @vPortExitCritical()
  %116 = call i64 @xTaskCheckForTimeOut(ptr noundef %9, ptr noundef %7)
  %117 = icmp eq i64 %116, 0
  br i1 %117, label %118, label %136

118:                                              ; preds = %115
  %119 = load ptr, ptr %11, align 8, !tbaa !5
  %120 = call i64 @prvIsQueueEmpty(ptr noundef %119)
  %121 = icmp ne i64 %120, 0
  br i1 %121, label %122, label %132

122:                                              ; preds = %118
  %123 = load ptr, ptr %11, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.QueueDefinition, ptr %123, i32 0, i32 4
  %125 = load i32, ptr %7, align 4, !tbaa !9
  call void @vTaskPlaceOnEventList(ptr noundef %124, i32 noundef %125)
  %126 = load ptr, ptr %11, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %126)
  %127 = call i64 @xTaskResumeAll()
  %128 = icmp eq i64 %127, 0
  br i1 %128, label %129, label %130

129:                                              ; preds = %122
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !24
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !25
  br label %131

130:                                              ; preds = %122
  br label %131

131:                                              ; preds = %130, %129
  br label %135

132:                                              ; preds = %118
  %133 = load ptr, ptr %11, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %133)
  %134 = call i64 @xTaskResumeAll()
  br label %135

135:                                              ; preds = %132, %131
  br label %145

136:                                              ; preds = %115
  %137 = load ptr, ptr %11, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %137)
  %138 = call i64 @xTaskResumeAll()
  %139 = load ptr, ptr %11, align 8, !tbaa !5
  %140 = call i64 @prvIsQueueEmpty(ptr noundef %139)
  %141 = icmp ne i64 %140, 0
  br i1 %141, label %142, label %143

142:                                              ; preds = %136
  store i64 0, ptr %4, align 8
  store i32 1, ptr %13, align 4
  br label %146

143:                                              ; preds = %136
  br label %144

144:                                              ; preds = %143
  br label %145

145:                                              ; preds = %144, %135
  br label %48

146:                                              ; preds = %142, %95
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %147 = load i64, ptr %4, align 8
  ret i64 %147
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 128}
!14 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !15, i64 32, !15, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!14, !12, i64 112}
!18 = !{!7, !7, i64 0}
!19 = !{!14, !12, i64 72}
!20 = !{i64 2148272904}
!21 = !{i64 2148272973}
!22 = !{!14, !7, i64 136}
!23 = !{!14, !7, i64 137}
!24 = !{i64 2148274653}
!25 = !{i64 2148274722}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortEnterCritical() local_unnamed_addr #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #2

declare void @vPortExitCritical() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #2

declare void @vTaskInternalSetTimeOutState(ptr noundef) local_unnamed_addr #2

declare void @vTaskSuspendAll() local_unnamed_addr #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) local_unnamed_addr #2

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) local_unnamed_addr #3

declare i64 @xTaskResumeAll() local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueEmpty(ptr noundef) local_unnamed_addr #3

; Function Attrs: nounwind uwtable
define dso_local noundef i64 @xQueuePeek(ptr noundef %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #3 {
  %4 = alloca i32, align 4
  %5 = alloca %struct.xTIME_OUT, align 8
  store i32 %2, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #4
  %6 = icmp eq ptr %0, null
  br i1 %6, label %7, label %9

7:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %3
  %10 = icmp eq ptr %1, null
  br i1 %10, label %11, label %.critedge

11:                                               ; preds = %9
  %12 = getelementptr inbounds i8, ptr %0, i64 128
  %13 = load i64, ptr %12, align 8, !tbaa !9
  %.not39 = icmp eq i64 %13, 0
  br i1 %.not39, label %.critedge, label %14

14:                                               ; preds = %11
  tail call void @vPortRaiseBASEPRI()
  br label %15

15:                                               ; preds = %15, %14
  br label %15

.critedge:                                        ; preds = %9, %11
  %16 = tail call i64 @xTaskGetSchedulerState() #4
  %17 = icmp eq i64 %16, 0
  %18 = icmp ne i32 %2, 0
  %19 = and i1 %17, %18
  br i1 %19, label %52, label %.preheader

.preheader:                                       ; preds = %.critedge
  tail call void @vPortEnterCritical() #4
  %20 = getelementptr inbounds i8, ptr %0, i64 112
  %21 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not40 = icmp eq i64 %21, 0
  br i1 %.not40, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %.preheader
  %22 = getelementptr inbounds i8, ptr %0, i64 136
  %23 = getelementptr inbounds i8, ptr %0, i64 137
  %24 = getelementptr inbounds i8, ptr %0, i64 72
  %25 = load i32, ptr %4, align 4, !tbaa !5
  %26 = icmp eq i32 %25, 0
  br i1 %26, label %.loopexit.sink.split, label %27

27:                                               ; preds = %.lr.ph
  call void @vTaskInternalSetTimeOutState(ptr noundef nonnull %5) #4
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %28 = load volatile i8, ptr %22, align 8, !tbaa !16
  %29 = icmp eq i8 %28, -1
  br i1 %29, label %30, label %31

30:                                               ; preds = %27
  store volatile i8 0, ptr %22, align 8, !tbaa !16
  br label %31

31:                                               ; preds = %30, %27
  %32 = load volatile i8, ptr %23, align 1, !tbaa !17
  %33 = icmp eq i8 %32, -1
  br i1 %33, label %34, label %35

34:                                               ; preds = %31
  store volatile i8 0, ptr %23, align 1, !tbaa !17
  br label %35

35:                                               ; preds = %34, %31
  call void @vPortExitCritical() #4
  %36 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %5, ptr noundef nonnull %4) #4
  %37 = icmp eq i64 %36, 0
  br i1 %37, label %41, label %38

38:                                               ; preds = %35
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %39 = call i64 @xTaskResumeAll() #4
  %40 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not32.peel = icmp eq i64 %40, 0
  br i1 %.not32.peel, label %50, label %.loopexit

41:                                               ; preds = %35
  %42 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not33.peel = icmp eq i64 %42, 0
  br i1 %.not33.peel, label %48, label %43

43:                                               ; preds = %41
  %44 = load i32, ptr %4, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %24, i32 noundef %44) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %45 = call i64 @xTaskResumeAll() #4
  %46 = icmp eq i64 %45, 0
  br i1 %46, label %47, label %50

47:                                               ; preds = %43
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %50

48:                                               ; preds = %41
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %49 = call i64 @xTaskResumeAll() #4
  br label %50

50:                                               ; preds = %48, %47, %43, %38
  call void @vPortEnterCritical() #4
  %51 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not.peel = icmp eq i64 %51, 0
  br i1 %.not.peel, label %.peel.next, label %._crit_edge

52:                                               ; preds = %.critedge
  tail call void @vPortRaiseBASEPRI()
  br label %53

53:                                               ; preds = %53, %52
  br label %53

._crit_edge:                                      ; preds = %86, %50, %.preheader
  %54 = getelementptr inbounds i8, ptr %0, i64 24
  %55 = load ptr, ptr %54, align 8, !tbaa !20
  call void @prvCopyDataFromQueue(ptr noundef nonnull %0, ptr noundef %1)
  store ptr %55, ptr %54, align 8, !tbaa !20
  %56 = getelementptr inbounds i8, ptr %0, i64 72
  %57 = load volatile i64, ptr %56, align 8, !tbaa !21
  %.not30 = icmp eq i64 %57, 0
  br i1 %.not30, label %.loopexit.sink.split, label %58

58:                                               ; preds = %._crit_edge
  %59 = call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %56) #4
  %.not31 = icmp eq i64 %59, 0
  br i1 %.not31, label %.loopexit.sink.split, label %60

60:                                               ; preds = %58
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !22
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !23
  br label %.loopexit.sink.split

.peel.next:                                       ; preds = %50, %86
  %61 = load i32, ptr %4, align 4, !tbaa !5
  %62 = icmp eq i32 %61, 0
  br i1 %62, label %.loopexit.sink.split, label %63

63:                                               ; preds = %.peel.next
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %64 = load volatile i8, ptr %22, align 8, !tbaa !16
  %65 = icmp eq i8 %64, -1
  br i1 %65, label %66, label %67

66:                                               ; preds = %63
  store volatile i8 0, ptr %22, align 8, !tbaa !16
  br label %67

67:                                               ; preds = %66, %63
  %68 = load volatile i8, ptr %23, align 1, !tbaa !17
  %69 = icmp eq i8 %68, -1
  br i1 %69, label %70, label %71

70:                                               ; preds = %67
  store volatile i8 0, ptr %23, align 1, !tbaa !17
  br label %71

71:                                               ; preds = %70, %67
  call void @vPortExitCritical() #4
  %72 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %5, ptr noundef nonnull %4) #4
  %73 = icmp eq i64 %72, 0
  br i1 %73, label %74, label %83

74:                                               ; preds = %71
  %75 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not33 = icmp eq i64 %75, 0
  br i1 %.not33, label %81, label %76

76:                                               ; preds = %74
  %77 = load i32, ptr %4, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %24, i32 noundef %77) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %78 = call i64 @xTaskResumeAll() #4
  %79 = icmp eq i64 %78, 0
  br i1 %79, label %80, label %86

80:                                               ; preds = %76
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %86

81:                                               ; preds = %74
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %82 = call i64 @xTaskResumeAll() #4
  br label %86

83:                                               ; preds = %71
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %84 = call i64 @xTaskResumeAll() #4
  %85 = call i64 @prvIsQueueEmpty(ptr noundef nonnull %0)
  %.not32 = icmp eq i64 %85, 0
  br i1 %.not32, label %86, label %.loopexit

86:                                               ; preds = %83, %81, %76, %80
  call void @vPortEnterCritical() #4
  %87 = load volatile i64, ptr %20, align 8, !tbaa !15
  %.not = icmp eq i64 %87, 0
  br i1 %.not, label %.peel.next, label %._crit_edge, !llvm.loop !24

.loopexit.sink.split:                             ; preds = %.peel.next, %.lr.ph, %58, %60, %._crit_edge
  %.2.ph = phi i64 [ 1, %._crit_edge ], [ 1, %60 ], [ 1, %58 ], [ 0, %.lr.ph ], [ 0, %.peel.next ]
  call void @vPortExitCritical() #4
  br label %.loopexit

.loopexit:                                        ; preds = %83, %.loopexit.sink.split, %38
  %.2 = phi i64 [ 0, %38 ], [ %.2.ph, %.loopexit.sink.split ], [ 0, %83 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #4
  ret i64 %.2
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !13, i64 128}
!10 = !{!"QueueDefinition", !11, i64 0, !11, i64 8, !7, i64 16, !12, i64 32, !12, i64 72, !13, i64 112, !13, i64 120, !13, i64 128, !7, i64 136, !7, i64 137}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"xLIST", !13, i64 0, !11, i64 8, !14, i64 16}
!13 = !{!"long", !7, i64 0}
!14 = !{!"xMINI_LIST_ITEM", !6, i64 0, !11, i64 8, !11, i64 16}
!15 = !{!10, !13, i64 112}
!16 = !{!10, !7, i64 136}
!17 = !{!10, !7, i64 137}
!18 = !{i64 2148274653}
!19 = !{i64 2148274722}
!20 = !{!7, !7, i64 0}
!21 = !{!10, !13, i64 72}
!22 = !{i64 2148272904}
!23 = !{i64 2148272973}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopFullUnrollPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass