; LLVM IR from gzc/CLRS :: C06-Heapsort/p_queue.ll (ZN7p_queue6insertEi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.p_queue = type { [10000 x i32], i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN7p_queue6insertEi(ptr noundef nonnull align 4 dereferenceable(40004) %0, i32 noundef %1) #1 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %6 = load ptr, ptr %3, align 8
  %7 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 1
  %8 = load i32, ptr %7, align 4, !tbaa !11
  %9 = add nsw i32 %8, 1
  store i32 %9, ptr %7, align 4, !tbaa !11
  %10 = load i32, ptr %4, align 4, !tbaa !9
  %11 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 0
  %12 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 1
  %13 = load i32, ptr %12, align 4, !tbaa !11
  %14 = sub nsw i32 %13, 1
  %15 = sext i32 %14 to i64
  %16 = getelementptr inbounds [10000 x i32], ptr %11, i64 0, i64 %15
  store i32 %10, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %17 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 1
  %18 = load i32, ptr %17, align 4, !tbaa !11
  %19 = sub nsw i32 %18, 1
  store i32 %19, ptr %5, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %38, %2
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = icmp sgt i32 %21, 0
  br i1 %22, label %23, label %36

23:                                               ; preds = %20
  %24 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 0
  %25 = load i32, ptr %5, align 4, !tbaa !9
  %26 = call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %6, i32 noundef %25)
  %27 = sext i32 %26 to i64
  %28 = getelementptr inbounds [10000 x i32], ptr %24, i64 0, i64 %27
  %29 = load i32, ptr %28, align 4, !tbaa !9
  %30 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 0
  %31 = load i32, ptr %5, align 4, !tbaa !9
  %32 = sext i32 %31 to i64
  %33 = getelementptr inbounds [10000 x i32], ptr %30, i64 0, i64 %32
  %34 = load i32, ptr %33, align 4, !tbaa !9
  %35 = icmp slt i32 %29, %34
  br label %36

36:                                               ; preds = %23, %20
  %37 = phi i1 [ false, %20 ], [ %35, %23 ]
  br i1 %37, label %38, label %50

38:                                               ; preds = %36
  %39 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 0
  %40 = load i32, ptr %5, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds [10000 x i32], ptr %39, i64 0, i64 %41
  %43 = getelementptr inbounds %class.p_queue, ptr %6, i32 0, i32 0
  %44 = load i32, ptr %5, align 4, !tbaa !9
  %45 = call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %6, i32 noundef %44)
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds [10000 x i32], ptr %43, i64 0, i64 %46
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %42, ptr noundef nonnull align 4 dereferenceable(4) %47) #4
  %48 = load i32, ptr %5, align 4, !tbaa !9
  %49 = call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %6, i32 noundef %48)
  store i32 %49, ptr %5, align 4, !tbaa !9
  br label %20, !llvm.loop !13

50:                                               ; preds = %36
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004), i32 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 40000}
!12 = !{!"_ZTS7p_queue", !7, i64 0, !10, i64 40000}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN7p_queue6insertEi(ptr noundef nonnull align 4 dereferenceable(40004) %0, i32 noundef %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 40000
  %4 = load i32, ptr %3, align 4, !tbaa !5
  %5 = add nsw i32 %4, 1
  store i32 %5, ptr %3, align 4, !tbaa !5
  %6 = sext i32 %4 to i64
  %7 = getelementptr inbounds [10000 x i32], ptr %0, i64 0, i64 %6
  store i32 %1, ptr %7, align 4, !tbaa !10
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = icmp sgt i32 %8, 1
  br i1 %9, label %.lr.ph.preheader, label %.critedge

.lr.ph.preheader:                                 ; preds = %2
  %10 = add nsw i32 %8, -1
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %19
  %.07 = phi i32 [ %23, %19 ], [ %10, %.lr.ph.preheader ]
  %11 = tail call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %0, i32 noundef %.07)
  %12 = sext i32 %11 to i64
  %13 = getelementptr inbounds [10000 x i32], ptr %0, i64 0, i64 %12
  %14 = load i32, ptr %13, align 4, !tbaa !10
  %15 = zext nneg i32 %.07 to i64
  %16 = getelementptr inbounds [10000 x i32], ptr %0, i64 0, i64 %15
  %17 = load i32, ptr %16, align 4, !tbaa !10
  %18 = icmp slt i32 %14, %17
  br i1 %18, label %19, label %.critedge

19:                                               ; preds = %.lr.ph
  %20 = tail call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %0, i32 noundef %.07)
  %21 = sext i32 %20 to i64
  %22 = getelementptr inbounds [10000 x i32], ptr %0, i64 0, i64 %21
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %16, ptr noundef nonnull align 4 dereferenceable(4) %22) #2
  %23 = tail call noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004) %0, i32 noundef %.07)
  %24 = icmp sgt i32 %23, 0
  br i1 %24, label %.lr.ph, label %.critedge, !llvm.loop !11

.critedge:                                        ; preds = %.lr.ph, %19, %2
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN7p_queue6parentEi(ptr noundef nonnull align 4 dereferenceable(40004), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 40000}
!6 = !{!"_ZTS7p_queue", !7, i64 0, !9, i64 40000}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!"int", !7, i64 0}
!10 = !{!9, !9, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass