; LLVM IR from Dev-XYS/Algorithms :: Splay(Single-Rotation).ll (Z6insertRP4nodeii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i32, i32, [2 x ptr] }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef %1, i32 noundef %2) #1 personality ptr @__gxx_personality_v0 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = load ptr, ptr %9, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %12, label %22

12:                                               ; preds = %3
  %13 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 24) #4
  %14 = load i32, ptr %5, align 4, !tbaa !9
  %15 = load i32, ptr %6, align 4, !tbaa !9
  invoke void @_ZN4nodeC2Eii(ptr noundef nonnull align 8 dereferenceable(24) %13, i32 noundef %14, i32 noundef %15)
          to label %16 unwind label %18

16:                                               ; preds = %12
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %13, ptr %17, align 8, !tbaa !5
  br label %53

18:                                               ; preds = %12
  %19 = landingpad { ptr, i32 }
          cleanup
  %20 = extractvalue { ptr, i32 } %19, 0
  store ptr %20, ptr %7, align 8
  %21 = extractvalue { ptr, i32 } %19, 1
  store i32 %21, ptr %8, align 4
  call void @_ZdlPvm(ptr noundef %13, i64 noundef 24) #5
  br label %54

22:                                               ; preds = %3
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = load ptr, ptr %24, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.node, ptr %25, i32 0, i32 0
  %27 = load i32, ptr %26, align 8, !tbaa !11
  %28 = icmp slt i32 %23, %27
  br i1 %28, label %29, label %37

29:                                               ; preds = %22
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = load ptr, ptr %30, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.node, ptr %31, i32 0, i32 2
  %33 = getelementptr inbounds [2 x ptr], ptr %32, i64 0, i64 0
  %34 = load i32, ptr %5, align 4, !tbaa !9
  %35 = load i32, ptr %6, align 4, !tbaa !9
  call void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %33, i32 noundef %34, i32 noundef %35)
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8) %36, i32 noundef 0)
  br label %53

37:                                               ; preds = %22
  %38 = load i32, ptr %5, align 4, !tbaa !9
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = load ptr, ptr %39, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct.node, ptr %40, i32 0, i32 0
  %42 = load i32, ptr %41, align 8, !tbaa !11
  %43 = icmp sgt i32 %38, %42
  br i1 %43, label %44, label %52

44:                                               ; preds = %37
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  %46 = load ptr, ptr %45, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.node, ptr %46, i32 0, i32 2
  %48 = getelementptr inbounds [2 x ptr], ptr %47, i64 0, i64 1
  %49 = load i32, ptr %5, align 4, !tbaa !9
  %50 = load i32, ptr %6, align 4, !tbaa !9
  call void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %48, i32 noundef %49, i32 noundef %50)
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8) %51, i32 noundef 1)
  br label %52

52:                                               ; preds = %44, %37
  br label %53

53:                                               ; preds = %52, %29, %16
  ret void

54:                                               ; preds = %18
  %55 = load ptr, ptr %7, align 8
  %56 = load i32, ptr %8, align 4
  %57 = insertvalue { ptr, i32 } poison, ptr %55, 0
  %58 = insertvalue { ptr, i32 } %57, i32 %56, 1
  resume { ptr, i32 } %58
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4nodeC2Eii(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nobuiltin nounwind
declare void @_ZdlPvm(ptr noundef, i64 noundef) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTS4node", !10, i64 0, !10, i64 4, !7, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #1 personality ptr @__gxx_personality_v0 {
  %4 = load ptr, ptr %0, align 8, !tbaa !5
  %5 = icmp eq ptr %4, null
  br i1 %5, label %6, label %8

6:                                                ; preds = %3
  %7 = tail call noalias noundef nonnull dereferenceable(24) ptr @_Znwm(i64 noundef 24) #3
  tail call void @_ZN4nodeC2Eii(ptr noundef nonnull align 8 dereferenceable(24) %7, i32 noundef %1, i32 noundef %2)
  store ptr %7, ptr %0, align 8, !tbaa !5
  br label %common.ret17

8:                                                ; preds = %3
  %9 = load i32, ptr %4, align 8, !tbaa !9
  %10 = icmp sgt i32 %9, %1
  br i1 %10, label %11, label %13

common.ret17:                                     ; preds = %13, %6, %15, %11
  ret void

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %4, i64 8
  tail call void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %12, i32 noundef %1, i32 noundef %2)
  tail call void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef 0)
  br label %common.ret17

13:                                               ; preds = %8
  %14 = icmp slt i32 %9, %1
  br i1 %14, label %15, label %common.ret17

15:                                               ; preds = %13
  %16 = getelementptr inbounds i8, ptr %4, i64 16
  tail call void @_Z6insertRP4nodeii(ptr noundef nonnull align 8 dereferenceable(8) %16, i32 noundef %1, i32 noundef %2)
  tail call void @_Z6rotateRP4nodei(ptr noundef nonnull align 8 dereferenceable(8) %0, i32 noundef 1)
  br label %common.ret17
}

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znwm(i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4nodeC2Eii(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef) unnamed_addr #0 align 2

declare i32 @__gxx_personality_v0(...)

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { builtin allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS4node", !11, i64 0, !11, i64 4, !7, i64 8}
!11 = !{!"int", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass