; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueuePeekFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortValidateInterruptPriority() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueuePeekFromISR(ptr noundef %0, ptr noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %9 = load ptr, ptr %3, align 8, !tbaa !5
  store ptr %9, ptr %8, align 8, !tbaa !5
  %10 = load ptr, ptr %8, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %12, label %14

12:                                               ; preds = %2
  call void @vPortRaiseBASEPRI()
  br label %13

13:                                               ; preds = %13, %12
  br label %13

14:                                               ; preds = %2
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %22

17:                                               ; preds = %14
  %18 = load ptr, ptr %8, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.QueueDefinition, ptr %18, i32 0, i32 7
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = icmp ne i64 %20, 0
  br label %22

22:                                               ; preds = %17, %14
  %23 = phi i1 [ false, %14 ], [ %21, %17 ]
  %24 = xor i1 %23, true
  %25 = zext i1 %24 to i32
  %26 = icmp eq i32 %25, 0
  br i1 %26, label %27, label %29

27:                                               ; preds = %22
  call void @vPortRaiseBASEPRI()
  br label %28

28:                                               ; preds = %28, %27
  br label %28

29:                                               ; preds = %22
  %30 = load ptr, ptr %8, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.QueueDefinition, ptr %30, i32 0, i32 7
  %32 = load i64, ptr %31, align 8, !tbaa !9
  %33 = icmp ne i64 %32, 0
  %34 = zext i1 %33 to i32
  %35 = icmp eq i32 %34, 0
  br i1 %35, label %36, label %38

36:                                               ; preds = %29
  call void @vPortRaiseBASEPRI()
  br label %37

37:                                               ; preds = %37, %36
  br label %37

38:                                               ; preds = %29
  call void @vPortValidateInterruptPriority()
  %39 = call i32 @ulPortRaiseBASEPRI()
  %40 = zext i32 %39 to i64
  store i64 %40, ptr %6, align 8, !tbaa !15
  %41 = load ptr, ptr %8, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.QueueDefinition, ptr %41, i32 0, i32 5
  %43 = load volatile i64, ptr %42, align 8, !tbaa !16
  %44 = icmp ugt i64 %43, 0
  br i1 %44, label %45, label %56

45:                                               ; preds = %38
  %46 = load ptr, ptr %8, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.QueueDefinition, ptr %46, i32 0, i32 2
  %48 = getelementptr inbounds %struct.QueuePointers, ptr %47, i32 0, i32 1
  %49 = load ptr, ptr %48, align 8, !tbaa !17
  store ptr %49, ptr %7, align 8, !tbaa !5
  %50 = load ptr, ptr %8, align 8, !tbaa !5
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  call void @prvCopyDataFromQueue(ptr noundef %50, ptr noundef %51)
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = load ptr, ptr %8, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.QueueDefinition, ptr %53, i32 0, i32 2
  %55 = getelementptr inbounds %struct.QueuePointers, ptr %54, i32 0, i32 1
  store ptr %52, ptr %55, align 8, !tbaa !17
  store i64 1, ptr %5, align 8, !tbaa !15
  br label %57

56:                                               ; preds = %38
  store i64 0, ptr %5, align 8, !tbaa !15
  br label %57

57:                                               ; preds = %56, %45
  %58 = load i64, ptr %6, align 8, !tbaa !15
  %59 = trunc i64 %58 to i32
  call void @vPortSetBASEPRI(i32 noundef %59)
  %60 = load i64, ptr %5, align 8, !tbaa !15
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret i64 %60
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 128}
!10 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !11, i64 32, !11, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137}
!11 = !{!"xLIST", !12, i64 0, !6, i64 8, !13, i64 16}
!12 = !{!"long", !7, i64 0}
!13 = !{!"xMINI_LIST_ITEM", !14, i64 0, !6, i64 8, !6, i64 16}
!14 = !{!"int", !7, i64 0}
!15 = !{!12, !12, i64 0}
!16 = !{!10, !12, i64 112}
!17 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare void @vPortValidateInterruptPriority() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden void @prvCopyDataFromQueue(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xQueuePeekFromISR(ptr noundef %0, ptr noundef %1) local_unnamed_addr #2 {
  %3 = icmp eq ptr %0, null
  br i1 %3, label %4, label %6

4:                                                ; preds = %2
  tail call void @vPortRaiseBASEPRI()
  br label %5

5:                                                ; preds = %5, %4
  br label %5

6:                                                ; preds = %2
  %7 = icmp eq ptr %1, null
  %8 = getelementptr inbounds i8, ptr %0, i64 128
  %9 = load i64, ptr %8, align 8, !tbaa !5
  %.not14 = icmp eq i64 %9, 0
  br i1 %7, label %10, label %.critedge

10:                                               ; preds = %6
  br i1 %.not14, label %.critedge.thread, label %11

11:                                               ; preds = %10
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

.critedge:                                        ; preds = %6
  br i1 %.not14, label %.critedge.thread, label %14

.critedge.thread:                                 ; preds = %10, %.critedge
  tail call void @vPortRaiseBASEPRI()
  br label %13

13:                                               ; preds = %13, %.critedge.thread
  br label %13

14:                                               ; preds = %.critedge
  tail call void @vPortValidateInterruptPriority() #3
  %15 = tail call i32 @ulPortRaiseBASEPRI()
  %16 = getelementptr inbounds i8, ptr %0, i64 112
  %17 = load volatile i64, ptr %16, align 8, !tbaa !14
  %.not13 = icmp eq i64 %17, 0
  br i1 %.not13, label %21, label %18

18:                                               ; preds = %14
  %19 = getelementptr inbounds i8, ptr %0, i64 24
  %20 = load ptr, ptr %19, align 8, !tbaa !15
  tail call void @prvCopyDataFromQueue(ptr noundef nonnull %0, ptr noundef nonnull %1)
  store ptr %20, ptr %19, align 8, !tbaa !15
  br label %21

21:                                               ; preds = %14, %18
  %.0 = phi i64 [ 1, %18 ], [ 0, %14 ]
  tail call void @vPortSetBASEPRI(i32 noundef %15)
  ret i64 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 128}
!6 = !{!"QueueDefinition", !7, i64 0, !7, i64 8, !8, i64 16, !10, i64 32, !10, i64 72, !11, i64 112, !11, i64 120, !11, i64 128, !8, i64 136, !8, i64 137}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !7, i64 8, !12, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"xMINI_LIST_ITEM", !13, i64 0, !7, i64 8, !7, i64 16}
!13 = !{!"int", !8, i64 0}
!14 = !{!6, !11, i64 112}
!15 = !{!8, !8, i64 0}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass