; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xEventGroupSync)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.EventGroupDef_t = type { i32, %struct.xLIST }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @xEventGroupSync(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %14, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  store i64 0, ptr %13, align 8, !tbaa !11
  %15 = load i32, ptr %7, align 4, !tbaa !9
  %16 = zext i32 %15 to i64
  %17 = and i64 %16, 4278190080
  %18 = icmp eq i64 %17, 0
  %19 = zext i1 %18 to i32
  %20 = icmp eq i32 %19, 0
  br i1 %20, label %21, label %23

21:                                               ; preds = %4
  call void @vPortRaiseBASEPRI()
  br label %22

22:                                               ; preds = %22, %21
  br label %22

23:                                               ; preds = %4
  %24 = load i32, ptr %7, align 4, !tbaa !9
  %25 = icmp ne i32 %24, 0
  %26 = zext i1 %25 to i32
  %27 = icmp eq i32 %26, 0
  br i1 %27, label %28, label %30

28:                                               ; preds = %23
  call void @vPortRaiseBASEPRI()
  br label %29

29:                                               ; preds = %29, %28
  br label %29

30:                                               ; preds = %23
  %31 = call i64 @xTaskGetSchedulerState()
  %32 = icmp eq i64 %31, 0
  br i1 %32, label %33, label %36

33:                                               ; preds = %30
  %34 = load i32, ptr %8, align 4, !tbaa !9
  %35 = icmp ne i32 %34, 0
  br label %36

36:                                               ; preds = %33, %30
  %37 = phi i1 [ false, %30 ], [ %35, %33 ]
  %38 = xor i1 %37, true
  %39 = zext i1 %38 to i32
  %40 = icmp eq i32 %39, 0
  br i1 %40, label %41, label %43

41:                                               ; preds = %36
  call void @vPortRaiseBASEPRI()
  br label %42

42:                                               ; preds = %42, %41
  br label %42

43:                                               ; preds = %36
  call void @vTaskSuspendAll()
  %44 = load ptr, ptr %11, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.EventGroupDef_t, ptr %44, i32 0, i32 0
  %46 = load i32, ptr %45, align 8, !tbaa !13
  store i32 %46, ptr %9, align 4, !tbaa !9
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = call i32 @xEventGroupSetBits(ptr noundef %47, i32 noundef %48)
  %50 = load i32, ptr %9, align 4, !tbaa !9
  %51 = load i32, ptr %6, align 4, !tbaa !9
  %52 = or i32 %50, %51
  %53 = load i32, ptr %7, align 4, !tbaa !9
  %54 = and i32 %52, %53
  %55 = load i32, ptr %7, align 4, !tbaa !9
  %56 = icmp eq i32 %54, %55
  br i1 %56, label %57, label %67

57:                                               ; preds = %43
  %58 = load i32, ptr %9, align 4, !tbaa !9
  %59 = load i32, ptr %6, align 4, !tbaa !9
  %60 = or i32 %58, %59
  store i32 %60, ptr %10, align 4, !tbaa !9
  %61 = load i32, ptr %7, align 4, !tbaa !9
  %62 = xor i32 %61, -1
  %63 = load ptr, ptr %11, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.EventGroupDef_t, ptr %63, i32 0, i32 0
  %65 = load i32, ptr %64, align 8, !tbaa !13
  %66 = and i32 %65, %62
  store i32 %66, ptr %64, align 8, !tbaa !13
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %84

67:                                               ; preds = %43
  %68 = load i32, ptr %8, align 4, !tbaa !9
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %70, label %79

70:                                               ; preds = %67
  %71 = load ptr, ptr %11, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.EventGroupDef_t, ptr %71, i32 0, i32 1
  %73 = load i32, ptr %7, align 4, !tbaa !9
  %74 = zext i32 %73 to i64
  %75 = or i64 %74, 16777216
  %76 = or i64 %75, 67108864
  %77 = trunc i64 %76 to i32
  %78 = load i32, ptr %8, align 4, !tbaa !9
  call void @vTaskPlaceOnUnorderedEventList(ptr noundef %72, i32 noundef %77, i32 noundef %78)
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %83

79:                                               ; preds = %67
  %80 = load ptr, ptr %11, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.EventGroupDef_t, ptr %80, i32 0, i32 0
  %82 = load i32, ptr %81, align 8, !tbaa !13
  store i32 %82, ptr %10, align 4, !tbaa !9
  store i64 1, ptr %13, align 8, !tbaa !11
  br label %83

83:                                               ; preds = %79, %70
  br label %84

84:                                               ; preds = %83, %57
  %85 = call i64 @xTaskResumeAll()
  store i64 %85, ptr %12, align 8, !tbaa !11
  %86 = load i32, ptr %8, align 4, !tbaa !9
  %87 = icmp ne i32 %86, 0
  br i1 %87, label %88, label %123

88:                                               ; preds = %84
  %89 = load i64, ptr %12, align 8, !tbaa !11
  %90 = icmp eq i64 %89, 0
  br i1 %90, label %91, label %92

91:                                               ; preds = %88
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !17
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  br label %93

92:                                               ; preds = %88
  br label %93

93:                                               ; preds = %92, %91
  %94 = call i32 @uxTaskResetEventItemValue()
  store i32 %94, ptr %10, align 4, !tbaa !9
  %95 = load i32, ptr %10, align 4, !tbaa !9
  %96 = zext i32 %95 to i64
  %97 = and i64 %96, 33554432
  %98 = icmp eq i64 %97, 0
  br i1 %98, label %99, label %117

99:                                               ; preds = %93
  call void @vPortEnterCritical()
  %100 = load ptr, ptr %11, align 8, !tbaa !5
  %101 = getelementptr inbounds %struct.EventGroupDef_t, ptr %100, i32 0, i32 0
  %102 = load i32, ptr %101, align 8, !tbaa !13
  store i32 %102, ptr %10, align 4, !tbaa !9
  %103 = load i32, ptr %10, align 4, !tbaa !9
  %104 = load i32, ptr %7, align 4, !tbaa !9
  %105 = and i32 %103, %104
  %106 = load i32, ptr %7, align 4, !tbaa !9
  %107 = icmp eq i32 %105, %106
  br i1 %107, label %108, label %115

108:                                              ; preds = %99
  %109 = load i32, ptr %7, align 4, !tbaa !9
  %110 = xor i32 %109, -1
  %111 = load ptr, ptr %11, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.EventGroupDef_t, ptr %111, i32 0, i32 0
  %113 = load i32, ptr %112, align 8, !tbaa !13
  %114 = and i32 %113, %110
  store i32 %114, ptr %112, align 8, !tbaa !13
  br label %116

115:                                              ; preds = %99
  br label %116

116:                                              ; preds = %115, %108
  call void @vPortExitCritical()
  store i64 1, ptr %13, align 8, !tbaa !11
  br label %118

117:                                              ; preds = %93
  br label %118

118:                                              ; preds = %117, %116
  %119 = load i32, ptr %10, align 4, !tbaa !9
  %120 = zext i32 %119 to i64
  %121 = and i64 %120, -4278190081
  %122 = trunc i64 %121 to i32
  store i32 %122, ptr %10, align 4, !tbaa !9
  br label %123

123:                                              ; preds = %118, %84
  %124 = load i64, ptr %13, align 8, !tbaa !11
  %125 = load i64, ptr %13, align 8, !tbaa !11
  %126 = load i32, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  ret i32 %126
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

declare i64 @xTaskGetSchedulerState() #3

declare void @vTaskSuspendAll() #3

; Function Attrs: nounwind uwtable
declare dso_local i32 @xEventGroupSetBits(ptr noundef, i32 noundef) #1

declare void @vTaskPlaceOnUnorderedEventList(ptr noundef, i32 noundef, i32 noundef) #3

declare i64 @xTaskResumeAll() #3

declare i32 @uxTaskResetEventItemValue() #3

declare void @vPortEnterCritical() #3

declare void @vPortExitCritical() #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !10, i64 0}
!14 = !{!"EventGroupDef_t", !10, i64 0, !15, i64 8}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{i64 2148145886}
!18 = !{i64 2148145955}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @xEventGroupSync(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = icmp ugt i32 %2, 16777215
  br i1 %5, label %6, label %8

6:                                                ; preds = %4
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %4
  %.not = icmp eq i32 %2, 0
  br i1 %.not, label %9, label %11

9:                                                ; preds = %8
  tail call void @vPortRaiseBASEPRI()
  br label %10

10:                                               ; preds = %10, %9
  br label %10

11:                                               ; preds = %8
  %12 = tail call i64 @xTaskGetSchedulerState() #3
  %13 = icmp eq i64 %12, 0
  %14 = icmp ne i32 %3, 0
  %15 = and i1 %14, %13
  br i1 %15, label %16, label %18

16:                                               ; preds = %11
  tail call void @vPortRaiseBASEPRI()
  br label %17

17:                                               ; preds = %17, %16
  br label %17

18:                                               ; preds = %11
  tail call void @vTaskSuspendAll() #3
  %19 = load i32, ptr %0, align 8, !tbaa !5
  %20 = tail call i32 @xEventGroupSetBits(ptr noundef nonnull %0, i32 noundef %1)
  %21 = or i32 %19, %1
  %22 = and i32 %21, %2
  %23 = icmp eq i32 %22, %2
  br i1 %23, label %24, label %28

24:                                               ; preds = %18
  %25 = xor i32 %2, -1
  %26 = load i32, ptr %0, align 8, !tbaa !5
  %27 = and i32 %26, %25
  store i32 %27, ptr %0, align 8, !tbaa !5
  br label %.thread

28:                                               ; preds = %18
  br i1 %14, label %32, label %29

29:                                               ; preds = %28
  %30 = load i32, ptr %0, align 8, !tbaa !5
  br label %.thread

.thread:                                          ; preds = %24, %29
  %.033.ph = phi i32 [ %30, %29 ], [ %21, %24 ]
  %31 = tail call i64 @xTaskResumeAll() #3
  br label %52

32:                                               ; preds = %28
  %33 = getelementptr inbounds i8, ptr %0, i64 8
  %34 = or disjoint i32 %2, 83886080
  tail call void @vTaskPlaceOnUnorderedEventList(ptr noundef nonnull %33, i32 noundef %34, i32 noundef %3) #3
  %35 = tail call i64 @xTaskResumeAll() #3
  %36 = icmp eq i64 %35, 0
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !14
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !15
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !16
  br label %38

38:                                               ; preds = %32, %37
  %39 = tail call i32 @uxTaskResetEventItemValue() #3
  %40 = and i32 %39, 33554432
  %41 = icmp eq i32 %40, 0
  br i1 %41, label %42, label %50

42:                                               ; preds = %38
  tail call void @vPortEnterCritical() #3
  %43 = load i32, ptr %0, align 8, !tbaa !5
  %44 = and i32 %43, %2
  %45 = icmp eq i32 %44, %2
  br i1 %45, label %46, label %49

46:                                               ; preds = %42
  %47 = xor i32 %2, -1
  %48 = and i32 %43, %47
  store i32 %48, ptr %0, align 8, !tbaa !5
  br label %49

49:                                               ; preds = %42, %46
  tail call void @vPortExitCritical() #3
  br label %50

50:                                               ; preds = %38, %49
  %.134 = phi i32 [ %43, %49 ], [ %39, %38 ]
  %51 = and i32 %.134, 16777215
  br label %52

52:                                               ; preds = %.thread, %50
  %.235 = phi i32 [ %51, %50 ], [ %.033.ph, %.thread ]
  ret i32 %.235
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #2

declare void @vTaskSuspendAll() local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @xEventGroupSetBits(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @vTaskPlaceOnUnorderedEventList(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

declare i64 @xTaskResumeAll() local_unnamed_addr #2

declare i32 @uxTaskResetEventItemValue() local_unnamed_addr #2

declare void @vPortEnterCritical() local_unnamed_addr #2

declare void @vPortExitCritical() local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"EventGroupDef_t", !7, i64 0, !10, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !12, i64 8, !13, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"xMINI_LIST_ITEM", !7, i64 0, !12, i64 8, !12, i64 16}
!14 = !{!7, !7, i64 0}
!15 = !{i64 2148145886}
!16 = !{i64 2148145955}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass