; LLVM IR from gazebosim/gz-physics :: tpe/lib/src/aabb_tree/AABB.ll (ZN4aabb4Tree12minimumImageERSt6vectorIdSaIdEES4_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::_Bit_reference" = type { ptr, i64 }
%"class.aabb::Tree" = type <{ i32, [4 x i8], %"class.std::vector.0", i32, i32, i32, i32, i8, [7 x i8], double, %"class.std::vector.5", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::unordered_map", i8, [7 x i8] }>
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<aabb::Node, std::allocator<aabb::Node>>::_Vector_impl" }
%"struct.std::_Vector_base<aabb::Node, std::allocator<aabb::Node>>::_Vector_impl" = type { %"struct.std::_Vector_base<aabb::Node, std::allocator<aabb::Node>>::_Vector_impl_data" }
%"struct.std::_Vector_base<aabb::Node, std::allocator<aabb::Node>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Bvector_base" }
%"struct.std::_Bvector_base" = type { %"struct.std::_Bvector_base<std::allocator<bool>>::_Bvector_impl" }
%"struct.std::_Bvector_base<std::allocator<bool>>::_Bvector_impl" = type { %"struct.std::_Bvector_base<std::allocator<bool>>::_Bvector_impl_data" }
%"struct.std::_Bvector_base<std::allocator<bool>>::_Bvector_impl_data" = type { %"struct.std::_Bit_iterator", %"struct.std::_Bit_iterator", ptr }
%"struct.std::_Bit_iterator" = type { %"struct.std::_Bit_iterator_base.base", [4 x i8] }
%"struct.std::_Bit_iterator_base.base" = type <{ ptr, i32 }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::unordered_map" = type { %"class.std::_Hashtable" }
%"class.std::_Hashtable" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"struct.std::__detail::_Hash_node_base" = type { ptr }
%"struct.std::__detail::_Prime_rehash_policy" = type { float, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN4aabb4Tree12minimumImageERSt6vectorIdSaIdEES4_(ptr noundef nonnull align 8 dereferenceable(233) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %"struct.std::_Bit_reference", align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #4
  store i8 0, ptr %7, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %12

12:                                               ; preds = %108, %3
  %13 = load i32, ptr %8, align 4, !tbaa !11
  %14 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 6
  %15 = load i32, ptr %14, align 4, !tbaa !13
  %16 = icmp ult i32 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %111

18:                                               ; preds = %12
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %10) #4
  %19 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 10
  %20 = load i32, ptr %8, align 4, !tbaa !11
  %21 = zext i32 %20 to i64
  %22 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %19, i64 noundef %21)
  %23 = getelementptr inbounds { ptr, i64 }, ptr %10, i32 0, i32 0
  %24 = extractvalue { ptr, i64 } %22, 0
  store ptr %24, ptr %23, align 8
  %25 = getelementptr inbounds { ptr, i64 }, ptr %10, i32 0, i32 1
  %26 = extractvalue { ptr, i64 } %22, 1
  store i64 %26, ptr %25, align 8
  %27 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %10) #4
  %28 = zext i1 %27 to i32
  call void @llvm.lifetime.end.p0(i64 16, ptr %10) #4
  store i32 %28, ptr %9, align 4, !tbaa !11
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = load i32, ptr %8, align 4, !tbaa !11
  %31 = zext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #4
  %33 = load double, ptr %32, align 8, !tbaa !36
  %34 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 12
  %35 = load i32, ptr %8, align 4, !tbaa !11
  %36 = zext i32 %35 to i64
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %36) #4
  %38 = load double, ptr %37, align 8, !tbaa !36
  %39 = fcmp olt double %33, %38
  br i1 %39, label %40, label %66

40:                                               ; preds = %18
  %41 = load i32, ptr %9, align 4, !tbaa !11
  %42 = sitofp i32 %41 to double
  %43 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 11
  %44 = load i32, ptr %8, align 4, !tbaa !11
  %45 = zext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %45) #4
  %47 = load double, ptr %46, align 8, !tbaa !36
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = load i32, ptr %8, align 4, !tbaa !11
  %50 = zext i32 %49 to i64
  %51 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %50) #4
  %52 = load double, ptr %51, align 8, !tbaa !36
  %53 = call double @llvm.fmuladd.f64(double %42, double %47, double %52)
  store double %53, ptr %51, align 8, !tbaa !36
  %54 = load i32, ptr %9, align 4, !tbaa !11
  %55 = sitofp i32 %54 to double
  %56 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 11
  %57 = load i32, ptr %8, align 4, !tbaa !11
  %58 = zext i32 %57 to i64
  %59 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %56, i64 noundef %58) #4
  %60 = load double, ptr %59, align 8, !tbaa !36
  %61 = fmul double %55, %60
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = load i32, ptr %8, align 4, !tbaa !11
  %64 = zext i32 %63 to i64
  %65 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %64) #4
  store double %61, ptr %65, align 8, !tbaa !36
  store i8 1, ptr %7, align 1, !tbaa !9
  br label %107

66:                                               ; preds = %18
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = load i32, ptr %8, align 4, !tbaa !11
  %69 = zext i32 %68 to i64
  %70 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %67, i64 noundef %69) #4
  %71 = load double, ptr %70, align 8, !tbaa !36
  %72 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 13
  %73 = load i32, ptr %8, align 4, !tbaa !11
  %74 = zext i32 %73 to i64
  %75 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %72, i64 noundef %74) #4
  %76 = load double, ptr %75, align 8, !tbaa !36
  %77 = fcmp oge double %71, %76
  br i1 %77, label %78, label %106

78:                                               ; preds = %66
  %79 = load i32, ptr %9, align 4, !tbaa !11
  %80 = sitofp i32 %79 to double
  %81 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 11
  %82 = load i32, ptr %8, align 4, !tbaa !11
  %83 = zext i32 %82 to i64
  %84 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %83) #4
  %85 = load double, ptr %84, align 8, !tbaa !36
  %86 = load ptr, ptr %5, align 8, !tbaa !5
  %87 = load i32, ptr %8, align 4, !tbaa !11
  %88 = zext i32 %87 to i64
  %89 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %86, i64 noundef %88) #4
  %90 = load double, ptr %89, align 8, !tbaa !36
  %91 = fneg double %80
  %92 = call double @llvm.fmuladd.f64(double %91, double %85, double %90)
  store double %92, ptr %89, align 8, !tbaa !36
  %93 = load i32, ptr %9, align 4, !tbaa !11
  %94 = sub nsw i32 0, %93
  %95 = sitofp i32 %94 to double
  %96 = getelementptr inbounds %"class.aabb::Tree", ptr %11, i32 0, i32 11
  %97 = load i32, ptr %8, align 4, !tbaa !11
  %98 = zext i32 %97 to i64
  %99 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %96, i64 noundef %98) #4
  %100 = load double, ptr %99, align 8, !tbaa !36
  %101 = fmul double %95, %100
  %102 = load ptr, ptr %6, align 8, !tbaa !5
  %103 = load i32, ptr %8, align 4, !tbaa !11
  %104 = zext i32 %103 to i64
  %105 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %102, i64 noundef %104) #4
  store double %101, ptr %105, align 8, !tbaa !36
  store i8 1, ptr %7, align 1, !tbaa !9
  br label %106

106:                                              ; preds = %78, %66
  br label %107

107:                                              ; preds = %106, %40
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %108

108:                                              ; preds = %107
  %109 = load i32, ptr %8, align 4, !tbaa !11
  %110 = add i32 %109, 1
  store i32 %110, ptr %8, align 4, !tbaa !11
  br label %12, !llvm.loop !37

111:                                              ; preds = %17
  %112 = load i8, ptr %7, align 1, !tbaa !9, !range !39, !noundef !40
  %113 = trunc i8 %112 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #4
  ret i1 %113
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 44}
!14 = !{!"_ZTSN4aabb4TreeE", !12, i64 0, !15, i64 8, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !10, i64 48, !19, i64 56, !20, i64 64, !26, i64 104, !26, i64 128, !26, i64 152, !30, i64 176, !10, i64 232}
!15 = !{!"_ZTSSt6vectorIN4aabb4NodeESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN4aabb4NodeESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN4aabb4NodeESaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN4aabb4NodeESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"double", !7, i64 0}
!20 = !{!"_ZTSSt6vectorIbSaIbEE", !21, i64 0}
!21 = !{!"_ZTSSt13_Bvector_baseISaIbEE", !22, i64 0}
!22 = !{!"_ZTSNSt13_Bvector_baseISaIbEE13_Bvector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt13_Bvector_baseISaIbEE18_Bvector_impl_dataE", !24, i64 0, !24, i64 16, !6, i64 32}
!24 = !{!"_ZTSSt13_Bit_iterator", !25, i64 0}
!25 = !{!"_ZTSSt18_Bit_iterator_base", !6, i64 0, !12, i64 8}
!26 = !{!"_ZTSSt6vectorIdSaIdEE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTSSt13unordered_mapIjjSt4hashIjESt8equal_toIjESaISt4pairIKjjEEE", !31, i64 0}
!31 = !{!"_ZTSSt10_HashtableIjSt4pairIKjjESaIS2_ENSt8__detail10_Select1stESt8equal_toIjESt4hashIjENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb0ELb1EEEE", !6, i64 0, !32, i64 8, !33, i64 16, !32, i64 24, !34, i64 32, !6, i64 48}
!32 = !{!"long", !7, i64 0}
!33 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !6, i64 0}
!34 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !35, i64 0, !32, i64 8}
!35 = !{!"float", !7, i64 0}
!36 = !{!19, !19, i64 0}
!37 = distinct !{!37, !38}
!38 = !{!"llvm.loop.mustprogress"}
!39 = !{i8 0, i8 2}
!40 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::_Bit_reference" = type { ptr, i64 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN4aabb4Tree12minimumImageERSt6vectorIdSaIdEES4_(ptr noundef nonnull align 8 dereferenceable(233) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #2 align 2 {
  %4 = alloca %"struct.std::_Bit_reference", align 8
  %5 = getelementptr inbounds i8, ptr %0, i64 44
  %6 = load i32, ptr %5, align 4, !tbaa !5
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %3
  %7 = getelementptr inbounds i8, ptr %0, i64 64
  %8 = getelementptr inbounds i8, ptr %4, i64 8
  %9 = getelementptr inbounds i8, ptr %0, i64 128
  %10 = getelementptr inbounds i8, ptr %0, i64 152
  %11 = getelementptr inbounds i8, ptr %0, i64 104
  br label %12

._crit_edge:                                      ; preds = %48, %3
  %.0.lcssa = phi i1 [ false, %3 ], [ %.1, %48 ]
  ret i1 %.0.lcssa

12:                                               ; preds = %.lr.ph, %48
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %48 ]
  %.028 = phi i1 [ false, %.lr.ph ], [ %.1, %48 ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #4
  %13 = call { ptr, i64 } @_ZNSt6vectorIbSaIbEEixEm(ptr noundef nonnull align 8 dereferenceable(40) %7, i64 noundef %indvars.iv)
  %14 = extractvalue { ptr, i64 } %13, 0
  store ptr %14, ptr %4, align 8
  %15 = extractvalue { ptr, i64 } %13, 1
  store i64 %15, ptr %8, align 8
  %16 = call noundef zeroext i1 @_ZNKSt14_Bit_referencecvbEv(ptr noundef nonnull align 8 dereferenceable(16) %4) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #4
  %17 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #4
  %18 = load double, ptr %17, align 8, !tbaa !33
  %19 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %indvars.iv) #4
  %20 = load double, ptr %19, align 8, !tbaa !33
  %21 = fcmp olt double %18, %20
  br i1 %21, label %22, label %29

22:                                               ; preds = %12
  %23 = uitofp i1 %16 to double
  %24 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv) #4
  %25 = load double, ptr %24, align 8, !tbaa !33
  %26 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #4
  %27 = load double, ptr %26, align 8, !tbaa !33
  %28 = call double @llvm.fmuladd.f64(double %23, double %25, double %27)
  store double %28, ptr %26, align 8, !tbaa !33
  br label %.sink.split

29:                                               ; preds = %12
  %30 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #4
  %31 = load double, ptr %30, align 8, !tbaa !33
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %indvars.iv) #4
  %33 = load double, ptr %32, align 8, !tbaa !33
  %34 = fcmp ult double %31, %33
  br i1 %34, label %48, label %35

35:                                               ; preds = %29
  %36 = uitofp i1 %16 to double
  %37 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv) #4
  %38 = load double, ptr %37, align 8, !tbaa !33
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #4
  %40 = load double, ptr %39, align 8, !tbaa !33
  %41 = fneg double %36
  %42 = call double @llvm.fmuladd.f64(double %41, double %38, double %40)
  store double %42, ptr %39, align 8, !tbaa !33
  %43 = sitofp i1 %16 to double
  br label %.sink.split

.sink.split:                                      ; preds = %22, %35
  %.sink31 = phi double [ %43, %35 ], [ %23, %22 ]
  %44 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %indvars.iv) #4
  %45 = load double, ptr %44, align 8, !tbaa !33
  %46 = fmul double %45, %.sink31
  %47 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %indvars.iv) #4
  store double %46, ptr %47, align 8, !tbaa !33
  br label %48

48:                                               ; preds = %.sink.split, %29
  %.1 = phi i1 [ %.028, %29 ], [ true, %.sink.split ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %49 = load i32, ptr %5, align 4, !tbaa !5
  %50 = zext i32 %49 to i64
  %51 = icmp ult i64 %indvars.iv.next, %50
  br i1 %51, label %12, label %._crit_edge, !llvm.loop !34
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 44}
!6 = !{!"_ZTSN4aabb4TreeE", !7, i64 0, !10, i64 8, !7, i64 32, !7, i64 36, !7, i64 40, !7, i64 44, !15, i64 48, !16, i64 56, !17, i64 64, !23, i64 104, !23, i64 128, !23, i64 152, !27, i64 176, !15, i64 232}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIN4aabb4NodeESaIS1_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIN4aabb4NodeESaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIN4aabb4NodeESaIS1_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIN4aabb4NodeESaIS1_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"bool", !8, i64 0}
!16 = !{!"double", !8, i64 0}
!17 = !{!"_ZTSSt6vectorIbSaIbEE", !18, i64 0}
!18 = !{!"_ZTSSt13_Bvector_baseISaIbEE", !19, i64 0}
!19 = !{!"_ZTSNSt13_Bvector_baseISaIbEE13_Bvector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt13_Bvector_baseISaIbEE18_Bvector_impl_dataE", !21, i64 0, !21, i64 16, !14, i64 32}
!21 = !{!"_ZTSSt13_Bit_iterator", !22, i64 0}
!22 = !{!"_ZTSSt18_Bit_iterator_base", !14, i64 0, !7, i64 8}
!23 = !{!"_ZTSSt6vectorIdSaIdEE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!27 = !{!"_ZTSSt13unordered_mapIjjSt4hashIjESt8equal_toIjESaISt4pairIKjjEEE", !28, i64 0}
!28 = !{!"_ZTSSt10_HashtableIjSt4pairIKjjESaIS2_ENSt8__detail10_Select1stESt8equal_toIjESt4hashIjENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb0ELb1EEEE", !14, i64 0, !29, i64 8, !30, i64 16, !29, i64 24, !31, i64 32, !14, i64 48}
!29 = !{!"long", !8, i64 0}
!30 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !14, i64 0}
!31 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !32, i64 0, !29, i64 8}
!32 = !{!"float", !8, i64 0}
!33 = !{!16, !16, i64 0}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass