; LLVM IR from alenic/realGA :: src/realga.ll (ZN6RealGA18popInitRandUniformEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.RealGA = type { ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.0", %"class.std::vector.0", %class.RealGAOptions, ptr, %"class.std::vector", float, i32, ptr, ptr, ptr, i32, float }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealGAOptions = type { i64, i64, %"class.std::vector", %"class.std::vector", i32, i32, float, i8, i32, i32, float, i32, i32, i32, float, float, float, float }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealChromosome = type <{ %"class.std::vector", float, [4 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZN6RealGA11evalFitnessERK14RealChromosome(ptr noundef nonnull align 8 dereferenceable(296), ptr noundef nonnull align 8 dereferenceable(28)) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6RealGA18popInitRandUniformEv(ptr noundef nonnull align 8 dereferenceable(296) %0) #2 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  store i32 0, ptr %3, align 4, !tbaa !9
  br label %5

5:                                                ; preds = %30, %1
  %6 = load i32, ptr %3, align 4, !tbaa !9
  %7 = sext i32 %6 to i64
  %8 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 5
  %9 = getelementptr inbounds %class.RealGAOptions, ptr %8, i32 0, i32 0
  %10 = load i64, ptr %9, align 8, !tbaa !11
  %11 = icmp ult i64 %7, %10
  br i1 %11, label %13, label %12

12:                                               ; preds = %5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  br label %33

13:                                               ; preds = %5
  %14 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 3
  %15 = load i32, ptr %3, align 4, !tbaa !9
  %16 = sext i32 %15 to i64
  %17 = call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %16) #4
  %18 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 1
  %19 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 2
  call void @_ZN14RealChromosome11randUniformERSt6vectorIfSaIfEES3_(ptr noundef nonnull align 8 dereferenceable(28) %17, ptr noundef nonnull align 8 dereferenceable(24) %18, ptr noundef nonnull align 8 dereferenceable(24) %19)
  %20 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 3
  %21 = load i32, ptr %3, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %22) #4
  %24 = call noundef float @_ZN6RealGA11evalFitnessERK14RealChromosome(ptr noundef nonnull align 8 dereferenceable(296) %4, ptr noundef nonnull align 8 dereferenceable(28) %23)
  %25 = getelementptr inbounds %class.RealGA, ptr %4, i32 0, i32 3
  %26 = load i32, ptr %3, align 4, !tbaa !9
  %27 = sext i32 %26 to i64
  %28 = call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %27) #4
  %29 = getelementptr inbounds %class.RealChromosome, ptr %28, i32 0, i32 1
  store float %24, ptr %29, align 8, !tbaa !29
  br label %30

30:                                               ; preds = %13
  %31 = load i32, ptr %3, align 4, !tbaa !9
  %32 = add nsw i32 %31, 1
  store i32 %32, ptr %3, align 4, !tbaa !9
  br label %5, !llvm.loop !31

33:                                               ; preds = %12
  ret void
}

declare void @_ZN14RealChromosome11randUniformERSt6vectorIfSaIfEES3_(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !22, i64 104}
!12 = !{!"_ZTS6RealGA", !13, i64 8, !13, i64 32, !17, i64 56, !17, i64 80, !21, i64 104, !6, i64 224, !13, i64 232, !24, i64 256, !10, i64 260, !6, i64 264, !6, i64 272, !6, i64 280, !10, i64 288, !24, i64 292}
!13 = !{!"_ZTSSt6vectorIfSaIfEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTS13RealGAOptions", !22, i64 0, !22, i64 8, !13, i64 16, !13, i64 40, !10, i64 64, !23, i64 68, !24, i64 72, !25, i64 76, !26, i64 80, !10, i64 84, !24, i64 88, !27, i64 92, !10, i64 96, !28, i64 100, !24, i64 104, !24, i64 108, !24, i64 112, !24, i64 116}
!22 = !{!"long", !7, i64 0}
!23 = !{!"_ZTS11VerboseType", !7, i64 0}
!24 = !{!"float", !7, i64 0}
!25 = !{!"bool", !7, i64 0}
!26 = !{!"_ZTS13SelectionType", !7, i64 0}
!27 = !{!"_ZTS13CrossoverType", !7, i64 0}
!28 = !{!"_ZTS12MutationType", !7, i64 0}
!29 = !{!30, !24, i64 24}
!30 = !{!"_ZTS14RealChromosome", !13, i64 0, !24, i64 24}
!31 = distinct !{!31, !32}
!32 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZN6RealGA11evalFitnessERK14RealChromosome(ptr noundef nonnull align 8 dereferenceable(296), ptr noundef nonnull align 8 dereferenceable(28)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6RealGA18popInitRandUniformEv(ptr noundef nonnull align 8 dereferenceable(296) %0) local_unnamed_addr #1 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 104
  %3 = load i64, ptr %2, align 8, !tbaa !5
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %1
  %4 = getelementptr inbounds i8, ptr %0, i64 56
  %5 = getelementptr inbounds i8, ptr %0, i64 8
  %6 = getelementptr inbounds i8, ptr %0, i64 32
  br label %7

._crit_edge:                                      ; preds = %7, %1
  ret void

7:                                                ; preds = %.lr.ph, %7
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %7 ]
  %8 = tail call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv) #3
  tail call void @_ZN14RealChromosome11randUniformERSt6vectorIfSaIfEES3_(ptr noundef nonnull align 8 dereferenceable(28) %8, ptr noundef nonnull align 8 dereferenceable(24) %5, ptr noundef nonnull align 8 dereferenceable(24) %6)
  %9 = tail call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv) #3
  %10 = tail call noundef float @_ZN6RealGA11evalFitnessERK14RealChromosome(ptr noundef nonnull align 8 dereferenceable(296) %0, ptr noundef nonnull align 8 dereferenceable(28) %9)
  %11 = tail call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv) #3
  %12 = getelementptr inbounds i8, ptr %11, i64 24
  store float %10, ptr %12, align 8, !tbaa !27
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %13 = load i64, ptr %2, align 8, !tbaa !5
  %14 = icmp ugt i64 %13, %indvars.iv.next
  br i1 %14, label %7, label %._crit_edge, !llvm.loop !29
}

declare void @_ZN14RealChromosome11randUniformERSt6vectorIfSaIfEES3_(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !19, i64 104}
!6 = !{!"_ZTS6RealGA", !7, i64 8, !7, i64 32, !14, i64 56, !14, i64 80, !18, i64 104, !11, i64 224, !7, i64 232, !22, i64 256, !20, i64 260, !11, i64 264, !11, i64 272, !11, i64 280, !20, i64 288, !22, i64 292}
!7 = !{!"_ZTSSt6vectorIfSaIfEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!18 = !{!"_ZTS13RealGAOptions", !19, i64 0, !19, i64 8, !7, i64 16, !7, i64 40, !20, i64 64, !21, i64 68, !22, i64 72, !23, i64 76, !24, i64 80, !20, i64 84, !22, i64 88, !25, i64 92, !20, i64 96, !26, i64 100, !22, i64 104, !22, i64 108, !22, i64 112, !22, i64 116}
!19 = !{!"long", !12, i64 0}
!20 = !{!"int", !12, i64 0}
!21 = !{!"_ZTS11VerboseType", !12, i64 0}
!22 = !{!"float", !12, i64 0}
!23 = !{!"bool", !12, i64 0}
!24 = !{!"_ZTS13SelectionType", !12, i64 0}
!25 = !{!"_ZTS13CrossoverType", !12, i64 0}
!26 = !{!"_ZTS12MutationType", !12, i64 0}
!27 = !{!28, !22, i64 24}
!28 = !{!"_ZTS14RealChromosome", !7, i64 0, !22, i64 24}
!29 = distinct !{!29, !30}
!30 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass