; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueueGiveFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.SemaphoreData = type { ptr, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortValidateInterruptPriority() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueGiveFromISR(ptr noundef %0, ptr noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  store ptr %10, ptr %7, align 8, !tbaa !5
  %11 = load ptr, ptr %7, align 8, !tbaa !5
  %12 = icmp eq ptr %11, null
  br i1 %12, label %13, label %15

13:                                               ; preds = %2
  call void @vPortRaiseBASEPRI()
  br label %14

14:                                               ; preds = %14, %13
  br label %14

15:                                               ; preds = %2
  %16 = load ptr, ptr %7, align 8, !tbaa !5
  %17 = getelementptr inbounds %struct.QueueDefinition, ptr %16, i32 0, i32 7
  %18 = load i64, ptr %17, align 8, !tbaa !9
  %19 = icmp eq i64 %18, 0
  %20 = zext i1 %19 to i32
  %21 = icmp eq i32 %20, 0
  br i1 %21, label %22, label %24

22:                                               ; preds = %15
  call void @vPortRaiseBASEPRI()
  br label %23

23:                                               ; preds = %23, %22
  br label %23

24:                                               ; preds = %15
  %25 = load ptr, ptr %7, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.QueueDefinition, ptr %25, i32 0, i32 0
  %27 = load ptr, ptr %26, align 8, !tbaa !15
  %28 = icmp eq ptr %27, null
  br i1 %28, label %29, label %35

29:                                               ; preds = %24
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.QueueDefinition, ptr %30, i32 0, i32 2
  %32 = getelementptr inbounds %struct.SemaphoreData, ptr %31, i32 0, i32 0
  %33 = load ptr, ptr %32, align 8, !tbaa !16
  %34 = icmp ne ptr %33, null
  br label %35

35:                                               ; preds = %29, %24
  %36 = phi i1 [ false, %24 ], [ %34, %29 ]
  %37 = xor i1 %36, true
  %38 = zext i1 %37 to i32
  %39 = icmp eq i32 %38, 0
  br i1 %39, label %40, label %42

40:                                               ; preds = %35
  call void @vPortRaiseBASEPRI()
  br label %41

41:                                               ; preds = %41, %40
  br label %41

42:                                               ; preds = %35
  call void @vPortValidateInterruptPriority()
  %43 = call i32 @ulPortRaiseBASEPRI()
  %44 = zext i32 %43 to i64
  store i64 %44, ptr %6, align 8, !tbaa !17
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %45 = load ptr, ptr %7, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.QueueDefinition, ptr %45, i32 0, i32 5
  %47 = load volatile i64, ptr %46, align 8, !tbaa !18
  store i64 %47, ptr %8, align 8, !tbaa !17
  %48 = load i64, ptr %8, align 8, !tbaa !17
  %49 = load ptr, ptr %7, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.QueueDefinition, ptr %49, i32 0, i32 6
  %51 = load i64, ptr %50, align 8, !tbaa !19
  %52 = icmp ult i64 %48, %51
  br i1 %52, label %53, label %105

53:                                               ; preds = %42
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #4
  %54 = load ptr, ptr %7, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.QueueDefinition, ptr %54, i32 0, i32 9
  %56 = load volatile i8, ptr %55, align 1, !tbaa !20
  store i8 %56, ptr %9, align 1, !tbaa !16
  %57 = load i64, ptr %8, align 8, !tbaa !17
  %58 = add i64 %57, 1
  %59 = load ptr, ptr %7, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.QueueDefinition, ptr %59, i32 0, i32 5
  store volatile i64 %58, ptr %60, align 8, !tbaa !18
  %61 = load i8, ptr %9, align 1, !tbaa !16
  %62 = sext i8 %61 to i32
  %63 = icmp eq i32 %62, -1
  br i1 %63, label %64, label %89

64:                                               ; preds = %53
  %65 = load ptr, ptr %7, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.QueueDefinition, ptr %65, i32 0, i32 4
  %67 = getelementptr inbounds %struct.xLIST, ptr %66, i32 0, i32 0
  %68 = load volatile i64, ptr %67, align 8, !tbaa !21
  %69 = icmp eq i64 %68, 0
  %70 = zext i1 %69 to i64
  %71 = select i1 %69, i64 1, i64 0
  %72 = icmp eq i64 %71, 0
  br i1 %72, label %73, label %87

73:                                               ; preds = %64
  %74 = load ptr, ptr %7, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.QueueDefinition, ptr %74, i32 0, i32 4
  %76 = call i64 @xTaskRemoveFromEventList(ptr noundef %75)
  %77 = icmp ne i64 %76, 0
  br i1 %77, label %78, label %85

78:                                               ; preds = %73
  %79 = load ptr, ptr %4, align 8, !tbaa !5
  %80 = icmp ne ptr %79, null
  br i1 %80, label %81, label %83

81:                                               ; preds = %78
  %82 = load ptr, ptr %4, align 8, !tbaa !5
  store i64 1, ptr %82, align 8, !tbaa !17
  br label %84

83:                                               ; preds = %78
  br label %84

84:                                               ; preds = %83, %81
  br label %86

85:                                               ; preds = %73
  br label %86

86:                                               ; preds = %85, %84
  br label %88

87:                                               ; preds = %64
  br label %88

88:                                               ; preds = %87, %86
  br label %104

89:                                               ; preds = %53
  %90 = load i8, ptr %9, align 1, !tbaa !16
  %91 = sext i8 %90 to i32
  %92 = icmp ne i32 %91, 127
  %93 = zext i1 %92 to i32
  %94 = icmp eq i32 %93, 0
  br i1 %94, label %95, label %97

95:                                               ; preds = %89
  call void @vPortRaiseBASEPRI()
  br label %96

96:                                               ; preds = %96, %95
  br label %96

97:                                               ; preds = %89
  %98 = load i8, ptr %9, align 1, !tbaa !16
  %99 = sext i8 %98 to i32
  %100 = add nsw i32 %99, 1
  %101 = trunc i32 %100 to i8
  %102 = load ptr, ptr %7, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.QueueDefinition, ptr %102, i32 0, i32 9
  store volatile i8 %101, ptr %103, align 1, !tbaa !20
  br label %104

104:                                              ; preds = %97, %88
  store i64 1, ptr %5, align 8, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #4
  br label %106

105:                                              ; preds = %42
  store i64 0, ptr %5, align 8, !tbaa !17
  br label %106

106:                                              ; preds = %105, %104
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %107 = load i64, ptr %6, align 8, !tbaa !17
  %108 = trunc i64 %107 to i32
  call void @vPortSetBASEPRI(i32 noundef %108)
  %109 = load i64, ptr %5, align 8, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret i64 %109
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !12, i64 128}
!10 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !11, i64 32, !11, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137}
!11 = !{!"xLIST", !12, i64 0, !6, i64 8, !13, i64 16}
!12 = !{!"long", !7, i64 0}
!13 = !{!"xMINI_LIST_ITEM", !14, i64 0, !6, i64 8, !6, i64 16}
!14 = !{!"int", !7, i64 0}
!15 = !{!10, !6, i64 0}
!16 = !{!7, !7, i64 0}
!17 = !{!12, !12, i64 0}
!18 = !{!10, !12, i64 112}
!19 = !{!10, !12, i64 120}
!20 = !{!10, !7, i64 137}
!21 = !{!10, !12, i64 72}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #1

declare void @vPortValidateInterruptPriority() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xQueueGiveFromISR(ptr noundef %0, ptr noundef writeonly %1) local_unnamed_addr #2 {
  %3 = icmp eq ptr %0, null
  br i1 %3, label %4, label %6

4:                                                ; preds = %2
  tail call void @vPortRaiseBASEPRI()
  br label %5

5:                                                ; preds = %5, %4
  br label %5

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 128
  %8 = load i64, ptr %7, align 8, !tbaa !5
  %.not = icmp eq i64 %8, 0
  br i1 %.not, label %11, label %9

9:                                                ; preds = %6
  tail call void @vPortRaiseBASEPRI()
  br label %10

10:                                               ; preds = %10, %9
  br label %10

11:                                               ; preds = %6
  %12 = load ptr, ptr %0, align 8, !tbaa !14
  %13 = icmp eq ptr %12, null
  br i1 %13, label %14, label %.critedge

14:                                               ; preds = %11
  %15 = getelementptr inbounds i8, ptr %0, i64 16
  %16 = load ptr, ptr %15, align 8, !tbaa !15
  %.not27 = icmp eq ptr %16, null
  br i1 %.not27, label %.critedge, label %17

17:                                               ; preds = %14
  tail call void @vPortRaiseBASEPRI()
  br label %18

18:                                               ; preds = %18, %17
  br label %18

.critedge:                                        ; preds = %11, %14
  tail call void @vPortValidateInterruptPriority() #3
  %19 = tail call i32 @ulPortRaiseBASEPRI()
  %20 = getelementptr inbounds i8, ptr %0, i64 112
  %21 = load volatile i64, ptr %20, align 8, !tbaa !16
  %22 = getelementptr inbounds i8, ptr %0, i64 120
  %23 = load i64, ptr %22, align 8, !tbaa !17
  %24 = icmp ult i64 %21, %23
  br i1 %24, label %25, label %41

25:                                               ; preds = %.critedge
  %26 = getelementptr inbounds i8, ptr %0, i64 137
  %27 = load volatile i8, ptr %26, align 1, !tbaa !18
  %28 = add nuw i64 %21, 1
  store volatile i64 %28, ptr %20, align 8, !tbaa !16
  switch i8 %27, label %39 [
    i8 -1, label %29
    i8 127, label %37
  ]

29:                                               ; preds = %25
  %30 = getelementptr inbounds i8, ptr %0, i64 72
  %31 = load volatile i64, ptr %30, align 8, !tbaa !19
  %.not26 = icmp eq i64 %31, 0
  br i1 %.not26, label %41, label %32

32:                                               ; preds = %29
  %33 = tail call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %30) #3
  %34 = icmp ne i64 %33, 0
  %35 = icmp ne ptr %1, null
  %or.cond = and i1 %35, %34
  br i1 %or.cond, label %36, label %41

36:                                               ; preds = %32
  store i64 1, ptr %1, align 8, !tbaa !20
  br label %41

37:                                               ; preds = %25
  tail call void @vPortRaiseBASEPRI()
  br label %38

38:                                               ; preds = %38, %37
  br label %38

39:                                               ; preds = %25
  %40 = add nuw i8 %27, 1
  store volatile i8 %40, ptr %26, align 1, !tbaa !18
  br label %41

41:                                               ; preds = %.critedge, %39, %29, %36, %32
  %.0 = phi i64 [ 1, %32 ], [ 1, %36 ], [ 1, %29 ], [ 1, %39 ], [ 0, %.critedge ]
  tail call void @vPortSetBASEPRI(i32 noundef %19)
  ret i64 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 128}
!6 = !{!"QueueDefinition", !7, i64 0, !7, i64 8, !8, i64 16, !10, i64 32, !10, i64 72, !11, i64 112, !11, i64 120, !11, i64 128, !8, i64 136, !8, i64 137}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !7, i64 8, !12, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"xMINI_LIST_ITEM", !13, i64 0, !7, i64 8, !7, i64 16}
!13 = !{!"int", !8, i64 0}
!14 = !{!6, !7, i64 0}
!15 = !{!8, !8, i64 0}
!16 = !{!6, !11, i64 112}
!17 = !{!6, !11, i64 120}
!18 = !{!6, !8, i64 137}
!19 = !{!6, !11, i64 72}
!20 = !{!11, !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass