; LLVM IR from alenic/realGA :: src/realga_mt.ll (ZN18RealGenMultithreadC2Ej)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.RealGenMultithread = type { %class.RealGA, i32, ptr }
%class.RealGA = type { ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.0", %"class.std::vector.0", %class.RealGAOptions, ptr, %"class.std::vector", float, i32, ptr, ptr, ptr, i32, float }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealGAOptions = type { i64, i64, %"class.std::vector", %"class.std::vector", i32, i32, float, i8, i32, i32, float, i32, i32, i32, float, float, float, float }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTV18RealGenMultithread = external dso_local unnamed_addr constant { [3 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18RealGenMultithreadC2Ej(ptr noundef nonnull align 8 dereferenceable(312) %0, i32 noundef %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  %7 = load ptr, ptr %3, align 8
  call void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296) %7)
  store ptr getelementptr inbounds inrange(-16, 8) ({ [3 x ptr] }, ptr @_ZTV18RealGenMultithread, i32 0, i32 0, i32 2), ptr %7, align 8, !tbaa !11
  %8 = load i32, ptr %4, align 4, !tbaa !9
  %9 = zext i32 %8 to i64
  %10 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %9, i64 8)
  %11 = extractvalue { i64, i1 } %10, 1
  %12 = extractvalue { i64, i1 } %10, 0
  %13 = select i1 %11, i64 -1, i64 %12
  %14 = invoke noalias noundef nonnull ptr @_Znam(i64 noundef %13) #5
          to label %15 unwind label %17

15:                                               ; preds = %2
  %16 = getelementptr inbounds %class.RealGenMultithread, ptr %7, i32 0, i32 2
  store ptr %14, ptr %16, align 8, !tbaa !13
  ret void

17:                                               ; preds = %2
  %18 = landingpad { ptr, i32 }
          cleanup
  %19 = extractvalue { ptr, i32 } %18, 0
  store ptr %19, ptr %5, align 8
  %20 = extractvalue { ptr, i32 } %18, 1
  store i32 %20, ptr %6, align 4
  call void @_ZN6RealGAD2Ev(ptr noundef nonnull align 8 dereferenceable(296) %7) #6
  br label %21

21:                                               ; preds = %17
  %22 = load ptr, ptr %5, align 8
  %23 = load i32, ptr %6, align 4
  %24 = insertvalue { ptr, i32 } poison, ptr %22, 0
  %25 = insertvalue { ptr, i32 } %24, i32 %23, 1
  resume { ptr, i32 } %25
}

declare void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296)) unnamed_addr #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #3

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nounwind
declare void @_ZN6RealGAD2Ev(ptr noundef nonnull align 8 dereferenceable(296)) unnamed_addr #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { builtin allocsize(0) }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"vtable pointer", !8, i64 0}
!13 = !{!14, !6, i64 304}
!14 = !{!"_ZTS18RealGenMultithread", !15, i64 0, !10, i64 296, !6, i64 304}
!15 = !{!"_ZTS6RealGA", !16, i64 8, !16, i64 32, !20, i64 56, !20, i64 80, !24, i64 104, !6, i64 224, !16, i64 232, !27, i64 256, !10, i64 260, !6, i64 264, !6, i64 272, !6, i64 280, !10, i64 288, !27, i64 292}
!16 = !{!"_ZTSSt6vectorIfSaIfEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!"_ZTS13RealGAOptions", !25, i64 0, !25, i64 8, !16, i64 16, !16, i64 40, !10, i64 64, !26, i64 68, !27, i64 72, !28, i64 76, !29, i64 80, !10, i64 84, !27, i64 88, !30, i64 92, !10, i64 96, !31, i64 100, !27, i64 104, !27, i64 108, !27, i64 112, !27, i64 116}
!25 = !{!"long", !7, i64 0}
!26 = !{!"_ZTS11VerboseType", !7, i64 0}
!27 = !{!"float", !7, i64 0}
!28 = !{!"bool", !7, i64 0}
!29 = !{!"_ZTS13SelectionType", !7, i64 0}
!30 = !{!"_ZTS13CrossoverType", !7, i64 0}
!31 = !{!"_ZTS12MutationType", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTV18RealGenMultithread = external dso_local unnamed_addr constant { [3 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18RealGenMultithreadC2Ej(ptr noundef nonnull align 8 dereferenceable(312) %0, i32 noundef %1) unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  tail call void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296) %0)
  store ptr getelementptr inbounds inrange(-16, 8) (i8, ptr @_ZTV18RealGenMultithread, i64 16), ptr %0, align 8, !tbaa !5
  %3 = zext i32 %1 to i64
  %4 = shl nuw nsw i64 %3, 3
  %5 = invoke noalias noundef nonnull ptr @_Znam(i64 noundef %4) #4
          to label %6 unwind label %8

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 304
  store ptr %5, ptr %7, align 8, !tbaa !8
  ret void

8:                                                ; preds = %2
  %9 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZN6RealGAD2Ev(ptr noundef nonnull align 8 dereferenceable(296) %0) #5
  resume { ptr, i32 } %9
}

declare void @_ZN6RealGAC2Ev(ptr noundef nonnull align 8 dereferenceable(296)) unnamed_addr #1

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) local_unnamed_addr #2

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nounwind
declare void @_ZN6RealGAD2Ev(ptr noundef nonnull align 8 dereferenceable(296)) unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { builtin allocsize(0) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !15, i64 304}
!9 = !{!"_ZTS18RealGenMultithread", !10, i64 0, !23, i64 296, !15, i64 304}
!10 = !{!"_ZTS6RealGA", !11, i64 8, !11, i64 32, !17, i64 56, !17, i64 80, !21, i64 104, !15, i64 224, !11, i64 232, !25, i64 256, !23, i64 260, !15, i64 264, !15, i64 272, !15, i64 280, !23, i64 288, !25, i64 292}
!11 = !{!"_ZTSSt6vectorIfSaIfEE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!15 = !{!"any pointer", !16, i64 0}
!16 = !{!"omnipotent char", !7, i64 0}
!17 = !{!"_ZTSSt6vectorI14RealChromosomeSaIS0_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseI14RealChromosomeSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI14RealChromosomeSaIS0_EE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!21 = !{!"_ZTS13RealGAOptions", !22, i64 0, !22, i64 8, !11, i64 16, !11, i64 40, !23, i64 64, !24, i64 68, !25, i64 72, !26, i64 76, !27, i64 80, !23, i64 84, !25, i64 88, !28, i64 92, !23, i64 96, !29, i64 100, !25, i64 104, !25, i64 108, !25, i64 112, !25, i64 116}
!22 = !{!"long", !16, i64 0}
!23 = !{!"int", !16, i64 0}
!24 = !{!"_ZTS11VerboseType", !16, i64 0}
!25 = !{!"float", !16, i64 0}
!26 = !{!"bool", !16, i64 0}
!27 = !{!"_ZTS13SelectionType", !16, i64 0}
!28 = !{!"_ZTS13CrossoverType", !16, i64 0}
!29 = !{!"_ZTS12MutationType", !16, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass