; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xTaskGenericNotifyFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [32 x i8], i64, i64, [1 x i32], [1 x i8] }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@xTickCount = external hidden global i32, align 4
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @uxListRemove(ptr noundef) #1

declare void @vListInsertEnd(ptr noundef, ptr noundef) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

declare void @vPortValidateInterruptPriority() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xTaskGenericNotifyFromISR(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4, ptr noundef %5) #3 {
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i8, align 1
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  store ptr %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !9
  store i32 %2, ptr %9, align 4, !tbaa !11
  store i32 %3, ptr %10, align 4, !tbaa !11
  store ptr %4, ptr %11, align 8, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  store i64 1, ptr %15, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  %18 = icmp eq ptr %17, null
  br i1 %18, label %19, label %21

19:                                               ; preds = %6
  call void @vPortRaiseBASEPRI()
  br label %20

20:                                               ; preds = %20, %19
  br label %20

21:                                               ; preds = %6
  %22 = load i64, ptr %8, align 8, !tbaa !9
  %23 = icmp ult i64 %22, 1
  %24 = zext i1 %23 to i32
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %28

26:                                               ; preds = %21
  call void @vPortRaiseBASEPRI()
  br label %27

27:                                               ; preds = %27, %26
  br label %27

28:                                               ; preds = %21
  call void @vPortValidateInterruptPriority()
  %29 = load ptr, ptr %7, align 8, !tbaa !5
  store ptr %29, ptr %13, align 8, !tbaa !5
  %30 = call i32 @ulPortRaiseBASEPRI()
  %31 = zext i32 %30 to i64
  store i64 %31, ptr %16, align 8, !tbaa !9
  %32 = load ptr, ptr %11, align 8, !tbaa !5
  %33 = icmp ne ptr %32, null
  br i1 %33, label %34, label %41

34:                                               ; preds = %28
  %35 = load ptr, ptr %13, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %35, i32 0, i32 8
  %37 = load i64, ptr %8, align 8, !tbaa !9
  %38 = getelementptr inbounds [1 x i32], ptr %36, i64 0, i64 %37
  %39 = load volatile i32, ptr %38, align 4, !tbaa !11
  %40 = load ptr, ptr %11, align 8, !tbaa !5
  store i32 %39, ptr %40, align 4, !tbaa !11
  br label %41

41:                                               ; preds = %34, %28
  %42 = load ptr, ptr %13, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %42, i32 0, i32 9
  %44 = load i64, ptr %8, align 8, !tbaa !9
  %45 = getelementptr inbounds [1 x i8], ptr %43, i64 0, i64 %44
  %46 = load volatile i8, ptr %45, align 1, !tbaa !13
  store i8 %46, ptr %14, align 1, !tbaa !13
  %47 = load ptr, ptr %13, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %47, i32 0, i32 9
  %49 = load i64, ptr %8, align 8, !tbaa !9
  %50 = getelementptr inbounds [1 x i8], ptr %48, i64 0, i64 %49
  store volatile i8 2, ptr %50, align 1, !tbaa !13
  %51 = load i32, ptr %10, align 4, !tbaa !11
  switch i32 %51, label %85 [
    i32 1, label %52
    i32 2, label %60
    i32 3, label %67
    i32 4, label %73
    i32 0, label %93
  ]

52:                                               ; preds = %41
  %53 = load i32, ptr %9, align 4, !tbaa !11
  %54 = load ptr, ptr %13, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %54, i32 0, i32 8
  %56 = load i64, ptr %8, align 8, !tbaa !9
  %57 = getelementptr inbounds [1 x i32], ptr %55, i64 0, i64 %56
  %58 = load volatile i32, ptr %57, align 4, !tbaa !11
  %59 = or i32 %58, %53
  store volatile i32 %59, ptr %57, align 4, !tbaa !11
  br label %93

60:                                               ; preds = %41
  %61 = load ptr, ptr %13, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %61, i32 0, i32 8
  %63 = load i64, ptr %8, align 8, !tbaa !9
  %64 = getelementptr inbounds [1 x i32], ptr %62, i64 0, i64 %63
  %65 = load volatile i32, ptr %64, align 4, !tbaa !11
  %66 = add i32 %65, 1
  store volatile i32 %66, ptr %64, align 4, !tbaa !11
  br label %93

67:                                               ; preds = %41
  %68 = load i32, ptr %9, align 4, !tbaa !11
  %69 = load ptr, ptr %13, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %69, i32 0, i32 8
  %71 = load i64, ptr %8, align 8, !tbaa !9
  %72 = getelementptr inbounds [1 x i32], ptr %70, i64 0, i64 %71
  store volatile i32 %68, ptr %72, align 4, !tbaa !11
  br label %93

73:                                               ; preds = %41
  %74 = load i8, ptr %14, align 1, !tbaa !13
  %75 = zext i8 %74 to i32
  %76 = icmp ne i32 %75, 2
  br i1 %76, label %77, label %83

77:                                               ; preds = %73
  %78 = load i32, ptr %9, align 4, !tbaa !11
  %79 = load ptr, ptr %13, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %79, i32 0, i32 8
  %81 = load i64, ptr %8, align 8, !tbaa !9
  %82 = getelementptr inbounds [1 x i32], ptr %80, i64 0, i64 %81
  store volatile i32 %78, ptr %82, align 4, !tbaa !11
  br label %84

83:                                               ; preds = %73
  store i64 0, ptr %15, align 8, !tbaa !9
  br label %84

84:                                               ; preds = %83, %77
  br label %93

85:                                               ; preds = %41
  %86 = load volatile i32, ptr @xTickCount, align 4, !tbaa !11
  %87 = icmp eq i32 %86, 0
  %88 = zext i1 %87 to i32
  %89 = icmp eq i32 %88, 0
  br i1 %89, label %90, label %92

90:                                               ; preds = %85
  call void @vPortRaiseBASEPRI()
  br label %91

91:                                               ; preds = %91, %90
  br label %91

92:                                               ; preds = %85
  br label %93

93:                                               ; preds = %92, %84, %67, %60, %52, %41
  %94 = load i8, ptr %14, align 1, !tbaa !13
  %95 = zext i8 %94 to i32
  %96 = icmp eq i32 %95, 1
  br i1 %96, label %97, label %145

97:                                               ; preds = %93
  %98 = load ptr, ptr %13, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %98, i32 0, i32 2
  %100 = getelementptr inbounds %struct.xLIST_ITEM, ptr %99, i32 0, i32 4
  %101 = load ptr, ptr %100, align 8, !tbaa !14
  %102 = icmp eq ptr %101, null
  %103 = zext i1 %102 to i32
  %104 = icmp eq i32 %103, 0
  br i1 %104, label %105, label %107

105:                                              ; preds = %97
  call void @vPortRaiseBASEPRI()
  br label %106

106:                                              ; preds = %106, %105
  br label %106

107:                                              ; preds = %97
  %108 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !9
  %109 = icmp eq i64 %108, 0
  br i1 %109, label %110, label %126

110:                                              ; preds = %107
  %111 = load ptr, ptr %13, align 8, !tbaa !5
  %112 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %111, i32 0, i32 1
  %113 = call i64 @uxListRemove(ptr noundef %112)
  %114 = load ptr, ptr %13, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %114, i32 0, i32 3
  %116 = load i64, ptr %115, align 8, !tbaa !17
  %117 = shl i64 1, %116
  %118 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %119 = or i64 %118, %117
  store volatile i64 %119, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %120 = load ptr, ptr %13, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %120, i32 0, i32 3
  %122 = load i64, ptr %121, align 8, !tbaa !17
  %123 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %122
  %124 = load ptr, ptr %13, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %124, i32 0, i32 1
  call void @vListInsertEnd(ptr noundef %123, ptr noundef %125)
  br label %129

126:                                              ; preds = %107
  %127 = load ptr, ptr %13, align 8, !tbaa !5
  %128 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %127, i32 0, i32 2
  call void @vListInsertEnd(ptr noundef @xPendingReadyList, ptr noundef %128)
  br label %129

129:                                              ; preds = %126, %110
  %130 = load ptr, ptr %13, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %130, i32 0, i32 3
  %132 = load i64, ptr %131, align 8, !tbaa !17
  %133 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %133, i32 0, i32 3
  %135 = load i64, ptr %134, align 8, !tbaa !17
  %136 = icmp ugt i64 %132, %135
  br i1 %136, label %137, label %143

137:                                              ; preds = %129
  %138 = load ptr, ptr %12, align 8, !tbaa !5
  %139 = icmp ne ptr %138, null
  br i1 %139, label %140, label %142

140:                                              ; preds = %137
  %141 = load ptr, ptr %12, align 8, !tbaa !5
  store i64 1, ptr %141, align 8, !tbaa !9
  br label %142

142:                                              ; preds = %140, %137
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !9
  br label %144

143:                                              ; preds = %129
  br label %144

144:                                              ; preds = %143, %142
  br label %145

145:                                              ; preds = %144, %93
  %146 = load i64, ptr %16, align 8, !tbaa !9
  %147 = trunc i64 %146 to i32
  call void @vPortSetBASEPRI(i32 noundef %147)
  %148 = load i64, ptr %15, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  ret i64 %148
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !6, i64 80}
!15 = !{!"tskTaskControlBlock", !6, i64 0, !16, i64 8, !16, i64 48, !10, i64 88, !6, i64 96, !7, i64 104, !10, i64 136, !10, i64 144, !7, i64 152, !7, i64 156}
!16 = !{!"xLIST_ITEM", !12, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!17 = !{!15, !10, i64 88}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@xTickCount = external hidden global i32, align 4
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

declare i64 @uxListRemove(ptr noundef) local_unnamed_addr #0

declare void @vListInsertEnd(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortValidateInterruptPriority() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xTaskGenericNotifyFromISR(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef writeonly %4, ptr noundef writeonly %5) local_unnamed_addr #2 {
  %7 = icmp eq ptr %0, null
  br i1 %7, label %8, label %10

8:                                                ; preds = %6
  tail call void @vPortRaiseBASEPRI()
  br label %9

9:                                                ; preds = %9, %8
  br label %9

10:                                               ; preds = %6
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %13, label %11

11:                                               ; preds = %10
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

13:                                               ; preds = %10
  tail call void @vPortValidateInterruptPriority() #3
  %14 = tail call i32 @ulPortRaiseBASEPRI()
  %.not38 = icmp eq ptr %4, null
  br i1 %.not38, label %18, label %15

15:                                               ; preds = %13
  %16 = getelementptr inbounds i8, ptr %0, i64 152
  %17 = load volatile i32, ptr %16, align 4, !tbaa !5
  store i32 %17, ptr %4, align 4, !tbaa !5
  br label %18

18:                                               ; preds = %15, %13
  %19 = getelementptr inbounds i8, ptr %0, i64 156
  %20 = load volatile i8, ptr %19, align 1, !tbaa !9
  store volatile i8 2, ptr %19, align 1, !tbaa !9
  switch i32 %3, label %34 [
    i32 1, label %21
    i32 2, label %25
    i32 3, label %29
    i32 4, label %31
    i32 0, label %38
  ]

21:                                               ; preds = %18
  %22 = getelementptr inbounds i8, ptr %0, i64 152
  %23 = load volatile i32, ptr %22, align 4, !tbaa !5
  %24 = or i32 %23, %2
  store volatile i32 %24, ptr %22, align 4, !tbaa !5
  br label %38

25:                                               ; preds = %18
  %26 = getelementptr inbounds i8, ptr %0, i64 152
  %27 = load volatile i32, ptr %26, align 4, !tbaa !5
  %28 = add i32 %27, 1
  store volatile i32 %28, ptr %26, align 4, !tbaa !5
  br label %38

29:                                               ; preds = %18
  %30 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %2, ptr %30, align 4, !tbaa !5
  br label %38

31:                                               ; preds = %18
  %.not39 = icmp eq i8 %20, 2
  br i1 %.not39, label %.thread, label %32

32:                                               ; preds = %31
  %33 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %2, ptr %33, align 4, !tbaa !5
  br label %38

34:                                               ; preds = %18
  %35 = load volatile i32, ptr @xTickCount, align 4, !tbaa !5
  %.not40 = icmp eq i32 %35, 0
  br i1 %.not40, label %38, label %36

36:                                               ; preds = %34
  tail call void @vPortRaiseBASEPRI()
  br label %37

37:                                               ; preds = %37, %36
  br label %37

38:                                               ; preds = %34, %32, %29, %25, %21, %18
  %39 = icmp eq i8 %20, 1
  br i1 %39, label %40, label %.thread

40:                                               ; preds = %38
  %41 = getelementptr inbounds i8, ptr %0, i64 48
  %42 = getelementptr inbounds i8, ptr %0, i64 80
  %43 = load ptr, ptr %42, align 8, !tbaa !10
  %.not41 = icmp eq ptr %43, null
  br i1 %.not41, label %46, label %44

44:                                               ; preds = %40
  tail call void @vPortRaiseBASEPRI()
  br label %45

45:                                               ; preds = %45, %44
  br label %45

46:                                               ; preds = %40
  %47 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !15
  %48 = icmp eq i64 %47, 0
  br i1 %48, label %49, label %58

49:                                               ; preds = %46
  %50 = getelementptr inbounds i8, ptr %0, i64 8
  %51 = tail call i64 @uxListRemove(ptr noundef nonnull %50) #3
  %52 = getelementptr inbounds i8, ptr %0, i64 88
  %53 = load i64, ptr %52, align 8, !tbaa !16
  %54 = shl nuw i64 1, %53
  %55 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %56 = or i64 %55, %54
  store volatile i64 %56, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %57 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %53
  tail call void @vListInsertEnd(ptr noundef nonnull %57, ptr noundef nonnull %50) #3
  br label %59

58:                                               ; preds = %46
  tail call void @vListInsertEnd(ptr noundef nonnull @xPendingReadyList, ptr noundef nonnull %41) #3
  br label %59

59:                                               ; preds = %58, %49
  %60 = getelementptr inbounds i8, ptr %0, i64 88
  %61 = load i64, ptr %60, align 8, !tbaa !16
  %62 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !17
  %63 = getelementptr inbounds i8, ptr %62, i64 88
  %64 = load i64, ptr %63, align 8, !tbaa !16
  %65 = icmp ugt i64 %61, %64
  br i1 %65, label %66, label %.thread

66:                                               ; preds = %59
  %.not42 = icmp eq ptr %5, null
  br i1 %.not42, label %68, label %67

67:                                               ; preds = %66
  store i64 1, ptr %5, align 8, !tbaa !15
  br label %68

68:                                               ; preds = %67, %66
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !15
  br label %.thread

.thread:                                          ; preds = %31, %68, %59, %38
  %.044 = phi i64 [ 1, %68 ], [ 1, %59 ], [ 1, %38 ], [ 0, %31 ]
  tail call void @vPortSetBASEPRI(i32 noundef %14)
  ret i64 %.044
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !12, i64 80}
!11 = !{!"tskTaskControlBlock", !12, i64 0, !13, i64 8, !13, i64 48, !14, i64 88, !12, i64 96, !7, i64 104, !14, i64 136, !14, i64 144, !7, i64 152, !7, i64 156}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!"xLIST_ITEM", !6, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32}
!14 = !{!"long", !7, i64 0}
!15 = !{!14, !14, i64 0}
!16 = !{!11, !14, i64 88}
!17 = !{!12, !12, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass