; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xTaskGenericNotify)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [32 x i8], i64, i64, [1 x i32], [1 x i8] }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@xTickCount = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortEnterCritical() #1

declare i64 @uxListRemove(ptr noundef) #1

declare void @vListInsertEnd(ptr noundef, ptr noundef) #1

declare void @vPortExitCritical() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xTaskGenericNotify(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef %4) #3 {
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i8, align 1
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i64 %1, ptr %7, align 8, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !11
  store i32 %3, ptr %9, align 4, !tbaa !11
  store ptr %4, ptr %10, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  store i64 1, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #4
  %14 = load i64, ptr %7, align 8, !tbaa !9
  %15 = icmp ult i64 %14, 1
  %16 = zext i1 %15 to i32
  %17 = icmp eq i32 %16, 0
  br i1 %17, label %18, label %20

18:                                               ; preds = %5
  call void @vPortRaiseBASEPRI()
  br label %19

19:                                               ; preds = %19, %18
  br label %19

20:                                               ; preds = %5
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %23, label %25

23:                                               ; preds = %20
  call void @vPortRaiseBASEPRI()
  br label %24

24:                                               ; preds = %24, %23
  br label %24

25:                                               ; preds = %20
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %26, ptr %11, align 8, !tbaa !5
  call void @vPortEnterCritical()
  %27 = load ptr, ptr %10, align 8, !tbaa !5
  %28 = icmp ne ptr %27, null
  br i1 %28, label %29, label %36

29:                                               ; preds = %25
  %30 = load ptr, ptr %11, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %30, i32 0, i32 8
  %32 = load i64, ptr %7, align 8, !tbaa !9
  %33 = getelementptr inbounds [1 x i32], ptr %31, i64 0, i64 %32
  %34 = load volatile i32, ptr %33, align 4, !tbaa !11
  %35 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %34, ptr %35, align 4, !tbaa !11
  br label %36

36:                                               ; preds = %29, %25
  %37 = load ptr, ptr %11, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %37, i32 0, i32 9
  %39 = load i64, ptr %7, align 8, !tbaa !9
  %40 = getelementptr inbounds [1 x i8], ptr %38, i64 0, i64 %39
  %41 = load volatile i8, ptr %40, align 1, !tbaa !13
  store i8 %41, ptr %13, align 1, !tbaa !13
  %42 = load ptr, ptr %11, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %42, i32 0, i32 9
  %44 = load i64, ptr %7, align 8, !tbaa !9
  %45 = getelementptr inbounds [1 x i8], ptr %43, i64 0, i64 %44
  store volatile i8 2, ptr %45, align 1, !tbaa !13
  %46 = load i32, ptr %9, align 4, !tbaa !11
  switch i32 %46, label %80 [
    i32 1, label %47
    i32 2, label %55
    i32 3, label %62
    i32 4, label %68
    i32 0, label %88
  ]

47:                                               ; preds = %36
  %48 = load i32, ptr %8, align 4, !tbaa !11
  %49 = load ptr, ptr %11, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %49, i32 0, i32 8
  %51 = load i64, ptr %7, align 8, !tbaa !9
  %52 = getelementptr inbounds [1 x i32], ptr %50, i64 0, i64 %51
  %53 = load volatile i32, ptr %52, align 4, !tbaa !11
  %54 = or i32 %53, %48
  store volatile i32 %54, ptr %52, align 4, !tbaa !11
  br label %88

55:                                               ; preds = %36
  %56 = load ptr, ptr %11, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %56, i32 0, i32 8
  %58 = load i64, ptr %7, align 8, !tbaa !9
  %59 = getelementptr inbounds [1 x i32], ptr %57, i64 0, i64 %58
  %60 = load volatile i32, ptr %59, align 4, !tbaa !11
  %61 = add i32 %60, 1
  store volatile i32 %61, ptr %59, align 4, !tbaa !11
  br label %88

62:                                               ; preds = %36
  %63 = load i32, ptr %8, align 4, !tbaa !11
  %64 = load ptr, ptr %11, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %64, i32 0, i32 8
  %66 = load i64, ptr %7, align 8, !tbaa !9
  %67 = getelementptr inbounds [1 x i32], ptr %65, i64 0, i64 %66
  store volatile i32 %63, ptr %67, align 4, !tbaa !11
  br label %88

68:                                               ; preds = %36
  %69 = load i8, ptr %13, align 1, !tbaa !13
  %70 = zext i8 %69 to i32
  %71 = icmp ne i32 %70, 2
  br i1 %71, label %72, label %78

72:                                               ; preds = %68
  %73 = load i32, ptr %8, align 4, !tbaa !11
  %74 = load ptr, ptr %11, align 8, !tbaa !5
  %75 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %74, i32 0, i32 8
  %76 = load i64, ptr %7, align 8, !tbaa !9
  %77 = getelementptr inbounds [1 x i32], ptr %75, i64 0, i64 %76
  store volatile i32 %73, ptr %77, align 4, !tbaa !11
  br label %79

78:                                               ; preds = %68
  store i64 0, ptr %12, align 8, !tbaa !9
  br label %79

79:                                               ; preds = %78, %72
  br label %88

80:                                               ; preds = %36
  %81 = load volatile i32, ptr @xTickCount, align 4, !tbaa !11
  %82 = icmp eq i32 %81, 0
  %83 = zext i1 %82 to i32
  %84 = icmp eq i32 %83, 0
  br i1 %84, label %85, label %87

85:                                               ; preds = %80
  call void @vPortRaiseBASEPRI()
  br label %86

86:                                               ; preds = %86, %85
  br label %86

87:                                               ; preds = %80
  br label %88

88:                                               ; preds = %87, %79, %62, %55, %47, %36
  %89 = load i8, ptr %13, align 1, !tbaa !13
  %90 = zext i8 %89 to i32
  %91 = icmp eq i32 %90, 1
  br i1 %91, label %92, label %128

92:                                               ; preds = %88
  %93 = load ptr, ptr %11, align 8, !tbaa !5
  %94 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %93, i32 0, i32 1
  %95 = call i64 @uxListRemove(ptr noundef %94)
  %96 = load ptr, ptr %11, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %96, i32 0, i32 3
  %98 = load i64, ptr %97, align 8, !tbaa !14
  %99 = shl i64 1, %98
  %100 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %101 = or i64 %100, %99
  store volatile i64 %101, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %102 = load ptr, ptr %11, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %102, i32 0, i32 3
  %104 = load i64, ptr %103, align 8, !tbaa !14
  %105 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %104
  %106 = load ptr, ptr %11, align 8, !tbaa !5
  %107 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %106, i32 0, i32 1
  call void @vListInsertEnd(ptr noundef %105, ptr noundef %107)
  %108 = load ptr, ptr %11, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %108, i32 0, i32 2
  %110 = getelementptr inbounds %struct.xLIST_ITEM, ptr %109, i32 0, i32 4
  %111 = load ptr, ptr %110, align 8, !tbaa !17
  %112 = icmp eq ptr %111, null
  %113 = zext i1 %112 to i32
  %114 = icmp eq i32 %113, 0
  br i1 %114, label %115, label %117

115:                                              ; preds = %92
  call void @vPortRaiseBASEPRI()
  br label %116

116:                                              ; preds = %116, %115
  br label %116

117:                                              ; preds = %92
  %118 = load ptr, ptr %11, align 8, !tbaa !5
  %119 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %118, i32 0, i32 3
  %120 = load i64, ptr %119, align 8, !tbaa !14
  %121 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %121, i32 0, i32 3
  %123 = load i64, ptr %122, align 8, !tbaa !14
  %124 = icmp ugt i64 %120, %123
  br i1 %124, label %125, label %126

125:                                              ; preds = %117
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !11
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  br label %127

126:                                              ; preds = %117
  br label %127

127:                                              ; preds = %126, %125
  br label %129

128:                                              ; preds = %88
  br label %129

129:                                              ; preds = %128, %127
  call void @vPortExitCritical()
  %130 = load i64, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  ret i64 %130
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !10, i64 88}
!15 = !{!"tskTaskControlBlock", !6, i64 0, !16, i64 8, !16, i64 48, !10, i64 88, !6, i64 96, !7, i64 104, !10, i64 136, !10, i64 144, !7, i64 152, !7, i64 156}
!16 = !{!"xLIST_ITEM", !12, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!17 = !{!15, !6, i64 80}
!18 = !{i64 2148458423}
!19 = !{i64 2148458492}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@xTickCount = external hidden global i32, align 4

declare void @vPortEnterCritical() local_unnamed_addr #0

declare i64 @uxListRemove(ptr noundef) local_unnamed_addr #0

declare void @vListInsertEnd(ptr noundef, ptr noundef) local_unnamed_addr #0

declare void @vPortExitCritical() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xTaskGenericNotify(ptr noundef %0, i64 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef writeonly %4) local_unnamed_addr #2 {
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %8, label %6

6:                                                ; preds = %5
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %5
  %9 = icmp eq ptr %0, null
  br i1 %9, label %10, label %12

10:                                               ; preds = %8
  tail call void @vPortRaiseBASEPRI()
  br label %11

11:                                               ; preds = %11, %10
  br label %11

12:                                               ; preds = %8
  tail call void @vPortEnterCritical() #3
  %.not33 = icmp eq ptr %4, null
  br i1 %.not33, label %16, label %13

13:                                               ; preds = %12
  %14 = getelementptr inbounds i8, ptr %0, i64 152
  %15 = load volatile i32, ptr %14, align 4, !tbaa !5
  store i32 %15, ptr %4, align 4, !tbaa !5
  br label %16

16:                                               ; preds = %13, %12
  %17 = getelementptr inbounds i8, ptr %0, i64 156
  %18 = load volatile i8, ptr %17, align 1, !tbaa !9
  store volatile i8 2, ptr %17, align 1, !tbaa !9
  switch i32 %3, label %32 [
    i32 1, label %19
    i32 2, label %23
    i32 3, label %27
    i32 4, label %29
    i32 0, label %36
  ]

19:                                               ; preds = %16
  %20 = getelementptr inbounds i8, ptr %0, i64 152
  %21 = load volatile i32, ptr %20, align 4, !tbaa !5
  %22 = or i32 %21, %2
  store volatile i32 %22, ptr %20, align 4, !tbaa !5
  br label %36

23:                                               ; preds = %16
  %24 = getelementptr inbounds i8, ptr %0, i64 152
  %25 = load volatile i32, ptr %24, align 4, !tbaa !5
  %26 = add i32 %25, 1
  store volatile i32 %26, ptr %24, align 4, !tbaa !5
  br label %36

27:                                               ; preds = %16
  %28 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %2, ptr %28, align 4, !tbaa !5
  br label %36

29:                                               ; preds = %16
  %.not34 = icmp eq i8 %18, 2
  br i1 %.not34, label %.thread, label %30

30:                                               ; preds = %29
  %31 = getelementptr inbounds i8, ptr %0, i64 152
  store volatile i32 %2, ptr %31, align 4, !tbaa !5
  br label %36

32:                                               ; preds = %16
  %33 = load volatile i32, ptr @xTickCount, align 4, !tbaa !5
  %.not35 = icmp eq i32 %33, 0
  br i1 %.not35, label %36, label %34

34:                                               ; preds = %32
  tail call void @vPortRaiseBASEPRI()
  br label %35

35:                                               ; preds = %35, %34
  br label %35

36:                                               ; preds = %32, %30, %27, %23, %19, %16
  %37 = icmp eq i8 %18, 1
  br i1 %37, label %38, label %.thread

38:                                               ; preds = %36
  %39 = getelementptr inbounds i8, ptr %0, i64 8
  %40 = tail call i64 @uxListRemove(ptr noundef nonnull %39) #3
  %41 = getelementptr inbounds i8, ptr %0, i64 88
  %42 = load i64, ptr %41, align 8, !tbaa !10
  %43 = shl nuw i64 1, %42
  %44 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %45 = or i64 %44, %43
  store volatile i64 %45, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %46 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %42
  tail call void @vListInsertEnd(ptr noundef nonnull %46, ptr noundef nonnull %39) #3
  %47 = getelementptr inbounds i8, ptr %0, i64 80
  %48 = load ptr, ptr %47, align 8, !tbaa !16
  %.not36 = icmp eq ptr %48, null
  br i1 %.not36, label %51, label %49

49:                                               ; preds = %38
  tail call void @vPortRaiseBASEPRI()
  br label %50

50:                                               ; preds = %50, %49
  br label %50

51:                                               ; preds = %38
  %52 = load i64, ptr %41, align 8, !tbaa !10
  %53 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !17
  %54 = getelementptr inbounds i8, ptr %53, i64 88
  %55 = load i64, ptr %54, align 8, !tbaa !10
  %56 = icmp ugt i64 %52, %55
  br i1 %56, label %57, label %.thread

57:                                               ; preds = %51
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !18
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !19
  br label %.thread

.thread:                                          ; preds = %29, %36, %57, %51
  %.038 = phi i64 [ 1, %36 ], [ 1, %57 ], [ 1, %51 ], [ 0, %29 ]
  tail call void @vPortExitCritical() #3
  ret i64 %.038
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !14, i64 88}
!11 = !{!"tskTaskControlBlock", !12, i64 0, !13, i64 8, !13, i64 48, !14, i64 88, !12, i64 96, !7, i64 104, !14, i64 136, !14, i64 144, !7, i64 152, !7, i64 156}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!"xLIST_ITEM", !6, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32}
!14 = !{!"long", !7, i64 0}
!15 = !{!14, !14, i64 0}
!16 = !{!11, !12, i64 80}
!17 = !{!12, !12, i64 0}
!18 = !{i64 2148458423}
!19 = !{i64 2148458492}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass