; LLVM IR from mickypaganini/SSI2016-jet-clustering :: spartyjet-4.0.2_mac/External/fastjet-3.0.0/plugins/SISCone/siscone/siscone/pro_9fa6560c (intersectEdd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.siscone::Creference" = type { [3 x i32] }
%"class.siscone::Cvicinity" = type { ptr, double, double, double, double, double, double, i32, %"class.std::vector", %"class.std::vector.0", ptr, %"class.std::vector.5", i32, double, double }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cmomentum, std::allocator<siscone::Cmomentum>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cvicinity_inclusion, std::allocator<siscone::Cvicinity_inclusion>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cvicinity_elm *, std::allocator<siscone::Cvicinity_elm *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.siscone::Cmomentum" = type <{ double, double, double, double, double, double, i32, i32, %"class.siscone::Creference", [4 x i8] }>
%"class.siscone::Cstable_cones" = type { %"class.siscone::Cvicinity", %"class.std::vector", ptr, i32, double, double, %"class.siscone::Cmomentum", ptr, ptr, i32, i32, %"class.siscone::Cmomentum", %"class.std::vector.10", %"class.std::vector.15", double }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl" }
%"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl" = type { %"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<siscone::Cmomentum *, std::allocator<siscone::Cmomentum *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<siscone::Creference, siscone::Creference>, std::allocator<std::pair<siscone::Creference, siscone::Creference>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @_ZN7siscone10CreferenceC1Ev(ptr noundef nonnull align 4 dereferenceable(12)) unnamed_addr #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #3

; Function Attrs: mustprogress uwtable
define dso_local { i64, i32 } @_ZN7siscone13Cstable_cones16circle_intersectEdd(ptr noundef nonnull align 8 dereferenceable(448) %0, double noundef %1, double noundef %2) #4 align 2 {
  %4 = alloca %"class.siscone::Creference", align 4
  %5 = alloca ptr, align 8
  %6 = alloca double, align 8
  %7 = alloca double, align 8
  %8 = alloca i32, align 4
  %9 = alloca double, align 8
  %10 = alloca double, align 8
  %11 = alloca { i64, i32 }, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store double %1, ptr %6, align 8, !tbaa !9
  store double %2, ptr %7, align 8, !tbaa !9
  %12 = load ptr, ptr %5, align 8
  call void @_ZN7siscone10CreferenceC1Ev(ptr noundef nonnull align 4 dereferenceable(12) %4)
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #6
  store i32 0, ptr %8, align 4, !tbaa !11
  br label %13

13:                                               ; preds = %59, %3
  %14 = load i32, ptr %8, align 4, !tbaa !11
  %15 = getelementptr inbounds %"class.siscone::Cvicinity", ptr %12, i32 0, i32 7
  %16 = load i32, ptr %15, align 8, !tbaa !13
  %17 = icmp slt i32 %14, %16
  br i1 %17, label %18, label %62

18:                                               ; preds = %13
  %19 = getelementptr inbounds %"class.siscone::Cvicinity", ptr %12, i32 0, i32 8
  %20 = load i32, ptr %8, align 4, !tbaa !11
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #6
  %23 = getelementptr inbounds %"class.siscone::Cmomentum", ptr %22, i32 0, i32 4
  %24 = load double, ptr %23, align 8, !tbaa !27
  %25 = load double, ptr %6, align 8, !tbaa !9
  %26 = fsub double %24, %25
  store double %26, ptr %9, align 8, !tbaa !9
  %27 = getelementptr inbounds %"class.siscone::Cvicinity", ptr %12, i32 0, i32 8
  %28 = load i32, ptr %8, align 4, !tbaa !11
  %29 = sext i32 %28 to i64
  %30 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %27, i64 noundef %29) #6
  %31 = getelementptr inbounds %"class.siscone::Cmomentum", ptr %30, i32 0, i32 5
  %32 = load double, ptr %31, align 8, !tbaa !30
  %33 = load double, ptr %7, align 8, !tbaa !9
  %34 = fsub double %32, %33
  %35 = call double @llvm.fabs.f64(double %34)
  store double %35, ptr %10, align 8, !tbaa !9
  %36 = load double, ptr %10, align 8, !tbaa !9
  %37 = fcmp ogt double %36, 0x400921FB54442D18
  br i1 %37, label %38, label %41

38:                                               ; preds = %18
  %39 = load double, ptr %10, align 8, !tbaa !9
  %40 = fsub double %39, 0x401921FB54442D18
  store double %40, ptr %10, align 8, !tbaa !9
  br label %41

41:                                               ; preds = %38, %18
  %42 = load double, ptr %9, align 8, !tbaa !9
  %43 = load double, ptr %9, align 8, !tbaa !9
  %44 = load double, ptr %10, align 8, !tbaa !9
  %45 = load double, ptr %10, align 8, !tbaa !9
  %46 = fmul double %44, %45
  %47 = call double @llvm.fmuladd.f64(double %42, double %43, double %46)
  %48 = getelementptr inbounds %"class.siscone::Cstable_cones", ptr %12, i32 0, i32 5
  %49 = load double, ptr %48, align 8, !tbaa !31
  %50 = fcmp olt double %47, %49
  br i1 %50, label %51, label %58

51:                                               ; preds = %41
  %52 = getelementptr inbounds %"class.siscone::Cvicinity", ptr %12, i32 0, i32 8
  %53 = load i32, ptr %8, align 4, !tbaa !11
  %54 = sext i32 %53 to i64
  %55 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %52, i64 noundef %54) #6
  %56 = getelementptr inbounds %"class.siscone::Cmomentum", ptr %55, i32 0, i32 8
  %57 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN7siscone10CreferencepLERKS0_(ptr noundef nonnull align 4 dereferenceable(12) %4, ptr noundef nonnull align 4 dereferenceable(12) %56)
  br label %58

58:                                               ; preds = %51, %41
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr %8, align 4, !tbaa !11
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %8, align 4, !tbaa !11
  br label %13, !llvm.loop !41

62:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #6
  %63 = getelementptr inbounds %"class.siscone::Creference", ptr %4, i32 0, i32 0
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %11, ptr align 4 %63, i64 12, i1 false)
  %64 = load { i64, i32 }, ptr %11, align 8
  ret { i64, i32 } %64
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #5

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #3

declare noundef nonnull align 4 dereferenceable(12) ptr @_ZN7siscone10CreferencepLERKS0_(ptr noundef nonnull align 4 dereferenceable(12), ptr noundef nonnull align 4 dereferenceable(12)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !12, i64 56}
!14 = !{!"_ZTSN7siscone9CvicinityE", !6, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !12, i64 56, !15, i64 64, !19, i64 88, !6, i64 112, !23, i64 120, !12, i64 144, !10, i64 152, !10, i64 160}
!15 = !{!"_ZTSSt6vectorIN7siscone9CmomentumESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIN7siscone19Cvicinity_inclusionESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorIPN7siscone13Cvicinity_elmESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!28, !10, i64 32}
!28 = !{!"_ZTSN7siscone9CmomentumE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !12, i64 48, !12, i64 52, !29, i64 56}
!29 = !{!"_ZTSN7siscone10CreferenceE", !7, i64 0}
!30 = !{!28, !10, i64 40}
!31 = !{!32, !10, i64 216}
!32 = !{!"_ZTSN7siscone13Cstable_conesE", !14, i64 0, !15, i64 168, !6, i64 192, !12, i64 200, !10, i64 208, !10, i64 216, !28, i64 224, !6, i64 296, !6, i64 304, !12, i64 312, !12, i64 316, !28, i64 320, !33, i64 392, !37, i64 416, !10, i64 440}
!33 = !{!"_ZTSSt6vectorIPN7siscone9CmomentumESaIS2_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!"_ZTSSt6vectorISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !38, i64 0}
!38 = !{!"_ZTSSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE12_Vector_implE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!41 = distinct !{!41, !42}
!42 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.siscone::Creference" = type { [3 x i32] }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

declare void @_ZN7siscone10CreferenceC1Ev(ptr noundef nonnull align 4 dereferenceable(12)) unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #2

; Function Attrs: mustprogress uwtable
define dso_local { i64, i32 } @_ZN7siscone13Cstable_cones16circle_intersectEdd(ptr noundef nonnull align 8 dereferenceable(448) %0, double noundef %1, double noundef %2) local_unnamed_addr #3 align 2 {
  %4 = alloca %"class.siscone::Creference", align 8
  call void @_ZN7siscone10CreferenceC1Ev(ptr noundef nonnull align 4 dereferenceable(12) %4)
  %5 = getelementptr inbounds i8, ptr %0, i64 56
  %6 = load i32, ptr %5, align 8, !tbaa !5
  %7 = icmp sgt i32 %6, 0
  br i1 %7, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %3
  %8 = getelementptr inbounds i8, ptr %0, i64 64
  %9 = getelementptr inbounds i8, ptr %0, i64 216
  br label %10

10:                                               ; preds = %.lr.ph, %30
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %30 ]
  %11 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv) #4
  %12 = getelementptr inbounds i8, ptr %11, i64 32
  %13 = load double, ptr %12, align 8, !tbaa !24
  %14 = fsub double %13, %1
  %15 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv) #4
  %16 = getelementptr inbounds i8, ptr %15, i64 40
  %17 = load double, ptr %16, align 8, !tbaa !27
  %18 = fsub double %17, %2
  %19 = call double @llvm.fabs.f64(double %18)
  %20 = fcmp ogt double %19, 0x400921FB54442D18
  %21 = fadd double %19, 0xC01921FB54442D18
  %.013 = select i1 %20, double %21, double %19
  %22 = fmul double %.013, %.013
  %23 = call double @llvm.fmuladd.f64(double %14, double %14, double %22)
  %24 = load double, ptr %9, align 8, !tbaa !28
  %25 = fcmp olt double %23, %24
  br i1 %25, label %26, label %30

26:                                               ; preds = %10
  %27 = call noundef nonnull align 8 dereferenceable(68) ptr @_ZNSt6vectorIN7siscone9CmomentumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %indvars.iv) #4
  %28 = getelementptr inbounds i8, ptr %27, i64 56
  %29 = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN7siscone10CreferencepLERKS0_(ptr noundef nonnull align 4 dereferenceable(12) %4, ptr noundef nonnull align 4 dereferenceable(12) %28)
  br label %30

30:                                               ; preds = %10, %26
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %31 = load i32, ptr %5, align 8, !tbaa !5
  %32 = sext i32 %31 to i64
  %33 = icmp slt i64 %indvars.iv.next, %32
  br i1 %33, label %10, label %._crit_edge, !llvm.loop !38

._crit_edge:                                      ; preds = %30, %3
  %.sroa.0.0.copyload = load i64, ptr %4, align 8
  %.sroa.2.0..sroa_idx = getelementptr inbounds i8, ptr %4, i64 8
  %.sroa.2.0.copyload = load i32, ptr %.sroa.2.0..sroa_idx, align 8
  %.fca.0.insert = insertvalue { i64, i32 } poison, i64 %.sroa.0.0.copyload, 0
  %.fca.1.insert = insertvalue { i64, i32 } %.fca.0.insert, i32 %.sroa.2.0.copyload, 1
  ret { i64, i32 } %.fca.1.insert
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

declare noundef nonnull align 4 dereferenceable(12) ptr @_ZN7siscone10CreferencepLERKS0_(ptr noundef nonnull align 4 dereferenceable(12), ptr noundef nonnull align 4 dereferenceable(12)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 56}
!6 = !{!"_ZTSN7siscone9CvicinityE", !7, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !11, i64 56, !12, i64 64, !16, i64 88, !7, i64 112, !20, i64 120, !11, i64 144, !10, i64 152, !10, i64 160}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"double", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!"_ZTSSt6vectorIN7siscone9CmomentumESaIS1_EE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIN7siscone9CmomentumESaIS1_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!16 = !{!"_ZTSSt6vectorIN7siscone19Cvicinity_inclusionESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIN7siscone19Cvicinity_inclusionESaIS1_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!20 = !{!"_ZTSSt6vectorIPN7siscone13Cvicinity_elmESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIPN7siscone13Cvicinity_elmESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!24 = !{!25, !10, i64 32}
!25 = !{!"_ZTSN7siscone9CmomentumE", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !10, i64 40, !11, i64 48, !11, i64 52, !26, i64 56}
!26 = !{!"_ZTSN7siscone10CreferenceE", !8, i64 0}
!27 = !{!25, !10, i64 40}
!28 = !{!29, !10, i64 216}
!29 = !{!"_ZTSN7siscone13Cstable_conesE", !6, i64 0, !12, i64 168, !7, i64 192, !11, i64 200, !10, i64 208, !10, i64 216, !25, i64 224, !7, i64 296, !7, i64 304, !11, i64 312, !11, i64 316, !25, i64 320, !30, i64 392, !34, i64 416, !10, i64 440}
!30 = !{!"_ZTSSt6vectorIPN7siscone9CmomentumESaIS2_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPN7siscone9CmomentumESaIS2_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!34 = !{!"_ZTSSt6vectorISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseISt4pairIN7siscone10CreferenceES2_ESaIS3_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!38 = distinct !{!38, !39}
!39 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass