; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xEventGroupWaitBits)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.EventGroupDef_t = type { i32, %struct.xLIST }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare i64 @xTaskGetSchedulerState() #2

declare void @vTaskSuspendAll() #2

declare void @vTaskPlaceOnUnorderedEventList(ptr noundef, i32 noundef, i32 noundef) #2

declare i64 @xTaskResumeAll() #2

declare i32 @uxTaskResetEventItemValue() #2

declare void @vPortEnterCritical() #2

declare void @vPortExitCritical() #2

; Function Attrs: nounwind uwtable
define dso_local i32 @xEventGroupWaitBits(ptr noundef %0, i32 noundef %1, i64 noundef %2, i64 noundef %3, i32 noundef %4) #3 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i64 %2, ptr %8, align 8, !tbaa !11
  store i64 %3, ptr %9, align 8, !tbaa !11
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %18, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #4
  store i64 0, ptr %16, align 8, !tbaa !11
  %19 = load ptr, ptr %6, align 8, !tbaa !5
  %20 = icmp eq ptr %19, null
  br i1 %20, label %21, label %23

21:                                               ; preds = %5
  call void @vPortRaiseBASEPRI()
  br label %22

22:                                               ; preds = %22, %21
  br label %22

23:                                               ; preds = %5
  %24 = load i32, ptr %7, align 4, !tbaa !9
  %25 = zext i32 %24 to i64
  %26 = and i64 %25, 4278190080
  %27 = icmp eq i64 %26, 0
  %28 = zext i1 %27 to i32
  %29 = icmp eq i32 %28, 0
  br i1 %29, label %30, label %32

30:                                               ; preds = %23
  call void @vPortRaiseBASEPRI()
  br label %31

31:                                               ; preds = %31, %30
  br label %31

32:                                               ; preds = %23
  %33 = load i32, ptr %7, align 4, !tbaa !9
  %34 = icmp ne i32 %33, 0
  %35 = zext i1 %34 to i32
  %36 = icmp eq i32 %35, 0
  br i1 %36, label %37, label %39

37:                                               ; preds = %32
  call void @vPortRaiseBASEPRI()
  br label %38

38:                                               ; preds = %38, %37
  br label %38

39:                                               ; preds = %32
  %40 = call i64 @xTaskGetSchedulerState()
  %41 = icmp eq i64 %40, 0
  br i1 %41, label %42, label %45

42:                                               ; preds = %39
  %43 = load i32, ptr %10, align 4, !tbaa !9
  %44 = icmp ne i32 %43, 0
  br label %45

45:                                               ; preds = %42, %39
  %46 = phi i1 [ false, %39 ], [ %44, %42 ]
  %47 = xor i1 %46, true
  %48 = zext i1 %47 to i32
  %49 = icmp eq i32 %48, 0
  br i1 %49, label %50, label %52

50:                                               ; preds = %45
  call void @vPortRaiseBASEPRI()
  br label %51

51:                                               ; preds = %51, %50
  br label %51

52:                                               ; preds = %45
  call void @vTaskSuspendAll()
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #4
  %53 = load ptr, ptr %11, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.EventGroupDef_t, ptr %53, i32 0, i32 0
  %55 = load i32, ptr %54, align 8, !tbaa !13
  store i32 %55, ptr %17, align 4, !tbaa !9
  %56 = load i32, ptr %17, align 4, !tbaa !9
  %57 = load i32, ptr %7, align 4, !tbaa !9
  %58 = load i64, ptr %9, align 8, !tbaa !11
  %59 = call i64 @prvTestWaitCondition(i32 noundef %56, i32 noundef %57, i64 noundef %58)
  store i64 %59, ptr %14, align 8, !tbaa !11
  %60 = load i64, ptr %14, align 8, !tbaa !11
  %61 = icmp ne i64 %60, 0
  br i1 %61, label %62, label %75

62:                                               ; preds = %52
  %63 = load i32, ptr %17, align 4, !tbaa !9
  store i32 %63, ptr %12, align 4, !tbaa !9
  store i32 0, ptr %10, align 4, !tbaa !9
  %64 = load i64, ptr %8, align 8, !tbaa !11
  %65 = icmp ne i64 %64, 0
  br i1 %65, label %66, label %73

66:                                               ; preds = %62
  %67 = load i32, ptr %7, align 4, !tbaa !9
  %68 = xor i32 %67, -1
  %69 = load ptr, ptr %11, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.EventGroupDef_t, ptr %69, i32 0, i32 0
  %71 = load i32, ptr %70, align 8, !tbaa !13
  %72 = and i32 %71, %68
  store i32 %72, ptr %70, align 8, !tbaa !13
  br label %74

73:                                               ; preds = %62
  br label %74

74:                                               ; preds = %73, %66
  br label %106

75:                                               ; preds = %52
  %76 = load i32, ptr %10, align 4, !tbaa !9
  %77 = icmp eq i32 %76, 0
  br i1 %77, label %78, label %80

78:                                               ; preds = %75
  %79 = load i32, ptr %17, align 4, !tbaa !9
  store i32 %79, ptr %12, align 4, !tbaa !9
  store i64 1, ptr %16, align 8, !tbaa !11
  br label %105

80:                                               ; preds = %75
  %81 = load i64, ptr %8, align 8, !tbaa !11
  %82 = icmp ne i64 %81, 0
  br i1 %82, label %83, label %88

83:                                               ; preds = %80
  %84 = load i32, ptr %13, align 4, !tbaa !9
  %85 = zext i32 %84 to i64
  %86 = or i64 %85, 16777216
  %87 = trunc i64 %86 to i32
  store i32 %87, ptr %13, align 4, !tbaa !9
  br label %89

88:                                               ; preds = %80
  br label %89

89:                                               ; preds = %88, %83
  %90 = load i64, ptr %9, align 8, !tbaa !11
  %91 = icmp ne i64 %90, 0
  br i1 %91, label %92, label %97

92:                                               ; preds = %89
  %93 = load i32, ptr %13, align 4, !tbaa !9
  %94 = zext i32 %93 to i64
  %95 = or i64 %94, 67108864
  %96 = trunc i64 %95 to i32
  store i32 %96, ptr %13, align 4, !tbaa !9
  br label %98

97:                                               ; preds = %89
  br label %98

98:                                               ; preds = %97, %92
  %99 = load ptr, ptr %11, align 8, !tbaa !5
  %100 = getelementptr inbounds %struct.EventGroupDef_t, ptr %99, i32 0, i32 1
  %101 = load i32, ptr %7, align 4, !tbaa !9
  %102 = load i32, ptr %13, align 4, !tbaa !9
  %103 = or i32 %101, %102
  %104 = load i32, ptr %10, align 4, !tbaa !9
  call void @vTaskPlaceOnUnorderedEventList(ptr noundef %100, i32 noundef %103, i32 noundef %104)
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %105

105:                                              ; preds = %98, %78
  br label %106

106:                                              ; preds = %105, %74
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #4
  %107 = call i64 @xTaskResumeAll()
  store i64 %107, ptr %15, align 8, !tbaa !11
  %108 = load i32, ptr %10, align 4, !tbaa !9
  %109 = icmp ne i32 %108, 0
  br i1 %109, label %110, label %150

110:                                              ; preds = %106
  %111 = load i64, ptr %15, align 8, !tbaa !11
  %112 = icmp eq i64 %111, 0
  br i1 %112, label %113, label %114

113:                                              ; preds = %110
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !17
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !18
  br label %115

114:                                              ; preds = %110
  br label %115

115:                                              ; preds = %114, %113
  %116 = call i32 @uxTaskResetEventItemValue()
  store i32 %116, ptr %12, align 4, !tbaa !9
  %117 = load i32, ptr %12, align 4, !tbaa !9
  %118 = zext i32 %117 to i64
  %119 = and i64 %118, 33554432
  %120 = icmp eq i64 %119, 0
  br i1 %120, label %121, label %144

121:                                              ; preds = %115
  call void @vPortEnterCritical()
  %122 = load ptr, ptr %11, align 8, !tbaa !5
  %123 = getelementptr inbounds %struct.EventGroupDef_t, ptr %122, i32 0, i32 0
  %124 = load i32, ptr %123, align 8, !tbaa !13
  store i32 %124, ptr %12, align 4, !tbaa !9
  %125 = load i32, ptr %12, align 4, !tbaa !9
  %126 = load i32, ptr %7, align 4, !tbaa !9
  %127 = load i64, ptr %9, align 8, !tbaa !11
  %128 = call i64 @prvTestWaitCondition(i32 noundef %125, i32 noundef %126, i64 noundef %127)
  %129 = icmp ne i64 %128, 0
  br i1 %129, label %130, label %142

130:                                              ; preds = %121
  %131 = load i64, ptr %8, align 8, !tbaa !11
  %132 = icmp ne i64 %131, 0
  br i1 %132, label %133, label %140

133:                                              ; preds = %130
  %134 = load i32, ptr %7, align 4, !tbaa !9
  %135 = xor i32 %134, -1
  %136 = load ptr, ptr %11, align 8, !tbaa !5
  %137 = getelementptr inbounds %struct.EventGroupDef_t, ptr %136, i32 0, i32 0
  %138 = load i32, ptr %137, align 8, !tbaa !13
  %139 = and i32 %138, %135
  store i32 %139, ptr %137, align 8, !tbaa !13
  br label %141

140:                                              ; preds = %130
  br label %141

141:                                              ; preds = %140, %133
  br label %143

142:                                              ; preds = %121
  br label %143

143:                                              ; preds = %142, %141
  store i64 1, ptr %16, align 8, !tbaa !11
  call void @vPortExitCritical()
  br label %145

144:                                              ; preds = %115
  br label %145

145:                                              ; preds = %144, %143
  %146 = load i32, ptr %12, align 4, !tbaa !9
  %147 = zext i32 %146 to i64
  %148 = and i64 %147, -4278190081
  %149 = trunc i64 %148 to i32
  store i32 %149, ptr %12, align 4, !tbaa !9
  br label %150

150:                                              ; preds = %145, %106
  %151 = load i64, ptr %16, align 8, !tbaa !11
  %152 = load i64, ptr %16, align 8, !tbaa !11
  %153 = load i32, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  ret i32 %153
}

; Function Attrs: nounwind uwtable
declare hidden i64 @prvTestWaitCondition(i32 noundef, i32 noundef, i64 noundef) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !10, i64 0}
!14 = !{!"EventGroupDef_t", !10, i64 0, !15, i64 8}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{i64 2148147433}
!18 = !{i64 2148147502}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #1

declare void @vTaskSuspendAll() local_unnamed_addr #1

declare void @vTaskPlaceOnUnorderedEventList(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare i64 @xTaskResumeAll() local_unnamed_addr #1

declare i32 @uxTaskResetEventItemValue() local_unnamed_addr #1

declare void @vPortEnterCritical() local_unnamed_addr #1

declare void @vPortExitCritical() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @xEventGroupWaitBits(ptr noundef %0, i32 noundef %1, i64 noundef %2, i64 noundef %3, i32 noundef %4) local_unnamed_addr #2 {
  %6 = icmp eq ptr %0, null
  br i1 %6, label %7, label %9

7:                                                ; preds = %5
  tail call void @vPortRaiseBASEPRI()
  br label %8

8:                                                ; preds = %8, %7
  br label %8

9:                                                ; preds = %5
  %10 = icmp ugt i32 %1, 16777215
  br i1 %10, label %11, label %13

11:                                               ; preds = %9
  tail call void @vPortRaiseBASEPRI()
  br label %12

12:                                               ; preds = %12, %11
  br label %12

13:                                               ; preds = %9
  %.not = icmp eq i32 %1, 0
  br i1 %.not, label %14, label %16

14:                                               ; preds = %13
  tail call void @vPortRaiseBASEPRI()
  br label %15

15:                                               ; preds = %15, %14
  br label %15

16:                                               ; preds = %13
  %17 = tail call i64 @xTaskGetSchedulerState() #3
  %18 = icmp eq i64 %17, 0
  %19 = icmp ne i32 %4, 0
  %20 = and i1 %19, %18
  br i1 %20, label %21, label %23

21:                                               ; preds = %16
  tail call void @vPortRaiseBASEPRI()
  br label %22

22:                                               ; preds = %22, %21
  br label %22

23:                                               ; preds = %16
  tail call void @vTaskSuspendAll() #3
  %24 = load i32, ptr %0, align 8, !tbaa !5
  %25 = tail call i64 @prvTestWaitCondition(i32 noundef %24, i32 noundef %1, i64 noundef %3)
  %.not47 = icmp eq i64 %25, 0
  br i1 %.not47, label %31, label %26

26:                                               ; preds = %23
  %.not50 = icmp eq i64 %2, 0
  br i1 %.not50, label %.thread, label %27

27:                                               ; preds = %26
  %28 = xor i32 %1, -1
  %29 = load i32, ptr %0, align 8, !tbaa !5
  %30 = and i32 %29, %28
  store i32 %30, ptr %0, align 8, !tbaa !5
  br label %.thread

31:                                               ; preds = %23
  %32 = icmp eq i32 %4, 0
  br i1 %32, label %.thread, label %34

.thread:                                          ; preds = %27, %26, %31
  %33 = tail call i64 @xTaskResumeAll() #3
  br label %57

34:                                               ; preds = %31
  %.not48 = icmp eq i64 %2, 0
  %spec.select = select i1 %.not48, i32 0, i32 16777216
  %.not49 = icmp eq i64 %3, 0
  %35 = or disjoint i32 %spec.select, 67108864
  %.143 = select i1 %.not49, i32 %spec.select, i32 %35
  %36 = getelementptr inbounds i8, ptr %0, i64 8
  %37 = or disjoint i32 %.143, %1
  tail call void @vTaskPlaceOnUnorderedEventList(ptr noundef nonnull %36, i32 noundef %37, i32 noundef %4) #3
  %38 = tail call i64 @xTaskResumeAll() #3
  %39 = icmp eq i64 %38, 0
  br i1 %39, label %40, label %41

40:                                               ; preds = %34
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !14
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !15
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !16
  br label %41

41:                                               ; preds = %34, %40
  %42 = tail call i32 @uxTaskResetEventItemValue() #3
  %43 = and i32 %42, 33554432
  %44 = icmp eq i32 %43, 0
  br i1 %44, label %45, label %55

45:                                               ; preds = %41
  tail call void @vPortEnterCritical() #3
  %46 = load i32, ptr %0, align 8, !tbaa !5
  %47 = tail call i64 @prvTestWaitCondition(i32 noundef %46, i32 noundef %1, i64 noundef %3)
  %48 = icmp ne i64 %47, 0
  %49 = icmp ne i64 %2, 0
  %or.cond = and i1 %49, %48
  br i1 %or.cond, label %50, label %54

50:                                               ; preds = %45
  %51 = xor i32 %1, -1
  %52 = load i32, ptr %0, align 8, !tbaa !5
  %53 = and i32 %52, %51
  store i32 %53, ptr %0, align 8, !tbaa !5
  br label %54

54:                                               ; preds = %45, %50
  tail call void @vPortExitCritical() #3
  br label %55

55:                                               ; preds = %41, %54
  %.140 = phi i32 [ %46, %54 ], [ %42, %41 ]
  %56 = and i32 %.140, 16777215
  br label %57

57:                                               ; preds = %.thread, %55
  %.241 = phi i32 [ %56, %55 ], [ %24, %.thread ]
  ret i32 %.241
}

; Function Attrs: nounwind uwtable
declare hidden i64 @prvTestWaitCondition(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #2

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"EventGroupDef_t", !7, i64 0, !10, i64 8}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !12, i64 8, !13, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"any pointer", !8, i64 0}
!13 = !{!"xMINI_LIST_ITEM", !7, i64 0, !12, i64 8, !12, i64 16}
!14 = !{!7, !7, i64 0}
!15 = !{i64 2148147433}
!16 = !{i64 2148147502}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass