; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xTaskGenericNotifyWait)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [32 x i8], i64, i64, [1 x i32], [1 x i8] }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @vPortEnterCritical() #1

declare void @vPortExitCritical() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

; Function Attrs: nounwind uwtable
declare hidden void @prvAddCurrentTaskToDelayedList(i32 noundef, i64 noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i64 @xTaskGenericNotifyWait(i64 noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3, i32 noundef %4) #3 {
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  store i64 %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !11
  store i32 %4, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %12 = load i64, ptr %6, align 8, !tbaa !5
  %13 = icmp ult i64 %12, 1
  %14 = zext i1 %13 to i32
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %16, label %18

16:                                               ; preds = %5
  call void @vPortRaiseBASEPRI()
  br label %17

17:                                               ; preds = %17, %16
  br label %17

18:                                               ; preds = %5
  call void @vPortEnterCritical()
  %19 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %20 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %19, i32 0, i32 9
  %21 = load i64, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds [1 x i8], ptr %20, i64 0, i64 %21
  %23 = load volatile i8, ptr %22, align 1, !tbaa !13
  %24 = zext i8 %23 to i32
  %25 = icmp ne i32 %24, 2
  br i1 %25, label %26, label %45

26:                                               ; preds = %18
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = xor i32 %27, -1
  %29 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %30 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %29, i32 0, i32 8
  %31 = load i64, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds [1 x i32], ptr %30, i64 0, i64 %31
  %33 = load volatile i32, ptr %32, align 4, !tbaa !9
  %34 = and i32 %33, %28
  store volatile i32 %34, ptr %32, align 4, !tbaa !9
  %35 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %36 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %35, i32 0, i32 9
  %37 = load i64, ptr %6, align 8, !tbaa !5
  %38 = getelementptr inbounds [1 x i8], ptr %36, i64 0, i64 %37
  store volatile i8 1, ptr %38, align 1, !tbaa !13
  %39 = load i32, ptr %10, align 4, !tbaa !9
  %40 = icmp ugt i32 %39, 0
  br i1 %40, label %41, label %43

41:                                               ; preds = %26
  %42 = load i32, ptr %10, align 4, !tbaa !9
  call void @prvAddCurrentTaskToDelayedList(i32 noundef %42, i64 noundef 1)
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !14
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !15
  br label %44

43:                                               ; preds = %26
  br label %44

44:                                               ; preds = %43, %41
  br label %46

45:                                               ; preds = %18
  br label %46

46:                                               ; preds = %45, %44
  call void @vPortExitCritical()
  call void @vPortEnterCritical()
  %47 = load ptr, ptr %9, align 8, !tbaa !11
  %48 = icmp ne ptr %47, null
  br i1 %48, label %49, label %56

49:                                               ; preds = %46
  %50 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %51 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %50, i32 0, i32 8
  %52 = load i64, ptr %6, align 8, !tbaa !5
  %53 = getelementptr inbounds [1 x i32], ptr %51, i64 0, i64 %52
  %54 = load volatile i32, ptr %53, align 4, !tbaa !9
  %55 = load ptr, ptr %9, align 8, !tbaa !11
  store i32 %54, ptr %55, align 4, !tbaa !9
  br label %56

56:                                               ; preds = %49, %46
  %57 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %58 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %57, i32 0, i32 9
  %59 = load i64, ptr %6, align 8, !tbaa !5
  %60 = getelementptr inbounds [1 x i8], ptr %58, i64 0, i64 %59
  %61 = load volatile i8, ptr %60, align 1, !tbaa !13
  %62 = zext i8 %61 to i32
  %63 = icmp ne i32 %62, 2
  br i1 %63, label %64, label %65

64:                                               ; preds = %56
  store i64 0, ptr %11, align 8, !tbaa !5
  br label %74

65:                                               ; preds = %56
  %66 = load i32, ptr %8, align 4, !tbaa !9
  %67 = xor i32 %66, -1
  %68 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %69 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %68, i32 0, i32 8
  %70 = load i64, ptr %6, align 8, !tbaa !5
  %71 = getelementptr inbounds [1 x i32], ptr %69, i64 0, i64 %70
  %72 = load volatile i32, ptr %71, align 4, !tbaa !9
  %73 = and i32 %72, %67
  store volatile i32 %73, ptr %71, align 4, !tbaa !9
  store i64 1, ptr %11, align 8, !tbaa !5
  br label %74

74:                                               ; preds = %65, %64
  %75 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !11
  %76 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %75, i32 0, i32 9
  %77 = load i64, ptr %6, align 8, !tbaa !5
  %78 = getelementptr inbounds [1 x i8], ptr %76, i64 0, i64 %77
  store volatile i8 0, ptr %78, align 1, !tbaa !13
  call void @vPortExitCritical()
  %79 = load i64, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  ret i64 %79
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{i64 2148456229}
!15 = !{i64 2148456298}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@pxCurrentTCB = external dso_local global ptr, align 8

declare void @vPortEnterCritical() local_unnamed_addr #0

declare void @vPortExitCritical() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @prvAddCurrentTaskToDelayedList(i32 noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xTaskGenericNotifyWait(i64 noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef writeonly %3, i32 noundef %4) local_unnamed_addr #2 {
  %.not = icmp eq i64 %0, 0
  br i1 %.not, label %8, label %6

6:                                                ; preds = %5
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %5
  tail call void @vPortEnterCritical() #3
  %9 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %10 = getelementptr inbounds i8, ptr %9, i64 156
  %11 = load volatile i8, ptr %10, align 1, !tbaa !9
  %.not16 = icmp eq i8 %11, 2
  br i1 %.not16, label %21, label %12

12:                                               ; preds = %8
  %13 = xor i32 %1, -1
  %14 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %15 = getelementptr inbounds i8, ptr %14, i64 152
  %16 = load volatile i32, ptr %15, align 4, !tbaa !10
  %17 = and i32 %16, %13
  store volatile i32 %17, ptr %15, align 4, !tbaa !10
  %18 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %19 = getelementptr inbounds i8, ptr %18, i64 156
  store volatile i8 1, ptr %19, align 1, !tbaa !9
  %.not17 = icmp eq i32 %4, 0
  br i1 %.not17, label %21, label %20

20:                                               ; preds = %12
  tail call void @prvAddCurrentTaskToDelayedList(i32 noundef %4, i64 noundef 1)
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !10
  tail call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !12
  tail call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !13
  br label %21

21:                                               ; preds = %8, %20, %12
  tail call void @vPortExitCritical() #3
  tail call void @vPortEnterCritical() #3
  %.not18 = icmp eq ptr %3, null
  br i1 %.not18, label %26, label %22

22:                                               ; preds = %21
  %23 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %24 = getelementptr inbounds i8, ptr %23, i64 152
  %25 = load volatile i32, ptr %24, align 4, !tbaa !10
  store i32 %25, ptr %3, align 4, !tbaa !10
  br label %26

26:                                               ; preds = %22, %21
  %27 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %28 = getelementptr inbounds i8, ptr %27, i64 156
  %29 = load volatile i8, ptr %28, align 1, !tbaa !9
  %.not19 = icmp eq i8 %29, 2
  br i1 %.not19, label %30, label %36

30:                                               ; preds = %26
  %31 = xor i32 %2, -1
  %32 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %33 = getelementptr inbounds i8, ptr %32, i64 152
  %34 = load volatile i32, ptr %33, align 4, !tbaa !10
  %35 = and i32 %34, %31
  store volatile i32 %35, ptr %33, align 4, !tbaa !10
  br label %36

36:                                               ; preds = %26, %30
  %.0 = phi i64 [ 1, %30 ], [ 0, %26 ]
  %37 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %38 = getelementptr inbounds i8, ptr %37, i64 156
  store volatile i8 0, ptr %38, align 1, !tbaa !9
  tail call void @vPortExitCritical() #3
  ret i64 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{i64 2148456229}
!13 = !{i64 2148456298}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass