; LLVM IR from alenic/realGA :: src/realga.ll (ZN6RealGA17fillFitnessValuesERSt6vectorI14RealChromosomeSaIS1_EE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.RealChromosome = type <{ %"class.std::vector", float, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl" = type { %"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" }
%"struct.std::_Vector_base<float, std::allocator<float>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealGA = type { ptr, %"class.std::vector", %"class.std::vector", %"class.std::vector.0", %"class.std::vector.0", %class.RealGAOptions, ptr, %"class.std::vector", float, i32, ptr, ptr, ptr, i32, float }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl" = type { %"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" }
%"struct.std::_Vector_base<RealChromosome, std::allocator<RealChromosome>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.RealGAOptions = type { i64, i64, %"class.std::vector", %"class.std::vector", i32, i32, float, i8, i32, i32, float, i32, i32, i32, float, float, float, float }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI14RealChromosomeSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN6RealGA17fillFitnessValuesERSt6vectorI14RealChromosomeSaIS1_EE(ptr noundef nonnull align 8 dereferenceable(296) %0, ptr noundef nonnull align 8 dereferenceable(24) %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %7

7:                                                ; preds = %25, %2
  %8 = load i32, ptr %5, align 4, !tbaa !9
  %9 = sext i32 %8 to i64
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = call noundef i64 @_ZNKSt6vectorI14RealChromosomeSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10) #2
  %12 = icmp ult i64 %9, %11
  br i1 %12, label %14, label %13

13:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  br label %28

14:                                               ; preds = %7
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = load i32, ptr %5, align 4, !tbaa !9
  %17 = sext i32 %16 to i64
  %18 = call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %17) #2
  %19 = getelementptr inbounds %class.RealChromosome, ptr %18, i32 0, i32 1
  %20 = load float, ptr %19, align 8, !tbaa !11
  %21 = getelementptr inbounds %class.RealGA, ptr %6, i32 0, i32 7
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #2
  store float %20, ptr %24, align 4, !tbaa !18
  br label %25

25:                                               ; preds = %14
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = add nsw i32 %26, 1
  store i32 %27, ptr %5, align 4, !tbaa !9
  br label %7, !llvm.loop !19

28:                                               ; preds = %13
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !17, i64 24}
!12 = !{!"_ZTS14RealChromosome", !13, i64 0, !17, i64 24}
!13 = !{!"_ZTSSt6vectorIfSaIfEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"float", !7, i64 0}
!18 = !{!17, !17, i64 0}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI14RealChromosomeSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN6RealGA17fillFitnessValuesERSt6vectorI14RealChromosomeSaIS1_EE(ptr noundef nonnull align 8 dereferenceable(296) %0, ptr noundef nonnull align 8 dereferenceable(24) %1) local_unnamed_addr #0 align 2 {
  %3 = tail call noundef i64 @_ZNKSt6vectorI14RealChromosomeSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #1
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %4 = getelementptr inbounds i8, ptr %0, i64 232
  br label %5

._crit_edge:                                      ; preds = %5, %2
  ret void

5:                                                ; preds = %.lr.ph, %5
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %5 ]
  %6 = tail call noundef nonnull align 8 dereferenceable(28) ptr @_ZNSt6vectorI14RealChromosomeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %indvars.iv) #1
  %7 = getelementptr inbounds i8, ptr %6, i64 24
  %8 = load float, ptr %7, align 8, !tbaa !5
  %9 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv) #1
  store float %8, ptr %9, align 4, !tbaa !15
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %10 = tail call noundef i64 @_ZNKSt6vectorI14RealChromosomeSaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1) #1
  %11 = icmp ugt i64 %10, %indvars.iv.next
  br i1 %11, label %5, label %._crit_edge, !llvm.loop !16
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIfSaIfEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !14, i64 24}
!6 = !{!"_ZTS14RealChromosome", !7, i64 0, !14, i64 24}
!7 = !{!"_ZTSSt6vectorIfSaIfEE", !8, i64 0}
!8 = !{!"_ZTSSt12_Vector_baseIfSaIfEE", !9, i64 0}
!9 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE12_Vector_implE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIfSaIfEE17_Vector_impl_dataE", !11, i64 0, !11, i64 8, !11, i64 16}
!11 = !{!"any pointer", !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C++ TBAA"}
!14 = !{!"float", !12, i64 0}
!15 = !{!14, !14, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass