; LLVM IR from nbosb/simdal :: src/simdal/db_entry (entry_vcml_payload_pci)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.simdal::entry_vcml_payload_pci" = type <{ %"class.simdal::entry_vcml_payload", i32, i32, i32, [4 x i8], i64, i32, i32, i8, [7 x i8] }>
%"class.simdal::entry_vcml_payload" = type { %"class.simdal::entry", i64, i64, i64, i64, i32, %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string" }
%"class.simdal::entry" = type { %"class.simdal::entry_base", ptr }
%"class.simdal::entry_base" = type { ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

@_ZTVN6simdal22entry_vcml_payload_pciE = external dso_local unnamed_addr constant { [5 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6simdal22entry_vcml_payload_pciC2EPNS_8mem_poolIS0_EE(ptr noundef nonnull align 8 dereferenceable(153) %0, ptr noundef %1) unnamed_addr #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEC2EPNS_8mem_poolIS1_EENS2_17payload_type_enumE(ptr noundef nonnull align 8 dereferenceable(120) %5, ptr noundef %6, i32 noundef 2)
  store ptr getelementptr inbounds inrange(-16, 24) ({ [5 x ptr] }, ptr @_ZTVN6simdal22entry_vcml_payload_pciE, i32 0, i32 0, i32 2), ptr %5, align 8, !tbaa !9
  %7 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 1
  store i32 0, ptr %7, align 8, !tbaa !11
  %8 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 2
  store i32 0, ptr %8, align 4, !tbaa !22
  %9 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 3
  store i32 0, ptr %9, align 8, !tbaa !23
  %10 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 5
  store i64 0, ptr %10, align 8, !tbaa !24
  %11 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 6
  store i32 0, ptr %11, align 8, !tbaa !25
  %12 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 7
  store i32 0, ptr %12, align 4, !tbaa !26
  %13 = getelementptr inbounds %"class.simdal::entry_vcml_payload_pci", ptr %5, i32 0, i32 8
  store i8 0, ptr %13, align 8, !tbaa !27
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEC2EPNS_8mem_poolIS1_EENS2_17payload_type_enumE(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, i32 noundef) unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"vtable pointer", !8, i64 0}
!11 = !{!12, !20, i64 120}
!12 = !{!"_ZTSN6simdal22entry_vcml_payload_pciE", !13, i64 0, !20, i64 120, !20, i64 124, !20, i64 128, !16, i64 136, !20, i64 144, !20, i64 148, !21, i64 152}
!13 = !{!"_ZTSN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEE", !14, i64 0, !16, i64 16, !16, i64 24, !16, i64 32, !16, i64 40, !17, i64 48, !18, i64 56, !18, i64 88}
!14 = !{!"_ZTSN6simdal5entryINS_22entry_vcml_payload_pciEEE", !15, i64 0, !6, i64 8}
!15 = !{!"_ZTSN6simdal10entry_baseE"}
!16 = !{!"long", !7, i64 0}
!17 = !{!"_ZTSN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEE17payload_type_enumE", !7, i64 0}
!18 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !19, i64 0, !16, i64 8, !7, i64 16}
!19 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!20 = !{!"int", !7, i64 0}
!21 = !{!"bool", !7, i64 0}
!22 = !{!12, !20, i64 124}
!23 = !{!12, !20, i64 128}
!24 = !{!12, !16, i64 136}
!25 = !{!12, !20, i64 144}
!26 = !{!12, !20, i64 148}
!27 = !{!12, !21, i64 152}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZTVN6simdal22entry_vcml_payload_pciE = external dso_local unnamed_addr constant { [5 x ptr] }, align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6simdal22entry_vcml_payload_pciC2EPNS_8mem_poolIS0_EE(ptr noundef nonnull align 8 dereferenceable(153) %0, ptr noundef %1) unnamed_addr #0 align 2 {
  tail call void @_ZN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEC2EPNS_8mem_poolIS1_EENS2_17payload_type_enumE(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef %1, i32 noundef 2)
  store ptr getelementptr inbounds inrange(-16, 24) (i8, ptr @_ZTVN6simdal22entry_vcml_payload_pciE, i64 16), ptr %0, align 8, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 120
  store i32 0, ptr %3, align 8, !tbaa !8
  %4 = getelementptr inbounds i8, ptr %0, i64 124
  store i32 0, ptr %4, align 4, !tbaa !21
  %5 = getelementptr inbounds i8, ptr %0, i64 128
  store i32 0, ptr %5, align 8, !tbaa !22
  %6 = getelementptr inbounds i8, ptr %0, i64 136
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(17) %6, i8 0, i64 17, i1 false)
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEC2EPNS_8mem_poolIS1_EENS2_17payload_type_enumE(ptr noundef nonnull align 8 dereferenceable(120), ptr noundef, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !19, i64 120}
!9 = !{!"_ZTSN6simdal22entry_vcml_payload_pciE", !10, i64 0, !19, i64 120, !19, i64 124, !19, i64 128, !15, i64 136, !19, i64 144, !19, i64 148, !20, i64 152}
!10 = !{!"_ZTSN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEEE", !11, i64 0, !15, i64 16, !15, i64 24, !15, i64 32, !15, i64 40, !16, i64 48, !17, i64 56, !17, i64 88}
!11 = !{!"_ZTSN6simdal5entryINS_22entry_vcml_payload_pciEEE", !12, i64 0, !13, i64 8}
!12 = !{!"_ZTSN6simdal10entry_baseE"}
!13 = !{!"any pointer", !14, i64 0}
!14 = !{!"omnipotent char", !7, i64 0}
!15 = !{!"long", !14, i64 0}
!16 = !{!"_ZTSN6simdal18entry_vcml_payloadINS_22entry_vcml_payload_pciEE17payload_type_enumE", !14, i64 0}
!17 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !18, i64 0, !15, i64 8, !14, i64 16}
!18 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!19 = !{!"int", !14, i64 0}
!20 = !{!"bool", !14, i64 0}
!21 = !{!9, !19, i64 124}
!22 = !{!9, !19, i64 128}


; Effective O3 passes: InstCombinePass,MemCpyOptPass,SROAPass,TailCallElimPass