; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueueGenericSendFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden i64 @prvCopyDataToQueue(ptr noundef, ptr noundef, i64 noundef) #3

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueGenericSendFromISR(ptr noundef %0, ptr noundef %1, ptr noundef %2, i64 noundef %3) #3 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i8, align 1
  %13 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store i64 %3, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %14, ptr %11, align 8, !tbaa !5
  %15 = load ptr, ptr %11, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %19

17:                                               ; preds = %4
  call void @vPortRaiseBASEPRI()
  br label %18

18:                                               ; preds = %18, %17
  br label %18

19:                                               ; preds = %4
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = icmp eq ptr %20, null
  br i1 %21, label %22, label %27

22:                                               ; preds = %19
  %23 = load ptr, ptr %11, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.QueueDefinition, ptr %23, i32 0, i32 7
  %25 = load i64, ptr %24, align 8, !tbaa !11
  %26 = icmp ne i64 %25, 0
  br label %27

27:                                               ; preds = %22, %19
  %28 = phi i1 [ false, %19 ], [ %26, %22 ]
  %29 = xor i1 %28, true
  %30 = zext i1 %29 to i32
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %34

32:                                               ; preds = %27
  call void @vPortRaiseBASEPRI()
  br label %33

33:                                               ; preds = %33, %32
  br label %33

34:                                               ; preds = %27
  %35 = load i64, ptr %8, align 8, !tbaa !9
  %36 = icmp eq i64 %35, 2
  br i1 %36, label %37, label %42

37:                                               ; preds = %34
  %38 = load ptr, ptr %11, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.QueueDefinition, ptr %38, i32 0, i32 6
  %40 = load i64, ptr %39, align 8, !tbaa !16
  %41 = icmp ne i64 %40, 1
  br label %42

42:                                               ; preds = %37, %34
  %43 = phi i1 [ false, %34 ], [ %41, %37 ]
  %44 = xor i1 %43, true
  %45 = zext i1 %44 to i32
  %46 = icmp eq i32 %45, 0
  br i1 %46, label %47, label %49

47:                                               ; preds = %42
  call void @vPortRaiseBASEPRI()
  br label %48

48:                                               ; preds = %48, %47
  br label %48

49:                                               ; preds = %42
  call void @vPortValidateInterruptPriority()
  %50 = call i32 @ulPortRaiseBASEPRI()
  %51 = zext i32 %50 to i64
  store i64 %51, ptr %10, align 8, !tbaa !9
  %52 = load ptr, ptr %11, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.QueueDefinition, ptr %52, i32 0, i32 5
  %54 = load volatile i64, ptr %53, align 8, !tbaa !17
  %55 = load ptr, ptr %11, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.QueueDefinition, ptr %55, i32 0, i32 6
  %57 = load i64, ptr %56, align 8, !tbaa !16
  %58 = icmp ult i64 %54, %57
  br i1 %58, label %62, label %59

59:                                               ; preds = %49
  %60 = load i64, ptr %8, align 8, !tbaa !9
  %61 = icmp eq i64 %60, 2
  br i1 %61, label %62, label %118

62:                                               ; preds = %59, %49
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #4
  %63 = load ptr, ptr %11, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.QueueDefinition, ptr %63, i32 0, i32 9
  %65 = load volatile i8, ptr %64, align 1, !tbaa !18
  store i8 %65, ptr %12, align 1, !tbaa !19
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %66 = load ptr, ptr %11, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.QueueDefinition, ptr %66, i32 0, i32 5
  %68 = load volatile i64, ptr %67, align 8, !tbaa !17
  store i64 %68, ptr %13, align 8, !tbaa !9
  %69 = load ptr, ptr %11, align 8, !tbaa !5
  %70 = load ptr, ptr %6, align 8, !tbaa !5
  %71 = load i64, ptr %8, align 8, !tbaa !9
  %72 = call i64 @prvCopyDataToQueue(ptr noundef %69, ptr noundef %70, i64 noundef %71)
  %73 = load i8, ptr %12, align 1, !tbaa !19
  %74 = sext i8 %73 to i32
  %75 = icmp eq i32 %74, -1
  br i1 %75, label %76, label %102

76:                                               ; preds = %62
  %77 = load ptr, ptr %11, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.QueueDefinition, ptr %77, i32 0, i32 4
  %79 = getelementptr inbounds %struct.xLIST, ptr %78, i32 0, i32 0
  %80 = load volatile i64, ptr %79, align 8, !tbaa !20
  %81 = icmp eq i64 %80, 0
  %82 = zext i1 %81 to i64
  %83 = select i1 %81, i64 1, i64 0
  %84 = icmp eq i64 %83, 0
  br i1 %84, label %85, label %99

85:                                               ; preds = %76
  %86 = load ptr, ptr %11, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.QueueDefinition, ptr %86, i32 0, i32 4
  %88 = call i64 @xTaskRemoveFromEventList(ptr noundef %87)
  %89 = icmp ne i64 %88, 0
  br i1 %89, label %90, label %97

90:                                               ; preds = %85
  %91 = load ptr, ptr %7, align 8, !tbaa !5
  %92 = icmp ne ptr %91, null
  br i1 %92, label %93, label %95

93:                                               ; preds = %90
  %94 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 1, ptr %94, align 8, !tbaa !9
  br label %96

95:                                               ; preds = %90
  br label %96

96:                                               ; preds = %95, %93
  br label %98

97:                                               ; preds = %85
  br label %98

98:                                               ; preds = %97, %96
  br label %100

99:                                               ; preds = %76
  br label %100

100:                                              ; preds = %99, %98
  %101 = load i64, ptr %13, align 8, !tbaa !9
  br label %117

102:                                              ; preds = %62
  %103 = load i8, ptr %12, align 1, !tbaa !19
  %104 = sext i8 %103 to i32
  %105 = icmp ne i32 %104, 127
  %106 = zext i1 %105 to i32
  %107 = icmp eq i32 %106, 0
  br i1 %107, label %108, label %110

108:                                              ; preds = %102
  call void @vPortRaiseBASEPRI()
  br label %109

109:                                              ; preds = %109, %108
  br label %109

110:                                              ; preds = %102
  %111 = load i8, ptr %12, align 1, !tbaa !19
  %112 = sext i8 %111 to i32
  %113 = add nsw i32 %112, 1
  %114 = trunc i32 %113 to i8
  %115 = load ptr, ptr %11, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.QueueDefinition, ptr %115, i32 0, i32 9
  store volatile i8 %114, ptr %116, align 1, !tbaa !18
  br label %117

117:                                              ; preds = %110, %100
  store i64 1, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #4
  br label %119

118:                                              ; preds = %59
  store i64 0, ptr %9, align 8, !tbaa !9
  br label %119

119:                                              ; preds = %118, %117
  %120 = load i64, ptr %10, align 8, !tbaa !9
  %121 = trunc i64 %120 to i32
  call void @vPortSetBASEPRI(i32 noundef %121)
  %122 = load i64, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  ret i64 %122
}

declare void @vPortValidateInterruptPriority() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 128}
!12 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !13, i64 32, !13, i64 72, !10, i64 112, !10, i64 120, !10, i64 128, !7, i64 136, !7, i64 137}
!13 = !{!"xLIST", !10, i64 0, !6, i64 8, !14, i64 16}
!14 = !{!"xMINI_LIST_ITEM", !15, i64 0, !6, i64 8, !6, i64 16}
!15 = !{!"int", !7, i64 0}
!16 = !{!12, !10, i64 120}
!17 = !{!12, !10, i64 112}
!18 = !{!12, !7, i64 137}
!19 = !{!7, !7, i64 0}
!20 = !{!12, !10, i64 72}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i64 @prvCopyDataToQueue(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xQueueGenericSendFromISR(ptr noundef %0, ptr noundef %1, ptr noundef writeonly %2, i64 noundef %3) local_unnamed_addr #2 {
  %5 = icmp eq ptr %0, null
  br i1 %5, label %6, label %8

6:                                                ; preds = %4
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %4
  %9 = icmp eq ptr %1, null
  br i1 %9, label %10, label %.critedge

10:                                               ; preds = %8
  %11 = getelementptr inbounds i8, ptr %0, i64 128
  %12 = load i64, ptr %11, align 8, !tbaa !5
  %.not = icmp eq i64 %12, 0
  br i1 %.not, label %.critedge, label %13

13:                                               ; preds = %10
  tail call void @vPortRaiseBASEPRI()
  br label %14

14:                                               ; preds = %14, %13
  br label %14

.critedge:                                        ; preds = %8, %10
  %15 = icmp eq i64 %3, 2
  br i1 %15, label %16, label %.critedge32

16:                                               ; preds = %.critedge
  %17 = getelementptr inbounds i8, ptr %0, i64 120
  %18 = load i64, ptr %17, align 8, !tbaa !14
  %.not33 = icmp eq i64 %18, 1
  br i1 %.not33, label %.critedge32, label %19

19:                                               ; preds = %16
  tail call void @vPortRaiseBASEPRI()
  br label %20

20:                                               ; preds = %20, %19
  br label %20

.critedge32:                                      ; preds = %.critedge, %16
  tail call void @vPortValidateInterruptPriority() #3
  %21 = tail call i32 @ulPortRaiseBASEPRI()
  %22 = getelementptr inbounds i8, ptr %0, i64 112
  %23 = load volatile i64, ptr %22, align 8, !tbaa !15
  %24 = getelementptr inbounds i8, ptr %0, i64 120
  %25 = load i64, ptr %24, align 8, !tbaa !14
  %26 = icmp ult i64 %23, %25
  %or.cond = or i1 %15, %26
  br i1 %or.cond, label %27, label %44

27:                                               ; preds = %.critedge32
  %28 = getelementptr inbounds i8, ptr %0, i64 137
  %29 = load volatile i8, ptr %28, align 1, !tbaa !16
  %30 = load volatile i64, ptr %22, align 8, !tbaa !15
  %31 = tail call i64 @prvCopyDataToQueue(ptr noundef nonnull %0, ptr noundef %1, i64 noundef %3)
  switch i8 %29, label %42 [
    i8 -1, label %32
    i8 127, label %40
  ]

32:                                               ; preds = %27
  %33 = getelementptr inbounds i8, ptr %0, i64 72
  %34 = load volatile i64, ptr %33, align 8, !tbaa !17
  %.not30 = icmp eq i64 %34, 0
  br i1 %.not30, label %44, label %35

35:                                               ; preds = %32
  %36 = tail call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %33) #3
  %37 = icmp ne i64 %36, 0
  %38 = icmp ne ptr %2, null
  %or.cond3 = and i1 %38, %37
  br i1 %or.cond3, label %39, label %44

39:                                               ; preds = %35
  store i64 1, ptr %2, align 8, !tbaa !18
  br label %44

40:                                               ; preds = %27
  tail call void @vPortRaiseBASEPRI()
  br label %41

41:                                               ; preds = %41, %40
  br label %41

42:                                               ; preds = %27
  %43 = add nuw i8 %29, 1
  store volatile i8 %43, ptr %28, align 1, !tbaa !16
  br label %44

44:                                               ; preds = %.critedge32, %42, %32, %39, %35
  %.0 = phi i64 [ 1, %35 ], [ 1, %39 ], [ 1, %32 ], [ 1, %42 ], [ 0, %.critedge32 ]
  tail call void @vPortSetBASEPRI(i32 noundef %21)
  ret i64 %.0
}

declare void @vPortValidateInterruptPriority() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 128}
!6 = !{!"QueueDefinition", !7, i64 0, !7, i64 8, !8, i64 16, !10, i64 32, !10, i64 72, !11, i64 112, !11, i64 120, !11, i64 128, !8, i64 136, !8, i64 137}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"xLIST", !11, i64 0, !7, i64 8, !12, i64 16}
!11 = !{!"long", !8, i64 0}
!12 = !{!"xMINI_LIST_ITEM", !13, i64 0, !7, i64 8, !7, i64 16}
!13 = !{!"int", !8, i64 0}
!14 = !{!6, !11, i64 120}
!15 = !{!6, !11, i64 112}
!16 = !{!6, !8, i64 137}
!17 = !{!6, !11, i64 72}
!18 = !{!11, !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass