; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xStreamBufferReceiveFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.StreamBufferDef_t = type { i64, i64, i64, i64, ptr, ptr, ptr, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden i64 @prvBytesInBuffer(ptr noundef) #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

declare i64 @xTaskGenericNotifyFromISR(ptr noundef, i64 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i64 @prvReadMessageFromBuffer(ptr noundef, ptr noundef, i64 noundef, i64 noundef, i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xStreamBufferReceiveFromISR(ptr noundef %0, ptr noundef %1, i64 noundef %2, ptr noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i64 %2, ptr %7, align 8, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %14, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  store i64 0, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %19

17:                                               ; preds = %4
  call void @vPortRaiseBASEPRI()
  br label %18

18:                                               ; preds = %18, %17
  br label %18

19:                                               ; preds = %4
  %20 = load ptr, ptr %9, align 8, !tbaa !5
  %21 = icmp eq ptr %20, null
  br i1 %21, label %22, label %24

22:                                               ; preds = %19
  call void @vPortRaiseBASEPRI()
  br label %23

23:                                               ; preds = %23, %22
  br label %23

24:                                               ; preds = %19
  %25 = load ptr, ptr %9, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %25, i32 0, i32 7
  %27 = load i8, ptr %26, align 8, !tbaa !11
  %28 = zext i8 %27 to i32
  %29 = and i32 %28, 1
  %30 = icmp ne i32 %29, 0
  br i1 %30, label %31, label %32

31:                                               ; preds = %24
  store i64 8, ptr %12, align 8, !tbaa !9
  br label %33

32:                                               ; preds = %24
  store i64 0, ptr %12, align 8, !tbaa !9
  br label %33

33:                                               ; preds = %32, %31
  %34 = load ptr, ptr %9, align 8, !tbaa !5
  %35 = call i64 @prvBytesInBuffer(ptr noundef %34)
  store i64 %35, ptr %11, align 8, !tbaa !9
  %36 = load i64, ptr %11, align 8, !tbaa !9
  %37 = load i64, ptr %12, align 8, !tbaa !9
  %38 = icmp ugt i64 %36, %37
  br i1 %38, label %39, label %68

39:                                               ; preds = %33
  %40 = load ptr, ptr %9, align 8, !tbaa !5
  %41 = load ptr, ptr %6, align 8, !tbaa !5
  %42 = load i64, ptr %7, align 8, !tbaa !9
  %43 = load i64, ptr %11, align 8, !tbaa !9
  %44 = load i64, ptr %12, align 8, !tbaa !9
  %45 = call i64 @prvReadMessageFromBuffer(ptr noundef %40, ptr noundef %41, i64 noundef %42, i64 noundef %43, i64 noundef %44)
  store i64 %45, ptr %10, align 8, !tbaa !9
  %46 = load i64, ptr %10, align 8, !tbaa !9
  %47 = icmp ne i64 %46, 0
  br i1 %47, label %48, label %66

48:                                               ; preds = %39
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %49 = call i32 @ulPortRaiseBASEPRI()
  %50 = zext i32 %49 to i64
  store i64 %50, ptr %13, align 8, !tbaa !9
  %51 = load ptr, ptr %9, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %51, i32 0, i32 5
  %53 = load volatile ptr, ptr %52, align 8, !tbaa !13
  %54 = icmp ne ptr %53, null
  br i1 %54, label %55, label %63

55:                                               ; preds = %48
  %56 = load ptr, ptr %9, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %56, i32 0, i32 5
  %58 = load volatile ptr, ptr %57, align 8, !tbaa !13
  %59 = load ptr, ptr %8, align 8, !tbaa !5
  %60 = call i64 @xTaskGenericNotifyFromISR(ptr noundef %58, i64 noundef 0, i32 noundef 0, i32 noundef 0, ptr noundef null, ptr noundef %59)
  %61 = load ptr, ptr %9, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %61, i32 0, i32 5
  store volatile ptr null, ptr %62, align 8, !tbaa !13
  br label %63

63:                                               ; preds = %55, %48
  %64 = load i64, ptr %13, align 8, !tbaa !9
  %65 = trunc i64 %64 to i32
  call void @vPortSetBASEPRI(i32 noundef %65)
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %67

66:                                               ; preds = %39
  br label %67

67:                                               ; preds = %66, %63
  br label %69

68:                                               ; preds = %33
  br label %69

69:                                               ; preds = %68, %67
  %70 = load i64, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  ret i64 %70
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !7, i64 56}
!12 = !{!"StreamBufferDef_t", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !7, i64 56}
!13 = !{!12, !6, i64 40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i64 @prvBytesInBuffer(ptr noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskGenericNotifyFromISR(ptr noundef, i64 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i64 @prvReadMessageFromBuffer(ptr noundef, ptr noundef, i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i64 @xStreamBufferReceiveFromISR(ptr noundef %0, ptr noundef %1, i64 noundef %2, ptr noundef %3) local_unnamed_addr #1 {
  %5 = icmp eq ptr %1, null
  br i1 %5, label %6, label %8

6:                                                ; preds = %4
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %4
  %9 = icmp eq ptr %0, null
  br i1 %9, label %10, label %12

10:                                               ; preds = %8
  tail call void @vPortRaiseBASEPRI()
  br label %11

11:                                               ; preds = %11, %10
  br label %11

12:                                               ; preds = %8
  %13 = getelementptr inbounds i8, ptr %0, i64 56
  %14 = load i8, ptr %13, align 8, !tbaa !5
  %15 = shl i8 %14, 3
  %16 = and i8 %15, 8
  %. = zext nneg i8 %16 to i64
  %17 = tail call i64 @prvBytesInBuffer(ptr noundef nonnull %0)
  %18 = icmp ugt i64 %17, %.
  br i1 %18, label %19, label %29

19:                                               ; preds = %12
  %20 = tail call i64 @prvReadMessageFromBuffer(ptr noundef nonnull %0, ptr noundef nonnull %1, i64 noundef %2, i64 noundef %17, i64 noundef %.)
  %.not23 = icmp eq i64 %20, 0
  br i1 %.not23, label %29, label %21

21:                                               ; preds = %19
  %22 = tail call i32 @ulPortRaiseBASEPRI()
  %23 = getelementptr inbounds i8, ptr %0, i64 40
  %24 = load volatile ptr, ptr %23, align 8, !tbaa !11
  %.not24 = icmp eq ptr %24, null
  br i1 %.not24, label %28, label %25

25:                                               ; preds = %21
  %26 = load volatile ptr, ptr %23, align 8, !tbaa !11
  %27 = tail call i64 @xTaskGenericNotifyFromISR(ptr noundef %26, i64 noundef 0, i32 noundef 0, i32 noundef 0, ptr noundef null, ptr noundef %3) #3
  store volatile ptr null, ptr %23, align 8, !tbaa !11
  br label %28

28:                                               ; preds = %25, %21
  tail call void @vPortSetBASEPRI(i32 noundef %22)
  br label %29

29:                                               ; preds = %12, %28, %19
  %.0 = phi i64 [ %20, %28 ], [ 0, %19 ], [ 0, %12 ]
  ret i64 %.0
}

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 56}
!6 = !{!"StreamBufferDef_t", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !8, i64 56}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !10, i64 40}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass