; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xQueueGenericSend)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }
%struct.QueueDefinition = type { ptr, ptr, %union.anon, %struct.xLIST, %struct.xLIST, i64, i64, i64, i8, i8 }
%union.anon = type { %struct.QueuePointers }
%struct.QueuePointers = type { ptr, ptr }
%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

declare void @vPortEnterCritical() #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) #2

declare void @vPortExitCritical() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i64 @xQueueGenericSend(ptr noundef %0, ptr noundef %1, i32 noundef %2, i64 noundef %3) #3 {
  %5 = alloca i64, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca %struct.xTIME_OUT, align 8
  %13 = alloca ptr, align 8
  %14 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i64 %3, ptr %9, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  store i64 0, ptr %10, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %15, ptr %13, align 8, !tbaa !5
  %16 = load ptr, ptr %13, align 8, !tbaa !5
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %20

18:                                               ; preds = %4
  call void @vPortRaiseBASEPRI()
  br label %19

19:                                               ; preds = %19, %18
  br label %19

20:                                               ; preds = %4
  %21 = load ptr, ptr %7, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %23, label %28

23:                                               ; preds = %20
  %24 = load ptr, ptr %13, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.QueueDefinition, ptr %24, i32 0, i32 7
  %26 = load i64, ptr %25, align 8, !tbaa !13
  %27 = icmp ne i64 %26, 0
  br label %28

28:                                               ; preds = %23, %20
  %29 = phi i1 [ false, %20 ], [ %27, %23 ]
  %30 = xor i1 %29, true
  %31 = zext i1 %30 to i32
  %32 = icmp eq i32 %31, 0
  br i1 %32, label %33, label %35

33:                                               ; preds = %28
  call void @vPortRaiseBASEPRI()
  br label %34

34:                                               ; preds = %34, %33
  br label %34

35:                                               ; preds = %28
  %36 = load i64, ptr %9, align 8, !tbaa !11
  %37 = icmp eq i64 %36, 2
  br i1 %37, label %38, label %43

38:                                               ; preds = %35
  %39 = load ptr, ptr %13, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.QueueDefinition, ptr %39, i32 0, i32 6
  %41 = load i64, ptr %40, align 8, !tbaa !17
  %42 = icmp ne i64 %41, 1
  br label %43

43:                                               ; preds = %38, %35
  %44 = phi i1 [ false, %35 ], [ %42, %38 ]
  %45 = xor i1 %44, true
  %46 = zext i1 %45 to i32
  %47 = icmp eq i32 %46, 0
  br i1 %47, label %48, label %50

48:                                               ; preds = %43
  call void @vPortRaiseBASEPRI()
  br label %49

49:                                               ; preds = %49, %48
  br label %49

50:                                               ; preds = %43
  %51 = call i64 @xTaskGetSchedulerState()
  %52 = icmp eq i64 %51, 0
  br i1 %52, label %53, label %56

53:                                               ; preds = %50
  %54 = load i32, ptr %8, align 4, !tbaa !9
  %55 = icmp ne i32 %54, 0
  br label %56

56:                                               ; preds = %53, %50
  %57 = phi i1 [ false, %50 ], [ %55, %53 ]
  %58 = xor i1 %57, true
  %59 = zext i1 %58 to i32
  %60 = icmp eq i32 %59, 0
  br i1 %60, label %61, label %63

61:                                               ; preds = %56
  call void @vPortRaiseBASEPRI()
  br label %62

62:                                               ; preds = %62, %61
  br label %62

63:                                               ; preds = %56
  br label %64

64:                                               ; preds = %155, %63
  call void @vPortEnterCritical()
  %65 = load ptr, ptr %13, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.QueueDefinition, ptr %65, i32 0, i32 5
  %67 = load volatile i64, ptr %66, align 8, !tbaa !18
  %68 = load ptr, ptr %13, align 8, !tbaa !5
  %69 = getelementptr inbounds %struct.QueueDefinition, ptr %68, i32 0, i32 6
  %70 = load i64, ptr %69, align 8, !tbaa !17
  %71 = icmp ult i64 %67, %70
  br i1 %71, label %75, label %72

72:                                               ; preds = %64
  %73 = load i64, ptr %9, align 8, !tbaa !11
  %74 = icmp eq i64 %73, 2
  br i1 %74, label %75, label %103

75:                                               ; preds = %72, %64
  %76 = load ptr, ptr %13, align 8, !tbaa !5
  %77 = load ptr, ptr %7, align 8, !tbaa !5
  %78 = load i64, ptr %9, align 8, !tbaa !11
  %79 = call i64 @prvCopyDataToQueue(ptr noundef %76, ptr noundef %77, i64 noundef %78)
  store i64 %79, ptr %11, align 8, !tbaa !11
  %80 = load ptr, ptr %13, align 8, !tbaa !5
  %81 = getelementptr inbounds %struct.QueueDefinition, ptr %80, i32 0, i32 4
  %82 = getelementptr inbounds %struct.xLIST, ptr %81, i32 0, i32 0
  %83 = load volatile i64, ptr %82, align 8, !tbaa !19
  %84 = icmp eq i64 %83, 0
  %85 = zext i1 %84 to i64
  %86 = select i1 %84, i64 1, i64 0
  %87 = icmp eq i64 %86, 0
  br i1 %87, label %88, label %96

88:                                               ; preds = %75
  %89 = load ptr, ptr %13, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.QueueDefinition, ptr %89, i32 0, i32 4
  %91 = call i64 @xTaskRemoveFromEventList(ptr noundef %90)
  %92 = icmp ne i64 %91, 0
  br i1 %92, label %93, label %94

93:                                               ; preds = %88
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !21
  br label %95

94:                                               ; preds = %88
  br label %95

95:                                               ; preds = %94, %93
  br label %102

96:                                               ; preds = %75
  %97 = load i64, ptr %11, align 8, !tbaa !11
  %98 = icmp ne i64 %97, 0
  br i1 %98, label %99, label %100

99:                                               ; preds = %96
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !22
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !23
  br label %101

100:                                              ; preds = %96
  br label %101

101:                                              ; preds = %100, %99
  br label %102

102:                                              ; preds = %101, %95
  call void @vPortExitCritical()
  store i64 1, ptr %5, align 8
  store i32 1, ptr %14, align 4
  br label %156

103:                                              ; preds = %72
  %104 = load i32, ptr %8, align 4, !tbaa !9
  %105 = icmp eq i32 %104, 0
  br i1 %105, label %106, label %107

106:                                              ; preds = %103
  call void @vPortExitCritical()
  store i64 0, ptr %5, align 8
  store i32 1, ptr %14, align 4
  br label %156

107:                                              ; preds = %103
  %108 = load i64, ptr %10, align 8, !tbaa !11
  %109 = icmp eq i64 %108, 0
  br i1 %109, label %110, label %111

110:                                              ; preds = %107
  call void @vTaskInternalSetTimeOutState(ptr noundef %12)
  store i64 1, ptr %10, align 8, !tbaa !11
  br label %112

111:                                              ; preds = %107
  br label %112

112:                                              ; preds = %111, %110
  br label %113

113:                                              ; preds = %112
  br label %114

114:                                              ; preds = %113
  call void @vPortExitCritical()
  call void @vTaskSuspendAll()
  call void @vPortEnterCritical()
  %115 = load ptr, ptr %13, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.QueueDefinition, ptr %115, i32 0, i32 8
  %117 = load volatile i8, ptr %116, align 8, !tbaa !24
  %118 = sext i8 %117 to i32
  %119 = icmp eq i32 %118, -1
  br i1 %119, label %120, label %123

120:                                              ; preds = %114
  %121 = load ptr, ptr %13, align 8, !tbaa !5
  %122 = getelementptr inbounds %struct.QueueDefinition, ptr %121, i32 0, i32 8
  store volatile i8 0, ptr %122, align 8, !tbaa !24
  br label %123

123:                                              ; preds = %120, %114
  %124 = load ptr, ptr %13, align 8, !tbaa !5
  %125 = getelementptr inbounds %struct.QueueDefinition, ptr %124, i32 0, i32 9
  %126 = load volatile i8, ptr %125, align 1, !tbaa !25
  %127 = sext i8 %126 to i32
  %128 = icmp eq i32 %127, -1
  br i1 %128, label %129, label %132

129:                                              ; preds = %123
  %130 = load ptr, ptr %13, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.QueueDefinition, ptr %130, i32 0, i32 9
  store volatile i8 0, ptr %131, align 1, !tbaa !25
  br label %132

132:                                              ; preds = %129, %123
  call void @vPortExitCritical()
  %133 = call i64 @xTaskCheckForTimeOut(ptr noundef %12, ptr noundef %8)
  %134 = icmp eq i64 %133, 0
  br i1 %134, label %135, label %152

135:                                              ; preds = %132
  %136 = load ptr, ptr %13, align 8, !tbaa !5
  %137 = call i64 @prvIsQueueFull(ptr noundef %136)
  %138 = icmp ne i64 %137, 0
  br i1 %138, label %139, label %148

139:                                              ; preds = %135
  %140 = load ptr, ptr %13, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.QueueDefinition, ptr %140, i32 0, i32 3
  %142 = load i32, ptr %8, align 4, !tbaa !9
  call void @vTaskPlaceOnEventList(ptr noundef %141, i32 noundef %142)
  %143 = load ptr, ptr %13, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %143)
  %144 = call i64 @xTaskResumeAll()
  %145 = icmp eq i64 %144, 0
  br i1 %145, label %146, label %147

146:                                              ; preds = %139
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !9
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !26
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !27
  br label %147

147:                                              ; preds = %146, %139
  br label %151

148:                                              ; preds = %135
  %149 = load ptr, ptr %13, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %149)
  %150 = call i64 @xTaskResumeAll()
  br label %151

151:                                              ; preds = %148, %147
  br label %155

152:                                              ; preds = %132
  %153 = load ptr, ptr %13, align 8, !tbaa !5
  call void @prvUnlockQueue(ptr noundef %153)
  %154 = call i64 @xTaskResumeAll()
  store i64 0, ptr %5, align 8
  store i32 1, ptr %14, align 4
  br label %156

155:                                              ; preds = %151
  br label %64

156:                                              ; preds = %152, %106, %102
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  %157 = load i64, ptr %5, align 8
  ret i64 %157
}

declare i64 @xTaskGetSchedulerState() #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvCopyDataToQueue(ptr noundef, ptr noundef, i64 noundef) #3

declare void @vTaskInternalSetTimeOutState(ptr noundef) #2

declare void @vTaskSuspendAll() #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueFull(ptr noundef) #3

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) #3

declare i64 @xTaskResumeAll() #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !12, i64 128}
!14 = !{!"QueueDefinition", !6, i64 0, !6, i64 8, !7, i64 16, !15, i64 32, !15, i64 72, !12, i64 112, !12, i64 120, !12, i64 128, !7, i64 136, !7, i64 137}
!15 = !{!"xLIST", !12, i64 0, !6, i64 8, !16, i64 16}
!16 = !{!"xMINI_LIST_ITEM", !10, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!14, !12, i64 120}
!18 = !{!14, !12, i64 112}
!19 = !{!14, !12, i64 72}
!20 = !{i64 2148260229}
!21 = !{i64 2148260298}
!22 = !{i64 2148260869}
!23 = !{i64 2148260938}
!24 = !{!14, !7, i64 136}
!25 = !{!14, !7, i64 137}
!26 = !{i64 2148262618}
!27 = !{i64 2148262687}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xTIME_OUT = type { i64, i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortEnterCritical() local_unnamed_addr #2

declare i64 @xTaskRemoveFromEventList(ptr noundef) local_unnamed_addr #2

declare void @vPortExitCritical() local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local range(i64 0, 2) i64 @xQueueGenericSend(ptr noundef %0, ptr noundef %1, i32 noundef %2, i64 noundef %3) local_unnamed_addr #3 {
  %5 = alloca i32, align 4
  %6 = alloca %struct.xTIME_OUT, align 8
  store i32 %2, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #4
  %7 = icmp eq ptr %0, null
  br i1 %7, label %8, label %10

8:                                                ; preds = %4
  tail call void @vPortRaiseBASEPRI()
  br label %9

9:                                                ; preds = %9, %8
  br label %9

10:                                               ; preds = %4
  %11 = icmp eq ptr %1, null
  br i1 %11, label %12, label %.critedge

12:                                               ; preds = %10
  %13 = getelementptr inbounds i8, ptr %0, i64 128
  %14 = load i64, ptr %13, align 8, !tbaa !9
  %.not33 = icmp eq i64 %14, 0
  br i1 %.not33, label %.critedge, label %15

15:                                               ; preds = %12
  tail call void @vPortRaiseBASEPRI()
  br label %16

16:                                               ; preds = %16, %15
  br label %16

.critedge:                                        ; preds = %10, %12
  %17 = icmp eq i64 %3, 2
  br i1 %17, label %18, label %.critedge32

18:                                               ; preds = %.critedge
  %19 = getelementptr inbounds i8, ptr %0, i64 120
  %20 = load i64, ptr %19, align 8, !tbaa !15
  %.not34 = icmp eq i64 %20, 1
  br i1 %.not34, label %.critedge32, label %21

21:                                               ; preds = %18
  tail call void @vPortRaiseBASEPRI()
  br label %22

22:                                               ; preds = %22, %21
  br label %22

.critedge32:                                      ; preds = %.critedge, %18
  %23 = tail call i64 @xTaskGetSchedulerState() #4
  %24 = icmp eq i64 %23, 0
  %25 = icmp ne i32 %2, 0
  %26 = and i1 %24, %25
  br i1 %26, label %61, label %.preheader

.preheader:                                       ; preds = %.critedge32
  tail call void @vPortEnterCritical() #4
  %27 = getelementptr inbounds i8, ptr %0, i64 112
  %28 = load volatile i64, ptr %27, align 8, !tbaa !16
  %29 = getelementptr inbounds i8, ptr %0, i64 120
  %30 = load i64, ptr %29, align 8, !tbaa !15
  %31 = icmp ult i64 %28, %30
  %or.cond35 = or i1 %17, %31
  br i1 %or.cond35, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader
  %32 = getelementptr inbounds i8, ptr %0, i64 136
  %33 = getelementptr inbounds i8, ptr %0, i64 137
  %34 = getelementptr inbounds i8, ptr %0, i64 32
  %35 = load i32, ptr %5, align 4, !tbaa !5
  %36 = icmp eq i32 %35, 0
  br i1 %36, label %.loopexit, label %37

37:                                               ; preds = %.lr.ph
  call void @vTaskInternalSetTimeOutState(ptr noundef nonnull %6) #4
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %38 = load volatile i8, ptr %32, align 8, !tbaa !17
  %39 = icmp eq i8 %38, -1
  br i1 %39, label %40, label %41

40:                                               ; preds = %37
  store volatile i8 0, ptr %32, align 8, !tbaa !17
  br label %41

41:                                               ; preds = %40, %37
  %42 = load volatile i8, ptr %33, align 1, !tbaa !18
  %43 = icmp eq i8 %42, -1
  br i1 %43, label %44, label %45

44:                                               ; preds = %41
  store volatile i8 0, ptr %33, align 1, !tbaa !18
  br label %45

45:                                               ; preds = %44, %41
  call void @vPortExitCritical() #4
  %46 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %6, ptr noundef nonnull %5) #4
  %47 = icmp eq i64 %46, 0
  br i1 %47, label %48, label %.loopexit37

48:                                               ; preds = %45
  %49 = call i64 @prvIsQueueFull(ptr noundef nonnull %0)
  %.not.peel = icmp eq i64 %49, 0
  br i1 %.not.peel, label %55, label %50

50:                                               ; preds = %48
  %51 = load i32, ptr %5, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %34, i32 noundef %51) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %52 = call i64 @xTaskResumeAll() #4
  %53 = icmp eq i64 %52, 0
  br i1 %53, label %54, label %57

54:                                               ; preds = %50
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  br label %57

55:                                               ; preds = %48
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %56 = call i64 @xTaskResumeAll() #4
  br label %57

57:                                               ; preds = %55, %54, %50
  call void @vPortEnterCritical() #4
  %58 = load volatile i64, ptr %27, align 8, !tbaa !16
  %59 = load i64, ptr %29, align 8, !tbaa !15
  %60 = icmp ult i64 %58, %59
  br i1 %60, label %._crit_edge, label %.peel.next

61:                                               ; preds = %.critedge32
  tail call void @vPortRaiseBASEPRI()
  br label %62

62:                                               ; preds = %62, %61
  br label %62

._crit_edge:                                      ; preds = %95, %57, %.preheader
  %63 = call i64 @prvCopyDataToQueue(ptr noundef nonnull %0, ptr noundef %1, i64 noundef %3)
  %64 = getelementptr inbounds i8, ptr %0, i64 72
  %65 = load volatile i64, ptr %64, align 8, !tbaa !21
  %.not28 = icmp eq i64 %65, 0
  br i1 %.not28, label %69, label %66

66:                                               ; preds = %._crit_edge
  %67 = call i64 @xTaskRemoveFromEventList(ptr noundef nonnull %64) #4
  %.not30 = icmp eq i64 %67, 0
  br i1 %.not30, label %71, label %68

68:                                               ; preds = %66
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !22
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !23
  br label %71

69:                                               ; preds = %._crit_edge
  %.not29 = icmp eq i64 %63, 0
  br i1 %.not29, label %71, label %70

70:                                               ; preds = %69
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !24
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !25
  br label %71

71:                                               ; preds = %70, %69, %68, %66
  call void @vPortExitCritical() #4
  br label %99

.peel.next:                                       ; preds = %57, %95
  %72 = load i32, ptr %5, align 4, !tbaa !5
  %73 = icmp eq i32 %72, 0
  br i1 %73, label %.loopexit, label %74

.loopexit:                                        ; preds = %.peel.next, %.lr.ph
  call void @vPortExitCritical() #4
  br label %99

74:                                               ; preds = %.peel.next
  call void @vPortExitCritical() #4
  call void @vTaskSuspendAll() #4
  call void @vPortEnterCritical() #4
  %75 = load volatile i8, ptr %32, align 8, !tbaa !17
  %76 = icmp eq i8 %75, -1
  br i1 %76, label %77, label %78

77:                                               ; preds = %74
  store volatile i8 0, ptr %32, align 8, !tbaa !17
  br label %78

78:                                               ; preds = %77, %74
  %79 = load volatile i8, ptr %33, align 1, !tbaa !18
  %80 = icmp eq i8 %79, -1
  br i1 %80, label %81, label %82

81:                                               ; preds = %78
  store volatile i8 0, ptr %33, align 1, !tbaa !18
  br label %82

82:                                               ; preds = %81, %78
  call void @vPortExitCritical() #4
  %83 = call i64 @xTaskCheckForTimeOut(ptr noundef nonnull %6, ptr noundef nonnull %5) #4
  %84 = icmp eq i64 %83, 0
  br i1 %84, label %85, label %.loopexit37

85:                                               ; preds = %82
  %86 = call i64 @prvIsQueueFull(ptr noundef nonnull %0)
  %.not = icmp eq i64 %86, 0
  br i1 %.not, label %92, label %87

87:                                               ; preds = %85
  %88 = load i32, ptr %5, align 4, !tbaa !5
  call void @vTaskPlaceOnEventList(ptr noundef nonnull %34, i32 noundef %88) #4
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %89 = call i64 @xTaskResumeAll() #4
  %90 = icmp eq i64 %89, 0
  br i1 %90, label %91, label %95

91:                                               ; preds = %87
  store volatile i32 268435456, ptr inttoptr (i64 3758157060 to ptr), align 4, !tbaa !5
  call void asm sideeffect "dsb", "~{memory},~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !19
  call void asm sideeffect "isb", "~{dirflag},~{fpsr},~{flags}"() #4, !srcloc !20
  br label %95

92:                                               ; preds = %85
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %93 = call i64 @xTaskResumeAll() #4
  br label %95

.loopexit37:                                      ; preds = %82, %45
  call void @prvUnlockQueue(ptr noundef nonnull %0)
  %94 = call i64 @xTaskResumeAll() #4
  br label %99

95:                                               ; preds = %92, %91, %87
  call void @vPortEnterCritical() #4
  %96 = load volatile i64, ptr %27, align 8, !tbaa !16
  %97 = load i64, ptr %29, align 8, !tbaa !15
  %98 = icmp ult i64 %96, %97
  br i1 %98, label %._crit_edge, label %.peel.next, !llvm.loop !26

99:                                               ; preds = %.loopexit37, %.loopexit, %71
  %.0 = phi i64 [ 1, %71 ], [ 0, %.loopexit ], [ 0, %.loopexit37 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #4
  ret i64 %.0
}

declare i64 @xTaskGetSchedulerState() local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvCopyDataToQueue(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #3

declare void @vTaskInternalSetTimeOutState(ptr noundef) local_unnamed_addr #2

declare void @vTaskSuspendAll() local_unnamed_addr #2

declare i64 @xTaskCheckForTimeOut(ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvIsQueueFull(ptr noundef) local_unnamed_addr #3

declare void @vTaskPlaceOnEventList(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden void @prvUnlockQueue(ptr noundef) local_unnamed_addr #3

declare i64 @xTaskResumeAll() local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !13, i64 128}
!10 = !{!"QueueDefinition", !11, i64 0, !11, i64 8, !7, i64 16, !12, i64 32, !12, i64 72, !13, i64 112, !13, i64 120, !13, i64 128, !7, i64 136, !7, i64 137}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!"xLIST", !13, i64 0, !11, i64 8, !14, i64 16}
!13 = !{!"long", !7, i64 0}
!14 = !{!"xMINI_LIST_ITEM", !6, i64 0, !11, i64 8, !11, i64 16}
!15 = !{!10, !13, i64 120}
!16 = !{!10, !13, i64 112}
!17 = !{!10, !7, i64 136}
!18 = !{!10, !7, i64 137}
!19 = !{i64 2148262618}
!20 = !{i64 2148262687}
!21 = !{!10, !13, i64 72}
!22 = !{i64 2148260229}
!23 = !{i64 2148260298}
!24 = !{i64 2148260869}
!25 = !{i64 2148260938}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopFullUnrollPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass