; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (xStreamBufferSendFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.StreamBufferDef_t = type { i64, i64, i64, i64, ptr, ptr, ptr, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @xStreamBufferSpacesAvailable(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvBytesInBuffer(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i64 @prvWriteMessageToBuffer(ptr noundef, ptr noundef, i64 noundef, i64 noundef, i64 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i64 @xStreamBufferSendFromISR(ptr noundef %0, ptr noundef %1, i64 noundef %2, ptr noundef %3) #2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i64 %2, ptr %7, align 8, !tbaa !9
  store ptr %3, ptr %8, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %14, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %15 = load i64, ptr %7, align 8, !tbaa !9
  store i64 %15, ptr %12, align 8, !tbaa !9
  %16 = load ptr, ptr %6, align 8, !tbaa !5
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %20

18:                                               ; preds = %4
  call void @vPortRaiseBASEPRI()
  br label %19

19:                                               ; preds = %19, %18
  br label %19

20:                                               ; preds = %4
  %21 = load ptr, ptr %9, align 8, !tbaa !5
  %22 = icmp eq ptr %21, null
  br i1 %22, label %23, label %25

23:                                               ; preds = %20
  call void @vPortRaiseBASEPRI()
  br label %24

24:                                               ; preds = %24, %23
  br label %24

25:                                               ; preds = %20
  %26 = load ptr, ptr %9, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %26, i32 0, i32 7
  %28 = load i8, ptr %27, align 8, !tbaa !11
  %29 = zext i8 %28 to i32
  %30 = and i32 %29, 1
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %35

32:                                               ; preds = %25
  %33 = load i64, ptr %12, align 8, !tbaa !9
  %34 = add i64 %33, 8
  store i64 %34, ptr %12, align 8, !tbaa !9
  br label %36

35:                                               ; preds = %25
  br label %36

36:                                               ; preds = %35, %32
  %37 = load ptr, ptr %9, align 8, !tbaa !5
  %38 = call i64 @xStreamBufferSpacesAvailable(ptr noundef %37)
  store i64 %38, ptr %11, align 8, !tbaa !9
  %39 = load ptr, ptr %9, align 8, !tbaa !5
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = load i64, ptr %7, align 8, !tbaa !9
  %42 = load i64, ptr %11, align 8, !tbaa !9
  %43 = load i64, ptr %12, align 8, !tbaa !9
  %44 = call i64 @prvWriteMessageToBuffer(ptr noundef %39, ptr noundef %40, i64 noundef %41, i64 noundef %42, i64 noundef %43)
  store i64 %44, ptr %10, align 8, !tbaa !9
  %45 = load i64, ptr %10, align 8, !tbaa !9
  %46 = icmp ugt i64 %45, 0
  br i1 %46, label %47, label %74

47:                                               ; preds = %36
  %48 = load ptr, ptr %9, align 8, !tbaa !5
  %49 = call i64 @prvBytesInBuffer(ptr noundef %48)
  %50 = load ptr, ptr %9, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %50, i32 0, i32 3
  %52 = load i64, ptr %51, align 8, !tbaa !13
  %53 = icmp uge i64 %49, %52
  br i1 %53, label %54, label %72

54:                                               ; preds = %47
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %55 = call i32 @ulPortRaiseBASEPRI()
  %56 = zext i32 %55 to i64
  store i64 %56, ptr %13, align 8, !tbaa !9
  %57 = load ptr, ptr %9, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %57, i32 0, i32 4
  %59 = load volatile ptr, ptr %58, align 8, !tbaa !14
  %60 = icmp ne ptr %59, null
  br i1 %60, label %61, label %69

61:                                               ; preds = %54
  %62 = load ptr, ptr %9, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %62, i32 0, i32 4
  %64 = load volatile ptr, ptr %63, align 8, !tbaa !14
  %65 = load ptr, ptr %8, align 8, !tbaa !5
  %66 = call i64 @xTaskGenericNotifyFromISR(ptr noundef %64, i64 noundef 0, i32 noundef 0, i32 noundef 0, ptr noundef null, ptr noundef %65)
  %67 = load ptr, ptr %9, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.StreamBufferDef_t, ptr %67, i32 0, i32 4
  store volatile ptr null, ptr %68, align 8, !tbaa !14
  br label %69

69:                                               ; preds = %61, %54
  %70 = load i64, ptr %13, align 8, !tbaa !9
  %71 = trunc i64 %70 to i32
  call void @vPortSetBASEPRI(i32 noundef %71)
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %73

72:                                               ; preds = %47
  br label %73

73:                                               ; preds = %72, %69
  br label %75

74:                                               ; preds = %36
  br label %75

75:                                               ; preds = %74, %73
  %76 = load i64, ptr %10, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  ret i64 %76
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #1

declare i64 @xTaskGenericNotifyFromISR(ptr noundef, i64 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !7, i64 56}
!12 = !{!"StreamBufferDef_t", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !7, i64 56}
!13 = !{!12, !10, i64 24}
!14 = !{!12, !6, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @xStreamBufferSpacesAvailable(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i64 @prvBytesInBuffer(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden i64 @prvWriteMessageToBuffer(ptr noundef, ptr noundef, i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i64 @xStreamBufferSendFromISR(ptr noundef %0, ptr noundef %1, i64 noundef %2, ptr noundef %3) local_unnamed_addr #1 {
  %5 = icmp eq ptr %1, null
  br i1 %5, label %6, label %8

6:                                                ; preds = %4
  tail call void @vPortRaiseBASEPRI()
  br label %7

7:                                                ; preds = %7, %6
  br label %7

8:                                                ; preds = %4
  %9 = icmp eq ptr %0, null
  br i1 %9, label %10, label %12

10:                                               ; preds = %8
  tail call void @vPortRaiseBASEPRI()
  br label %11

11:                                               ; preds = %11, %10
  br label %11

12:                                               ; preds = %8
  %13 = getelementptr inbounds i8, ptr %0, i64 56
  %14 = load i8, ptr %13, align 8, !tbaa !5
  %15 = shl i8 %14, 3
  %16 = and i8 %15, 8
  %17 = zext nneg i8 %16 to i64
  %spec.select = add i64 %17, %2
  %18 = tail call i64 @xStreamBufferSpacesAvailable(ptr noundef nonnull %0)
  %19 = tail call i64 @prvWriteMessageToBuffer(ptr noundef nonnull %0, ptr noundef nonnull %1, i64 noundef %2, i64 noundef %18, i64 noundef %spec.select)
  %.not22 = icmp eq i64 %19, 0
  br i1 %.not22, label %32, label %20

20:                                               ; preds = %12
  %21 = tail call i64 @prvBytesInBuffer(ptr noundef nonnull %0)
  %22 = getelementptr inbounds i8, ptr %0, i64 24
  %23 = load i64, ptr %22, align 8, !tbaa !11
  %.not23 = icmp ult i64 %21, %23
  br i1 %.not23, label %32, label %24

24:                                               ; preds = %20
  %25 = tail call i32 @ulPortRaiseBASEPRI()
  %26 = getelementptr inbounds i8, ptr %0, i64 32
  %27 = load volatile ptr, ptr %26, align 8, !tbaa !12
  %.not24 = icmp eq ptr %27, null
  br i1 %.not24, label %31, label %28

28:                                               ; preds = %24
  %29 = load volatile ptr, ptr %26, align 8, !tbaa !12
  %30 = tail call i64 @xTaskGenericNotifyFromISR(ptr noundef %29, i64 noundef 0, i32 noundef 0, i32 noundef 0, ptr noundef null, ptr noundef %3) #3
  store volatile ptr null, ptr %26, align 8, !tbaa !12
  br label %31

31:                                               ; preds = %28, %24
  tail call void @vPortSetBASEPRI(i32 noundef %25)
  br label %32

32:                                               ; preds = %12, %31, %20
  ret i64 %19
}

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #0

declare i64 @xTaskGenericNotifyFromISR(ptr noundef, i64 noundef, i32 noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #0

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !8, i64 56}
!6 = !{!"StreamBufferDef_t", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !10, i64 32, !10, i64 40, !10, i64 48, !8, i64 56}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !7, i64 24}
!12 = !{!6, !10, i64 32}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass