; LLVM IR from whoiswelliton/Computer_Engineering_UTFPR-PB :: Embedded_Systems/TIVA Connected TM4C1294XL Projects/00 - freeRTOS10_on_TIVA (vTaskGenericNotifyGiveFromISR)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }
%struct.tskTaskControlBlock = type { ptr, %struct.xLIST_ITEM, %struct.xLIST_ITEM, i64, ptr, [32 x i8], i64, i64, [1 x i32], [1 x i8] }
%struct.xLIST_ITEM = type { i32, ptr, ptr, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i64 @uxListRemove(ptr noundef) #1

declare void @vListInsertEnd(ptr noundef, ptr noundef) #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() #2

declare void @vPortValidateInterruptPriority() #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() #2

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local void @vTaskGenericNotifyGiveFromISR(ptr noundef %0, i64 noundef %1, ptr noundef %2) #3 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = icmp eq ptr %10, null
  br i1 %11, label %12, label %14

12:                                               ; preds = %3
  call void @vPortRaiseBASEPRI()
  br label %13

13:                                               ; preds = %13, %12
  br label %13

14:                                               ; preds = %3
  %15 = load i64, ptr %5, align 8, !tbaa !9
  %16 = icmp ult i64 %15, 1
  %17 = zext i1 %16 to i32
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %21

19:                                               ; preds = %14
  call void @vPortRaiseBASEPRI()
  br label %20

20:                                               ; preds = %20, %19
  br label %20

21:                                               ; preds = %14
  call void @vPortValidateInterruptPriority()
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %22, ptr %7, align 8, !tbaa !5
  %23 = call i32 @ulPortRaiseBASEPRI()
  %24 = zext i32 %23 to i64
  store i64 %24, ptr %9, align 8, !tbaa !9
  %25 = load ptr, ptr %7, align 8, !tbaa !5
  %26 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %25, i32 0, i32 9
  %27 = load i64, ptr %5, align 8, !tbaa !9
  %28 = getelementptr inbounds [1 x i8], ptr %26, i64 0, i64 %27
  %29 = load volatile i8, ptr %28, align 1, !tbaa !11
  store i8 %29, ptr %8, align 1, !tbaa !11
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %30, i32 0, i32 9
  %32 = load i64, ptr %5, align 8, !tbaa !9
  %33 = getelementptr inbounds [1 x i8], ptr %31, i64 0, i64 %32
  store volatile i8 2, ptr %33, align 1, !tbaa !11
  %34 = load ptr, ptr %7, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %34, i32 0, i32 8
  %36 = load i64, ptr %5, align 8, !tbaa !9
  %37 = getelementptr inbounds [1 x i32], ptr %35, i64 0, i64 %36
  %38 = load volatile i32, ptr %37, align 4, !tbaa !12
  %39 = add i32 %38, 1
  store volatile i32 %39, ptr %37, align 4, !tbaa !12
  %40 = load i8, ptr %8, align 1, !tbaa !11
  %41 = zext i8 %40 to i32
  %42 = icmp eq i32 %41, 1
  br i1 %42, label %43, label %91

43:                                               ; preds = %21
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %44, i32 0, i32 2
  %46 = getelementptr inbounds %struct.xLIST_ITEM, ptr %45, i32 0, i32 4
  %47 = load ptr, ptr %46, align 8, !tbaa !14
  %48 = icmp eq ptr %47, null
  %49 = zext i1 %48 to i32
  %50 = icmp eq i32 %49, 0
  br i1 %50, label %51, label %53

51:                                               ; preds = %43
  call void @vPortRaiseBASEPRI()
  br label %52

52:                                               ; preds = %52, %51
  br label %52

53:                                               ; preds = %43
  %54 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !9
  %55 = icmp eq i64 %54, 0
  br i1 %55, label %56, label %72

56:                                               ; preds = %53
  %57 = load ptr, ptr %7, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %57, i32 0, i32 1
  %59 = call i64 @uxListRemove(ptr noundef %58)
  %60 = load ptr, ptr %7, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %60, i32 0, i32 3
  %62 = load i64, ptr %61, align 8, !tbaa !17
  %63 = shl i64 1, %62
  %64 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %65 = or i64 %64, %63
  store volatile i64 %65, ptr @uxTopReadyPriority, align 8, !tbaa !9
  %66 = load ptr, ptr %7, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %66, i32 0, i32 3
  %68 = load i64, ptr %67, align 8, !tbaa !17
  %69 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %68
  %70 = load ptr, ptr %7, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %70, i32 0, i32 1
  call void @vListInsertEnd(ptr noundef %69, ptr noundef %71)
  br label %75

72:                                               ; preds = %53
  %73 = load ptr, ptr %7, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %73, i32 0, i32 2
  call void @vListInsertEnd(ptr noundef @xPendingReadyList, ptr noundef %74)
  br label %75

75:                                               ; preds = %72, %56
  %76 = load ptr, ptr %7, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %76, i32 0, i32 3
  %78 = load i64, ptr %77, align 8, !tbaa !17
  %79 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.tskTaskControlBlock, ptr %79, i32 0, i32 3
  %81 = load i64, ptr %80, align 8, !tbaa !17
  %82 = icmp ugt i64 %78, %81
  br i1 %82, label %83, label %89

83:                                               ; preds = %75
  %84 = load ptr, ptr %6, align 8, !tbaa !5
  %85 = icmp ne ptr %84, null
  br i1 %85, label %86, label %88

86:                                               ; preds = %83
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  store i64 1, ptr %87, align 8, !tbaa !9
  br label %88

88:                                               ; preds = %86, %83
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !9
  br label %90

89:                                               ; preds = %75
  br label %90

90:                                               ; preds = %89, %88
  br label %91

91:                                               ; preds = %90, %21
  %92 = load i64, ptr %9, align 8, !tbaa !9
  %93 = trunc i64 %92 to i32
  call void @vPortSetBASEPRI(i32 noundef %93)
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = !{!15, !6, i64 80}
!15 = !{!"tskTaskControlBlock", !6, i64 0, !16, i64 8, !16, i64 48, !10, i64 88, !6, i64 96, !7, i64 104, !10, i64 136, !10, i64 144, !7, i64 152, !7, i64 156}
!16 = !{!"xLIST_ITEM", !13, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32}
!17 = !{!15, !10, i64 88}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.xLIST = type { i64, ptr, %struct.xMINI_LIST_ITEM }
%struct.xMINI_LIST_ITEM = type { i32, ptr, ptr }

@pxCurrentTCB = external dso_local global ptr, align 8
@pxReadyTasksLists = external hidden global [15 x %struct.xLIST], align 16
@uxTopReadyPriority = external hidden global i64, align 8
@uxSchedulerSuspended = external hidden global i64, align 8
@xPendingReadyList = external hidden global %struct.xLIST, align 8
@xYieldPending = external hidden global i64, align 8

declare i64 @uxListRemove(ptr noundef) local_unnamed_addr #0

declare void @vListInsertEnd(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortRaiseBASEPRI() local_unnamed_addr #1

declare void @vPortValidateInterruptPriority() local_unnamed_addr #0

; Function Attrs: alwaysinline nounwind uwtable
declare hidden i32 @ulPortRaiseBASEPRI() local_unnamed_addr #1

; Function Attrs: alwaysinline nounwind uwtable
declare hidden void @vPortSetBASEPRI(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @vTaskGenericNotifyGiveFromISR(ptr noundef %0, i64 noundef %1, ptr noundef writeonly %2) local_unnamed_addr #2 {
  %4 = icmp eq ptr %0, null
  br i1 %4, label %5, label %7

5:                                                ; preds = %3
  tail call void @vPortRaiseBASEPRI()
  br label %6

6:                                                ; preds = %6, %5
  br label %6

7:                                                ; preds = %3
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %10, label %8

8:                                                ; preds = %7
  tail call void @vPortRaiseBASEPRI()
  br label %9

9:                                                ; preds = %9, %8
  br label %9

10:                                               ; preds = %7
  tail call void @vPortValidateInterruptPriority() #3
  %11 = tail call i32 @ulPortRaiseBASEPRI()
  %12 = getelementptr inbounds i8, ptr %0, i64 156
  %13 = load volatile i8, ptr %12, align 1, !tbaa !5
  store volatile i8 2, ptr %12, align 1, !tbaa !5
  %14 = getelementptr inbounds i8, ptr %0, i64 152
  %15 = load volatile i32, ptr %14, align 4, !tbaa !8
  %16 = add i32 %15, 1
  store volatile i32 %16, ptr %14, align 4, !tbaa !8
  %17 = icmp eq i8 %13, 1
  br i1 %17, label %18, label %47

18:                                               ; preds = %10
  %19 = getelementptr inbounds i8, ptr %0, i64 48
  %20 = getelementptr inbounds i8, ptr %0, i64 80
  %21 = load ptr, ptr %20, align 8, !tbaa !10
  %.not20 = icmp eq ptr %21, null
  br i1 %.not20, label %24, label %22

22:                                               ; preds = %18
  tail call void @vPortRaiseBASEPRI()
  br label %23

23:                                               ; preds = %23, %22
  br label %23

24:                                               ; preds = %18
  %25 = load volatile i64, ptr @uxSchedulerSuspended, align 8, !tbaa !15
  %26 = icmp eq i64 %25, 0
  br i1 %26, label %27, label %36

27:                                               ; preds = %24
  %28 = getelementptr inbounds i8, ptr %0, i64 8
  %29 = tail call i64 @uxListRemove(ptr noundef nonnull %28) #3
  %30 = getelementptr inbounds i8, ptr %0, i64 88
  %31 = load i64, ptr %30, align 8, !tbaa !16
  %32 = shl nuw i64 1, %31
  %33 = load volatile i64, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %34 = or i64 %33, %32
  store volatile i64 %34, ptr @uxTopReadyPriority, align 8, !tbaa !15
  %35 = getelementptr inbounds [15 x %struct.xLIST], ptr @pxReadyTasksLists, i64 0, i64 %31
  tail call void @vListInsertEnd(ptr noundef nonnull %35, ptr noundef nonnull %28) #3
  br label %37

36:                                               ; preds = %24
  tail call void @vListInsertEnd(ptr noundef nonnull @xPendingReadyList, ptr noundef nonnull %19) #3
  br label %37

37:                                               ; preds = %36, %27
  %38 = getelementptr inbounds i8, ptr %0, i64 88
  %39 = load i64, ptr %38, align 8, !tbaa !16
  %40 = load volatile ptr, ptr @pxCurrentTCB, align 8, !tbaa !17
  %41 = getelementptr inbounds i8, ptr %40, i64 88
  %42 = load i64, ptr %41, align 8, !tbaa !16
  %43 = icmp ugt i64 %39, %42
  br i1 %43, label %44, label %47

44:                                               ; preds = %37
  %.not21 = icmp eq ptr %2, null
  br i1 %.not21, label %46, label %45

45:                                               ; preds = %44
  store i64 1, ptr %2, align 8, !tbaa !15
  br label %46

46:                                               ; preds = %45, %44
  store volatile i64 1, ptr @xYieldPending, align 8, !tbaa !15
  br label %47

47:                                               ; preds = %46, %37, %10
  tail call void @vPortSetBASEPRI(i32 noundef %11)
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = !{!11, !12, i64 80}
!11 = !{!"tskTaskControlBlock", !12, i64 0, !13, i64 8, !13, i64 48, !14, i64 88, !12, i64 96, !6, i64 104, !14, i64 136, !14, i64 144, !6, i64 152, !6, i64 156}
!12 = !{!"any pointer", !6, i64 0}
!13 = !{!"xLIST_ITEM", !9, i64 0, !12, i64 8, !12, i64 16, !12, i64 24, !12, i64 32}
!14 = !{!"long", !6, i64 0}
!15 = !{!14, !14, i64 0}
!16 = !{!11, !14, i64 88}
!17 = !{!12, !12, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass