; LLVM IR from DionysiosB/CodeForces :: 0500-0599/551C-GukiZHatesBoxes.ll (Z5checkSt6vectorIlSaIlEEll)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5checkSt6vectorIlSaIlEEll(ptr noundef %0, i64 noundef %1, i64 noundef %2) #0 {
  %4 = alloca i1, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store i64 %2, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  store i64 0, ptr %8, align 8, !tbaa !9
  %12 = load i64, ptr %7, align 8, !tbaa !9
  %13 = add nsw i64 %12, -1
  store i64 %13, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  store i64 0, ptr %9, align 8, !tbaa !9
  br label %14

14:                                               ; preds = %60, %3
  %15 = load i64, ptr %9, align 8, !tbaa !9
  %16 = load i64, ptr %6, align 8, !tbaa !9
  %17 = icmp slt i64 %15, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %14
  store i32 2, ptr %10, align 4
  br label %63

19:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  %20 = load i64, ptr %7, align 8, !tbaa !9
  %21 = load i64, ptr %8, align 8, !tbaa !9
  %22 = sub nsw i64 %20, %21
  store i64 %22, ptr %11, align 8, !tbaa !9
  br label %23

23:                                               ; preds = %55, %19
  %24 = load i64, ptr %11, align 8, !tbaa !9
  %25 = icmp sgt i64 %24, 0
  br i1 %25, label %26, label %56

26:                                               ; preds = %23
  %27 = load i64, ptr %8, align 8, !tbaa !9
  %28 = call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %29 = icmp uge i64 %27, %28
  br i1 %29, label %30, label %31

30:                                               ; preds = %26
  store i1 true, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %57

31:                                               ; preds = %26
  %32 = load i64, ptr %8, align 8, !tbaa !9
  %33 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %32) #2
  %34 = load i64, ptr %33, align 8, !tbaa !9
  %35 = load i64, ptr %11, align 8, !tbaa !9
  %36 = icmp sle i64 %34, %35
  br i1 %36, label %37, label %49

37:                                               ; preds = %31
  %38 = load i64, ptr %8, align 8, !tbaa !9
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %38) #2
  %40 = load i64, ptr %39, align 8, !tbaa !9
  %41 = load i64, ptr %11, align 8, !tbaa !9
  %42 = sub nsw i64 %41, %40
  store i64 %42, ptr %11, align 8, !tbaa !9
  %43 = load i64, ptr %8, align 8, !tbaa !9
  %44 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %43) #2
  store i64 0, ptr %44, align 8, !tbaa !9
  %45 = load i64, ptr %8, align 8, !tbaa !9
  %46 = add nsw i64 %45, 1
  store i64 %46, ptr %8, align 8, !tbaa !9
  %47 = load i64, ptr %11, align 8, !tbaa !9
  %48 = add nsw i64 %47, -1
  store i64 %48, ptr %11, align 8, !tbaa !9
  br label %55

49:                                               ; preds = %31
  %50 = load i64, ptr %11, align 8, !tbaa !9
  %51 = load i64, ptr %8, align 8, !tbaa !9
  %52 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %51) #2
  %53 = load i64, ptr %52, align 8, !tbaa !9
  %54 = sub nsw i64 %53, %50
  store i64 %54, ptr %52, align 8, !tbaa !9
  store i64 0, ptr %11, align 8, !tbaa !9
  br label %55

55:                                               ; preds = %49, %37
  br label %23, !llvm.loop !11

56:                                               ; preds = %23
  store i32 0, ptr %10, align 4
  br label %57

57:                                               ; preds = %56, %30
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  %58 = load i32, ptr %10, align 4
  switch i32 %58, label %63 [
    i32 0, label %59
  ]

59:                                               ; preds = %57
  br label %60

60:                                               ; preds = %59
  %61 = load i64, ptr %9, align 8, !tbaa !9
  %62 = add nsw i64 %61, 1
  store i64 %62, ptr %9, align 8, !tbaa !9
  br label %14, !llvm.loop !13

63:                                               ; preds = %57, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  %64 = load i32, ptr %10, align 4
  switch i32 %64, label %71 [
    i32 2, label %65
  ]

65:                                               ; preds = %63
  %66 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEE4backEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %67 = load i64, ptr %66, align 8, !tbaa !9
  %68 = icmp eq i64 %67, 0
  br i1 %68, label %69, label %70

69:                                               ; preds = %65
  store i1 true, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %71

70:                                               ; preds = %65
  store i1 false, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %71

71:                                               ; preds = %70, %69, %63
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  %72 = load i1, ptr %4, align 1
  ret i1 %72
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEE4backEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5checkSt6vectorIlSaIlEEll(ptr noundef %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #0 {
  %.not2935 = icmp sgt i64 %1, 0
  br i1 %.not2935, label %.lr.ph38, label %.critedge31

.lr.ph38:                                         ; preds = %3, %.critedge
  %.02237 = phi i64 [ %20, %.critedge ], [ 0, %3 ]
  %.02336 = phi i64 [ %.124.lcssa, %.critedge ], [ 0, %3 ]
  %4 = xor i64 %.02336, -1
  %5 = add i64 %4, %2
  %6 = icmp slt i64 %5, 1
  br i1 %6, label %.critedge, label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph38, %14
  %.034 = phi i64 [ %18, %14 ], [ %5, %.lr.ph38 ]
  %.12433 = phi i64 [ %16, %14 ], [ %.02336, %.lr.ph38 ]
  %7 = tail call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %.not = icmp ult i64 %.12433, %7
  br i1 %.not, label %8, label %.loopexit

8:                                                ; preds = %.lr.ph
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.12433) #1
  %10 = load i64, ptr %9, align 8, !tbaa !5
  %.not28 = icmp sgt i64 %10, %.034
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.12433) #1
  %12 = load i64, ptr %11, align 8, !tbaa !5
  br i1 %.not28, label %.thread, label %14

.thread:                                          ; preds = %8
  %13 = sub nsw i64 %12, %.034
  store i64 %13, ptr %11, align 8, !tbaa !5
  br label %.critedge

14:                                               ; preds = %8
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.12433) #1
  store i64 0, ptr %15, align 8, !tbaa !5
  %16 = add nuw nsw i64 %.12433, 1
  %17 = xor i64 %12, -1
  %18 = add i64 %.034, %17
  %19 = icmp slt i64 %18, 1
  br i1 %19, label %.critedge, label %.lr.ph, !llvm.loop !9

.critedge:                                        ; preds = %14, %.thread, %.lr.ph38
  %.124.lcssa = phi i64 [ %.02336, %.lr.ph38 ], [ %.12433, %.thread ], [ %16, %14 ]
  %20 = add nuw nsw i64 %.02237, 1
  %exitcond.not = icmp eq i64 %20, %1
  br i1 %exitcond.not, label %.critedge31, label %.lr.ph38, !llvm.loop !11

.critedge31:                                      ; preds = %.critedge, %3
  %21 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEE4backEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %22 = load i64, ptr %21, align 8, !tbaa !5
  %23 = icmp eq i64 %22, 0
  br label %.loopexit

.loopexit:                                        ; preds = %.lr.ph, %.critedge31
  %.3 = phi i1 [ %23, %.critedge31 ], [ true, %.lr.ph ]
  ret i1 %.3
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIlSaIlEE4backEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass