; LLVM IR from DionysiosB/CodeForces :: 0700-0799/729C-RoadToCinema.ll (Z5checkSt6vectorIlSaIlEEll)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5checkSt6vectorIlSaIlEEll(ptr noundef %0, i64 noundef %1, i64 noundef %2) #0 {
  %4 = alloca i1, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store i64 %2, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  store i64 0, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  store i64 1, ptr %9, align 8, !tbaa !9
  br label %12

12:                                               ; preds = %61, %3
  %13 = load i64, ptr %9, align 8, !tbaa !9
  %14 = call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %15 = icmp ult i64 %13, %14
  br i1 %15, label %17, label %16

16:                                               ; preds = %12
  store i32 2, ptr %10, align 4
  br label %64

17:                                               ; preds = %12
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  %18 = load i64, ptr %9, align 8, !tbaa !9
  %19 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %18) #2
  %20 = load i64, ptr %19, align 8, !tbaa !9
  %21 = load i64, ptr %9, align 8, !tbaa !9
  %22 = sub nsw i64 %21, 1
  %23 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %22) #2
  %24 = load i64, ptr %23, align 8, !tbaa !9
  %25 = sub nsw i64 %20, %24
  store i64 %25, ptr %11, align 8, !tbaa !9
  %26 = load i64, ptr %7, align 8, !tbaa !9
  %27 = load i64, ptr %11, align 8, !tbaa !9
  %28 = icmp slt i64 %26, %27
  br i1 %28, label %29, label %30

29:                                               ; preds = %17
  store i1 false, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %58

30:                                               ; preds = %17
  %31 = load i64, ptr %7, align 8, !tbaa !9
  %32 = load i64, ptr %11, align 8, !tbaa !9
  %33 = mul nsw i64 2, %32
  %34 = icmp sge i64 %31, %33
  br i1 %34, label %35, label %39

35:                                               ; preds = %30
  %36 = load i64, ptr %11, align 8, !tbaa !9
  %37 = load i64, ptr %8, align 8, !tbaa !9
  %38 = add nsw i64 %37, %36
  store i64 %38, ptr %8, align 8, !tbaa !9
  br label %51

39:                                               ; preds = %30
  %40 = load i64, ptr %11, align 8, !tbaa !9
  %41 = mul nsw i64 2, %40
  %42 = load i64, ptr %7, align 8, !tbaa !9
  %43 = sub nsw i64 %41, %42
  %44 = mul nsw i64 2, %43
  %45 = load i64, ptr %7, align 8, !tbaa !9
  %46 = load i64, ptr %11, align 8, !tbaa !9
  %47 = sub nsw i64 %45, %46
  %48 = add nsw i64 %44, %47
  %49 = load i64, ptr %8, align 8, !tbaa !9
  %50 = add nsw i64 %49, %48
  store i64 %50, ptr %8, align 8, !tbaa !9
  br label %51

51:                                               ; preds = %39, %35
  br label %52

52:                                               ; preds = %51
  %53 = load i64, ptr %8, align 8, !tbaa !9
  %54 = load i64, ptr %6, align 8, !tbaa !9
  %55 = icmp sgt i64 %53, %54
  br i1 %55, label %56, label %57

56:                                               ; preds = %52
  store i1 false, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %58

57:                                               ; preds = %52
  store i32 0, ptr %10, align 4
  br label %58

58:                                               ; preds = %57, %56, %29
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  %59 = load i32, ptr %10, align 4
  switch i32 %59, label %64 [
    i32 0, label %60
  ]

60:                                               ; preds = %58
  br label %61

61:                                               ; preds = %60
  %62 = load i64, ptr %9, align 8, !tbaa !9
  %63 = add nsw i64 %62, 1
  store i64 %63, ptr %9, align 8, !tbaa !9
  br label %12, !llvm.loop !11

64:                                               ; preds = %58, %16
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  %65 = load i32, ptr %10, align 4
  switch i32 %65, label %70 [
    i32 2, label %66
  ]

66:                                               ; preds = %64
  %67 = load i64, ptr %8, align 8, !tbaa !9
  %68 = load i64, ptr %6, align 8, !tbaa !9
  %69 = icmp sle i64 %67, %68
  store i1 %69, ptr %4, align 1
  store i32 1, ptr %10, align 4
  br label %70

70:                                               ; preds = %66, %64
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  %71 = load i1, ptr %4, align 1
  ret i1 %71
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z5checkSt6vectorIlSaIlEEll(ptr noundef nonnull %0, i64 noundef %1, i64 noundef %2) local_unnamed_addr #0 {
  %4 = tail call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %.not3236 = icmp ult i64 %4, 2
  br i1 %.not3236, label %.thread, label %.lr.ph

5:                                                ; preds = %15
  %6 = add nuw nsw i64 %.02438, 1
  %7 = tail call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #1
  %.not32.not = icmp ult i64 %6, %7
  br i1 %.not32.not, label %.lr.ph, label %.thread, !llvm.loop !5

.lr.ph:                                           ; preds = %3, %5
  %.02438 = phi i64 [ %6, %5 ], [ 1, %3 ]
  %.02537 = phi i64 [ %.126, %5 ], [ 0, %3 ]
  %8 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.02438) #1
  %9 = load i64, ptr %8, align 8, !tbaa !7
  %10 = add nsw i64 %.02438, -1
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %10) #1
  %12 = load i64, ptr %11, align 8, !tbaa !7
  %13 = sub nsw i64 %9, %12
  %14 = icmp sgt i64 %13, %2
  br i1 %14, label %.thread, label %15

15:                                               ; preds = %.lr.ph
  %16 = shl nsw i64 %13, 1
  %.not = icmp sgt i64 %16, %2
  %17 = sub nsw i64 %16, %2
  %18 = shl nsw i64 %17, 1
  %19 = sub i64 %2, %13
  %20 = add nsw i64 %19, %18
  %.pn = select i1 %.not, i64 %20, i64 %13
  %.126 = add nsw i64 %.pn, %.02537
  %.not35 = icmp sgt i64 %.126, %1
  br i1 %.not35, label %.thread, label %5

.thread:                                          ; preds = %15, %5, %.lr.ph, %3
  %.not32.lcssa = phi i1 [ true, %3 ], [ false, %.lr.ph ], [ true, %5 ], [ false, %15 ]
  %.328 = phi i64 [ 0, %3 ], [ %.02537, %.lr.ph ], [ %.126, %5 ], [ %.126, %15 ]
  %21 = icmp sle i64 %.328, %1
  %.3 = and i1 %.not32.lcssa, %21
  ret i1 %.3
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"long", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass