; LLVM IR from DionysiosB/CodeForces :: 0400-0499/486D-ValidSets.ll (Z3dfsllRKSt6vectorIS_IlSaIlEESaIS1_EERKS1_lll)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z3dfsllRKSt6vectorIS_IlSaIlEESaIS1_EERKS1_lll(i64 noundef %0, i64 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %4, i64 noundef %5, i64 noundef %6) #0 {
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  %17 = alloca i32, align 4
  %18 = alloca i64, align 8
  store i64 %0, ptr %8, align 8, !tbaa !5
  store i64 %1, ptr %9, align 8, !tbaa !5
  store ptr %2, ptr %10, align 8, !tbaa !9
  store ptr %3, ptr %11, align 8, !tbaa !9
  store i64 %4, ptr %12, align 8, !tbaa !5
  store i64 %5, ptr %13, align 8, !tbaa !5
  store i64 %6, ptr %14, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  store i64 1, ptr %15, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #3
  store i64 0, ptr %16, align 8, !tbaa !5
  br label %19

19:                                               ; preds = %83, %7
  %20 = load i64, ptr %16, align 8, !tbaa !5
  %21 = load ptr, ptr %10, align 8, !tbaa !9
  %22 = load i64, ptr %8, align 8, !tbaa !5
  %23 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %22) #3
  %24 = call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %23) #3
  %25 = icmp ult i64 %20, %24
  br i1 %25, label %27, label %26

26:                                               ; preds = %19
  store i32 2, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #3
  br label %86

27:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #3
  %28 = load ptr, ptr %10, align 8, !tbaa !9
  %29 = load i64, ptr %8, align 8, !tbaa !5
  %30 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %29) #3
  %31 = load i64, ptr %16, align 8, !tbaa !5
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %30, i64 noundef %31) #3
  %33 = load i64, ptr %32, align 8, !tbaa !5
  store i64 %33, ptr %18, align 8, !tbaa !5
  %34 = load i64, ptr %18, align 8, !tbaa !5
  %35 = load i64, ptr %9, align 8, !tbaa !5
  %36 = icmp eq i64 %34, %35
  br i1 %36, label %37, label %38

37:                                               ; preds = %27
  store i32 4, ptr %17, align 4
  br label %80

38:                                               ; preds = %27
  %39 = load ptr, ptr %11, align 8, !tbaa !9
  %40 = load i64, ptr %18, align 8, !tbaa !5
  %41 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %39, i64 noundef %40) #3
  %42 = load i64, ptr %41, align 8, !tbaa !5
  %43 = load i64, ptr %12, align 8, !tbaa !5
  %44 = load i64, ptr %13, align 8, !tbaa !5
  %45 = add nsw i64 %43, %44
  %46 = icmp sle i64 %42, %45
  br i1 %46, label %47, label %79

47:                                               ; preds = %38
  %48 = load ptr, ptr %11, align 8, !tbaa !9
  %49 = load i64, ptr %18, align 8, !tbaa !5
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %49) #3
  %51 = load i64, ptr %50, align 8, !tbaa !5
  %52 = load i64, ptr %12, align 8, !tbaa !5
  %53 = icmp sgt i64 %51, %52
  br i1 %53, label %65, label %54

54:                                               ; preds = %47
  %55 = load ptr, ptr %11, align 8, !tbaa !9
  %56 = load i64, ptr %18, align 8, !tbaa !5
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %55, i64 noundef %56) #3
  %58 = load i64, ptr %57, align 8, !tbaa !5
  %59 = load i64, ptr %12, align 8, !tbaa !5
  %60 = icmp eq i64 %58, %59
  br i1 %60, label %61, label %79

61:                                               ; preds = %54
  %62 = load i64, ptr %18, align 8, !tbaa !5
  %63 = load i64, ptr %14, align 8, !tbaa !5
  %64 = icmp sgt i64 %62, %63
  br i1 %64, label %65, label %79

65:                                               ; preds = %61, %47
  %66 = load i64, ptr %18, align 8, !tbaa !5
  %67 = load i64, ptr %8, align 8, !tbaa !5
  %68 = load ptr, ptr %10, align 8, !tbaa !9
  %69 = load ptr, ptr %11, align 8, !tbaa !9
  %70 = load i64, ptr %12, align 8, !tbaa !5
  %71 = load i64, ptr %13, align 8, !tbaa !5
  %72 = load i64, ptr %14, align 8, !tbaa !5
  %73 = call noundef i64 @_Z3dfsllRKSt6vectorIS_IlSaIlEESaIS1_EERKS1_lll(i64 noundef %66, i64 noundef %67, ptr noundef nonnull align 8 dereferenceable(24) %68, ptr noundef nonnull align 8 dereferenceable(24) %69, i64 noundef %70, i64 noundef %71, i64 noundef %72)
  %74 = add nsw i64 %73, 1
  %75 = load i64, ptr %15, align 8, !tbaa !11
  %76 = mul nsw i64 %75, %74
  store i64 %76, ptr %15, align 8, !tbaa !11
  %77 = load i64, ptr %15, align 8, !tbaa !11
  %78 = srem i64 %77, 1000000007
  store i64 %78, ptr %15, align 8, !tbaa !11
  br label %79

79:                                               ; preds = %65, %61, %54, %38
  store i32 0, ptr %17, align 4
  br label %80

80:                                               ; preds = %79, %37
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #3
  %81 = load i32, ptr %17, align 4
  switch i32 %81, label %88 [
    i32 0, label %82
    i32 4, label %83
  ]

82:                                               ; preds = %80
  br label %83

83:                                               ; preds = %82, %80
  %84 = load i64, ptr %16, align 8, !tbaa !5
  %85 = add nsw i64 %84, 1
  store i64 %85, ptr %16, align 8, !tbaa !5
  br label %19, !llvm.loop !13

86:                                               ; preds = %26
  %87 = load i64, ptr %15, align 8, !tbaa !11
  store i32 1, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  ret i64 %87

88:                                               ; preds = %80
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z3dfsllRKSt6vectorIS_IlSaIlEESaIS1_EERKS1_lll(i64 noundef %0, i64 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %4, i64 noundef %5, i64 noundef %6) local_unnamed_addr #0 {
  %8 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %0) #1
  %9 = tail call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #1
  %.not35 = icmp eq i64 %9, 0
  br i1 %.not35, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %7
  %10 = add nsw i64 %5, %4
  br label %11

._crit_edge:                                      ; preds = %33, %7
  %.0.lcssa = phi i64 [ 1, %7 ], [ %.2, %33 ]
  ret i64 %.0.lcssa

11:                                               ; preds = %.lr.ph, %33
  %.034 = phi i64 [ 1, %.lr.ph ], [ %.2, %33 ]
  %.03033 = phi i64 [ 0, %.lr.ph ], [ %34, %33 ]
  %12 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %0) #1
  %13 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %.03033) #1
  %14 = load i64, ptr %13, align 8, !tbaa !5
  %15 = icmp eq i64 %14, %1
  br i1 %15, label %33, label %16

16:                                               ; preds = %11
  %17 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %14) #1
  %18 = load i64, ptr %17, align 8, !tbaa !5
  %.not = icmp sgt i64 %18, %10
  br i1 %.not, label %33, label %19

19:                                               ; preds = %16
  %20 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %14) #1
  %21 = load i64, ptr %20, align 8, !tbaa !5
  %22 = icmp sgt i64 %21, %4
  br i1 %22, label %28, label %23

23:                                               ; preds = %19
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %14) #1
  %25 = load i64, ptr %24, align 8, !tbaa !5
  %26 = icmp eq i64 %25, %4
  %27 = icmp sgt i64 %14, %6
  %or.cond = and i1 %27, %26
  br i1 %or.cond, label %28, label %33

28:                                               ; preds = %23, %19
  %29 = tail call noundef i64 @_Z3dfsllRKSt6vectorIS_IlSaIlEESaIS1_EERKS1_lll(i64 noundef %14, i64 noundef %0, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %4, i64 noundef %5, i64 noundef %6)
  %30 = add nsw i64 %29, 1
  %31 = mul nsw i64 %30, %.034
  %32 = srem i64 %31, 1000000007
  br label %33

33:                                               ; preds = %16, %23, %28, %11
  %.2 = phi i64 [ %.034, %11 ], [ %32, %28 ], [ %.034, %23 ], [ %.034, %16 ]
  %34 = add nuw nsw i64 %.03033, 1
  %35 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %0) #1
  %36 = tail call noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %35) #1
  %37 = icmp ult i64 %34, %36
  br i1 %37, label %11, label %._crit_edge, !llvm.loop !9
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IlSaIlEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIlSaIlEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIlSaIlEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass