; LLVM IR from ARM-software/Arm-2D :: Acceleration/Arm/ACI/arm_2d_rgb565_aci_fvp_plugin (arm_2d_rgb565_aci_fvp)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ACIVCX3DecodeInfo = type { i8, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z22arm_mix_rgb16_uint16x2PtPKtS1_S1_(ptr noundef, ptr noundef, ptr noundef, ptr noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z23arm_pack_rgb16_uint16x2PtS_PKtS1_b(ptr noundef, ptr noundef, ptr noundef, ptr noundef, i1 noundef zeroext) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN21arm_2d_rgb565_aci_fvp21isCDECoprocessorValidEj(ptr noundef nonnull align 8 dereferenceable(240), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN21arm_2d_rgb565_aci_fvp18exec_vcx3_beatwiseEPK17ACIVCX3DecodeInfojjjhhPj(ptr noundef nonnull align 8 dereferenceable(240) %0, ptr noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i8 noundef zeroext %5, i8 noundef zeroext %6, ptr noundef %7) #2 align 2 {
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i8, align 1
  %16 = alloca i8, align 1
  %17 = alloca ptr, align 8
  %18 = alloca i8, align 1
  store ptr %0, ptr %10, align 8, !tbaa !5
  store ptr %1, ptr %11, align 8, !tbaa !5
  store i32 %2, ptr %12, align 4, !tbaa !9
  store i32 %3, ptr %13, align 4, !tbaa !9
  store i32 %4, ptr %14, align 4, !tbaa !9
  store i8 %5, ptr %15, align 1, !tbaa !11
  store i8 %6, ptr %16, align 1, !tbaa !11
  store ptr %7, ptr %17, align 8, !tbaa !5
  %19 = load ptr, ptr %10, align 8
  %20 = load ptr, ptr %11, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.ACIVCX3DecodeInfo, ptr %20, i32 0, i32 1
  %22 = load i32, ptr %21, align 4, !tbaa !12
  %23 = call noundef zeroext i1 @_ZN21arm_2d_rgb565_aci_fvp21isCDECoprocessorValidEj(ptr noundef nonnull align 8 dereferenceable(240) %19, i32 noundef %22)
  br i1 %23, label %25, label %24

24:                                               ; preds = %8
  store i32 100, ptr %9, align 4
  br label %52

25:                                               ; preds = %8
  %26 = load ptr, ptr %11, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.ACIVCX3DecodeInfo, ptr %26, i32 0, i32 0
  %28 = load i8, ptr %27, align 4, !tbaa !15, !range !16, !noundef !17
  %29 = trunc i8 %28 to i1
  br i1 %29, label %30, label %51

30:                                               ; preds = %25
  %31 = load ptr, ptr %11, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.ACIVCX3DecodeInfo, ptr %31, i32 0, i32 2
  %33 = load i32, ptr %32, align 4, !tbaa !18
  %34 = and i32 %33, 15
  %35 = icmp eq i32 %34, 1
  br i1 %35, label %36, label %37

36:                                               ; preds = %30
  call void @_Z22arm_mix_rgb16_uint16x2PtPKtS1_S1_(ptr noundef %12, ptr noundef %12, ptr noundef %13, ptr noundef %14)
  br label %48

37:                                               ; preds = %30
  call void @llvm.lifetime.start.p0(i64 1, ptr %18) #3
  %38 = load ptr, ptr %11, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.ACIVCX3DecodeInfo, ptr %38, i32 0, i32 2
  %40 = load i32, ptr %39, align 4, !tbaa !18
  %41 = and i32 %40, 8
  %42 = icmp ugt i32 %41, 0
  %43 = zext i1 %42 to i64
  %44 = select i1 %42, i1 false, i1 true
  %45 = zext i1 %44 to i8
  store i8 %45, ptr %18, align 1, !tbaa !19
  %46 = load i8, ptr %18, align 1, !tbaa !19, !range !16, !noundef !17
  %47 = trunc i8 %46 to i1
  call void @_Z23arm_pack_rgb16_uint16x2PtS_PKtS1_b(ptr noundef %12, ptr noundef %12, ptr noundef %13, ptr noundef %14, i1 noundef zeroext %47)
  call void @llvm.lifetime.end.p0(i64 1, ptr %18) #3
  br label %48

48:                                               ; preds = %37, %36
  %49 = load i32, ptr %12, align 4, !tbaa !9
  %50 = load ptr, ptr %17, align 8, !tbaa !5
  store i32 %49, ptr %50, align 4, !tbaa !9
  store i32 0, ptr %9, align 4
  br label %52

51:                                               ; preds = %25
  store i32 100, ptr %9, align 4
  br label %52

52:                                               ; preds = %51, %48, %24
  %53 = load i32, ptr %9, align 4
  ret i32 %53
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 4}
!13 = !{!"_ZTS17ACIVCX3DecodeInfo", !14, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20}
!14 = !{!"bool", !7, i64 0}
!15 = !{!13, !14, i64 0}
!16 = !{i8 0, i8 2}
!17 = !{}
!18 = !{!13, !10, i64 8}
!19 = !{!14, !14, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z22arm_mix_rgb16_uint16x2PtPKtS1_S1_(ptr noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z23arm_pack_rgb16_uint16x2PtS_PKtS1_b(ptr noundef, ptr noundef, ptr noundef, ptr noundef, i1 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN21arm_2d_rgb565_aci_fvp21isCDECoprocessorValidEj(ptr noundef nonnull align 8 dereferenceable(240), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 0, 101) i32 @_ZN21arm_2d_rgb565_aci_fvp18exec_vcx3_beatwiseEPK17ACIVCX3DecodeInfojjjhhPj(ptr noundef nonnull align 8 dereferenceable(240) %0, ptr nocapture noundef readonly %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i8 noundef zeroext %5, i8 noundef zeroext %6, ptr nocapture noundef writeonly %7) local_unnamed_addr #1 align 2 {
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i32 %2, ptr %9, align 4, !tbaa !5
  store i32 %3, ptr %10, align 4, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !5
  %12 = getelementptr inbounds i8, ptr %1, i64 4
  %13 = load i32, ptr %12, align 4, !tbaa !9
  %14 = tail call noundef zeroext i1 @_ZN21arm_2d_rgb565_aci_fvp21isCDECoprocessorValidEj(ptr noundef nonnull align 8 dereferenceable(240) %0, i32 noundef %13)
  br i1 %14, label %15, label %28

15:                                               ; preds = %8
  %16 = load i8, ptr %1, align 4, !tbaa !12, !range !13, !noundef !14
  %17 = trunc nuw i8 %16 to i1
  br i1 %17, label %18, label %28

18:                                               ; preds = %15
  %19 = getelementptr inbounds i8, ptr %1, i64 8
  %20 = load i32, ptr %19, align 4, !tbaa !15
  %21 = and i32 %20, 15
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %23, label %24

23:                                               ; preds = %18
  call void @_Z22arm_mix_rgb16_uint16x2PtPKtS1_S1_(ptr noundef nonnull %9, ptr noundef nonnull %9, ptr noundef nonnull %10, ptr noundef nonnull %11)
  br label %26

24:                                               ; preds = %18
  %25 = and i32 %20, 8
  %.not = icmp eq i32 %25, 0
  call void @_Z23arm_pack_rgb16_uint16x2PtS_PKtS1_b(ptr noundef nonnull %9, ptr noundef nonnull %9, ptr noundef nonnull %10, ptr noundef nonnull %11, i1 noundef zeroext %.not)
  br label %26

26:                                               ; preds = %24, %23
  %27 = load i32, ptr %9, align 4, !tbaa !5
  store i32 %27, ptr %7, align 4, !tbaa !5
  br label %28

28:                                               ; preds = %15, %8, %26
  %.0 = phi i32 [ 0, %26 ], [ 100, %8 ], [ 100, %15 ]
  ret i32 %.0
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 4}
!10 = !{!"_ZTS17ACIVCX3DecodeInfo", !11, i64 0, !6, i64 4, !6, i64 8, !6, i64 12, !6, i64 16, !6, i64 20}
!11 = !{!"bool", !7, i64 0}
!12 = !{!10, !11, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!10, !6, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass