; LLVM IR from rweather/lightweight-crypto :: src/genavr/algorithm_gift128_fixsliced.ll (ZN14Gift128StateFS10rol_nibbleER4CodeRK3Regj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Gift128StateFS = type <{ %class.Reg, %class.Reg, %class.Reg, %class.Reg, %class.Reg, %class.Reg, i8, [7 x i8] }>
%class.Reg = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14Gift128StateFS10rol_nibbleER4CodeRK3Regj(ptr noundef nonnull align 8 dereferenceable(145) %0, ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %3) #1 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %11 = load i32, ptr %8, align 4, !tbaa !9
  %12 = icmp eq i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %4
  store i32 -286331154, ptr %9, align 4, !tbaa !9
  br label %20

14:                                               ; preds = %4
  %15 = load i32, ptr %8, align 4, !tbaa !9
  %16 = icmp eq i32 %15, 2
  br i1 %16, label %17, label %18

17:                                               ; preds = %14
  store i32 -858993460, ptr %9, align 4, !tbaa !9
  br label %19

18:                                               ; preds = %14
  store i32 -2004318072, ptr %9, align 4, !tbaa !9
  br label %19

19:                                               ; preds = %18, %17
  br label %20

20:                                               ; preds = %19, %13
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = getelementptr inbounds %class.Gift128StateFS, ptr %10, i32 0, i32 4
  %23 = load ptr, ptr %7, align 8, !tbaa !5
  call void @_ZN4Code4moveERK3RegS2_b(ptr noundef nonnull align 8 dereferenceable(200) %21, ptr noundef nonnull align 8 dereferenceable(24) %22, ptr noundef nonnull align 8 dereferenceable(24) %23, i1 noundef zeroext false)
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = getelementptr inbounds %class.Gift128StateFS, ptr %10, i32 0, i32 4
  %26 = load i32, ptr %8, align 4, !tbaa !9
  call void @_ZN4Code3lslERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %24, ptr noundef nonnull align 8 dereferenceable(24) %25, i32 noundef %26)
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = getelementptr inbounds %class.Gift128StateFS, ptr %10, i32 0, i32 4
  %29 = load i32, ptr %9, align 4, !tbaa !9
  %30 = zext i32 %29 to i64
  call void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %27, ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %30)
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = load ptr, ptr %7, align 8, !tbaa !5
  %33 = load i32, ptr %8, align 4, !tbaa !9
  %34 = sub i32 4, %33
  call void @_ZN4Code3lsrERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %31, ptr noundef nonnull align 8 dereferenceable(24) %32, i32 noundef %34)
  %35 = load ptr, ptr %6, align 8, !tbaa !5
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = load i32, ptr %9, align 4, !tbaa !9
  %38 = xor i32 %37, -1
  %39 = zext i32 %38 to i64
  call void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %35, ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %39)
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  %42 = getelementptr inbounds %class.Gift128StateFS, ptr %10, i32 0, i32 4
  call void @_ZN4Code5logorERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %40, ptr noundef nonnull align 8 dereferenceable(24) %41, ptr noundef nonnull align 8 dereferenceable(24) %42)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  ret void
}

declare void @_ZN4Code4moveERK3RegS2_b(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i1 noundef zeroext) #2

declare void @_ZN4Code3lslERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

declare void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2

declare void @_ZN4Code3lsrERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

declare void @_ZN4Code5logorERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN14Gift128StateFS10rol_nibbleER4CodeRK3Regj(ptr noundef nonnull align 8 dereferenceable(145) %0, ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %3) local_unnamed_addr #0 align 2 {
  %switch.selectcmp = icmp eq i32 %3, 2
  %switch.select = select i1 %switch.selectcmp, i32 -858993460, i32 -2004318072
  %switch.selectcmp17 = icmp eq i32 %3, 1
  %switch.select18 = select i1 %switch.selectcmp17, i32 -286331154, i32 %switch.select
  %5 = getelementptr inbounds i8, ptr %0, i64 96
  tail call void @_ZN4Code4moveERK3RegS2_b(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %5, ptr noundef nonnull align 8 dereferenceable(24) %2, i1 noundef zeroext false)
  tail call void @_ZN4Code3lslERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %5, i32 noundef %3)
  %6 = zext i32 %switch.select18 to i64
  tail call void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %6)
  %7 = sub i32 4, %3
  tail call void @_ZN4Code3lsrERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %7)
  %8 = xor i32 %switch.select18, -1
  %9 = zext nneg i32 %8 to i64
  tail call void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %9)
  tail call void @_ZN4Code5logorERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(24) %5)
  ret void
}

declare void @_ZN4Code4moveERK3RegS2_b(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i1 noundef zeroext) local_unnamed_addr #1

declare void @_ZN4Code3lslERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

declare void @_ZN4Code6logandERK3Regy(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1

declare void @_ZN4Code3lsrERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

declare void @_ZN4Code5logorERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass