; LLVM IR from chdb-io/chdb :: base/glibc-compatibility/musl/sched_cpucount.ll_ (sched_cpucount)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @__sched_cpucount(i64 noundef %0, ptr noundef %1) #0 {
  %3 = alloca i64, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca ptr, align 8
  store i64 %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #2
  store i64 0, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  %9 = load ptr, ptr %4, align 8, !tbaa !9
  store ptr %9, ptr %8, align 8, !tbaa !9
  store i64 0, ptr %5, align 8, !tbaa !5
  br label %10

10:                                               ; preds = %37, %2
  %11 = load i64, ptr %5, align 8, !tbaa !5
  %12 = load i64, ptr %3, align 8, !tbaa !5
  %13 = icmp ult i64 %11, %12
  br i1 %13, label %14, label %40

14:                                               ; preds = %10
  store i64 0, ptr %6, align 8, !tbaa !5
  br label %15

15:                                               ; preds = %33, %14
  %16 = load i64, ptr %6, align 8, !tbaa !5
  %17 = icmp ult i64 %16, 8
  br i1 %17, label %18, label %36

18:                                               ; preds = %15
  %19 = load ptr, ptr %8, align 8, !tbaa !9
  %20 = load i64, ptr %5, align 8, !tbaa !5
  %21 = getelementptr inbounds i8, ptr %19, i64 %20
  %22 = load i8, ptr %21, align 1, !tbaa !11
  %23 = zext i8 %22 to i32
  %24 = load i64, ptr %6, align 8, !tbaa !5
  %25 = trunc i64 %24 to i32
  %26 = shl i32 1, %25
  %27 = and i32 %23, %26
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %29, label %32

29:                                               ; preds = %18
  %30 = load i64, ptr %7, align 8, !tbaa !5
  %31 = add i64 %30, 1
  store i64 %31, ptr %7, align 8, !tbaa !5
  br label %32

32:                                               ; preds = %29, %18
  br label %33

33:                                               ; preds = %32
  %34 = load i64, ptr %6, align 8, !tbaa !5
  %35 = add i64 %34, 1
  store i64 %35, ptr %6, align 8, !tbaa !5
  br label %15, !llvm.loop !12

36:                                               ; preds = %15
  br label %37

37:                                               ; preds = %36
  %38 = load i64, ptr %5, align 8, !tbaa !5
  %39 = add i64 %38, 1
  store i64 %39, ptr %5, align 8, !tbaa !5
  br label %10, !llvm.loop !14

40:                                               ; preds = %10
  %41 = load i64, ptr %7, align 8, !tbaa !5
  %42 = trunc i64 %41 to i32
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #2
  ret i32 %42
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) uwtable
define dso_local i32 @__sched_cpucount(i64 noundef %0, ptr nocapture noundef readonly %1) local_unnamed_addr #0 {
  %.not16 = icmp eq i64 %0, 0
  br i1 %.not16, label %._crit_edge, label %.preheader.preheader

.preheader.preheader:                             ; preds = %2
  %min.iters.check = icmp ult i64 %0, 8
  br i1 %min.iters.check, label %.preheader.preheader19, label %vector.ph

vector.ph:                                        ; preds = %.preheader.preheader
  %n.vec = and i64 %0, -8
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %49, %vector.body ]
  %vec.phi17 = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %50, %vector.body ]
  %3 = getelementptr inbounds i8, ptr %1, i64 %index
  %4 = getelementptr inbounds i8, ptr %3, i64 4
  %wide.load = load <4 x i8>, ptr %3, align 1, !tbaa !5
  %wide.load18 = load <4 x i8>, ptr %4, align 1, !tbaa !5
  %5 = zext <4 x i8> %wide.load to <4 x i32>
  %6 = zext <4 x i8> %wide.load18 to <4 x i32>
  %7 = and <4 x i32> %5, <i32 1, i32 1, i32 1, i32 1>
  %8 = and <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>
  %9 = add <4 x i32> %7, %vec.phi
  %10 = add <4 x i32> %8, %vec.phi17
  %11 = lshr <4 x i32> %5, <i32 1, i32 1, i32 1, i32 1>
  %12 = lshr <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>
  %13 = and <4 x i32> %11, <i32 1, i32 1, i32 1, i32 1>
  %14 = and <4 x i32> %12, <i32 1, i32 1, i32 1, i32 1>
  %15 = add <4 x i32> %13, %9
  %16 = add <4 x i32> %14, %10
  %17 = lshr <4 x i32> %5, <i32 2, i32 2, i32 2, i32 2>
  %18 = lshr <4 x i32> %6, <i32 2, i32 2, i32 2, i32 2>
  %19 = and <4 x i32> %17, <i32 1, i32 1, i32 1, i32 1>
  %20 = and <4 x i32> %18, <i32 1, i32 1, i32 1, i32 1>
  %21 = add <4 x i32> %19, %15
  %22 = add <4 x i32> %20, %16
  %23 = lshr <4 x i32> %5, <i32 3, i32 3, i32 3, i32 3>
  %24 = lshr <4 x i32> %6, <i32 3, i32 3, i32 3, i32 3>
  %25 = and <4 x i32> %23, <i32 1, i32 1, i32 1, i32 1>
  %26 = and <4 x i32> %24, <i32 1, i32 1, i32 1, i32 1>
  %27 = add <4 x i32> %25, %21
  %28 = add <4 x i32> %26, %22
  %29 = lshr <4 x i32> %5, <i32 4, i32 4, i32 4, i32 4>
  %30 = lshr <4 x i32> %6, <i32 4, i32 4, i32 4, i32 4>
  %31 = and <4 x i32> %29, <i32 1, i32 1, i32 1, i32 1>
  %32 = and <4 x i32> %30, <i32 1, i32 1, i32 1, i32 1>
  %33 = add <4 x i32> %31, %27
  %34 = add <4 x i32> %32, %28
  %35 = lshr <4 x i32> %5, <i32 5, i32 5, i32 5, i32 5>
  %36 = lshr <4 x i32> %6, <i32 5, i32 5, i32 5, i32 5>
  %37 = and <4 x i32> %35, <i32 1, i32 1, i32 1, i32 1>
  %38 = and <4 x i32> %36, <i32 1, i32 1, i32 1, i32 1>
  %39 = add <4 x i32> %37, %33
  %40 = add <4 x i32> %38, %34
  %41 = lshr <4 x i32> %5, <i32 6, i32 6, i32 6, i32 6>
  %42 = lshr <4 x i32> %6, <i32 6, i32 6, i32 6, i32 6>
  %43 = and <4 x i32> %41, <i32 1, i32 1, i32 1, i32 1>
  %44 = and <4 x i32> %42, <i32 1, i32 1, i32 1, i32 1>
  %45 = add <4 x i32> %43, %39
  %46 = add <4 x i32> %44, %40
  %47 = lshr <4 x i32> %5, <i32 7, i32 7, i32 7, i32 7>
  %48 = lshr <4 x i32> %6, <i32 7, i32 7, i32 7, i32 7>
  %49 = add <4 x i32> %47, %45
  %50 = add <4 x i32> %48, %46
  %index.next = add nuw i64 %index, 8
  %51 = icmp eq i64 %index.next, %n.vec
  br i1 %51, label %middle.block, label %vector.body, !llvm.loop !8

middle.block:                                     ; preds = %vector.body
  %bin.rdx = add <4 x i32> %50, %49
  %52 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
  %cmp.n = icmp eq i64 %n.vec, %0
  br i1 %cmp.n, label %._crit_edge, label %.preheader.preheader19

.preheader.preheader19:                           ; preds = %middle.block, %.preheader.preheader
  %.015.ph = phi i64 [ 0, %.preheader.preheader ], [ %n.vec, %middle.block ]
  %.01014.ph = phi i32 [ 0, %.preheader.preheader ], [ %52, %middle.block ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader19, %.preheader
  %.015 = phi i64 [ %70, %.preheader ], [ %.015.ph, %.preheader.preheader19 ]
  %.01014 = phi i32 [ %spec.select.7, %.preheader ], [ %.01014.ph, %.preheader.preheader19 ]
  %53 = getelementptr inbounds i8, ptr %1, i64 %.015
  %54 = load i8, ptr %53, align 1, !tbaa !5
  %55 = zext i8 %54 to i32
  %56 = and i32 %55, 1
  %spec.select = add i32 %56, %.01014
  %57 = lshr i32 %55, 1
  %58 = and i32 %57, 1
  %spec.select.1 = add i32 %58, %spec.select
  %59 = lshr i32 %55, 2
  %60 = and i32 %59, 1
  %spec.select.2 = add i32 %60, %spec.select.1
  %61 = lshr i32 %55, 3
  %62 = and i32 %61, 1
  %spec.select.3 = add i32 %62, %spec.select.2
  %63 = lshr i32 %55, 4
  %64 = and i32 %63, 1
  %spec.select.4 = add i32 %64, %spec.select.3
  %65 = lshr i32 %55, 5
  %66 = and i32 %65, 1
  %spec.select.5 = add i32 %66, %spec.select.4
  %67 = lshr i32 %55, 6
  %68 = and i32 %67, 1
  %spec.select.6 = add i32 %68, %spec.select.5
  %69 = lshr i32 %55, 7
  %spec.select.7 = add i32 %69, %spec.select.6
  %70 = add nuw i64 %.015, 1
  %exitcond.not = icmp eq i64 %70, %0
  br i1 %exitcond.not, label %._crit_edge, label %.preheader, !llvm.loop !12

._crit_edge:                                      ; preds = %.preheader, %middle.block, %2
  %.010.lcssa = phi i32 [ 0, %2 ], [ %52, %middle.block ], [ %spec.select.7, %.preheader ]
  ret i32 %.010.lcssa
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #1

attributes #0 = { nofree norecurse nosync nounwind memory(argmem: read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9, !10, !11}
!9 = !{!"llvm.loop.mustprogress"}
!10 = !{!"llvm.loop.isvectorized", i32 1}
!11 = !{!"llvm.loop.unroll.runtime.disable"}
!12 = distinct !{!12, !9, !11, !10}


; Effective O3 passes: AggressiveInstCombinePass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass