; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code13moveHighFirstERK3RegS2_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code13moveHighFirstERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %9 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %10)
  store i32 %11, ptr %8, align 4, !tbaa !9
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12)
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = icmp slt i32 %13, %14
  br i1 %15, label %16, label %19

16:                                               ; preds = %3
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17)
  store i32 %18, ptr %8, align 4, !tbaa !9
  br label %19

19:                                               ; preds = %16, %3
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = sub nsw i32 %20, 1
  store i32 %21, ptr %7, align 4, !tbaa !9
  br label %22

22:                                               ; preds = %101, %19
  %23 = load i32, ptr %7, align 4, !tbaa !9
  %24 = icmp sge i32 %23, 0
  br i1 %24, label %25, label %104

25:                                               ; preds = %22
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %26, i32 noundef %27)
  %29 = zext i8 %28 to i32
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = load i32, ptr %7, align 4, !tbaa !9
  %32 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %30, i32 noundef %31)
  %33 = zext i8 %32 to i32
  %34 = icmp eq i32 %29, %33
  br i1 %34, label %35, label %36

35:                                               ; preds = %25
  br label %101

36:                                               ; preds = %25
  %37 = load ptr, ptr %5, align 8, !tbaa !5
  %38 = load i32, ptr %7, align 4, !tbaa !9
  %39 = sub nsw i32 %38, 1
  %40 = call noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %37, i32 noundef %39)
  br i1 %40, label %41, label %65

41:                                               ; preds = %36
  %42 = load ptr, ptr %6, align 8, !tbaa !5
  %43 = load i32, ptr %7, align 4, !tbaa !9
  %44 = sub nsw i32 %43, 1
  %45 = call noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %42, i32 noundef %44)
  br i1 %45, label %46, label %65

46:                                               ; preds = %41
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = sub nsw i32 %49, 1
  %51 = call noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24) %47, ptr noundef nonnull align 8 dereferenceable(24) %48, i32 noundef %50)
  br i1 %51, label %52, label %65

52:                                               ; preds = %46
  %53 = call noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200) %9, i32 noundef 1)
  br i1 %53, label %54, label %65

54:                                               ; preds = %52
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = load i32, ptr %7, align 4, !tbaa !9
  %57 = sub nsw i32 %56, 1
  %58 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %55, i32 noundef %57)
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = load i32, ptr %7, align 4, !tbaa !9
  %61 = sub nsw i32 %60, 1
  %62 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %59, i32 noundef %61)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %9, i32 noundef 35, i8 noundef zeroext %58, i8 noundef zeroext %62)
  %63 = load i32, ptr %7, align 4, !tbaa !9
  %64 = add nsw i32 %63, -1
  store i32 %64, ptr %7, align 4, !tbaa !9
  br label %100

65:                                               ; preds = %52, %46, %41, %36
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = load i32, ptr %7, align 4, !tbaa !9
  %68 = sub nsw i32 %67, 1
  %69 = call noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %66, i32 noundef %68)
  br i1 %69, label %70, label %92

70:                                               ; preds = %65
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = load i32, ptr %7, align 4, !tbaa !9
  %73 = sub nsw i32 %72, 1
  %74 = call noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %71, i32 noundef %73)
  br i1 %74, label %75, label %92

75:                                               ; preds = %70
  %76 = load ptr, ptr %5, align 8, !tbaa !5
  %77 = load ptr, ptr %6, align 8, !tbaa !5
  %78 = load i32, ptr %7, align 4, !tbaa !9
  %79 = sub nsw i32 %78, 1
  %80 = call noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24) %76, ptr noundef nonnull align 8 dereferenceable(24) %77, i32 noundef %79)
  br i1 %80, label %81, label %92

81:                                               ; preds = %75
  %82 = call noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200) %9, i32 noundef 1)
  br i1 %82, label %83, label %92

83:                                               ; preds = %81
  %84 = load ptr, ptr %5, align 8, !tbaa !5
  %85 = load i32, ptr %7, align 4, !tbaa !9
  %86 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %84, i32 noundef %85)
  %87 = load ptr, ptr %6, align 8, !tbaa !5
  %88 = load i32, ptr %7, align 4, !tbaa !9
  %89 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %87, i32 noundef %88)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %9, i32 noundef 35, i8 noundef zeroext %86, i8 noundef zeroext %89)
  %90 = load i32, ptr %7, align 4, !tbaa !9
  %91 = add nsw i32 %90, -1
  store i32 %91, ptr %7, align 4, !tbaa !9
  br label %99

92:                                               ; preds = %81, %75, %70, %65
  %93 = load ptr, ptr %5, align 8, !tbaa !5
  %94 = load i32, ptr %7, align 4, !tbaa !9
  %95 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %93, i32 noundef %94)
  %96 = load ptr, ptr %6, align 8, !tbaa !5
  %97 = load i32, ptr %7, align 4, !tbaa !9
  %98 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %96, i32 noundef %97)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %9, i32 noundef 34, i8 noundef zeroext %95, i8 noundef zeroext %98)
  br label %99

99:                                               ; preds = %92, %83
  br label %100

100:                                              ; preds = %99, %54
  br label %101

101:                                              ; preds = %100, %35
  %102 = load i32, ptr %7, align 4, !tbaa !9
  %103 = add nsw i32 %102, -1
  store i32 %103, ptr %7, align 4, !tbaa !9
  br label %22, !llvm.loop !11

104:                                              ; preds = %22
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret void
}

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code13moveHighFirstERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #1 align 2 {
  %4 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %5 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %6 = icmp slt i32 %5, %4
  br i1 %6, label %7, label %9

7:                                                ; preds = %3
  %8 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  br label %9

9:                                                ; preds = %7, %3
  %.0 = phi i32 [ %8, %7 ], [ %4, %3 ]
  %10 = icmp sgt i32 %.0, 0
  br i1 %10, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %9, %34
  %.039.in42 = phi i32 [ %.1, %34 ], [ %.0, %9 ]
  %.03943 = add nsw i32 %.039.in42, -1
  %11 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.03943)
  %12 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %.03943)
  %13 = icmp eq i8 %11, %12
  br i1 %13, label %34, label %14

14:                                               ; preds = %.lr.ph
  %15 = add nsw i32 %.039.in42, -2
  %16 = tail call noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %15)
  br i1 %16, label %17, label %23

17:                                               ; preds = %14
  %18 = tail call noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %15)
  br i1 %18, label %19, label %23

19:                                               ; preds = %17
  %20 = tail call noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %15)
  br i1 %20, label %21, label %23

21:                                               ; preds = %19
  %22 = tail call noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 1)
  br i1 %22, label %.sink.split, label %23

23:                                               ; preds = %21, %19, %17, %14
  %24 = tail call noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %15)
  br i1 %24, label %25, label %31

25:                                               ; preds = %23
  %26 = tail call noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %15)
  br i1 %26, label %27, label %31

27:                                               ; preds = %25
  %28 = tail call noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %15)
  br i1 %28, label %29, label %31

29:                                               ; preds = %27
  %30 = tail call noundef zeroext i1 @_ZNK4Code7hasFlagENS_4FlagE(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 1)
  br i1 %30, label %.sink.split, label %31

31:                                               ; preds = %29, %27, %25, %23
  br label %.sink.split

.sink.split:                                      ; preds = %29, %21, %31
  %.sink47 = phi i32 [ %.03943, %31 ], [ %15, %21 ], [ %.03943, %29 ]
  %.sink = phi i32 [ 34, %31 ], [ 35, %21 ], [ 35, %29 ]
  %.1.ph = phi i32 [ %.03943, %31 ], [ %15, %21 ], [ %15, %29 ]
  %32 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.sink47)
  %33 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %.sink47)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %.sink, i8 noundef zeroext %32, i8 noundef zeroext %33)
  br label %34

34:                                               ; preds = %.sink.split, %.lr.ph
  %.1 = phi i32 [ %.03943, %.lr.ph ], [ %.1.ph, %.sink.split ]
  %35 = icmp sgt i32 %.1, 0
  br i1 %35, label %.lr.ph, label %._crit_edge, !llvm.loop !5

._crit_edge:                                      ; preds = %34, %9
  ret void
}

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL9isRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL12isRevRegPairRK3Regi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZL9noOverlapRK3RegS1_i(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass