; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code5logorERK3Regy)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code5logorERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i64 %2, ptr %6, align 8, !tbaa !9
  %11 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !11
  br label %12

12:                                               ; preds = %70, %3
  %13 = load i32, ptr %7, align 4, !tbaa !11
  %14 = load ptr, ptr %5, align 8, !tbaa !5
  %15 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14)
  %16 = icmp slt i32 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %73

18:                                               ; preds = %12
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  %19 = load i64, ptr %6, align 8, !tbaa !9
  %20 = trunc i64 %19 to i8
  store i8 %20, ptr %8, align 1, !tbaa !13
  %21 = load i8, ptr %8, align 1, !tbaa !13
  %22 = zext i8 %21 to i32
  %23 = icmp eq i32 %22, 255
  br i1 %23, label %24, label %43

24:                                               ; preds = %18
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = load i32, ptr %7, align 4, !tbaa !11
  %27 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %25, i32 noundef %26)
  %28 = zext i8 %27 to i32
  %29 = icmp sge i32 %28, 16
  br i1 %29, label %30, label %35

30:                                               ; preds = %24
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = load i32, ptr %7, align 4, !tbaa !11
  %33 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %31, i32 noundef %32)
  %34 = load i8, ptr %8, align 1, !tbaa !13
  call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %11, i32 noundef 26, i8 noundef zeroext %33, i8 noundef zeroext %34)
  br label %42

35:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  %36 = load i8, ptr %8, align 1, !tbaa !13
  %37 = call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %11, i8 noundef zeroext %36)
  store i8 %37, ptr %9, align 1, !tbaa !13
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = load i32, ptr %7, align 4, !tbaa !11
  %40 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %38, i32 noundef %39)
  %41 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %11, i32 noundef 34, i8 noundef zeroext %40, i8 noundef zeroext %41)
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  br label %42

42:                                               ; preds = %35, %30
  br label %67

43:                                               ; preds = %18
  %44 = load i8, ptr %8, align 1, !tbaa !13
  %45 = zext i8 %44 to i32
  %46 = icmp ne i32 %45, 0
  br i1 %46, label %47, label %66

47:                                               ; preds = %43
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = load i32, ptr %7, align 4, !tbaa !11
  %50 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %48, i32 noundef %49)
  %51 = zext i8 %50 to i32
  %52 = icmp sge i32 %51, 16
  br i1 %52, label %53, label %58

53:                                               ; preds = %47
  %54 = load ptr, ptr %5, align 8, !tbaa !5
  %55 = load i32, ptr %7, align 4, !tbaa !11
  %56 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %54, i32 noundef %55)
  %57 = load i8, ptr %8, align 1, !tbaa !13
  call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %11, i32 noundef 39, i8 noundef zeroext %56, i8 noundef zeroext %57)
  br label %65

58:                                               ; preds = %47
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  %59 = load i8, ptr %8, align 1, !tbaa !13
  %60 = call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %11, i8 noundef zeroext %59)
  store i8 %60, ptr %10, align 1, !tbaa !13
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = load i32, ptr %7, align 4, !tbaa !11
  %63 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %61, i32 noundef %62)
  %64 = load i8, ptr %10, align 1, !tbaa !13
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %11, i32 noundef 38, i8 noundef zeroext %63, i8 noundef zeroext %64)
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  br label %65

65:                                               ; preds = %58, %53
  br label %66

66:                                               ; preds = %65, %43
  br label %67

67:                                               ; preds = %66, %42
  %68 = load i64, ptr %6, align 8, !tbaa !9
  %69 = lshr i64 %68, 8
  store i64 %69, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  br label %70

70:                                               ; preds = %67
  %71 = load i32, ptr %7, align 4, !tbaa !11
  %72 = add nsw i32 %71, 1
  store i32 %72, ptr %7, align 4, !tbaa !11
  br label %12, !llvm.loop !14

73:                                               ; preds = %17
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code5logorERK3Regy(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2) local_unnamed_addr #1 align 2 {
  %4 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %5 = icmp sgt i32 %4, 0
  br i1 %5, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %23, %3
  ret void

.lr.ph:                                           ; preds = %3, %23
  %.028 = phi i64 [ %24, %23 ], [ %2, %3 ]
  %.02527 = phi i32 [ %25, %23 ], [ 0, %3 ]
  %6 = trunc i64 %.028 to i8
  switch i8 %6, label %15 [
    i8 -1, label %7
    i8 0, label %23
  ]

7:                                                ; preds = %.lr.ph
  %8 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  %9 = icmp ugt i8 %8, 15
  br i1 %9, label %10, label %12

10:                                               ; preds = %7
  %11 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  tail call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 26, i8 noundef zeroext %11, i8 noundef zeroext -1)
  br label %23

12:                                               ; preds = %7
  %13 = tail call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext -1)
  %14 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 34, i8 noundef zeroext %14, i8 noundef zeroext %13)
  br label %23

15:                                               ; preds = %.lr.ph
  %16 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  %17 = icmp ugt i8 %16, 15
  br i1 %17, label %18, label %20

18:                                               ; preds = %15
  %19 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  tail call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 39, i8 noundef zeroext %19, i8 noundef zeroext %6)
  br label %23

20:                                               ; preds = %15
  %21 = tail call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext %6)
  %22 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.02527)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 38, i8 noundef zeroext %22, i8 noundef zeroext %21)
  br label %23

23:                                               ; preds = %.lr.ph, %20, %18, %10, %12
  %24 = lshr i64 %.028, 8
  %25 = add nuw nsw i32 %.02527, 1
  %26 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %27 = icmp slt i32 %25, %26
  br i1 %27, label %.lr.ph, label %._crit_edge, !llvm.loop !5
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass