; LLVM IR from ARM-software/Arm-2D :: Acceleration/Arm/ACI/arm_2d_rgb565_aci_fvp_plugin (arm_2d_rgb565_aci_fvp)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::valarray" = type { i64, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_Z19uint32x1_to_uint8x4j(ptr dead_on_unwind noalias writable sret(%"class.std::valarray") align 8 %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i1, align 1
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8
  store i32 %1, ptr %4, align 4, !tbaa !5
  store i1 false, ptr %5, align 1
  call void @_ZNSt8valarrayIhEC2Em(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 4)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %7

7:                                                ; preds = %21, %2
  %8 = load i32, ptr %6, align 4, !tbaa !5
  %9 = icmp slt i32 %8, 4
  br i1 %9, label %11, label %10

10:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  br label %24

11:                                               ; preds = %7
  %12 = load i32, ptr %4, align 4, !tbaa !5
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = mul nsw i32 %13, 8
  %15 = lshr i32 %12, %14
  %16 = and i32 %15, 255
  %17 = trunc i32 %16 to i8
  %18 = load i32, ptr %6, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef %19) #4
  store i8 %17, ptr %20, align 1, !tbaa !9
  br label %21

21:                                               ; preds = %11
  %22 = load i32, ptr %6, align 4, !tbaa !5
  %23 = add nsw i32 %22, 1
  store i32 %23, ptr %6, align 4, !tbaa !5
  br label %7, !llvm.loop !10

24:                                               ; preds = %10
  store i1 true, ptr %5, align 1
  %25 = load i1, ptr %5, align 1
  br i1 %25, label %27, label %26

26:                                               ; preds = %24
  call void @_ZNSt8valarrayIhED2Ev(ptr noundef nonnull align 8 dereferenceable(16) %0) #4
  br label %27

27:                                               ; preds = %26, %24
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZNSt8valarrayIhEC2Em(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) #3 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNSt8valarrayIhED2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::valarray" = type { i64, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_Z19uint32x1_to_uint8x4j(ptr dead_on_unwind noalias nonnull writable sret(%"class.std::valarray") align 8 %0, i32 noundef %1) local_unnamed_addr #0 {
  tail call void @_ZNSt8valarrayIhEC2Em(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 4)
  %3 = trunc i32 %1 to i8
  %4 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 0) #3
  store i8 %3, ptr %4, align 1, !tbaa !5
  %5 = lshr i32 %1, 8
  %6 = trunc i32 %5 to i8
  %7 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 1) #3
  store i8 %6, ptr %7, align 1, !tbaa !5
  %8 = lshr i32 %1, 16
  %9 = trunc i32 %8 to i8
  %10 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 2) #3
  store i8 %9, ptr %10, align 1, !tbaa !5
  %11 = lshr i32 %1, 24
  %12 = trunc nuw i32 %11 to i8
  %13 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 noundef 3) #3
  store i8 %12, ptr %13, align 1, !tbaa !5
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZNSt8valarrayIhEC2Em(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt8valarrayIhEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass