; LLVM IR from FedericaPaoli1/stm32-speech-recognition-and-traduction :: Drivers/CMSIS/DSP/Source/StatisticsFunctions (arm_var_q31)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @arm_var_q31(ptr noundef %0, i32 noundef %1, ptr noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  store i64 0, ptr %8, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #2
  store i64 0, ptr %11, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  %14 = load i32, ptr %5, align 4, !tbaa !9
  %15 = icmp ule i32 %14, 1
  br i1 %15, label %16, label %18

16:                                               ; preds = %3
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  store i32 0, ptr %17, align 4, !tbaa !9
  store i32 1, ptr %13, align 4
  br label %62

18:                                               ; preds = %3
  %19 = load i32, ptr %5, align 4, !tbaa !9
  store i32 %19, ptr %7, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %23, %18
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = icmp ugt i32 %21, 0
  br i1 %22, label %23, label %41

23:                                               ; preds = %20
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds i32, ptr %24, i32 1
  store ptr %25, ptr %4, align 8, !tbaa !5
  %26 = load i32, ptr %24, align 4, !tbaa !9
  %27 = ashr i32 %26, 8
  store i32 %27, ptr %12, align 4, !tbaa !9
  %28 = load i32, ptr %12, align 4, !tbaa !9
  %29 = sext i32 %28 to i64
  %30 = load i32, ptr %12, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = mul nsw i64 %29, %31
  %33 = load i64, ptr %11, align 8, !tbaa !11
  %34 = add nsw i64 %33, %32
  store i64 %34, ptr %11, align 8, !tbaa !11
  %35 = load i32, ptr %12, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = load i64, ptr %8, align 8, !tbaa !11
  %38 = add nsw i64 %37, %36
  store i64 %38, ptr %8, align 8, !tbaa !11
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = add i32 %39, -1
  store i32 %40, ptr %7, align 4, !tbaa !9
  br label %20, !llvm.loop !13

41:                                               ; preds = %20
  %42 = load i64, ptr %11, align 8, !tbaa !11
  %43 = load i32, ptr %5, align 4, !tbaa !9
  %44 = sub i32 %43, 1
  %45 = zext i32 %44 to i64
  %46 = sdiv i64 %42, %45
  store i64 %46, ptr %9, align 8, !tbaa !11
  %47 = load i64, ptr %8, align 8, !tbaa !11
  %48 = load i64, ptr %8, align 8, !tbaa !11
  %49 = mul nsw i64 %47, %48
  %50 = load i32, ptr %5, align 4, !tbaa !9
  %51 = load i32, ptr %5, align 4, !tbaa !9
  %52 = sub i32 %51, 1
  %53 = mul i32 %50, %52
  %54 = zext i32 %53 to i64
  %55 = sdiv i64 %49, %54
  store i64 %55, ptr %10, align 8, !tbaa !11
  %56 = load i64, ptr %9, align 8, !tbaa !11
  %57 = load i64, ptr %10, align 8, !tbaa !11
  %58 = sub nsw i64 %56, %57
  %59 = ashr i64 %58, 15
  %60 = trunc i64 %59 to i32
  %61 = load ptr, ptr %6, align 8, !tbaa !5
  store i32 %60, ptr %61, align 4, !tbaa !9
  store i32 0, ptr %13, align 4
  br label %62

62:                                               ; preds = %41, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  %63 = load i32, ptr %13, align 4
  switch i32 %63, label %65 [
    i32 0, label %64
    i32 1, label %64
  ]

64:                                               ; preds = %62, %62
  ret void

65:                                               ; preds = %62
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable
define dso_local void @arm_var_q31(ptr nocapture noundef readonly %0, i32 noundef %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 {
  %4 = icmp ult i32 %1, 2
  br i1 %4, label %39, label %.preheader.preheader

.preheader.preheader:                             ; preds = %3
  %5 = zext i32 %1 to i64
  %min.iters.check = icmp ult i32 %1, 4
  br i1 %min.iters.check, label %.preheader.preheader39, label %vector.ph

vector.ph:                                        ; preds = %.preheader.preheader
  %n.vec = and i64 %5, 4294967292
  %6 = shl nuw nsw i64 %n.vec, 2
  %ind.end = getelementptr i8, ptr %0, i64 %6
  %.cast = trunc nuw i64 %n.vec to i32
  %ind.end30 = sub i32 %1, %.cast
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %vec.phi = phi <2 x i64> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
  %vec.phi32 = phi <2 x i64> [ zeroinitializer, %vector.ph ], [ %15, %vector.body ]
  %vec.phi33 = phi <2 x i64> [ zeroinitializer, %vector.ph ], [ %16, %vector.body ]
  %vec.phi34 = phi <2 x i64> [ zeroinitializer, %vector.ph ], [ %17, %vector.body ]
  %offset.idx = shl i64 %index, 2
  %next.gep = getelementptr i8, ptr %0, i64 %offset.idx
  %7 = getelementptr i8, ptr %next.gep, i64 8
  %wide.load = load <2 x i32>, ptr %next.gep, align 4, !tbaa !5
  %wide.load36 = load <2 x i32>, ptr %7, align 4, !tbaa !5
  %8 = ashr <2 x i32> %wide.load, <i32 8, i32 8>
  %9 = ashr <2 x i32> %wide.load36, <i32 8, i32 8>
  %10 = sext <2 x i32> %8 to <2 x i64>
  %11 = sext <2 x i32> %9 to <2 x i64>
  %12 = mul nsw <2 x i64> %10, %10
  %13 = mul nsw <2 x i64> %11, %11
  %14 = add <2 x i64> %12, %vec.phi
  %15 = add <2 x i64> %13, %vec.phi32
  %16 = add <2 x i64> %vec.phi33, %10
  %17 = add <2 x i64> %vec.phi34, %11
  %index.next = add nuw i64 %index, 4
  %18 = icmp eq i64 %index.next, %n.vec
  br i1 %18, label %middle.block, label %vector.body, !llvm.loop !9

middle.block:                                     ; preds = %vector.body
  %bin.rdx = add <2 x i64> %15, %14
  %19 = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
  %bin.rdx37 = add <2 x i64> %17, %16
  %20 = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %bin.rdx37)
  %cmp.n = icmp eq i64 %n.vec, %5
  br i1 %cmp.n, label %.loopexit, label %.preheader.preheader39

.preheader.preheader39:                           ; preds = %middle.block, %.preheader.preheader
  %.026.ph = phi ptr [ %0, %.preheader.preheader ], [ %ind.end, %middle.block ]
  %.01925.ph = phi i64 [ 0, %.preheader.preheader ], [ %19, %middle.block ]
  %.02024.ph = phi i32 [ %1, %.preheader.preheader ], [ %ind.end30, %middle.block ]
  %.02123.ph = phi i64 [ 0, %.preheader.preheader ], [ %20, %middle.block ]
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader39, %.preheader
  %.026 = phi ptr [ %21, %.preheader ], [ %.026.ph, %.preheader.preheader39 ]
  %.01925 = phi i64 [ %26, %.preheader ], [ %.01925.ph, %.preheader.preheader39 ]
  %.02024 = phi i32 [ %28, %.preheader ], [ %.02024.ph, %.preheader.preheader39 ]
  %.02123 = phi i64 [ %27, %.preheader ], [ %.02123.ph, %.preheader.preheader39 ]
  %21 = getelementptr inbounds i8, ptr %.026, i64 4
  %22 = load i32, ptr %.026, align 4, !tbaa !5
  %23 = ashr i32 %22, 8
  %24 = sext i32 %23 to i64
  %25 = mul nsw i64 %24, %24
  %26 = add nuw nsw i64 %25, %.01925
  %27 = add nsw i64 %.02123, %24
  %28 = add i32 %.02024, -1
  %.not = icmp eq i32 %28, 0
  br i1 %.not, label %.loopexit, label %.preheader, !llvm.loop !13

.loopexit:                                        ; preds = %.preheader, %middle.block
  %.lcssa29 = phi i64 [ %19, %middle.block ], [ %26, %.preheader ]
  %.lcssa = phi i64 [ %20, %middle.block ], [ %27, %.preheader ]
  %29 = add i32 %1, -1
  %30 = zext i32 %29 to i64
  %31 = udiv i64 %.lcssa29, %30
  %32 = mul nsw i64 %.lcssa, %.lcssa
  %33 = mul i32 %29, %1
  %34 = zext i32 %33 to i64
  %35 = udiv i64 %32, %34
  %36 = sub nsw i64 %31, %35
  %37 = lshr i64 %36, 15
  %38 = trunc i64 %37 to i32
  br label %39

39:                                               ; preds = %3, %.loopexit
  %storemerge = phi i32 [ %38, %.loopexit ], [ 0, %3 ]
  store i32 %storemerge, ptr %2, align 4, !tbaa !5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) #1

attributes #0 = { nofree norecurse nosync nounwind memory(read, argmem: readwrite, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10, !11, !12}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!"llvm.loop.isvectorized", i32 1}
!12 = !{!"llvm.loop.unroll.runtime.disable"}
!13 = distinct !{!13, !10, !12, !11}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass