; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code19allocateExplicitRegEhj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Reg = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.Code = type { %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector", i32, i32, i32, i32, [16 x i8], i32, i32, i32, %"class.std::__cxx11::basic_string", %"class.std::map" }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<Insn, std::allocator<Insn>>::_Vector_impl" }
%"struct.std::_Vector_base<Insn, std::allocator<Insn>>::_Vector_impl" = type { %"struct.std::_Vector_base<Insn, std::allocator<Insn>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Insn, std::allocator<Insn>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon.13 }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon.13 = type { i64, [8 x i8] }
%"class.std::map" = type { %"class.std::_Rb_tree" }
%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<unsigned char, std::pair<const unsigned char, Sbox>, std::_Select1st<std::pair<const unsigned char, Sbox>>, std::less<unsigned char>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<unsigned char, std::pair<const unsigned char, Sbox>, std::_Select1st<std::pair<const unsigned char, Sbox>>, std::less<unsigned char>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"struct.std::_Rb_tree_header" = type { %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::_Rb_tree_node_base" = type { i32, ptr, ptr, ptr }

@_ZTISt14overflow_error = external constant ptr
@.str.20 = external hidden unnamed_addr constant [35 x i8], align 1

declare ptr @__cxa_allocate_exception(i64)

declare i32 @__gxx_personality_v0(...)

declare void @__cxa_free_exception(ptr)

declare void @__cxa_throw(ptr, ptr, ptr)

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 1 dereferenceable(1)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3RegC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3RegD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code19allocateExplicitRegEhj(ptr dead_on_unwind noalias writable sret(%class.Reg) align 8 %0, ptr noundef nonnull align 8 dereferenceable(200) %1, i8 noundef zeroext %2, i32 noundef %3) #0 align 2 personality ptr @__gxx_personality_v0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca i1, align 1
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i8 %2, ptr %7, align 1, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !10
  %12 = load ptr, ptr %6, align 8
  store i1 false, ptr %9, align 1
  call void @_ZN3RegC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0)
  br label %13

13:                                               ; preds = %49, %4
  %14 = load i32, ptr %8, align 4, !tbaa !10
  %15 = icmp ugt i32 %14, 0
  br i1 %15, label %16, label %54

16:                                               ; preds = %13
  %17 = getelementptr inbounds %class.Code, ptr %12, i32 0, i32 3
  %18 = load i32, ptr %17, align 8, !tbaa !12
  %19 = load i8, ptr %7, align 1, !tbaa !9
  %20 = zext i8 %19 to i32
  %21 = shl i32 1, %20
  %22 = and i32 %18, %21
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %24, label %35

24:                                               ; preds = %16
  %25 = call ptr @__cxa_allocate_exception(i64 16) #4
  invoke void @_ZNSt14overflow_errorC1EPKc(ptr noundef nonnull align 8 dereferenceable(16) %25, ptr noundef @.str.20)
          to label %26 unwind label %27

26:                                               ; preds = %24
  invoke void @__cxa_throw(ptr %25, ptr @_ZTISt14overflow_error, ptr @_ZNSt14overflow_errorD1Ev) #5
          to label %64 unwind label %31

27:                                               ; preds = %24
  %28 = landingpad { ptr, i32 }
          cleanup
  %29 = extractvalue { ptr, i32 } %28, 0
  store ptr %29, ptr %10, align 8
  %30 = extractvalue { ptr, i32 } %28, 1
  store i32 %30, ptr %11, align 4
  call void @__cxa_free_exception(ptr %25) #4
  br label %58

31:                                               ; preds = %35, %26
  %32 = landingpad { ptr, i32 }
          cleanup
  %33 = extractvalue { ptr, i32 } %32, 0
  store ptr %33, ptr %10, align 8
  %34 = extractvalue { ptr, i32 } %32, 1
  store i32 %34, ptr %11, align 4
  br label %58

35:                                               ; preds = %16
  %36 = load i8, ptr %7, align 1, !tbaa !9
  %37 = zext i8 %36 to i32
  %38 = shl i32 1, %37
  %39 = getelementptr inbounds %class.Code, ptr %12, i32 0, i32 3
  %40 = load i32, ptr %39, align 8, !tbaa !12
  %41 = or i32 %40, %38
  store i32 %41, ptr %39, align 8, !tbaa !12
  %42 = load i8, ptr %7, align 1, !tbaa !9
  %43 = zext i8 %42 to i32
  %44 = shl i32 1, %43
  %45 = getelementptr inbounds %class.Code, ptr %12, i32 0, i32 4
  %46 = load i32, ptr %45, align 4, !tbaa !38
  %47 = or i32 %46, %44
  store i32 %47, ptr %45, align 4, !tbaa !38
  %48 = getelementptr inbounds %class.Reg, ptr %0, i32 0, i32 0
  invoke void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24) %48, ptr noundef nonnull align 1 dereferenceable(1) %7)
          to label %49 unwind label %31

49:                                               ; preds = %35
  %50 = load i8, ptr %7, align 1, !tbaa !9
  %51 = add i8 %50, 1
  store i8 %51, ptr %7, align 1, !tbaa !9
  %52 = load i32, ptr %8, align 4, !tbaa !10
  %53 = add i32 %52, -1
  store i32 %53, ptr %8, align 4, !tbaa !10
  br label %13, !llvm.loop !39

54:                                               ; preds = %13
  store i1 true, ptr %9, align 1
  %55 = load i1, ptr %9, align 1
  br i1 %55, label %57, label %56

56:                                               ; preds = %54
  call void @_ZN3RegD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %57

57:                                               ; preds = %56, %54
  ret void

58:                                               ; preds = %31, %27
  call void @_ZN3RegD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  br label %59

59:                                               ; preds = %58
  %60 = load ptr, ptr %10, align 8
  %61 = load i32, ptr %11, align 4
  %62 = insertvalue { ptr, i32 } poison, ptr %60, 0
  %63 = insertvalue { ptr, i32 } %62, i32 %61, 1
  resume { ptr, i32 } %63

64:                                               ; preds = %26
  unreachable
}

declare void @_ZNSt14overflow_errorC1EPKc(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZNSt14overflow_errorD1Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 72}
!13 = !{!"_ZTS4Code", !14, i64 0, !18, i64 24, !22, i64 48, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !7, i64 88, !11, i64 104, !26, i64 108, !11, i64 112, !27, i64 120, !30, i64 152}
!14 = !{!"_ZTSSt6vectorI4InsnSaIS0_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseI4InsnSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseI4InsnSaIS0_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI4InsnSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIiSaIiEE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIhSaIhEE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIhSaIhEE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSN4Code12PrologueTypeE", !7, i64 0}
!27 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !28, i64 0, !29, i64 8, !7, i64 16}
!28 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!29 = !{!"long", !7, i64 0}
!30 = !{!"_ZTSSt3mapIh4SboxSt4lessIhESaISt4pairIKhS0_EEE", !31, i64 0}
!31 = !{!"_ZTSSt8_Rb_treeIhSt4pairIKh4SboxESt10_Select1stIS3_ESt4lessIhESaIS3_EE", !32, i64 0}
!32 = !{!"_ZTSNSt8_Rb_treeIhSt4pairIKh4SboxESt10_Select1stIS3_ESt4lessIhESaIS3_EE13_Rb_tree_implIS7_Lb1EEE", !33, i64 0, !35, i64 8}
!33 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessIhEE", !34, i64 0}
!34 = !{!"_ZTSSt4lessIhE"}
!35 = !{!"_ZTSSt15_Rb_tree_header", !36, i64 0, !29, i64 32}
!36 = !{!"_ZTSSt18_Rb_tree_node_base", !37, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!37 = !{!"_ZTSSt14_Rb_tree_color", !7, i64 0}
!38 = !{!13, !11, i64 76}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Reg = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@_ZTISt14overflow_error = external constant ptr
@.str.20 = external hidden unnamed_addr constant [35 x i8], align 1

declare ptr @__cxa_allocate_exception(i64) local_unnamed_addr

declare i32 @__gxx_personality_v0(...)

declare void @__cxa_free_exception(ptr) local_unnamed_addr

declare void @__cxa_throw(ptr, ptr, ptr) local_unnamed_addr

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3RegC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN3RegD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code19allocateExplicitRegEhj(ptr dead_on_unwind noalias nonnull writable sret(%class.Reg) align 8 %0, ptr nocapture noundef nonnull align 8 dereferenceable(200) %1, i8 noundef zeroext %2, i32 noundef %3) local_unnamed_addr #0 align 2 personality ptr @__gxx_personality_v0 {
  %5 = alloca i8, align 1
  store i8 %2, ptr %5, align 1, !tbaa !5
  tail call void @_ZN3RegC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0)
  %.not9 = icmp eq i32 %3, 0
  br i1 %.not9, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %4
  %6 = getelementptr inbounds i8, ptr %1, i64 72
  %7 = getelementptr inbounds i8, ptr %1, i64 76
  br label %8

8:                                                ; preds = %.lr.ph, %23
  %9 = phi i8 [ %2, %.lr.ph ], [ %25, %23 ]
  %.0610 = phi i32 [ %3, %.lr.ph ], [ %26, %23 ]
  %10 = load i32, ptr %6, align 8, !tbaa !8
  %11 = zext nneg i8 %9 to i32
  %12 = shl nuw i32 1, %11
  %13 = and i32 %12, %10
  %.not7 = icmp eq i32 %13, 0
  br i1 %.not7, label %19, label %14

14:                                               ; preds = %8
  %15 = call ptr @__cxa_allocate_exception(i64 16) #4
  invoke void @_ZNSt14overflow_errorC1EPKc(ptr noundef nonnull align 8 dereferenceable(16) %15, ptr noundef nonnull @.str.20)
          to label %16 unwind label %17

16:                                               ; preds = %14
  invoke void @__cxa_throw(ptr nonnull %15, ptr nonnull @_ZTISt14overflow_error, ptr nonnull @_ZNSt14overflow_errorD1Ev) #5
          to label %28 unwind label %.loopexit.split-lp

17:                                               ; preds = %14
  %18 = landingpad { ptr, i32 }
          cleanup
  call void @__cxa_free_exception(ptr %15) #4
  br label %27

.loopexit:                                        ; preds = %19
  %lpad.loopexit = landingpad { ptr, i32 }
          cleanup
  br label %27

.loopexit.split-lp:                               ; preds = %16
  %lpad.loopexit.split-lp = landingpad { ptr, i32 }
          cleanup
  br label %27

19:                                               ; preds = %8
  %20 = or i32 %12, %10
  store i32 %20, ptr %6, align 8, !tbaa !8
  %21 = load i32, ptr %7, align 4, !tbaa !36
  %22 = or i32 %21, %12
  store i32 %22, ptr %7, align 4, !tbaa !36
  invoke void @_ZNSt6vectorIhSaIhEE9push_backERKh(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 1 dereferenceable(1) %5)
          to label %23 unwind label %.loopexit

23:                                               ; preds = %19
  %24 = load i8, ptr %5, align 1, !tbaa !5
  %25 = add i8 %24, 1
  store i8 %25, ptr %5, align 1, !tbaa !5
  %26 = add i32 %.0610, -1
  %.not = icmp eq i32 %26, 0
  br i1 %.not, label %._crit_edge, label %8, !llvm.loop !37

._crit_edge:                                      ; preds = %23, %4
  ret void

27:                                               ; preds = %.loopexit, %.loopexit.split-lp, %17
  %.pn = phi { ptr, i32 } [ %18, %17 ], [ %lpad.loopexit, %.loopexit ], [ %lpad.loopexit.split-lp, %.loopexit.split-lp ]
  call void @_ZN3RegD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #4
  resume { ptr, i32 } %.pn

28:                                               ; preds = %16
  unreachable
}

declare void @_ZNSt14overflow_errorC1EPKc(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef) unnamed_addr #2

; Function Attrs: nounwind
declare void @_ZNSt14overflow_errorD1Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !23, i64 72}
!9 = !{!"_ZTS4Code", !10, i64 0, !15, i64 24, !19, i64 48, !23, i64 72, !23, i64 76, !23, i64 80, !23, i64 84, !6, i64 88, !23, i64 104, !24, i64 108, !23, i64 112, !25, i64 120, !28, i64 152}
!10 = !{!"_ZTSSt6vectorI4InsnSaIS0_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseI4InsnSaIS0_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseI4InsnSaIS0_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseI4InsnSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !6, i64 0}
!15 = !{!"_ZTSSt6vectorIiSaIiEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!19 = !{!"_ZTSSt6vectorIhSaIhEE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIhSaIhEE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIhSaIhEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!23 = !{!"int", !6, i64 0}
!24 = !{!"_ZTSN4Code12PrologueTypeE", !6, i64 0}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !26, i64 0, !27, i64 8, !6, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !14, i64 0}
!27 = !{!"long", !6, i64 0}
!28 = !{!"_ZTSSt3mapIh4SboxSt4lessIhESaISt4pairIKhS0_EEE", !29, i64 0}
!29 = !{!"_ZTSSt8_Rb_treeIhSt4pairIKh4SboxESt10_Select1stIS3_ESt4lessIhESaIS3_EE", !30, i64 0}
!30 = !{!"_ZTSNSt8_Rb_treeIhSt4pairIKh4SboxESt10_Select1stIS3_ESt4lessIhESaIS3_EE13_Rb_tree_implIS7_Lb1EEE", !31, i64 0, !33, i64 8}
!31 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessIhEE", !32, i64 0}
!32 = !{!"_ZTSSt4lessIhE"}
!33 = !{!"_ZTSSt15_Rb_tree_header", !34, i64 0, !27, i64 32}
!34 = !{!"_ZTSSt18_Rb_tree_node_base", !35, i64 0, !14, i64 8, !14, i64 16, !14, i64 24}
!35 = !{!"_ZTSSt14_Rb_tree_color", !6, i64 0}
!36 = !{!9, !23, i64 76}
!37 = distinct !{!37, !38}
!38 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass