; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code6lognotERK3RegS2_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6oneregEN4Insn4TypeEh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code6lognotERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #2 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %10 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11)
  store i32 %12, ptr %8, align 4, !tbaa !9
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13)
  %15 = load i32, ptr %8, align 4, !tbaa !9
  %16 = icmp slt i32 %14, %15
  br i1 %16, label %17, label %20

17:                                               ; preds = %3
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %18)
  store i32 %19, ptr %8, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %17, %3
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %21

21:                                               ; preds = %35, %20
  %22 = load i32, ptr %7, align 4, !tbaa !9
  %23 = load i32, ptr %8, align 4, !tbaa !9
  %24 = icmp slt i32 %22, %23
  br i1 %24, label %25, label %38

25:                                               ; preds = %21
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  %27 = load i32, ptr %7, align 4, !tbaa !9
  %28 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %26, i32 noundef %27)
  %29 = load ptr, ptr %6, align 8, !tbaa !5
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %29, i32 noundef %30)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %10, i32 noundef 34, i8 noundef zeroext %28, i8 noundef zeroext %31)
  %32 = load ptr, ptr %5, align 8, !tbaa !5
  %33 = load i32, ptr %7, align 4, !tbaa !9
  %34 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %32, i32 noundef %33)
  call void @_ZN4Code6oneregEN4Insn4TypeEh(ptr noundef nonnull align 8 dereferenceable(200) %10, i32 noundef 13, i8 noundef zeroext %34)
  br label %35

35:                                               ; preds = %25
  %36 = load i32, ptr %7, align 4, !tbaa !9
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %7, align 4, !tbaa !9
  br label %21, !llvm.loop !11

38:                                               ; preds = %21
  br label %39

39:                                               ; preds = %60, %38
  %40 = load i32, ptr %7, align 4, !tbaa !9
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  %42 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %41)
  %43 = icmp slt i32 %40, %42
  br i1 %43, label %44, label %63

44:                                               ; preds = %39
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = load i32, ptr %7, align 4, !tbaa !9
  %47 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %45, i32 noundef %46)
  %48 = zext i8 %47 to i32
  %49 = icmp sge i32 %48, 16
  br i1 %49, label %50, label %54

50:                                               ; preds = %44
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  %52 = load i32, ptr %7, align 4, !tbaa !9
  %53 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %51, i32 noundef %52)
  call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %10, i32 noundef 26, i8 noundef zeroext %53, i8 noundef zeroext -1)
  br label %60

54:                                               ; preds = %44
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  %55 = call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %10, i8 noundef zeroext -1)
  store i8 %55, ptr %9, align 1, !tbaa !13
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = load i32, ptr %7, align 4, !tbaa !9
  %58 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %56, i32 noundef %57)
  %59 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %10, i32 noundef 34, i8 noundef zeroext %58, i8 noundef zeroext %59)
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  br label %60

60:                                               ; preds = %54, %50
  %61 = load i32, ptr %7, align 4, !tbaa !9
  %62 = add nsw i32 %61, 1
  store i32 %62, ptr %7, align 4, !tbaa !9
  br label %39, !llvm.loop !14

63:                                               ; preds = %39
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6oneregEN4Insn4TypeEh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code6lognotERK3RegS2_(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #1 align 2 {
  %4 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %5 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  %6 = icmp slt i32 %5, %4
  br i1 %6, label %7, label %9

7:                                                ; preds = %3
  %8 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
  br label %9

9:                                                ; preds = %7, %3
  %.023 = phi i32 [ %8, %7 ], [ %4, %3 ]
  %10 = icmp sgt i32 %.023, 0
  br i1 %10, label %.lr.ph, label %.preheader

.preheader:                                       ; preds = %.lr.ph, %9
  %.0.lcssa = phi i32 [ 0, %9 ], [ %.023, %.lr.ph ]
  %11 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %12 = icmp slt i32 %.0.lcssa, %11
  br i1 %12, label %.lr.ph27, label %._crit_edge

.lr.ph:                                           ; preds = %9, %.lr.ph
  %.025 = phi i32 [ %16, %.lr.ph ], [ 0, %9 ]
  %13 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.025)
  %14 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %2, i32 noundef %.025)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 34, i8 noundef zeroext %13, i8 noundef zeroext %14)
  %15 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.025)
  tail call void @_ZN4Code6oneregEN4Insn4TypeEh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 13, i8 noundef zeroext %15)
  %16 = add nuw nsw i32 %.025, 1
  %exitcond.not = icmp eq i32 %16, %.023
  br i1 %exitcond.not, label %.preheader, label %.lr.ph, !llvm.loop !5

.lr.ph27:                                         ; preds = %.preheader, %24
  %.126 = phi i32 [ %25, %24 ], [ %.0.lcssa, %.preheader ]
  %17 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.126)
  %18 = icmp ugt i8 %17, 15
  br i1 %18, label %19, label %21

19:                                               ; preds = %.lr.ph27
  %20 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.126)
  tail call void @_ZN4Code6immregEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 26, i8 noundef zeroext %20, i8 noundef zeroext -1)
  br label %24

21:                                               ; preds = %.lr.ph27
  %22 = tail call noundef zeroext i8 @_ZN4Code7immtempEh(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext -1)
  %23 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.126)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 34, i8 noundef zeroext %23, i8 noundef zeroext %22)
  br label %24

24:                                               ; preds = %21, %19
  %25 = add nuw nsw i32 %.126, 1
  %26 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %27 = icmp slt i32 %25, %26
  br i1 %27, label %.lr.ph27, label %._crit_edge, !llvm.loop !7

._crit_edge:                                      ; preds = %24, %.preheader
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass