; LLVM IR from ARM-software/Arm-2D :: Helper/Source/arm_2d_helper_list.ll_ (arm_2d_list_core_get_inner_tile)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.__arm_2d_list_core_t = type { %struct.anon, %struct.anon.0, %struct.anon.22 }
%struct.anon = type { %struct.__arm_2d_list_core_cfg_t }
%struct.__arm_2d_list_core_cfg_t = type { %struct.arm_2d_size_t, ptr, %union.anon, ptr, ptr, ptr, i32, ptr, i16, i16, i16, i16, ptr }
%struct.arm_2d_size_t = type { i16, i16 }
%union.anon = type { ptr }
%struct.anon.0 = type { %struct.anon.1, %struct.anon.19 }
%struct.anon.1 = type { %struct.arm_2d_tile_t, %struct.arm_2d_tile_t, %struct.__arm_2d_list_work_area_t, i8, %union.anon.17 }
%struct.arm_2d_tile_t = type { %union.anon.2, %union.anon.13, %union.anon.16 }
%union.anon.2 = type { %struct.anon.3 }
%struct.anon.3 = type { i8, %union.arm_2d_color_info_t, %union.anon.6 }
%union.arm_2d_color_info_t = type { %struct.anon.4 }
%struct.anon.4 = type { i8 }
%union.anon.6 = type { i16 }
%union.anon.13 = type { %struct.arm_2d_region_t }
%struct.arm_2d_region_t = type { %union.anon.14, %union.anon.15 }
%union.anon.14 = type { %struct.arm_2d_location_t }
%struct.arm_2d_location_t = type { i16, i16 }
%union.anon.15 = type { %struct.arm_2d_size_t }
%union.anon.16 = type { ptr }
%struct.__arm_2d_list_work_area_t = type { ptr, %struct.arm_2d_region_t, %struct.arm_2d_list_item_param_t, i32 }
%struct.arm_2d_list_item_param_t = type { i8, i8, i16 }
%union.anon.17 = type { %struct.anon.18 }
%struct.anon.18 = type { i16 }
%struct.anon.19 = type { %struct.arm_2d_tile_t, i64, i64, %struct.arm_2d_helper_pi_slider_t, %struct.anon.20, i16, i8, i8, %struct.anon.21 }
%struct.arm_2d_helper_pi_slider_t = type { [40 x i8] }
%struct.anon.20 = type { i32, i32, i32, %struct.arm_2d_region_t }
%struct.anon.21 = type { i16, i32 }
%struct.anon.22 = type { i8, i8, i16, i32, %union.anon.23 }
%union.anon.23 = type { %struct.anon.24 }
%struct.anon.24 = type { i16, i16, i16, i16 }

@.str = external hidden unnamed_addr constant [15 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [88 x i8], align 1
@__PRETTY_FUNCTION__.__arm_2d_list_core_get_inner_tile = external hidden unnamed_addr constant [73 x i8], align 1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @__arm_2d_list_core_get_inner_tile(ptr noundef nonnull %0) #1 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %4 = icmp ne ptr null, %3
  br i1 %4, label %5, label %6

5:                                                ; preds = %1
  br label %7

6:                                                ; preds = %1
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 1312, ptr noundef @__PRETTY_FUNCTION__.__arm_2d_list_core_get_inner_tile) #2
  unreachable

7:                                                ; preds = %5
  %8 = load ptr, ptr %2, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.__arm_2d_list_core_t, ptr %8, i32 0, i32 1
  %10 = getelementptr inbounds %struct.anon.0, ptr %9, i32 0, i32 0
  %11 = getelementptr inbounds %struct.anon.1, ptr %10, i32 0, i32 1
  ret ptr %11
}

attributes #0 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local nonnull ptr @__arm_2d_list_core_get_inner_tile(ptr noundef nonnull readnone %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 104
  ret ptr %2
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass