; LLVM IR from rweather/lightweight-crypto :: src/genavr/algorithm_gift64.ll (ZN11Gift64State14inv_rotate_keyER4Codei)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Gift64State = type { %class.Reg, %class.Reg, %class.Reg, %class.Reg, %class.Reg, %class.Reg, %class.Reg }
%class.Reg = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i8 noundef zeroext) #1 align 2

declare void @_ZN4Code3rolERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

declare void @_ZN4Code3rorERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i8 noundef zeroext) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11Gift64State14inv_rotate_keyER4Codei(ptr noundef nonnull align 8 dereferenceable(168) %0, ptr noundef nonnull align 8 dereferenceable(200) %1, i32 noundef %2) #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %9 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %10 = load i32, ptr %6, align 4, !tbaa !9
  %11 = srem i32 %10, 4
  switch i32 %11, label %13 [
    i32 0, label %12
    i32 1, label %14
    i32 2, label %15
    i32 3, label %16
  ]

12:                                               ; preds = %3
  br label %13

13:                                               ; preds = %12, %3
  store i32 12, ptr %7, align 4, !tbaa !9
  store i32 8, ptr %8, align 4, !tbaa !9
  br label %17

14:                                               ; preds = %3
  store i32 8, ptr %7, align 4, !tbaa !9
  store i32 4, ptr %8, align 4, !tbaa !9
  br label %17

15:                                               ; preds = %3
  store i32 4, ptr %7, align 4, !tbaa !9
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %17

16:                                               ; preds = %3
  store i32 0, ptr %7, align 4, !tbaa !9
  store i32 12, ptr %8, align 4, !tbaa !9
  br label %17

17:                                               ; preds = %16, %15, %14, %13
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 4
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = trunc i32 %20 to i8
  call void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %18, ptr noundef nonnull align 8 dereferenceable(24) %19, i8 noundef zeroext %21)
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 5
  %24 = load i32, ptr %8, align 4, !tbaa !9
  %25 = add nsw i32 %24, 2
  %26 = trunc i32 %25 to i8
  call void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %22, ptr noundef nonnull align 8 dereferenceable(24) %23, i8 noundef zeroext %26)
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 4
  %29 = load i32, ptr %7, align 4, !tbaa !9
  %30 = trunc i32 %29 to i8
  call void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %27, ptr noundef nonnull align 8 dereferenceable(24) %28, i8 noundef zeroext %30)
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 5
  %33 = load i32, ptr %7, align 4, !tbaa !9
  %34 = add nsw i32 %33, 2
  %35 = trunc i32 %34 to i8
  call void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %31, ptr noundef nonnull align 8 dereferenceable(24) %32, i8 noundef zeroext %35)
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 4
  call void @_ZN4Code3rorERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %36, ptr noundef nonnull align 8 dereferenceable(24) %37, i32 noundef 4)
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %class.Gift64State, ptr %9, i32 0, i32 5
  call void @_ZN4Code3rolERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %38, ptr noundef nonnull align 8 dereferenceable(24) %39, i32 noundef 2)
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i8 noundef zeroext) local_unnamed_addr #0 align 2

declare void @_ZN4Code3rolERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

declare void @_ZN4Code3rorERK3Regj(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200), ptr noundef nonnull align 8 dereferenceable(24), i8 noundef zeroext) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11Gift64State14inv_rotate_keyER4Codei(ptr noundef nonnull align 8 dereferenceable(168) %0, ptr noundef nonnull align 8 dereferenceable(200) %1, i32 noundef %2) local_unnamed_addr #0 align 2 {
  %4 = srem i32 %2, 4
  %5 = icmp ult i32 %4, 4
  %switch.idx.cast = trunc nuw nsw i32 %4 to i8
  %6 = shl nuw nsw i8 %switch.idx.cast, 2
  %switch.offset = sub nuw nsw i8 12, %6
  %switch.shiftamt = shl nuw nsw i32 %4, 3
  %switch.downshift = lshr i32 201327624, %switch.shiftamt
  %switch.masked = trunc i32 %switch.downshift to i8
  %.011 = select i1 %5, i8 %switch.offset, i8 12
  %.0 = select i1 %5, i8 %switch.masked, i8 8
  %7 = getelementptr inbounds i8, ptr %0, i64 96
  tail call void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %7, i8 noundef zeroext %.0)
  %8 = getelementptr inbounds i8, ptr %0, i64 120
  %9 = or disjoint i8 %.0, 2
  tail call void @_ZN4Code7stlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %8, i8 noundef zeroext %9)
  tail call void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %7, i8 noundef zeroext %.011)
  %10 = or disjoint i8 %.011, 2
  tail call void @_ZN4Code7ldlocalERK3Regh(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %8, i8 noundef zeroext %10)
  tail call void @_ZN4Code3rorERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %7, i32 noundef 4)
  tail call void @_ZN4Code3rolERK3Regj(ptr noundef nonnull align 8 dereferenceable(200) %1, ptr noundef nonnull align 8 dereferenceable(24) %8, i32 noundef 2)
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass