; LLVM IR from ERGO-Code/HiGHS :: src/simplex/HSimplexNlaProductForm.ll (ZNK17ProductFormUpdate5btranER11HVectorBaseIdE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ProductFormUpdate = type { i8, i32, i32, %"class.std::vector", %"class.std::vector.3", %"class.std::vector", %"class.std::vector", %"class.std::vector.3" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.HVectorBase = type { i32, i32, %"class.std::vector", %"class.std::vector.3", double, %"class.std::vector.8", %"class.std::vector", ptr, i8, i32, %"class.std::vector", %"class.std::vector.3" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.52 = external hidden unnamed_addr constant [88 x i8], align 1
@.str.53 = external hidden unnamed_addr constant [21 x i8], align 1
@__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE = external hidden unnamed_addr constant [47 x i8], align 1
@.str.54 = external hidden unnamed_addr constant [40 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZNK17ProductFormUpdate5btranER11HVectorBaseIdE(ptr noundef nonnull align 8 dereferenceable(136) %0, ptr noundef nonnull align 8 dereferenceable(176) %1) #3 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca double, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %10 = load ptr, ptr %3, align 8
  %11 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 0
  %12 = load i8, ptr %11, align 8, !tbaa !9, !range !21, !noundef !22
  %13 = trunc i8 %12 to i1
  br i1 %13, label %15, label %14

14:                                               ; preds = %2
  br label %135

15:                                               ; preds = %2
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %class.HVectorBase, ptr %16, i32 0, i32 0
  %18 = load i32, ptr %17, align 8, !tbaa !23
  %19 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 1
  %20 = load i32, ptr %19, align 4, !tbaa !30
  %21 = icmp eq i32 %18, %20
  br i1 %21, label %22, label %23

22:                                               ; preds = %15
  br label %25

23:                                               ; preds = %15
  call void @__assert_fail(ptr noundef @.str.53, ptr noundef @.str.52, i32 noundef 68, ptr noundef @__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE) #4
  unreachable

24:                                               ; No predecessors!
  br label %25

25:                                               ; preds = %24, %22
  %26 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 5
  %27 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #5
  %28 = trunc i64 %27 to i32
  %29 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 2
  %30 = load i32, ptr %29, align 8, !tbaa !31
  %31 = add nsw i32 %30, 1
  %32 = icmp eq i32 %28, %31
  br i1 %32, label %33, label %34

33:                                               ; preds = %25
  br label %36

34:                                               ; preds = %25
  call void @__assert_fail(ptr noundef @.str.54, ptr noundef @.str.52, i32 noundef 69, ptr noundef @__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE) #4
  unreachable

35:                                               ; No predecessors!
  br label %36

36:                                               ; preds = %35, %33
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  %37 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 2
  %38 = load i32, ptr %37, align 8, !tbaa !31
  %39 = sub nsw i32 %38, 1
  store i32 %39, ptr %5, align 4, !tbaa !32
  br label %40

40:                                               ; preds = %132, %36
  %41 = load i32, ptr %5, align 4, !tbaa !32
  %42 = icmp sge i32 %41, 0
  br i1 %42, label %44, label %43

43:                                               ; preds = %40
  store i32 2, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  br label %135

44:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  %45 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 3
  %46 = load i32, ptr %5, align 4, !tbaa !32
  %47 = sext i32 %46 to i64
  %48 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef %47) #5
  %49 = load i32, ptr %48, align 4, !tbaa !32
  store i32 %49, ptr %7, align 4, !tbaa !32
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %class.HVectorBase, ptr %50, i32 0, i32 3
  %52 = load i32, ptr %7, align 4, !tbaa !32
  %53 = sext i32 %52 to i64
  %54 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef %53) #5
  %55 = load double, ptr %54, align 8, !tbaa !33
  store double %55, ptr %8, align 8, !tbaa !33
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %56 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 5
  %57 = load i32, ptr %5, align 4, !tbaa !32
  %58 = sext i32 %57 to i64
  %59 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %56, i64 noundef %58) #5
  %60 = load i32, ptr %59, align 4, !tbaa !32
  store i32 %60, ptr %9, align 4, !tbaa !32
  br label %61

61:                                               ; preds = %90, %44
  %62 = load i32, ptr %9, align 4, !tbaa !32
  %63 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 5
  %64 = load i32, ptr %5, align 4, !tbaa !32
  %65 = add nsw i32 %64, 1
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %66) #5
  %68 = load i32, ptr %67, align 4, !tbaa !32
  %69 = icmp slt i32 %62, %68
  br i1 %69, label %71, label %70

70:                                               ; preds = %61
  store i32 5, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %93

71:                                               ; preds = %61
  %72 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 7
  %73 = load i32, ptr %9, align 4, !tbaa !32
  %74 = sext i32 %73 to i64
  %75 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %72, i64 noundef %74) #5
  %76 = load double, ptr %75, align 8, !tbaa !33
  %77 = load ptr, ptr %4, align 8, !tbaa !5
  %78 = getelementptr inbounds %class.HVectorBase, ptr %77, i32 0, i32 3
  %79 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 6
  %80 = load i32, ptr %9, align 4, !tbaa !32
  %81 = sext i32 %80 to i64
  %82 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %79, i64 noundef %81) #5
  %83 = load i32, ptr %82, align 4, !tbaa !32
  %84 = sext i32 %83 to i64
  %85 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %84) #5
  %86 = load double, ptr %85, align 8, !tbaa !33
  %87 = load double, ptr %8, align 8, !tbaa !33
  %88 = fneg double %76
  %89 = call double @llvm.fmuladd.f64(double %88, double %86, double %87)
  store double %89, ptr %8, align 8, !tbaa !33
  br label %90

90:                                               ; preds = %71
  %91 = load i32, ptr %9, align 4, !tbaa !32
  %92 = add nsw i32 %91, 1
  store i32 %92, ptr %9, align 4, !tbaa !32
  br label %61, !llvm.loop !34

93:                                               ; preds = %70
  %94 = getelementptr inbounds %struct.ProductFormUpdate, ptr %10, i32 0, i32 4
  %95 = load i32, ptr %5, align 4, !tbaa !32
  %96 = sext i32 %95 to i64
  %97 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %94, i64 noundef %96) #5
  %98 = load double, ptr %97, align 8, !tbaa !33
  %99 = load double, ptr %8, align 8, !tbaa !33
  %100 = fdiv double %99, %98
  store double %100, ptr %8, align 8, !tbaa !33
  %101 = load ptr, ptr %4, align 8, !tbaa !5
  %102 = getelementptr inbounds %class.HVectorBase, ptr %101, i32 0, i32 3
  %103 = load i32, ptr %7, align 4, !tbaa !32
  %104 = sext i32 %103 to i64
  %105 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %102, i64 noundef %104) #5
  %106 = load double, ptr %105, align 8, !tbaa !33
  %107 = fcmp oeq double %106, 0.000000e+00
  br i1 %107, label %108, label %118

108:                                              ; preds = %93
  %109 = load i32, ptr %7, align 4, !tbaa !32
  %110 = load ptr, ptr %4, align 8, !tbaa !5
  %111 = getelementptr inbounds %class.HVectorBase, ptr %110, i32 0, i32 2
  %112 = load ptr, ptr %4, align 8, !tbaa !5
  %113 = getelementptr inbounds %class.HVectorBase, ptr %112, i32 0, i32 1
  %114 = load i32, ptr %113, align 4, !tbaa !36
  %115 = add nsw i32 %114, 1
  store i32 %115, ptr %113, align 4, !tbaa !36
  %116 = sext i32 %114 to i64
  %117 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %111, i64 noundef %116) #5
  store i32 %109, ptr %117, align 4, !tbaa !32
  br label %118

118:                                              ; preds = %108, %93
  %119 = load double, ptr %8, align 8, !tbaa !33
  %120 = call double @llvm.fabs.f64(double %119)
  %121 = fcmp olt double %120, 0x3D06849B86A12B9B
  br i1 %121, label %122, label %123

122:                                              ; preds = %118
  br label %125

123:                                              ; preds = %118
  %124 = load double, ptr %8, align 8, !tbaa !33
  br label %125

125:                                              ; preds = %123, %122
  %126 = phi double [ 1.000000e-100, %122 ], [ %124, %123 ]
  %127 = load ptr, ptr %4, align 8, !tbaa !5
  %128 = getelementptr inbounds %class.HVectorBase, ptr %127, i32 0, i32 3
  %129 = load i32, ptr %7, align 4, !tbaa !32
  %130 = sext i32 %129 to i64
  %131 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %128, i64 noundef %130) #5
  store double %126, ptr %131, align 8, !tbaa !33
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  br label %132

132:                                              ; preds = %125
  %133 = load i32, ptr %5, align 4, !tbaa !32
  %134 = add nsw i32 %133, -1
  store i32 %134, ptr %5, align 4, !tbaa !32
  br label %40, !llvm.loop !37

135:                                              ; preds = %43, %14
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS17ProductFormUpdate", !11, i64 0, !12, i64 4, !12, i64 8, !13, i64 16, !17, i64 40, !13, i64 64, !13, i64 88, !17, i64 112}
!11 = !{!"bool", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIiSaIiEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt6vectorIdSaIdEE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{i8 0, i8 2}
!22 = !{}
!23 = !{!24, !12, i64 0}
!24 = !{!"_ZTS11HVectorBaseIdE", !12, i64 0, !12, i64 4, !13, i64 8, !17, i64 32, !25, i64 56, !26, i64 64, !13, i64 88, !6, i64 112, !11, i64 120, !12, i64 124, !13, i64 128, !17, i64 152}
!25 = !{!"double", !7, i64 0}
!26 = !{!"_ZTSSt6vectorIcSaIcEE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!10, !12, i64 4}
!31 = !{!10, !12, i64 8}
!32 = !{!12, !12, i64 0}
!33 = !{!25, !25, i64 0}
!34 = distinct !{!34, !35}
!35 = !{!"llvm.loop.mustprogress"}
!36 = !{!24, !12, i64 4}
!37 = distinct !{!37, !35}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str.52 = external hidden unnamed_addr constant [88 x i8], align 1
@.str.53 = external hidden unnamed_addr constant [21 x i8], align 1
@__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE = external hidden unnamed_addr constant [47 x i8], align 1
@.str.54 = external hidden unnamed_addr constant [40 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #0

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZNK17ProductFormUpdate5btranER11HVectorBaseIdE(ptr noundef nonnull align 8 dereferenceable(136) %0, ptr noundef nonnull align 8 dereferenceable(176) %1) local_unnamed_addr #2 align 2 {
  %3 = load i8, ptr %0, align 8, !tbaa !5, !range !20, !noundef !21
  %4 = trunc nuw i8 %3 to i1
  br i1 %4, label %5, label %.loopexit

5:                                                ; preds = %2
  %6 = load i32, ptr %1, align 8, !tbaa !22
  %7 = getelementptr inbounds i8, ptr %0, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !29
  %9 = icmp eq i32 %6, %8
  br i1 %9, label %11, label %10

10:                                               ; preds = %5
  tail call void @__assert_fail(ptr noundef nonnull @.str.53, ptr noundef nonnull @.str.52, i32 noundef 68, ptr noundef nonnull @__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE) #3
  unreachable

11:                                               ; preds = %5
  %12 = getelementptr inbounds i8, ptr %0, i64 64
  %13 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %14 = trunc i64 %13 to i32
  %15 = getelementptr inbounds i8, ptr %0, i64 8
  %16 = load i32, ptr %15, align 8, !tbaa !30
  %17 = add nsw i32 %16, 1
  %18 = icmp eq i32 %17, %14
  br i1 %18, label %.preheader, label %28

.preheader:                                       ; preds = %11
  %19 = icmp sgt i32 %16, 0
  br i1 %19, label %.lr.ph32, label %.loopexit

.lr.ph32:                                         ; preds = %.preheader
  %20 = getelementptr inbounds i8, ptr %0, i64 16
  %21 = getelementptr inbounds i8, ptr %1, i64 32
  %22 = getelementptr inbounds i8, ptr %0, i64 112
  %23 = getelementptr inbounds i8, ptr %0, i64 88
  %24 = getelementptr inbounds i8, ptr %0, i64 40
  %25 = getelementptr inbounds i8, ptr %1, i64 8
  %26 = getelementptr inbounds i8, ptr %1, i64 4
  %27 = zext nneg i32 %16 to i64
  br label %29

28:                                               ; preds = %11
  tail call void @__assert_fail(ptr noundef nonnull @.str.54, ptr noundef nonnull @.str.52, i32 noundef 69, ptr noundef nonnull @__PRETTY_FUNCTION__._ZNK17ProductFormUpdate5btranER11HVectorBaseIdE) #3
  unreachable

29:                                               ; preds = %.lr.ph32, %65
  %indvars.iv34 = phi i64 [ %27, %.lr.ph32 ], [ %indvars.iv.next35, %65 ]
  %indvars.iv.next35 = add nsw i64 %indvars.iv34, -1
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %indvars.iv.next35) #4
  %31 = load i32, ptr %30, align 4, !tbaa !31
  %32 = sext i32 %31 to i64
  %33 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %32) #4
  %34 = load double, ptr %33, align 8, !tbaa !32
  %35 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv.next35) #4
  %36 = load i32, ptr %35, align 4, !tbaa !31
  %37 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv34) #4
  %38 = load i32, ptr %37, align 4, !tbaa !31
  %39 = icmp slt i32 %36, %38
  br i1 %39, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %29
  %40 = sext i32 %36 to i64
  br label %.lr.ph

._crit_edge:                                      ; preds = %.lr.ph, %29
  %.025.lcssa = phi double [ %34, %29 ], [ %55, %.lr.ph ]
  %41 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %indvars.iv.next35) #4
  %42 = load double, ptr %41, align 8, !tbaa !32
  %43 = fdiv double %.025.lcssa, %42
  %44 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %32) #4
  %45 = load double, ptr %44, align 8, !tbaa !32
  %46 = fcmp oeq double %45, 0.000000e+00
  br i1 %46, label %60, label %65

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i64 [ %40, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %.02527 = phi double [ %34, %.lr.ph.preheader ], [ %55, %.lr.ph ]
  %47 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %indvars.iv) #4
  %48 = load double, ptr %47, align 8, !tbaa !32
  %49 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %indvars.iv) #4
  %50 = load i32, ptr %49, align 4, !tbaa !31
  %51 = sext i32 %50 to i64
  %52 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %51) #4
  %53 = load double, ptr %52, align 8, !tbaa !32
  %54 = fneg double %48
  %55 = tail call double @llvm.fmuladd.f64(double %54, double %53, double %.02527)
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %56 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv34) #4
  %57 = load i32, ptr %56, align 4, !tbaa !31
  %58 = sext i32 %57 to i64
  %59 = icmp slt i64 %indvars.iv.next, %58
  br i1 %59, label %.lr.ph, label %._crit_edge, !llvm.loop !33

60:                                               ; preds = %._crit_edge
  %61 = load i32, ptr %26, align 4, !tbaa !35
  %62 = add nsw i32 %61, 1
  store i32 %62, ptr %26, align 4, !tbaa !35
  %63 = sext i32 %61 to i64
  %64 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %63) #4
  store i32 %31, ptr %64, align 4, !tbaa !31
  br label %65

65:                                               ; preds = %60, %._crit_edge
  %66 = tail call double @llvm.fabs.f64(double %43)
  %67 = fcmp olt double %66, 0x3D06849B86A12B9B
  %68 = select i1 %67, double 1.000000e-100, double %43
  %69 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %32) #4
  store double %68, ptr %69, align 8, !tbaa !32
  %70 = icmp sgt i64 %indvars.iv34, 1
  br i1 %70, label %29, label %.loopexit, !llvm.loop !36

.loopexit:                                        ; preds = %65, %.preheader, %2
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS17ProductFormUpdate", !7, i64 0, !10, i64 4, !10, i64 8, !11, i64 16, !16, i64 40, !11, i64 64, !11, i64 88, !16, i64 112}
!7 = !{!"bool", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"_ZTSSt6vectorIiSaIiEE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!15 = !{!"any pointer", !8, i64 0}
!16 = !{!"_ZTSSt6vectorIdSaIdEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!20 = !{i8 0, i8 2}
!21 = !{}
!22 = !{!23, !10, i64 0}
!23 = !{!"_ZTS11HVectorBaseIdE", !10, i64 0, !10, i64 4, !11, i64 8, !16, i64 32, !24, i64 56, !25, i64 64, !11, i64 88, !15, i64 112, !7, i64 120, !10, i64 124, !11, i64 128, !16, i64 152}
!24 = !{!"double", !8, i64 0}
!25 = !{!"_ZTSSt6vectorIcSaIcEE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !15, i64 0, !15, i64 8, !15, i64 16}
!29 = !{!6, !10, i64 4}
!30 = !{!6, !10, i64 8}
!31 = !{!10, !10, i64 0}
!32 = !{!24, !24, i64 0}
!33 = distinct !{!33, !34}
!34 = !{!"llvm.loop.mustprogress"}
!35 = !{!23, !10, i64 4}
!36 = distinct !{!36, !34}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass