; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code10ld_st_longERK3RegN4Insn4TypeEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext, i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code10ld_st_longERK3RegN4Insn4TypeEj(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, i32 noundef %3) #2 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !11
  %12 = load ptr, ptr %5, align 8
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13)
  %15 = icmp eq i32 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  br label %138

17:                                               ; preds = %4
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = icmp eq i32 %18, 23
  br i1 %19, label %20, label %57

20:                                               ; preds = %17
  %21 = load i32, ptr %8, align 4, !tbaa !11
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %27, label %23

23:                                               ; preds = %20
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %24)
  %26 = icmp sgt i32 %25, 1
  br i1 %26, label %27, label %57

27:                                               ; preds = %23, %20
  %28 = load i32, ptr %8, align 4, !tbaa !11
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 26, i32 noundef %28)
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !11
  br label %29

29:                                               ; preds = %41, %27
  %30 = load i32, ptr %9, align 4, !tbaa !11
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %31)
  %33 = sub nsw i32 %32, 1
  %34 = icmp slt i32 %30, %33
  br i1 %34, label %36, label %35

35:                                               ; preds = %29
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %44

36:                                               ; preds = %29
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = load i32, ptr %9, align 4, !tbaa !11
  %40 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %38, i32 noundef %39)
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %37, i8 noundef zeroext %40, i8 noundef zeroext -1)
  br label %41

41:                                               ; preds = %36
  %42 = load i32, ptr %9, align 4, !tbaa !11
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %9, align 4, !tbaa !11
  br label %29, !llvm.loop !13

44:                                               ; preds = %35
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = load ptr, ptr %6, align 8, !tbaa !5
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %47)
  %49 = sub nsw i32 %48, 1
  %50 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %46, i32 noundef %49)
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %45, i8 noundef zeroext %50, i8 noundef zeroext 0)
  %51 = load i32, ptr %8, align 4, !tbaa !11
  %52 = load ptr, ptr %6, align 8, !tbaa !5
  %53 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %52)
  %54 = add i32 %51, %53
  %55 = sub i32 %54, 1
  %56 = sub i32 0, %55
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 26, i32 noundef %56)
  br label %137

57:                                               ; preds = %23, %17
  %58 = load i32, ptr %8, align 4, !tbaa !11
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %59)
  %61 = add nsw i32 %58, %60
  %62 = icmp sle i32 %61, 64
  br i1 %62, label %63, label %83

63:                                               ; preds = %57
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !11
  br label %64

64:                                               ; preds = %79, %63
  %65 = load i32, ptr %10, align 4, !tbaa !11
  %66 = load ptr, ptr %6, align 8, !tbaa !5
  %67 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %66)
  %68 = icmp slt i32 %65, %67
  br i1 %68, label %70, label %69

69:                                               ; preds = %64
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %82

70:                                               ; preds = %64
  %71 = load i32, ptr %7, align 4, !tbaa !9
  %72 = load ptr, ptr %6, align 8, !tbaa !5
  %73 = load i32, ptr %10, align 4, !tbaa !11
  %74 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %72, i32 noundef %73)
  %75 = load i32, ptr %8, align 4, !tbaa !11
  %76 = load i32, ptr %10, align 4, !tbaa !11
  %77 = add i32 %75, %76
  %78 = trunc i32 %77 to i8
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %71, i8 noundef zeroext %74, i8 noundef zeroext %78)
  br label %79

79:                                               ; preds = %70
  %80 = load i32, ptr %10, align 4, !tbaa !11
  %81 = add nsw i32 %80, 1
  store i32 %81, ptr %10, align 4, !tbaa !11
  br label %64, !llvm.loop !15

82:                                               ; preds = %69
  br label %136

83:                                               ; preds = %57
  %84 = load i32, ptr %7, align 4, !tbaa !9
  %85 = icmp eq i32 %84, 24
  br i1 %85, label %89, label %86

86:                                               ; preds = %83
  %87 = load i32, ptr %7, align 4, !tbaa !9
  %88 = icmp eq i32 %87, 54
  br i1 %88, label %89, label %91

89:                                               ; preds = %86, %83
  %90 = load i32, ptr %8, align 4, !tbaa !11
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 28, i32 noundef %90)
  br label %93

91:                                               ; preds = %86
  %92 = load i32, ptr %8, align 4, !tbaa !11
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 30, i32 noundef %92)
  br label %93

93:                                               ; preds = %91, %89
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !11
  br label %94

94:                                               ; preds = %106, %93
  %95 = load i32, ptr %11, align 4, !tbaa !11
  %96 = load ptr, ptr %6, align 8, !tbaa !5
  %97 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %96)
  %98 = sub nsw i32 %97, 1
  %99 = icmp slt i32 %95, %98
  br i1 %99, label %101, label %100

100:                                              ; preds = %94
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %109

101:                                              ; preds = %94
  %102 = load i32, ptr %7, align 4, !tbaa !9
  %103 = load ptr, ptr %6, align 8, !tbaa !5
  %104 = load i32, ptr %11, align 4, !tbaa !11
  %105 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %103, i32 noundef %104)
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %102, i8 noundef zeroext %105, i8 noundef zeroext -1)
  br label %106

106:                                              ; preds = %101
  %107 = load i32, ptr %11, align 4, !tbaa !11
  %108 = add nsw i32 %107, 1
  store i32 %108, ptr %11, align 4, !tbaa !11
  br label %94, !llvm.loop !16

109:                                              ; preds = %100
  %110 = load i32, ptr %7, align 4, !tbaa !9
  %111 = load ptr, ptr %6, align 8, !tbaa !5
  %112 = load ptr, ptr %6, align 8, !tbaa !5
  %113 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %112)
  %114 = sub nsw i32 %113, 1
  %115 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %111, i32 noundef %114)
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %110, i8 noundef zeroext %115, i8 noundef zeroext 0)
  %116 = load i32, ptr %7, align 4, !tbaa !9
  %117 = icmp eq i32 %116, 24
  br i1 %117, label %121, label %118

118:                                              ; preds = %109
  %119 = load i32, ptr %7, align 4, !tbaa !9
  %120 = icmp eq i32 %119, 54
  br i1 %120, label %121, label %128

121:                                              ; preds = %118, %109
  %122 = load i32, ptr %8, align 4, !tbaa !11
  %123 = load ptr, ptr %6, align 8, !tbaa !5
  %124 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %123)
  %125 = add i32 %122, %124
  %126 = sub i32 %125, 1
  %127 = sub i32 0, %126
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 28, i32 noundef %127)
  br label %135

128:                                              ; preds = %118
  %129 = load i32, ptr %8, align 4, !tbaa !11
  %130 = load ptr, ptr %6, align 8, !tbaa !5
  %131 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %130)
  %132 = add i32 %129, %131
  %133 = sub i32 %132, 1
  %134 = sub i32 0, %133
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 30, i32 noundef %134)
  br label %135

135:                                              ; preds = %128, %121
  br label %136

136:                                              ; preds = %135, %82
  br label %137

137:                                              ; preds = %136, %44
  br label %138

138:                                              ; preds = %137, %16
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN4Insn4TypeE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext, i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code10ld_st_longERK3RegN4Insn4TypeEj(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 align 2 {
  %5 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %.loopexit, label %7

7:                                                ; preds = %4
  %8 = icmp eq i32 %2, 23
  br i1 %8, label %9, label %24

9:                                                ; preds = %7
  %.not = icmp eq i32 %3, 0
  br i1 %.not, label %10, label %13

10:                                               ; preds = %9
  %11 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %12 = icmp sgt i32 %11, 1
  br i1 %12, label %13, label %24

13:                                               ; preds = %10, %9
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext 26, i32 noundef %3)
  %14 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %15 = icmp sgt i32 %14, 1
  br i1 %15, label %.lr.ph62, label %._crit_edge63

._crit_edge63:                                    ; preds = %.lr.ph62, %13
  %16 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %17 = add nsw i32 %16, -1
  %18 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %17)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 23, i8 noundef zeroext %18, i8 noundef zeroext 0)
  br label %.loopexit.sink.split

.lr.ph62:                                         ; preds = %13, %.lr.ph62
  %.04960 = phi i32 [ %20, %.lr.ph62 ], [ 0, %13 ]
  %19 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.04960)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 23, i8 noundef zeroext %19, i8 noundef zeroext -1)
  %20 = add nuw nsw i32 %.04960, 1
  %21 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %22 = add nsw i32 %21, -1
  %23 = icmp slt i32 %20, %22
  br i1 %23, label %.lr.ph62, label %._crit_edge63, !llvm.loop !5

24:                                               ; preds = %10, %7
  %25 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %26 = add nsw i32 %25, %3
  %27 = icmp slt i32 %26, 65
  br i1 %27, label %.preheader, label %36

.preheader:                                       ; preds = %24
  %28 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %29 = icmp sgt i32 %28, 0
  br i1 %29, label %.lr.ph59, label %.loopexit

.lr.ph59:                                         ; preds = %.preheader, %.lr.ph59
  %.04858 = phi i32 [ %33, %.lr.ph59 ], [ 0, %.preheader ]
  %30 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.04858)
  %31 = add i32 %.04858, %3
  %32 = trunc i32 %31 to i8
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %30, i8 noundef zeroext %32)
  %33 = add nuw nsw i32 %.04858, 1
  %34 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %35 = icmp slt i32 %33, %34
  br i1 %35, label %.lr.ph59, label %.loopexit, !llvm.loop !7

36:                                               ; preds = %24
  %switch.selectcmp.case1 = icmp eq i32 %2, 54
  %switch.selectcmp.case2 = icmp eq i32 %2, 24
  %switch.selectcmp = or i1 %switch.selectcmp.case1, %switch.selectcmp.case2
  %37 = select i1 %switch.selectcmp, i8 28, i8 30
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext %37, i32 noundef %3)
  %38 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %39 = icmp sgt i32 %38, 1
  br i1 %39, label %.lr.ph, label %._crit_edge

._crit_edge:                                      ; preds = %.lr.ph, %36
  %40 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %41 = add nsw i32 %40, -1
  %42 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %41)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %42, i8 noundef zeroext 0)
  %switch.selectcmp.case168 = icmp eq i32 %2, 54
  %switch.selectcmp.case269 = icmp eq i32 %2, 24
  %switch.selectcmp70 = or i1 %switch.selectcmp.case168, %switch.selectcmp.case269
  %43 = select i1 %switch.selectcmp70, i8 28, i8 30
  br label %.loopexit.sink.split

.lr.ph:                                           ; preds = %36, %.lr.ph
  %.057 = phi i32 [ %45, %.lr.ph ], [ 0, %36 ]
  %44 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.057)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %44, i8 noundef zeroext -1)
  %45 = add nuw nsw i32 %.057, 1
  %46 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %47 = add nsw i32 %46, -1
  %48 = icmp slt i32 %45, %47
  br i1 %48, label %.lr.ph, label %._crit_edge, !llvm.loop !8

.loopexit.sink.split:                             ; preds = %._crit_edge, %._crit_edge63
  %.sink64 = phi i8 [ 26, %._crit_edge63 ], [ %43, %._crit_edge ]
  %49 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %50 = add i32 %49, %3
  %51 = sub i32 1, %50
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext %.sink64, i32 noundef %51)
  br label %.loopexit

.loopexit:                                        ; preds = %.lr.ph59, %.loopexit.sink.split, %.preheader, %4
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}
!8 = distinct !{!8, !6}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass