; LLVM IR from skywind3000/ml :: NeuralNetwork (ineuron)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.INEURON = type { i32, i32, double, double, ptr, ptr, [1 x double] }

@.str = external hidden unnamed_addr constant [16 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [72 x i8], align 1
@__PRETTY_FUNCTION__.ineuron_create = external hidden unnamed_addr constant [49 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [15 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local ptr @ineuron_create(i32 noundef %0, double noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca double, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store double %1, ptr %5, align 8, !tbaa !9
  store i32 %2, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = icmp sgt i32 %10, 0
  br i1 %11, label %12, label %13

12:                                               ; preds = %3
  br label %14

13:                                               ; preds = %3
  call void @__assert_fail(ptr noundef @.str, ptr noundef @.str.1, i32 noundef 105, ptr noundef @__PRETTY_FUNCTION__.ineuron_create) #5
  unreachable

14:                                               ; preds = %12
  %15 = load i32, ptr %4, align 4, !tbaa !5
  %16 = sext i32 %15 to i64
  %17 = mul i64 8, %16
  %18 = add i64 48, %17
  store i64 %18, ptr %8, align 8, !tbaa !11
  %19 = load i64, ptr %8, align 8, !tbaa !11
  %20 = call noalias ptr @malloc(i64 noundef %19) #6
  store ptr %20, ptr %7, align 8, !tbaa !13
  %21 = load ptr, ptr %7, align 8, !tbaa !13
  %22 = icmp ne ptr %21, null
  br i1 %22, label %23, label %24

23:                                               ; preds = %14
  br label %25

24:                                               ; preds = %14
  call void @__assert_fail(ptr noundef @.str.2, ptr noundef @.str.1, i32 noundef 109, ptr noundef @__PRETTY_FUNCTION__.ineuron_create) #5
  unreachable

25:                                               ; preds = %23
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = load ptr, ptr %7, align 8, !tbaa !13
  %28 = getelementptr inbounds %struct.INEURON, ptr %27, i32 0, i32 0
  store i32 %26, ptr %28, align 8, !tbaa !15
  %29 = load ptr, ptr %7, align 8, !tbaa !13
  %30 = getelementptr inbounds %struct.INEURON, ptr %29, i32 0, i32 1
  store i32 0, ptr %30, align 4, !tbaa !17
  %31 = load double, ptr %5, align 8, !tbaa !9
  %32 = load ptr, ptr %7, align 8, !tbaa !13
  %33 = getelementptr inbounds %struct.INEURON, ptr %32, i32 0, i32 2
  store double %31, ptr %33, align 8, !tbaa !18
  %34 = load ptr, ptr %7, align 8, !tbaa !13
  %35 = getelementptr inbounds %struct.INEURON, ptr %34, i32 0, i32 3
  store double 0.000000e+00, ptr %35, align 8, !tbaa !19
  %36 = load ptr, ptr %7, align 8, !tbaa !13
  %37 = getelementptr inbounds %struct.INEURON, ptr %36, i32 0, i32 4
  store ptr null, ptr %37, align 8, !tbaa !20
  %38 = load ptr, ptr %7, align 8, !tbaa !13
  %39 = getelementptr inbounds %struct.INEURON, ptr %38, i32 0, i32 5
  store ptr null, ptr %39, align 8, !tbaa !21
  %40 = load i32, ptr %6, align 4, !tbaa !5
  switch i32 %40, label %66 [
    i32 0, label %41
    i32 1, label %46
    i32 2, label %51
    i32 3, label %56
    i32 4, label %61
  ]

41:                                               ; preds = %25
  %42 = load ptr, ptr %7, align 8, !tbaa !13
  %43 = getelementptr inbounds %struct.INEURON, ptr %42, i32 0, i32 4
  store ptr @ineuron_normal_function, ptr %43, align 8, !tbaa !20
  %44 = load ptr, ptr %7, align 8, !tbaa !13
  %45 = getelementptr inbounds %struct.INEURON, ptr %44, i32 0, i32 5
  store ptr @ineuron_normal_derivative, ptr %45, align 8, !tbaa !21
  br label %66

46:                                               ; preds = %25
  %47 = load ptr, ptr %7, align 8, !tbaa !13
  %48 = getelementptr inbounds %struct.INEURON, ptr %47, i32 0, i32 4
  store ptr @ineuron_sigmod_function, ptr %48, align 8, !tbaa !20
  %49 = load ptr, ptr %7, align 8, !tbaa !13
  %50 = getelementptr inbounds %struct.INEURON, ptr %49, i32 0, i32 5
  store ptr @ineuron_sigmod_derivative, ptr %50, align 8, !tbaa !21
  br label %66

51:                                               ; preds = %25
  %52 = load ptr, ptr %7, align 8, !tbaa !13
  %53 = getelementptr inbounds %struct.INEURON, ptr %52, i32 0, i32 4
  store ptr @ineuron_bipolar_function, ptr %53, align 8, !tbaa !20
  %54 = load ptr, ptr %7, align 8, !tbaa !13
  %55 = getelementptr inbounds %struct.INEURON, ptr %54, i32 0, i32 5
  store ptr @ineuron_bipolar_derivative, ptr %55, align 8, !tbaa !21
  br label %66

56:                                               ; preds = %25
  %57 = load ptr, ptr %7, align 8, !tbaa !13
  %58 = getelementptr inbounds %struct.INEURON, ptr %57, i32 0, i32 4
  store ptr @ineuron_threshold_function, ptr %58, align 8, !tbaa !20
  %59 = load ptr, ptr %7, align 8, !tbaa !13
  %60 = getelementptr inbounds %struct.INEURON, ptr %59, i32 0, i32 5
  store ptr @ineuron_threshold_derivative, ptr %60, align 8, !tbaa !21
  br label %66

61:                                               ; preds = %25
  %62 = load ptr, ptr %7, align 8, !tbaa !13
  %63 = getelementptr inbounds %struct.INEURON, ptr %62, i32 0, i32 4
  store ptr @ineuron_tanh_function, ptr %63, align 8, !tbaa !20
  %64 = load ptr, ptr %7, align 8, !tbaa !13
  %65 = getelementptr inbounds %struct.INEURON, ptr %64, i32 0, i32 5
  store ptr @ineuron_tanh_derivative, ptr %65, align 8, !tbaa !21
  br label %66

66:                                               ; preds = %61, %56, %51, %46, %41, %25
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %67

67:                                               ; preds = %77, %66
  %68 = load i32, ptr %9, align 4, !tbaa !5
  %69 = load i32, ptr %4, align 4, !tbaa !5
  %70 = icmp slt i32 %68, %69
  br i1 %70, label %71, label %80

71:                                               ; preds = %67
  %72 = load ptr, ptr %7, align 8, !tbaa !13
  %73 = getelementptr inbounds %struct.INEURON, ptr %72, i32 0, i32 6
  %74 = load i32, ptr %9, align 4, !tbaa !5
  %75 = sext i32 %74 to i64
  %76 = getelementptr inbounds [1 x double], ptr %73, i64 0, i64 %75
  store double 0.000000e+00, ptr %76, align 8, !tbaa !9
  br label %77

77:                                               ; preds = %71
  %78 = load i32, ptr %9, align 4, !tbaa !5
  %79 = add nsw i32 %78, 1
  store i32 %79, ptr %9, align 4, !tbaa !5
  br label %67, !llvm.loop !22

80:                                               ; preds = %67
  %81 = load ptr, ptr %7, align 8, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  ret ptr %81
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #2

; Function Attrs: nounwind allocsize(0)
declare noalias ptr @malloc(i64 noundef) #3

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_normal_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_normal_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_sigmod_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_sigmod_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_bipolar_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_bipolar_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_threshold_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_threshold_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_tanh_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_tanh_derivative(double noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn nounwind }
attributes #6 = { nounwind allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"any pointer", !7, i64 0}
!15 = !{!16, !6, i64 0}
!16 = !{!"INEURON", !6, i64 0, !6, i64 4, !10, i64 8, !10, i64 16, !14, i64 24, !14, i64 32, !7, i64 40}
!17 = !{!16, !6, i64 4}
!18 = !{!16, !10, i64 8}
!19 = !{!16, !10, i64 16}
!20 = !{!16, !14, i64 24}
!21 = !{!16, !14, i64 32}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [16 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [72 x i8], align 1
@__PRETTY_FUNCTION__.ineuron_create = external hidden unnamed_addr constant [49 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [15 x i8], align 1
@switch.table.ineuron_create = private unnamed_addr constant [5 x ptr] [ptr @ineuron_normal_function, ptr @ineuron_sigmod_function, ptr @ineuron_bipolar_function, ptr @ineuron_threshold_function, ptr @ineuron_tanh_function], align 8
@switch.table.ineuron_create.1 = private unnamed_addr constant [5 x ptr] [ptr @ineuron_normal_derivative, ptr @ineuron_sigmod_derivative, ptr @ineuron_bipolar_derivative, ptr @ineuron_threshold_derivative, ptr @ineuron_tanh_derivative], align 8

; Function Attrs: nounwind uwtable
define dso_local noalias noundef ptr @ineuron_create(i32 noundef %0, double noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = icmp sgt i32 %0, 0
  br i1 %4, label %6, label %5

5:                                                ; preds = %3
  tail call void @__assert_fail(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 105, ptr noundef nonnull @__PRETTY_FUNCTION__.ineuron_create) #4
  unreachable

6:                                                ; preds = %3
  %7 = zext nneg i32 %0 to i64
  %8 = shl nuw nsw i64 %7, 3
  %9 = add nuw nsw i64 %8, 48
  %10 = tail call noalias ptr @malloc(i64 noundef %9) #5
  %.not = icmp eq ptr %10, null
  br i1 %.not, label %11, label %12

11:                                               ; preds = %6
  tail call void @__assert_fail(ptr noundef nonnull @.str.2, ptr noundef nonnull @.str.1, i32 noundef 109, ptr noundef nonnull @__PRETTY_FUNCTION__.ineuron_create) #4
  unreachable

12:                                               ; preds = %6
  store i32 %0, ptr %10, align 8, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %10, i64 4
  store i32 0, ptr %13, align 4, !tbaa !12
  %14 = getelementptr inbounds i8, ptr %10, i64 8
  store double %1, ptr %14, align 8, !tbaa !13
  %15 = getelementptr inbounds i8, ptr %10, i64 16
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(24) %15, i8 0, i64 24, i1 false)
  %16 = icmp ult i32 %2, 5
  br i1 %16, label %switch.lookup, label %._crit_edge

switch.lookup:                                    ; preds = %12
  %17 = getelementptr inbounds i8, ptr %10, i64 32
  %18 = getelementptr inbounds i8, ptr %10, i64 24
  %19 = zext nneg i32 %2 to i64
  %switch.gep = getelementptr inbounds [5 x ptr], ptr @switch.table.ineuron_create, i64 0, i64 %19
  %switch.load = load ptr, ptr %switch.gep, align 8
  %20 = zext nneg i32 %2 to i64
  %switch.gep32 = getelementptr inbounds [5 x ptr], ptr @switch.table.ineuron_create.1, i64 0, i64 %20
  %switch.load33 = load ptr, ptr %switch.gep32, align 8
  store ptr %switch.load, ptr %18, align 8, !tbaa !14
  store ptr %switch.load33, ptr %17, align 8, !tbaa !15
  br label %._crit_edge

._crit_edge:                                      ; preds = %12, %switch.lookup
  %21 = getelementptr inbounds i8, ptr %10, i64 40
  %22 = zext nneg i32 %0 to i64
  %23 = shl nuw nsw i64 %22, 3
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(1) %21, i8 0, i64 %23, i1 false), !tbaa !16
  ret ptr %10
}

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nofree nounwind willreturn allockind("alloc,uninitialized") allocsize(0) memory(inaccessiblemem: readwrite)
declare noalias noundef ptr @malloc(i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_normal_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_normal_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_sigmod_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_sigmod_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_bipolar_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_bipolar_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_threshold_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_threshold_derivative(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_tanh_function(double noundef) #0

; Function Attrs: nounwind uwtable
declare hidden double @ineuron_tanh_derivative(double noundef) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nofree nounwind willreturn allockind("alloc,uninitialized") allocsize(0) memory(inaccessiblemem: readwrite) "alloc-family"="malloc" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { noreturn nounwind }
attributes #5 = { nounwind allocsize(0) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"INEURON", !7, i64 0, !7, i64 4, !10, i64 8, !10, i64 16, !11, i64 24, !11, i64 32, !8, i64 40}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = !{!"double", !8, i64 0}
!11 = !{!"any pointer", !8, i64 0}
!12 = !{!6, !7, i64 4}
!13 = !{!6, !10, i64 8}
!14 = !{!6, !11, i64 24}
!15 = !{!6, !11, i64 32}
!16 = !{!10, !10, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopIdiomRecognizePass,LoopRotatePass,LoopSimplifyPass,MemCpyOptPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass