; LLVM IR from CLASS-SZ/class_sz :: class-sz/tools (r8lib)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@r8vec_direct_product.contig = external hidden global i32, align 4
@r8vec_direct_product.rep = external hidden global i32, align 4
@r8vec_direct_product.skip = external hidden global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local void @r8vec_direct_product(i32 noundef %0, i32 noundef %1, ptr noundef %2, i32 noundef %3, i32 noundef %4, ptr noundef %5) #1 {
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  store i32 %0, ptr %7, align 4, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !9
  store i32 %3, ptr %10, align 4, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #2
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = icmp eq i32 %17, 0
  br i1 %18, label %19, label %47

19:                                               ; preds = %6
  store i32 1, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  store i32 1, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  %20 = load i32, ptr %11, align 4, !tbaa !5
  store i32 %20, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  store i32 0, ptr %14, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %43, %19
  %22 = load i32, ptr %14, align 4, !tbaa !5
  %23 = load i32, ptr %11, align 4, !tbaa !5
  %24 = icmp slt i32 %22, %23
  br i1 %24, label %25, label %46

25:                                               ; preds = %21
  store i32 0, ptr %13, align 4, !tbaa !5
  br label %26

26:                                               ; preds = %39, %25
  %27 = load i32, ptr %13, align 4, !tbaa !5
  %28 = load i32, ptr %10, align 4, !tbaa !5
  %29 = icmp slt i32 %27, %28
  br i1 %29, label %30, label %42

30:                                               ; preds = %26
  %31 = load ptr, ptr %12, align 8, !tbaa !9
  %32 = load i32, ptr %13, align 4, !tbaa !5
  %33 = load i32, ptr %14, align 4, !tbaa !5
  %34 = load i32, ptr %10, align 4, !tbaa !5
  %35 = mul nsw i32 %33, %34
  %36 = add nsw i32 %32, %35
  %37 = sext i32 %36 to i64
  %38 = getelementptr inbounds double, ptr %31, i64 %37
  store double 0.000000e+00, ptr %38, align 8, !tbaa !11
  br label %39

39:                                               ; preds = %30
  %40 = load i32, ptr %13, align 4, !tbaa !5
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %13, align 4, !tbaa !5
  br label %26, !llvm.loop !13

42:                                               ; preds = %26
  br label %43

43:                                               ; preds = %42
  %44 = load i32, ptr %14, align 4, !tbaa !5
  %45 = add nsw i32 %44, 1
  store i32 %45, ptr %14, align 4, !tbaa !5
  br label %21, !llvm.loop !15

46:                                               ; preds = %21
  br label %47

47:                                               ; preds = %46, %6
  %48 = load i32, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  %49 = load i32, ptr %8, align 4, !tbaa !5
  %50 = sdiv i32 %48, %49
  store i32 %50, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  %51 = load i32, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  %52 = load i32, ptr %8, align 4, !tbaa !5
  %53 = mul nsw i32 %51, %52
  store i32 %53, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  store i32 0, ptr %13, align 4, !tbaa !5
  br label %54

54:                                               ; preds = %100, %47
  %55 = load i32, ptr %13, align 4, !tbaa !5
  %56 = load i32, ptr %8, align 4, !tbaa !5
  %57 = icmp slt i32 %55, %56
  br i1 %57, label %58, label %103

58:                                               ; preds = %54
  %59 = load i32, ptr %13, align 4, !tbaa !5
  %60 = load i32, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  %61 = mul nsw i32 %59, %60
  %62 = add nsw i32 0, %61
  store i32 %62, ptr %16, align 4, !tbaa !5
  store i32 1, ptr %15, align 4, !tbaa !5
  br label %63

63:                                               ; preds = %96, %58
  %64 = load i32, ptr %15, align 4, !tbaa !5
  %65 = load i32, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  %66 = icmp sle i32 %64, %65
  br i1 %66, label %67, label %99

67:                                               ; preds = %63
  %68 = load i32, ptr %16, align 4, !tbaa !5
  store i32 %68, ptr %14, align 4, !tbaa !5
  br label %69

69:                                               ; preds = %89, %67
  %70 = load i32, ptr %14, align 4, !tbaa !5
  %71 = load i32, ptr %16, align 4, !tbaa !5
  %72 = load i32, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  %73 = add nsw i32 %71, %72
  %74 = icmp slt i32 %70, %73
  br i1 %74, label %75, label %92

75:                                               ; preds = %69
  %76 = load ptr, ptr %9, align 8, !tbaa !9
  %77 = load i32, ptr %13, align 4, !tbaa !5
  %78 = sext i32 %77 to i64
  %79 = getelementptr inbounds double, ptr %76, i64 %78
  %80 = load double, ptr %79, align 8, !tbaa !11
  %81 = load ptr, ptr %12, align 8, !tbaa !9
  %82 = load i32, ptr %7, align 4, !tbaa !5
  %83 = load i32, ptr %14, align 4, !tbaa !5
  %84 = load i32, ptr %10, align 4, !tbaa !5
  %85 = mul nsw i32 %83, %84
  %86 = add nsw i32 %82, %85
  %87 = sext i32 %86 to i64
  %88 = getelementptr inbounds double, ptr %81, i64 %87
  store double %80, ptr %88, align 8, !tbaa !11
  br label %89

89:                                               ; preds = %75
  %90 = load i32, ptr %14, align 4, !tbaa !5
  %91 = add nsw i32 %90, 1
  store i32 %91, ptr %14, align 4, !tbaa !5
  br label %69, !llvm.loop !16

92:                                               ; preds = %69
  %93 = load i32, ptr %16, align 4, !tbaa !5
  %94 = load i32, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  %95 = add nsw i32 %93, %94
  store i32 %95, ptr %16, align 4, !tbaa !5
  br label %96

96:                                               ; preds = %92
  %97 = load i32, ptr %15, align 4, !tbaa !5
  %98 = add nsw i32 %97, 1
  store i32 %98, ptr %15, align 4, !tbaa !5
  br label %63, !llvm.loop !17

99:                                               ; preds = %63
  br label %100

100:                                              ; preds = %99
  %101 = load i32, ptr %13, align 4, !tbaa !5
  %102 = add nsw i32 %101, 1
  store i32 %102, ptr %13, align 4, !tbaa !5
  br label %54, !llvm.loop !18

103:                                              ; preds = %54
  %104 = load i32, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  %105 = load i32, ptr %8, align 4, !tbaa !5
  %106 = mul nsw i32 %104, %105
  store i32 %106, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"double", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}
!18 = distinct !{!18, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@r8vec_direct_product.contig = external hidden local_unnamed_addr global i32, align 4
@r8vec_direct_product.rep = external hidden local_unnamed_addr global i32, align 4
@r8vec_direct_product.skip = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: nofree norecurse nosync nounwind memory(readwrite, inaccessiblemem: none) uwtable
define dso_local void @r8vec_direct_product(i32 noundef %0, i32 noundef %1, ptr nocapture noundef readonly %2, i32 noundef %3, i32 noundef %4, ptr nocapture noundef writeonly %5) local_unnamed_addr #0 {
  %7 = icmp eq i32 %0, 0
  br i1 %7, label %8, label %..loopexit_crit_edge

..loopexit_crit_edge:                             ; preds = %6
  %.pre = load i32, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  %.pre63 = load i32, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  %.pre65.pre = load i32, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  br label %.loopexit

8:                                                ; preds = %6
  %9 = icmp sgt i32 %4, 0
  %10 = icmp sgt i32 %3, 0
  %or.cond = and i1 %9, %10
  br i1 %or.cond, label %.preheader37.us.preheader, label %.loopexit

.preheader37.us.preheader:                        ; preds = %8
  %11 = zext nneg i32 %3 to i64
  %12 = zext nneg i32 %4 to i64
  %13 = mul nuw nsw i64 %12, %11
  %14 = shl i64 %13, 3
  tail call void @llvm.memset.p0.i64(ptr align 8 %5, i8 0, i64 %14, i1 false), !tbaa !9
  br label %.loopexit

.loopexit:                                        ; preds = %..loopexit_crit_edge, %.preheader37.us.preheader, %8
  %.pre65 = phi i32 [ %.pre65.pre, %..loopexit_crit_edge ], [ 1, %.preheader37.us.preheader ], [ 1, %8 ]
  %15 = phi i32 [ %.pre63, %..loopexit_crit_edge ], [ 1, %.preheader37.us.preheader ], [ 1, %8 ]
  %16 = phi i32 [ %.pre, %..loopexit_crit_edge ], [ %4, %.preheader37.us.preheader ], [ %4, %8 ]
  %17 = sdiv i32 %16, %1
  store i32 %17, ptr @r8vec_direct_product.rep, align 4, !tbaa !5
  %18 = mul i32 %15, %1
  store i32 %18, ptr @r8vec_direct_product.skip, align 4, !tbaa !5
  %19 = icmp slt i32 %1, 1
  %.not41 = icmp slt i32 %17, 1
  %or.cond67 = select i1 %19, i1 true, i1 %.not41
  br i1 %or.cond67, label %._crit_edge48, label %.preheader.lr.ph.preheader

.preheader.lr.ph.preheader:                       ; preds = %.loopexit
  %20 = sext i32 %18 to i64
  %21 = sext i32 %3 to i64
  %22 = sext i32 %0 to i64
  %23 = sext i32 %.pre65 to i64
  %wide.trip.count = zext nneg i32 %1 to i64
  %24 = icmp sgt i32 %.pre65, 0
  %invariant.gep = getelementptr double, ptr %5, i64 %22
  %ident.check.not = icmp eq i32 %3, 1
  br label %.preheader.lr.ph

.preheader.lr.ph:                                 ; preds = %.preheader.lr.ph.preheader, %._crit_edge44
  %indvars.iv59 = phi i64 [ 0, %.preheader.lr.ph.preheader ], [ %indvars.iv.next60, %._crit_edge44 ]
  %indvars.iv = phi i32 [ 0, %.preheader.lr.ph.preheader ], [ %indvars.iv.next, %._crit_edge44 ]
  %25 = sext i32 %indvars.iv to i64
  %26 = add nsw i64 %23, %25
  %27 = add nsw i64 %25, 1
  %28 = sext i32 %indvars.iv to i64
  %29 = getelementptr inbounds double, ptr %2, i64 %indvars.iv59
  br label %.preheader

.preheader:                                       ; preds = %.preheader.lr.ph, %._crit_edge
  %indvar = phi i64 [ 0, %.preheader.lr.ph ], [ %indvar.next, %._crit_edge ]
  %indvars.iv53 = phi i64 [ %28, %.preheader.lr.ph ], [ %indvars.iv.next54, %._crit_edge ]
  %.03142 = phi i32 [ 1, %.preheader.lr.ph ], [ %43, %._crit_edge ]
  %30 = mul i64 %indvar, %20
  %31 = add i64 %26, %30
  %32 = add i64 %27, %30
  %smax = tail call i64 @llvm.smax.i64(i64 %31, i64 %32)
  %33 = mul i64 %indvar, %20
  %34 = add i64 %33, %25
  %35 = sub i64 %smax, %34
  %36 = add nsw i64 %indvars.iv53, %23
  br i1 %24, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %.preheader
  %.pre64 = load double, ptr %29, align 8, !tbaa !9
  %min.iters.check = icmp ugt i64 %35, 3
  %or.cond68 = and i1 %min.iters.check, %ident.check.not
  br i1 %or.cond68, label %vector.ph, label %.lr.ph.preheader69

vector.ph:                                        ; preds = %.lr.ph.preheader
  %n.vec = and i64 %35, -4
  %ind.end = add i64 %indvars.iv53, %n.vec
  %broadcast.splatinsert = insertelement <2 x double> poison, double %.pre64, i64 0
  %broadcast.splat = shufflevector <2 x double> %broadcast.splatinsert, <2 x double> poison, <2 x i32> zeroinitializer
  %37 = getelementptr double, ptr %invariant.gep, i64 %indvars.iv53
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %vector.ph
  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
  %38 = getelementptr double, ptr %37, i64 %index
  %39 = getelementptr i8, ptr %38, i64 16
  store <2 x double> %broadcast.splat, ptr %38, align 8, !tbaa !9
  store <2 x double> %broadcast.splat, ptr %39, align 8, !tbaa !9
  %index.next = add nuw i64 %index, 4
  %40 = icmp eq i64 %index.next, %n.vec
  br i1 %40, label %middle.block, label %vector.body, !llvm.loop !11

middle.block:                                     ; preds = %vector.body
  %cmp.n = icmp eq i64 %35, %n.vec
  br i1 %cmp.n, label %._crit_edge, label %.lr.ph.preheader69

.lr.ph.preheader69:                               ; preds = %middle.block, %.lr.ph.preheader
  %indvars.iv55.ph = phi i64 [ %indvars.iv53, %.lr.ph.preheader ], [ %ind.end, %middle.block ]
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader69, %.lr.ph
  %indvars.iv55 = phi i64 [ %indvars.iv.next56, %.lr.ph ], [ %indvars.iv55.ph, %.lr.ph.preheader69 ]
  %41 = mul nsw i64 %indvars.iv55, %21
  %gep = getelementptr double, ptr %invariant.gep, i64 %41
  store double %.pre64, ptr %gep, align 8, !tbaa !9
  %indvars.iv.next56 = add nsw i64 %indvars.iv55, 1
  %42 = icmp slt i64 %indvars.iv.next56, %36
  br i1 %42, label %.lr.ph, label %._crit_edge, !llvm.loop !15

._crit_edge:                                      ; preds = %.lr.ph, %middle.block, %.preheader
  %indvars.iv.next54 = add nsw i64 %indvars.iv53, %20
  %43 = add nuw i32 %.03142, 1
  %exitcond.not = icmp eq i32 %.03142, %17
  %indvar.next = add i64 %indvar, 1
  br i1 %exitcond.not, label %._crit_edge44, label %.preheader, !llvm.loop !16

._crit_edge44:                                    ; preds = %._crit_edge
  %indvars.iv.next60 = add nuw nsw i64 %indvars.iv59, 1
  %indvars.iv.next = add i32 %indvars.iv, %.pre65
  %exitcond62.not = icmp eq i64 %indvars.iv.next60, %wide.trip.count
  br i1 %exitcond62.not, label %._crit_edge48, label %.preheader.lr.ph, !llvm.loop !17

._crit_edge48:                                    ; preds = %._crit_edge44, %.loopexit
  %44 = mul nsw i32 %.pre65, %1
  store i32 %44, ptr @r8vec_direct_product.contig, align 4, !tbaa !5
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.smax.i64(i64, i64) #2

attributes #0 = { nofree norecurse nosync nounwind memory(readwrite, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}
!11 = distinct !{!11, !12, !13, !14}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!"llvm.loop.isvectorized", i32 1}
!14 = !{!"llvm.loop.unroll.runtime.disable"}
!15 = distinct !{!15, !12, !13}
!16 = distinct !{!16, !12}
!17 = distinct !{!17, !12}


; Effective O3 passes: BDCEPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopIdiomRecognizePass,LoopInstSimplifyPass,LoopLoadEliminationPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,LoopVectorizePass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass