; LLVM IR from ERGO-Code/HiGHS :: src/lp_data/HighsSolution.ll (Z17isBasisConsistentRK7HighsLpRK10HighsBasis)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.HighsLp = type { i32, i32, %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3", %class.HighsSparseMatrix, i32, double, %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", i32, i32, %"class.std::vector.13", %"class.std::vector.13", %"class.std::vector.18", %struct.HighsNameHash, %struct.HighsNameHash, i32, i32, %struct.HighsScale, i8, i8, i32, i8, %struct.HighsLpMods }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.HighsSparseMatrix = type { i32, i32, i32, %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.3" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.18" = type { %"struct.std::_Vector_base.19" }
%"struct.std::_Vector_base.19" = type { %"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl" }
%"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl" = type { %"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl_data" }
%"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.HighsNameHash = type { %"class.std::unordered_map" }
%"class.std::unordered_map" = type { %"class.std::_Hashtable" }
%"class.std::_Hashtable" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"struct.std::__detail::_Hash_node_base" = type { ptr }
%"struct.std::__detail::_Prime_rehash_policy" = type { float, i64 }
%struct.HighsScale = type { i32, i8, i32, i32, double, %"class.std::vector.3", %"class.std::vector.3" }
%struct.HighsLpMods = type { %"class.std::vector.8", %"class.std::vector.8", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.18", %"class.std::vector.8", %"class.std::vector.3", %"class.std::vector.8", %"class.std::vector.3", %"class.std::vector.8", %"class.std::vector.3", %"class.std::vector.3", %"class.std::vector.3" }
%struct.HighsBasis = type { i8, i8, i8, i8, i32, i32, %"class.std::__cxx11::basic_string", %"class.std::vector.28", %"class.std::vector.28" }
%"class.std::vector.28" = type { %"struct.std::_Vector_base.29" }
%"struct.std::_Vector_base.29" = type { %"struct.std::_Vector_base<HighsBasisStatus, std::allocator<HighsBasisStatus>>::_Vector_impl" }
%"struct.std::_Vector_base<HighsBasisStatus, std::allocator<HighsBasisStatus>>::_Vector_impl" = type { %"struct.std::_Vector_base<HighsBasisStatus, std::allocator<HighsBasisStatus>>::_Vector_impl_data" }
%"struct.std::_Vector_base<HighsBasisStatus, std::allocator<HighsBasisStatus>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z16isBasisRightSizeRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920), ptr noundef nonnull align 8 dereferenceable(96)) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_Z17isBasisConsistentRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920) %0, ptr noundef nonnull align 8 dereferenceable(96) %1) #2 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = load ptr, ptr %5, align 8, !tbaa !5
  %11 = call noundef zeroext i1 @_Z16isBasisRightSizeRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920) %9, ptr noundef nonnull align 8 dereferenceable(96) %10)
  br i1 %11, label %13, label %12

12:                                               ; preds = %2
  store i1 false, ptr %3, align 1
  br label %65

13:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %14

14:                                               ; preds = %33, %13
  %15 = load i32, ptr %7, align 4, !tbaa !9
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = getelementptr inbounds %class.HighsLp, ptr %16, i32 0, i32 0
  %18 = load i32, ptr %17, align 8, !tbaa !11
  %19 = icmp slt i32 %15, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %36

21:                                               ; preds = %14
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds %struct.HighsBasis, ptr %22, i32 0, i32 7
  %24 = load i32, ptr %7, align 4, !tbaa !9
  %25 = sext i32 %24 to i64
  %26 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %25) #3
  %27 = load i8, ptr %26, align 1, !tbaa !45
  %28 = icmp eq i8 %27, 1
  br i1 %28, label %29, label %32

29:                                               ; preds = %21
  %30 = load i32, ptr %6, align 4, !tbaa !9
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %6, align 4, !tbaa !9
  br label %32

32:                                               ; preds = %29, %21
  br label %33

33:                                               ; preds = %32
  %34 = load i32, ptr %7, align 4, !tbaa !9
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %7, align 4, !tbaa !9
  br label %14, !llvm.loop !47

36:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %37

37:                                               ; preds = %56, %36
  %38 = load i32, ptr %8, align 4, !tbaa !9
  %39 = load ptr, ptr %4, align 8, !tbaa !5
  %40 = getelementptr inbounds %class.HighsLp, ptr %39, i32 0, i32 1
  %41 = load i32, ptr %40, align 4, !tbaa !49
  %42 = icmp slt i32 %38, %41
  br i1 %42, label %44, label %43

43:                                               ; preds = %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %59

44:                                               ; preds = %37
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.HighsBasis, ptr %45, i32 0, i32 8
  %47 = load i32, ptr %8, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #3
  %50 = load i8, ptr %49, align 1, !tbaa !45
  %51 = icmp eq i8 %50, 1
  br i1 %51, label %52, label %55

52:                                               ; preds = %44
  %53 = load i32, ptr %6, align 4, !tbaa !9
  %54 = add nsw i32 %53, 1
  store i32 %54, ptr %6, align 4, !tbaa !9
  br label %55

55:                                               ; preds = %52, %44
  br label %56

56:                                               ; preds = %55
  %57 = load i32, ptr %8, align 4, !tbaa !9
  %58 = add nsw i32 %57, 1
  store i32 %58, ptr %8, align 4, !tbaa !9
  br label %37, !llvm.loop !50

59:                                               ; preds = %43
  %60 = load i32, ptr %6, align 4, !tbaa !9
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = getelementptr inbounds %class.HighsLp, ptr %61, i32 0, i32 1
  %63 = load i32, ptr %62, align 4, !tbaa !49
  %64 = icmp eq i32 %60, %63
  store i1 %64, ptr %3, align 1
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  br label %65

65:                                               ; preds = %59, %12
  %66 = load i1, ptr %3, align 1
  ret i1 %66
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 0}
!12 = !{!"_ZTS7HighsLp", !10, i64 0, !10, i64 4, !13, i64 8, !13, i64 32, !13, i64 56, !13, i64 80, !13, i64 104, !17, i64 128, !23, i64 240, !24, i64 248, !25, i64 256, !25, i64 288, !10, i64 320, !10, i64 324, !28, i64 328, !28, i64 352, !32, i64 376, !36, i64 400, !36, i64 456, !10, i64 512, !10, i64 516, !42, i64 520, !43, i64 592, !43, i64 593, !10, i64 596, !43, i64 600, !44, i64 608}
!13 = !{!"_ZTSSt6vectorIdSaIdEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTS17HighsSparseMatrix", !18, i64 0, !10, i64 4, !10, i64 8, !19, i64 16, !19, i64 40, !19, i64 64, !13, i64 88}
!18 = !{!"_ZTS12MatrixFormat", !7, i64 0}
!19 = !{!"_ZTSSt6vectorIiSaIiEE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTS8ObjSense", !7, i64 0}
!24 = !{!"double", !7, i64 0}
!25 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !26, i64 0, !27, i64 8, !7, i64 16}
!26 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!27 = !{!"long", !7, i64 0}
!28 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!"_ZTSSt6vectorI12HighsVarTypeSaIS0_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseI12HighsVarTypeSaIS0_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!36 = !{!"_ZTS13HighsNameHash", !37, i64 0}
!37 = !{!"_ZTSSt13unordered_mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiSt4hashIS5_ESt8equal_toIS5_ESaISt4pairIKS5_iEEE", !38, i64 0}
!38 = !{!"_ZTSSt10_HashtableINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_iESaIS8_ENSt8__detail10_Select1stESt8equal_toIS5_ESt4hashIS5_ENSA_18_Mod_range_hashingENSA_20_Default_ranged_hashENSA_20_Prime_rehash_policyENSA_17_Hashtable_traitsILb1ELb0ELb1EEEE", !6, i64 0, !27, i64 8, !39, i64 16, !27, i64 24, !40, i64 32, !6, i64 48}
!39 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !6, i64 0}
!40 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !41, i64 0, !27, i64 8}
!41 = !{!"float", !7, i64 0}
!42 = !{!"_ZTS10HighsScale", !10, i64 0, !43, i64 4, !10, i64 8, !10, i64 12, !24, i64 16, !13, i64 24, !13, i64 48}
!43 = !{!"bool", !7, i64 0}
!44 = !{!"_ZTS11HighsLpMods", !19, i64 0, !19, i64 24, !13, i64 48, !13, i64 72, !32, i64 96, !19, i64 120, !13, i64 144, !19, i64 168, !13, i64 192, !19, i64 216, !13, i64 240, !13, i64 264, !13, i64 288}
!45 = !{!46, !46, i64 0}
!46 = !{!"_ZTS16HighsBasisStatus", !7, i64 0}
!47 = distinct !{!47, !48}
!48 = !{!"llvm.loop.mustprogress"}
!49 = !{!12, !10, i64 4}
!50 = distinct !{!50, !48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_Z16isBasisRightSizeRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920), ptr noundef nonnull align 8 dereferenceable(96)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z17isBasisConsistentRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920) %0, ptr noundef nonnull align 8 dereferenceable(96) %1) local_unnamed_addr #0 {
  %3 = tail call noundef zeroext i1 @_Z16isBasisRightSizeRK7HighsLpRK10HighsBasis(ptr noundef nonnull align 8 dereferenceable(920) %0, ptr noundef nonnull align 8 dereferenceable(96) %1)
  br i1 %3, label %.preheader21, label %28

.preheader21:                                     ; preds = %2
  %4 = load i32, ptr %0, align 8, !tbaa !5
  %5 = icmp sgt i32 %4, 0
  br i1 %5, label %.lr.ph, label %.preheader

.lr.ph:                                           ; preds = %.preheader21
  %6 = getelementptr inbounds i8, ptr %1, i64 48
  br label %11

.preheader:                                       ; preds = %11, %.preheader21
  %.017.lcssa = phi i32 [ 0, %.preheader21 ], [ %spec.select, %11 ]
  %7 = getelementptr inbounds i8, ptr %0, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !43
  %9 = icmp sgt i32 %8, 0
  br i1 %9, label %.lr.ph26, label %._crit_edge

.lr.ph26:                                         ; preds = %.preheader
  %10 = getelementptr inbounds i8, ptr %1, i64 72
  br label %20

11:                                               ; preds = %.lr.ph, %11
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %11 ]
  %.01722 = phi i32 [ 0, %.lr.ph ], [ %spec.select, %11 ]
  %12 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %indvars.iv) #1
  %13 = load i8, ptr %12, align 1, !tbaa !44
  %14 = icmp eq i8 %13, 1
  %15 = zext i1 %14 to i32
  %spec.select = add nuw nsw i32 %.01722, %15
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %16 = load i32, ptr %0, align 8, !tbaa !5
  %17 = sext i32 %16 to i64
  %18 = icmp slt i64 %indvars.iv.next, %17
  br i1 %18, label %11, label %.preheader, !llvm.loop !46

._crit_edge:                                      ; preds = %20, %.preheader
  %.2.lcssa = phi i32 [ %.017.lcssa, %.preheader ], [ %spec.select20, %20 ]
  %.lcssa = phi i32 [ %8, %.preheader ], [ %25, %20 ]
  %19 = icmp eq i32 %.2.lcssa, %.lcssa
  br label %28

20:                                               ; preds = %.lr.ph26, %20
  %indvars.iv31 = phi i64 [ 0, %.lr.ph26 ], [ %indvars.iv.next32, %20 ]
  %.224 = phi i32 [ %.017.lcssa, %.lr.ph26 ], [ %spec.select20, %20 ]
  %21 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNKSt6vectorI16HighsBasisStatusSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %10, i64 noundef %indvars.iv31) #1
  %22 = load i8, ptr %21, align 1, !tbaa !44
  %23 = icmp eq i8 %22, 1
  %24 = zext i1 %23 to i32
  %spec.select20 = add nsw i32 %.224, %24
  %indvars.iv.next32 = add nuw nsw i64 %indvars.iv31, 1
  %25 = load i32, ptr %7, align 4, !tbaa !43
  %26 = sext i32 %25 to i64
  %27 = icmp slt i64 %indvars.iv.next32, %26
  br i1 %27, label %20, label %._crit_edge, !llvm.loop !48

28:                                               ; preds = %2, %._crit_edge
  %.018 = phi i1 [ %19, %._crit_edge ], [ false, %2 ]
  ret i1 %.018
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS7HighsLp", !7, i64 0, !7, i64 4, !10, i64 8, !10, i64 32, !10, i64 56, !10, i64 80, !10, i64 104, !15, i64 128, !21, i64 240, !22, i64 248, !23, i64 256, !23, i64 288, !7, i64 320, !7, i64 324, !26, i64 328, !26, i64 352, !30, i64 376, !34, i64 400, !34, i64 456, !7, i64 512, !7, i64 516, !40, i64 520, !41, i64 592, !41, i64 593, !7, i64 596, !41, i64 600, !42, i64 608}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIdSaIdEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!"_ZTS17HighsSparseMatrix", !16, i64 0, !7, i64 4, !7, i64 8, !17, i64 16, !17, i64 40, !17, i64 64, !10, i64 88}
!16 = !{!"_ZTS12MatrixFormat", !8, i64 0}
!17 = !{!"_ZTSSt6vectorIiSaIiEE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!21 = !{!"_ZTS8ObjSense", !8, i64 0}
!22 = !{!"double", !8, i64 0}
!23 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !24, i64 0, !25, i64 8, !8, i64 16}
!24 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !14, i64 0}
!25 = !{!"long", !8, i64 0}
!26 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!30 = !{!"_ZTSSt6vectorI12HighsVarTypeSaIS0_EE", !31, i64 0}
!31 = !{!"_ZTSSt12_Vector_baseI12HighsVarTypeSaIS0_EE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE12_Vector_implE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!34 = !{!"_ZTS13HighsNameHash", !35, i64 0}
!35 = !{!"_ZTSSt13unordered_mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiSt4hashIS5_ESt8equal_toIS5_ESaISt4pairIKS5_iEEE", !36, i64 0}
!36 = !{!"_ZTSSt10_HashtableINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_iESaIS8_ENSt8__detail10_Select1stESt8equal_toIS5_ESt4hashIS5_ENSA_18_Mod_range_hashingENSA_20_Default_ranged_hashENSA_20_Prime_rehash_policyENSA_17_Hashtable_traitsILb1ELb0ELb1EEEE", !14, i64 0, !25, i64 8, !37, i64 16, !25, i64 24, !38, i64 32, !14, i64 48}
!37 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !14, i64 0}
!38 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !39, i64 0, !25, i64 8}
!39 = !{!"float", !8, i64 0}
!40 = !{!"_ZTS10HighsScale", !7, i64 0, !41, i64 4, !7, i64 8, !7, i64 12, !22, i64 16, !10, i64 24, !10, i64 48}
!41 = !{!"bool", !8, i64 0}
!42 = !{!"_ZTS11HighsLpMods", !17, i64 0, !17, i64 24, !10, i64 48, !10, i64 72, !30, i64 96, !17, i64 120, !10, i64 144, !17, i64 168, !10, i64 192, !17, i64 216, !10, i64 240, !10, i64 264, !10, i64 288}
!43 = !{!6, !7, i64 4}
!44 = !{!45, !45, i64 0}
!45 = !{!"_ZTS16HighsBasisStatus", !8, i64 0}
!46 = distinct !{!46, !47}
!47 = !{!"llvm.loop.mustprogress"}
!48 = distinct !{!48, !47}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass