; LLVM IR from rweather/lightweight-crypto :: src/genavr/code.ll (ZN4Code9ld_xor_inERK3RegN4Insn4TypeEj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7tempregEv(ptr noundef nonnull align 8 dereferenceable(200)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext, i32 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code9ld_xor_inERK3RegN4Insn4TypeEj(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, i32 noundef %3) #2 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !9
  store i32 %3, ptr %8, align 4, !tbaa !11
  %12 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  %13 = call noundef zeroext i8 @_ZN4Code7tempregEv(ptr noundef nonnull align 8 dereferenceable(200) %12)
  store i8 %13, ptr %9, align 1, !tbaa !13
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14)
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %4
  br label %122

18:                                               ; preds = %4
  %19 = load i32, ptr %8, align 4, !tbaa !11
  %20 = load ptr, ptr %6, align 8, !tbaa !5
  %21 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %20)
  %22 = add nsw i32 %19, %21
  %23 = icmp sle i32 %22, 64
  br i1 %23, label %24, label %61

24:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !11
  br label %25

25:                                               ; preds = %57, %24
  %26 = load i32, ptr %10, align 4, !tbaa !11
  %27 = load ptr, ptr %6, align 8, !tbaa !5
  %28 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %27)
  %29 = icmp slt i32 %26, %28
  br i1 %29, label %31, label %30

30:                                               ; preds = %25
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  br label %60

31:                                               ; preds = %25
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = load i8, ptr %9, align 1, !tbaa !13
  %34 = load i32, ptr %8, align 4, !tbaa !11
  %35 = load i32, ptr %10, align 4, !tbaa !11
  %36 = add i32 %34, %35
  %37 = trunc i32 %36 to i8
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %32, i8 noundef zeroext %33, i8 noundef zeroext %37)
  %38 = load i8, ptr %9, align 1, !tbaa !13
  %39 = load ptr, ptr %6, align 8, !tbaa !5
  %40 = load i32, ptr %10, align 4, !tbaa !11
  %41 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %39, i32 noundef %40)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 19, i8 noundef zeroext %38, i8 noundef zeroext %41)
  %42 = load i32, ptr %7, align 4, !tbaa !9
  %43 = icmp eq i32 %42, 24
  br i1 %43, label %44, label %50

44:                                               ; preds = %31
  %45 = load i8, ptr %9, align 1, !tbaa !13
  %46 = load i32, ptr %8, align 4, !tbaa !11
  %47 = load i32, ptr %10, align 4, !tbaa !11
  %48 = add i32 %46, %47
  %49 = trunc i32 %48 to i8
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 54, i8 noundef zeroext %45, i8 noundef zeroext %49)
  br label %56

50:                                               ; preds = %31
  %51 = load i8, ptr %9, align 1, !tbaa !13
  %52 = load i32, ptr %8, align 4, !tbaa !11
  %53 = load i32, ptr %10, align 4, !tbaa !11
  %54 = add i32 %52, %53
  %55 = trunc i32 %54 to i8
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 55, i8 noundef zeroext %51, i8 noundef zeroext %55)
  br label %56

56:                                               ; preds = %50, %44
  br label %57

57:                                               ; preds = %56
  %58 = load i32, ptr %10, align 4, !tbaa !11
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr %10, align 4, !tbaa !11
  br label %25, !llvm.loop !14

60:                                               ; preds = %30
  br label %121

61:                                               ; preds = %18
  %62 = load i32, ptr %7, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 24
  br i1 %63, label %64, label %66

64:                                               ; preds = %61
  %65 = load i32, ptr %8, align 4, !tbaa !11
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 28, i32 noundef %65)
  br label %68

66:                                               ; preds = %61
  %67 = load i32, ptr %8, align 4, !tbaa !11
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 30, i32 noundef %67)
  br label %68

68:                                               ; preds = %66, %64
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !11
  br label %69

69:                                               ; preds = %90, %68
  %70 = load i32, ptr %11, align 4, !tbaa !11
  %71 = load ptr, ptr %6, align 8, !tbaa !5
  %72 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %71)
  %73 = sub nsw i32 %72, 1
  %74 = icmp slt i32 %70, %73
  br i1 %74, label %76, label %75

75:                                               ; preds = %69
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %93

76:                                               ; preds = %69
  %77 = load i32, ptr %7, align 4, !tbaa !9
  %78 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %77, i8 noundef zeroext %78, i8 noundef zeroext 0)
  %79 = load i8, ptr %9, align 1, !tbaa !13
  %80 = load ptr, ptr %6, align 8, !tbaa !5
  %81 = load i32, ptr %11, align 4, !tbaa !11
  %82 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %80, i32 noundef %81)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 19, i8 noundef zeroext %79, i8 noundef zeroext %82)
  %83 = load i32, ptr %7, align 4, !tbaa !9
  %84 = icmp eq i32 %83, 24
  br i1 %84, label %85, label %87

85:                                               ; preds = %76
  %86 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 54, i8 noundef zeroext %86, i8 noundef zeroext -1)
  br label %89

87:                                               ; preds = %76
  %88 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 55, i8 noundef zeroext %88, i8 noundef zeroext -1)
  br label %89

89:                                               ; preds = %87, %85
  br label %90

90:                                               ; preds = %89
  %91 = load i32, ptr %11, align 4, !tbaa !11
  %92 = add nsw i32 %91, 1
  store i32 %92, ptr %11, align 4, !tbaa !11
  br label %69, !llvm.loop !16

93:                                               ; preds = %75
  %94 = load i32, ptr %7, align 4, !tbaa !9
  %95 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef %94, i8 noundef zeroext %95, i8 noundef zeroext 0)
  %96 = load i8, ptr %9, align 1, !tbaa !13
  %97 = load ptr, ptr %6, align 8, !tbaa !5
  %98 = load ptr, ptr %6, align 8, !tbaa !5
  %99 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %98)
  %100 = sub nsw i32 %99, 1
  %101 = call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %97, i32 noundef %100)
  call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 19, i8 noundef zeroext %96, i8 noundef zeroext %101)
  %102 = load i32, ptr %7, align 4, !tbaa !9
  %103 = icmp eq i32 %102, 24
  br i1 %103, label %104, label %112

104:                                              ; preds = %93
  %105 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 54, i8 noundef zeroext %105, i8 noundef zeroext 0)
  %106 = load i32, ptr %8, align 4, !tbaa !11
  %107 = load ptr, ptr %6, align 8, !tbaa !5
  %108 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %107)
  %109 = add i32 %106, %108
  %110 = sub i32 %109, 1
  %111 = sub i32 0, %110
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 28, i32 noundef %111)
  br label %120

112:                                              ; preds = %93
  %113 = load i8, ptr %9, align 1, !tbaa !13
  call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %12, i32 noundef 55, i8 noundef zeroext %113, i8 noundef zeroext 0)
  %114 = load i32, ptr %8, align 4, !tbaa !11
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %115)
  %117 = add i32 %114, %116
  %118 = sub i32 %117, 1
  %119 = sub i32 0, %118
  call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %12, i8 noundef zeroext 30, i32 noundef %119)
  br label %120

120:                                              ; preds = %112, %104
  br label %121

121:                                              ; preds = %120, %60
  br label %122

122:                                              ; preds = %121, %17
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTSN4Insn4TypeE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}
!16 = distinct !{!16, !15}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i8 @_ZN4Code7tempregEv(ptr noundef nonnull align 8 dereferenceable(200)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200), i32 noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200), i8 noundef zeroext, i32 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN4Code9ld_xor_inERK3RegN4Insn4TypeEj(ptr noundef nonnull align 8 dereferenceable(200) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #1 align 2 {
  %5 = tail call noundef zeroext i8 @_ZN4Code7tempregEv(ptr noundef nonnull align 8 dereferenceable(200) %0)
  %6 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %7 = icmp eq i32 %6, 0
  br i1 %7, label %.loopexit, label %8

8:                                                ; preds = %4
  %9 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %10 = add nsw i32 %9, %3
  %11 = icmp slt i32 %10, 65
  br i1 %11, label %.preheader, label %27

.preheader:                                       ; preds = %8
  %12 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %13 = icmp sgt i32 %12, 0
  br i1 %13, label %.lr.ph53, label %.loopexit

.lr.ph53:                                         ; preds = %.preheader
  %14 = icmp eq i32 %2, 24
  br i1 %14, label %.lr.ph53.split.us, label %.lr.ph53.split

.lr.ph53.split.us:                                ; preds = %.lr.ph53, %.lr.ph53.split.us
  %.04652.us = phi i32 [ %18, %.lr.ph53.split.us ], [ 0, %.lr.ph53 ]
  %15 = add i32 %.04652.us, %3
  %16 = trunc i32 %15 to i8
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 24, i8 noundef zeroext %5, i8 noundef zeroext %16)
  %17 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.04652.us)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 19, i8 noundef zeroext %5, i8 noundef zeroext %17)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 54, i8 noundef zeroext %5, i8 noundef zeroext %16)
  %18 = add nuw nsw i32 %.04652.us, 1
  %19 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %20 = icmp slt i32 %18, %19
  br i1 %20, label %.lr.ph53.split.us, label %.loopexit, !llvm.loop !5

.lr.ph53.split:                                   ; preds = %.lr.ph53, %.lr.ph53.split
  %.04652 = phi i32 [ %24, %.lr.ph53.split ], [ 0, %.lr.ph53 ]
  %21 = add i32 %.04652, %3
  %22 = trunc i32 %21 to i8
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %5, i8 noundef zeroext %22)
  %23 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.04652)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 19, i8 noundef zeroext %5, i8 noundef zeroext %23)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 55, i8 noundef zeroext %5, i8 noundef zeroext %22)
  %24 = add nuw nsw i32 %.04652, 1
  %25 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %26 = icmp slt i32 %24, %25
  br i1 %26, label %.lr.ph53.split, label %.loopexit, !llvm.loop !5

27:                                               ; preds = %8
  %28 = icmp eq i32 %2, 24
  br i1 %28, label %29, label %.thread

29:                                               ; preds = %27
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext 28, i32 noundef %3)
  %30 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %31 = icmp sgt i32 %30, 1
  br i1 %31, label %.lr.ph.split.us, label %._crit_edge

.thread:                                          ; preds = %27
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext 30, i32 noundef %3)
  %32 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %33 = icmp sgt i32 %32, 1
  br i1 %33, label %.lr.ph.split, label %._crit_edge

.lr.ph.split.us:                                  ; preds = %29, %.lr.ph.split.us
  %.051.us = phi i32 [ %35, %.lr.ph.split.us ], [ 0, %29 ]
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 24, i8 noundef zeroext %5, i8 noundef zeroext 0)
  %34 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.051.us)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 19, i8 noundef zeroext %5, i8 noundef zeroext %34)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 54, i8 noundef zeroext %5, i8 noundef zeroext -1)
  %35 = add nuw nsw i32 %.051.us, 1
  %36 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %37 = add nsw i32 %36, -1
  %38 = icmp slt i32 %35, %37
  br i1 %38, label %.lr.ph.split.us, label %._crit_edge, !llvm.loop !7

._crit_edge:                                      ; preds = %.lr.ph.split, %.lr.ph.split.us, %.thread, %29
  %.62 = phi i8 [ 30, %.thread ], [ 28, %29 ], [ 28, %.lr.ph.split.us ], [ 30, %.lr.ph.split ]
  %. = phi i32 [ 55, %.thread ], [ 54, %29 ], [ 54, %.lr.ph.split.us ], [ 55, %.lr.ph.split ]
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %5, i8 noundef zeroext 0)
  %39 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %40 = add nsw i32 %39, -1
  %41 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %40)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 19, i8 noundef zeroext %5, i8 noundef zeroext %41)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %., i8 noundef zeroext %5, i8 noundef zeroext 0)
  %42 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %43 = add i32 %42, %3
  %44 = sub i32 1, %43
  tail call void @_ZN4Code7add_ptrEhi(ptr noundef nonnull align 8 dereferenceable(200) %0, i8 noundef zeroext %.62, i32 noundef %44)
  br label %.loopexit

.lr.ph.split:                                     ; preds = %.thread, %.lr.ph.split
  %.051 = phi i32 [ %46, %.lr.ph.split ], [ 0, %.thread ]
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef %2, i8 noundef zeroext %5, i8 noundef zeroext 0)
  %45 = tail call noundef zeroext i8 @_ZNK3Reg3regEi(ptr noundef nonnull align 8 dereferenceable(24) %1, i32 noundef %.051)
  tail call void @_ZN4Code6tworegEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 19, i8 noundef zeroext %5, i8 noundef zeroext %45)
  tail call void @_ZN4Code6memoryEN4Insn4TypeEhh(ptr noundef nonnull align 8 dereferenceable(200) %0, i32 noundef 55, i8 noundef zeroext %5, i8 noundef zeroext -1)
  %46 = add nuw nsw i32 %.051, 1
  %47 = tail call noundef i32 @_ZNK3Reg4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %1)
  %48 = add nsw i32 %47, -1
  %49 = icmp slt i32 %46, %48
  br i1 %49, label %.lr.ph.split, label %._crit_edge, !llvm.loop !7

.loopexit:                                        ; preds = %.lr.ph53.split, %.lr.ph53.split.us, %._crit_edge, %.preheader, %4
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass