; LLVM IR from ERGO-Code/HiGHS :: src/simplex (HSimplexNlaDebug)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.HSimplexNla = type { ptr, ptr, ptr, ptr, ptr, ptr, %class.HFactor, i8, double, %struct.ProductFormUpdate, %struct.SimplexIterate }
%class.HFactor = type { double, double, i32, %"class.std::vector", %"class.std::vector", %"class.std::vector", %struct.RefactorInfo, i32, i32, i32, i32, i32, i32, i32, double, i8, ptr, ptr, ptr, ptr, double, double, i32, double, %"class.std::unique_ptr", %struct.HighsLogOptions, i8, i8, i32, i32, ptr, i32, %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.15", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", i32, i32, %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %class.HVectorBase }
%struct.RefactorInfo = type { i8, %"class.std::vector", %"class.std::vector", %"class.std::vector.3", double }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<signed char, std::allocator<signed char>>::_Vector_impl" }
%"struct.std::_Vector_base<signed char, std::allocator<signed char>>::_Vector_impl" = type { %"struct.std::_Vector_base<signed char, std::allocator<signed char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<signed char, std::allocator<signed char>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::unique_ptr" = type { %"struct.std::__uniq_ptr_data" }
%"struct.std::__uniq_ptr_data" = type { %"class.std::__uniq_ptr_impl" }
%"class.std::__uniq_ptr_impl" = type { %"class.std::tuple" }
%"class.std::tuple" = type { %"struct.std::_Tuple_impl" }
%"struct.std::_Tuple_impl" = type { %"struct.std::_Head_base.9" }
%"struct.std::_Head_base.9" = type { ptr }
%struct.HighsLogOptions = type <{ ptr, ptr, ptr, ptr, ptr, ptr, %"class.std::function", ptr, i8, [7 x i8] }>
%"class.std::function" = type { %"class.std::_Function_base", ptr }
%"class.std::_Function_base" = type { %"union.std::_Any_data", ptr }
%"union.std::_Any_data" = type { %"union.std::_Nocopy_types" }
%"union.std::_Nocopy_types" = type { { i64, i64 } }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.HVectorBase = type { i32, i32, %"class.std::vector", %"class.std::vector.10", double, %"class.std::vector.15", %"class.std::vector", ptr, i8, i32, %"class.std::vector", %"class.std::vector.10" }
%struct.ProductFormUpdate = type { i8, i32, i32, %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10" }
%struct.SimplexIterate = type { i8, %struct.SimplexBasis, %struct.InvertibleRepresentation, %"class.std::vector.10" }
%struct.SimplexBasis = type { %"class.std::vector", %"class.std::vector.3", %"class.std::vector.3", i64, i32, i32, %"class.std::__cxx11::basic_string" }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%struct.InvertibleRepresentation = type { %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector.10" }
%class.HighsLp = type { i32, i32, %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.10", %class.HighsSparseMatrix, i32, double, %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", i32, i32, %"class.std::vector.22", %"class.std::vector.22", %"class.std::vector.27", %struct.HighsNameHash, %struct.HighsNameHash, i32, i32, %struct.HighsScale, i8, i8, i32, i8, %struct.HighsLpMods }
%class.HighsSparseMatrix = type { i32, i32, i32, %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.10" }
%"class.std::vector.22" = type { %"struct.std::_Vector_base.23" }
%"struct.std::_Vector_base.23" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.27" = type { %"struct.std::_Vector_base.28" }
%"struct.std::_Vector_base.28" = type { %"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl" }
%"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl" = type { %"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl_data" }
%"struct.std::_Vector_base<HighsVarType, std::allocator<HighsVarType>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.HighsNameHash = type { %"class.std::unordered_map" }
%"class.std::unordered_map" = type { %"class.std::_Hashtable" }
%"class.std::_Hashtable" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"struct.std::__detail::_Hash_node_base" = type { ptr }
%"struct.std::__detail::_Prime_rehash_policy" = type { float, i64 }
%struct.HighsScale = type { i32, i8, i32, i32, double, %"class.std::vector.10", %"class.std::vector.10" }
%struct.HighsLpMods = type { %"class.std::vector", %"class.std::vector", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.27", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector.10", %"class.std::vector", %"class.std::vector.10", %"class.std::vector.10", %"class.std::vector.10" }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIdERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef double @_ZNK11HSimplexNla24debugInvertResidualErrorEbRK11HVectorBaseIdERS1_(ptr noundef nonnull align 8 dereferenceable(2864) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(176) %2, ptr noundef nonnull align 8 dereferenceable(176) %3) #4 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca double, align 8
  %21 = alloca i32, align 4
  %22 = alloca double, align 8
  %23 = alloca i32, align 4
  %24 = alloca double, align 8
  %25 = alloca i32, align 4
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca i32, align 4
  %29 = alloca double, align 8
  %30 = alloca i32, align 4
  %31 = alloca double, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  %32 = zext i1 %1 to i8
  store i8 %32, ptr %6, align 1, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %33 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %34 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !11
  %36 = getelementptr inbounds %class.HighsLp, ptr %35, i32 0, i32 1
  %37 = load i32, ptr %36, align 4, !tbaa !50
  store i32 %37, ptr %9, align 4, !tbaa !71
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %38 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 0
  %39 = load ptr, ptr %38, align 8, !tbaa !11
  %40 = getelementptr inbounds %class.HighsLp, ptr %39, i32 0, i32 0
  %41 = load i32, ptr %40, align 8, !tbaa !72
  store i32 %41, ptr %10, align 4, !tbaa !71
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #5
  %42 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 0
  %43 = load ptr, ptr %42, align 8, !tbaa !11
  %44 = getelementptr inbounds %class.HighsLp, ptr %43, i32 0, i32 7
  %45 = getelementptr inbounds %class.HighsSparseMatrix, ptr %44, i32 0, i32 3
  store ptr %45, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #5
  %46 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 0
  %47 = load ptr, ptr %46, align 8, !tbaa !11
  %48 = getelementptr inbounds %class.HighsLp, ptr %47, i32 0, i32 7
  %49 = getelementptr inbounds %class.HighsSparseMatrix, ptr %48, i32 0, i32 5
  store ptr %49, ptr %12, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #5
  %50 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 0
  %51 = load ptr, ptr %50, align 8, !tbaa !11
  %52 = getelementptr inbounds %class.HighsLp, ptr %51, i32 0, i32 7
  %53 = getelementptr inbounds %class.HighsSparseMatrix, ptr %52, i32 0, i32 6
  store ptr %53, ptr %13, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #5
  %54 = getelementptr inbounds %class.HSimplexNla, ptr %33, i32 0, i32 2
  %55 = load ptr, ptr %54, align 8, !tbaa !73
  store ptr %55, ptr %14, align 8, !tbaa !5
  %56 = load i8, ptr %6, align 1, !tbaa !9, !range !74, !noundef !75
  %57 = trunc i8 %56 to i1
  br i1 %57, label %58, label %142

58:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #5
  store i32 0, ptr %15, align 4, !tbaa !71
  br label %59

59:                                               ; preds = %138, %58
  %60 = load i32, ptr %15, align 4, !tbaa !71
  %61 = load i32, ptr %9, align 4, !tbaa !71
  %62 = icmp slt i32 %60, %61
  br i1 %62, label %64, label %63

63:                                               ; preds = %59
  store i32 2, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #5
  br label %141

64:                                               ; preds = %59
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #5
  %65 = load ptr, ptr %14, align 8, !tbaa !5
  %66 = load i32, ptr %15, align 4, !tbaa !71
  %67 = sext i32 %66 to i64
  %68 = getelementptr inbounds i32, ptr %65, i64 %67
  %69 = load i32, ptr %68, align 4, !tbaa !71
  store i32 %69, ptr %17, align 4, !tbaa !71
  %70 = load i32, ptr %17, align 4, !tbaa !71
  %71 = load i32, ptr %10, align 4, !tbaa !71
  %72 = icmp slt i32 %70, %71
  br i1 %72, label %73, label %119

73:                                               ; preds = %64
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #5
  %74 = load ptr, ptr %11, align 8, !tbaa !5
  %75 = load i32, ptr %17, align 4, !tbaa !71
  %76 = sext i32 %75 to i64
  %77 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %74, i64 noundef %76) #5
  %78 = load i32, ptr %77, align 4, !tbaa !71
  store i32 %78, ptr %18, align 4, !tbaa !71
  br label %79

79:                                               ; preds = %115, %73
  %80 = load i32, ptr %18, align 4, !tbaa !71
  %81 = load ptr, ptr %11, align 8, !tbaa !5
  %82 = load i32, ptr %17, align 4, !tbaa !71
  %83 = add nsw i32 %82, 1
  %84 = sext i32 %83 to i64
  %85 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %81, i64 noundef %84) #5
  %86 = load i32, ptr %85, align 4, !tbaa !71
  %87 = icmp slt i32 %80, %86
  br i1 %87, label %89, label %88

88:                                               ; preds = %79
  store i32 5, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #5
  br label %118

89:                                               ; preds = %79
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #5
  %90 = load ptr, ptr %12, align 8, !tbaa !5
  %91 = load i32, ptr %18, align 4, !tbaa !71
  %92 = sext i32 %91 to i64
  %93 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %90, i64 noundef %92) #5
  %94 = load i32, ptr %93, align 4, !tbaa !71
  store i32 %94, ptr %19, align 4, !tbaa !71
  call void @llvm.lifetime.start.p0(i64 8, ptr %20) #5
  %95 = load ptr, ptr %7, align 8, !tbaa !5
  %96 = getelementptr inbounds %class.HVectorBase, ptr %95, i32 0, i32 3
  %97 = load i32, ptr %19, align 4, !tbaa !71
  %98 = sext i32 %97 to i64
  %99 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %96, i64 noundef %98) #5
  %100 = load double, ptr %99, align 8, !tbaa !76
  store double %100, ptr %20, align 8, !tbaa !76
  %101 = load double, ptr %20, align 8, !tbaa !76
  %102 = load ptr, ptr %13, align 8, !tbaa !5
  %103 = load i32, ptr %18, align 4, !tbaa !71
  %104 = sext i32 %103 to i64
  %105 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %102, i64 noundef %104) #5
  %106 = load double, ptr %105, align 8, !tbaa !76
  %107 = load ptr, ptr %8, align 8, !tbaa !5
  %108 = getelementptr inbounds %class.HVectorBase, ptr %107, i32 0, i32 3
  %109 = load i32, ptr %15, align 4, !tbaa !71
  %110 = sext i32 %109 to i64
  %111 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %108, i64 noundef %110) #5
  %112 = load double, ptr %111, align 8, !tbaa !76
  %113 = fneg double %101
  %114 = call double @llvm.fmuladd.f64(double %113, double %106, double %112)
  store double %114, ptr %111, align 8, !tbaa !76
  call void @llvm.lifetime.end.p0(i64 8, ptr %20) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #5
  br label %115

115:                                              ; preds = %89
  %116 = load i32, ptr %18, align 4, !tbaa !71
  %117 = add nsw i32 %116, 1
  store i32 %117, ptr %18, align 4, !tbaa !71
  br label %79, !llvm.loop !77

118:                                              ; preds = %88
  br label %137

119:                                              ; preds = %64
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #5
  %120 = load i32, ptr %17, align 4, !tbaa !71
  %121 = load i32, ptr %10, align 4, !tbaa !71
  %122 = sub nsw i32 %120, %121
  store i32 %122, ptr %21, align 4, !tbaa !71
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #5
  %123 = load ptr, ptr %7, align 8, !tbaa !5
  %124 = getelementptr inbounds %class.HVectorBase, ptr %123, i32 0, i32 3
  %125 = load i32, ptr %21, align 4, !tbaa !71
  %126 = sext i32 %125 to i64
  %127 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %124, i64 noundef %126) #5
  %128 = load double, ptr %127, align 8, !tbaa !76
  store double %128, ptr %22, align 8, !tbaa !76
  %129 = load double, ptr %22, align 8, !tbaa !76
  %130 = load ptr, ptr %8, align 8, !tbaa !5
  %131 = getelementptr inbounds %class.HVectorBase, ptr %130, i32 0, i32 3
  %132 = load i32, ptr %15, align 4, !tbaa !71
  %133 = sext i32 %132 to i64
  %134 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %131, i64 noundef %133) #5
  %135 = load double, ptr %134, align 8, !tbaa !76
  %136 = fsub double %135, %129
  store double %136, ptr %134, align 8, !tbaa !76
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #5
  br label %137

137:                                              ; preds = %119, %118
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #5
  br label %138

138:                                              ; preds = %137
  %139 = load i32, ptr %15, align 4, !tbaa !71
  %140 = add nsw i32 %139, 1
  store i32 %140, ptr %15, align 4, !tbaa !71
  br label %59, !llvm.loop !79

141:                                              ; preds = %63
  br label %220

142:                                              ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #5
  store i32 0, ptr %23, align 4, !tbaa !71
  br label %143

143:                                              ; preds = %216, %142
  %144 = load i32, ptr %23, align 4, !tbaa !71
  %145 = load i32, ptr %9, align 4, !tbaa !71
  %146 = icmp slt i32 %144, %145
  br i1 %146, label %148, label %147

147:                                              ; preds = %143
  store i32 8, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #5
  br label %219

148:                                              ; preds = %143
  call void @llvm.lifetime.start.p0(i64 8, ptr %24) #5
  %149 = load ptr, ptr %7, align 8, !tbaa !5
  %150 = getelementptr inbounds %class.HVectorBase, ptr %149, i32 0, i32 3
  %151 = load i32, ptr %23, align 4, !tbaa !71
  %152 = sext i32 %151 to i64
  %153 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %150, i64 noundef %152) #5
  %154 = load double, ptr %153, align 8, !tbaa !76
  store double %154, ptr %24, align 8, !tbaa !76
  call void @llvm.lifetime.start.p0(i64 4, ptr %25) #5
  %155 = load ptr, ptr %14, align 8, !tbaa !5
  %156 = load i32, ptr %23, align 4, !tbaa !71
  %157 = sext i32 %156 to i64
  %158 = getelementptr inbounds i32, ptr %155, i64 %157
  %159 = load i32, ptr %158, align 4, !tbaa !71
  store i32 %159, ptr %25, align 4, !tbaa !71
  %160 = load i32, ptr %25, align 4, !tbaa !71
  %161 = load i32, ptr %10, align 4, !tbaa !71
  %162 = icmp slt i32 %160, %161
  br i1 %162, label %163, label %203

163:                                              ; preds = %148
  call void @llvm.lifetime.start.p0(i64 4, ptr %26) #5
  %164 = load ptr, ptr %11, align 8, !tbaa !5
  %165 = load i32, ptr %25, align 4, !tbaa !71
  %166 = sext i32 %165 to i64
  %167 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %164, i64 noundef %166) #5
  %168 = load i32, ptr %167, align 4, !tbaa !71
  store i32 %168, ptr %26, align 4, !tbaa !71
  br label %169

169:                                              ; preds = %199, %163
  %170 = load i32, ptr %26, align 4, !tbaa !71
  %171 = load ptr, ptr %11, align 8, !tbaa !5
  %172 = load i32, ptr %25, align 4, !tbaa !71
  %173 = add nsw i32 %172, 1
  %174 = sext i32 %173 to i64
  %175 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %171, i64 noundef %174) #5
  %176 = load i32, ptr %175, align 4, !tbaa !71
  %177 = icmp slt i32 %170, %176
  br i1 %177, label %179, label %178

178:                                              ; preds = %169
  store i32 11, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %26) #5
  br label %202

179:                                              ; preds = %169
  call void @llvm.lifetime.start.p0(i64 4, ptr %27) #5
  %180 = load ptr, ptr %12, align 8, !tbaa !5
  %181 = load i32, ptr %26, align 4, !tbaa !71
  %182 = sext i32 %181 to i64
  %183 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %180, i64 noundef %182) #5
  %184 = load i32, ptr %183, align 4, !tbaa !71
  store i32 %184, ptr %27, align 4, !tbaa !71
  %185 = load double, ptr %24, align 8, !tbaa !76
  %186 = load ptr, ptr %13, align 8, !tbaa !5
  %187 = load i32, ptr %26, align 4, !tbaa !71
  %188 = sext i32 %187 to i64
  %189 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %186, i64 noundef %188) #5
  %190 = load double, ptr %189, align 8, !tbaa !76
  %191 = load ptr, ptr %8, align 8, !tbaa !5
  %192 = getelementptr inbounds %class.HVectorBase, ptr %191, i32 0, i32 3
  %193 = load i32, ptr %27, align 4, !tbaa !71
  %194 = sext i32 %193 to i64
  %195 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %192, i64 noundef %194) #5
  %196 = load double, ptr %195, align 8, !tbaa !76
  %197 = fneg double %185
  %198 = call double @llvm.fmuladd.f64(double %197, double %190, double %196)
  store double %198, ptr %195, align 8, !tbaa !76
  call void @llvm.lifetime.end.p0(i64 4, ptr %27) #5
  br label %199

199:                                              ; preds = %179
  %200 = load i32, ptr %26, align 4, !tbaa !71
  %201 = add nsw i32 %200, 1
  store i32 %201, ptr %26, align 4, !tbaa !71
  br label %169, !llvm.loop !80

202:                                              ; preds = %178
  br label %215

203:                                              ; preds = %148
  call void @llvm.lifetime.start.p0(i64 4, ptr %28) #5
  %204 = load i32, ptr %25, align 4, !tbaa !71
  %205 = load i32, ptr %10, align 4, !tbaa !71
  %206 = sub nsw i32 %204, %205
  store i32 %206, ptr %28, align 4, !tbaa !71
  %207 = load double, ptr %24, align 8, !tbaa !76
  %208 = load ptr, ptr %8, align 8, !tbaa !5
  %209 = getelementptr inbounds %class.HVectorBase, ptr %208, i32 0, i32 3
  %210 = load i32, ptr %28, align 4, !tbaa !71
  %211 = sext i32 %210 to i64
  %212 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %209, i64 noundef %211) #5
  %213 = load double, ptr %212, align 8, !tbaa !76
  %214 = fsub double %213, %207
  store double %214, ptr %212, align 8, !tbaa !76
  call void @llvm.lifetime.end.p0(i64 4, ptr %28) #5
  br label %215

215:                                              ; preds = %203, %202
  call void @llvm.lifetime.end.p0(i64 4, ptr %25) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %24) #5
  br label %216

216:                                              ; preds = %215
  %217 = load i32, ptr %23, align 4, !tbaa !71
  %218 = add nsw i32 %217, 1
  store i32 %218, ptr %23, align 4, !tbaa !71
  br label %143, !llvm.loop !81

219:                                              ; preds = %147
  br label %220

220:                                              ; preds = %219, %141
  call void @llvm.lifetime.start.p0(i64 8, ptr %29) #5
  store double 0.000000e+00, ptr %29, align 8, !tbaa !76
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #5
  store i32 0, ptr %30, align 4, !tbaa !71
  br label %221

221:                                              ; preds = %236, %220
  %222 = load i32, ptr %30, align 4, !tbaa !71
  %223 = load i32, ptr %9, align 4, !tbaa !71
  %224 = icmp slt i32 %222, %223
  br i1 %224, label %226, label %225

225:                                              ; preds = %221
  store i32 14, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #5
  br label %239

226:                                              ; preds = %221
  call void @llvm.lifetime.start.p0(i64 8, ptr %31) #5
  %227 = load ptr, ptr %8, align 8, !tbaa !5
  %228 = getelementptr inbounds %class.HVectorBase, ptr %227, i32 0, i32 3
  %229 = load i32, ptr %30, align 4, !tbaa !71
  %230 = sext i32 %229 to i64
  %231 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %228, i64 noundef %230) #5
  %232 = load double, ptr %231, align 8, !tbaa !76
  %233 = call double @llvm.fabs.f64(double %232)
  store double %233, ptr %31, align 8, !tbaa !76
  %234 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIdERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %31, ptr noundef nonnull align 8 dereferenceable(8) %29)
  %235 = load double, ptr %234, align 8, !tbaa !76
  store double %235, ptr %29, align 8, !tbaa !76
  call void @llvm.lifetime.end.p0(i64 8, ptr %31) #5
  br label %236

236:                                              ; preds = %226
  %237 = load i32, ptr %30, align 4, !tbaa !71
  %238 = add nsw i32 %237, 1
  store i32 %238, ptr %30, align 4, !tbaa !71
  br label %221, !llvm.loop !82

239:                                              ; preds = %225
  %240 = load double, ptr %29, align 8, !tbaa !76
  store i32 1, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %29) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  ret double %240
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"_ZTS11HSimplexNla", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !13, i64 48, !10, i64 1960, !14, i64 1968, !43, i64 1976, !44, i64 2112}
!13 = !{!"_ZTS7HFactor", !14, i64 0, !14, i64 8, !15, i64 16, !16, i64 24, !16, i64 48, !16, i64 72, !20, i64 96, !15, i64 184, !15, i64 188, !15, i64 192, !15, i64 196, !15, i64 200, !15, i64 204, !15, i64 208, !14, i64 216, !10, i64 224, !6, i64 232, !6, i64 240, !6, i64 248, !6, i64 256, !14, i64 264, !14, i64 272, !15, i64 280, !14, i64 288, !25, i64 296, !31, i64 304, !10, i64 400, !10, i64 401, !15, i64 404, !15, i64 408, !6, i64 416, !15, i64 424, !16, i64 432, !34, i64 456, !16, i64 480, !16, i64 504, !16, i64 528, !34, i64 552, !16, i64 576, !16, i64 600, !16, i64 624, !16, i64 648, !16, i64 672, !16, i64 696, !16, i64 720, !34, i64 744, !34, i64 768, !16, i64 792, !16, i64 816, !16, i64 840, !16, i64 864, !16, i64 888, !16, i64 912, !38, i64 936, !34, i64 960, !16, i64 984, !16, i64 1008, !16, i64 1032, !16, i64 1056, !16, i64 1080, !16, i64 1104, !16, i64 1128, !16, i64 1152, !16, i64 1176, !16, i64 1200, !34, i64 1224, !16, i64 1248, !16, i64 1272, !34, i64 1296, !16, i64 1320, !16, i64 1344, !34, i64 1368, !15, i64 1392, !15, i64 1396, !16, i64 1400, !16, i64 1424, !16, i64 1448, !34, i64 1472, !16, i64 1496, !16, i64 1520, !16, i64 1544, !16, i64 1568, !34, i64 1592, !34, i64 1616, !16, i64 1640, !16, i64 1664, !16, i64 1688, !34, i64 1712, !42, i64 1736}
!14 = !{!"double", !7, i64 0}
!15 = !{!"int", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIiSaIiEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTS12RefactorInfo", !10, i64 0, !16, i64 8, !16, i64 32, !21, i64 56, !14, i64 80}
!21 = !{!"_ZTSSt6vectorIaSaIaEE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIaSaIaEE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIaSaIaEE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIaSaIaEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt10unique_ptrIN7HFactor7LogDataESt14default_deleteIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt15__uniq_ptr_dataIN7HFactor7LogDataESt14default_deleteIS1_ELb1ELb1EE", !27, i64 0}
!27 = !{!"_ZTSSt15__uniq_ptr_implIN7HFactor7LogDataESt14default_deleteIS1_EE", !28, i64 0}
!28 = !{!"_ZTSSt5tupleIJPN7HFactor7LogDataESt14default_deleteIS1_EEE", !29, i64 0}
!29 = !{!"_ZTSSt11_Tuple_implILm0EJPN7HFactor7LogDataESt14default_deleteIS1_EEE", !30, i64 0}
!30 = !{!"_ZTSSt10_Head_baseILm0EPN7HFactor7LogDataELb0EE", !6, i64 0}
!31 = !{!"_ZTS15HighsLogOptions", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !32, i64 48, !6, i64 80, !10, i64 88}
!32 = !{!"_ZTSSt8functionIFviRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPK20HighsCallbackDataOutP19HighsCallbackDataInPvEE", !33, i64 0, !6, i64 24}
!33 = !{!"_ZTSSt14_Function_base", !7, i64 0, !6, i64 16}
!34 = !{!"_ZTSSt6vectorIdSaIdEE", !35, i64 0}
!35 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !37, i64 0}
!37 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!38 = !{!"_ZTSSt6vectorIcSaIcEE", !39, i64 0}
!39 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !40, i64 0}
!40 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !41, i64 0}
!41 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!42 = !{!"_ZTS11HVectorBaseIdE", !15, i64 0, !15, i64 4, !16, i64 8, !34, i64 32, !14, i64 56, !38, i64 64, !16, i64 88, !6, i64 112, !10, i64 120, !15, i64 124, !16, i64 128, !34, i64 152}
!43 = !{!"_ZTS17ProductFormUpdate", !10, i64 0, !15, i64 4, !15, i64 8, !16, i64 16, !34, i64 40, !16, i64 64, !16, i64 88, !34, i64 112}
!44 = !{!"_ZTS14SimplexIterate", !10, i64 0, !45, i64 8, !49, i64 128, !34, i64 728}
!45 = !{!"_ZTS12SimplexBasis", !16, i64 0, !21, i64 24, !21, i64 48, !46, i64 72, !15, i64 80, !15, i64 84, !47, i64 88}
!46 = !{!"long", !7, i64 0}
!47 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !48, i64 0, !46, i64 8, !7, i64 16}
!48 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !6, i64 0}
!49 = !{!"_ZTS24InvertibleRepresentation", !16, i64 0, !16, i64 24, !16, i64 48, !16, i64 72, !34, i64 96, !16, i64 120, !16, i64 144, !34, i64 168, !16, i64 192, !16, i64 216, !34, i64 240, !16, i64 264, !16, i64 288, !16, i64 312, !34, i64 336, !16, i64 360, !16, i64 384, !16, i64 408, !16, i64 432, !34, i64 456, !16, i64 480, !16, i64 504, !34, i64 528, !16, i64 552, !34, i64 576}
!50 = !{!51, !15, i64 4}
!51 = !{!"_ZTS7HighsLp", !15, i64 0, !15, i64 4, !34, i64 8, !34, i64 32, !34, i64 56, !34, i64 80, !34, i64 104, !52, i64 128, !54, i64 240, !14, i64 248, !47, i64 256, !47, i64 288, !15, i64 320, !15, i64 324, !55, i64 328, !55, i64 352, !59, i64 376, !63, i64 400, !63, i64 456, !15, i64 512, !15, i64 516, !69, i64 520, !10, i64 592, !10, i64 593, !15, i64 596, !10, i64 600, !70, i64 608}
!52 = !{!"_ZTS17HighsSparseMatrix", !53, i64 0, !15, i64 4, !15, i64 8, !16, i64 16, !16, i64 40, !16, i64 64, !34, i64 88}
!53 = !{!"_ZTS12MatrixFormat", !7, i64 0}
!54 = !{!"_ZTS8ObjSense", !7, i64 0}
!55 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !56, i64 0}
!56 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !57, i64 0}
!57 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !58, i64 0}
!58 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!59 = !{!"_ZTSSt6vectorI12HighsVarTypeSaIS0_EE", !60, i64 0}
!60 = !{!"_ZTSSt12_Vector_baseI12HighsVarTypeSaIS0_EE", !61, i64 0}
!61 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE12_Vector_implE", !62, i64 0}
!62 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!63 = !{!"_ZTS13HighsNameHash", !64, i64 0}
!64 = !{!"_ZTSSt13unordered_mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiSt4hashIS5_ESt8equal_toIS5_ESaISt4pairIKS5_iEEE", !65, i64 0}
!65 = !{!"_ZTSSt10_HashtableINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_iESaIS8_ENSt8__detail10_Select1stESt8equal_toIS5_ESt4hashIS5_ENSA_18_Mod_range_hashingENSA_20_Default_ranged_hashENSA_20_Prime_rehash_policyENSA_17_Hashtable_traitsILb1ELb0ELb1EEEE", !6, i64 0, !46, i64 8, !66, i64 16, !46, i64 24, !67, i64 32, !6, i64 48}
!66 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !6, i64 0}
!67 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !68, i64 0, !46, i64 8}
!68 = !{!"float", !7, i64 0}
!69 = !{!"_ZTS10HighsScale", !15, i64 0, !10, i64 4, !15, i64 8, !15, i64 12, !14, i64 16, !34, i64 24, !34, i64 48}
!70 = !{!"_ZTS11HighsLpMods", !16, i64 0, !16, i64 24, !34, i64 48, !34, i64 72, !59, i64 96, !16, i64 120, !34, i64 144, !16, i64 168, !34, i64 192, !16, i64 216, !34, i64 240, !34, i64 264, !34, i64 288}
!71 = !{!15, !15, i64 0}
!72 = !{!51, !15, i64 0}
!73 = !{!12, !6, i64 16}
!74 = !{i8 0, i8 2}
!75 = !{}
!76 = !{!14, !14, i64 0}
!77 = distinct !{!77, !78}
!78 = !{!"llvm.loop.mustprogress"}
!79 = distinct !{!79, !78}
!80 = distinct !{!80, !78}
!81 = distinct !{!81, !78}
!82 = distinct !{!82, !78}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fabs.f64(double) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIdERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef double @_ZNK11HSimplexNla24debugInvertResidualErrorEbRK11HVectorBaseIdERS1_(ptr nocapture noundef nonnull readonly align 8 dereferenceable(2864) %0, i1 noundef zeroext %1, ptr noundef nonnull align 8 dereferenceable(176) %2, ptr noundef nonnull align 8 dereferenceable(176) %3) local_unnamed_addr #1 align 2 {
  %5 = alloca double, align 8
  %6 = alloca double, align 8
  %7 = load ptr, ptr %0, align 8, !tbaa !5
  %8 = getelementptr inbounds i8, ptr %7, i64 4
  %9 = load i32, ptr %8, align 4, !tbaa !48
  %10 = load i32, ptr %7, align 8, !tbaa !69
  %11 = getelementptr inbounds i8, ptr %7, i64 144
  %12 = getelementptr inbounds i8, ptr %7, i64 192
  %13 = getelementptr inbounds i8, ptr %7, i64 216
  %14 = getelementptr inbounds i8, ptr %0, i64 16
  %15 = load ptr, ptr %14, align 8, !tbaa !70
  %16 = icmp sgt i32 %9, 0
  br i1 %1, label %.preheader, label %.preheader73

.preheader73:                                     ; preds = %4
  br i1 %16, label %.lr.ph77, label %.loopexit71.thread

.lr.ph77:                                         ; preds = %.preheader73
  %17 = getelementptr inbounds i8, ptr %2, i64 32
  %18 = getelementptr inbounds i8, ptr %3, i64 32
  %wide.trip.count = zext nneg i32 %9 to i64
  br label %58

.preheader:                                       ; preds = %4
  br i1 %16, label %.lr.ph81, label %.loopexit71.thread

.lr.ph81:                                         ; preds = %.preheader
  %19 = getelementptr inbounds i8, ptr %2, i64 32
  %20 = getelementptr inbounds i8, ptr %3, i64 32
  %wide.trip.count95 = zext nneg i32 %9 to i64
  br label %21

21:                                               ; preds = %.lr.ph81, %.loopexit
  %indvars.iv92 = phi i64 [ 0, %.lr.ph81 ], [ %indvars.iv.next93, %.loopexit ]
  %22 = getelementptr inbounds i32, ptr %15, i64 %indvars.iv92
  %23 = load i32, ptr %22, align 4, !tbaa !71
  %24 = icmp slt i32 %23, %10
  br i1 %24, label %25, label %50

25:                                               ; preds = %21
  %26 = sext i32 %23 to i64
  %27 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %26) #4
  %28 = load i32, ptr %27, align 4, !tbaa !71
  %29 = add nsw i32 %23, 1
  %30 = sext i32 %29 to i64
  %31 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %30) #4
  %32 = load i32, ptr %31, align 4, !tbaa !71
  %33 = icmp slt i32 %28, %32
  br i1 %33, label %.lr.ph79.preheader, label %.loopexit

.lr.ph79.preheader:                               ; preds = %25
  %34 = sext i32 %28 to i64
  br label %.lr.ph79

.lr.ph79:                                         ; preds = %.lr.ph79.preheader, %.lr.ph79
  %indvars.iv89 = phi i64 [ %34, %.lr.ph79.preheader ], [ %indvars.iv.next90, %.lr.ph79 ]
  %35 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv89) #4
  %36 = load i32, ptr %35, align 4, !tbaa !71
  %37 = sext i32 %36 to i64
  %38 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %37) #4
  %39 = load double, ptr %38, align 8, !tbaa !72
  %40 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %indvars.iv89) #4
  %41 = load double, ptr %40, align 8, !tbaa !72
  %42 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %indvars.iv92) #4
  %43 = load double, ptr %42, align 8, !tbaa !72
  %44 = fneg double %39
  %45 = tail call double @llvm.fmuladd.f64(double %44, double %41, double %43)
  store double %45, ptr %42, align 8, !tbaa !72
  %indvars.iv.next90 = add nsw i64 %indvars.iv89, 1
  %46 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %30) #4
  %47 = load i32, ptr %46, align 4, !tbaa !71
  %48 = sext i32 %47 to i64
  %49 = icmp slt i64 %indvars.iv.next90, %48
  br i1 %49, label %.lr.ph79, label %.loopexit, !llvm.loop !73

50:                                               ; preds = %21
  %51 = sub nsw i32 %23, %10
  %52 = sext i32 %51 to i64
  %53 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %52) #4
  %54 = load double, ptr %53, align 8, !tbaa !72
  %55 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %indvars.iv92) #4
  %56 = load double, ptr %55, align 8, !tbaa !72
  %57 = fsub double %56, %54
  store double %57, ptr %55, align 8, !tbaa !72
  br label %.loopexit

.loopexit:                                        ; preds = %.lr.ph79, %25, %50
  %indvars.iv.next93 = add nuw nsw i64 %indvars.iv92, 1
  %exitcond96.not = icmp eq i64 %indvars.iv.next93, %wide.trip.count95
  br i1 %exitcond96.not, label %.loopexit71, label %21, !llvm.loop !75

58:                                               ; preds = %.lr.ph77, %.loopexit72
  %indvars.iv86 = phi i64 [ 0, %.lr.ph77 ], [ %indvars.iv.next87, %.loopexit72 ]
  %59 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %indvars.iv86) #4
  %60 = load double, ptr %59, align 8, !tbaa !72
  %61 = getelementptr inbounds i32, ptr %15, i64 %indvars.iv86
  %62 = load i32, ptr %61, align 4, !tbaa !71
  %63 = icmp slt i32 %62, %10
  br i1 %63, label %64, label %88

64:                                               ; preds = %58
  %65 = sext i32 %62 to i64
  %66 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %65) #4
  %67 = load i32, ptr %66, align 4, !tbaa !71
  %68 = add nsw i32 %62, 1
  %69 = sext i32 %68 to i64
  %70 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %69) #4
  %71 = load i32, ptr %70, align 4, !tbaa !71
  %72 = icmp slt i32 %67, %71
  br i1 %72, label %.lr.ph, label %.loopexit72

.lr.ph:                                           ; preds = %64
  %73 = fneg double %60
  %74 = sext i32 %67 to i64
  br label %75

75:                                               ; preds = %.lr.ph, %75
  %indvars.iv = phi i64 [ %74, %.lr.ph ], [ %indvars.iv.next, %75 ]
  %76 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %indvars.iv) #4
  %77 = load i32, ptr %76, align 4, !tbaa !71
  %78 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %indvars.iv) #4
  %79 = load double, ptr %78, align 8, !tbaa !72
  %80 = sext i32 %77 to i64
  %81 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %80) #4
  %82 = load double, ptr %81, align 8, !tbaa !72
  %83 = tail call double @llvm.fmuladd.f64(double %73, double %79, double %82)
  store double %83, ptr %81, align 8, !tbaa !72
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %84 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %69) #4
  %85 = load i32, ptr %84, align 4, !tbaa !71
  %86 = sext i32 %85 to i64
  %87 = icmp slt i64 %indvars.iv.next, %86
  br i1 %87, label %75, label %.loopexit72, !llvm.loop !76

88:                                               ; preds = %58
  %89 = sub nsw i32 %62, %10
  %90 = sext i32 %89 to i64
  %91 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %90) #4
  %92 = load double, ptr %91, align 8, !tbaa !72
  %93 = fsub double %92, %60
  store double %93, ptr %91, align 8, !tbaa !72
  br label %.loopexit72

.loopexit72:                                      ; preds = %75, %64, %88
  %indvars.iv.next87 = add nuw nsw i64 %indvars.iv86, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next87, %wide.trip.count
  br i1 %exitcond.not, label %.loopexit71, label %58, !llvm.loop !77

.loopexit71.thread:                               ; preds = %.preheader73, %.preheader
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #4
  br label %._crit_edge

.loopexit71:                                      ; preds = %.loopexit72, %.loopexit
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #4
  store double 0.000000e+00, ptr %5, align 8, !tbaa !72
  %94 = icmp sgt i32 %9, 0
  br i1 %94, label %.lr.ph83, label %._crit_edge

.lr.ph83:                                         ; preds = %.loopexit71
  %95 = getelementptr inbounds i8, ptr %3, i64 32
  %wide.trip.count100 = zext nneg i32 %9 to i64
  br label %97

._crit_edge:                                      ; preds = %97, %.loopexit71.thread, %.loopexit71
  %96 = phi double [ 0.000000e+00, %.loopexit71 ], [ 0.000000e+00, %.loopexit71.thread ], [ %102, %97 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #4
  ret double %96

97:                                               ; preds = %.lr.ph83, %97
  %indvars.iv97 = phi i64 [ 0, %.lr.ph83 ], [ %indvars.iv.next98, %97 ]
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %6) #4
  %98 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %95, i64 noundef %indvars.iv97) #4
  %99 = load double, ptr %98, align 8, !tbaa !72
  %100 = call double @llvm.fabs.f64(double %99)
  store double %100, ptr %6, align 8, !tbaa !72
  %101 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIdERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %5)
  %102 = load double, ptr %101, align 8, !tbaa !72
  store double %102, ptr %5, align 8, !tbaa !72
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %6) #4
  %indvars.iv.next98 = add nuw nsw i64 %indvars.iv97, 1
  %exitcond101.not = icmp eq i64 %indvars.iv.next98, %wide.trip.count100
  br i1 %exitcond101.not, label %._crit_edge, label %97, !llvm.loop !78
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS11HSimplexNla", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !10, i64 48, !18, i64 1960, !11, i64 1968, !41, i64 1976, !42, i64 2112}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS7HFactor", !11, i64 0, !11, i64 8, !12, i64 16, !13, i64 24, !13, i64 48, !13, i64 72, !17, i64 96, !12, i64 184, !12, i64 188, !12, i64 192, !12, i64 196, !12, i64 200, !12, i64 204, !12, i64 208, !11, i64 216, !18, i64 224, !7, i64 232, !7, i64 240, !7, i64 248, !7, i64 256, !11, i64 264, !11, i64 272, !12, i64 280, !11, i64 288, !23, i64 296, !29, i64 304, !18, i64 400, !18, i64 401, !12, i64 404, !12, i64 408, !7, i64 416, !12, i64 424, !13, i64 432, !32, i64 456, !13, i64 480, !13, i64 504, !13, i64 528, !32, i64 552, !13, i64 576, !13, i64 600, !13, i64 624, !13, i64 648, !13, i64 672, !13, i64 696, !13, i64 720, !32, i64 744, !32, i64 768, !13, i64 792, !13, i64 816, !13, i64 840, !13, i64 864, !13, i64 888, !13, i64 912, !36, i64 936, !32, i64 960, !13, i64 984, !13, i64 1008, !13, i64 1032, !13, i64 1056, !13, i64 1080, !13, i64 1104, !13, i64 1128, !13, i64 1152, !13, i64 1176, !13, i64 1200, !32, i64 1224, !13, i64 1248, !13, i64 1272, !32, i64 1296, !13, i64 1320, !13, i64 1344, !32, i64 1368, !12, i64 1392, !12, i64 1396, !13, i64 1400, !13, i64 1424, !13, i64 1448, !32, i64 1472, !13, i64 1496, !13, i64 1520, !13, i64 1544, !13, i64 1568, !32, i64 1592, !32, i64 1616, !13, i64 1640, !13, i64 1664, !13, i64 1688, !32, i64 1712, !40, i64 1736}
!11 = !{!"double", !8, i64 0}
!12 = !{!"int", !8, i64 0}
!13 = !{!"_ZTSSt6vectorIiSaIiEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!17 = !{!"_ZTS12RefactorInfo", !18, i64 0, !13, i64 8, !13, i64 32, !19, i64 56, !11, i64 80}
!18 = !{!"bool", !8, i64 0}
!19 = !{!"_ZTSSt6vectorIaSaIaEE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIaSaIaEE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIaSaIaEE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIaSaIaEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!23 = !{!"_ZTSSt10unique_ptrIN7HFactor7LogDataESt14default_deleteIS1_EE", !24, i64 0}
!24 = !{!"_ZTSSt15__uniq_ptr_dataIN7HFactor7LogDataESt14default_deleteIS1_ELb1ELb1EE", !25, i64 0}
!25 = !{!"_ZTSSt15__uniq_ptr_implIN7HFactor7LogDataESt14default_deleteIS1_EE", !26, i64 0}
!26 = !{!"_ZTSSt5tupleIJPN7HFactor7LogDataESt14default_deleteIS1_EEE", !27, i64 0}
!27 = !{!"_ZTSSt11_Tuple_implILm0EJPN7HFactor7LogDataESt14default_deleteIS1_EEE", !28, i64 0}
!28 = !{!"_ZTSSt10_Head_baseILm0EPN7HFactor7LogDataELb0EE", !7, i64 0}
!29 = !{!"_ZTS15HighsLogOptions", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !30, i64 48, !7, i64 80, !18, i64 88}
!30 = !{!"_ZTSSt8functionIFviRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPK20HighsCallbackDataOutP19HighsCallbackDataInPvEE", !31, i64 0, !7, i64 24}
!31 = !{!"_ZTSSt14_Function_base", !8, i64 0, !7, i64 16}
!32 = !{!"_ZTSSt6vectorIdSaIdEE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!36 = !{!"_ZTSSt6vectorIcSaIcEE", !37, i64 0}
!37 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !38, i64 0}
!38 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !39, i64 0}
!39 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!40 = !{!"_ZTS11HVectorBaseIdE", !12, i64 0, !12, i64 4, !13, i64 8, !32, i64 32, !11, i64 56, !36, i64 64, !13, i64 88, !7, i64 112, !18, i64 120, !12, i64 124, !13, i64 128, !32, i64 152}
!41 = !{!"_ZTS17ProductFormUpdate", !18, i64 0, !12, i64 4, !12, i64 8, !13, i64 16, !32, i64 40, !13, i64 64, !13, i64 88, !32, i64 112}
!42 = !{!"_ZTS14SimplexIterate", !18, i64 0, !43, i64 8, !47, i64 128, !32, i64 728}
!43 = !{!"_ZTS12SimplexBasis", !13, i64 0, !19, i64 24, !19, i64 48, !44, i64 72, !12, i64 80, !12, i64 84, !45, i64 88}
!44 = !{!"long", !8, i64 0}
!45 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !46, i64 0, !44, i64 8, !8, i64 16}
!46 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !7, i64 0}
!47 = !{!"_ZTS24InvertibleRepresentation", !13, i64 0, !13, i64 24, !13, i64 48, !13, i64 72, !32, i64 96, !13, i64 120, !13, i64 144, !32, i64 168, !13, i64 192, !13, i64 216, !32, i64 240, !13, i64 264, !13, i64 288, !13, i64 312, !32, i64 336, !13, i64 360, !13, i64 384, !13, i64 408, !13, i64 432, !32, i64 456, !13, i64 480, !13, i64 504, !32, i64 528, !13, i64 552, !32, i64 576}
!48 = !{!49, !12, i64 4}
!49 = !{!"_ZTS7HighsLp", !12, i64 0, !12, i64 4, !32, i64 8, !32, i64 32, !32, i64 56, !32, i64 80, !32, i64 104, !50, i64 128, !52, i64 240, !11, i64 248, !45, i64 256, !45, i64 288, !12, i64 320, !12, i64 324, !53, i64 328, !53, i64 352, !57, i64 376, !61, i64 400, !61, i64 456, !12, i64 512, !12, i64 516, !67, i64 520, !18, i64 592, !18, i64 593, !12, i64 596, !18, i64 600, !68, i64 608}
!50 = !{!"_ZTS17HighsSparseMatrix", !51, i64 0, !12, i64 4, !12, i64 8, !13, i64 16, !13, i64 40, !13, i64 64, !32, i64 88}
!51 = !{!"_ZTS12MatrixFormat", !8, i64 0}
!52 = !{!"_ZTS8ObjSense", !8, i64 0}
!53 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !54, i64 0}
!54 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !55, i64 0}
!55 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !56, i64 0}
!56 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!57 = !{!"_ZTSSt6vectorI12HighsVarTypeSaIS0_EE", !58, i64 0}
!58 = !{!"_ZTSSt12_Vector_baseI12HighsVarTypeSaIS0_EE", !59, i64 0}
!59 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE12_Vector_implE", !60, i64 0}
!60 = !{!"_ZTSNSt12_Vector_baseI12HighsVarTypeSaIS0_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!61 = !{!"_ZTS13HighsNameHash", !62, i64 0}
!62 = !{!"_ZTSSt13unordered_mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEiSt4hashIS5_ESt8equal_toIS5_ESaISt4pairIKS5_iEEE", !63, i64 0}
!63 = !{!"_ZTSSt10_HashtableINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_iESaIS8_ENSt8__detail10_Select1stESt8equal_toIS5_ESt4hashIS5_ENSA_18_Mod_range_hashingENSA_20_Default_ranged_hashENSA_20_Prime_rehash_policyENSA_17_Hashtable_traitsILb1ELb0ELb1EEEE", !7, i64 0, !44, i64 8, !64, i64 16, !44, i64 24, !65, i64 32, !7, i64 48}
!64 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !7, i64 0}
!65 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !66, i64 0, !44, i64 8}
!66 = !{!"float", !8, i64 0}
!67 = !{!"_ZTS10HighsScale", !12, i64 0, !18, i64 4, !12, i64 8, !12, i64 12, !11, i64 16, !32, i64 24, !32, i64 48}
!68 = !{!"_ZTS11HighsLpMods", !13, i64 0, !13, i64 24, !32, i64 48, !32, i64 72, !57, i64 96, !13, i64 120, !32, i64 144, !13, i64 168, !32, i64 192, !13, i64 216, !32, i64 240, !32, i64 264, !32, i64 288}
!69 = !{!49, !12, i64 0}
!70 = !{!6, !7, i64 16}
!71 = !{!12, !12, i64 0}
!72 = !{!11, !11, i64 0}
!73 = distinct !{!73, !74}
!74 = !{!"llvm.loop.mustprogress"}
!75 = distinct !{!75, !74}
!76 = distinct !{!76, !74}
!77 = distinct !{!77, !74}
!78 = distinct !{!78, !74}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass