; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/URI/1905/main.ll (Z3dfsii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vis = external dso_local global %"class.std::vector", align 8
@co = external dso_local global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %5 = load i32, ptr %3, align 4, !tbaa !5
  %6 = icmp sge i32 %5, 0
  br i1 %6, label %7, label %146

7:                                                ; preds = %2
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = icmp slt i32 %8, 5
  br i1 %9, label %10, label %146

10:                                               ; preds = %7
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = icmp sge i32 %11, 0
  br i1 %12, label %13, label %146

13:                                               ; preds = %10
  %14 = load i32, ptr %4, align 4, !tbaa !5
  %15 = icmp slt i32 %14, 5
  br i1 %15, label %16, label %146

16:                                               ; preds = %13
  %17 = load i32, ptr @co, align 4, !tbaa !5
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %146, label %19

19:                                               ; preds = %16
  %20 = load i32, ptr %3, align 4, !tbaa !5
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %21) #2
  %23 = load i32, ptr %4, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %24) #2
  store i32 1, ptr %25, align 4, !tbaa !5
  %26 = load i32, ptr %3, align 4, !tbaa !5
  %27 = icmp eq i32 %26, 4
  br i1 %27, label %28, label %32

28:                                               ; preds = %19
  %29 = load i32, ptr %4, align 4, !tbaa !5
  %30 = icmp eq i32 %29, 4
  br i1 %30, label %31, label %32

31:                                               ; preds = %28
  store i32 1, ptr @co, align 4, !tbaa !5
  br label %145

32:                                               ; preds = %28, %19
  %33 = load i32, ptr %3, align 4, !tbaa !5
  %34 = add nsw i32 %33, 1
  %35 = icmp slt i32 %34, 5
  br i1 %35, label %36, label %60

36:                                               ; preds = %32
  %37 = load i32, ptr %3, align 4, !tbaa !5
  %38 = add nsw i32 %37, 1
  %39 = sext i32 %38 to i64
  %40 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %39) #2
  %41 = load i32, ptr %4, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %40, i64 noundef %42) #2
  %44 = load i32, ptr %43, align 4, !tbaa !5
  %45 = icmp eq i32 %44, 0
  br i1 %45, label %46, label %60

46:                                               ; preds = %36
  %47 = load i32, ptr %3, align 4, !tbaa !5
  %48 = add nsw i32 %47, 1
  %49 = sext i32 %48 to i64
  %50 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %49) #2
  %51 = load i32, ptr %4, align 4, !tbaa !5
  %52 = sext i32 %51 to i64
  %53 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %52) #2
  %54 = load i32, ptr %53, align 4, !tbaa !5
  %55 = icmp eq i32 %54, 0
  br i1 %55, label %56, label %60

56:                                               ; preds = %46
  %57 = load i32, ptr %3, align 4, !tbaa !5
  %58 = add nsw i32 %57, 1
  %59 = load i32, ptr %4, align 4, !tbaa !5
  call void @_Z3dfsii(i32 noundef %58, i32 noundef %59)
  br label %60

60:                                               ; preds = %56, %46, %36, %32
  %61 = load i32, ptr %3, align 4, !tbaa !5
  %62 = sub nsw i32 %61, 1
  %63 = icmp sge i32 %62, 0
  br i1 %63, label %64, label %88

64:                                               ; preds = %60
  %65 = load i32, ptr %3, align 4, !tbaa !5
  %66 = sub nsw i32 %65, 1
  %67 = sext i32 %66 to i64
  %68 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %67) #2
  %69 = load i32, ptr %4, align 4, !tbaa !5
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %70) #2
  %72 = load i32, ptr %71, align 4, !tbaa !5
  %73 = icmp eq i32 %72, 0
  br i1 %73, label %74, label %88

74:                                               ; preds = %64
  %75 = load i32, ptr %3, align 4, !tbaa !5
  %76 = sub nsw i32 %75, 1
  %77 = sext i32 %76 to i64
  %78 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %77) #2
  %79 = load i32, ptr %4, align 4, !tbaa !5
  %80 = sext i32 %79 to i64
  %81 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %78, i64 noundef %80) #2
  %82 = load i32, ptr %81, align 4, !tbaa !5
  %83 = icmp eq i32 %82, 0
  br i1 %83, label %84, label %88

84:                                               ; preds = %74
  %85 = load i32, ptr %3, align 4, !tbaa !5
  %86 = sub nsw i32 %85, 1
  %87 = load i32, ptr %4, align 4, !tbaa !5
  call void @_Z3dfsii(i32 noundef %86, i32 noundef %87)
  br label %88

88:                                               ; preds = %84, %74, %64, %60
  %89 = load i32, ptr %4, align 4, !tbaa !5
  %90 = add nsw i32 %89, 1
  %91 = icmp slt i32 %90, 5
  br i1 %91, label %92, label %116

92:                                               ; preds = %88
  %93 = load i32, ptr %3, align 4, !tbaa !5
  %94 = sext i32 %93 to i64
  %95 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %94) #2
  %96 = load i32, ptr %4, align 4, !tbaa !5
  %97 = add nsw i32 %96, 1
  %98 = sext i32 %97 to i64
  %99 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %95, i64 noundef %98) #2
  %100 = load i32, ptr %99, align 4, !tbaa !5
  %101 = icmp eq i32 %100, 0
  br i1 %101, label %102, label %116

102:                                              ; preds = %92
  %103 = load i32, ptr %3, align 4, !tbaa !5
  %104 = sext i32 %103 to i64
  %105 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %104) #2
  %106 = load i32, ptr %4, align 4, !tbaa !5
  %107 = add nsw i32 %106, 1
  %108 = sext i32 %107 to i64
  %109 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %105, i64 noundef %108) #2
  %110 = load i32, ptr %109, align 4, !tbaa !5
  %111 = icmp eq i32 %110, 0
  br i1 %111, label %112, label %116

112:                                              ; preds = %102
  %113 = load i32, ptr %3, align 4, !tbaa !5
  %114 = load i32, ptr %4, align 4, !tbaa !5
  %115 = add nsw i32 %114, 1
  call void @_Z3dfsii(i32 noundef %113, i32 noundef %115)
  br label %116

116:                                              ; preds = %112, %102, %92, %88
  %117 = load i32, ptr %4, align 4, !tbaa !5
  %118 = sub nsw i32 %117, 1
  %119 = icmp sge i32 %118, 0
  br i1 %119, label %120, label %144

120:                                              ; preds = %116
  %121 = load i32, ptr %3, align 4, !tbaa !5
  %122 = sext i32 %121 to i64
  %123 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %122) #2
  %124 = load i32, ptr %4, align 4, !tbaa !5
  %125 = sub nsw i32 %124, 1
  %126 = sext i32 %125 to i64
  %127 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %123, i64 noundef %126) #2
  %128 = load i32, ptr %127, align 4, !tbaa !5
  %129 = icmp eq i32 %128, 0
  br i1 %129, label %130, label %144

130:                                              ; preds = %120
  %131 = load i32, ptr %3, align 4, !tbaa !5
  %132 = sext i32 %131 to i64
  %133 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %132) #2
  %134 = load i32, ptr %4, align 4, !tbaa !5
  %135 = sub nsw i32 %134, 1
  %136 = sext i32 %135 to i64
  %137 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %133, i64 noundef %136) #2
  %138 = load i32, ptr %137, align 4, !tbaa !5
  %139 = icmp eq i32 %138, 0
  br i1 %139, label %140, label %144

140:                                              ; preds = %130
  %141 = load i32, ptr %3, align 4, !tbaa !5
  %142 = load i32, ptr %4, align 4, !tbaa !5
  %143 = sub nsw i32 %142, 1
  call void @_Z3dfsii(i32 noundef %141, i32 noundef %143)
  br label %144

144:                                              ; preds = %140, %130, %120, %116
  br label %145

145:                                              ; preds = %144, %31
  br label %146

146:                                              ; preds = %145, %16, %13, %10, %7, %2
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vis = external dso_local global %"class.std::vector", align 8
@co = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %or.cond = icmp ugt i32 %0, 4
  %3 = zext nneg i32 %0 to i64
  %4 = icmp eq i32 %0, 4
  %5 = add nuw nsw i32 %0, 1
  %6 = icmp ult i32 %0, 4
  %7 = zext nneg i32 %5 to i64
  %8 = add nsw i32 %0, -1
  %.not = icmp eq i32 %0, 0
  br i1 %or.cond, label %.loopexit.split, label %tailrecurse

tailrecurse:                                      ; preds = %2, %66
  %.tr51 = phi i32 [ %60, %66 ], [ %1, %2 ]
  %9 = icmp ugt i32 %.tr51, 4
  %10 = load i32, ptr @co, align 4
  %11 = icmp ne i32 %10, 0
  %or.cond7 = select i1 %9, i1 true, i1 %11
  br i1 %or.cond7, label %.loopexit.split, label %12

12:                                               ; preds = %tailrecurse
  %13 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %3) #1
  %14 = zext nneg i32 %.tr51 to i64
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %14) #1
  store i32 1, ptr %15, align 4, !tbaa !5
  %16 = icmp eq i32 %.tr51, 4
  %or.cond9 = and i1 %4, %16
  br i1 %or.cond9, label %17, label %18

17:                                               ; preds = %12
  store i32 1, ptr @co, align 4, !tbaa !5
  br label %.loopexit.split

18:                                               ; preds = %12
  br i1 %6, label %19, label %.thread

19:                                               ; preds = %18
  %20 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %7) #1
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %14) #1
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = icmp eq i32 %22, 0
  br i1 %23, label %24, label %30

24:                                               ; preds = %19
  %25 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %7) #1
  %26 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %14) #1
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = icmp eq i32 %27, 0
  br i1 %28, label %29, label %30

29:                                               ; preds = %24
  tail call void @_Z3dfsii(i32 noundef %5, i32 noundef %.tr51)
  br label %30

30:                                               ; preds = %29, %24, %19
  br i1 %.not, label %43, label %.thread

.thread:                                          ; preds = %18, %30
  %31 = phi i32 [ %8, %30 ], [ 3, %18 ]
  %32 = zext nneg i32 %31 to i64
  %33 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %32) #1
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %14) #1
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = icmp eq i32 %35, 0
  br i1 %36, label %37, label %43

37:                                               ; preds = %.thread
  %38 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %32) #1
  %39 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %14) #1
  %40 = load i32, ptr %39, align 4, !tbaa !5
  %41 = icmp eq i32 %40, 0
  br i1 %41, label %42, label %43

42:                                               ; preds = %37
  tail call void @_Z3dfsii(i32 noundef %31, i32 noundef %.tr51)
  br label %43

43:                                               ; preds = %42, %37, %.thread, %30
  %44 = add nuw nsw i32 %.tr51, 1
  %45 = icmp ult i32 %.tr51, 4
  br i1 %45, label %46, label %.thread49

46:                                               ; preds = %43
  %47 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %3) #1
  %48 = zext nneg i32 %44 to i64
  %49 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %47, i64 noundef %48) #1
  %50 = load i32, ptr %49, align 4, !tbaa !5
  %51 = icmp eq i32 %50, 0
  br i1 %51, label %52, label %58

52:                                               ; preds = %46
  %53 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %3) #1
  %54 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %48) #1
  %55 = load i32, ptr %54, align 4, !tbaa !5
  %56 = icmp eq i32 %55, 0
  br i1 %56, label %57, label %58

57:                                               ; preds = %52
  tail call void @_Z3dfsii(i32 noundef %0, i32 noundef %44)
  br label %58

58:                                               ; preds = %57, %52, %46
  %59 = add nsw i32 %.tr51, -1
  %.not50 = icmp eq i32 %.tr51, 0
  br i1 %.not50, label %.loopexit.split, label %.thread49

.thread49:                                        ; preds = %43, %58
  %60 = phi i32 [ %59, %58 ], [ 3, %43 ]
  %61 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %3) #1
  %62 = zext nneg i32 %60 to i64
  %63 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %61, i64 noundef %62) #1
  %64 = load i32, ptr %63, align 4, !tbaa !5
  %65 = icmp eq i32 %64, 0
  br i1 %65, label %66, label %.loopexit.split

66:                                               ; preds = %.thread49
  %67 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %3) #1
  %68 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %67, i64 noundef %62) #1
  %69 = load i32, ptr %68, align 4, !tbaa !5
  %70 = icmp eq i32 %69, 0
  br i1 %70, label %tailrecurse, label %.loopexit.split

.loopexit.split:                                  ; preds = %tailrecurse, %58, %.thread49, %66, %2, %17
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopInstSimplifyPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass