; LLVM IR from indjev99/Evolving-Snakes :: sources/ctrRandom.ll (ZN9ctrRandom5thinkEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.decision = type { i8, i8, i8, i8, i8, i32 }
%struct.controller = type { ptr, [3 x i32], [3 x i8], [1 x i32], [1 x i8], [1 x i32], [1 x i8], i32, i32 }

; Function Attrs: mustprogress nounwind uwtable
define dso_local { i64, i32 } @_ZN9ctrRandom5thinkEv(ptr noundef nonnull align 8 dereferenceable(48) %0) unnamed_addr #0 align 2 {
  %2 = alloca %struct.decision, align 4
  %3 = alloca ptr, align 8
  %4 = alloca { i64, i32 }, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8
  %6 = call i32 @rand() #3
  %7 = srem i32 %6, 8
  %8 = icmp ne i32 %7, 0
  %9 = xor i1 %8, true
  %10 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 0
  %11 = zext i1 %9 to i8
  store i8 %11, ptr %10, align 4, !tbaa !9
  %12 = call i32 @rand() #3
  %13 = srem i32 %12, 8
  %14 = icmp ne i32 %13, 0
  %15 = xor i1 %14, true
  %16 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 1
  %17 = zext i1 %15 to i8
  store i8 %17, ptr %16, align 1, !tbaa !13
  %18 = call i32 @rand() #3
  %19 = srem i32 %18, 8
  %20 = icmp ne i32 %19, 0
  %21 = xor i1 %20, true
  %22 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 2
  %23 = zext i1 %21 to i8
  store i8 %23, ptr %22, align 2, !tbaa !14
  %24 = call i32 @rand() #3
  %25 = srem i32 %24, 8
  %26 = icmp ne i32 %25, 0
  %27 = xor i1 %26, true
  %28 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 3
  %29 = zext i1 %27 to i8
  store i8 %29, ptr %28, align 1, !tbaa !15
  %30 = getelementptr inbounds %struct.controller, ptr %5, i32 0, i32 7
  %31 = load i32, ptr %30, align 8, !tbaa !16
  %32 = icmp sgt i32 %31, 0
  br i1 %32, label %33, label %45

33:                                               ; preds = %1
  %34 = call i32 @rand() #3
  %35 = srem i32 %34, 150
  %36 = icmp ne i32 %35, 0
  %37 = xor i1 %36, true
  %38 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 4
  %39 = zext i1 %37 to i8
  store i8 %39, ptr %38, align 4, !tbaa !18
  %40 = call i32 @rand() #3
  %41 = getelementptr inbounds %struct.controller, ptr %5, i32 0, i32 7
  %42 = load i32, ptr %41, align 8, !tbaa !16
  %43 = srem i32 %40, %42
  %44 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 5
  store i32 %43, ptr %44, align 4, !tbaa !19
  br label %47

45:                                               ; preds = %1
  %46 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 4
  store i8 0, ptr %46, align 4, !tbaa !18
  br label %47

47:                                               ; preds = %45, %33
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %4, ptr align 4 %2, i64 12, i1 false)
  %48 = load { i64, i32 }, ptr %4, align 8
  ret { i64, i32 } %48
}

; Function Attrs: nounwind
declare i32 @rand() #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS8decision", !11, i64 0, !11, i64 1, !11, i64 2, !11, i64 3, !11, i64 4, !12, i64 8}
!11 = !{!"bool", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!10, !11, i64 1}
!14 = !{!10, !11, i64 2}
!15 = !{!10, !11, i64 3}
!16 = !{!17, !12, i64 40}
!17 = !{!"_ZTS10controller", !7, i64 8, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !12, i64 40, !12, i64 44}
!18 = !{!10, !11, i64 4}
!19 = !{!10, !12, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local { i64, i32 } @_ZN9ctrRandom5thinkEv(ptr nocapture noundef nonnull readonly align 8 dereferenceable(48) %0) unnamed_addr #0 align 2 {
  %2 = tail call i32 @rand() #2
  %3 = tail call i32 @rand() #2
  %4 = tail call i32 @rand() #2
  %5 = tail call i32 @rand() #2
  %6 = getelementptr inbounds i8, ptr %0, i64 40
  %7 = load i32, ptr %6, align 8, !tbaa !5
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %9, label %16

9:                                                ; preds = %1
  %10 = tail call i32 @rand() #2
  %11 = srem i32 %10, 150
  %.not7 = icmp eq i32 %11, 0
  %12 = tail call i32 @rand() #2
  %13 = load i32, ptr %6, align 8, !tbaa !5
  %14 = srem i32 %12, %13
  %15 = select i1 %.not7, i64 4294967296, i64 0
  br label %16

16:                                               ; preds = %1, %9
  %.sroa.5.0 = phi i64 [ %15, %9 ], [ 0, %1 ]
  %.sroa.7.sroa.1.0 = phi i32 [ %14, %9 ], [ undef, %1 ]
  %17 = and i32 %5, 7
  %.not6 = icmp eq i32 %17, 0
  %18 = and i32 %4, 7
  %.not5 = icmp eq i32 %18, 0
  %19 = and i32 %3, 7
  %.not4 = icmp eq i32 %19, 0
  %20 = and i32 %2, 7
  %.not = icmp eq i32 %20, 0
  %.sroa.4.0.insert.shift = select i1 %.not6, i64 16777216, i64 0
  %.sroa.3.0.insert.shift = select i1 %.not5, i64 65536, i64 0
  %.sroa.22.0.insert.shift = select i1 %.not4, i64 256, i64 0
  %.sroa.01.0.insert.ext = zext i1 %.not to i64
  %.sroa.4.0.insert.insert = or disjoint i64 %.sroa.22.0.insert.shift, %.sroa.01.0.insert.ext
  %.sroa.3.0.insert.insert = or disjoint i64 %.sroa.4.0.insert.insert, %.sroa.3.0.insert.shift
  %.sroa.22.0.insert.insert = or disjoint i64 %.sroa.3.0.insert.insert, %.sroa.4.0.insert.shift
  %.sroa.01.0.insert.insert = or disjoint i64 %.sroa.22.0.insert.insert, %.sroa.5.0
  %.fca.0.insert = insertvalue { i64, i32 } poison, i64 %.sroa.01.0.insert.insert, 0
  %.fca.1.insert = insertvalue { i64, i32 } %.fca.0.insert, i32 %.sroa.7.sroa.1.0, 1
  ret { i64, i32 } %.fca.1.insert
}

; Function Attrs: nounwind
declare i32 @rand() local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 40}
!6 = !{!"_ZTS10controller", !7, i64 8, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !9, i64 40, !9, i64 44}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!"int", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass