; LLVM IR from turi-code/SFrame :: oss_src/graphlab/scheduler/fifo_scheduler.ll (ZN8graphlab14fifo_scheduler8scheduleEmd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.graphlab::fifo_scheduler" = type { %"class.graphlab::ischeduler", %"class.graphlab::dense_bitset", %"class.std::vector", %"class.std::vector.6", %"class.std::vector.11", i64, i64, i64 }
%"class.graphlab::ischeduler" = type { ptr }
%"class.graphlab::dense_bitset" = type { ptr, i64, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.6" = type { %"struct.std::_Vector_base.7" }
%"struct.std::_Vector_base.7" = type { %"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl" }
%"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl" = type { %"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl_data" }
%"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8graphlab14fifo_scheduler8scheduleEmd(ptr noundef nonnull align 8 dereferenceable(128) %0, i64 noundef %1, double noundef %2) unnamed_addr #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca double, align 8
  %7 = alloca i64, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  store double %2, ptr %6, align 8, !tbaa !11
  %11 = load ptr, ptr %4, align 8
  %12 = load i64, ptr %5, align 8, !tbaa !9
  %13 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 7
  %14 = load i64, ptr %13, align 8, !tbaa !13
  %15 = icmp ult i64 %12, %14
  br i1 %15, label %16, label %73

16:                                               ; preds = %3
  %17 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 1
  %18 = load i64, ptr %5, align 8, !tbaa !9
  %19 = call noundef zeroext i1 @_ZN8graphlab12dense_bitset7set_bitEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %18)
  br i1 %19, label %73, label %20

20:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  store i64 0, ptr %7, align 8, !tbaa !9
  %21 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %22 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #5
  %23 = icmp ugt i64 %22, 1
  br i1 %23, label %24, label %63

24:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  %25 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %26 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %25) #5
  %27 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %28 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %27) #5
  %29 = mul i64 %26, %28
  %30 = sub i64 %29, 1
  %31 = trunc i64 %30 to i32
  %32 = call noundef i32 @_ZN8graphlab6random12fast_uniformIjEET_S2_S2_(i32 noundef 0, i32 noundef %31)
  store i32 %32, ptr %8, align 4, !tbaa !29
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  %33 = load i32, ptr %8, align 4, !tbaa !29
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %36 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %35) #5
  %37 = udiv i64 %34, %36
  %38 = trunc i64 %37 to i32
  store i32 %38, ptr %9, align 4, !tbaa !29
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %39 = load i32, ptr %8, align 4, !tbaa !29
  %40 = zext i32 %39 to i64
  %41 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %42 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %41) #5
  %43 = urem i64 %40, %42
  %44 = trunc i64 %43 to i32
  store i32 %44, ptr %10, align 4, !tbaa !29
  %45 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %46 = load i32, ptr %9, align 4, !tbaa !29
  %47 = zext i32 %46 to i64
  %48 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef %47) #5
  %49 = call noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80) %48) #5
  %50 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %51 = load i32, ptr %10, align 4, !tbaa !29
  %52 = zext i32 %51 to i64
  %53 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %50, i64 noundef %52) #5
  %54 = call noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80) %53) #5
  %55 = icmp ult i64 %49, %54
  br i1 %55, label %56, label %58

56:                                               ; preds = %24
  %57 = load i32, ptr %9, align 4, !tbaa !29
  br label %60

58:                                               ; preds = %24
  %59 = load i32, ptr %10, align 4, !tbaa !29
  br label %60

60:                                               ; preds = %58, %56
  %61 = phi i32 [ %57, %56 ], [ %59, %58 ]
  %62 = zext i32 %61 to i64
  store i64 %62, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  br label %63

63:                                               ; preds = %60, %20
  %64 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 3
  %65 = load i64, ptr %7, align 8, !tbaa !9
  %66 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %64, i64 noundef %65) #5
  call void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1) %66)
  %67 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 2
  %68 = load i64, ptr %7, align 8, !tbaa !9
  %69 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %67, i64 noundef %68) #5
  call void @_ZNSt5dequeImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(80) %69, ptr noundef nonnull align 8 dereferenceable(8) %5)
  %70 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %11, i32 0, i32 3
  %71 = load i64, ptr %7, align 8, !tbaa !9
  %72 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %70, i64 noundef %71) #5
  call void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1) %72)
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %73

73:                                               ; preds = %63, %16, %3
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN8graphlab12dense_bitset7set_bitEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN8graphlab6random12fast_uniformIjEET_S2_S2_(i32 noundef, i32 noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1)) #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5dequeImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 8 dereferenceable(8)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1)) #4 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"double", !7, i64 0}
!13 = !{!14, !10, i64 120}
!14 = !{!"_ZTSN8graphlab14fifo_schedulerE", !15, i64 0, !16, i64 8, !17, i64 32, !21, i64 56, !25, i64 80, !10, i64 104, !10, i64 112, !10, i64 120}
!15 = !{!"_ZTSN8graphlab10ischedulerE"}
!16 = !{!"_ZTSN8graphlab12dense_bitsetE", !6, i64 0, !10, i64 8, !10, i64 16}
!17 = !{!"_ZTSSt6vectorISt5dequeImSaImEESaIS2_EE", !18, i64 0}
!18 = !{!"_ZTSSt12_Vector_baseISt5dequeImSaImEESaIS2_EE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE12_Vector_implE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!21 = !{!"_ZTSSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTSSt6vectorImSaImEE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseImSaImEE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!29 = !{!30, !30, i64 0}
!30 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN8graphlab14fifo_scheduler8scheduleEmd(ptr noundef nonnull align 8 dereferenceable(128) %0, i64 noundef %1, double noundef %2) unnamed_addr #0 align 2 {
  %4 = alloca i64, align 8
  store i64 %1, ptr %4, align 8, !tbaa !5
  %5 = getelementptr inbounds i8, ptr %0, i64 120
  %6 = load i64, ptr %5, align 8, !tbaa !9
  %7 = icmp ugt i64 %6, %1
  br i1 %7, label %8, label %37

8:                                                ; preds = %3
  %9 = getelementptr inbounds i8, ptr %0, i64 8
  %10 = tail call noundef zeroext i1 @_ZN8graphlab12dense_bitset7set_bitEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %1)
  br i1 %10, label %37, label %11

11:                                               ; preds = %8
  %12 = getelementptr inbounds i8, ptr %0, i64 32
  %13 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %14 = icmp ugt i64 %13, 1
  br i1 %14, label %15, label %32

15:                                               ; preds = %11
  %16 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %17 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %18 = mul i64 %17, %16
  %19 = trunc i64 %18 to i32
  %20 = add i32 %19, -1
  %21 = tail call noundef i32 @_ZN8graphlab6random12fast_uniformIjEET_S2_S2_(i32 noundef 0, i32 noundef %20)
  %22 = zext i32 %21 to i64
  %23 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %24 = udiv i64 %22, %23
  %25 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #4
  %26 = urem i64 %22, %25
  %27 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %24) #4
  %28 = tail call noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80) %27) #4
  %29 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %26) #4
  %30 = tail call noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80) %29) #4
  %31 = icmp ult i64 %28, %30
  %.v = select i1 %31, i64 %24, i64 %26
  br label %32

32:                                               ; preds = %15, %11
  %.0 = phi i64 [ %.v, %15 ], [ 0, %11 ]
  %33 = getelementptr inbounds i8, ptr %0, i64 56
  %34 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %.0) #4
  tail call void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1) %34)
  %35 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %.0) #4
  call void @_ZNSt5dequeImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(80) %35, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %36 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %.0) #4
  call void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1) %36)
  br label %37

37:                                               ; preds = %32, %8, %3
  ret void
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN8graphlab12dense_bitset7set_bitEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_ZN8graphlab6random12fast_uniformIjEET_S2_S2_(i32 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt5dequeImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(80)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5dequeImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 120}
!10 = !{!"_ZTSN8graphlab14fifo_schedulerE", !11, i64 0, !12, i64 8, !14, i64 32, !18, i64 56, !22, i64 80, !6, i64 104, !6, i64 112, !6, i64 120}
!11 = !{!"_ZTSN8graphlab10ischedulerE"}
!12 = !{!"_ZTSN8graphlab12dense_bitsetE", !13, i64 0, !6, i64 8, !6, i64 16}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSSt6vectorISt5dequeImSaImEESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseISt5dequeImSaImEESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!18 = !{!"_ZTSSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!22 = !{!"_ZTSSt6vectorImSaImEE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseImSaImEE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass