; LLVM IR from indjev99/Evolving-Snakes :: sources/window_functions.ll (Z11keyCallbackP10GLFWwindowiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::queue" = type { %"class.std::deque" }
%"class.std::deque" = type { %"class.std::_Deque_base" }
%"class.std::_Deque_base" = type { %"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl" }
%"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl" = type { %"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl_data" }
%"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl_data" = type { ptr, i64, %"struct.std::_Deque_iterator", %"struct.std::_Deque_iterator" }
%"struct.std::_Deque_iterator" = type { ptr, ptr, ptr, ptr }

@presses = external dso_local global %"class.std::queue", align 8
@paused = external dso_local global i8, align 1
@new_neural_network = external dso_local global i8, align 1
@change_settings = external dso_local global i8, align 1
@draw_sim = external dso_local global i8, align 1
@draw_sim_mode = external dso_local global i32, align 4
@draw_neural_net = external dso_local global i8, align 1
@draw_neural_net_mode = external dso_local global i32, align 4
@draw_neural_net_neuron = external dso_local global i32, align 4
@draw_neural_net_neuron_increment = external dso_local global i8, align 1
@save_data = external dso_local global i8, align 1
@load_data = external dso_local global i8, align 1
@reset = external dso_local global i8, align 1
@control = external dso_local global i8, align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z11keyCallbackP10GLFWwindowiiii(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  store i32 %4, ptr %10, align 4, !tbaa !9
  %15 = load i32, ptr %7, align 4, !tbaa !9
  %16 = icmp eq i32 %15, 87
  br i1 %16, label %20, label %17

17:                                               ; preds = %5
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = icmp eq i32 %18, 265
  br i1 %19, label %20, label %24

20:                                               ; preds = %17, %5
  %21 = load i32, ptr %9, align 4, !tbaa !9
  %22 = icmp eq i32 %21, 1
  br i1 %22, label %23, label %24

23:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  store i32 0, ptr %11, align 4, !tbaa !9
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %11)
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  br label %24

24:                                               ; preds = %23, %20, %17
  %25 = load i32, ptr %7, align 4, !tbaa !9
  %26 = icmp eq i32 %25, 68
  br i1 %26, label %30, label %27

27:                                               ; preds = %24
  %28 = load i32, ptr %7, align 4, !tbaa !9
  %29 = icmp eq i32 %28, 262
  br i1 %29, label %30, label %34

30:                                               ; preds = %27, %24
  %31 = load i32, ptr %9, align 4, !tbaa !9
  %32 = icmp eq i32 %31, 1
  br i1 %32, label %33, label %34

33:                                               ; preds = %30
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 1, ptr %12, align 4, !tbaa !9
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %12)
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %34

34:                                               ; preds = %33, %30, %27
  %35 = load i32, ptr %7, align 4, !tbaa !9
  %36 = icmp eq i32 %35, 83
  br i1 %36, label %40, label %37

37:                                               ; preds = %34
  %38 = load i32, ptr %7, align 4, !tbaa !9
  %39 = icmp eq i32 %38, 264
  br i1 %39, label %40, label %44

40:                                               ; preds = %37, %34
  %41 = load i32, ptr %9, align 4, !tbaa !9
  %42 = icmp eq i32 %41, 1
  br i1 %42, label %43, label %44

43:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #2
  store i32 2, ptr %13, align 4, !tbaa !9
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %13)
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #2
  br label %44

44:                                               ; preds = %43, %40, %37
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = icmp eq i32 %45, 65
  br i1 %46, label %50, label %47

47:                                               ; preds = %44
  %48 = load i32, ptr %7, align 4, !tbaa !9
  %49 = icmp eq i32 %48, 263
  br i1 %49, label %50, label %54

50:                                               ; preds = %47, %44
  %51 = load i32, ptr %9, align 4, !tbaa !9
  %52 = icmp eq i32 %51, 1
  br i1 %52, label %53, label %54

53:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #2
  store i32 3, ptr %14, align 4, !tbaa !9
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %14)
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #2
  br label %54

54:                                               ; preds = %53, %50, %47
  %55 = load i32, ptr %7, align 4, !tbaa !9
  %56 = icmp eq i32 %55, 290
  br i1 %56, label %57, label %61

57:                                               ; preds = %54
  %58 = load i32, ptr %9, align 4, !tbaa !9
  %59 = icmp eq i32 %58, 1
  br i1 %59, label %60, label %61

60:                                               ; preds = %57
  store i8 1, ptr @new_neural_network, align 1, !tbaa !11
  br label %61

61:                                               ; preds = %60, %57, %54
  %62 = load i32, ptr %7, align 4, !tbaa !9
  %63 = icmp eq i32 %62, 291
  br i1 %63, label %64, label %72

64:                                               ; preds = %61
  %65 = load i32, ptr %9, align 4, !tbaa !9
  %66 = icmp eq i32 %65, 1
  br i1 %66, label %67, label %72

67:                                               ; preds = %64
  %68 = load i8, ptr @paused, align 1, !tbaa !11, !range !13, !noundef !14
  %69 = trunc i8 %68 to i1
  %70 = xor i1 %69, true
  %71 = zext i1 %70 to i8
  store i8 %71, ptr @paused, align 1, !tbaa !11
  br label %72

72:                                               ; preds = %67, %64, %61
  %73 = load i32, ptr %7, align 4, !tbaa !9
  %74 = icmp eq i32 %73, 292
  br i1 %74, label %75, label %83

75:                                               ; preds = %72
  %76 = load i32, ptr %9, align 4, !tbaa !9
  %77 = icmp eq i32 %76, 1
  br i1 %77, label %78, label %83

78:                                               ; preds = %75
  %79 = load i8, ptr @draw_sim, align 1, !tbaa !11, !range !13, !noundef !14
  %80 = trunc i8 %79 to i1
  %81 = xor i1 %80, true
  %82 = zext i1 %81 to i8
  store i8 %82, ptr @draw_sim, align 1, !tbaa !11
  br label %83

83:                                               ; preds = %78, %75, %72
  %84 = load i32, ptr %7, align 4, !tbaa !9
  %85 = icmp eq i32 %84, 293
  br i1 %85, label %86, label %93

86:                                               ; preds = %83
  %87 = load i32, ptr %9, align 4, !tbaa !9
  %88 = icmp eq i32 %87, 1
  br i1 %88, label %89, label %93

89:                                               ; preds = %86
  %90 = load i32, ptr @draw_sim_mode, align 4, !tbaa !9
  %91 = add nsw i32 %90, 1
  %92 = srem i32 %91, 4
  store i32 %92, ptr @draw_sim_mode, align 4, !tbaa !9
  br label %93

93:                                               ; preds = %89, %86, %83
  %94 = load i32, ptr %7, align 4, !tbaa !9
  %95 = icmp eq i32 %94, 294
  br i1 %95, label %96, label %104

96:                                               ; preds = %93
  %97 = load i32, ptr %9, align 4, !tbaa !9
  %98 = icmp eq i32 %97, 1
  br i1 %98, label %99, label %104

99:                                               ; preds = %96
  %100 = load i8, ptr @draw_neural_net, align 1, !tbaa !11, !range !13, !noundef !14
  %101 = trunc i8 %100 to i1
  %102 = xor i1 %101, true
  %103 = zext i1 %102 to i8
  store i8 %103, ptr @draw_neural_net, align 1, !tbaa !11
  br label %104

104:                                              ; preds = %99, %96, %93
  %105 = load i32, ptr %7, align 4, !tbaa !9
  %106 = icmp eq i32 %105, 295
  br i1 %106, label %107, label %114

107:                                              ; preds = %104
  %108 = load i32, ptr %9, align 4, !tbaa !9
  %109 = icmp eq i32 %108, 1
  br i1 %109, label %110, label %114

110:                                              ; preds = %107
  %111 = load i32, ptr @draw_neural_net_mode, align 4, !tbaa !9
  %112 = add nsw i32 %111, 1
  %113 = srem i32 %112, 4
  store i32 %113, ptr @draw_neural_net_mode, align 4, !tbaa !9
  br label %114

114:                                              ; preds = %110, %107, %104
  %115 = load i32, ptr %7, align 4, !tbaa !9
  %116 = icmp eq i32 %115, 296
  br i1 %116, label %117, label %123

117:                                              ; preds = %114
  %118 = load i32, ptr %9, align 4, !tbaa !9
  %119 = icmp eq i32 %118, 1
  br i1 %119, label %120, label %123

120:                                              ; preds = %117
  %121 = load i32, ptr @draw_neural_net_neuron, align 4, !tbaa !9
  %122 = add nsw i32 %121, 1
  store i32 %122, ptr @draw_neural_net_neuron, align 4, !tbaa !9
  store i8 1, ptr @draw_neural_net_neuron_increment, align 1, !tbaa !11
  br label %123

123:                                              ; preds = %120, %117, %114
  %124 = load i32, ptr %7, align 4, !tbaa !9
  %125 = icmp eq i32 %124, 297
  br i1 %125, label %126, label %130

126:                                              ; preds = %123
  %127 = load i32, ptr %9, align 4, !tbaa !9
  %128 = icmp eq i32 %127, 1
  br i1 %128, label %129, label %130

129:                                              ; preds = %126
  store i8 1, ptr @change_settings, align 1, !tbaa !11
  br label %130

130:                                              ; preds = %129, %126, %123
  %131 = load i32, ptr %7, align 4, !tbaa !9
  %132 = icmp eq i32 %131, 298
  br i1 %132, label %133, label %137

133:                                              ; preds = %130
  %134 = load i32, ptr %9, align 4, !tbaa !9
  %135 = icmp eq i32 %134, 1
  br i1 %135, label %136, label %137

136:                                              ; preds = %133
  store i8 1, ptr @save_data, align 1, !tbaa !11
  br label %137

137:                                              ; preds = %136, %133, %130
  %138 = load i32, ptr %7, align 4, !tbaa !9
  %139 = icmp eq i32 %138, 299
  br i1 %139, label %140, label %144

140:                                              ; preds = %137
  %141 = load i32, ptr %9, align 4, !tbaa !9
  %142 = icmp eq i32 %141, 1
  br i1 %142, label %143, label %144

143:                                              ; preds = %140
  store i8 1, ptr @load_data, align 1, !tbaa !11
  br label %144

144:                                              ; preds = %143, %140, %137
  %145 = load i32, ptr %7, align 4, !tbaa !9
  %146 = icmp eq i32 %145, 300
  br i1 %146, label %147, label %151

147:                                              ; preds = %144
  %148 = load i32, ptr %9, align 4, !tbaa !9
  %149 = icmp eq i32 %148, 1
  br i1 %149, label %150, label %151

150:                                              ; preds = %147
  store i8 1, ptr @reset, align 1, !tbaa !11
  br label %151

151:                                              ; preds = %150, %147, %144
  %152 = load i32, ptr %7, align 4, !tbaa !9
  %153 = icmp eq i32 %152, 301
  br i1 %153, label %154, label %162

154:                                              ; preds = %151
  %155 = load i32, ptr %9, align 4, !tbaa !9
  %156 = icmp eq i32 %155, 1
  br i1 %156, label %157, label %162

157:                                              ; preds = %154
  %158 = load i8, ptr @control, align 1, !tbaa !11, !range !13, !noundef !14
  %159 = trunc i8 %158 to i1
  %160 = xor i1 %159, true
  %161 = zext i1 %160 to i8
  store i8 %161, ptr @control, align 1, !tbaa !11
  br label %162

162:                                              ; preds = %157, %154, %151
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::queue" = type { %"class.std::deque" }
%"class.std::deque" = type { %"class.std::_Deque_base" }
%"class.std::_Deque_base" = type { %"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl" }
%"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl" = type { %"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl_data" }
%"struct.std::_Deque_base<int, std::allocator<int>>::_Deque_impl_data" = type { ptr, i64, %"struct.std::_Deque_iterator", %"struct.std::_Deque_iterator" }
%"struct.std::_Deque_iterator" = type { ptr, ptr, ptr, ptr }

@presses = external dso_local global %"class.std::queue", align 8
@paused = external dso_local local_unnamed_addr global i8, align 1
@new_neural_network = external dso_local local_unnamed_addr global i8, align 1
@change_settings = external dso_local local_unnamed_addr global i8, align 1
@draw_sim = external dso_local local_unnamed_addr global i8, align 1
@draw_sim_mode = external dso_local local_unnamed_addr global i32, align 4
@draw_neural_net = external dso_local local_unnamed_addr global i8, align 1
@draw_neural_net_mode = external dso_local local_unnamed_addr global i32, align 4
@draw_neural_net_neuron = external dso_local local_unnamed_addr global i32, align 4
@draw_neural_net_neuron_increment = external dso_local local_unnamed_addr global i8, align 1
@save_data = external dso_local local_unnamed_addr global i8, align 1
@load_data = external dso_local local_unnamed_addr global i8, align 1
@reset = external dso_local local_unnamed_addr global i8, align 1
@control = external dso_local local_unnamed_addr global i8, align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z11keyCallbackP10GLFWwindowiiii(ptr nocapture noundef readnone %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = icmp eq i32 %1, 87
  %11 = icmp eq i32 %1, 265
  %or.cond = or i1 %10, %11
  %12 = icmp eq i32 %3, 1
  %or.cond3 = and i1 %or.cond, %12
  br i1 %or.cond3, label %13, label %14

13:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #2
  store i32 0, ptr %6, align 4, !tbaa !5
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %6)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #2
  br label %14

14:                                               ; preds = %5, %13
  %15 = icmp eq i32 %1, 68
  %16 = icmp eq i32 %1, 262
  %or.cond5 = or i1 %15, %16
  %or.cond7 = and i1 %or.cond5, %12
  br i1 %or.cond7, label %17, label %18

17:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #2
  store i32 1, ptr %7, align 4, !tbaa !5
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %7)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #2
  br label %18

18:                                               ; preds = %14, %17
  %19 = icmp eq i32 %1, 83
  %20 = icmp eq i32 %1, 264
  %or.cond9 = or i1 %19, %20
  %or.cond11 = and i1 %or.cond9, %12
  br i1 %or.cond11, label %21, label %22

21:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %8) #2
  store i32 2, ptr %8, align 4, !tbaa !5
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %8)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %8) #2
  br label %22

22:                                               ; preds = %18, %21
  %23 = icmp eq i32 %1, 65
  %24 = icmp eq i32 %1, 263
  %or.cond13 = or i1 %23, %24
  %or.cond15 = and i1 %or.cond13, %12
  br i1 %or.cond15, label %.thread, label %25

.thread:                                          ; preds = %22
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %9) #2
  store i32 3, ptr %9, align 4, !tbaa !5
  call void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80) @presses, ptr noundef nonnull align 4 dereferenceable(4) %9)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %9) #2
  br label %.thread106

25:                                               ; preds = %22
  %26 = icmp eq i32 %1, 290
  %or.cond17 = and i1 %26, %12
  br i1 %or.cond17, label %27, label %28

27:                                               ; preds = %25
  store i8 1, ptr @new_neural_network, align 1, !tbaa !9
  br label %.thread106

28:                                               ; preds = %25
  %29 = icmp eq i32 %1, 291
  %or.cond19 = and i1 %29, %12
  br i1 %or.cond19, label %30, label %33

30:                                               ; preds = %28
  %31 = load i8, ptr @paused, align 1, !tbaa !9, !range !11, !noundef !12
  %32 = xor i8 %31, 1
  store i8 %32, ptr @paused, align 1, !tbaa !9
  br label %.thread106

33:                                               ; preds = %28
  %34 = icmp eq i32 %1, 292
  %or.cond21 = and i1 %34, %12
  br i1 %or.cond21, label %35, label %38

35:                                               ; preds = %33
  %36 = load i8, ptr @draw_sim, align 1, !tbaa !9, !range !11, !noundef !12
  %37 = xor i8 %36, 1
  store i8 %37, ptr @draw_sim, align 1, !tbaa !9
  br label %.thread106

38:                                               ; preds = %33
  %39 = icmp eq i32 %1, 293
  %or.cond23 = and i1 %39, %12
  br i1 %or.cond23, label %40, label %44

40:                                               ; preds = %38
  %41 = load i32, ptr @draw_sim_mode, align 4, !tbaa !5
  %42 = add nsw i32 %41, 1
  %43 = srem i32 %42, 4
  store i32 %43, ptr @draw_sim_mode, align 4, !tbaa !5
  br label %.thread106

44:                                               ; preds = %38
  %45 = icmp eq i32 %1, 294
  %or.cond25 = and i1 %45, %12
  br i1 %or.cond25, label %46, label %49

46:                                               ; preds = %44
  %47 = load i8, ptr @draw_neural_net, align 1, !tbaa !9, !range !11, !noundef !12
  %48 = xor i8 %47, 1
  store i8 %48, ptr @draw_neural_net, align 1, !tbaa !9
  br label %.thread106

49:                                               ; preds = %44
  %50 = icmp eq i32 %1, 295
  %or.cond27 = and i1 %50, %12
  br i1 %or.cond27, label %51, label %55

51:                                               ; preds = %49
  %52 = load i32, ptr @draw_neural_net_mode, align 4, !tbaa !5
  %53 = add nsw i32 %52, 1
  %54 = srem i32 %53, 4
  store i32 %54, ptr @draw_neural_net_mode, align 4, !tbaa !5
  br label %.thread106

55:                                               ; preds = %49
  %56 = icmp eq i32 %1, 296
  %or.cond29 = and i1 %56, %12
  br i1 %or.cond29, label %57, label %60

57:                                               ; preds = %55
  %58 = load i32, ptr @draw_neural_net_neuron, align 4, !tbaa !5
  %59 = add nsw i32 %58, 1
  store i32 %59, ptr @draw_neural_net_neuron, align 4, !tbaa !5
  store i8 1, ptr @draw_neural_net_neuron_increment, align 1, !tbaa !9
  br label %.thread106

60:                                               ; preds = %55
  %61 = icmp eq i32 %1, 297
  %or.cond31 = and i1 %61, %12
  br i1 %or.cond31, label %62, label %63

62:                                               ; preds = %60
  store i8 1, ptr @change_settings, align 1, !tbaa !9
  br label %.thread106

63:                                               ; preds = %60
  %64 = icmp eq i32 %1, 298
  %or.cond33 = and i1 %64, %12
  br i1 %or.cond33, label %65, label %66

65:                                               ; preds = %63
  store i8 1, ptr @save_data, align 1, !tbaa !9
  br label %.thread106

66:                                               ; preds = %63
  %67 = icmp eq i32 %1, 299
  %or.cond35 = and i1 %67, %12
  br i1 %or.cond35, label %68, label %69

68:                                               ; preds = %66
  store i8 1, ptr @load_data, align 1, !tbaa !9
  br label %.thread106

69:                                               ; preds = %66
  %70 = icmp eq i32 %1, 300
  %or.cond37 = and i1 %70, %12
  br i1 %or.cond37, label %71, label %72

71:                                               ; preds = %69
  store i8 1, ptr @reset, align 1, !tbaa !9
  br label %.thread106

72:                                               ; preds = %69
  %73 = icmp eq i32 %1, 301
  %or.cond39 = and i1 %73, %12
  br i1 %or.cond39, label %74, label %.thread106

74:                                               ; preds = %72
  %75 = load i8, ptr @control, align 1, !tbaa !9, !range !11, !noundef !12
  %76 = xor i8 %75, 1
  store i8 %76, ptr @control, align 1, !tbaa !9
  br label %.thread106

.thread106:                                       ; preds = %27, %.thread, %30, %35, %40, %46, %51, %57, %62, %65, %68, %71, %74, %72
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt5queueIiSt5dequeIiSaIiEEE4pushEOi(ptr noundef nonnull align 8 dereferenceable(80), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass