; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/devices (mfrc522)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@MFRC522_PCD_DumpVersionToSerial.str = external hidden constant [23 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.20 = external hidden constant [11 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.21 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.22 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.23 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.24 = external hidden constant [13 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.25 = external hidden constant [67 x i8], align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local void @MFRC522_PCD_DumpVersionToSerial() #1 {
  %1 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr %1) #3
  %2 = call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 110)
  store i8 %2, ptr %1, align 1, !tbaa !5
  br label %3

3:                                                ; preds = %0
  %4 = load i8, ptr %1, align 1, !tbaa !5
  %5 = zext i8 %4 to i32
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str, i32 noundef %5)
  br label %6

6:                                                ; preds = %3
  br label %7

7:                                                ; preds = %6
  %8 = load i8, ptr %1, align 1, !tbaa !5
  %9 = zext i8 %8 to i32
  switch i32 %9, label %26 [
    i32 136, label %10
    i32 144, label %14
    i32 145, label %18
    i32 146, label %22
  ]

10:                                               ; preds = %7
  br label %11

11:                                               ; preds = %10
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.20)
  br label %12

12:                                               ; preds = %11
  br label %13

13:                                               ; preds = %12
  br label %30

14:                                               ; preds = %7
  br label %15

15:                                               ; preds = %14
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.21)
  br label %16

16:                                               ; preds = %15
  br label %17

17:                                               ; preds = %16
  br label %30

18:                                               ; preds = %7
  br label %19

19:                                               ; preds = %18
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.22)
  br label %20

20:                                               ; preds = %19
  br label %21

21:                                               ; preds = %20
  br label %30

22:                                               ; preds = %7
  br label %23

23:                                               ; preds = %22
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.23)
  br label %24

24:                                               ; preds = %23
  br label %25

25:                                               ; preds = %24
  br label %30

26:                                               ; preds = %7
  br label %27

27:                                               ; preds = %26
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.24)
  br label %28

28:                                               ; preds = %27
  br label %29

29:                                               ; preds = %28
  br label %30

30:                                               ; preds = %29, %25, %21, %17, %13
  %31 = load i8, ptr %1, align 1, !tbaa !5
  %32 = zext i8 %31 to i32
  %33 = icmp eq i32 %32, 0
  br i1 %33, label %38, label %34

34:                                               ; preds = %30
  %35 = load i8, ptr %1, align 1, !tbaa !5
  %36 = zext i8 %35 to i32
  %37 = icmp eq i32 %36, 255
  br i1 %37, label %38, label %42

38:                                               ; preds = %34, %30
  br label %39

39:                                               ; preds = %38
  call void (ptr, ...) @dhdebug_ram(ptr noundef @MFRC522_PCD_DumpVersionToSerial.str.25)
  br label %40

40:                                               ; preds = %39
  br label %41

41:                                               ; preds = %40
  br label %42

42:                                               ; preds = %41, %34
  call void @llvm.lifetime.end.p0(i64 1, ptr %1) #3
  ret void
}

declare void @dhdebug_ram(ptr noundef, ...) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@MFRC522_PCD_DumpVersionToSerial.str = external hidden constant [23 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.20 = external hidden constant [11 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.21 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.22 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.23 = external hidden constant [8 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.24 = external hidden constant [13 x i8], align 4
@MFRC522_PCD_DumpVersionToSerial.str.25 = external hidden constant [67 x i8], align 4

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @MFRC522_PCD_DumpVersionToSerial() local_unnamed_addr #0 {
  %1 = tail call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 110)
  %2 = zext i8 %1 to i32
  tail call void (ptr, ...) @dhdebug_ram(ptr noundef nonnull @MFRC522_PCD_DumpVersionToSerial.str, i32 noundef %2) #2
  switch i8 %1, label %6 [
    i8 -120, label %.thread.sink.split
    i8 -112, label %3
    i8 -111, label %4
    i8 -110, label %5
  ]

3:                                                ; preds = %0
  br label %.thread.sink.split

4:                                                ; preds = %0
  br label %.thread.sink.split

5:                                                ; preds = %0
  br label %.thread.sink.split

6:                                                ; preds = %0
  tail call void (ptr, ...) @dhdebug_ram(ptr noundef nonnull @MFRC522_PCD_DumpVersionToSerial.str.24) #2
  %7 = add i8 %1, 1
  %or.cond = icmp ult i8 %7, 2
  br i1 %or.cond, label %.thread.sink.split, label %.thread

.thread.sink.split:                               ; preds = %6, %0, %5, %4, %3
  %MFRC522_PCD_DumpVersionToSerial.str.20.sink = phi ptr [ @MFRC522_PCD_DumpVersionToSerial.str.21, %3 ], [ @MFRC522_PCD_DumpVersionToSerial.str.22, %4 ], [ @MFRC522_PCD_DumpVersionToSerial.str.23, %5 ], [ @MFRC522_PCD_DumpVersionToSerial.str.20, %0 ], [ @MFRC522_PCD_DumpVersionToSerial.str.25, %6 ]
  tail call void (ptr, ...) @dhdebug_ram(ptr noundef nonnull %MFRC522_PCD_DumpVersionToSerial.str.20.sink) #2
  br label %.thread

.thread:                                          ; preds = %.thread.sink.split, %6
  ret void
}

declare void @dhdebug_ram(ptr noundef, ...) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,SROAPass,SimplifyCFGPass,TailCallElimPass