; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/URI/1121/main.ll (Z16change_directionRKcRc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z16change_directionRKcRc(ptr noundef nonnull align 1 dereferenceable(1) %0, ptr noundef nonnull align 1 dereferenceable(1) %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = load ptr, ptr %3, align 8, !tbaa !5
  %6 = load i8, ptr %5, align 1, !tbaa !9
  %7 = sext i8 %6 to i32
  %8 = icmp eq i32 %7, 69
  br i1 %8, label %9, label %35

9:                                                ; preds = %2
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = load i8, ptr %10, align 1, !tbaa !9
  %12 = sext i8 %11 to i32
  %13 = icmp eq i32 %12, 78
  br i1 %13, label %14, label %16

14:                                               ; preds = %9
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 79, ptr %15, align 1, !tbaa !9
  br label %34

16:                                               ; preds = %9
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = load i8, ptr %17, align 1, !tbaa !9
  %19 = sext i8 %18 to i32
  %20 = icmp eq i32 %19, 83
  br i1 %20, label %21, label %23

21:                                               ; preds = %16
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 76, ptr %22, align 1, !tbaa !9
  br label %33

23:                                               ; preds = %16
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = load i8, ptr %24, align 1, !tbaa !9
  %26 = sext i8 %25 to i32
  %27 = icmp eq i32 %26, 76
  br i1 %27, label %28, label %30

28:                                               ; preds = %23
  %29 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 78, ptr %29, align 1, !tbaa !9
  br label %32

30:                                               ; preds = %23
  %31 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 83, ptr %31, align 1, !tbaa !9
  br label %32

32:                                               ; preds = %30, %28
  br label %33

33:                                               ; preds = %32, %21
  br label %34

34:                                               ; preds = %33, %14
  br label %61

35:                                               ; preds = %2
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  %37 = load i8, ptr %36, align 1, !tbaa !9
  %38 = sext i8 %37 to i32
  %39 = icmp eq i32 %38, 78
  br i1 %39, label %40, label %42

40:                                               ; preds = %35
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 76, ptr %41, align 1, !tbaa !9
  br label %60

42:                                               ; preds = %35
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  %44 = load i8, ptr %43, align 1, !tbaa !9
  %45 = sext i8 %44 to i32
  %46 = icmp eq i32 %45, 83
  br i1 %46, label %47, label %49

47:                                               ; preds = %42
  %48 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 79, ptr %48, align 1, !tbaa !9
  br label %59

49:                                               ; preds = %42
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = load i8, ptr %50, align 1, !tbaa !9
  %52 = sext i8 %51 to i32
  %53 = icmp eq i32 %52, 76
  br i1 %53, label %54, label %56

54:                                               ; preds = %49
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 83, ptr %55, align 1, !tbaa !9
  br label %58

56:                                               ; preds = %49
  %57 = load ptr, ptr %4, align 8, !tbaa !5
  store i8 78, ptr %57, align 1, !tbaa !9
  br label %58

58:                                               ; preds = %56, %54
  br label %59

59:                                               ; preds = %58, %47
  br label %60

60:                                               ; preds = %59, %40
  br label %61

61:                                               ; preds = %60, %34
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
define dso_local void @_Z16change_directionRKcRc(ptr nocapture noundef nonnull readonly align 1 dereferenceable(1) %0, ptr nocapture noundef nonnull align 1 dereferenceable(1) %1) local_unnamed_addr #0 {
  %3 = load i8, ptr %0, align 1, !tbaa !5
  %4 = icmp eq i8 %3, 69
  %5 = load i8, ptr %1, align 1, !tbaa !5
  %switch.tableidx = add i8 %5, -76
  %6 = icmp ult i8 %switch.tableidx, 8
  br i1 %4, label %7, label %8

7:                                                ; preds = %2
  br i1 %6, label %switch.lookup, label %11

8:                                                ; preds = %2
  br i1 %6, label %switch.lookup16, label %11

switch.lookup:                                    ; preds = %7
  %9 = shl nuw nsw i8 %switch.tableidx, 3
  %switch.shiftamt = zext nneg i8 %9 to i64
  %switch.downshift = lshr i64 5499831187294606158, %switch.shiftamt
  %switch.masked = trunc i64 %switch.downshift to i8
  br label %11

switch.lookup16:                                  ; preds = %8
  %10 = shl nuw nsw i8 %switch.tableidx, 3
  %switch.shiftamt19 = zext nneg i8 %10 to i64
  %switch.downshift20 = lshr i64 5714591075407777363, %switch.shiftamt19
  %switch.masked21 = trunc i64 %switch.downshift20 to i8
  br label %11

11:                                               ; preds = %8, %switch.lookup16, %7, %switch.lookup
  %.sink = phi i8 [ %switch.masked, %switch.lookup ], [ 83, %7 ], [ %switch.masked21, %switch.lookup16 ], [ 78, %8 ]
  store i8 %.sink, ptr %1, align 1, !tbaa !5
  ret void
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass