; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/URI/2465/main.ll (Z3dfsii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vis = external dso_local global %"class.std::vector", align 8
@cont = external dso_local global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %5 = load i32, ptr %3, align 4, !tbaa !5
  %6 = icmp sge i32 %5, 0
  br i1 %6, label %7, label %173

7:                                                ; preds = %2
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #2
  %10 = trunc i64 %9 to i32
  %11 = icmp slt i32 %8, %10
  br i1 %11, label %12, label %173

12:                                               ; preds = %7
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = icmp sge i32 %13, 0
  br i1 %14, label %15, label %173

15:                                               ; preds = %12
  %16 = load i32, ptr %4, align 4, !tbaa !5
  %17 = call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #2
  %18 = trunc i64 %17 to i32
  %19 = icmp slt i32 %16, %18
  br i1 %19, label %20, label %173

20:                                               ; preds = %15
  %21 = load i32, ptr %3, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %22) #2
  %24 = load i32, ptr %4, align 4, !tbaa !5
  %25 = sext i32 %24 to i64
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %25) #2
  store i32 1, ptr %26, align 4, !tbaa !5
  %27 = load i32, ptr @cont, align 4, !tbaa !5
  %28 = add nsw i32 %27, 1
  store i32 %28, ptr @cont, align 4, !tbaa !5
  %29 = load i32, ptr %3, align 4, !tbaa !5
  %30 = sub nsw i32 %29, 1
  %31 = icmp sge i32 %30, 0
  br i1 %31, label %32, label %63

32:                                               ; preds = %20
  %33 = load i32, ptr %3, align 4, !tbaa !5
  %34 = sub nsw i32 %33, 1
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %35) #2
  %37 = load i32, ptr %4, align 4, !tbaa !5
  %38 = sext i32 %37 to i64
  %39 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %38) #2
  %40 = load i32, ptr %39, align 4, !tbaa !5
  %41 = load i32, ptr %3, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %42) #2
  %44 = load i32, ptr %4, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %45) #2
  %47 = load i32, ptr %46, align 4, !tbaa !5
  %48 = icmp sge i32 %40, %47
  br i1 %48, label %49, label %63

49:                                               ; preds = %32
  %50 = load i32, ptr %3, align 4, !tbaa !5
  %51 = sub nsw i32 %50, 1
  %52 = sext i32 %51 to i64
  %53 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %52) #2
  %54 = load i32, ptr %4, align 4, !tbaa !5
  %55 = sext i32 %54 to i64
  %56 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %55) #2
  %57 = load i32, ptr %56, align 4, !tbaa !5
  %58 = icmp ne i32 %57, 0
  br i1 %58, label %63, label %59

59:                                               ; preds = %49
  %60 = load i32, ptr %3, align 4, !tbaa !5
  %61 = sub nsw i32 %60, 1
  %62 = load i32, ptr %4, align 4, !tbaa !5
  call void @_Z3dfsii(i32 noundef %61, i32 noundef %62)
  br label %63

63:                                               ; preds = %59, %49, %32, %20
  %64 = load i32, ptr %3, align 4, !tbaa !5
  %65 = add nsw i32 %64, 1
  %66 = call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #2
  %67 = trunc i64 %66 to i32
  %68 = icmp slt i32 %65, %67
  br i1 %68, label %69, label %100

69:                                               ; preds = %63
  %70 = load i32, ptr %3, align 4, !tbaa !5
  %71 = add nsw i32 %70, 1
  %72 = sext i32 %71 to i64
  %73 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %72) #2
  %74 = load i32, ptr %4, align 4, !tbaa !5
  %75 = sext i32 %74 to i64
  %76 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %75) #2
  %77 = load i32, ptr %76, align 4, !tbaa !5
  %78 = load i32, ptr %3, align 4, !tbaa !5
  %79 = sext i32 %78 to i64
  %80 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %79) #2
  %81 = load i32, ptr %4, align 4, !tbaa !5
  %82 = sext i32 %81 to i64
  %83 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %80, i64 noundef %82) #2
  %84 = load i32, ptr %83, align 4, !tbaa !5
  %85 = icmp sge i32 %77, %84
  br i1 %85, label %86, label %100

86:                                               ; preds = %69
  %87 = load i32, ptr %3, align 4, !tbaa !5
  %88 = add nsw i32 %87, 1
  %89 = sext i32 %88 to i64
  %90 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %89) #2
  %91 = load i32, ptr %4, align 4, !tbaa !5
  %92 = sext i32 %91 to i64
  %93 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %90, i64 noundef %92) #2
  %94 = load i32, ptr %93, align 4, !tbaa !5
  %95 = icmp ne i32 %94, 0
  br i1 %95, label %100, label %96

96:                                               ; preds = %86
  %97 = load i32, ptr %3, align 4, !tbaa !5
  %98 = add nsw i32 %97, 1
  %99 = load i32, ptr %4, align 4, !tbaa !5
  call void @_Z3dfsii(i32 noundef %98, i32 noundef %99)
  br label %100

100:                                              ; preds = %96, %86, %69, %63
  %101 = load i32, ptr %4, align 4, !tbaa !5
  %102 = sub nsw i32 %101, 1
  %103 = icmp sge i32 %102, 0
  br i1 %103, label %104, label %135

104:                                              ; preds = %100
  %105 = load i32, ptr %3, align 4, !tbaa !5
  %106 = sext i32 %105 to i64
  %107 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %106) #2
  %108 = load i32, ptr %4, align 4, !tbaa !5
  %109 = sub nsw i32 %108, 1
  %110 = sext i32 %109 to i64
  %111 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %107, i64 noundef %110) #2
  %112 = load i32, ptr %111, align 4, !tbaa !5
  %113 = load i32, ptr %3, align 4, !tbaa !5
  %114 = sext i32 %113 to i64
  %115 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %114) #2
  %116 = load i32, ptr %4, align 4, !tbaa !5
  %117 = sext i32 %116 to i64
  %118 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %115, i64 noundef %117) #2
  %119 = load i32, ptr %118, align 4, !tbaa !5
  %120 = icmp sge i32 %112, %119
  br i1 %120, label %121, label %135

121:                                              ; preds = %104
  %122 = load i32, ptr %3, align 4, !tbaa !5
  %123 = sext i32 %122 to i64
  %124 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %123) #2
  %125 = load i32, ptr %4, align 4, !tbaa !5
  %126 = sub nsw i32 %125, 1
  %127 = sext i32 %126 to i64
  %128 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %124, i64 noundef %127) #2
  %129 = load i32, ptr %128, align 4, !tbaa !5
  %130 = icmp ne i32 %129, 0
  br i1 %130, label %135, label %131

131:                                              ; preds = %121
  %132 = load i32, ptr %3, align 4, !tbaa !5
  %133 = load i32, ptr %4, align 4, !tbaa !5
  %134 = sub nsw i32 %133, 1
  call void @_Z3dfsii(i32 noundef %132, i32 noundef %134)
  br label %135

135:                                              ; preds = %131, %121, %104, %100
  %136 = load i32, ptr %4, align 4, !tbaa !5
  %137 = add nsw i32 %136, 1
  %138 = call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #2
  %139 = trunc i64 %138 to i32
  %140 = icmp slt i32 %137, %139
  br i1 %140, label %141, label %172

141:                                              ; preds = %135
  %142 = load i32, ptr %3, align 4, !tbaa !5
  %143 = sext i32 %142 to i64
  %144 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %143) #2
  %145 = load i32, ptr %4, align 4, !tbaa !5
  %146 = add nsw i32 %145, 1
  %147 = sext i32 %146 to i64
  %148 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %144, i64 noundef %147) #2
  %149 = load i32, ptr %148, align 4, !tbaa !5
  %150 = load i32, ptr %3, align 4, !tbaa !5
  %151 = sext i32 %150 to i64
  %152 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %151) #2
  %153 = load i32, ptr %4, align 4, !tbaa !5
  %154 = sext i32 %153 to i64
  %155 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %152, i64 noundef %154) #2
  %156 = load i32, ptr %155, align 4, !tbaa !5
  %157 = icmp sge i32 %149, %156
  br i1 %157, label %158, label %172

158:                                              ; preds = %141
  %159 = load i32, ptr %3, align 4, !tbaa !5
  %160 = sext i32 %159 to i64
  %161 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %160) #2
  %162 = load i32, ptr %4, align 4, !tbaa !5
  %163 = add nsw i32 %162, 1
  %164 = sext i32 %163 to i64
  %165 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %161, i64 noundef %164) #2
  %166 = load i32, ptr %165, align 4, !tbaa !5
  %167 = icmp ne i32 %166, 0
  br i1 %167, label %172, label %168

168:                                              ; preds = %158
  %169 = load i32, ptr %3, align 4, !tbaa !5
  %170 = load i32, ptr %4, align 4, !tbaa !5
  %171 = add nsw i32 %170, 1
  call void @_Z3dfsii(i32 noundef %169, i32 noundef %171)
  br label %172

172:                                              ; preds = %168, %158, %141, %135
  br label %173

173:                                              ; preds = %172, %15, %12, %7, %2
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vis = external dso_local global %"class.std::vector", align 8
@cont = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = icmp sgt i32 %0, -1
  %4 = zext nneg i32 %0 to i64
  %5 = add nsw i32 %0, -1
  %.not = icmp eq i32 %0, 0
  %6 = zext nneg i32 %5 to i64
  %7 = add nuw nsw i32 %0, 1
  %8 = zext nneg i32 %7 to i64
  br i1 %3, label %tailrecurse.preheader, label %.split58

tailrecurse.preheader:                            ; preds = %2
  %9 = zext i32 %1 to i64
  %10 = icmp sgt i32 %1, -1
  br label %tailrecurse

tailrecurse:                                      ; preds = %tailrecurse.preheader, %79
  %indvars.iv = phi i64 [ %9, %tailrecurse.preheader ], [ %indvars.iv.next, %79 ]
  %11 = tail call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #1
  %12 = trunc i64 %11 to i32
  %13 = icmp sgt i32 %12, %0
  %or.cond = and i1 %10, %13
  br i1 %or.cond, label %14, label %.split58

14:                                               ; preds = %tailrecurse
  %15 = tail call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #1
  %16 = trunc i64 %15 to i32
  %17 = trunc nuw i64 %indvars.iv to i32
  %18 = icmp slt i32 %17, %16
  br i1 %18, label %19, label %.split58

19:                                               ; preds = %14
  %20 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %4) #1
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %indvars.iv) #1
  store i32 1, ptr %21, align 4, !tbaa !5
  %22 = load i32, ptr @cont, align 4, !tbaa !5
  %23 = add nsw i32 %22, 1
  store i32 %23, ptr @cont, align 4, !tbaa !5
  br i1 %.not, label %36, label %24

24:                                               ; preds = %19
  %25 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %6) #1
  %26 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %indvars.iv) #1
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %indvars.iv) #1
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %.not48 = icmp slt i32 %27, %30
  br i1 %.not48, label %36, label %31

31:                                               ; preds = %24
  %32 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %6) #1
  %33 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %indvars.iv) #1
  %34 = load i32, ptr %33, align 4, !tbaa !5
  %.not49 = icmp eq i32 %34, 0
  br i1 %.not49, label %35, label %36

35:                                               ; preds = %31
  tail call void @_Z3dfsii(i32 noundef %5, i32 noundef %17)
  br label %36

36:                                               ; preds = %35, %31, %24, %19
  %37 = tail call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #1
  %38 = trunc i64 %37 to i32
  %39 = icmp slt i32 %7, %38
  br i1 %39, label %40, label %52

40:                                               ; preds = %36
  %41 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %8) #1
  %42 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %indvars.iv) #1
  %43 = load i32, ptr %42, align 4, !tbaa !5
  %44 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %45 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %44, i64 noundef %indvars.iv) #1
  %46 = load i32, ptr %45, align 4, !tbaa !5
  %.not50 = icmp slt i32 %43, %46
  br i1 %.not50, label %52, label %47

47:                                               ; preds = %40
  %48 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %8) #1
  %49 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %indvars.iv) #1
  %50 = load i32, ptr %49, align 4, !tbaa !5
  %.not51 = icmp eq i32 %50, 0
  br i1 %.not51, label %51, label %52

51:                                               ; preds = %47
  tail call void @_Z3dfsii(i32 noundef %7, i32 noundef %17)
  br label %52

52:                                               ; preds = %51, %47, %40, %36
  %53 = add nsw i32 %17, -1
  %.not56 = icmp eq i64 %indvars.iv, 0
  br i1 %.not56, label %67, label %54

54:                                               ; preds = %52
  %55 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %56 = zext nneg i32 %53 to i64
  %57 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %55, i64 noundef %56) #1
  %58 = load i32, ptr %57, align 4, !tbaa !5
  %59 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %60 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %59, i64 noundef %indvars.iv) #1
  %61 = load i32, ptr %60, align 4, !tbaa !5
  %.not52 = icmp slt i32 %58, %61
  br i1 %.not52, label %67, label %62

62:                                               ; preds = %54
  %63 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %4) #1
  %64 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %56) #1
  %65 = load i32, ptr %64, align 4, !tbaa !5
  %.not53 = icmp eq i32 %65, 0
  br i1 %.not53, label %66, label %67

66:                                               ; preds = %62
  tail call void @_Z3dfsii(i32 noundef %0, i32 noundef %53)
  br label %67

67:                                               ; preds = %66, %62, %54, %52
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %68 = tail call noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) @v) #1
  %69 = trunc i64 %68 to i32
  %70 = trunc nuw i64 %indvars.iv.next to i32
  %71 = icmp slt i32 %70, %69
  br i1 %71, label %72, label %.split58

72:                                               ; preds = %67
  %73 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %74 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %indvars.iv.next) #1
  %75 = load i32, ptr %74, align 4, !tbaa !5
  %76 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %4) #1
  %77 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %76, i64 noundef %indvars.iv) #1
  %78 = load i32, ptr %77, align 4, !tbaa !5
  %.not54 = icmp slt i32 %75, %78
  br i1 %.not54, label %.split58, label %79

79:                                               ; preds = %72
  %80 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vis, i64 noundef %4) #1
  %81 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %80, i64 noundef %indvars.iv.next) #1
  %82 = load i32, ptr %81, align 4, !tbaa !5
  %.not55 = icmp eq i32 %82, 0
  br i1 %.not55, label %tailrecurse, label %.split58

.split58:                                         ; preds = %tailrecurse, %14, %79, %72, %67, %2
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIS_IiSaIiEESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass