; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/URI/2546/main.ll (Z5buildiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl" }
%"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Data = type { i32, i32 }
%class.anon = type { i8 }

@v = external dso_local global %"class.std::vector", align 8
@st = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5buildiii(i32 noundef %0, i32 noundef %1, i32 noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca %struct.Data, align 4
  %9 = alloca %class.anon, align 1
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !5
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = load i32, ptr %6, align 4, !tbaa !5
  %12 = icmp eq i32 %10, %11
  br i1 %12, label %13, label %27

13:                                               ; preds = %3
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = sext i32 %14 to i64
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %15) #5
  %17 = load i32, ptr %16, align 4, !tbaa !5
  %18 = load i32, ptr %4, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %19) #5
  %21 = getelementptr inbounds %struct.Data, ptr %20, i32 0, i32 1
  store i32 %17, ptr %21, align 4, !tbaa !9
  %22 = load i32, ptr %5, align 4, !tbaa !5
  %23 = load i32, ptr %4, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %24) #5
  %26 = getelementptr inbounds %struct.Data, ptr %25, i32 0, i32 0
  store i32 %22, ptr %26, align 4, !tbaa !11
  br label %52

27:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = load i32, ptr %6, align 4, !tbaa !5
  %30 = call noundef i32 @_Z6middleii(i32 noundef %28, i32 noundef %29)
  store i32 %30, ptr %7, align 4, !tbaa !5
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = call noundef i32 @_Z4lefti(i32 noundef %31)
  %33 = load i32, ptr %5, align 4, !tbaa !5
  %34 = load i32, ptr %7, align 4, !tbaa !5
  call void @_Z5buildiii(i32 noundef %32, i32 noundef %33, i32 noundef %34)
  %35 = load i32, ptr %4, align 4, !tbaa !5
  %36 = call noundef i32 @_Z5righti(i32 noundef %35)
  %37 = load i32, ptr %7, align 4, !tbaa !5
  %38 = add nsw i32 %37, 1
  %39 = load i32, ptr %6, align 4, !tbaa !5
  call void @_Z5buildiii(i32 noundef %36, i32 noundef %38, i32 noundef %39)
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #5
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = call noundef i32 @_Z4lefti(i32 noundef %40)
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %42) #5
  %44 = load i32, ptr %4, align 4, !tbaa !5
  %45 = call noundef i32 @_Z5righti(i32 noundef %44)
  %46 = sext i32 %45 to i64
  %47 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %46) #5
  %48 = call i64 @"_ZZ5buildiiiENK3$_0clERK4DataS2_"(ptr noundef nonnull align 1 dereferenceable(1) %9, ptr noundef nonnull align 4 dereferenceable(8) %43, ptr noundef nonnull align 4 dereferenceable(8) %47)
  store i64 %48, ptr %8, align 4
  %49 = load i32, ptr %4, align 4, !tbaa !5
  %50 = sext i32 %49 to i64
  %51 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %50) #5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %51, ptr align 4 %8, i64 8, i1 false), !tbaa.struct !12
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  br label %52

52:                                               ; preds = %27, %13
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6middleii(i32 noundef, i32 noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z4lefti(i32 noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5righti(i32 noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden i64 @"_ZZ5buildiiiENK3$_0clERK4DataS2_"(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) #3 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 4}
!10 = !{!"_ZTS4Data", !6, i64 0, !6, i64 4}
!11 = !{!10, !6, i64 0}
!12 = !{i64 0, i64 4, !5, i64 4, i64 4, !5}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl" }
%"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl" = type { %"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Data, std::allocator<Data>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.anon = type { i8 }

@v = external dso_local global %"class.std::vector", align 8
@st = external dso_local global %"class.std::vector.0", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z5buildiii(i32 noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = alloca %class.anon, align 1
  %5 = icmp eq i32 %1, %2
  br i1 %5, label %common.ret, label %13

common.ret:                                       ; preds = %3
  %6 = sext i32 %1 to i64
  %7 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %6) #3
  %8 = load i32, ptr %7, align 4, !tbaa !5
  %9 = sext i32 %0 to i64
  %10 = tail call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %9) #3
  %11 = getelementptr inbounds i8, ptr %10, i64 4
  store i32 %8, ptr %11, align 4, !tbaa !9
  %12 = tail call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %9) #3
  store i32 %1, ptr %12, align 4, !tbaa !11
  br label %common.ret18

common.ret18:                                     ; preds = %13, %common.ret
  ret void

13:                                               ; preds = %3
  %14 = tail call noundef i32 @_Z6middleii(i32 noundef %1, i32 noundef %2)
  %15 = tail call noundef i32 @_Z4lefti(i32 noundef %0)
  tail call void @_Z5buildiii(i32 noundef %15, i32 noundef %1, i32 noundef %14)
  %16 = tail call noundef i32 @_Z5righti(i32 noundef %0)
  %17 = add nsw i32 %14, 1
  tail call void @_Z5buildiii(i32 noundef %16, i32 noundef %17, i32 noundef %2)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  %18 = tail call noundef i32 @_Z4lefti(i32 noundef %0)
  %19 = sext i32 %18 to i64
  %20 = tail call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %19) #3
  %21 = tail call noundef i32 @_Z5righti(i32 noundef %0)
  %22 = sext i32 %21 to i64
  %23 = tail call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %22) #3
  %24 = call i64 @"_ZZ5buildiiiENK3$_0clERK4DataS2_"(ptr noundef nonnull align 1 dereferenceable(1) %4, ptr noundef nonnull align 4 dereferenceable(8) %20, ptr noundef nonnull align 4 dereferenceable(8) %23)
  %25 = sext i32 %0 to i64
  %26 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %25) #3
  store i64 %24, ptr %26, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  br label %common.ret18
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorI4DataSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z6middleii(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z4lefti(i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_Z5righti(i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden i64 @"_ZZ5buildiiiENK3$_0clERK4DataS2_"(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 4}
!10 = !{!"_ZTS4Data", !6, i64 0, !6, i64 4}
!11 = !{!10, !6, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass