; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/URI/2519/main.ll (Z6updateiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@fk = external dso_local global %"class.std::vector", align 8
@n = external dso_local global i32, align 4
@m = external dso_local global i32, align 4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updateiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  %12 = load i32, ptr %5, align 4, !tbaa !5
  store i32 %12, ptr %9, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %54, %4
  %14 = load i32, ptr %9, align 4, !tbaa !5
  %15 = load i32, ptr @n, align 4, !tbaa !5
  %16 = add nsw i32 %15, 1
  %17 = icmp slt i32 %14, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %13
  store i32 2, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  br label %61

19:                                               ; preds = %13
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #2
  %20 = load i32, ptr %6, align 4, !tbaa !5
  store i32 %20, ptr %11, align 4, !tbaa !5
  br label %21

21:                                               ; preds = %46, %19
  %22 = load i32, ptr %11, align 4, !tbaa !5
  %23 = load i32, ptr @m, align 4, !tbaa !5
  %24 = add nsw i32 %23, 1
  %25 = icmp slt i32 %22, %24
  br i1 %25, label %27, label %26

26:                                               ; preds = %21
  store i32 5, ptr %10, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #2
  br label %53

27:                                               ; preds = %21
  %28 = load i32, ptr %8, align 4, !tbaa !5
  %29 = load i32, ptr %9, align 4, !tbaa !5
  %30 = sext i32 %29 to i64
  %31 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @fk, i64 noundef %30) #2
  %32 = load i32, ptr %11, align 4, !tbaa !5
  %33 = sext i32 %32 to i64
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %33) #2
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = sub nsw i32 %35, %28
  store i32 %36, ptr %34, align 4, !tbaa !5
  %37 = load i32, ptr %7, align 4, !tbaa !5
  %38 = load i32, ptr %9, align 4, !tbaa !5
  %39 = sext i32 %38 to i64
  %40 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @fk, i64 noundef %39) #2
  %41 = load i32, ptr %11, align 4, !tbaa !5
  %42 = sext i32 %41 to i64
  %43 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %40, i64 noundef %42) #2
  %44 = load i32, ptr %43, align 4, !tbaa !5
  %45 = add nsw i32 %44, %37
  store i32 %45, ptr %43, align 4, !tbaa !5
  br label %46

46:                                               ; preds = %27
  %47 = load i32, ptr %11, align 4, !tbaa !5
  %48 = load i32, ptr %11, align 4, !tbaa !5
  %49 = sub nsw i32 0, %48
  %50 = and i32 %47, %49
  %51 = load i32, ptr %11, align 4, !tbaa !5
  %52 = add nsw i32 %51, %50
  store i32 %52, ptr %11, align 4, !tbaa !5
  br label %21, !llvm.loop !9

53:                                               ; preds = %26
  br label %54

54:                                               ; preds = %53
  %55 = load i32, ptr %9, align 4, !tbaa !5
  %56 = load i32, ptr %9, align 4, !tbaa !5
  %57 = sub nsw i32 0, %56
  %58 = and i32 %55, %57
  %59 = load i32, ptr %9, align 4, !tbaa !5
  %60 = add nsw i32 %59, %58
  store i32 %60, ptr %9, align 4, !tbaa !5
  br label %13, !llvm.loop !11

61:                                               ; preds = %18
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@fk = external dso_local global %"class.std::vector", align 8
@n = external dso_local local_unnamed_addr global i32, align 4
@m = external dso_local local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updateiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = load i32, ptr @n, align 4, !tbaa !5
  %.not20 = icmp slt i32 %5, %0
  %6 = load i32, ptr @m, align 4
  %7 = icmp slt i32 %6, %1
  %or.cond = select i1 %.not20, i1 true, i1 %7
  br i1 %or.cond, label %._crit_edge22, label %.preheader

.preheader:                                       ; preds = %4, %._crit_edge
  %8 = phi i32 [ %11, %._crit_edge ], [ %5, %4 ]
  %9 = phi i32 [ %12, %._crit_edge ], [ %6, %4 ]
  %.01621 = phi i32 [ %15, %._crit_edge ], [ %0, %4 ]
  %.not1718 = icmp slt i32 %9, %1
  br i1 %.not1718, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader
  %10 = sext i32 %.01621 to i64
  br label %16

._crit_edge22:                                    ; preds = %._crit_edge, %4
  ret void

._crit_edge.loopexit:                             ; preds = %16
  %.pre = load i32, ptr @n, align 4, !tbaa !5
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.preheader
  %11 = phi i32 [ %.pre, %._crit_edge.loopexit ], [ %8, %.preheader ]
  %12 = phi i32 [ %29, %._crit_edge.loopexit ], [ %9, %.preheader ]
  %13 = sub nsw i32 0, %.01621
  %14 = and i32 %.01621, %13
  %15 = add nsw i32 %14, %.01621
  %.not = icmp sgt i32 %15, %11
  br i1 %.not, label %._crit_edge22, label %.preheader, !llvm.loop !9

16:                                               ; preds = %.lr.ph, %16
  %.019 = phi i32 [ %1, %.lr.ph ], [ %28, %16 ]
  %17 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @fk, i64 noundef %10) #1
  %18 = sext i32 %.019 to i64
  %19 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %18) #1
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = sub nsw i32 %20, %3
  store i32 %21, ptr %19, align 4, !tbaa !5
  %22 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @fk, i64 noundef %10) #1
  %23 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %18) #1
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %25 = add nsw i32 %24, %2
  store i32 %25, ptr %23, align 4, !tbaa !5
  %26 = sub nsw i32 0, %.019
  %27 = and i32 %.019, %26
  %28 = add nsw i32 %27, %.019
  %29 = load i32, ptr @m, align 4, !tbaa !5
  %.not17 = icmp sgt i32 %28, %29
  br i1 %.not17, label %._crit_edge.loopexit, label %16, !llvm.loop !12
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10, !11}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!"llvm.loop.unswitch.partial.disable"}
!12 = distinct !{!12, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass