; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/Neps Academy/Troco em Moedas (main)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }

@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca [6 x i32], align 16
  %5 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #6
  store i32 0, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 24, ptr %4) #6
  call void @llvm.memset.p0.i64(ptr align 16 %4, i8 0, i64 24, i1 false)
  %6 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 4 dereferenceable(4) %2)
  br label %7

7:                                                ; preds = %10, %0
  %8 = load i32, ptr %2, align 4, !tbaa !5
  %9 = icmp sge i32 %8, 100
  br i1 %9, label %10, label %18

10:                                               ; preds = %7
  %11 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 0
  %12 = load i32, ptr %11, align 16, !tbaa !5
  %13 = add nsw i32 %12, 1
  store i32 %13, ptr %11, align 16, !tbaa !5
  %14 = load i32, ptr %2, align 4, !tbaa !5
  %15 = sub nsw i32 %14, 100
  store i32 %15, ptr %2, align 4, !tbaa !5
  %16 = load i32, ptr %3, align 4, !tbaa !5
  %17 = add nsw i32 %16, 1
  store i32 %17, ptr %3, align 4, !tbaa !5
  br label %7, !llvm.loop !9

18:                                               ; preds = %7
  br label %19

19:                                               ; preds = %22, %18
  %20 = load i32, ptr %2, align 4, !tbaa !5
  %21 = icmp sge i32 %20, 50
  br i1 %21, label %22, label %30

22:                                               ; preds = %19
  %23 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 1
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %25 = add nsw i32 %24, 1
  store i32 %25, ptr %23, align 4, !tbaa !5
  %26 = load i32, ptr %2, align 4, !tbaa !5
  %27 = sub nsw i32 %26, 50
  store i32 %27, ptr %2, align 4, !tbaa !5
  %28 = load i32, ptr %3, align 4, !tbaa !5
  %29 = add nsw i32 %28, 1
  store i32 %29, ptr %3, align 4, !tbaa !5
  br label %19, !llvm.loop !11

30:                                               ; preds = %19
  br label %31

31:                                               ; preds = %34, %30
  %32 = load i32, ptr %2, align 4, !tbaa !5
  %33 = icmp sge i32 %32, 25
  br i1 %33, label %34, label %42

34:                                               ; preds = %31
  %35 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 2
  %36 = load i32, ptr %35, align 8, !tbaa !5
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %35, align 8, !tbaa !5
  %38 = load i32, ptr %2, align 4, !tbaa !5
  %39 = sub nsw i32 %38, 25
  store i32 %39, ptr %2, align 4, !tbaa !5
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %3, align 4, !tbaa !5
  br label %31, !llvm.loop !12

42:                                               ; preds = %31
  br label %43

43:                                               ; preds = %46, %42
  %44 = load i32, ptr %2, align 4, !tbaa !5
  %45 = icmp sge i32 %44, 10
  br i1 %45, label %46, label %54

46:                                               ; preds = %43
  %47 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 3
  %48 = load i32, ptr %47, align 4, !tbaa !5
  %49 = add nsw i32 %48, 1
  store i32 %49, ptr %47, align 4, !tbaa !5
  %50 = load i32, ptr %2, align 4, !tbaa !5
  %51 = sub nsw i32 %50, 10
  store i32 %51, ptr %2, align 4, !tbaa !5
  %52 = load i32, ptr %3, align 4, !tbaa !5
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %3, align 4, !tbaa !5
  br label %43, !llvm.loop !13

54:                                               ; preds = %43
  br label %55

55:                                               ; preds = %58, %54
  %56 = load i32, ptr %2, align 4, !tbaa !5
  %57 = icmp sge i32 %56, 5
  br i1 %57, label %58, label %66

58:                                               ; preds = %55
  %59 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 4
  %60 = load i32, ptr %59, align 16, !tbaa !5
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %59, align 16, !tbaa !5
  %62 = load i32, ptr %2, align 4, !tbaa !5
  %63 = sub nsw i32 %62, 5
  store i32 %63, ptr %2, align 4, !tbaa !5
  %64 = load i32, ptr %3, align 4, !tbaa !5
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %3, align 4, !tbaa !5
  br label %55, !llvm.loop !14

66:                                               ; preds = %55
  br label %67

67:                                               ; preds = %70, %66
  %68 = load i32, ptr %2, align 4, !tbaa !5
  %69 = icmp sge i32 %68, 1
  br i1 %69, label %70, label %78

70:                                               ; preds = %67
  %71 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 5
  %72 = load i32, ptr %71, align 4, !tbaa !5
  %73 = add nsw i32 %72, 1
  store i32 %73, ptr %71, align 4, !tbaa !5
  %74 = load i32, ptr %2, align 4, !tbaa !5
  %75 = sub nsw i32 %74, 1
  store i32 %75, ptr %2, align 4, !tbaa !5
  %76 = load i32, ptr %3, align 4, !tbaa !5
  %77 = add nsw i32 %76, 1
  store i32 %77, ptr %3, align 4, !tbaa !5
  br label %67, !llvm.loop !15

78:                                               ; preds = %67
  %79 = load i32, ptr %3, align 4, !tbaa !5
  %80 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %79)
  %81 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %80, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #6
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %82

82:                                               ; preds = %93, %78
  %83 = load i32, ptr %5, align 4, !tbaa !5
  %84 = icmp slt i32 %83, 6
  br i1 %84, label %86, label %85

85:                                               ; preds = %82
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #6
  br label %96

86:                                               ; preds = %82
  %87 = load i32, ptr %5, align 4, !tbaa !5
  %88 = sext i32 %87 to i64
  %89 = getelementptr inbounds [6 x i32], ptr %4, i64 0, i64 %88
  %90 = load i32, ptr %89, align 4, !tbaa !5
  %91 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %90)
  %92 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %91, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  br label %93

93:                                               ; preds = %86
  %94 = load i32, ptr %5, align 4, !tbaa !5
  %95 = add nsw i32 %94, 1
  store i32 %95, ptr %5, align 4, !tbaa !5
  br label %82, !llvm.loop !16

96:                                               ; preds = %85
  call void @llvm.lifetime.end.p0(i64 24, ptr %4) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #6
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4)) #3

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #4 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #5

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !10}
!16 = distinct !{!16, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }

@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #0 {
  %1 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #6
  %2 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 4 dereferenceable(4) %1)
  %.pr = load i32, ptr %1, align 4, !tbaa !5
  %3 = icmp sgt i32 %.pr, 99
  br i1 %3, label %.lr.ph.preheader, label %thread-pre-split

.lr.ph.preheader:                                 ; preds = %0
  %4 = call i32 @llvm.usub.sat.i32(i32 %.pr, i32 199)
  %5 = add nuw i32 %4, 99
  %6 = udiv i32 %5, 100
  %7 = add nuw nsw i32 %6, 1
  %.neg = mul nsw i32 %6, -100
  %8 = add nsw i32 %.pr, -100
  %9 = add nsw i32 %.neg, %8
  store i32 %9, ptr %1, align 4, !tbaa !5
  br label %thread-pre-split

thread-pre-split:                                 ; preds = %.lr.ph.preheader, %0
  %.pr11 = phi i32 [ %9, %.lr.ph.preheader ], [ %.pr, %0 ]
  %.lcssa = phi i32 [ %7, %.lr.ph.preheader ], [ 0, %0 ]
  %10 = icmp sgt i32 %.pr11, 49
  br i1 %10, label %.lr.ph24, label %thread-pre-split12

.lr.ph24:                                         ; preds = %thread-pre-split
  %11 = call i32 @llvm.usub.sat.i32(i32 %.pr11, i32 99)
  %12 = add nuw i32 %11, 49
  %13 = udiv i32 %12, 50
  %14 = add nuw nsw i32 %13, 1
  %.neg87 = mul nsw i32 %13, -50
  %15 = add nuw nsw i32 %.lcssa, %13
  %16 = add nsw i32 %.pr11, -50
  %17 = add nsw i32 %.neg87, %16
  %18 = add nuw nsw i32 %15, 1
  store i32 %17, ptr %1, align 4, !tbaa !5
  br label %thread-pre-split12

thread-pre-split12:                               ; preds = %.lr.ph24, %thread-pre-split
  %.pr13 = phi i32 [ %17, %.lr.ph24 ], [ %.pr11, %thread-pre-split ]
  %.sroa.5.0 = phi i32 [ %14, %.lr.ph24 ], [ 0, %thread-pre-split ]
  %.1.lcssa = phi i32 [ %18, %.lr.ph24 ], [ %.lcssa, %thread-pre-split ]
  %19 = icmp sgt i32 %.pr13, 24
  br i1 %19, label %.lr.ph30, label %thread-pre-split14

.lr.ph30:                                         ; preds = %thread-pre-split12
  %20 = call i32 @llvm.usub.sat.i32(i32 %.pr13, i32 49)
  %21 = add nuw i32 %20, 24
  %22 = udiv i32 %21, 25
  %23 = add nuw nsw i32 %22, 1
  %.neg88 = mul nsw i32 %22, -25
  %24 = add nuw nsw i32 %.1.lcssa, %22
  %25 = add nsw i32 %.pr13, -25
  %26 = add nsw i32 %.neg88, %25
  %27 = add nuw nsw i32 %24, 1
  store i32 %26, ptr %1, align 4, !tbaa !5
  br label %thread-pre-split14

thread-pre-split14:                               ; preds = %.lr.ph30, %thread-pre-split12
  %.pr15 = phi i32 [ %26, %.lr.ph30 ], [ %.pr13, %thread-pre-split12 ]
  %.sroa.8.0 = phi i32 [ %23, %.lr.ph30 ], [ 0, %thread-pre-split12 ]
  %.2.lcssa = phi i32 [ %27, %.lr.ph30 ], [ %.1.lcssa, %thread-pre-split12 ]
  %28 = icmp sgt i32 %.pr15, 9
  br i1 %28, label %.lr.ph36, label %thread-pre-split16

.lr.ph36:                                         ; preds = %thread-pre-split14
  %29 = call i32 @llvm.usub.sat.i32(i32 %.pr15, i32 19)
  %30 = add nuw i32 %29, 9
  %31 = udiv i32 %30, 10
  %32 = add nuw nsw i32 %31, 1
  %.neg89 = mul nsw i32 %31, -10
  %33 = add nuw nsw i32 %.2.lcssa, %31
  %34 = add nsw i32 %.pr15, -10
  %35 = add nsw i32 %.neg89, %34
  %36 = add nuw nsw i32 %33, 1
  store i32 %35, ptr %1, align 4, !tbaa !5
  br label %thread-pre-split16

thread-pre-split16:                               ; preds = %.lr.ph36, %thread-pre-split14
  %.pr17 = phi i32 [ %35, %.lr.ph36 ], [ %.pr15, %thread-pre-split14 ]
  %.sroa.11.0 = phi i32 [ %32, %.lr.ph36 ], [ 0, %thread-pre-split14 ]
  %.3.lcssa = phi i32 [ %36, %.lr.ph36 ], [ %.2.lcssa, %thread-pre-split14 ]
  %37 = icmp sgt i32 %.pr17, 4
  br i1 %37, label %.lr.ph42, label %thread-pre-split18

.lr.ph42:                                         ; preds = %thread-pre-split16
  %38 = call i32 @llvm.usub.sat.i32(i32 %.pr17, i32 9)
  %39 = add nuw i32 %38, 4
  %40 = udiv i32 %39, 5
  %41 = add nuw nsw i32 %40, 1
  %.neg90 = mul nsw i32 %40, -5
  %42 = add nuw nsw i32 %.3.lcssa, %40
  %43 = add nsw i32 %.pr17, -5
  %44 = add nsw i32 %.neg90, %43
  %45 = add nuw nsw i32 %42, 1
  store i32 %44, ptr %1, align 4, !tbaa !5
  br label %thread-pre-split18

thread-pre-split18:                               ; preds = %.lr.ph42, %thread-pre-split16
  %.pr19 = phi i32 [ %44, %.lr.ph42 ], [ %.pr17, %thread-pre-split16 ]
  %.sroa.14.0 = phi i32 [ %41, %.lr.ph42 ], [ 0, %thread-pre-split16 ]
  %.4.lcssa = phi i32 [ %45, %.lr.ph42 ], [ %.3.lcssa, %thread-pre-split16 ]
  %46 = icmp sgt i32 %.pr19, 0
  br i1 %46, label %.lr.ph48, label %48

.lr.ph48:                                         ; preds = %thread-pre-split18
  %47 = add nuw i32 %.4.lcssa, %.pr19
  store i32 0, ptr %1, align 4, !tbaa !5
  br label %48

48:                                               ; preds = %.lr.ph48, %thread-pre-split18
  %.sroa.17.0 = phi i32 [ %.pr19, %.lr.ph48 ], [ 0, %thread-pre-split18 ]
  %.5.lcssa = phi i32 [ %47, %.lr.ph48 ], [ %.4.lcssa, %thread-pre-split18 ]
  %49 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.5.lcssa)
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %49, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %51 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.lcssa)
  %52 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %51, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %53 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.sroa.5.0)
  %54 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %53, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %55 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.sroa.8.0)
  %56 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %55, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.sroa.11.0)
  %58 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %57, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %59 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.sroa.14.0)
  %60 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %59, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  %61 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.sroa.17.0)
  %62 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %61, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1) #6
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.usub.sat.i32(i32, i32) #5

attributes #0 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,SCCPPass,SROAPass,SimplifyCFGPass