; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/devices (mfrc522)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_WriteRegister(i8 noundef zeroext, i8 noundef zeroext) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_WriteRegister_n(i8 noundef zeroext, i8 noundef zeroext, ptr noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext) #0

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_SetRegisterBitMask(i8 noundef zeroext, i8 noundef zeroext) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @MFRC522_PCD_CalculateCRC(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i16, align 2
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 0)
  call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 10, i8 noundef zeroext 4)
  call void @MFRC522_PCD_SetRegisterBitMask(i8 noundef zeroext 20, i8 noundef zeroext -128)
  %11 = load i8, ptr %6, align 1, !tbaa !9
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  call void @MFRC522_PCD_WriteRegister_n(i8 noundef zeroext 18, i8 noundef zeroext %11, ptr noundef %12)
  call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 3)
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #2
  store i16 5000, ptr %8, align 2, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #2
  br label %13

13:                                               ; preds = %27, %3
  br label %14

14:                                               ; preds = %13
  %15 = call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 10)
  store i8 %15, ptr %9, align 1, !tbaa !9
  %16 = load i8, ptr %9, align 1, !tbaa !9
  %17 = zext i8 %16 to i32
  %18 = and i32 %17, 4
  %19 = icmp ne i32 %18, 0
  br i1 %19, label %20, label %21

20:                                               ; preds = %14
  br label %28

21:                                               ; preds = %14
  %22 = load i16, ptr %8, align 2, !tbaa !10
  %23 = add i16 %22, -1
  store i16 %23, ptr %8, align 2, !tbaa !10
  %24 = zext i16 %23 to i32
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 3, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %35

27:                                               ; preds = %21
  br label %13

28:                                               ; preds = %20
  call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 0)
  %29 = call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 68)
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = getelementptr inbounds i8, ptr %30, i64 0
  store i8 %29, ptr %31, align 1, !tbaa !9
  %32 = call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 66)
  %33 = load ptr, ptr %7, align 8, !tbaa !5
  %34 = getelementptr inbounds i8, ptr %33, i64 1
  store i8 %32, ptr %34, align 1, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %35

35:                                               ; preds = %28, %26
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #2
  %36 = load i32, ptr %4, align 4
  ret i32 %36
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_WriteRegister(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_WriteRegister_n(i8 noundef zeroext, i8 noundef zeroext, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @MFRC522_PCD_SetRegisterBitMask(i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 4) i32 @MFRC522_PCD_CalculateCRC(ptr noundef %0, i8 noundef zeroext %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 {
  tail call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 0)
  tail call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 10, i8 noundef zeroext 4)
  tail call void @MFRC522_PCD_SetRegisterBitMask(i8 noundef zeroext 20, i8 noundef zeroext -128)
  tail call void @MFRC522_PCD_WriteRegister_n(i8 noundef zeroext 18, i8 noundef zeroext %1, ptr noundef %0)
  tail call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 3)
  br label %4

4:                                                ; preds = %7, %3
  %.06 = phi i16 [ 5000, %3 ], [ %8, %7 ]
  %5 = tail call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 10)
  %6 = and i8 %5, 4
  %.not = icmp eq i8 %6, 0
  br i1 %.not, label %7, label %10

7:                                                ; preds = %4
  %8 = add nsw i16 %.06, -1
  %9 = icmp eq i16 %8, 0
  br i1 %9, label %.loopexit, label %4

10:                                               ; preds = %4
  tail call void @MFRC522_PCD_WriteRegister(i8 noundef zeroext 2, i8 noundef zeroext 0)
  %11 = tail call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 68)
  store i8 %11, ptr %2, align 1, !tbaa !5
  %12 = tail call zeroext i8 @MFRC522_PCD_ReadRegister(i8 noundef zeroext 66)
  %13 = getelementptr inbounds i8, ptr %2, i64 1
  store i8 %12, ptr %13, align 1, !tbaa !5
  br label %.loopexit

.loopexit:                                        ; preds = %7, %10
  %.0 = phi i32 [ 0, %10 ], [ 3, %7 ]
  ret i32 %.0
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass