; LLVM IR from indjev99/Evolving-Snakes :: sources/ctrNeuralNetwork.ll (ZN16ctrNeuralNetwork13decodeOutputsEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.decision = type { i8, i8, i8, i8, i8, i32 }
%struct.ctrNeuralNetwork = type { %struct.controller, double, double, double, i32, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %"class.std::vector.5", %"class.std::vector.5" }
%struct.controller = type { ptr, [3 x i32], [3 x i8], [1 x i32], [1 x i8], [1 x i32], [1 x i8], i32, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<std::vector<double>>, std::allocator<std::vector<std::vector<double>>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<std::vector<double>>, std::allocator<std::vector<std::vector<double>>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<std::vector<double>>, std::allocator<std::vector<std::vector<double>>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<std::vector<double>>, std::allocator<std::vector<std::vector<double>>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.round.f64(double) #2

; Function Attrs: mustprogress nounwind uwtable
define dso_local { i64, i32 } @_ZN16ctrNeuralNetwork13decodeOutputsEv(ptr noundef nonnull align 8 dereferenceable(200) %0) #1 align 2 {
  %2 = alloca %struct.decision, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca { i64, i32 }, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !9
  %7 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %8 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %9 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  %10 = sub i64 %9, 1
  %11 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %10) #4
  %12 = load i32, ptr %4, align 4, !tbaa !9
  %13 = add nsw i32 %12, 1
  store i32 %13, ptr %4, align 4, !tbaa !9
  %14 = sext i32 %12 to i64
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %14) #4
  %16 = load double, ptr %15, align 8, !tbaa !11
  %17 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 3
  %18 = load double, ptr %17, align 8, !tbaa !13
  %19 = fcmp oge double %16, %18
  br i1 %19, label %20, label %22

20:                                               ; preds = %1
  %21 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 0
  store i8 1, ptr %21, align 4, !tbaa !28
  br label %24

22:                                               ; preds = %1
  %23 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 0
  store i8 0, ptr %23, align 4, !tbaa !28
  br label %24

24:                                               ; preds = %22, %20
  %25 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %26 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %27 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #4
  %28 = sub i64 %27, 1
  %29 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %28) #4
  %30 = load i32, ptr %4, align 4, !tbaa !9
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %4, align 4, !tbaa !9
  %32 = sext i32 %30 to i64
  %33 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %32) #4
  %34 = load double, ptr %33, align 8, !tbaa !11
  %35 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 3
  %36 = load double, ptr %35, align 8, !tbaa !13
  %37 = fcmp oge double %34, %36
  br i1 %37, label %38, label %40

38:                                               ; preds = %24
  %39 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 1
  store i8 1, ptr %39, align 1, !tbaa !31
  br label %42

40:                                               ; preds = %24
  %41 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 1
  store i8 0, ptr %41, align 1, !tbaa !31
  br label %42

42:                                               ; preds = %40, %38
  %43 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %44 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %45 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %44) #4
  %46 = sub i64 %45, 1
  %47 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %46) #4
  %48 = load i32, ptr %4, align 4, !tbaa !9
  %49 = add nsw i32 %48, 1
  store i32 %49, ptr %4, align 4, !tbaa !9
  %50 = sext i32 %48 to i64
  %51 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %47, i64 noundef %50) #4
  %52 = load double, ptr %51, align 8, !tbaa !11
  %53 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 3
  %54 = load double, ptr %53, align 8, !tbaa !13
  %55 = fcmp oge double %52, %54
  br i1 %55, label %56, label %58

56:                                               ; preds = %42
  %57 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 2
  store i8 1, ptr %57, align 2, !tbaa !32
  br label %60

58:                                               ; preds = %42
  %59 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 2
  store i8 0, ptr %59, align 2, !tbaa !32
  br label %60

60:                                               ; preds = %58, %56
  %61 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %62 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %63 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %62) #4
  %64 = sub i64 %63, 1
  %65 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %61, i64 noundef %64) #4
  %66 = load i32, ptr %4, align 4, !tbaa !9
  %67 = add nsw i32 %66, 1
  store i32 %67, ptr %4, align 4, !tbaa !9
  %68 = sext i32 %66 to i64
  %69 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %65, i64 noundef %68) #4
  %70 = load double, ptr %69, align 8, !tbaa !11
  %71 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 3
  %72 = load double, ptr %71, align 8, !tbaa !13
  %73 = fcmp oge double %70, %72
  br i1 %73, label %74, label %76

74:                                               ; preds = %60
  %75 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 3
  store i8 1, ptr %75, align 1, !tbaa !33
  br label %78

76:                                               ; preds = %60
  %77 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 3
  store i8 0, ptr %77, align 1, !tbaa !33
  br label %78

78:                                               ; preds = %76, %74
  %79 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %80 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %81 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %80) #4
  %82 = sub i64 %81, 1
  %83 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %79, i64 noundef %82) #4
  %84 = load i32, ptr %4, align 4, !tbaa !9
  %85 = add nsw i32 %84, 1
  store i32 %85, ptr %4, align 4, !tbaa !9
  %86 = sext i32 %84 to i64
  %87 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %83, i64 noundef %86) #4
  %88 = load double, ptr %87, align 8, !tbaa !11
  %89 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 3
  %90 = load double, ptr %89, align 8, !tbaa !13
  %91 = fcmp oge double %88, %90
  br i1 %91, label %92, label %94

92:                                               ; preds = %78
  %93 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 4
  store i8 1, ptr %93, align 4, !tbaa !34
  br label %96

94:                                               ; preds = %78
  %95 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 4
  store i8 0, ptr %95, align 4, !tbaa !34
  br label %96

96:                                               ; preds = %94, %92
  %97 = getelementptr inbounds %struct.controller, ptr %6, i32 0, i32 7
  %98 = load i32, ptr %97, align 8, !tbaa !35
  %99 = sitofp i32 %98 to double
  %100 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 7
  %101 = getelementptr inbounds %struct.ctrNeuralNetwork, ptr %6, i32 0, i32 5
  %102 = call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %101) #4
  %103 = sub i64 %102, 1
  %104 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %100, i64 noundef %103) #4
  %105 = load i32, ptr %4, align 4, !tbaa !9
  %106 = add nsw i32 %105, 1
  store i32 %106, ptr %4, align 4, !tbaa !9
  %107 = sext i32 %105 to i64
  %108 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %104, i64 noundef %107) #4
  %109 = load double, ptr %108, align 8, !tbaa !11
  %110 = fmul double %99, %109
  %111 = call double @llvm.round.f64(double %110)
  %112 = fptosi double %111 to i32
  %113 = getelementptr inbounds %struct.decision, ptr %2, i32 0, i32 5
  store i32 %112, ptr %113, align 4, !tbaa !36
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %5, ptr align 4 %2, i64 12, i1 false)
  %114 = load { i64, i32 }, ptr %5, align 8
  ret { i64, i32 } %114
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"double", !7, i64 0}
!13 = !{!14, !12, i64 64}
!14 = !{!"_ZTS16ctrNeuralNetwork", !15, i64 0, !12, i64 48, !12, i64 56, !12, i64 64, !10, i64 72, !16, i64 80, !20, i64 104, !24, i64 128, !24, i64 152, !24, i64 176}
!15 = !{!"_ZTS10controller", !7, i64 8, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !10, i64 40, !10, i64 44}
!16 = !{!"_ZTSSt6vectorIiSaIiEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"_ZTSSt6vectorIS_IS_IdSaIdEESaIS1_EESaIS3_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!24 = !{!"_ZTSSt6vectorIS_IdSaIdEESaIS1_EE", !25, i64 0}
!25 = !{!"_ZTSSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE12_Vector_implE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!28 = !{!29, !30, i64 0}
!29 = !{!"_ZTS8decision", !30, i64 0, !30, i64 1, !30, i64 2, !30, i64 3, !30, i64 4, !10, i64 8}
!30 = !{!"bool", !7, i64 0}
!31 = !{!29, !30, i64 1}
!32 = !{!29, !30, i64 2}
!33 = !{!29, !30, i64 3}
!34 = !{!29, !30, i64 4}
!35 = !{!15, !10, i64 40}
!36 = !{!29, !10, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.round.f64(double) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local { i64, i32 } @_ZN16ctrNeuralNetwork13decodeOutputsEv(ptr noundef nonnull align 8 dereferenceable(200) %0) local_unnamed_addr #0 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 128
  %3 = getelementptr inbounds i8, ptr %0, i64 80
  %4 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %5 = add i64 %4, -1
  %6 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %5) #2
  %7 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef 0) #2
  %8 = load double, ptr %7, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %0, i64 64
  %10 = load double, ptr %9, align 8, !tbaa !9
  %11 = fcmp oge double %8, %10
  %. = zext i1 %11 to i64
  %12 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %13 = add i64 %12, -1
  %14 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %13) #2
  %15 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef 1) #2
  %16 = load double, ptr %15, align 8, !tbaa !5
  %17 = load double, ptr %9, align 8, !tbaa !9
  %18 = fcmp ult double %16, %17
  %.sroa.3.0 = select i1 %18, i64 0, i64 256
  %19 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %20 = add i64 %19, -1
  %21 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %20) #2
  %22 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef 2) #2
  %23 = load double, ptr %22, align 8, !tbaa !5
  %24 = load double, ptr %9, align 8, !tbaa !9
  %25 = fcmp ult double %23, %24
  %.sroa.5.0 = select i1 %25, i64 0, i64 65536
  %26 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %27 = add i64 %26, -1
  %28 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %27) #2
  %29 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef 3) #2
  %30 = load double, ptr %29, align 8, !tbaa !5
  %31 = load double, ptr %9, align 8, !tbaa !9
  %32 = fcmp ult double %30, %31
  %.sroa.7.0 = select i1 %32, i64 0, i64 16777216
  %33 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %34 = add i64 %33, -1
  %35 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %34) #2
  %36 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef 4) #2
  %37 = load double, ptr %36, align 8, !tbaa !5
  %38 = load double, ptr %9, align 8, !tbaa !9
  %39 = fcmp ult double %37, %38
  %.sroa.9.0 = select i1 %39, i64 0, i64 4294967296
  %40 = getelementptr inbounds i8, ptr %0, i64 40
  %41 = load i32, ptr %40, align 8, !tbaa !26
  %42 = sitofp i32 %41 to double
  %43 = tail call noundef i64 @_ZNKSt6vectorIiSaIiEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #2
  %44 = add i64 %43, -1
  %45 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IdSaIdEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %44) #2
  %46 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %45, i64 noundef 5) #2
  %47 = load double, ptr %46, align 8, !tbaa !5
  %48 = fmul double %47, %42
  %49 = tail call double @llvm.round.f64(double %48)
  %50 = fptosi double %49 to i32
  %.sroa.7.0.insert.insert = or disjoint i64 %.sroa.3.0, %.
  %.sroa.5.0.insert.insert = or disjoint i64 %.sroa.7.0.insert.insert, %.sroa.5.0
  %.sroa.3.0.insert.insert = or disjoint i64 %.sroa.5.0.insert.insert, %.sroa.7.0
  %.sroa.06.0.insert.insert = or disjoint i64 %.sroa.3.0.insert.insert, %.sroa.9.0
  %.fca.0.insert = insertvalue { i64, i32 } poison, i64 %.sroa.06.0.insert.insert, 0
  %.fca.1.insert = insertvalue { i64, i32 } %.fca.0.insert, i32 %50, 1
  ret { i64, i32 } %.fca.1.insert
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 64}
!10 = !{!"_ZTS16ctrNeuralNetwork", !11, i64 0, !6, i64 48, !6, i64 56, !6, i64 64, !12, i64 72, !13, i64 80, !18, i64 104, !22, i64 128, !22, i64 152, !22, i64 176}
!11 = !{!"_ZTS10controller", !7, i64 8, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !12, i64 40, !12, i64 44}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIiSaIiEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!17 = !{!"any pointer", !7, i64 0}
!18 = !{!"_ZTSSt6vectorIS_IS_IdSaIdEESaIS1_EESaIS3_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IdSaIdEESaIS2_EESaIS4_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!22 = !{!"_ZTSSt6vectorIS_IdSaIdEESaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}
!26 = !{!11, !12, i64 40}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass