; LLVM IR from romerojosh/zefr :: src/hexas.ll (ZN5Hexas16calc_nodal_basisEPdS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.Elements = type { ptr, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i8], %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %"class.std::vector.0", %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector.5, %class.mdvector.5, %class.mdvector.5, %class.mdvector.5, %class.mdvector.5, %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, i32, %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector", %"class.std::vector.7", %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, i64, i64, i64, i64, i64, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdview, %class.mdview, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, %class.mdvector, i32, [4 x i8], %class.mdvector, %class.mdvector, i32, ptr, %"class.std::vector.7", %class.mdvector.5, %class.mdvector, %class.mdvector, %class.mdvector }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.mdview = type { %class.mdvector.12, %class.mdvector.5, i32, [4 x i8] }
%class.mdvector.12 = type <{ i32, [4 x i8], i64, i64, %"struct.std::array", %"struct.std::array", %"class.std::vector.13", ptr, i8, [7 x i8] }>
%"struct.std::array" = type { [6 x i32] }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<double *, std::allocator<double *>>::_Vector_impl" }
%"struct.std::_Vector_base<double *, std::allocator<double *>>::_Vector_impl" = type { %"struct.std::_Vector_base<double *, std::allocator<double *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double *, std::allocator<double *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.7" = type { %"struct.std::_Vector_base.8" }
%"struct.std::_Vector_base.8" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.mdvector.5 = type <{ i32, [4 x i8], i64, i64, %"struct.std::array", %"struct.std::array", %"class.std::vector.0", ptr, i8, [7 x i8] }>
%class.mdvector = type <{ i32, [4 x i8], i64, i64, %"struct.std::array", %"struct.std::array", %"class.std::vector", ptr, i8, [7 x i8] }>

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, double noundef) #2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5Hexas16calc_nodal_basisEPdS0_(ptr noundef nonnull align 8 dereferenceable(13968) %0, ptr noundef %1, ptr noundef %2) unnamed_addr #3 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %12 = load ptr, ptr %4, align 8
  %13 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 82
  %14 = call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #4
  %15 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %16 = load i32, ptr %15, align 4, !tbaa !9
  %17 = zext i32 %16 to i64
  %18 = icmp ult i64 %14, %17
  br i1 %18, label %33, label %19

19:                                               ; preds = %3
  %20 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 83
  %21 = call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %20) #4
  %22 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %23 = load i32, ptr %22, align 4, !tbaa !9
  %24 = zext i32 %23 to i64
  %25 = icmp ult i64 %21, %24
  br i1 %25, label %33, label %26

26:                                               ; preds = %19
  %27 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 84
  %28 = call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %27) #4
  %29 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %30 = load i32, ptr %29, align 4, !tbaa !9
  %31 = zext i32 %30 to i64
  %32 = icmp ult i64 %28, %31
  br i1 %32, label %33, label %46

33:                                               ; preds = %26, %19, %3
  %34 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 82
  %35 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %36 = load i32, ptr %35, align 4, !tbaa !9
  %37 = zext i32 %36 to i64
  call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %37)
  %38 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 83
  %39 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %40 = load i32, ptr %39, align 4, !tbaa !9
  %41 = zext i32 %40 to i64
  call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %41)
  %42 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 84
  %43 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %44 = load i32, ptr %43, align 4, !tbaa !9
  %45 = zext i32 %44 to i64
  call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %45)
  br label %46

46:                                               ; preds = %33, %26
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !36
  br label %47

47:                                               ; preds = %84, %46
  %48 = load i32, ptr %7, align 4, !tbaa !36
  %49 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %50 = load i32, ptr %49, align 4, !tbaa !9
  %51 = icmp ult i32 %48, %50
  br i1 %51, label %53, label %52

52:                                               ; preds = %47
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %87

53:                                               ; preds = %47
  %54 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 38
  %55 = load i32, ptr %7, align 4, !tbaa !36
  %56 = load ptr, ptr %5, align 8, !tbaa !5
  %57 = getelementptr inbounds double, ptr %56, i64 0
  %58 = load double, ptr %57, align 8, !tbaa !37
  %59 = call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %54, i32 noundef %55, double noundef %58)
  %60 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 82
  %61 = load i32, ptr %7, align 4, !tbaa !36
  %62 = sext i32 %61 to i64
  %63 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %62) #4
  store double %59, ptr %63, align 8, !tbaa !37
  %64 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 38
  %65 = load i32, ptr %7, align 4, !tbaa !36
  %66 = load ptr, ptr %5, align 8, !tbaa !5
  %67 = getelementptr inbounds double, ptr %66, i64 1
  %68 = load double, ptr %67, align 8, !tbaa !37
  %69 = call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %64, i32 noundef %65, double noundef %68)
  %70 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 83
  %71 = load i32, ptr %7, align 4, !tbaa !36
  %72 = sext i32 %71 to i64
  %73 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %70, i64 noundef %72) #4
  store double %69, ptr %73, align 8, !tbaa !37
  %74 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 38
  %75 = load i32, ptr %7, align 4, !tbaa !36
  %76 = load ptr, ptr %5, align 8, !tbaa !5
  %77 = getelementptr inbounds double, ptr %76, i64 2
  %78 = load double, ptr %77, align 8, !tbaa !37
  %79 = call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %74, i32 noundef %75, double noundef %78)
  %80 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 84
  %81 = load i32, ptr %7, align 4, !tbaa !36
  %82 = sext i32 %81 to i64
  %83 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %80, i64 noundef %82) #4
  store double %79, ptr %83, align 8, !tbaa !37
  br label %84

84:                                               ; preds = %53
  %85 = load i32, ptr %7, align 4, !tbaa !36
  %86 = add nsw i32 %85, 1
  store i32 %86, ptr %7, align 4, !tbaa !36
  br label %47, !llvm.loop !39

87:                                               ; preds = %52
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !36
  br label %88

88:                                               ; preds = %148, %87
  %89 = load i32, ptr %8, align 4, !tbaa !36
  %90 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %91 = load i32, ptr %90, align 4, !tbaa !9
  %92 = icmp ult i32 %89, %91
  br i1 %92, label %94, label %93

93:                                               ; preds = %88
  store i32 5, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %151

94:                                               ; preds = %88
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #4
  store i32 0, ptr %10, align 4, !tbaa !36
  br label %95

95:                                               ; preds = %144, %94
  %96 = load i32, ptr %10, align 4, !tbaa !36
  %97 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %98 = load i32, ptr %97, align 4, !tbaa !9
  %99 = icmp ult i32 %96, %98
  br i1 %99, label %101, label %100

100:                                              ; preds = %95
  store i32 8, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #4
  br label %147

101:                                              ; preds = %95
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  store i32 0, ptr %11, align 4, !tbaa !36
  br label %102

102:                                              ; preds = %140, %101
  %103 = load i32, ptr %11, align 4, !tbaa !36
  %104 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %105 = load i32, ptr %104, align 4, !tbaa !9
  %106 = icmp ult i32 %103, %105
  br i1 %106, label %108, label %107

107:                                              ; preds = %102
  store i32 11, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  br label %143

108:                                              ; preds = %102
  %109 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 82
  %110 = load i32, ptr %11, align 4, !tbaa !36
  %111 = sext i32 %110 to i64
  %112 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %109, i64 noundef %111) #4
  %113 = load double, ptr %112, align 8, !tbaa !37
  %114 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 83
  %115 = load i32, ptr %10, align 4, !tbaa !36
  %116 = sext i32 %115 to i64
  %117 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %114, i64 noundef %116) #4
  %118 = load double, ptr %117, align 8, !tbaa !37
  %119 = fmul double %113, %118
  %120 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 84
  %121 = load i32, ptr %8, align 4, !tbaa !36
  %122 = sext i32 %121 to i64
  %123 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %120, i64 noundef %122) #4
  %124 = load double, ptr %123, align 8, !tbaa !37
  %125 = fmul double %119, %124
  %126 = load ptr, ptr %6, align 8, !tbaa !5
  %127 = load i32, ptr %11, align 4, !tbaa !36
  %128 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %129 = load i32, ptr %128, align 4, !tbaa !9
  %130 = load i32, ptr %10, align 4, !tbaa !36
  %131 = getelementptr inbounds %class.Elements, ptr %12, i32 0, i32 14
  %132 = load i32, ptr %131, align 4, !tbaa !9
  %133 = load i32, ptr %8, align 4, !tbaa !36
  %134 = mul i32 %132, %133
  %135 = add i32 %130, %134
  %136 = mul i32 %129, %135
  %137 = add i32 %127, %136
  %138 = zext i32 %137 to i64
  %139 = getelementptr inbounds double, ptr %126, i64 %138
  store double %125, ptr %139, align 8, !tbaa !37
  br label %140

140:                                              ; preds = %108
  %141 = load i32, ptr %11, align 4, !tbaa !36
  %142 = add nsw i32 %141, 1
  store i32 %142, ptr %11, align 4, !tbaa !36
  br label %102, !llvm.loop !41

143:                                              ; preds = %107
  br label %144

144:                                              ; preds = %143
  %145 = load i32, ptr %10, align 4, !tbaa !36
  %146 = add nsw i32 %145, 1
  store i32 %146, ptr %10, align 4, !tbaa !36
  br label %95, !llvm.loop !42

147:                                              ; preds = %100
  br label %148

148:                                              ; preds = %147
  %149 = load i32, ptr %8, align 4, !tbaa !36
  %150 = add nsw i32 %149, 1
  store i32 %150, ptr %8, align 4, !tbaa !36
  br label %88, !llvm.loop !43

151:                                              ; preds = %93
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 68}
!10 = !{!"_ZTS8Elements", !6, i64 8, !6, i64 16, !11, i64 24, !12, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !12, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !12, i64 92, !12, i64 96, !13, i64 104, !13, i64 216, !13, i64 328, !13, i64 440, !21, i64 552, !13, i64 576, !13, i64 688, !13, i64 800, !13, i64 912, !13, i64 1024, !25, i64 1136, !25, i64 1248, !25, i64 1360, !25, i64 1472, !25, i64 1584, !16, i64 1696, !16, i64 1720, !16, i64 1744, !16, i64 1768, !13, i64 1792, !13, i64 1904, !13, i64 2016, !13, i64 2128, !13, i64 2240, !13, i64 2352, !13, i64 2464, !13, i64 2576, !13, i64 2688, !13, i64 2800, !13, i64 2912, !13, i64 3024, !13, i64 3136, !13, i64 3248, !13, i64 3360, !13, i64 3472, !13, i64 3584, !13, i64 3696, !13, i64 3808, !13, i64 3920, !13, i64 4032, !13, i64 4144, !13, i64 4256, !13, i64 4368, !13, i64 4480, !13, i64 4592, !13, i64 4704, !13, i64 4816, !13, i64 4928, !13, i64 5040, !13, i64 5152, !13, i64 5264, !13, i64 5376, !13, i64 5488, !13, i64 5600, !13, i64 5712, !13, i64 5824, !13, i64 5936, !12, i64 6048, !16, i64 6056, !16, i64 6080, !16, i64 6104, !16, i64 6128, !16, i64 6152, !16, i64 6176, !16, i64 6200, !26, i64 6224, !13, i64 6248, !13, i64 6360, !13, i64 6472, !13, i64 6584, !13, i64 6696, !13, i64 6808, !13, i64 6920, !13, i64 7032, !13, i64 7144, !14, i64 7256, !14, i64 7264, !14, i64 7272, !14, i64 7280, !14, i64 7288, !13, i64 7296, !13, i64 7408, !13, i64 7520, !13, i64 7632, !13, i64 7744, !13, i64 7856, !13, i64 7968, !13, i64 8080, !13, i64 8192, !13, i64 8304, !13, i64 8416, !13, i64 8528, !13, i64 8640, !13, i64 8752, !13, i64 8864, !13, i64 8976, !13, i64 9088, !13, i64 9200, !13, i64 9312, !13, i64 9424, !13, i64 9536, !13, i64 9648, !13, i64 9760, !13, i64 9872, !13, i64 9984, !13, i64 10096, !13, i64 10208, !13, i64 10320, !13, i64 10432, !13, i64 10544, !13, i64 10656, !13, i64 10768, !13, i64 10880, !13, i64 10992, !13, i64 11104, !13, i64 11216, !13, i64 11328, !13, i64 11440, !13, i64 11552, !13, i64 11664, !13, i64 11776, !13, i64 11888, !13, i64 12000, !30, i64 12112, !30, i64 12344, !13, i64 12576, !13, i64 12688, !13, i64 12800, !13, i64 12912, !13, i64 13024, !13, i64 13136, !12, i64 13248, !13, i64 13256, !13, i64 13368, !12, i64 13480, !6, i64 13488, !26, i64 13496, !25, i64 13520, !13, i64 13632, !13, i64 13744, !13, i64 13856}
!11 = !{!"_ZTS8ELE_TYPE", !7, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!"_ZTS8mdvectorIdE", !12, i64 0, !14, i64 8, !14, i64 16, !15, i64 24, !15, i64 48, !16, i64 72, !6, i64 96, !20, i64 104}
!14 = !{!"long", !7, i64 0}
!15 = !{!"_ZTSSt5arrayIjLm6EE", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIdSaIdEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!"_ZTSSt6vectorIjSaIjEE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!25 = !{!"_ZTS8mdvectorIjE", !12, i64 0, !14, i64 8, !14, i64 16, !15, i64 24, !15, i64 48, !21, i64 72, !6, i64 96, !20, i64 104}
!26 = !{!"_ZTSSt6vectorIiSaIiEE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = !{!"_ZTS6mdviewIdE", !31, i64 0, !25, i64 112, !12, i64 224}
!31 = !{!"_ZTS8mdvectorIPdE", !12, i64 0, !14, i64 8, !14, i64 16, !15, i64 24, !15, i64 48, !32, i64 72, !6, i64 96, !20, i64 104}
!32 = !{!"_ZTSSt6vectorIPdSaIS0_EE", !33, i64 0}
!33 = !{!"_ZTSSt12_Vector_baseIPdSaIS0_EE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPdSaIS0_EE12_Vector_implE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseIPdSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!36 = !{!12, !12, i64 0}
!37 = !{!38, !38, i64 0}
!38 = !{!"double", !7, i64 0}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}
!41 = distinct !{!41, !40}
!42 = distinct !{!42, !40}
!43 = distinct !{!43, !40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, double noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN5Hexas16calc_nodal_basisEPdS0_(ptr noundef nonnull align 8 dereferenceable(13968) %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2) unnamed_addr #2 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 6080
  %5 = tail call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %6 = getelementptr inbounds i8, ptr %0, i64 68
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = zext i32 %7 to i64
  %9 = icmp ult i64 %5, %8
  br i1 %9, label %22, label %10

10:                                               ; preds = %3
  %11 = getelementptr inbounds i8, ptr %0, i64 6104
  %12 = tail call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11) #3
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = zext i32 %13 to i64
  %15 = icmp ult i64 %12, %14
  br i1 %15, label %22, label %16

16:                                               ; preds = %10
  %17 = getelementptr inbounds i8, ptr %0, i64 6128
  %18 = tail call noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  %19 = load i32, ptr %6, align 4, !tbaa !5
  %20 = zext i32 %19 to i64
  %21 = icmp ult i64 %18, %20
  br i1 %21, label %22, label %29

22:                                               ; preds = %16, %10, %3
  %.pre-phi = phi i64 [ %20, %16 ], [ %14, %10 ], [ %8, %3 ]
  tail call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %.pre-phi)
  %23 = getelementptr inbounds i8, ptr %0, i64 6104
  %24 = load i32, ptr %6, align 4, !tbaa !5
  %25 = zext i32 %24 to i64
  tail call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %23, i64 noundef %25)
  %26 = getelementptr inbounds i8, ptr %0, i64 6128
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = zext i32 %27 to i64
  tail call void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %28)
  %.pre = load i32, ptr %6, align 4, !tbaa !5
  br label %29

29:                                               ; preds = %22, %16
  %30 = phi i32 [ %.pre, %22 ], [ %19, %16 ]
  %.not = icmp eq i32 %30, 0
  br i1 %.not, label %._crit_edge36, label %.lr.ph

.lr.ph:                                           ; preds = %29
  %31 = getelementptr inbounds i8, ptr %0, i64 1696
  %32 = getelementptr inbounds i8, ptr %1, i64 8
  %33 = getelementptr inbounds i8, ptr %0, i64 6104
  %34 = getelementptr inbounds i8, ptr %1, i64 16
  %35 = getelementptr inbounds i8, ptr %0, i64 6128
  br label %38

.preheader28:                                     ; preds = %38
  %.not37 = icmp eq i32 %49, 0
  br i1 %.not37, label %._crit_edge36, label %.preheader27.preheader

.preheader27.preheader:                           ; preds = %.preheader28
  %36 = getelementptr inbounds i8, ptr %0, i64 6104
  %37 = getelementptr inbounds i8, ptr %0, i64 6128
  br label %.preheader27

38:                                               ; preds = %.lr.ph, %38
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %38 ]
  %39 = load double, ptr %1, align 8, !tbaa !35
  %40 = trunc nuw nsw i64 %indvars.iv to i32
  %41 = tail call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %31, i32 noundef %40, double noundef %39)
  %42 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv) #3
  store double %41, ptr %42, align 8, !tbaa !35
  %43 = load double, ptr %32, align 8, !tbaa !35
  %44 = tail call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %31, i32 noundef %40, double noundef %43)
  %45 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %33, i64 noundef %indvars.iv) #3
  store double %44, ptr %45, align 8, !tbaa !35
  %46 = load double, ptr %34, align 8, !tbaa !35
  %47 = tail call noundef double @_ZL8LagrangeRKSt6vectorIdSaIdEEjd(ptr noundef nonnull align 8 dereferenceable(24) %31, i32 noundef %40, double noundef %46)
  %48 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %35, i64 noundef %indvars.iv) #3
  store double %47, ptr %48, align 8, !tbaa !35
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %49 = load i32, ptr %6, align 4, !tbaa !5
  %50 = zext i32 %49 to i64
  %51 = icmp ult i64 %indvars.iv.next, %50
  br i1 %51, label %38, label %.preheader28, !llvm.loop !37

.preheader27:                                     ; preds = %.preheader27.preheader, %._crit_edge33
  %52 = phi i32 [ %49, %.preheader27.preheader ], [ %57, %._crit_edge33 ]
  %indvars.iv51 = phi i64 [ 0, %.preheader27.preheader ], [ %indvars.iv.next52, %._crit_edge33 ]
  %.not39 = icmp eq i32 %52, 0
  br i1 %.not39, label %._crit_edge33, label %.preheader.preheader

.preheader.preheader:                             ; preds = %.preheader27
  %53 = trunc nuw nsw i64 %indvars.iv51 to i32
  br label %.preheader

._crit_edge36:                                    ; preds = %._crit_edge33, %29, %.preheader28
  ret void

.preheader:                                       ; preds = %.preheader.preheader, %._crit_edge
  %54 = phi i32 [ %52, %.preheader.preheader ], [ %60, %._crit_edge ]
  %55 = phi i32 [ 1, %.preheader.preheader ], [ %61, %._crit_edge ]
  %indvars.iv48 = phi i64 [ 0, %.preheader.preheader ], [ %indvars.iv.next49, %._crit_edge ]
  %.not41 = icmp eq i32 %55, 0
  br i1 %.not41, label %._crit_edge, label %.lr.ph31

.lr.ph31:                                         ; preds = %.preheader
  %56 = trunc nuw nsw i64 %indvars.iv48 to i32
  br label %64

._crit_edge33:                                    ; preds = %._crit_edge, %.preheader27
  %57 = phi i32 [ 0, %.preheader27 ], [ %60, %._crit_edge ]
  %indvars.iv.next52 = add nuw nsw i64 %indvars.iv51, 1
  %58 = zext i32 %57 to i64
  %59 = icmp ult i64 %indvars.iv.next52, %58
  br i1 %59, label %.preheader27, label %._crit_edge36, !llvm.loop !39

._crit_edge:                                      ; preds = %64, %.preheader
  %60 = phi i32 [ %54, %.preheader ], [ %73, %64 ]
  %61 = phi i32 [ 0, %.preheader ], [ %73, %64 ]
  %indvars.iv.next49 = add nuw nsw i64 %indvars.iv48, 1
  %62 = zext i32 %61 to i64
  %63 = icmp ult i64 %indvars.iv.next49, %62
  br i1 %63, label %.preheader, label %._crit_edge33, !llvm.loop !41

64:                                               ; preds = %.lr.ph31, %64
  %indvars.iv45 = phi i64 [ 0, %.lr.ph31 ], [ %indvars.iv.next46, %64 ]
  %65 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %indvars.iv45) #3
  %66 = load double, ptr %65, align 8, !tbaa !35
  %67 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %indvars.iv48) #3
  %68 = load double, ptr %67, align 8, !tbaa !35
  %69 = fmul double %66, %68
  %70 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdSaIdEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %indvars.iv51) #3
  %71 = load double, ptr %70, align 8, !tbaa !35
  %72 = fmul double %69, %71
  %73 = load i32, ptr %6, align 4, !tbaa !5
  %74 = mul i32 %73, %53
  %75 = add i32 %74, %56
  %76 = mul i32 %75, %73
  %77 = trunc nuw nsw i64 %indvars.iv45 to i32
  %78 = add i32 %76, %77
  %79 = zext i32 %78 to i64
  %80 = getelementptr inbounds double, ptr %2, i64 %79
  store double %72, ptr %80, align 8, !tbaa !35
  %indvars.iv.next46 = add nuw nsw i64 %indvars.iv45, 1
  %81 = zext i32 %73 to i64
  %82 = icmp ult i64 %indvars.iv.next46, %81
  br i1 %82, label %64, label %._crit_edge, !llvm.loop !42
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdSaIdEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIdSaIdEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 68}
!6 = !{!"_ZTS8Elements", !7, i64 8, !7, i64 16, !10, i64 24, !11, i64 28, !11, i64 32, !11, i64 36, !11, i64 40, !11, i64 44, !11, i64 48, !11, i64 52, !11, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !11, i64 72, !11, i64 76, !11, i64 80, !11, i64 84, !11, i64 88, !11, i64 92, !11, i64 96, !12, i64 104, !12, i64 216, !12, i64 328, !12, i64 440, !20, i64 552, !12, i64 576, !12, i64 688, !12, i64 800, !12, i64 912, !12, i64 1024, !24, i64 1136, !24, i64 1248, !24, i64 1360, !24, i64 1472, !24, i64 1584, !15, i64 1696, !15, i64 1720, !15, i64 1744, !15, i64 1768, !12, i64 1792, !12, i64 1904, !12, i64 2016, !12, i64 2128, !12, i64 2240, !12, i64 2352, !12, i64 2464, !12, i64 2576, !12, i64 2688, !12, i64 2800, !12, i64 2912, !12, i64 3024, !12, i64 3136, !12, i64 3248, !12, i64 3360, !12, i64 3472, !12, i64 3584, !12, i64 3696, !12, i64 3808, !12, i64 3920, !12, i64 4032, !12, i64 4144, !12, i64 4256, !12, i64 4368, !12, i64 4480, !12, i64 4592, !12, i64 4704, !12, i64 4816, !12, i64 4928, !12, i64 5040, !12, i64 5152, !12, i64 5264, !12, i64 5376, !12, i64 5488, !12, i64 5600, !12, i64 5712, !12, i64 5824, !12, i64 5936, !11, i64 6048, !15, i64 6056, !15, i64 6080, !15, i64 6104, !15, i64 6128, !15, i64 6152, !15, i64 6176, !15, i64 6200, !25, i64 6224, !12, i64 6248, !12, i64 6360, !12, i64 6472, !12, i64 6584, !12, i64 6696, !12, i64 6808, !12, i64 6920, !12, i64 7032, !12, i64 7144, !13, i64 7256, !13, i64 7264, !13, i64 7272, !13, i64 7280, !13, i64 7288, !12, i64 7296, !12, i64 7408, !12, i64 7520, !12, i64 7632, !12, i64 7744, !12, i64 7856, !12, i64 7968, !12, i64 8080, !12, i64 8192, !12, i64 8304, !12, i64 8416, !12, i64 8528, !12, i64 8640, !12, i64 8752, !12, i64 8864, !12, i64 8976, !12, i64 9088, !12, i64 9200, !12, i64 9312, !12, i64 9424, !12, i64 9536, !12, i64 9648, !12, i64 9760, !12, i64 9872, !12, i64 9984, !12, i64 10096, !12, i64 10208, !12, i64 10320, !12, i64 10432, !12, i64 10544, !12, i64 10656, !12, i64 10768, !12, i64 10880, !12, i64 10992, !12, i64 11104, !12, i64 11216, !12, i64 11328, !12, i64 11440, !12, i64 11552, !12, i64 11664, !12, i64 11776, !12, i64 11888, !12, i64 12000, !29, i64 12112, !29, i64 12344, !12, i64 12576, !12, i64 12688, !12, i64 12800, !12, i64 12912, !12, i64 13024, !12, i64 13136, !11, i64 13248, !12, i64 13256, !12, i64 13368, !11, i64 13480, !7, i64 13488, !25, i64 13496, !24, i64 13520, !12, i64 13632, !12, i64 13744, !12, i64 13856}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS8ELE_TYPE", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!"_ZTS8mdvectorIdE", !11, i64 0, !13, i64 8, !13, i64 16, !14, i64 24, !14, i64 48, !15, i64 72, !7, i64 96, !19, i64 104}
!13 = !{!"long", !8, i64 0}
!14 = !{!"_ZTSSt5arrayIjLm6EE", !8, i64 0}
!15 = !{!"_ZTSSt6vectorIdSaIdEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!19 = !{!"bool", !8, i64 0}
!20 = !{!"_ZTSSt6vectorIjSaIjEE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!24 = !{!"_ZTS8mdvectorIjE", !11, i64 0, !13, i64 8, !13, i64 16, !14, i64 24, !14, i64 48, !20, i64 72, !7, i64 96, !19, i64 104}
!25 = !{!"_ZTSSt6vectorIiSaIiEE", !26, i64 0}
!26 = !{!"_ZTSSt12_Vector_baseIiSaIiEE", !27, i64 0}
!27 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE12_Vector_implE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!29 = !{!"_ZTS6mdviewIdE", !30, i64 0, !24, i64 112, !11, i64 224}
!30 = !{!"_ZTS8mdvectorIPdE", !11, i64 0, !13, i64 8, !13, i64 16, !14, i64 24, !14, i64 48, !31, i64 72, !7, i64 96, !19, i64 104}
!31 = !{!"_ZTSSt6vectorIPdSaIS0_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseIPdSaIS0_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseIPdSaIS0_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseIPdSaIS0_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!35 = !{!36, !36, i64 0}
!36 = !{!"double", !8, i64 0}
!37 = distinct !{!37, !38}
!38 = !{!"llvm.loop.mustprogress"}
!39 = distinct !{!39, !38, !40}
!40 = !{!"llvm.loop.unswitch.partial.disable"}
!41 = distinct !{!41, !38, !40}
!42 = distinct !{!42, !38}


; Effective O3 passes: BDCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimpleLoopUnswitchPass,SimplifyCFGPass,TailCallElimPass