; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/Neps Academy (MesaRedondaOBI2019)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }

@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  store i32 0, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  %7 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 4 dereferenceable(4) %2)
  %8 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) %7, ptr noundef nonnull align 4 dereferenceable(4) %3)
  br label %9

9:                                                ; preds = %19, %0
  %10 = load i32, ptr %2, align 4, !tbaa !5
  %11 = add nsw i32 %10, -1
  store i32 %11, ptr %2, align 4, !tbaa !5
  %12 = icmp ne i32 %10, 0
  br i1 %12, label %13, label %20

13:                                               ; preds = %9
  %14 = load i32, ptr %4, align 4, !tbaa !5
  %15 = add nsw i32 %14, 1
  store i32 %15, ptr %4, align 4, !tbaa !5
  %16 = load i32, ptr %4, align 4, !tbaa !5
  %17 = icmp sgt i32 %16, 2
  br i1 %17, label %18, label %19

18:                                               ; preds = %13
  store i32 0, ptr %4, align 4, !tbaa !5
  br label %19

19:                                               ; preds = %18, %13
  br label %9, !llvm.loop !9

20:                                               ; preds = %9
  br label %21

21:                                               ; preds = %31, %20
  %22 = load i32, ptr %3, align 4, !tbaa !5
  %23 = add nsw i32 %22, -1
  store i32 %23, ptr %3, align 4, !tbaa !5
  %24 = icmp ne i32 %22, 0
  br i1 %24, label %25, label %32

25:                                               ; preds = %21
  %26 = load i32, ptr %5, align 4, !tbaa !5
  %27 = add nsw i32 %26, 1
  store i32 %27, ptr %5, align 4, !tbaa !5
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = icmp sgt i32 %28, 2
  br i1 %29, label %30, label %31

30:                                               ; preds = %25
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %31

31:                                               ; preds = %30, %25
  br label %21, !llvm.loop !11

32:                                               ; preds = %21
  %33 = load i32, ptr %5, align 4, !tbaa !5
  %34 = load i32, ptr %4, align 4, !tbaa !5
  %35 = icmp eq i32 %33, %34
  br i1 %35, label %36, label %43

36:                                               ; preds = %32
  %37 = load i32, ptr %5, align 4, !tbaa !5
  %38 = add nsw i32 %37, 1
  store i32 %38, ptr %5, align 4, !tbaa !5
  %39 = load i32, ptr %5, align 4, !tbaa !5
  %40 = icmp sgt i32 %39, 2
  br i1 %40, label %41, label %42

41:                                               ; preds = %36
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %42

42:                                               ; preds = %41, %36
  br label %43

43:                                               ; preds = %42, %32
  store i32 0, ptr %6, align 4, !tbaa !5
  br label %44

44:                                               ; preds = %54, %43
  %45 = load i32, ptr %6, align 4, !tbaa !5
  %46 = load i32, ptr %4, align 4, !tbaa !5
  %47 = icmp eq i32 %45, %46
  br i1 %47, label %52, label %48

48:                                               ; preds = %44
  %49 = load i32, ptr %5, align 4, !tbaa !5
  %50 = load i32, ptr %6, align 4, !tbaa !5
  %51 = icmp eq i32 %49, %50
  br label %52

52:                                               ; preds = %48, %44
  %53 = phi i1 [ true, %44 ], [ %51, %48 ]
  br i1 %53, label %54, label %57

54:                                               ; preds = %52
  %55 = load i32, ptr %6, align 4, !tbaa !5
  %56 = add nsw i32 %55, 1
  store i32 %56, ptr %6, align 4, !tbaa !5
  br label %44, !llvm.loop !12

57:                                               ; preds = %52
  %58 = load i32, ptr %6, align 4, !tbaa !5
  %59 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %58)
  %60 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %59, ptr noundef @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #5
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4)) #2

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }

@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #5
  %3 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 4 dereferenceable(4) %1)
  %4 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16) %3, ptr noundef nonnull align 4 dereferenceable(4) %2)
  %.promoted = load i32, ptr %1, align 4, !tbaa !5
  %.not19 = icmp eq i32 %.promoted, 0
  br i1 %.not19, label %.preheader, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %0
  %xtraiter = and i32 %.promoted, 3
  %5 = icmp ult i32 %.promoted, 4
  br i1 %5, label %.preheader.loopexit.unr-lcssa, label %.lr.ph.preheader.new

.lr.ph.preheader.new:                             ; preds = %.lr.ph.preheader
  %unroll_iter = and i32 %.promoted, -4
  br label %.lr.ph

.preheader.loopexit.unr-lcssa:                    ; preds = %.lr.ph, %.lr.ph.preheader
  %spec.store.select.lcssa.ph = phi i32 [ poison, %.lr.ph.preheader ], [ %spec.store.select.3, %.lr.ph ]
  %.01720.unr = phi i32 [ 0, %.lr.ph.preheader ], [ %spec.store.select.3, %.lr.ph ]
  %lcmp.mod.not = icmp eq i32 %xtraiter, 0
  br i1 %lcmp.mod.not, label %.preheader, label %.lr.ph.epil

.lr.ph.epil:                                      ; preds = %.preheader.loopexit.unr-lcssa, %.lr.ph.epil
  %.01720.epil = phi i32 [ %spec.store.select.epil, %.lr.ph.epil ], [ %.01720.unr, %.preheader.loopexit.unr-lcssa ]
  %epil.iter = phi i32 [ %epil.iter.next, %.lr.ph.epil ], [ 0, %.preheader.loopexit.unr-lcssa ]
  %6 = add nsw i32 %.01720.epil, 1
  %7 = icmp sgt i32 %.01720.epil, 1
  %spec.store.select.epil = select i1 %7, i32 0, i32 %6
  %epil.iter.next = add i32 %epil.iter, 1
  %epil.iter.cmp.not = icmp eq i32 %epil.iter.next, %xtraiter
  br i1 %epil.iter.cmp.not, label %.preheader, label %.lr.ph.epil, !llvm.loop !9

.preheader:                                       ; preds = %.preheader.loopexit.unr-lcssa, %.lr.ph.epil, %0
  %.017.lcssa = phi i32 [ 0, %0 ], [ %spec.store.select.lcssa.ph, %.preheader.loopexit.unr-lcssa ], [ %spec.store.select.epil, %.lr.ph.epil ]
  store i32 -1, ptr %1, align 4, !tbaa !5
  %.promoted22 = load i32, ptr %2, align 4, !tbaa !5
  %.not1824 = icmp eq i32 %.promoted22, 0
  br i1 %.not1824, label %._crit_edge.thread, label %.lr.ph26.preheader

.lr.ph26.preheader:                               ; preds = %.preheader
  %xtraiter36 = and i32 %.promoted22, 3
  %8 = icmp ult i32 %.promoted22, 4
  br i1 %8, label %._crit_edge.unr-lcssa, label %.lr.ph26.preheader.new

.lr.ph26.preheader.new:                           ; preds = %.lr.ph26.preheader
  %unroll_iter40 = and i32 %.promoted22, -4
  br label %.lr.ph26

._crit_edge.thread:                               ; preds = %.preheader
  store i32 -1, ptr %2, align 4, !tbaa !5
  %9 = icmp eq i32 %.017.lcssa, 0
  br label %31

.lr.ph:                                           ; preds = %.lr.ph, %.lr.ph.preheader.new
  %.01720 = phi i32 [ 0, %.lr.ph.preheader.new ], [ %spec.store.select.3, %.lr.ph ]
  %niter = phi i32 [ 0, %.lr.ph.preheader.new ], [ %niter.next.3, %.lr.ph ]
  %10 = add nsw i32 %.01720, 1
  %11 = icmp sgt i32 %.01720, 1
  %spec.store.select = select i1 %11, i32 0, i32 %10
  %12 = add nsw i32 %spec.store.select, 1
  %13 = icmp sgt i32 %spec.store.select, 1
  %spec.store.select.1 = select i1 %13, i32 0, i32 %12
  %14 = add nsw i32 %spec.store.select.1, 1
  %15 = icmp sgt i32 %spec.store.select.1, 1
  %spec.store.select.2 = select i1 %15, i32 0, i32 %14
  %16 = add nsw i32 %spec.store.select.2, 1
  %17 = icmp sgt i32 %spec.store.select.2, 1
  %spec.store.select.3 = select i1 %17, i32 0, i32 %16
  %niter.next.3 = add i32 %niter, 4
  %niter.ncmp.3 = icmp eq i32 %niter.next.3, %unroll_iter
  br i1 %niter.ncmp.3, label %.preheader.loopexit.unr-lcssa, label %.lr.ph, !llvm.loop !11

.lr.ph26:                                         ; preds = %.lr.ph26, %.lr.ph26.preheader.new
  %.01625 = phi i32 [ 0, %.lr.ph26.preheader.new ], [ %spec.store.select1.3, %.lr.ph26 ]
  %niter41 = phi i32 [ 0, %.lr.ph26.preheader.new ], [ %niter41.next.3, %.lr.ph26 ]
  %18 = add i32 %.01625, 1
  %19 = icmp sgt i32 %.01625, 1
  %spec.store.select1 = select i1 %19, i32 0, i32 %18
  %20 = add i32 %spec.store.select1, 1
  %21 = icmp sgt i32 %spec.store.select1, 1
  %spec.store.select1.1 = select i1 %21, i32 0, i32 %20
  %22 = add i32 %spec.store.select1.1, 1
  %23 = icmp sgt i32 %spec.store.select1.1, 1
  %spec.store.select1.2 = select i1 %23, i32 0, i32 %22
  %24 = add i32 %spec.store.select1.2, 1
  %25 = icmp sgt i32 %spec.store.select1.2, 1
  %spec.store.select1.3 = select i1 %25, i32 0, i32 %24
  %niter41.next.3 = add i32 %niter41, 4
  %niter41.ncmp.3 = icmp eq i32 %niter41.next.3, %unroll_iter40
  br i1 %niter41.ncmp.3, label %._crit_edge.unr-lcssa, label %.lr.ph26, !llvm.loop !13

._crit_edge.unr-lcssa:                            ; preds = %.lr.ph26, %.lr.ph26.preheader
  %spec.store.select1.lcssa.ph = phi i32 [ poison, %.lr.ph26.preheader ], [ %spec.store.select1.3, %.lr.ph26 ]
  %.01625.unr = phi i32 [ 0, %.lr.ph26.preheader ], [ %spec.store.select1.3, %.lr.ph26 ]
  %lcmp.mod38.not = icmp eq i32 %xtraiter36, 0
  br i1 %lcmp.mod38.not, label %._crit_edge, label %.lr.ph26.epil

.lr.ph26.epil:                                    ; preds = %._crit_edge.unr-lcssa, %.lr.ph26.epil
  %.01625.epil = phi i32 [ %spec.store.select1.epil, %.lr.ph26.epil ], [ %.01625.unr, %._crit_edge.unr-lcssa ]
  %epil.iter37 = phi i32 [ %epil.iter37.next, %.lr.ph26.epil ], [ 0, %._crit_edge.unr-lcssa ]
  %26 = add i32 %.01625.epil, 1
  %27 = icmp sgt i32 %.01625.epil, 1
  %spec.store.select1.epil = select i1 %27, i32 0, i32 %26
  %epil.iter37.next = add i32 %epil.iter37, 1
  %epil.iter37.cmp.not = icmp eq i32 %epil.iter37.next, %xtraiter36
  br i1 %epil.iter37.cmp.not, label %._crit_edge, label %.lr.ph26.epil, !llvm.loop !14

._crit_edge:                                      ; preds = %.lr.ph26.epil, %._crit_edge.unr-lcssa
  %spec.store.select1.lcssa = phi i32 [ %spec.store.select1.lcssa.ph, %._crit_edge.unr-lcssa ], [ %spec.store.select1.epil, %.lr.ph26.epil ]
  store i32 -1, ptr %2, align 4, !tbaa !5
  %28 = icmp eq i32 %spec.store.select1.lcssa, %.017.lcssa
  %29 = add nsw i32 %spec.store.select1.lcssa, 1
  %30 = icmp sgt i32 %spec.store.select1.lcssa, 1
  %spec.select = select i1 %30, i32 0, i32 %29
  br label %31

31:                                               ; preds = %._crit_edge, %._crit_edge.thread
  %32 = phi i1 [ %9, %._crit_edge.thread ], [ %28, %._crit_edge ]
  %.016.lcssa34 = phi i32 [ 0, %._crit_edge.thread ], [ %spec.store.select1.lcssa, %._crit_edge ]
  %33 = phi i32 [ 1, %._crit_edge.thread ], [ %spec.select, %._crit_edge ]
  %.1 = select i1 %32, i32 %33, i32 %.016.lcssa34
  br label %34

34:                                               ; preds = %34, %31
  %.0 = phi i32 [ 0, %31 ], [ %38, %34 ]
  %35 = icmp eq i32 %.0, %.017.lcssa
  %36 = icmp eq i32 %.1, %.0
  %37 = select i1 %35, i1 true, i1 %36
  %38 = add nuw nsw i32 %.0, 1
  br i1 %37, label %34, label %39, !llvm.loop !15

39:                                               ; preds = %34
  %40 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i32 noundef %.0)
  %41 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8) %40, ptr noundef nonnull @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1) #5
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERi(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEi(ptr noundef nonnull align 8 dereferenceable(8), i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEPFRSoS_E(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.unroll.disable"}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !10}
!15 = distinct !{!15, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass