; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/Neps Academy/Produto do Intervalo/main.ll (Z6updateiiiix)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@st = external dso_local global %"class.std::vector", align 8
@a = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updateiiiix(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i64 noundef %4) #2 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i64, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i32 %2, ptr %8, align 4, !tbaa !5
  store i32 %3, ptr %9, align 4, !tbaa !5
  store i64 %4, ptr %10, align 8, !tbaa !9
  %14 = load i32, ptr %7, align 4, !tbaa !5
  %15 = load i32, ptr %8, align 4, !tbaa !5
  %16 = icmp eq i32 %14, %15
  br i1 %16, label %17, label %26

17:                                               ; preds = %5
  %18 = load i64, ptr %10, align 8, !tbaa !9
  %19 = load i32, ptr %6, align 4, !tbaa !5
  %20 = sext i32 %19 to i64
  %21 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %20) #3
  store i64 %18, ptr %21, align 8, !tbaa !9
  %22 = load i64, ptr %10, align 8, !tbaa !9
  %23 = load i32, ptr %9, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @a, i64 noundef %24) #3
  store i64 %22, ptr %25, align 8, !tbaa !9
  br label %66

26:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %27 = load i32, ptr %7, align 4, !tbaa !5
  %28 = load i32, ptr %8, align 4, !tbaa !5
  %29 = add nsw i32 %27, %28
  %30 = ashr i32 %29, 1
  store i32 %30, ptr %11, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %31 = load i32, ptr %6, align 4, !tbaa !5
  %32 = mul nsw i32 %31, 2
  store i32 %32, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %33 = load i32, ptr %6, align 4, !tbaa !5
  %34 = mul nsw i32 %33, 2
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %13, align 4, !tbaa !5
  %36 = load i32, ptr %9, align 4, !tbaa !5
  %37 = load i32, ptr %11, align 4, !tbaa !5
  %38 = icmp sle i32 %36, %37
  br i1 %38, label %39, label %45

39:                                               ; preds = %26
  %40 = load i32, ptr %12, align 4, !tbaa !5
  %41 = load i32, ptr %7, align 4, !tbaa !5
  %42 = load i32, ptr %11, align 4, !tbaa !5
  %43 = load i32, ptr %9, align 4, !tbaa !5
  %44 = load i64, ptr %10, align 8, !tbaa !9
  call void @_Z6updateiiiix(i32 noundef %40, i32 noundef %41, i32 noundef %42, i32 noundef %43, i64 noundef %44)
  br label %52

45:                                               ; preds = %26
  %46 = load i32, ptr %13, align 4, !tbaa !5
  %47 = load i32, ptr %11, align 4, !tbaa !5
  %48 = add nsw i32 %47, 1
  %49 = load i32, ptr %8, align 4, !tbaa !5
  %50 = load i32, ptr %9, align 4, !tbaa !5
  %51 = load i64, ptr %10, align 8, !tbaa !9
  call void @_Z6updateiiiix(i32 noundef %46, i32 noundef %48, i32 noundef %49, i32 noundef %50, i64 noundef %51)
  br label %52

52:                                               ; preds = %45, %39
  %53 = load i32, ptr %12, align 4, !tbaa !5
  %54 = sext i32 %53 to i64
  %55 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %54) #3
  %56 = load i64, ptr %55, align 8, !tbaa !9
  %57 = load i32, ptr %13, align 4, !tbaa !5
  %58 = sext i32 %57 to i64
  %59 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %58) #3
  %60 = load i64, ptr %59, align 8, !tbaa !9
  %61 = mul nsw i64 %56, %60
  %62 = srem i64 %61, 1000000007
  %63 = load i32, ptr %6, align 4, !tbaa !5
  %64 = sext i32 %63 to i64
  %65 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %64) #3
  store i64 %62, ptr %65, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %66

66:                                               ; preds = %52, %17
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@st = external dso_local global %"class.std::vector", align 8
@a = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updateiiiix(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i64 noundef %4) local_unnamed_addr #0 {
  %6 = icmp eq i32 %1, %2
  br i1 %6, label %7, label %10

7:                                                ; preds = %5
  %8 = sext i32 %0 to i64
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %8) #1
  store i64 %4, ptr %9, align 8, !tbaa !5
  br label %27

10:                                               ; preds = %5
  %11 = add nsw i32 %2, %1
  %12 = ashr i32 %11, 1
  %13 = shl nsw i32 %0, 1
  %14 = or disjoint i32 %13, 1
  %.not = icmp slt i32 %12, %3
  br i1 %.not, label %16, label %15

15:                                               ; preds = %10
  tail call void @_Z6updateiiiix(i32 noundef %13, i32 noundef %1, i32 noundef %12, i32 noundef %3, i64 noundef %4)
  br label %18

16:                                               ; preds = %10
  %17 = add nsw i32 %12, 1
  tail call void @_Z6updateiiiix(i32 noundef %14, i32 noundef %17, i32 noundef %2, i32 noundef %3, i64 noundef %4)
  br label %18

18:                                               ; preds = %16, %15
  %19 = sext i32 %13 to i64
  %20 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %19) #1
  %21 = load i64, ptr %20, align 8, !tbaa !5
  %22 = sext i32 %14 to i64
  %23 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %22) #1
  %24 = load i64, ptr %23, align 8, !tbaa !5
  %25 = mul nsw i64 %24, %21
  %26 = srem i64 %25, 1000000007
  br label %27

27:                                               ; preds = %18, %7
  %.sink31 = phi i32 [ %0, %18 ], [ %3, %7 ]
  %st.sink = phi ptr [ @st, %18 ], [ @a, %7 ]
  %.sink = phi i64 [ %26, %18 ], [ %4, %7 ]
  %28 = sext i32 %.sink31 to i64
  %29 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %st.sink, i64 noundef %28) #1
  store i64 %.sink, ptr %29, align 8, !tbaa !5
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass