; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/DH (uart)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @dh_uart_init(i32 noundef %0, i32 noundef %1, i8 noundef signext %2, i32 noundef %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  store i32 %0, ptr %6, align 4, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !5
  store i8 %2, ptr %8, align 1, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !5
  %10 = load i32, ptr %6, align 4, !tbaa !5
  %11 = icmp slt i32 %10, 300
  br i1 %11, label %15, label %12

12:                                               ; preds = %4
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = icmp sgt i32 %13, 230400
  br i1 %14, label %15, label %16

15:                                               ; preds = %12, %4
  store i32 -1, ptr %5, align 4
  br label %95

16:                                               ; preds = %12
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = icmp slt i32 %17, 5
  br i1 %18, label %22, label %19

19:                                               ; preds = %16
  %20 = load i32, ptr %7, align 4, !tbaa !5
  %21 = icmp sgt i32 %20, 8
  br i1 %21, label %22, label %23

22:                                               ; preds = %19, %16
  store i32 -1, ptr %5, align 4
  br label %95

23:                                               ; preds = %19
  %24 = load i8, ptr %8, align 1, !tbaa !9
  %25 = sext i8 %24 to i32
  %26 = icmp ne i32 %25, 78
  br i1 %26, label %27, label %36

27:                                               ; preds = %23
  %28 = load i8, ptr %8, align 1, !tbaa !9
  %29 = sext i8 %28 to i32
  %30 = icmp ne i32 %29, 79
  br i1 %30, label %31, label %36

31:                                               ; preds = %27
  %32 = load i8, ptr %8, align 1, !tbaa !9
  %33 = sext i8 %32 to i32
  %34 = icmp ne i32 %33, 69
  br i1 %34, label %35, label %36

35:                                               ; preds = %31
  store i32 -1, ptr %5, align 4
  br label %95

36:                                               ; preds = %31, %27, %23
  %37 = load i32, ptr %9, align 4, !tbaa !5
  %38 = icmp slt i32 %37, 1
  br i1 %38, label %42, label %39

39:                                               ; preds = %36
  %40 = load i32, ptr %9, align 4, !tbaa !5
  %41 = icmp sgt i32 %40, 2
  br i1 %41, label %42, label %43

42:                                               ; preds = %39, %36
  store i32 -1, ptr %5, align 4
  br label %95

43:                                               ; preds = %39
  call void @ets_isr_mask(i32 noundef 32)
  br label %44

44:                                               ; preds = %43
  %45 = load volatile i32, ptr inttoptr (i64 1610614808 to ptr), align 4, !tbaa !5
  %46 = and i32 %45, -305
  %47 = or i32 %46, 0
  store volatile i32 %47, ptr inttoptr (i64 1610614808 to ptr), align 4, !tbaa !5
  br label %48

48:                                               ; preds = %44
  call void @gpio_output_set(i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 10)
  %49 = load volatile i32, ptr inttoptr (i64 1610614804 to ptr), align 4, !tbaa !5
  %50 = or i32 %49, 128
  store volatile i32 %50, ptr inttoptr (i64 1610614804 to ptr), align 4, !tbaa !5
  %51 = load volatile i32, ptr inttoptr (i64 1610614808 to ptr), align 4, !tbaa !5
  %52 = and i32 %51, -129
  store volatile i32 %52, ptr inttoptr (i64 1610614808 to ptr), align 4, !tbaa !5
  %53 = load i32, ptr %6, align 4, !tbaa !5
  %54 = sdiv i32 80000000, %53
  store volatile i32 %54, ptr inttoptr (i64 1610612756 to ptr), align 4, !tbaa !5
  store volatile i32 0, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %55 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %56 = load i8, ptr %8, align 1, !tbaa !9
  %57 = sext i8 %56 to i32
  %58 = icmp eq i32 %57, 69
  %59 = zext i1 %58 to i64
  %60 = select i1 %58, i32 0, i32 1
  %61 = shl i32 %60, 0
  %62 = or i32 %55, %61
  store volatile i32 %62, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %63 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %64 = load i8, ptr %8, align 1, !tbaa !9
  %65 = sext i8 %64 to i32
  %66 = icmp eq i32 %65, 78
  %67 = zext i1 %66 to i64
  %68 = select i1 %66, i32 0, i32 1
  %69 = shl i32 %68, 1
  %70 = or i32 %63, %69
  store volatile i32 %70, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %71 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %72 = load i32, ptr %7, align 4, !tbaa !5
  %73 = sub nsw i32 %72, 5
  %74 = shl i32 %73, 2
  %75 = or i32 %71, %74
  store volatile i32 %75, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %76 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %77 = load i32, ptr %9, align 4, !tbaa !5
  %78 = icmp eq i32 %77, 2
  %79 = zext i1 %78 to i64
  %80 = select i1 %78, i32 3, i32 1
  %81 = shl i32 %80, 4
  %82 = or i32 %76, %81
  store volatile i32 %82, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %83 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %84 = zext i32 %83 to i64
  %85 = or i64 %84, 393216
  %86 = trunc i64 %85 to i32
  store volatile i32 %86, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %87 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  %88 = zext i32 %87 to i64
  %89 = and i64 %88, -393217
  %90 = trunc i64 %89 to i32
  store volatile i32 %90, ptr inttoptr (i64 1610612768 to ptr), align 4, !tbaa !5
  store volatile i32 8454145, ptr inttoptr (i64 1610612772 to ptr), align 4, !tbaa !5
  call void @ets_isr_attach(i32 noundef 5, ptr noundef @int_cb, ptr noundef null)
  store volatile i32 65535, ptr inttoptr (i64 1610612752 to ptr), align 4, !tbaa !5
  %91 = load volatile i32, ptr inttoptr (i64 1610612748 to ptr), align 4, !tbaa !5
  %92 = zext i32 %91 to i64
  %93 = or i64 %92, 1
  %94 = trunc i64 %93 to i32
  store volatile i32 %94, ptr inttoptr (i64 1610612748 to ptr), align 4, !tbaa !5
  call void @ets_isr_unmask(i32 noundef 32)
  store i32 0, ptr %5, align 4
  br label %95

95:                                               ; preds = %48, %42, %35, %22, %15
  %96 = load i32, ptr %5, align 4
  ret i32 %96
}

declare void @ets_isr_mask(i32 noundef) #1

declare void @gpio_output_set(i32 noundef, i32 noundef, i32 noundef, i32 noundef) #1

declare void @ets_isr_attach(i32 noundef, ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden void @int_cb(ptr noundef) #0

declare void @ets_isr_unmask(i32 noundef) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @dh_uart_init(i32 noundef %0, i32 noundef %1, i8 noundef signext %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = add i32 %0, -230401
  %or.cond = icmp ult i32 %5, -230101
  %6 = add i32 %1, -9
  %or.cond3 = icmp ult i32 %6, -4
  %or.cond29 = or i1 %or.cond, %or.cond3
  br i1 %or.cond29, label %39, label %7

7:                                                ; preds = %4
  switch i8 %2, label %39 [
    i8 79, label %8
    i8 78, label %8
    i8 69, label %8
  ]

8:                                                ; preds = %7, %7, %7
  %9 = add i32 %3, -3
  %or.cond11 = icmp ult i32 %9, -2
  br i1 %or.cond11, label %39, label %10

10:                                               ; preds = %8
  tail call void @ets_isr_mask(i32 noundef 32) #2
  %11 = load volatile i32, ptr inttoptr (i64 1610614808 to ptr), align 8, !tbaa !5
  %12 = and i32 %11, -305
  store volatile i32 %12, ptr inttoptr (i64 1610614808 to ptr), align 8, !tbaa !5
  tail call void @gpio_output_set(i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 10) #2
  %13 = load volatile i32, ptr inttoptr (i64 1610614804 to ptr), align 4, !tbaa !5
  %14 = or i32 %13, 128
  store volatile i32 %14, ptr inttoptr (i64 1610614804 to ptr), align 4, !tbaa !5
  %15 = load volatile i32, ptr inttoptr (i64 1610614808 to ptr), align 8, !tbaa !5
  %16 = and i32 %15, -129
  store volatile i32 %16, ptr inttoptr (i64 1610614808 to ptr), align 8, !tbaa !5
  %17 = udiv i32 80000000, %0
  store volatile i32 %17, ptr inttoptr (i64 1610612756 to ptr), align 4, !tbaa !5
  store volatile i32 0, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %18 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %19 = icmp ne i8 %2, 69
  %20 = zext i1 %19 to i32
  %21 = or i32 %18, %20
  store volatile i32 %21, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %22 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %.not = icmp eq i8 %2, 78
  %23 = select i1 %.not, i32 0, i32 2
  %24 = or i32 %22, %23
  store volatile i32 %24, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %25 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %26 = shl nuw nsw i32 %1, 2
  %27 = add nsw i32 %26, -20
  %28 = or i32 %25, %27
  store volatile i32 %28, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %29 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %30 = icmp eq i32 %3, 2
  %31 = select i1 %30, i32 48, i32 16
  %32 = or i32 %29, %31
  store volatile i32 %32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %33 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %34 = or i32 %33, 393216
  store volatile i32 %34, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %35 = load volatile i32, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  %36 = and i32 %35, -393217
  store volatile i32 %36, ptr inttoptr (i64 1610612768 to ptr), align 32, !tbaa !5
  store volatile i32 8454145, ptr inttoptr (i64 1610612772 to ptr), align 4, !tbaa !5
  tail call void @ets_isr_attach(i32 noundef 5, ptr noundef nonnull @int_cb, ptr noundef null) #2
  store volatile i32 65535, ptr inttoptr (i64 1610612752 to ptr), align 16, !tbaa !5
  %37 = load volatile i32, ptr inttoptr (i64 1610612748 to ptr), align 4, !tbaa !5
  %38 = or i32 %37, 1
  store volatile i32 %38, ptr inttoptr (i64 1610612748 to ptr), align 4, !tbaa !5
  tail call void @ets_isr_unmask(i32 noundef 32) #2
  br label %39

39:                                               ; preds = %8, %7, %4, %10
  %.0 = phi i32 [ 0, %10 ], [ -1, %4 ], [ -1, %7 ], [ -1, %8 ]
  ret i32 %.0
}

declare void @ets_isr_mask(i32 noundef) local_unnamed_addr #1

declare void @gpio_output_set(i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @ets_isr_attach(i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare hidden void @int_cb(ptr noundef) #0

declare void @ets_isr_unmask(i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass