; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/CSES/CountingRooms.ll (Z3dfsii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vi = external dso_local global %"class.std::vector.0", align 8
@n = external dso_local global i32, align 4
@m = external dso_local global i32, align 4
@__const._Z3dfsii.row = external hidden unnamed_addr constant [4 x i32], align 16
@__const._Z3dfsii.col = external hidden unnamed_addr constant [4 x i32], align 16

; Function Attrs: mustprogress uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca [4 x i32], align 16
  %6 = alloca [4 x i32], align 16
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = sext i32 %10 to i64
  %12 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %11) #4
  %13 = load i32, ptr %4, align 4, !tbaa !5
  %14 = sext i32 %13 to i64
  %15 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %14) #4
  store i32 1, ptr %15, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr %5) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %5, ptr align 16 @__const._Z3dfsii.row, i64 16, i1 false)
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 16 %6, ptr align 16 @__const._Z3dfsii.col, i64 16, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !5
  br label %16

16:                                               ; preds = %70, %2
  %17 = load i32, ptr %7, align 4, !tbaa !5
  %18 = icmp slt i32 %17, 4
  br i1 %18, label %20, label %19

19:                                               ; preds = %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %73

20:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %21 = load i32, ptr %7, align 4, !tbaa !5
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds [4 x i32], ptr %5, i64 0, i64 %22
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %25 = load i32, ptr %3, align 4, !tbaa !5
  %26 = add nsw i32 %24, %25
  store i32 %26, ptr %8, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %27 = load i32, ptr %7, align 4, !tbaa !5
  %28 = sext i32 %27 to i64
  %29 = getelementptr inbounds [4 x i32], ptr %6, i64 0, i64 %28
  %30 = load i32, ptr %29, align 4, !tbaa !5
  %31 = load i32, ptr %4, align 4, !tbaa !5
  %32 = add nsw i32 %30, %31
  store i32 %32, ptr %9, align 4, !tbaa !5
  %33 = load i32, ptr %8, align 4, !tbaa !5
  %34 = icmp sge i32 %33, 0
  br i1 %34, label %35, label %69

35:                                               ; preds = %20
  %36 = load i32, ptr %8, align 4, !tbaa !5
  %37 = load i32, ptr @n, align 4, !tbaa !5
  %38 = icmp slt i32 %36, %37
  br i1 %38, label %39, label %69

39:                                               ; preds = %35
  %40 = load i32, ptr %9, align 4, !tbaa !5
  %41 = icmp sge i32 %40, 0
  br i1 %41, label %42, label %69

42:                                               ; preds = %39
  %43 = load i32, ptr %9, align 4, !tbaa !5
  %44 = load i32, ptr @m, align 4, !tbaa !5
  %45 = icmp slt i32 %43, %44
  br i1 %45, label %46, label %69

46:                                               ; preds = %42
  %47 = load i32, ptr %8, align 4, !tbaa !5
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %48) #4
  %50 = load i32, ptr %9, align 4, !tbaa !5
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %51) #4
  %53 = load i32, ptr %52, align 4, !tbaa !5
  %54 = icmp ne i32 %53, 0
  br i1 %54, label %68, label %55

55:                                               ; preds = %46
  %56 = load i32, ptr %8, align 4, !tbaa !5
  %57 = sext i32 %56 to i64
  %58 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %57) #4
  %59 = load i32, ptr %9, align 4, !tbaa !5
  %60 = sext i32 %59 to i64
  %61 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %58, i64 noundef %60) #4
  %62 = load i8, ptr %61, align 1, !tbaa !9
  %63 = sext i8 %62 to i32
  %64 = icmp eq i32 %63, 46
  br i1 %64, label %65, label %68

65:                                               ; preds = %55
  %66 = load i32, ptr %8, align 4, !tbaa !5
  %67 = load i32, ptr %9, align 4, !tbaa !5
  call void @_Z3dfsii(i32 noundef %66, i32 noundef %67)
  br label %68

68:                                               ; preds = %65, %55, %46
  br label %69

69:                                               ; preds = %68, %42, %39, %35, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %70

70:                                               ; preds = %69
  %71 = load i32, ptr %7, align 4, !tbaa !5
  %72 = add nsw i32 %71, 1
  store i32 %72, ptr %7, align 4, !tbaa !5
  br label %16, !llvm.loop !10

73:                                               ; preds = %19
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %5) #4
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<char>, std::allocator<std::vector<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@v = external dso_local global %"class.std::vector", align 8
@vi = external dso_local global %"class.std::vector.0", align 8
@n = external dso_local local_unnamed_addr global i32, align 4
@m = external dso_local local_unnamed_addr global i32, align 4
@__const._Z3dfsii.row = external hidden unnamed_addr constant [4 x i32], align 16
@__const._Z3dfsii.col = external hidden unnamed_addr constant [4 x i32], align 16

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z3dfsii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  br label %tailrecurse

tailrecurse:                                      ; preds = %96, %2
  %.tr = phi i32 [ %0, %2 ], [ %80, %96 ]
  %.tr25 = phi i32 [ %1, %2 ], [ %82, %96 ]
  %3 = sext i32 %.tr to i64
  %4 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %3) #1
  %5 = sext i32 %.tr25 to i64
  %6 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %5) #1
  store i32 1, ptr %6, align 4, !tbaa !5
  %7 = load i32, ptr @__const._Z3dfsii.row, align 16, !tbaa !5
  %8 = add nsw i32 %7, %.tr
  %9 = load i32, ptr @__const._Z3dfsii.col, align 16, !tbaa !5
  %10 = add nsw i32 %9, %.tr25
  %11 = icmp sgt i32 %8, -1
  br i1 %11, label %12, label %30

12:                                               ; preds = %tailrecurse
  %13 = load i32, ptr @n, align 4, !tbaa !5
  %14 = icmp slt i32 %8, %13
  %15 = icmp sgt i32 %10, -1
  %or.cond = select i1 %14, i1 %15, i1 false
  %16 = load i32, ptr @m, align 4
  %17 = icmp slt i32 %10, %16
  %or.cond22 = select i1 %or.cond, i1 %17, i1 false
  br i1 %or.cond22, label %18, label %30

18:                                               ; preds = %12
  %19 = zext nneg i32 %8 to i64
  %20 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %19) #1
  %21 = zext nneg i32 %10 to i64
  %22 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %21) #1
  %23 = load i32, ptr %22, align 4, !tbaa !5
  %.not = icmp eq i32 %23, 0
  br i1 %.not, label %24, label %30

24:                                               ; preds = %18
  %25 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %19) #1
  %26 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %25, i64 noundef %21) #1
  %27 = load i8, ptr %26, align 1, !tbaa !9
  %28 = icmp eq i8 %27, 46
  br i1 %28, label %29, label %30

29:                                               ; preds = %24
  tail call void @_Z3dfsii(i32 noundef %8, i32 noundef %10)
  br label %30

30:                                               ; preds = %18, %24, %29, %12, %tailrecurse
  %31 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.row, i64 4), align 4, !tbaa !5
  %32 = add nsw i32 %31, %.tr
  %33 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.col, i64 4), align 4, !tbaa !5
  %34 = add nsw i32 %33, %.tr25
  %35 = icmp sgt i32 %32, -1
  br i1 %35, label %36, label %54

36:                                               ; preds = %30
  %37 = load i32, ptr @n, align 4, !tbaa !5
  %38 = icmp slt i32 %32, %37
  %39 = icmp sgt i32 %34, -1
  %or.cond.1 = select i1 %38, i1 %39, i1 false
  %40 = load i32, ptr @m, align 4
  %41 = icmp slt i32 %34, %40
  %or.cond22.1 = select i1 %or.cond.1, i1 %41, i1 false
  br i1 %or.cond22.1, label %42, label %54

42:                                               ; preds = %36
  %43 = zext nneg i32 %32 to i64
  %44 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %43) #1
  %45 = zext nneg i32 %34 to i64
  %46 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %44, i64 noundef %45) #1
  %47 = load i32, ptr %46, align 4, !tbaa !5
  %.not.1 = icmp eq i32 %47, 0
  br i1 %.not.1, label %48, label %54

48:                                               ; preds = %42
  %49 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %43) #1
  %50 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %45) #1
  %51 = load i8, ptr %50, align 1, !tbaa !9
  %52 = icmp eq i8 %51, 46
  br i1 %52, label %53, label %54

53:                                               ; preds = %48
  tail call void @_Z3dfsii(i32 noundef %32, i32 noundef %34)
  br label %54

54:                                               ; preds = %53, %48, %42, %36, %30
  %55 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.row, i64 8), align 8, !tbaa !5
  %56 = add nsw i32 %55, %.tr
  %57 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.col, i64 8), align 8, !tbaa !5
  %58 = add nsw i32 %57, %.tr25
  %59 = icmp sgt i32 %56, -1
  br i1 %59, label %60, label %78

60:                                               ; preds = %54
  %61 = load i32, ptr @n, align 4, !tbaa !5
  %62 = icmp slt i32 %56, %61
  %63 = icmp sgt i32 %58, -1
  %or.cond.2 = select i1 %62, i1 %63, i1 false
  %64 = load i32, ptr @m, align 4
  %65 = icmp slt i32 %58, %64
  %or.cond22.2 = select i1 %or.cond.2, i1 %65, i1 false
  br i1 %or.cond22.2, label %66, label %78

66:                                               ; preds = %60
  %67 = zext nneg i32 %56 to i64
  %68 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %67) #1
  %69 = zext nneg i32 %58 to i64
  %70 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %69) #1
  %71 = load i32, ptr %70, align 4, !tbaa !5
  %.not.2 = icmp eq i32 %71, 0
  br i1 %.not.2, label %72, label %78

72:                                               ; preds = %66
  %73 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %67) #1
  %74 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %69) #1
  %75 = load i8, ptr %74, align 1, !tbaa !9
  %76 = icmp eq i8 %75, 46
  br i1 %76, label %77, label %78

77:                                               ; preds = %72
  tail call void @_Z3dfsii(i32 noundef %56, i32 noundef %58)
  br label %78

78:                                               ; preds = %77, %72, %66, %60, %54
  %79 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.row, i64 12), align 4, !tbaa !5
  %80 = add nsw i32 %79, %.tr
  %81 = load i32, ptr getelementptr inbounds (i8, ptr @__const._Z3dfsii.col, i64 12), align 4, !tbaa !5
  %82 = add nsw i32 %81, %.tr25
  %83 = icmp sgt i32 %80, -1
  br i1 %83, label %84, label %101

84:                                               ; preds = %78
  %85 = load i32, ptr @n, align 4, !tbaa !5
  %86 = icmp slt i32 %80, %85
  %87 = icmp sgt i32 %82, -1
  %or.cond.3 = select i1 %86, i1 %87, i1 false
  %88 = load i32, ptr @m, align 4
  %89 = icmp slt i32 %82, %88
  %or.cond22.3 = select i1 %or.cond.3, i1 %89, i1 false
  br i1 %or.cond22.3, label %90, label %101

90:                                               ; preds = %84
  %91 = zext nneg i32 %80 to i64
  %92 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @vi, i64 noundef %91) #1
  %93 = zext nneg i32 %82 to i64
  %94 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %92, i64 noundef %93) #1
  %95 = load i32, ptr %94, align 4, !tbaa !5
  %.not.3 = icmp eq i32 %95, 0
  br i1 %.not.3, label %96, label %101

96:                                               ; preds = %90
  %97 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @v, i64 noundef %91) #1
  %98 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %97, i64 noundef %93) #1
  %99 = load i8, ptr %98, align 1, !tbaa !9
  %100 = icmp eq i8 %99, 46
  br i1 %100, label %tailrecurse, label %101

101:                                              ; preds = %96, %90, %84, %78
  ret void
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IcSaIcEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass