; LLVM IR from Eaglegor/SchedulerEngine :: Engine/Concepts/Capacity.ll (ZNK9Scheduler8CapacityngEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Scheduler::Capacity" = type { [4 x float] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef, float noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK9Scheduler8CapacityngEv(ptr dead_on_unwind noalias writable sret(%"class.Scheduler::Capacity") align 4 %0, ptr noundef nonnull align 4 dereferenceable(16) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %4, align 8
  call void @_ZN9Scheduler8CapacityC1ERKS0_(ptr noundef nonnull align 4 dereferenceable(16) %0, ptr noundef nonnull align 4 dereferenceable(16) %6)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %7

7:                                                ; preds = %18, %2
  %8 = load i32, ptr %5, align 4, !tbaa !9
  %9 = icmp slt i32 %8, 4
  br i1 %9, label %11, label %10

10:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  br label %21

11:                                               ; preds = %7
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = sext i32 %12 to i64
  %14 = load i32, ptr %5, align 4, !tbaa !9
  %15 = sext i32 %14 to i64
  %16 = call noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef %15)
  %17 = fneg float %16
  call void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef %13, float noundef %17)
  br label %18

18:                                               ; preds = %11
  %19 = load i32, ptr %5, align 4, !tbaa !9
  %20 = add nsw i32 %19, 1
  store i32 %20, ptr %5, align 4, !tbaa !9
  br label %7, !llvm.loop !11

21:                                               ; preds = %10
  ret void
}

declare void @_ZN9Scheduler8CapacityC1ERKS0_(ptr, ptr)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.Scheduler::Capacity" = type { [4 x float] }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef, float noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZNK9Scheduler8CapacityngEv(ptr dead_on_unwind noalias writable sret(%"class.Scheduler::Capacity") align 4 %0, ptr noundef nonnull align 4 dereferenceable(16) %1) local_unnamed_addr #1 align 2 {
  tail call void @_ZN9Scheduler8CapacityC1ERKS0_(ptr noundef nonnull align 4 dereferenceable(16) %0, ptr noundef nonnull align 4 dereferenceable(16) %1)
  %3 = tail call noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 0)
  %4 = fneg float %3
  tail call void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 0, float noundef %4)
  %5 = tail call noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 1)
  %6 = fneg float %5
  tail call void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 1, float noundef %6)
  %7 = tail call noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 2)
  %8 = fneg float %7
  tail call void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 2, float noundef %8)
  %9 = tail call noundef float @_ZNK9Scheduler8Capacity8getValueEm(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 3)
  %10 = fneg float %9
  tail call void @_ZN9Scheduler8Capacity8setValueEmf(ptr noundef nonnull align 4 dereferenceable(16) %0, i64 noundef 3, float noundef %10)
  ret void
}

declare void @_ZN9Scheduler8CapacityC1ERKS0_(ptr, ptr) local_unnamed_addr

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass