; LLVM IR from AnneLivia/Competitive-Programming :: Online Judges/Neps Academy/Produto do Intervalo/main.ll (Z5queryiiiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@st = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i64 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #2 {
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i64, align 8
  %16 = alloca i64, align 8
  store i32 %0, ptr %7, align 4, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !5
  store i32 %2, ptr %9, align 4, !tbaa !5
  store i32 %3, ptr %10, align 4, !tbaa !5
  store i32 %4, ptr %11, align 4, !tbaa !5
  %17 = load i32, ptr %8, align 4, !tbaa !5
  %18 = load i32, ptr %11, align 4, !tbaa !5
  %19 = icmp sgt i32 %17, %18
  br i1 %19, label %24, label %20

20:                                               ; preds = %5
  %21 = load i32, ptr %9, align 4, !tbaa !5
  %22 = load i32, ptr %10, align 4, !tbaa !5
  %23 = icmp slt i32 %21, %22
  br i1 %23, label %24, label %25

24:                                               ; preds = %20, %5
  store i64 1, ptr %6, align 8
  br label %65

25:                                               ; preds = %20
  %26 = load i32, ptr %10, align 4, !tbaa !5
  %27 = load i32, ptr %8, align 4, !tbaa !5
  %28 = icmp sle i32 %26, %27
  br i1 %28, label %29, label %38

29:                                               ; preds = %25
  %30 = load i32, ptr %9, align 4, !tbaa !5
  %31 = load i32, ptr %11, align 4, !tbaa !5
  %32 = icmp sle i32 %30, %31
  br i1 %32, label %33, label %38

33:                                               ; preds = %29
  %34 = load i32, ptr %7, align 4, !tbaa !5
  %35 = sext i32 %34 to i64
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %35) #3
  %37 = load i64, ptr %36, align 8, !tbaa !9
  store i64 %37, ptr %6, align 8
  br label %65

38:                                               ; preds = %29, %25
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %39 = load i32, ptr %8, align 4, !tbaa !5
  %40 = load i32, ptr %9, align 4, !tbaa !5
  %41 = add nsw i32 %39, %40
  %42 = ashr i32 %41, 1
  store i32 %42, ptr %12, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %43 = load i32, ptr %7, align 4, !tbaa !5
  %44 = mul nsw i32 %43, 2
  store i32 %44, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  %45 = load i32, ptr %7, align 4, !tbaa !5
  %46 = mul nsw i32 %45, 2
  %47 = add nsw i32 %46, 1
  store i32 %47, ptr %14, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #3
  %48 = load i32, ptr %13, align 4, !tbaa !5
  %49 = load i32, ptr %8, align 4, !tbaa !5
  %50 = load i32, ptr %12, align 4, !tbaa !5
  %51 = load i32, ptr %10, align 4, !tbaa !5
  %52 = load i32, ptr %11, align 4, !tbaa !5
  %53 = call noundef i64 @_Z5queryiiiii(i32 noundef %48, i32 noundef %49, i32 noundef %50, i32 noundef %51, i32 noundef %52)
  store i64 %53, ptr %15, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #3
  %54 = load i32, ptr %14, align 4, !tbaa !5
  %55 = load i32, ptr %12, align 4, !tbaa !5
  %56 = add nsw i32 %55, 1
  %57 = load i32, ptr %9, align 4, !tbaa !5
  %58 = load i32, ptr %10, align 4, !tbaa !5
  %59 = load i32, ptr %11, align 4, !tbaa !5
  %60 = call noundef i64 @_Z5queryiiiii(i32 noundef %54, i32 noundef %56, i32 noundef %57, i32 noundef %58, i32 noundef %59)
  store i64 %60, ptr %16, align 8, !tbaa !9
  %61 = load i64, ptr %15, align 8, !tbaa !9
  %62 = load i64, ptr %16, align 8, !tbaa !9
  %63 = mul nsw i64 %61, %62
  %64 = srem i64 %63, 1000000007
  store i64 %64, ptr %6, align 8
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %65

65:                                               ; preds = %38, %33, %24
  %66 = load i64, ptr %6, align 8
  ret i64 %66
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@st = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i64 @_Z5queryiiiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = icmp sgt i32 %1, %4
  %7 = icmp slt i32 %2, %3
  %or.cond = or i1 %7, %6
  br i1 %or.cond, label %common.ret32, label %8

8:                                                ; preds = %5
  %.not = icmp sgt i32 %3, %1
  %.not30 = icmp sgt i32 %2, %4
  %or.cond31 = or i1 %.not, %.not30
  br i1 %or.cond31, label %13, label %9

9:                                                ; preds = %8
  %10 = sext i32 %0 to i64
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @st, i64 noundef %10) #1
  %12 = load i64, ptr %11, align 8, !tbaa !5
  br label %common.ret32

common.ret32:                                     ; preds = %5, %9, %13
  %common.ret32.op = phi i64 [ %22, %13 ], [ %12, %9 ], [ 1, %5 ]
  ret i64 %common.ret32.op

13:                                               ; preds = %8
  %14 = add nsw i32 %2, %1
  %15 = ashr i32 %14, 1
  %16 = shl nsw i32 %0, 1
  %17 = or disjoint i32 %16, 1
  %18 = tail call noundef i64 @_Z5queryiiiii(i32 noundef %16, i32 noundef %1, i32 noundef %15, i32 noundef %3, i32 noundef %4)
  %19 = add nsw i32 %15, 1
  %20 = tail call noundef i64 @_Z5queryiiiii(i32 noundef %17, i32 noundef %19, i32 noundef %2, i32 noundef %3, i32 noundef %4)
  %21 = mul nsw i64 %20, %18
  %22 = srem i64 %21, 1000000007
  br label %common.ret32
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass