; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/devices (mcp4725)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mVoltage = external hidden global float, align 4
@mcp4725_write.str = external hidden constant [31 x i8], align 4
@mAddress = external hidden global i32, align 4
@mcp4725_write.str.1 = external hidden constant [25 x i8], align 4

; Function Attrs: nounwind uwtable
define dso_local i32 @mcp4725_write(i32 noundef %0, i32 noundef %1, float noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca float, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i16, align 2
  %11 = alloca [3 x i8], align 1
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store float %2, ptr %7, align 4, !tbaa !9
  %12 = load float, ptr %7, align 4, !tbaa !9
  %13 = fcmp olt float %12, 0.000000e+00
  br i1 %13, label %18, label %14

14:                                               ; preds = %3
  %15 = load float, ptr %7, align 4, !tbaa !9
  %16 = load float, ptr @mVoltage, align 4, !tbaa !9
  %17 = fcmp ogt float %15, %16
  br i1 %17, label %18, label %19

18:                                               ; preds = %14, %3
  store i32 2, ptr %4, align 4
  br label %67

19:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %20 = load i32, ptr %5, align 4, !tbaa !5
  %21 = icmp ne i32 %20, -1
  br i1 %21, label %22, label %36

22:                                               ; preds = %19
  %23 = load i32, ptr %6, align 4, !tbaa !5
  %24 = icmp ne i32 %23, -1
  br i1 %24, label %25, label %36

25:                                               ; preds = %22
  %26 = load i32, ptr %5, align 4, !tbaa !5
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = call i32 @dh_i2c_init(i32 noundef %26, i32 noundef %27)
  store i32 %28, ptr %8, align 4, !tbaa !5
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %35

30:                                               ; preds = %25
  br label %31

31:                                               ; preds = %30
  call void (ptr, ...) @dhdebug_ram(ptr noundef @mcp4725_write.str)
  br label %32

32:                                               ; preds = %31
  br label %33

33:                                               ; preds = %32
  %34 = load i32, ptr %8, align 4, !tbaa !5
  store i32 %34, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %66

35:                                               ; preds = %25
  br label %36

36:                                               ; preds = %35, %22, %19
  call void @llvm.lifetime.start.p0(i64 2, ptr %10) #3
  %37 = load float, ptr %7, align 4, !tbaa !9
  %38 = load float, ptr @mVoltage, align 4, !tbaa !9
  %39 = fdiv float %37, %38
  %40 = fmul float %39, 4.095000e+03
  %41 = fptoui float %40 to i16
  store i16 %41, ptr %10, align 2, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 3, ptr %11) #3
  %42 = getelementptr inbounds [3 x i8], ptr %11, i64 0, i64 0
  store i8 64, ptr %42, align 1, !tbaa !13
  %43 = load i16, ptr %10, align 2, !tbaa !11
  %44 = zext i16 %43 to i32
  %45 = ashr i32 %44, 4
  %46 = and i32 %45, 255
  %47 = trunc i32 %46 to i8
  %48 = getelementptr inbounds [3 x i8], ptr %11, i64 0, i64 1
  store i8 %47, ptr %48, align 1, !tbaa !13
  %49 = load i16, ptr %10, align 2, !tbaa !11
  %50 = zext i16 %49 to i32
  %51 = and i32 %50, 15
  %52 = shl i32 %51, 4
  %53 = trunc i32 %52 to i8
  %54 = getelementptr inbounds [3 x i8], ptr %11, i64 0, i64 2
  store i8 %53, ptr %54, align 1, !tbaa !13
  %55 = load i32, ptr @mAddress, align 4, !tbaa !5
  %56 = getelementptr inbounds [3 x i8], ptr %11, i64 0, i64 0
  %57 = call i32 @dh_i2c_write(i32 noundef %55, ptr noundef %56, i32 noundef 3, i32 noundef 1)
  store i32 %57, ptr %8, align 4, !tbaa !5
  %58 = icmp ne i32 %57, 0
  br i1 %58, label %59, label %64

59:                                               ; preds = %36
  br label %60

60:                                               ; preds = %59
  call void (ptr, ...) @dhdebug_ram(ptr noundef @mcp4725_write.str.1)
  br label %61

61:                                               ; preds = %60
  br label %62

62:                                               ; preds = %61
  %63 = load i32, ptr %8, align 4, !tbaa !5
  store i32 %63, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %65

64:                                               ; preds = %36
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %65

65:                                               ; preds = %64, %62
  call void @llvm.lifetime.end.p0(i64 3, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %10) #3
  br label %66

66:                                               ; preds = %65, %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %67

67:                                               ; preds = %66, %18
  %68 = load i32, ptr %4, align 4
  ret i32 %68
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @dh_i2c_init(i32 noundef, i32 noundef) #2

declare void @dhdebug_ram(ptr noundef, ...) #2

declare i32 @dh_i2c_write(i32 noundef, ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"float", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"short", !7, i64 0}
!13 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mVoltage = external hidden local_unnamed_addr global float, align 4
@mcp4725_write.str = external hidden constant [31 x i8], align 4
@mAddress = external hidden local_unnamed_addr global i32, align 4
@mcp4725_write.str.1 = external hidden constant [25 x i8], align 4

; Function Attrs: nounwind uwtable
define dso_local i32 @mcp4725_write(i32 noundef %0, i32 noundef %1, float noundef %2) local_unnamed_addr #0 {
  %4 = alloca [3 x i8], align 1
  %5 = fcmp olt float %2, 0.000000e+00
  %6 = load float, ptr @mVoltage, align 4
  %7 = fcmp olt float %6, %2
  %or.cond19 = select i1 %5, i1 true, i1 %7
  br i1 %or.cond19, label %28, label %8

8:                                                ; preds = %3
  %9 = icmp ne i32 %0, -1
  %10 = icmp ne i32 %1, -1
  %or.cond = and i1 %9, %10
  br i1 %or.cond, label %11, label %14

11:                                               ; preds = %8
  %12 = tail call i32 @dh_i2c_init(i32 noundef %0, i32 noundef %1) #3
  %.not = icmp eq i32 %12, 0
  br i1 %.not, label %._crit_edge, label %13

._crit_edge:                                      ; preds = %11
  %.pre = load float, ptr @mVoltage, align 4, !tbaa !5
  br label %14

13:                                               ; preds = %11
  tail call void (ptr, ...) @dhdebug_ram(ptr noundef nonnull @mcp4725_write.str) #3
  br label %28

14:                                               ; preds = %._crit_edge, %8
  %15 = phi float [ %.pre, %._crit_edge ], [ %6, %8 ]
  %16 = fdiv float %2, %15
  %17 = fmul float %16, 4.095000e+03
  %18 = fptoui float %17 to i16
  call void @llvm.lifetime.start.p0(i64 3, ptr nonnull %4) #3
  store i8 64, ptr %4, align 1, !tbaa !9
  %19 = lshr i16 %18, 4
  %20 = trunc i16 %19 to i8
  %21 = getelementptr inbounds i8, ptr %4, i64 1
  store i8 %20, ptr %21, align 1, !tbaa !9
  %.tr = trunc i16 %18 to i8
  %22 = shl i8 %.tr, 4
  %23 = getelementptr inbounds i8, ptr %4, i64 2
  store i8 %22, ptr %23, align 1, !tbaa !9
  %24 = load i32, ptr @mAddress, align 4, !tbaa !10
  %25 = call i32 @dh_i2c_write(i32 noundef %24, ptr noundef nonnull %4, i32 noundef 3, i32 noundef 1) #3
  %.not17 = icmp eq i32 %25, 0
  br i1 %.not17, label %27, label %26

26:                                               ; preds = %14
  call void (ptr, ...) @dhdebug_ram(ptr noundef nonnull @mcp4725_write.str.1) #3
  br label %27

27:                                               ; preds = %14, %26
  call void @llvm.lifetime.end.p0(i64 3, ptr nonnull %4) #3
  br label %28

28:                                               ; preds = %13, %27, %3
  %.2 = phi i32 [ 2, %3 ], [ %12, %13 ], [ %25, %27 ]
  ret i32 %.2
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @dh_i2c_init(i32 noundef, i32 noundef) local_unnamed_addr #2

declare void @dhdebug_ram(ptr noundef, ...) local_unnamed_addr #2

declare i32 @dh_i2c_write(i32 noundef, ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass