; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/devices (max6675)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mCSPin = external hidden global i32, align 4
@.str = external hidden unnamed_addr constant [13 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [15 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [30 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local ptr @max6675_read(i32 noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca [2 x i8], align 1
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  %10 = load i32, ptr %4, align 4, !tbaa !5
  %11 = icmp eq i32 %10, -2
  br i1 %11, label %12, label %15

12:                                               ; preds = %2
  %13 = load i32, ptr @mCSPin, align 4, !tbaa !5
  %14 = call i32 @dh_spi_set_cs_pin(i32 noundef %13)
  br label %35

15:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %16 = load i32, ptr %4, align 4, !tbaa !5
  %17 = icmp ne i32 %16, -1
  %18 = zext i1 %17 to i32
  store i32 %18, ptr %6, align 4, !tbaa !5
  %19 = load i32, ptr %6, align 4, !tbaa !5
  %20 = icmp ne i32 %19, 0
  br i1 %20, label %21, label %26

21:                                               ; preds = %15
  %22 = load i32, ptr %4, align 4, !tbaa !5
  %23 = call i32 @dh_spi_set_cs_pin(i32 noundef %22)
  %24 = icmp eq i32 0, %23
  %25 = zext i1 %24 to i32
  store i32 %25, ptr %6, align 4, !tbaa !5
  br label %26

26:                                               ; preds = %21, %15
  %27 = load i32, ptr %6, align 4, !tbaa !5
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %30, label %29

29:                                               ; preds = %26
  store ptr @.str, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %32

30:                                               ; preds = %26
  %31 = load i32, ptr %4, align 4, !tbaa !5
  store i32 %31, ptr @mCSPin, align 4, !tbaa !5
  store i32 0, ptr %7, align 4
  br label %32

32:                                               ; preds = %30, %29
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %33 = load i32, ptr %7, align 4
  switch i32 %33, label %77 [
    i32 0, label %34
    i32 1, label %75
  ]

34:                                               ; preds = %32
  br label %35

35:                                               ; preds = %34, %12
  %36 = call i32 @dh_spi_set_mode(i32 noundef 0)
  %37 = load i32, ptr @mCSPin, align 4, !tbaa !5
  %38 = zext i32 %37 to i64
  %39 = shl i64 1, %38
  %40 = trunc i64 %39 to i32
  %41 = call i32 @dh_gpio_write(i32 noundef %40, i32 noundef 0)
  call void @delay_ms(i32 noundef 250)
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #4
  %42 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 0
  call void @dh_spi_read(ptr noundef %42, i32 noundef 2)
  %43 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 0
  %44 = load i8, ptr %43, align 1, !tbaa !11
  %45 = zext i8 %44 to i32
  %46 = and i32 %45, 128
  %47 = icmp ne i32 %46, 0
  br i1 %47, label %54, label %48

48:                                               ; preds = %35
  %49 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 1
  %50 = load i8, ptr %49, align 1, !tbaa !11
  %51 = zext i8 %50 to i32
  %52 = and i32 %51, 2
  %53 = icmp ne i32 %52, 0
  br i1 %53, label %54, label %55

54:                                               ; preds = %48, %35
  store ptr @.str.1, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %74

55:                                               ; preds = %48
  %56 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 1
  %57 = load i8, ptr %56, align 1, !tbaa !11
  %58 = zext i8 %57 to i32
  %59 = and i32 %58, 4
  %60 = icmp ne i32 %59, 0
  br i1 %60, label %61, label %62

61:                                               ; preds = %55
  store ptr @.str.2, ptr %3, align 8
  store i32 1, ptr %7, align 4
  br label %74

62:                                               ; preds = %55
  %63 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 1
  %64 = load i8, ptr %63, align 1, !tbaa !11
  %65 = zext i8 %64 to i32
  %66 = and i32 %65, 248
  %67 = trunc i32 %66 to i8
  store i8 %67, ptr %63, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %68 = getelementptr inbounds [2 x i8], ptr %8, i64 0, i64 0
  %69 = call i32 @signedInt16be(ptr noundef %68, i32 noundef 0)
  store i32 %69, ptr %9, align 4, !tbaa !5
  %70 = load i32, ptr %9, align 4, !tbaa !5
  %71 = sitofp i32 %70 to float
  %72 = fdiv float %71, 3.200000e+01
  %73 = load ptr, ptr %5, align 8, !tbaa !9
  store float %72, ptr %73, align 4, !tbaa !12
  store ptr null, ptr %3, align 8
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %74

74:                                               ; preds = %62, %61, %54
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #4
  br label %75

75:                                               ; preds = %74, %32
  %76 = load ptr, ptr %3, align 8
  ret ptr %76

77:                                               ; preds = %32
  unreachable
}

declare i32 @dh_spi_set_cs_pin(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare i32 @dh_spi_set_mode(i32 noundef) #1

declare i32 @dh_gpio_write(i32 noundef, i32 noundef) #1

declare void @delay_ms(i32 noundef) #1

declare void @dh_spi_read(ptr noundef, i32 noundef) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @signedInt16be(ptr noundef, i32 noundef) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"float", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mCSPin = external hidden local_unnamed_addr global i32, align 4
@.str = external hidden unnamed_addr constant [13 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [15 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [30 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @max6675_read(i32 noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = alloca [2 x i8], align 1
  switch i32 %0, label %7 [
    i32 -2, label %4
    i32 -1, label %.thread15
  ]

4:                                                ; preds = %2
  %5 = load i32, ptr @mCSPin, align 4, !tbaa !5
  %6 = tail call i32 @dh_spi_set_cs_pin(i32 noundef %5) #4
  br label %11

7:                                                ; preds = %2
  %8 = tail call i32 @dh_spi_set_cs_pin(i32 noundef %0) #4
  %9 = icmp eq i32 %8, 0
  br i1 %9, label %10, label %.thread15

10:                                               ; preds = %7
  store i32 %0, ptr @mCSPin, align 4, !tbaa !5
  br label %11

11:                                               ; preds = %10, %4
  %12 = tail call i32 @dh_spi_set_mode(i32 noundef 0) #4
  %13 = load i32, ptr @mCSPin, align 4, !tbaa !5
  %14 = zext nneg i32 %13 to i64
  %15 = shl nuw i64 1, %14
  %16 = trunc i64 %15 to i32
  %17 = tail call i32 @dh_gpio_write(i32 noundef %16, i32 noundef 0) #4
  tail call void @delay_ms(i32 noundef 250) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %3) #4
  call void @dh_spi_read(ptr noundef nonnull %3, i32 noundef 2) #4
  %18 = load i8, ptr %3, align 1, !tbaa !9
  %.not = icmp sgt i8 %18, -1
  br i1 %.not, label %19, label %31

19:                                               ; preds = %11
  %20 = getelementptr inbounds i8, ptr %3, i64 1
  %21 = load i8, ptr %20, align 1, !tbaa !9
  %22 = zext i8 %21 to i32
  %23 = and i32 %22, 2
  %.not11 = icmp eq i32 %23, 0
  br i1 %.not11, label %24, label %31

24:                                               ; preds = %19
  %25 = and i32 %22, 4
  %.not12 = icmp eq i32 %25, 0
  br i1 %.not12, label %26, label %31

26:                                               ; preds = %24
  %27 = and i8 %21, -8
  store i8 %27, ptr %20, align 1, !tbaa !9
  %28 = call i32 @signedInt16be(ptr noundef nonnull %3, i32 noundef 0)
  %29 = sitofp i32 %28 to float
  %30 = fmul float %29, 3.125000e-02
  store float %30, ptr %1, align 4, !tbaa !10
  br label %31

31:                                               ; preds = %24, %11, %19, %26
  %.1 = phi ptr [ null, %26 ], [ @.str.1, %19 ], [ @.str.1, %11 ], [ @.str.2, %24 ]
  call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %3) #4
  br label %.thread15

.thread15:                                        ; preds = %2, %7, %31
  %.2 = phi ptr [ %.1, %31 ], [ @.str, %7 ], [ @.str, %2 ]
  ret ptr %.2
}

declare i32 @dh_spi_set_cs_pin(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

declare i32 @dh_spi_set_mode(i32 noundef) local_unnamed_addr #1

declare i32 @dh_gpio_write(i32 noundef, i32 noundef) local_unnamed_addr #1

declare void @delay_ms(i32 noundef) local_unnamed_addr #1

declare void @dh_spi_read(ptr noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @signedInt16be(ptr noundef, i32 noundef) local_unnamed_addr #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"float", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass