; LLVM IR from Eaglegor/SchedulerEngine :: Persistence/SceneLoaders/TspLibSceneLoader (TspLibSceneLoader)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9Scheduler17TspLibSceneLoader16loadBinaryMatrixERSiRmRNS_20TspLibRoutingServiceERj(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef nonnull align 8 dereferenceable(16) %1, ptr noundef nonnull align 8 dereferenceable(8) %2, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr noundef nonnull align 4 dereferenceable(4) %4) #1 align 2 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i64, align 8
  %16 = alloca i32, align 4
  %17 = alloca i64, align 8
  %18 = alloca float, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %1, ptr %7, align 8, !tbaa !5
  store ptr %2, ptr %8, align 8, !tbaa !5
  store ptr %3, ptr %9, align 8, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !5
  %19 = load ptr, ptr %6, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  %20 = load ptr, ptr %7, align 8, !tbaa !5
  %21 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %20, ptr noundef %11, i64 noundef 4)
  %22 = load ptr, ptr %7, align 8, !tbaa !5
  %23 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %22, ptr noundef %12, i64 noundef 4)
  %24 = load ptr, ptr %7, align 8, !tbaa !5
  %25 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %24, ptr noundef %13, i64 noundef 4)
  %26 = load ptr, ptr %9, align 8, !tbaa !5
  %27 = load i32, ptr %11, align 4, !tbaa !9
  %28 = zext i32 %27 to i64
  call void @_ZN9Scheduler20TspLibRoutingService4initEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %28)
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #4
  store i64 0, ptr %15, align 8, !tbaa !11
  br label %29

29:                                               ; preds = %61, %5
  %30 = load i64, ptr %15, align 8, !tbaa !11
  %31 = load i32, ptr %11, align 4, !tbaa !9
  %32 = zext i32 %31 to i64
  %33 = icmp ult i64 %30, %32
  br i1 %33, label %35, label %34

34:                                               ; preds = %29
  store i32 2, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #4
  br label %64

35:                                               ; preds = %29
  call void @llvm.lifetime.start.p0(i64 8, ptr %17) #4
  store i64 0, ptr %17, align 8, !tbaa !11
  br label %36

36:                                               ; preds = %57, %35
  %37 = load i64, ptr %17, align 8, !tbaa !11
  %38 = load i32, ptr %11, align 4, !tbaa !9
  %39 = zext i32 %38 to i64
  %40 = icmp ult i64 %37, %39
  br i1 %40, label %42, label %41

41:                                               ; preds = %36
  store i32 5, ptr %16, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %17) #4
  br label %60

42:                                               ; preds = %36
  %43 = load ptr, ptr %7, align 8, !tbaa !5
  %44 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %43, ptr noundef %14, i64 noundef 4)
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #4
  %45 = load i32, ptr %14, align 4, !tbaa !9
  %46 = uitofp i32 %45 to float
  %47 = fpext float %46 to double
  %48 = load i32, ptr %13, align 4, !tbaa !9
  %49 = uitofp i32 %48 to double
  %50 = call double @pow(double noundef 1.000000e+01, double noundef %49) #4
  %51 = fdiv double %47, %50
  %52 = fptrunc double %51 to float
  store float %52, ptr %18, align 4, !tbaa !13
  %53 = load ptr, ptr %9, align 8, !tbaa !5
  %54 = load i64, ptr %15, align 8, !tbaa !11
  %55 = load i64, ptr %17, align 8, !tbaa !11
  %56 = load float, ptr %18, align 4, !tbaa !13
  call void @_ZN9Scheduler20TspLibRoutingService11insertRouteEmmf(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %54, i64 noundef %55, float noundef %56)
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #4
  br label %57

57:                                               ; preds = %42
  %58 = load i64, ptr %17, align 8, !tbaa !11
  %59 = add i64 %58, 1
  store i64 %59, ptr %17, align 8, !tbaa !11
  br label %36, !llvm.loop !15

60:                                               ; preds = %41
  br label %61

61:                                               ; preds = %60
  %62 = load i64, ptr %15, align 8, !tbaa !11
  %63 = add i64 %62, 1
  store i64 %63, ptr %15, align 8, !tbaa !11
  br label %29, !llvm.loop !17

64:                                               ; preds = %34
  %65 = load i32, ptr %12, align 4, !tbaa !9
  %66 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %65, ptr %66, align 4, !tbaa !9
  %67 = load i32, ptr %11, align 4, !tbaa !9
  %68 = zext i32 %67 to i64
  %69 = load ptr, ptr %8, align 8, !tbaa !5
  store i64 %68, ptr %69, align 8, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #4
  ret void
}

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef, i64 noundef) #2

declare void @_ZN9Scheduler20TspLibRoutingService4initEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2

; Function Attrs: nounwind
declare double @pow(double noundef, double noundef) #3

declare void @_ZN9Scheduler20TspLibRoutingService11insertRouteEmmf(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, i64 noundef, float noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"float", !7, i64 0}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN9Scheduler17TspLibSceneLoader16loadBinaryMatrixERSiRmRNS_20TspLibRoutingServiceERj(ptr nocapture noundef nonnull readnone align 8 dereferenceable(8) %0, ptr noundef nonnull align 8 dereferenceable(16) %1, ptr nocapture noundef nonnull writeonly align 8 dereferenceable(8) %2, ptr noundef nonnull align 8 dereferenceable(24) %3, ptr nocapture noundef nonnull writeonly align 4 dereferenceable(4) %4) local_unnamed_addr #1 align 2 {
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %8) #4
  %10 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %1, ptr noundef nonnull %6, i64 noundef 4)
  %11 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %1, ptr noundef nonnull %7, i64 noundef 4)
  %12 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %1, ptr noundef nonnull %8, i64 noundef 4)
  %13 = load i32, ptr %6, align 4, !tbaa !5
  %14 = zext i32 %13 to i64
  call void @_ZN9Scheduler20TspLibRoutingService4initEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %14)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %9) #4
  %15 = load i32, ptr %6, align 4, !tbaa !5
  %.not = icmp eq i32 %15, 0
  br i1 %.not, label %._crit_edge18, label %.preheader

.preheader:                                       ; preds = %5, %._crit_edge
  %16 = phi i32 [ %18, %._crit_edge ], [ 1, %5 ]
  %.017 = phi i64 [ %19, %._crit_edge ], [ 0, %5 ]
  %.not19 = icmp eq i32 %16, 0
  br i1 %.not19, label %._crit_edge, label %.lr.ph

._crit_edge18:                                    ; preds = %._crit_edge, %5
  %.lcssa = phi i64 [ 0, %5 ], [ %20, %._crit_edge ]
  %17 = load i32, ptr %7, align 4, !tbaa !5
  store i32 %17, ptr %4, align 4, !tbaa !5
  store i64 %.lcssa, ptr %2, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %9) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #4
  ret void

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  %18 = phi i32 [ 0, %.preheader ], [ %32, %.lr.ph ]
  %19 = add nuw nsw i64 %.017, 1
  %20 = zext i32 %18 to i64
  %21 = icmp ult i64 %19, %20
  br i1 %21, label %.preheader, label %._crit_edge18, !llvm.loop !11

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %.01516 = phi i64 [ %31, %.lr.ph ], [ 0, %.preheader ]
  %22 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16) %1, ptr noundef nonnull %9, i64 noundef 4)
  %23 = load i32, ptr %9, align 4, !tbaa !5
  %24 = uitofp i32 %23 to float
  %25 = fpext float %24 to double
  %26 = load i32, ptr %8, align 4, !tbaa !5
  %27 = uitofp i32 %26 to double
  %28 = call double @pow(double noundef 1.000000e+01, double noundef %27) #4
  %29 = fdiv double %25, %28
  %30 = fptrunc double %29 to float
  call void @_ZN9Scheduler20TspLibRoutingService11insertRouteEmmf(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %.017, i64 noundef %.01516, float noundef %30)
  %31 = add nuw nsw i64 %.01516, 1
  %32 = load i32, ptr %6, align 4, !tbaa !5
  %33 = zext i32 %32 to i64
  %34 = icmp ult i64 %31, %33
  br i1 %34, label %.lr.ph, label %._crit_edge, !llvm.loop !13
}

declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSi4readEPcl(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef, i64 noundef) local_unnamed_addr #2

declare void @_ZN9Scheduler20TspLibRoutingService4initEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nofree nounwind willreturn memory(write)
declare double @pow(double noundef, double noundef) local_unnamed_addr #3

declare void @_ZN9Scheduler20TspLibRoutingService11insertRouteEmmf(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, i64 noundef, float noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nofree nounwind willreturn memory(write) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Effective O3 passes: ADCEPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass