; LLVM IR from turi-code/SFrame :: oss_src/graphlab/scheduler/fifo_scheduler.ll (ZN8graphlab14fifo_scheduler8get_nextEmRm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.graphlab::fifo_scheduler" = type { %"class.graphlab::ischeduler", %"class.graphlab::dense_bitset", %"class.std::vector", %"class.std::vector.6", %"class.std::vector.11", i64, i64, i64 }
%"class.graphlab::ischeduler" = type { ptr }
%"class.graphlab::dense_bitset" = type { ptr, i64, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::deque<unsigned long>, std::allocator<std::deque<unsigned long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.6" = type { %"struct.std::_Vector_base.7" }
%"struct.std::_Vector_base.7" = type { %"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl" }
%"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl" = type { %"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl_data" }
%"struct.std::_Vector_base<graphlab::padded_simple_spinlock, std::allocator<graphlab::padded_simple_spinlock>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1)) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1)) #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN8graphlab14fifo_scheduler8get_nextEmRm(ptr noundef nonnull align 8 dereferenceable(128) %0, i64 noundef %1, ptr noundef nonnull align 8 dereferenceable(8) %2) unnamed_addr #3 align 2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i32, align 4
  %11 = alloca i64, align 8
  %12 = alloca i8, align 1
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  %13 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %14 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 4
  %15 = load i64, ptr %6, align 8, !tbaa !9
  %16 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %15) #4
  %17 = load i64, ptr %16, align 8, !tbaa !9
  %18 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 6
  %19 = load i64, ptr %18, align 8, !tbaa !11
  %20 = urem i64 %17, %19
  %21 = load i64, ptr %6, align 8, !tbaa !9
  %22 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 6
  %23 = load i64, ptr %22, align 8, !tbaa !11
  %24 = mul i64 %21, %23
  %25 = add i64 %20, %24
  store i64 %25, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  store i64 0, ptr %9, align 8, !tbaa !9
  br label %26

26:                                               ; preds = %95, %3
  %27 = load i64, ptr %9, align 8, !tbaa !9
  %28 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 2
  %29 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %28) #4
  %30 = icmp ult i64 %27, %29
  br i1 %30, label %32, label %31

31:                                               ; preds = %26
  store i32 2, ptr %10, align 4
  br label %98

32:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #4
  %33 = load i64, ptr %8, align 8, !tbaa !9
  %34 = load i64, ptr %9, align 8, !tbaa !9
  %35 = add i64 %33, %34
  %36 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 2
  %37 = call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %36) #4
  %38 = urem i64 %35, %37
  store i64 %38, ptr %11, align 8, !tbaa !9
  %39 = load i64, ptr %9, align 8, !tbaa !9
  %40 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 6
  %41 = load i64, ptr %40, align 8, !tbaa !11
  %42 = icmp ult i64 %39, %41
  %43 = zext i1 %42 to i64
  %44 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 4
  %45 = load i64, ptr %6, align 8, !tbaa !9
  %46 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %44, i64 noundef %45) #4
  %47 = load i64, ptr %46, align 8, !tbaa !9
  %48 = add i64 %47, %43
  store i64 %48, ptr %46, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #4
  store i8 0, ptr %12, align 1, !tbaa !27
  %49 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 3
  %50 = load i64, ptr %11, align 8, !tbaa !9
  %51 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %49, i64 noundef %50) #4
  call void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1) %51)
  br label %52

52:                                               ; preds = %83, %32
  %53 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 2
  %54 = load i64, ptr %11, align 8, !tbaa !9
  %55 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %54) #4
  %56 = call noundef zeroext i1 @_ZNKSt5dequeImSaImEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(80) %55) #4
  %57 = xor i1 %56, true
  br i1 %57, label %58, label %84

58:                                               ; preds = %52
  %59 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 2
  %60 = load i64, ptr %11, align 8, !tbaa !9
  %61 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %59, i64 noundef %60) #4
  %62 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt5dequeImSaImEE5frontEv(ptr noundef nonnull align 8 dereferenceable(80) %61) #4
  %63 = load i64, ptr %62, align 8, !tbaa !9
  %64 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 %63, ptr %64, align 8, !tbaa !9
  %65 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 2
  %66 = load i64, ptr %11, align 8, !tbaa !9
  %67 = call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %65, i64 noundef %66) #4
  call void @_ZNSt5dequeImSaImEE9pop_frontEv(ptr noundef nonnull align 8 dereferenceable(80) %67) #4
  %68 = load ptr, ptr %7, align 8, !tbaa !5
  %69 = load i64, ptr %68, align 8, !tbaa !9
  %70 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 7
  %71 = load i64, ptr %70, align 8, !tbaa !29
  %72 = icmp ult i64 %69, %71
  br i1 %72, label %73, label %83

73:                                               ; preds = %58
  %74 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 1
  %75 = load ptr, ptr %7, align 8, !tbaa !5
  %76 = load i64, ptr %75, align 8, !tbaa !9
  %77 = call noundef zeroext i1 @_ZN8graphlab12dense_bitset9clear_bitEm(ptr noundef nonnull align 8 dereferenceable(24) %74, i64 noundef %76)
  %78 = zext i1 %77 to i8
  store i8 %78, ptr %12, align 1, !tbaa !27
  %79 = load i8, ptr %12, align 1, !tbaa !27, !range !30, !noundef !31
  %80 = trunc i8 %79 to i1
  br i1 %80, label %81, label %82

81:                                               ; preds = %73
  br label %84

82:                                               ; preds = %73
  br label %83

83:                                               ; preds = %82, %58
  br label %52, !llvm.loop !32

84:                                               ; preds = %81, %52
  %85 = getelementptr inbounds %"class.graphlab::fifo_scheduler", ptr %13, i32 0, i32 3
  %86 = load i64, ptr %11, align 8, !tbaa !9
  %87 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %85, i64 noundef %86) #4
  call void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1) %87)
  %88 = load i8, ptr %12, align 1, !tbaa !27, !range !30, !noundef !31
  %89 = trunc i8 %88 to i1
  br i1 %89, label %90, label %91

90:                                               ; preds = %84
  store i32 0, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %92

91:                                               ; preds = %84
  store i32 0, ptr %10, align 4
  br label %92

92:                                               ; preds = %91, %90
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #4
  %93 = load i32, ptr %10, align 4
  switch i32 %93, label %98 [
    i32 0, label %94
  ]

94:                                               ; preds = %92
  br label %95

95:                                               ; preds = %94
  %96 = load i64, ptr %9, align 8, !tbaa !9
  %97 = add i64 %96, 1
  store i64 %97, ptr %9, align 8, !tbaa !9
  br label %26, !llvm.loop !34

98:                                               ; preds = %92, %31
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  %99 = load i32, ptr %10, align 4
  switch i32 %99, label %101 [
    i32 2, label %100
  ]

100:                                              ; preds = %98
  store i32 1, ptr %4, align 4
  store i32 1, ptr %10, align 4
  br label %101

101:                                              ; preds = %100, %98
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  %102 = load i32, ptr %4, align 4
  ret i32 %102
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt5dequeImSaImEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(80)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt5dequeImSaImEE5frontEv(ptr noundef nonnull align 8 dereferenceable(80)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt5dequeImSaImEE9pop_frontEv(ptr noundef nonnull align 8 dereferenceable(80)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN8graphlab12dense_bitset9clear_bitEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !10, i64 112}
!12 = !{!"_ZTSN8graphlab14fifo_schedulerE", !13, i64 0, !14, i64 8, !15, i64 32, !19, i64 56, !23, i64 80, !10, i64 104, !10, i64 112, !10, i64 120}
!13 = !{!"_ZTSN8graphlab10ischedulerE"}
!14 = !{!"_ZTSN8graphlab12dense_bitsetE", !6, i64 0, !10, i64 8, !10, i64 16}
!15 = !{!"_ZTSSt6vectorISt5dequeImSaImEESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseISt5dequeImSaImEESaIS2_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!19 = !{!"_ZTSSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!23 = !{!"_ZTSSt6vectorImSaImEE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseImSaImEE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!27 = !{!28, !28, i64 0}
!28 = !{!"bool", !7, i64 0}
!29 = !{!12, !10, i64 120}
!30 = !{i8 0, i8 2}
!31 = !{}
!32 = distinct !{!32, !33}
!33 = !{!"llvm.loop.mustprogress"}
!34 = distinct !{!34, !33}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN8graphlab14fifo_scheduler8get_nextEmRm(ptr noundef nonnull align 8 dereferenceable(128) %0, i64 noundef %1, ptr nocapture noundef nonnull align 8 dereferenceable(8) %2) unnamed_addr #0 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 80
  %5 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %1) #2
  %6 = load i64, ptr %5, align 8, !tbaa !5
  %7 = getelementptr inbounds i8, ptr %0, i64 112
  %8 = load i64, ptr %7, align 8, !tbaa !9
  %9 = urem i64 %6, %8
  %10 = mul i64 %8, %1
  %11 = add i64 %9, %10
  %12 = getelementptr inbounds i8, ptr %0, i64 32
  %13 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #2
  %.not30 = icmp eq i64 %13, 0
  br i1 %.not30, label %._crit_edge, label %.lr.ph33

.lr.ph33:                                         ; preds = %3
  %14 = getelementptr inbounds i8, ptr %0, i64 56
  %15 = getelementptr inbounds i8, ptr %0, i64 120
  %16 = getelementptr inbounds i8, ptr %0, i64 8
  br label %17

17:                                               ; preds = %.lr.ph33, %.loopexit
  %.02731 = phi i64 [ 0, %.lr.ph33 ], [ %45, %.loopexit ]
  %18 = add i64 %11, %.02731
  %19 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #2
  %20 = urem i64 %18, %19
  %21 = load i64, ptr %7, align 8, !tbaa !9
  %22 = icmp ult i64 %.02731, %21
  %23 = zext i1 %22 to i64
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %1) #2
  %25 = load i64, ptr %24, align 8, !tbaa !5
  %26 = add i64 %25, %23
  store i64 %26, ptr %24, align 8, !tbaa !5
  %27 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %20) #2
  tail call void @_ZNK8graphlab22padded_simple_spinlock4lockEv(ptr noundef nonnull align 1 dereferenceable(1) %27)
  %28 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %20) #2
  %29 = tail call noundef zeroext i1 @_ZNKSt5dequeImSaImEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(80) %28) #2
  br i1 %29, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %17, %39
  %30 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %20) #2
  %31 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt5dequeImSaImEE5frontEv(ptr noundef nonnull align 8 dereferenceable(80) %30) #2
  %32 = load i64, ptr %31, align 8, !tbaa !5
  store i64 %32, ptr %2, align 8, !tbaa !5
  %33 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %20) #2
  tail call void @_ZNSt5dequeImSaImEE9pop_frontEv(ptr noundef nonnull align 8 dereferenceable(80) %33) #2
  %34 = load i64, ptr %2, align 8, !tbaa !5
  %35 = load i64, ptr %15, align 8, !tbaa !26
  %36 = icmp ult i64 %34, %35
  br i1 %36, label %37, label %39

37:                                               ; preds = %.lr.ph
  %38 = tail call noundef zeroext i1 @_ZN8graphlab12dense_bitset9clear_bitEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %34)
  br i1 %38, label %42, label %39

39:                                               ; preds = %37, %.lr.ph
  %40 = tail call noundef nonnull align 8 dereferenceable(80) ptr @_ZNSt6vectorISt5dequeImSaImEESaIS2_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %12, i64 noundef %20) #2
  %41 = tail call noundef zeroext i1 @_ZNKSt5dequeImSaImEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(80) %40) #2
  br i1 %41, label %.loopexit, label %.lr.ph, !llvm.loop !27

42:                                               ; preds = %37
  %43 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %20) #2
  tail call void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1) %43)
  br label %._crit_edge

.loopexit:                                        ; preds = %39, %17
  %44 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %20) #2
  tail call void @_ZNK8graphlab22padded_simple_spinlock6unlockEv(ptr noundef nonnull align 1 dereferenceable(1) %44)
  %45 = add nuw i64 %.02731, 1
  %46 = tail call noundef i64 @_ZNKSt6vectorISt5dequeImSaImEESaIS2_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #2
  %.not.not = icmp ult i64 %45, %46
  br i1 %.not.not, label %17, label %._crit_edge, !llvm.loop !29

._crit_edge:                                      ; preds = %.loopexit, %42, %3
  %.not.lcssa = phi i32 [ 1, %3 ], [ 0, %42 ], [ 1, %.loopexit ]
  ret i32 %.not.lcssa
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorImSaImEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZNKSt5dequeImSaImEE5emptyEv(ptr noundef nonnull align 8 dereferenceable(80)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt5dequeImSaImEE5frontEv(ptr noundef nonnull align 8 dereferenceable(80)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt5dequeImSaImEE9pop_frontEv(ptr noundef nonnull align 8 dereferenceable(80)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN8graphlab12dense_bitset9clear_bitEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !6, i64 112}
!10 = !{!"_ZTSN8graphlab14fifo_schedulerE", !11, i64 0, !12, i64 8, !14, i64 32, !18, i64 56, !22, i64 80, !6, i64 104, !6, i64 112, !6, i64 120}
!11 = !{!"_ZTSN8graphlab10ischedulerE"}
!12 = !{!"_ZTSN8graphlab12dense_bitsetE", !13, i64 0, !6, i64 8, !6, i64 16}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"_ZTSSt6vectorISt5dequeImSaImEESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseISt5dequeImSaImEESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseISt5dequeImSaImEESaIS2_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!18 = !{!"_ZTSSt6vectorIN8graphlab22padded_simple_spinlockESaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN8graphlab22padded_simple_spinlockESaIS1_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!22 = !{!"_ZTSSt6vectorImSaImEE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseImSaImEE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseImSaImEE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseImSaImEE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!26 = !{!10, !6, i64 120}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = distinct !{!29, !28}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass