; LLVM IR from devicehive/esp8266-firmware :: esp-utils/esp-terminal.ll (Z18SerialPortRecievedP10SerialPortPKcj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@term = external dso_local global ptr, align 8
@recieved = external dso_local global i32, align 4
@detectBuf = external dso_local global [7 x i8], align 1
@detectBufPos = external dso_local global i32, align 4
@isWorking = external dso_local global i8, align 1
@mCurrentPort = external dso_local global ptr, align 8

declare void @_ZN8Terminal3putEPKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z18SerialPortRecievedP10SerialPortPKcj(ptr noundef %0, ptr noundef %1, i32 noundef %2) #1 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !9
  %10 = load ptr, ptr @mCurrentPort, align 8, !tbaa !5
  %11 = icmp ne ptr %10, null
  br i1 %11, label %12, label %17

12:                                               ; preds = %3
  %13 = load ptr, ptr @mCurrentPort, align 8, !tbaa !5
  %14 = load ptr, ptr %4, align 8, !tbaa !5
  %15 = icmp ne ptr %13, %14
  br i1 %15, label %16, label %17

16:                                               ; preds = %12
  br label %92

17:                                               ; preds = %12, %3
  %18 = load i8, ptr @isWorking, align 1, !tbaa !11, !range !13, !noundef !14
  %19 = trunc i8 %18 to i1
  br i1 %19, label %20, label %43

20:                                               ; preds = %17
  br label %21

21:                                               ; preds = %30, %20
  %22 = load i32, ptr @recieved, align 4, !tbaa !9
  %23 = icmp slt i32 %22, 4
  br i1 %23, label %24, label %28

24:                                               ; preds = %21
  %25 = load ptr, ptr %5, align 8, !tbaa !5
  %26 = load i8, ptr %25, align 1, !tbaa !15
  %27 = icmp ne i8 %26, 0
  br label %28

28:                                               ; preds = %24, %21
  %29 = phi i1 [ false, %21 ], [ %27, %24 ]
  br i1 %29, label %30, label %35

30:                                               ; preds = %28
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds i8, ptr %31, i32 1
  store ptr %32, ptr %5, align 8, !tbaa !5
  %33 = load i32, ptr @recieved, align 4, !tbaa !9
  %34 = add nsw i32 %33, 1
  store i32 %34, ptr @recieved, align 4, !tbaa !9
  br label %21, !llvm.loop !16

35:                                               ; preds = %28
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = load i8, ptr %36, align 1, !tbaa !15
  %38 = icmp ne i8 %37, 0
  br i1 %38, label %39, label %42

39:                                               ; preds = %35
  %40 = load ptr, ptr @term, align 8, !tbaa !5
  %41 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_ZN8Terminal3putEPKc(ptr noundef nonnull align 8 dereferenceable(8) %40, ptr noundef %41)
  br label %42

42:                                               ; preds = %39, %35
  br label %92

43:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  br label %44

44:                                               ; preds = %88, %43
  %45 = load i32, ptr %7, align 4, !tbaa !9
  %46 = load i32, ptr %6, align 4, !tbaa !9
  %47 = icmp ult i32 %45, %46
  br i1 %47, label %49, label %48

48:                                               ; preds = %44
  store i32 4, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  br label %91

49:                                               ; preds = %44
  %50 = load i32, ptr @detectBufPos, align 4, !tbaa !9
  %51 = zext i32 %50 to i64
  %52 = icmp uge i64 %51, 6
  br i1 %52, label %53, label %77

53:                                               ; preds = %49
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !9
  br label %54

54:                                               ; preds = %68, %53
  %55 = load i32, ptr %9, align 4, !tbaa !9
  %56 = zext i32 %55 to i64
  %57 = icmp ult i64 %56, 6
  br i1 %57, label %59, label %58

58:                                               ; preds = %54
  store i32 7, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %71

59:                                               ; preds = %54
  %60 = load i32, ptr %9, align 4, !tbaa !9
  %61 = add i32 %60, 1
  %62 = zext i32 %61 to i64
  %63 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %62
  %64 = load i8, ptr %63, align 1, !tbaa !15
  %65 = load i32, ptr %9, align 4, !tbaa !9
  %66 = zext i32 %65 to i64
  %67 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %66
  store i8 %64, ptr %67, align 1, !tbaa !15
  br label %68

68:                                               ; preds = %59
  %69 = load i32, ptr %9, align 4, !tbaa !9
  %70 = add i32 %69, 1
  store i32 %70, ptr %9, align 4, !tbaa !9
  br label %54, !llvm.loop !18

71:                                               ; preds = %58
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  %73 = load i32, ptr %7, align 4, !tbaa !9
  %74 = zext i32 %73 to i64
  %75 = getelementptr inbounds i8, ptr %72, i64 %74
  %76 = load i8, ptr %75, align 1, !tbaa !15
  store i8 %76, ptr getelementptr inbounds ([7 x i8], ptr @detectBuf, i64 0, i64 5), align 1, !tbaa !15
  br label %87

77:                                               ; preds = %49
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = load i32, ptr %7, align 4, !tbaa !9
  %80 = zext i32 %79 to i64
  %81 = getelementptr inbounds i8, ptr %78, i64 %80
  %82 = load i8, ptr %81, align 1, !tbaa !15
  %83 = load i32, ptr @detectBufPos, align 4, !tbaa !9
  %84 = add i32 %83, 1
  store i32 %84, ptr @detectBufPos, align 4, !tbaa !9
  %85 = zext i32 %83 to i64
  %86 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %85
  store i8 %82, ptr %86, align 1, !tbaa !15
  br label %87

87:                                               ; preds = %77, %71
  br label %88

88:                                               ; preds = %87
  %89 = load i32, ptr %7, align 4, !tbaa !9
  %90 = add i32 %89, 1
  store i32 %90, ptr %7, align 4, !tbaa !9
  br label %44, !llvm.loop !19

91:                                               ; preds = %48
  br label %92

92:                                               ; preds = %91, %42, %16
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!7, !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = distinct !{!18, !17}
!19 = distinct !{!19, !17}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@term = external dso_local local_unnamed_addr global ptr, align 8
@recieved = external dso_local local_unnamed_addr global i32, align 4
@detectBuf = external dso_local local_unnamed_addr global [7 x i8], align 1
@detectBufPos = external dso_local local_unnamed_addr global i32, align 4
@isWorking = external dso_local local_unnamed_addr global i8, align 1
@mCurrentPort = external dso_local local_unnamed_addr global ptr, align 8

declare void @_ZN8Terminal3putEPKc(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_Z18SerialPortRecievedP10SerialPortPKcj(ptr noundef readnone %0, ptr noundef %1, i32 noundef %2) local_unnamed_addr #1 {
  %4 = load ptr, ptr @mCurrentPort, align 8, !tbaa !5
  %.not = icmp eq ptr %4, null
  %.not21 = icmp eq ptr %4, %0
  %or.cond = or i1 %.not, %.not21
  br i1 %or.cond, label %5, label %.critedge.thread

5:                                                ; preds = %3
  %6 = load i8, ptr @isWorking, align 1, !tbaa !9, !range !11, !noundef !12
  %7 = trunc nuw i8 %6 to i1
  br i1 %7, label %thread-pre-split, label %.preheader26

.preheader26:                                     ; preds = %5
  %.not33 = icmp eq i32 %2, 0
  br i1 %.not33, label %.critedge.thread, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %.preheader26
  %detectBufPos.promoted = load i32, ptr @detectBufPos, align 4, !tbaa !13
  %wide.trip.count = zext i32 %2 to i64
  %xtraiter = and i64 %wide.trip.count, 1
  %8 = icmp eq i32 %2, 1
  br i1 %8, label %.critedge.thread.loopexit40.unr-lcssa, label %.lr.ph.preheader.new

.lr.ph.preheader.new:                             ; preds = %.lr.ph.preheader
  %unroll_iter = and i64 %wide.trip.count, 4294967294
  br label %.lr.ph

thread-pre-split:                                 ; preds = %5
  %.pr = load i32, ptr @recieved, align 4, !tbaa !13
  %9 = icmp slt i32 %.pr, 4
  br i1 %9, label %.lr.ph32.preheader, label %.critedge

.lr.ph32.preheader:                               ; preds = %thread-pre-split
  %10 = sub i32 3, %.pr
  %11 = zext i32 %10 to i64
  %12 = getelementptr i8, ptr %1, i64 %11
  %scevgep = getelementptr i8, ptr %12, i64 1
  br label %.lr.ph32

.lr.ph32:                                         ; preds = %.lr.ph32.preheader, %15
  %.01631 = phi ptr [ %16, %15 ], [ %1, %.lr.ph32.preheader ]
  %13 = phi i32 [ %17, %15 ], [ %.pr, %.lr.ph32.preheader ]
  %14 = load i8, ptr %.01631, align 1, !tbaa !15
  %.not22 = icmp eq i8 %14, 0
  br i1 %.not22, label %.critedge.thread, label %15

15:                                               ; preds = %.lr.ph32
  %16 = getelementptr inbounds i8, ptr %.01631, i64 1
  %17 = add i32 %13, 1
  store i32 %17, ptr @recieved, align 4, !tbaa !13
  %exitcond37.not = icmp eq i32 %17, 4
  br i1 %exitcond37.not, label %.critedge, label %.lr.ph32, !llvm.loop !16

.critedge:                                        ; preds = %15, %thread-pre-split
  %.016.lcssa = phi ptr [ %1, %thread-pre-split ], [ %scevgep, %15 ]
  %.pr24 = load i8, ptr %.016.lcssa, align 1, !tbaa !15
  %.not23 = icmp eq i8 %.pr24, 0
  br i1 %.not23, label %.critedge.thread, label %18

18:                                               ; preds = %.critedge
  %19 = load ptr, ptr @term, align 8, !tbaa !5
  tail call void @_ZN8Terminal3putEPKc(ptr noundef nonnull align 8 dereferenceable(8) %19, ptr noundef nonnull %.016.lcssa)
  br label %.critedge.thread

.lr.ph:                                           ; preds = %38, %.lr.ph.preheader.new
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader.new ], [ %indvars.iv.next.1, %38 ]
  %20 = phi i32 [ %detectBufPos.promoted, %.lr.ph.preheader.new ], [ %39, %38 ]
  %niter = phi i64 [ 0, %.lr.ph.preheader.new ], [ %niter.next.1, %38 ]
  %21 = icmp ugt i32 %20, 5
  %22 = getelementptr inbounds i8, ptr %1, i64 %indvars.iv
  br i1 %21, label %.preheader.preheader, label %24

.preheader.preheader:                             ; preds = %.lr.ph
  tail call void @llvm.memmove.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(6) @detectBuf, ptr noundef nonnull align 1 dereferenceable(6) getelementptr inbounds (i8, ptr @detectBuf, i64 1), i64 6, i1 false), !tbaa !15
  %23 = load i8, ptr %22, align 1, !tbaa !15
  store i8 %23, ptr getelementptr inbounds (i8, ptr @detectBuf, i64 5), align 1, !tbaa !15
  br label %.lr.ph.1

24:                                               ; preds = %.lr.ph
  %25 = zext nneg i32 %20 to i64
  %26 = load i8, ptr %22, align 1, !tbaa !15
  %27 = add nuw nsw i32 %20, 1
  store i32 %27, ptr @detectBufPos, align 4, !tbaa !13
  %28 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %25
  store i8 %26, ptr %28, align 1, !tbaa !15
  br label %.lr.ph.1

.lr.ph.1:                                         ; preds = %.preheader.preheader, %24
  %29 = phi i32 [ %20, %.preheader.preheader ], [ %27, %24 ]
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %30 = icmp ugt i32 %29, 5
  %31 = getelementptr inbounds i8, ptr %1, i64 %indvars.iv.next
  br i1 %30, label %.preheader.preheader.1, label %32

32:                                               ; preds = %.lr.ph.1
  %33 = zext nneg i32 %29 to i64
  %34 = load i8, ptr %31, align 1, !tbaa !15
  %35 = add nuw nsw i32 %29, 1
  store i32 %35, ptr @detectBufPos, align 4, !tbaa !13
  %36 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %33
  store i8 %34, ptr %36, align 1, !tbaa !15
  br label %38

.preheader.preheader.1:                           ; preds = %.lr.ph.1
  tail call void @llvm.memmove.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(6) @detectBuf, ptr noundef nonnull align 1 dereferenceable(6) getelementptr inbounds (i8, ptr @detectBuf, i64 1), i64 6, i1 false), !tbaa !15
  %37 = load i8, ptr %31, align 1, !tbaa !15
  store i8 %37, ptr getelementptr inbounds (i8, ptr @detectBuf, i64 5), align 1, !tbaa !15
  br label %38

38:                                               ; preds = %.preheader.preheader.1, %32
  %39 = phi i32 [ %29, %.preheader.preheader.1 ], [ %35, %32 ]
  %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
  %niter.next.1 = add i64 %niter, 2
  %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
  br i1 %niter.ncmp.1, label %.critedge.thread.loopexit40.unr-lcssa, label %.lr.ph, !llvm.loop !18

.critedge.thread.loopexit40.unr-lcssa:            ; preds = %38, %.lr.ph.preheader
  %indvars.iv.unr = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next.1, %38 ]
  %.unr = phi i32 [ %detectBufPos.promoted, %.lr.ph.preheader ], [ %39, %38 ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %.critedge.thread, label %.lr.ph.epil

.lr.ph.epil:                                      ; preds = %.critedge.thread.loopexit40.unr-lcssa
  %40 = icmp ugt i32 %.unr, 5
  %41 = getelementptr inbounds i8, ptr %1, i64 %indvars.iv.unr
  br i1 %40, label %.preheader.preheader.epil, label %42

42:                                               ; preds = %.lr.ph.epil
  %43 = zext nneg i32 %.unr to i64
  %44 = load i8, ptr %41, align 1, !tbaa !15
  %45 = add nuw nsw i32 %.unr, 1
  store i32 %45, ptr @detectBufPos, align 4, !tbaa !13
  %46 = getelementptr inbounds [7 x i8], ptr @detectBuf, i64 0, i64 %43
  store i8 %44, ptr %46, align 1, !tbaa !15
  br label %.critedge.thread

.preheader.preheader.epil:                        ; preds = %.lr.ph.epil
  tail call void @llvm.memmove.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(6) @detectBuf, ptr noundef nonnull align 1 dereferenceable(6) getelementptr inbounds (i8, ptr @detectBuf, i64 1), i64 6, i1 false), !tbaa !15
  %47 = load i8, ptr %41, align 1, !tbaa !15
  store i8 %47, ptr getelementptr inbounds (i8, ptr @detectBuf, i64 5), align 1, !tbaa !15
  br label %.critedge.thread

.critedge.thread:                                 ; preds = %.critedge.thread.loopexit40.unr-lcssa, %.preheader.preheader.epil, %42, %.lr.ph32, %.preheader26, %3, %.critedge, %18
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!7, !7, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = distinct !{!18, !17}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopIdiomRecognizePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass