; LLVM IR from vss2sn/cvrp :: src/genetic_algorithm.ll (ZNK10GASolution13checkValidityEi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.GASolution = type <{ %class.Solution, i32, i32, i64, %"class.std::vector.10", i64, %"class.std::vector.15", %"class.std::vector.15", i32, [4 x i8] }>
%class.Solution = type { ptr, %"class.std::vector", %"class.std::vector.0", %"class.std::vector.5", %struct.Node, i32 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<Node, std::allocator<Node>>::_Vector_impl" }
%"struct.std::_Vector_base<Node, std::allocator<Node>>::_Vector_impl" = type { %"struct.std::_Vector_base<Node, std::allocator<Node>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Node, std::allocator<Node>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<Vehicle, std::allocator<Vehicle>>::_Vector_impl" }
%"struct.std::_Vector_base<Vehicle, std::allocator<Vehicle>>::_Vector_impl" = type { %"struct.std::_Vector_base<Vehicle, std::allocator<Vehicle>>::_Vector_impl_data" }
%"struct.std::_Vector_base<Vehicle, std::allocator<Vehicle>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<double>, std::allocator<std::vector<double>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.Node = type <{ i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl" = type { %"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" }
%"struct.std::_Vector_base<double, std::allocator<double>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZNK10GASolution13checkValidityEi(ptr noundef nonnull align 8 dereferenceable(204) %0, i32 noundef %1) #1 align 2 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %10 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %67, %2
  %12 = load i32, ptr %6, align 4, !tbaa !9
  %13 = sext i32 %12 to i64
  %14 = getelementptr inbounds %class.GASolution, ptr %10, i32 0, i32 5
  %15 = load i64, ptr %14, align 8, !tbaa !11
  %16 = icmp ult i64 %13, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %11
  store i32 2, ptr %7, align 4
  br label %70

18:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %19 = getelementptr inbounds %class.Solution, ptr %10, i32 0, i32 5
  %20 = load i32, ptr %19, align 4, !tbaa !37
  store i32 %20, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #2
  %21 = getelementptr inbounds %class.GASolution, ptr %10, i32 0, i32 7
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %23) #2
  %25 = load i32, ptr %6, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %26) #2
  %28 = load i32, ptr %27, align 4, !tbaa !9
  store i32 %28, ptr %9, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %41, %18
  %30 = load i32, ptr %9, align 4, !tbaa !9
  %31 = getelementptr inbounds %class.GASolution, ptr %10, i32 0, i32 7
  %32 = load i32, ptr %5, align 4, !tbaa !9
  %33 = sext i32 %32 to i64
  %34 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %31, i64 noundef %33) #2
  %35 = load i32, ptr %6, align 4, !tbaa !9
  %36 = add nsw i32 %35, 1
  %37 = sext i32 %36 to i64
  %38 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %34, i64 noundef %37) #2
  %39 = load i32, ptr %38, align 4, !tbaa !9
  %40 = icmp slt i32 %30, %39
  br i1 %40, label %41, label %59

41:                                               ; preds = %29
  %42 = getelementptr inbounds %class.Solution, ptr %10, i32 0, i32 1
  %43 = getelementptr inbounds %class.GASolution, ptr %10, i32 0, i32 6
  %44 = load i32, ptr %5, align 4, !tbaa !9
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %43, i64 noundef %45) #2
  %47 = load i32, ptr %9, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %46, i64 noundef %48) #2
  %50 = load i32, ptr %49, align 4, !tbaa !9
  %51 = sext i32 %50 to i64
  %52 = call noundef nonnull align 4 dereferenceable(17) ptr @_ZNKSt6vectorI4NodeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %42, i64 noundef %51) #2
  %53 = getelementptr inbounds %struct.Node, ptr %52, i32 0, i32 3
  %54 = load i32, ptr %53, align 4, !tbaa !38
  %55 = load i32, ptr %8, align 4, !tbaa !9
  %56 = sub nsw i32 %55, %54
  store i32 %56, ptr %8, align 4, !tbaa !9
  %57 = load i32, ptr %9, align 4, !tbaa !9
  %58 = add nsw i32 %57, 1
  store i32 %58, ptr %9, align 4, !tbaa !9
  br label %29, !llvm.loop !39

59:                                               ; preds = %29
  %60 = load i32, ptr %8, align 4, !tbaa !9
  %61 = icmp slt i32 %60, 0
  br i1 %61, label %62, label %63

62:                                               ; preds = %59
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %64

63:                                               ; preds = %59
  store i32 0, ptr %7, align 4
  br label %64

64:                                               ; preds = %63, %62
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  %65 = load i32, ptr %7, align 4
  switch i32 %65, label %70 [
    i32 0, label %66
  ]

66:                                               ; preds = %64
  br label %67

67:                                               ; preds = %66
  %68 = load i32, ptr %6, align 4, !tbaa !9
  %69 = add nsw i32 %68, 1
  store i32 %69, ptr %6, align 4, !tbaa !9
  br label %11, !llvm.loop !41

70:                                               ; preds = %64, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %71 = load i32, ptr %7, align 4
  switch i32 %71, label %75 [
    i32 2, label %72
    i32 1, label %73
  ]

72:                                               ; preds = %70
  store i1 true, ptr %3, align 1
  br label %73

73:                                               ; preds = %72, %70
  %74 = load i1, ptr %3, align 1
  ret i1 %74

75:                                               ; preds = %70
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(17) ptr @_ZNKSt6vectorI4NodeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !28, i64 144}
!12 = !{!"_ZTS10GASolution", !13, i64 0, !10, i64 104, !10, i64 108, !28, i64 112, !29, i64 120, !28, i64 144, !33, i64 152, !33, i64 176, !10, i64 200}
!13 = !{!"_ZTS8Solution", !14, i64 8, !18, i64 32, !22, i64 56, !26, i64 80, !10, i64 100}
!14 = !{!"_ZTSSt6vectorI4NodeSaIS0_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseI4NodeSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseI4NodeSaIS0_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI4NodeSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorI7VehicleSaIS0_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseI7VehicleSaIS0_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseI7VehicleSaIS0_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseI7VehicleSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIS_IdSaIdEESaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTS4Node", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !27, i64 16}
!27 = !{!"bool", !7, i64 0}
!28 = !{!"long", !7, i64 0}
!29 = !{!"_ZTSSt6vectorIdSaIdEE", !30, i64 0}
!30 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !32, i64 0}
!32 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!33 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !34, i64 0}
!34 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !35, i64 0}
!35 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !36, i64 0}
!36 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!37 = !{!13, !10, i64 100}
!38 = !{!26, !10, i64 12}
!39 = distinct !{!39, !40}
!40 = !{!"llvm.loop.mustprogress"}
!41 = distinct !{!41, !40}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZNK10GASolution13checkValidityEi(ptr noundef nonnull align 8 dereferenceable(204) %0, i32 noundef %1) local_unnamed_addr #0 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 144
  %4 = getelementptr inbounds i8, ptr %0, i64 100
  %5 = getelementptr inbounds i8, ptr %0, i64 176
  %6 = sext i32 %1 to i64
  %7 = getelementptr inbounds i8, ptr %0, i64 8
  %8 = getelementptr inbounds i8, ptr %0, i64 152
  br label %9

9:                                                ; preds = %._crit_edge, %2
  %indvars.iv27 = phi i64 [ %indvars.iv.next28, %._crit_edge ], [ 0, %2 ]
  %10 = load i64, ptr %3, align 8, !tbaa !5
  %.not = icmp ule i64 %10, %indvars.iv27
  br i1 %.not, label %35, label %11

11:                                               ; preds = %9
  %12 = load i32, ptr %4, align 4, !tbaa !35
  %13 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %6) #1
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %indvars.iv27) #1
  %15 = load i32, ptr %14, align 4, !tbaa !36
  %16 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %6) #1
  %indvars.iv.next28 = add nuw nsw i64 %indvars.iv27, 1
  %17 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %indvars.iv.next28) #1
  %18 = load i32, ptr %17, align 4, !tbaa !36
  %19 = icmp slt i32 %15, %18
  br i1 %19, label %.lr.ph.preheader, label %._crit_edge

.lr.ph.preheader:                                 ; preds = %11
  %20 = sext i32 %15 to i64
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %indvars.iv = phi i64 [ %20, %.lr.ph.preheader ], [ %indvars.iv.next, %.lr.ph ]
  %.01522 = phi i32 [ %12, %.lr.ph.preheader ], [ %28, %.lr.ph ]
  %21 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %6) #1
  %22 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %indvars.iv) #1
  %23 = load i32, ptr %22, align 4, !tbaa !36
  %24 = sext i32 %23 to i64
  %25 = tail call noundef nonnull align 4 dereferenceable(17) ptr @_ZNKSt6vectorI4NodeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %24) #1
  %26 = getelementptr inbounds i8, ptr %25, i64 12
  %27 = load i32, ptr %26, align 4, !tbaa !37
  %28 = sub nsw i32 %.01522, %27
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %29 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %6) #1
  %30 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNKSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %indvars.iv.next28) #1
  %31 = load i32, ptr %30, align 4, !tbaa !36
  %32 = sext i32 %31 to i64
  %33 = icmp slt i64 %indvars.iv.next, %32
  br i1 %33, label %.lr.ph, label %._crit_edge, !llvm.loop !38

._crit_edge:                                      ; preds = %.lr.ph, %11
  %.015.lcssa = phi i32 [ %12, %11 ], [ %28, %.lr.ph ]
  %34 = icmp sgt i32 %.015.lcssa, -1
  br i1 %34, label %9, label %35, !llvm.loop !40

35:                                               ; preds = %9, %._crit_edge
  ret i1 %.not
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(17) ptr @_ZNKSt6vectorI4NodeSaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !26, i64 144}
!6 = !{!"_ZTS10GASolution", !7, i64 0, !24, i64 104, !24, i64 108, !26, i64 112, !27, i64 120, !26, i64 144, !31, i64 152, !31, i64 176, !24, i64 200}
!7 = !{!"_ZTS8Solution", !8, i64 8, !15, i64 32, !19, i64 56, !23, i64 80, !24, i64 100}
!8 = !{!"_ZTSSt6vectorI4NodeSaIS0_EE", !9, i64 0}
!9 = !{!"_ZTSSt12_Vector_baseI4NodeSaIS0_EE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseI4NodeSaIS0_EE12_Vector_implE", !11, i64 0}
!11 = !{!"_ZTSNSt12_Vector_baseI4NodeSaIS0_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!12 = !{!"any pointer", !13, i64 0}
!13 = !{!"omnipotent char", !14, i64 0}
!14 = !{!"Simple C++ TBAA"}
!15 = !{!"_ZTSSt6vectorI7VehicleSaIS0_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseI7VehicleSaIS0_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseI7VehicleSaIS0_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseI7VehicleSaIS0_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!19 = !{!"_ZTSSt6vectorIS_IdSaIdEESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseISt6vectorIdSaIdEESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!23 = !{!"_ZTS4Node", !24, i64 0, !24, i64 4, !24, i64 8, !24, i64 12, !25, i64 16}
!24 = !{!"int", !13, i64 0}
!25 = !{!"bool", !13, i64 0}
!26 = !{!"long", !13, i64 0}
!27 = !{!"_ZTSSt6vectorIdSaIdEE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIdSaIdEE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!31 = !{!"_ZTSSt6vectorIS_IiSaIiEESaIS1_EE", !32, i64 0}
!32 = !{!"_ZTSSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE", !33, i64 0}
!33 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE12_Vector_implE", !34, i64 0}
!34 = !{!"_ZTSNSt12_Vector_baseISt6vectorIiSaIiEESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!35 = !{!7, !24, i64 100}
!36 = !{!24, !24, i64 0}
!37 = !{!23, !24, i64 12}
!38 = distinct !{!38, !39}
!39 = !{!"llvm.loop.mustprogress"}
!40 = distinct !{!40, !39}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass