; LLVM IR from devicehive/esp8266-firmware :: firmware-src/sources/devices (mfrc522)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_chipSelectPin = external hidden global i32, align 4

declare i32 @dh_spi_set_cs_pin(i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @dh_spi_set_mode(i32 noundef) #0

declare void @dh_spi_write(ptr noundef, i32 noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @dh_spi_read(ptr noundef, i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local void @MFRC522_PCD_ReadRegister_n(i8 noundef zeroext %0, i8 noundef zeroext %1, ptr noundef %2, i8 noundef zeroext %3) #2 {
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i8, align 1
  %13 = alloca i8, align 1
  store i8 %0, ptr %5, align 1, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !8
  store i8 %3, ptr %8, align 1, !tbaa !5
  %14 = load i8, ptr %6, align 1, !tbaa !5
  %15 = zext i8 %14 to i32
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %4
  br label %93

18:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  %19 = load i8, ptr %5, align 1, !tbaa !5
  %20 = zext i8 %19 to i32
  %21 = and i32 %20, 126
  %22 = or i32 128, %21
  %23 = trunc i32 %22 to i8
  store i8 %23, ptr %9, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  store i8 0, ptr %10, align 1, !tbaa !5
  %24 = call i32 @dh_spi_set_mode(i32 noundef 0)
  %25 = load i32, ptr @_chipSelectPin, align 4, !tbaa !10
  %26 = call i32 @dh_spi_set_cs_pin(i32 noundef %25)
  %27 = load i8, ptr %6, align 1, !tbaa !5
  %28 = add i8 %27, -1
  store i8 %28, ptr %6, align 1, !tbaa !5
  call void @dh_spi_write(ptr noundef %9, i32 noundef 1, i32 noundef 0)
  br label %29

29:                                               ; preds = %85, %18
  %30 = load i8, ptr %10, align 1, !tbaa !5
  %31 = zext i8 %30 to i32
  %32 = load i8, ptr %6, align 1, !tbaa !5
  %33 = zext i8 %32 to i32
  %34 = icmp slt i32 %31, %33
  br i1 %34, label %35, label %88

35:                                               ; preds = %29
  %36 = load i8, ptr %10, align 1, !tbaa !5
  %37 = zext i8 %36 to i32
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %39, label %80

39:                                               ; preds = %35
  %40 = load i8, ptr %8, align 1, !tbaa !5
  %41 = zext i8 %40 to i32
  %42 = icmp ne i32 %41, 0
  br i1 %42, label %43, label %80

43:                                               ; preds = %39
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #3
  store i8 0, ptr %11, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %12) #3
  %44 = load i8, ptr %8, align 1, !tbaa !5
  store i8 %44, ptr %12, align 1, !tbaa !5
  br label %45

45:                                               ; preds = %57, %43
  %46 = load i8, ptr %12, align 1, !tbaa !5
  %47 = zext i8 %46 to i32
  %48 = icmp sle i32 %47, 7
  br i1 %48, label %49, label %60

49:                                               ; preds = %45
  %50 = load i8, ptr %12, align 1, !tbaa !5
  %51 = zext i8 %50 to i32
  %52 = shl i32 1, %51
  %53 = load i8, ptr %11, align 1, !tbaa !5
  %54 = zext i8 %53 to i32
  %55 = or i32 %54, %52
  %56 = trunc i32 %55 to i8
  store i8 %56, ptr %11, align 1, !tbaa !5
  br label %57

57:                                               ; preds = %49
  %58 = load i8, ptr %12, align 1, !tbaa !5
  %59 = add i8 %58, 1
  store i8 %59, ptr %12, align 1, !tbaa !5
  br label %45, !llvm.loop !12

60:                                               ; preds = %45
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #3
  call void @dh_spi_read(ptr noundef %13, i32 noundef 1)
  call void @dh_spi_write(ptr noundef %9, i32 noundef 1, i32 noundef 0)
  %61 = load ptr, ptr %7, align 8, !tbaa !8
  %62 = load i8, ptr %10, align 1, !tbaa !5
  %63 = zext i8 %62 to i64
  %64 = getelementptr inbounds i8, ptr %61, i64 %63
  %65 = load i8, ptr %64, align 1, !tbaa !5
  %66 = zext i8 %65 to i32
  %67 = load i8, ptr %11, align 1, !tbaa !5
  %68 = zext i8 %67 to i32
  %69 = xor i32 %68, -1
  %70 = and i32 %66, %69
  %71 = load i8, ptr %13, align 1, !tbaa !5
  %72 = zext i8 %71 to i32
  %73 = load i8, ptr %11, align 1, !tbaa !5
  %74 = zext i8 %73 to i32
  %75 = and i32 %72, %74
  %76 = or i32 %70, %75
  %77 = trunc i32 %76 to i8
  %78 = load ptr, ptr %7, align 8, !tbaa !8
  %79 = getelementptr inbounds i8, ptr %78, i64 0
  store i8 %77, ptr %79, align 1, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #3
  br label %85

80:                                               ; preds = %39, %35
  %81 = load ptr, ptr %7, align 8, !tbaa !8
  %82 = load i8, ptr %10, align 1, !tbaa !5
  %83 = zext i8 %82 to i64
  %84 = getelementptr inbounds i8, ptr %81, i64 %83
  call void @dh_spi_read(ptr noundef %84, i32 noundef 1)
  call void @dh_spi_write(ptr noundef %9, i32 noundef 1, i32 noundef 0)
  br label %85

85:                                               ; preds = %80, %60
  %86 = load i8, ptr %10, align 1, !tbaa !5
  %87 = add i8 %86, 1
  store i8 %87, ptr %10, align 1, !tbaa !5
  br label %29, !llvm.loop !14

88:                                               ; preds = %29
  %89 = load ptr, ptr %7, align 8, !tbaa !8
  %90 = load i8, ptr %10, align 1, !tbaa !5
  %91 = zext i8 %90 to i64
  %92 = getelementptr inbounds i8, ptr %89, i64 %91
  call void @dh_spi_read(ptr noundef %92, i32 noundef 1)
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  br label %93

93:                                               ; preds = %88, %17
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !6, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = distinct !{!14, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_chipSelectPin = external hidden local_unnamed_addr global i32, align 4

declare i32 @dh_spi_set_cs_pin(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @dh_spi_set_mode(i32 noundef) local_unnamed_addr #0

declare void @dh_spi_write(ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare void @dh_spi_read(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @MFRC522_PCD_ReadRegister_n(i8 noundef zeroext %0, i8 noundef zeroext %1, ptr noundef %2, i8 noundef zeroext %3) local_unnamed_addr #2 {
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = icmp eq i8 %1, 0
  br i1 %7, label %36, label %8

8:                                                ; preds = %4
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #3
  %9 = and i8 %0, 126
  %10 = or disjoint i8 %9, -128
  store i8 %10, ptr %5, align 1, !tbaa !5
  %11 = tail call i32 @dh_spi_set_mode(i32 noundef 0) #3
  %12 = load i32, ptr @_chipSelectPin, align 4, !tbaa !8
  %13 = tail call i32 @dh_spi_set_cs_pin(i32 noundef %12) #3
  %14 = add i8 %1, -1
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  %.not = icmp eq i8 %14, 0
  br i1 %.not, label %._crit_edge32, label %.lr.ph31

.lr.ph31:                                         ; preds = %8
  %.not37 = icmp eq i8 %3, 0
  br i1 %.not37, label %.lr.ph31.split.us.preheader, label %.lr.ph31.split

.lr.ph31.split.us.preheader:                      ; preds = %.lr.ph31
  %wide.trip.count57 = zext i8 %14 to i64
  br label %.lr.ph31.split.us

.lr.ph31.split.us:                                ; preds = %.lr.ph31.split.us.preheader, %.lr.ph31.split.us
  %indvars.iv54 = phi i64 [ 0, %.lr.ph31.split.us.preheader ], [ %indvars.iv.next55, %.lr.ph31.split.us ]
  %15 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv54
  call void @dh_spi_read(ptr noundef %15, i32 noundef 1) #3
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  %indvars.iv.next55 = add nuw nsw i64 %indvars.iv54, 1
  %exitcond58.not = icmp eq i64 %indvars.iv.next55, %wide.trip.count57
  br i1 %exitcond58.not, label %._crit_edge32, label %.lr.ph31.split.us, !llvm.loop !10

.lr.ph31.split:                                   ; preds = %.lr.ph31
  %16 = icmp ult i8 %3, 8
  br i1 %16, label %.lr.ph31.split.split.us.preheader, label %17

17:                                               ; preds = %.lr.ph31.split
  %wide.trip.count = zext i8 %14 to i64
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #3
  call void @dh_spi_read(ptr noundef nonnull %6, i32 noundef 1) #3
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #3
  %exitcond.peel.not = icmp eq i8 %14, 1
  br i1 %exitcond.peel.not, label %._crit_edge32, label %.lr.ph31.split.split.peel.next

.lr.ph31.split.split.us.preheader:                ; preds = %.lr.ph31.split
  %18 = zext nneg i8 %3 to i32
  %wide.trip.count52 = zext i8 %14 to i64
  br label %.lr.ph31.split.split.us

.lr.ph31.split.split.us:                          ; preds = %.lr.ph31.split.split.us.preheader, %22
  %indvars.iv49 = phi i64 [ 0, %.lr.ph31.split.split.us.preheader ], [ %indvars.iv.next50, %22 ]
  %19 = icmp eq i64 %indvars.iv49, 0
  br i1 %19, label %.preheader.us, label %20

20:                                               ; preds = %.lr.ph31.split.split.us
  %21 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv49
  call void @dh_spi_read(ptr noundef nonnull %21, i32 noundef 1) #3
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  br label %22

22:                                               ; preds = %._crit_edge.us, %20
  %indvars.iv.next50 = add nuw nsw i64 %indvars.iv49, 1
  %exitcond53.not = icmp eq i64 %indvars.iv.next50, %wide.trip.count52
  br i1 %exitcond53.not, label %._crit_edge32, label %.lr.ph31.split.split.us, !llvm.loop !10

.preheader.us:                                    ; preds = %.lr.ph31.split.split.us, %.preheader.us
  %indvars.iv45 = phi i32 [ %indvars.iv.next46, %.preheader.us ], [ %18, %.lr.ph31.split.split.us ]
  %.02327.us = phi i8 [ %25, %.preheader.us ], [ 0, %.lr.ph31.split.split.us ]
  %23 = shl nuw nsw i32 1, %indvars.iv45
  %24 = trunc nuw i32 %23 to i8
  %25 = or i8 %.02327.us, %24
  %indvars.iv.next46 = add nuw nsw i32 %indvars.iv45, 1
  %26 = and i32 %indvars.iv.next46, 255
  %exitcond48.not = icmp eq i32 %26, 8
  br i1 %exitcond48.not, label %._crit_edge.us, label %.preheader.us, !llvm.loop !12

._crit_edge.us:                                   ; preds = %.preheader.us
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #3
  call void @dh_spi_read(ptr noundef nonnull %6, i32 noundef 1) #3
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  %27 = load i8, ptr %2, align 1, !tbaa !5
  %28 = xor i8 %25, -1
  %29 = and i8 %27, %28
  %30 = load i8, ptr %6, align 1, !tbaa !5
  %31 = and i8 %30, %25
  %32 = or i8 %31, %29
  store i8 %32, ptr %2, align 1, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #3
  br label %22

.lr.ph31.split.split.peel.next:                   ; preds = %17, %.lr.ph31.split.split.peel.next
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph31.split.split.peel.next ], [ 1, %17 ]
  %33 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv
  call void @dh_spi_read(ptr noundef nonnull %33, i32 noundef 1) #3
  call void @dh_spi_write(ptr noundef nonnull %5, i32 noundef 1, i32 noundef 0) #3
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %._crit_edge32, label %.lr.ph31.split.split.peel.next, !llvm.loop !13

._crit_edge32:                                    ; preds = %.lr.ph31.split.split.peel.next, %22, %.lr.ph31.split.us, %17, %8
  %34 = zext i8 %14 to i64
  %35 = getelementptr inbounds i8, ptr %2, i64 %34
  call void @dh_spi_read(ptr noundef %35, i32 noundef 1) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #3
  br label %36

36:                                               ; preds = %4, %._crit_edge32
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}
!13 = distinct !{!13, !11, !14}
!14 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopFullUnrollPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass