; LLVM IR from tum-i4/obfuscation-benchmarks :: tigress-generated-programs (RandomFunc)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @RandomFunc(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca [1 x i8], align 1
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %8, i64 0
  %10 = load i8, ptr %9, align 1, !tbaa !9
  %11 = zext i8 %10 to i64
  %12 = add i64 %11, 914778474
  %13 = mul i64 %12, 22
  %14 = trunc i64 %13 to i8
  %15 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  store i8 %14, ptr %15, align 1, !tbaa !9
  store i8 0, ptr %7, align 1, !tbaa !9
  br label %16

16:                                               ; preds = %66, %2
  %17 = load i8, ptr %7, align 1, !tbaa !9
  %18 = zext i8 %17 to i32
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = getelementptr inbounds i8, ptr %19, i64 1
  %21 = load i8, ptr %20, align 1, !tbaa !9
  %22 = zext i8 %21 to i32
  %23 = icmp slt i32 %18, %22
  br i1 %23, label %24, label %69

24:                                               ; preds = %16
  store i8 0, ptr %6, align 1, !tbaa !9
  br label %25

25:                                               ; preds = %63, %24
  %26 = load i8, ptr %6, align 1, !tbaa !9
  %27 = zext i8 %26 to i32
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = getelementptr inbounds i8, ptr %28, i64 1
  %30 = load i8, ptr %29, align 1, !tbaa !9
  %31 = zext i8 %30 to i32
  %32 = icmp slt i32 %27, %31
  br i1 %32, label %33, label %66

33:                                               ; preds = %25
  %34 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  %35 = load i8, ptr %34, align 1, !tbaa !9
  %36 = zext i8 %35 to i32
  %37 = load i8, ptr %6, align 1, !tbaa !9
  %38 = zext i8 %37 to i32
  %39 = load i8, ptr %7, align 1, !tbaa !9
  %40 = zext i8 %39 to i32
  %41 = add nsw i32 %38, %40
  %42 = icmp slt i32 %36, %41
  br i1 %42, label %43, label %54

43:                                               ; preds = %33
  %44 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  %45 = load i8, ptr %44, align 1, !tbaa !9
  %46 = zext i8 %45 to i32
  %47 = load i8, ptr %6, align 1, !tbaa !9
  %48 = zext i8 %47 to i64
  %49 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 %48
  %50 = load i8, ptr %49, align 1, !tbaa !9
  %51 = zext i8 %50 to i32
  %52 = add nsw i32 %51, %46
  %53 = trunc i32 %52 to i8
  store i8 %53, ptr %49, align 1, !tbaa !9
  br label %63

54:                                               ; preds = %33
  %55 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  %56 = load i8, ptr %55, align 1, !tbaa !9
  %57 = zext i8 %56 to i32
  %58 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  %59 = load i8, ptr %58, align 1, !tbaa !9
  %60 = zext i8 %59 to i32
  %61 = mul nsw i32 %60, %57
  %62 = trunc i32 %61 to i8
  store i8 %62, ptr %58, align 1, !tbaa !9
  br label %63

63:                                               ; preds = %54, %43
  %64 = load i8, ptr %6, align 1, !tbaa !9
  %65 = add i8 %64, 1
  store i8 %65, ptr %6, align 1, !tbaa !9
  br label %25, !llvm.loop !10

66:                                               ; preds = %25
  %67 = load i8, ptr %7, align 1, !tbaa !9
  %68 = add i8 %67, 1
  store i8 %68, ptr %7, align 1, !tbaa !9
  br label %16, !llvm.loop !12

69:                                               ; preds = %16
  %70 = getelementptr inbounds [1 x i8], ptr %5, i64 0, i64 0
  %71 = load i8, ptr %70, align 1, !tbaa !9
  %72 = zext i8 %71 to i64
  %73 = sub i64 %72, 304314215
  %74 = add i64 %73, 127
  %75 = trunc i64 %74 to i8
  %76 = load ptr, ptr %4, align 8, !tbaa !5
  %77 = getelementptr inbounds i8, ptr %76, i64 0
  store i8 %75, ptr %77, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable
define dso_local void @RandomFunc(ptr nocapture noundef readonly %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = load i8, ptr %0, align 1, !tbaa !5
  %4 = mul i8 %3, 22
  %5 = add i8 %4, 28
  %6 = getelementptr inbounds i8, ptr %0, i64 1
  %7 = load i8, ptr %6, align 1, !tbaa !5
  %.not = icmp eq i8 %7, 0
  br i1 %.not, label %._crit_edge, label %.preheader.preheader

.preheader.preheader:                             ; preds = %2
  %wide.trip.count24 = zext i8 %7 to i32
  %xtraiter = and i32 %wide.trip.count24, 1
  %8 = icmp eq i8 %7, 1
  %unroll_iter = and i32 %wide.trip.count24, 254
  %lcmp.mod.not = icmp eq i32 %xtraiter, 0
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %24
  %indvars.iv21 = phi i32 [ 0, %.preheader.preheader ], [ %indvars.iv.next22, %24 ]
  %.sroa.0.018 = phi i8 [ %5, %.preheader.preheader ], [ %storemerge.lcssa, %24 ]
  br i1 %8, label %.unr-lcssa, label %.preheader.new

.preheader.new:                                   ; preds = %.preheader, %.preheader.new
  %indvars.iv = phi i32 [ %indvars.iv.next.1, %.preheader.new ], [ 0, %.preheader ]
  %.sroa.0.116 = phi i8 [ %storemerge.1, %.preheader.new ], [ %.sroa.0.018, %.preheader ]
  %niter = phi i32 [ %niter.next.1, %.preheader.new ], [ 0, %.preheader ]
  %9 = zext i8 %.sroa.0.116 to i32
  %10 = add nuw nsw i32 %indvars.iv21, %indvars.iv
  %11 = icmp ugt i32 %10, %9
  %12 = shl i8 %.sroa.0.116, 1
  %13 = mul i8 %.sroa.0.116, %.sroa.0.116
  %storemerge = select i1 %11, i8 %12, i8 %13
  %indvars.iv.next = or disjoint i32 %indvars.iv, 1
  %14 = zext i8 %storemerge to i32
  %15 = add nuw nsw i32 %indvars.iv21, %indvars.iv.next
  %16 = icmp ugt i32 %15, %14
  %17 = shl i8 %storemerge, 1
  %18 = mul i8 %storemerge, %storemerge
  %storemerge.1 = select i1 %16, i8 %17, i8 %18
  %indvars.iv.next.1 = add nuw nsw i32 %indvars.iv, 2
  %niter.next.1 = add i32 %niter, 2
  %niter.ncmp.1 = icmp eq i32 %niter.next.1, %unroll_iter
  br i1 %niter.ncmp.1, label %.unr-lcssa, label %.preheader.new, !llvm.loop !8

.unr-lcssa:                                       ; preds = %.preheader.new, %.preheader
  %storemerge.lcssa.ph = phi i8 [ poison, %.preheader ], [ %storemerge.1, %.preheader.new ]
  %indvars.iv.unr = phi i32 [ 0, %.preheader ], [ %indvars.iv.next.1, %.preheader.new ]
  %.sroa.0.116.unr = phi i8 [ %.sroa.0.018, %.preheader ], [ %storemerge.1, %.preheader.new ]
  br i1 %lcmp.mod.not, label %24, label %.epilog-lcssa

.epilog-lcssa:                                    ; preds = %.unr-lcssa
  %19 = zext i8 %.sroa.0.116.unr to i32
  %20 = add nuw nsw i32 %indvars.iv21, %indvars.iv.unr
  %21 = icmp ugt i32 %20, %19
  %22 = shl i8 %.sroa.0.116.unr, 1
  %23 = mul i8 %.sroa.0.116.unr, %.sroa.0.116.unr
  %storemerge.epil = select i1 %21, i8 %22, i8 %23
  br label %24

24:                                               ; preds = %.unr-lcssa, %.epilog-lcssa
  %storemerge.lcssa = phi i8 [ %storemerge.lcssa.ph, %.unr-lcssa ], [ %storemerge.epil, %.epilog-lcssa ]
  %indvars.iv.next22 = add nuw nsw i32 %indvars.iv21, 1
  %exitcond25.not = icmp eq i32 %indvars.iv.next22, %wide.trip.count24
  br i1 %exitcond25.not, label %._crit_edge, label %.preheader, !llvm.loop !10

._crit_edge:                                      ; preds = %24, %2
  %.sroa.0.0.lcssa = phi i8 [ %5, %2 ], [ %storemerge.lcssa, %24 ]
  %25 = add i8 %.sroa.0.0.lcssa, 24
  store i8 %25, ptr %1, align 1, !tbaa !5
  ret void
}

attributes #0 = { nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}
!10 = distinct !{!10, !9}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass