; LLVM IR from AnneLivia/Competitive-Programming :: Algorithms/Genetic algorithm/main.ll (Z9crossoveriiRSt6vectorIiSaIiEE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@genes_number = external dso_local global i32, align 4
@population = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind
declare i32 @rand() #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z9crossoveriiRSt6vectorIiSaIiEE(i32 noundef %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %10 = call i32 @rand() #4
  %11 = load i32, ptr @genes_number, align 4, !tbaa !5
  %12 = srem i32 %10, %11
  store i32 %12, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  store i32 0, ptr %8, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %26, %3
  %14 = load i32, ptr %8, align 4, !tbaa !5
  %15 = load i32, ptr %7, align 4, !tbaa !5
  %16 = icmp sle i32 %14, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  br label %29

18:                                               ; preds = %13
  %19 = load ptr, ptr %6, align 8, !tbaa !9
  %20 = load i32, ptr %4, align 4, !tbaa !5
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @population, i64 noundef %21) #4
  %23 = load i32, ptr %8, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %24) #4
  call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) %19, ptr noundef nonnull align 4 dereferenceable(4) %25)
  br label %26

26:                                               ; preds = %18
  %27 = load i32, ptr %8, align 4, !tbaa !5
  %28 = add nsw i32 %27, 1
  store i32 %28, ptr %8, align 4, !tbaa !5
  br label %13, !llvm.loop !11

29:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  %30 = load i32, ptr %7, align 4, !tbaa !5
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %9, align 4, !tbaa !5
  br label %32

32:                                               ; preds = %45, %29
  %33 = load i32, ptr %9, align 4, !tbaa !5
  %34 = load i32, ptr @genes_number, align 4, !tbaa !5
  %35 = icmp slt i32 %33, %34
  br i1 %35, label %37, label %36

36:                                               ; preds = %32
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %48

37:                                               ; preds = %32
  %38 = load ptr, ptr %6, align 8, !tbaa !9
  %39 = load i32, ptr %5, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @population, i64 noundef %40) #4
  %42 = load i32, ptr %9, align 4, !tbaa !5
  %43 = sext i32 %42 to i64
  %44 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %43) #4
  call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) %38, ptr noundef nonnull align 4 dereferenceable(4) %44)
  br label %45

45:                                               ; preds = %37
  %46 = load i32, ptr %9, align 4, !tbaa !5
  %47 = add nsw i32 %46, 1
  store i32 %47, ptr %9, align 4, !tbaa !5
  br label %32, !llvm.loop !13

48:                                               ; preds = %36
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<int>, std::allocator<std::vector<int>>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@genes_number = external dso_local local_unnamed_addr global i32, align 4
@population = external dso_local global %"class.std::vector", align 8

; Function Attrs: nounwind
declare i32 @rand() local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z9crossoveriiRSt6vectorIiSaIiEE(i32 noundef %0, i32 noundef %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #1 {
  %4 = tail call i32 @rand() #3
  %5 = load i32, ptr @genes_number, align 4, !tbaa !5
  %6 = srem i32 %4, %5
  %.not13 = icmp slt i32 %6, 0
  br i1 %.not13, label %..preheader_crit_edge, label %.lr.ph

..preheader_crit_edge:                            ; preds = %3
  %.pre22 = add nsw i32 %6, 1
  br label %.preheader

.lr.ph:                                           ; preds = %3
  %7 = sext i32 %0 to i64
  %8 = add nuw i32 %6, 1
  %wide.trip.count = zext i32 %8 to i64
  br label %13

.preheader.loopexit:                              ; preds = %13
  %.pre = load i32, ptr @genes_number, align 4, !tbaa !5
  br label %.preheader

.preheader:                                       ; preds = %..preheader_crit_edge, %.preheader.loopexit
  %.015.pre-phi = phi i32 [ %.pre22, %..preheader_crit_edge ], [ %8, %.preheader.loopexit ]
  %9 = phi i32 [ %5, %..preheader_crit_edge ], [ %.pre, %.preheader.loopexit ]
  %10 = icmp slt i32 %.015.pre-phi, %9
  br i1 %10, label %.lr.ph17, label %._crit_edge

.lr.ph17:                                         ; preds = %.preheader
  %11 = sext i32 %1 to i64
  %12 = sext i32 %.015.pre-phi to i64
  br label %16

13:                                               ; preds = %.lr.ph, %13
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %13 ]
  %14 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @population, i64 noundef %7) #3
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %indvars.iv) #3
  tail call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 4 dereferenceable(4) %15)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.preheader.loopexit, label %13, !llvm.loop !9

._crit_edge:                                      ; preds = %16, %.preheader
  ret void

16:                                               ; preds = %.lr.ph17, %16
  %indvars.iv19 = phi i64 [ %12, %.lr.ph17 ], [ %indvars.iv.next20, %16 ]
  %17 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNSt6vectorIS_IiSaIiEESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) @population, i64 noundef %11) #3
  %18 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %indvars.iv19) #3
  tail call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 4 dereferenceable(4) %18)
  %indvars.iv.next20 = add nsw i64 %indvars.iv19, 1
  %19 = load i32, ptr @genes_number, align 4, !tbaa !5
  %20 = sext i32 %19 to i64
  %21 = icmp slt i64 %indvars.iv.next20, %20
  br i1 %21, label %16, label %._crit_edge, !llvm.loop !11
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Effective O3 passes: GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass