; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/SIM/FPU_funcs.ll (Z5FSGNJjj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.IEEE754 = type { %union.anon }
%union.anon = type { i32 }

@_ZL12use_soft_fpu = external hidden global i32, align 4
@.str.24 = external hidden unnamed_addr constant [6 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_Z19FSGNJ_WITH_SOFT_FPUjj(i32 noundef, i32 noundef) #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z1LPKc(ptr noundef) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z5FSGNJjj(i32 noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca %class.IEEE754, align 4
  %7 = alloca %class.IEEE754, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  %8 = load i32, ptr @_ZL12use_soft_fpu, align 4, !tbaa !5
  %9 = icmp ne i32 %8, 0
  br i1 %9, label %10, label %14

10:                                               ; preds = %2
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = load i32, ptr %5, align 4, !tbaa !5
  %13 = call noundef i32 @_Z19FSGNJ_WITH_SOFT_FPUjj(i32 noundef %11, i32 noundef %12)
  store i32 %13, ptr %3, align 4
  br label %28

14:                                               ; preds = %2
  call void @_Z1LPKc(ptr noundef @.str.24)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %15 = load i32, ptr %4, align 4, !tbaa !5
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %15)
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  %16 = load i32, ptr %5, align 4, !tbaa !5
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %7, i32 noundef %16)
  %17 = getelementptr inbounds %class.IEEE754, ptr %7, i32 0, i32 0
  %18 = load i32, ptr %17, align 4
  %19 = lshr i32 %18, 31
  %20 = getelementptr inbounds %class.IEEE754, ptr %6, i32 0, i32 0
  %21 = load i32, ptr %20, align 4
  %22 = and i32 %19, 1
  %23 = shl i32 %22, 31
  %24 = and i32 %21, 2147483647
  %25 = or i32 %24, %23
  store i32 %25, ptr %20, align 4
  %26 = getelementptr inbounds %class.IEEE754, ptr %7, i32 0, i32 0
  %27 = load i32, ptr %26, align 4, !tbaa !9
  store i32 %27, ptr %3, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  br label %28

28:                                               ; preds = %14, %10
  %29 = load i32, ptr %3, align 4
  ret i32 %29
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.IEEE754 = type { %union.anon }
%union.anon = type { i32 }

@_ZL12use_soft_fpu = external hidden local_unnamed_addr global i32, align 4
@.str.24 = external hidden unnamed_addr constant [6 x i8], align 1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i32 @_Z19FSGNJ_WITH_SOFT_FPUjj(i32 noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z1LPKc(ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z5FSGNJjj(i32 noundef %0, i32 noundef %1) local_unnamed_addr #2 {
  %3 = alloca %class.IEEE754, align 4
  %4 = alloca %class.IEEE754, align 4
  %5 = load i32, ptr @_ZL12use_soft_fpu, align 4, !tbaa !5
  %.not = icmp eq i32 %5, 0
  br i1 %.not, label %8, label %6

6:                                                ; preds = %2
  %7 = tail call noundef i32 @_Z19FSGNJ_WITH_SOFT_FPUjj(i32 noundef %0, i32 noundef %1)
  br label %10

8:                                                ; preds = %2
  tail call void @_Z1LPKc(ptr noundef nonnull @.str.24)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #4
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %3, i32 noundef %0)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #4
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %4, i32 noundef %1)
  %9 = load i32, ptr %4, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #4
  br label %10

10:                                               ; preds = %8, %6
  %.0 = phi i32 [ %7, %6 ], [ %9, %8 ]
  ret i32 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,TailCallElimPass