; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/FIRMWARE/LIBFEMTORV32 (cycles_32)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@cycles.cycles_lap_ = external hidden global i32, align 4
@cycles.cycles_ = external hidden global i64, align 8
@cycles.last_cycles32_ = external hidden global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local i64 @cycles() #0 {
  %1 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #2
  %2 = load i32, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %3 = icmp eq i32 %2, 0
  br i1 %3, label %4, label %14

4:                                                ; preds = %0
  %5 = load volatile i32, ptr inttoptr (i64 6291456 to ptr), align 4, !tbaa !5
  %6 = and i32 %5, 127
  store i32 %6, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %7 = load i32, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %8 = icmp eq i32 %7, 32
  br i1 %8, label %9, label %10

9:                                                ; preds = %4
  store i32 -1, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  br label %13

10:                                               ; preds = %4
  %11 = load i32, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %12 = shl i32 1, %11
  store i32 %12, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %10, %9
  br label %14

14:                                               ; preds = %13, %0
  %15 = call i32 asm sideeffect "rdcycle $0", "=r,~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  store i32 %15, ptr %1, align 4, !tbaa !5
  %16 = load i32, ptr %1, align 4, !tbaa !5
  %17 = load i32, ptr @cycles.last_cycles32_, align 4, !tbaa !5
  %18 = icmp ult i32 %16, %17
  br i1 %18, label %19, label %24

19:                                               ; preds = %14
  %20 = load i32, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %21 = zext i32 %20 to i64
  %22 = load i64, ptr @cycles.cycles_, align 8, !tbaa !10
  %23 = add i64 %22, %21
  store i64 %23, ptr @cycles.cycles_, align 8, !tbaa !10
  br label %24

24:                                               ; preds = %19, %14
  %25 = load i32, ptr %1, align 4, !tbaa !5
  %26 = zext i32 %25 to i64
  %27 = load i64, ptr @cycles.cycles_, align 8, !tbaa !10
  %28 = add i64 %27, %26
  store i64 %28, ptr @cycles.cycles_, align 8, !tbaa !10
  %29 = load i32, ptr @cycles.last_cycles32_, align 4, !tbaa !5
  %30 = zext i32 %29 to i64
  %31 = load i64, ptr @cycles.cycles_, align 8, !tbaa !10
  %32 = sub i64 %31, %30
  store i64 %32, ptr @cycles.cycles_, align 8, !tbaa !10
  %33 = load i32, ptr %1, align 4, !tbaa !5
  store i32 %33, ptr @cycles.last_cycles32_, align 4, !tbaa !5
  %34 = load i64, ptr @cycles.cycles_, align 8, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #2
  ret i64 %34
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 553}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@cycles.cycles_lap_ = external hidden local_unnamed_addr global i32, align 4
@cycles.cycles_ = external hidden local_unnamed_addr global i64, align 8
@cycles.last_cycles32_ = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local i64 @cycles() local_unnamed_addr #0 {
  %1 = load i32, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  %2 = icmp eq i32 %1, 0
  br i1 %2, label %.sink.split, label %7

.sink.split:                                      ; preds = %0
  %3 = load volatile i32, ptr inttoptr (i64 6291456 to ptr), align 2097152, !tbaa !5
  %4 = and i32 %3, 127
  %5 = icmp eq i32 %4, 32
  %6 = shl nuw i32 1, %4
  %.sink = select i1 %5, i32 -1, i32 %6
  store i32 %.sink, ptr @cycles.cycles_lap_, align 4, !tbaa !5
  br label %7

7:                                                ; preds = %.sink.split, %0
  %8 = tail call i32 asm sideeffect "rdcycle $0", "=r,~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  %9 = load i32, ptr @cycles.last_cycles32_, align 4, !tbaa !5
  %10 = icmp ult i32 %8, %9
  %.pre = load i64, ptr @cycles.cycles_, align 8, !tbaa !10
  %11 = load i32, ptr @cycles.cycles_lap_, align 4
  %narrow = select i1 %10, i32 %11, i32 0
  %12 = zext i32 %narrow to i64
  %13 = add i64 %.pre, %12
  %14 = zext i32 %8 to i64
  %15 = zext i32 %9 to i64
  %16 = sub nsw i64 %14, %15
  %17 = add i64 %16, %13
  store i64 %17, ptr @cycles.cycles_, align 8, !tbaa !10
  store i32 %8, ptr @cycles.last_cycles32_, align 4, !tbaa !5
  ret i64 %17
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 553}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass