; LLVM IR from QiaoLiuHit/LSOTB-TIR :: vlfeat-0.9.19/vl/host.ll (vl_x86cpu_info_to_string_copy)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._VlX86CpuInfo = type { %union.anon, i32, i32, i32, i32, i32, i32, i32 }
%union.anon = type { [8 x i32] }

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [1 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.6 = external hidden unnamed_addr constant [7 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [7 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [5 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @_vl_x86cpu_info_to_string_copy(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #4
  store ptr null, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  store i32 0, ptr %4, align 4, !tbaa !9
  br label %5

5:                                                ; preds = %20, %1
  %6 = load ptr, ptr %3, align 8, !tbaa !5
  %7 = icmp eq ptr %6, null
  br i1 %7, label %8, label %72

8:                                                ; preds = %5
  %9 = load i32, ptr %4, align 4, !tbaa !9
  %10 = icmp sgt i32 %9, 0
  br i1 %10, label %11, label %20

11:                                               ; preds = %8
  %12 = load i32, ptr %4, align 4, !tbaa !9
  %13 = sext i32 %12 to i64
  %14 = mul i64 1, %13
  %15 = call ptr @vl_malloc(i64 noundef %14)
  store ptr %15, ptr %3, align 8, !tbaa !5
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = icmp eq ptr %16, null
  br i1 %17, label %18, label %19

18:                                               ; preds = %11
  br label %72

19:                                               ; preds = %11
  br label %20

20:                                               ; preds = %19, %8
  %21 = load ptr, ptr %3, align 8, !tbaa !5
  %22 = load i32, ptr %4, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = load ptr, ptr %2, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %24, i32 0, i32 0
  %26 = getelementptr inbounds [32 x i8], ptr %25, i64 0, i64 0
  %27 = load ptr, ptr %2, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %27, i32 0, i32 7
  %29 = load i32, ptr %28, align 4, !tbaa !11
  %30 = icmp ne i32 %29, 0
  %31 = zext i1 %30 to i64
  %32 = select i1 %30, ptr @.str.1, ptr @.str.2
  %33 = load ptr, ptr %2, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %33, i32 0, i32 6
  %35 = load i32, ptr %34, align 4, !tbaa !13
  %36 = icmp ne i32 %35, 0
  %37 = zext i1 %36 to i64
  %38 = select i1 %36, ptr @.str.3, ptr @.str.2
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %39, i32 0, i32 5
  %41 = load i32, ptr %40, align 4, !tbaa !14
  %42 = icmp ne i32 %41, 0
  %43 = zext i1 %42 to i64
  %44 = select i1 %42, ptr @.str.4, ptr @.str.2
  %45 = load ptr, ptr %2, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %45, i32 0, i32 4
  %47 = load i32, ptr %46, align 4, !tbaa !15
  %48 = icmp ne i32 %47, 0
  %49 = zext i1 %48 to i64
  %50 = select i1 %48, ptr @.str.5, ptr @.str.2
  %51 = load ptr, ptr %2, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %51, i32 0, i32 3
  %53 = load i32, ptr %52, align 4, !tbaa !16
  %54 = icmp ne i32 %53, 0
  %55 = zext i1 %54 to i64
  %56 = select i1 %54, ptr @.str.6, ptr @.str.2
  %57 = load ptr, ptr %2, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %57, i32 0, i32 2
  %59 = load i32, ptr %58, align 4, !tbaa !17
  %60 = icmp ne i32 %59, 0
  %61 = zext i1 %60 to i64
  %62 = select i1 %60, ptr @.str.7, ptr @.str.2
  %63 = load ptr, ptr %2, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %63, i32 0, i32 1
  %65 = load i32, ptr %64, align 4, !tbaa !18
  %66 = icmp ne i32 %65, 0
  %67 = zext i1 %66 to i64
  %68 = select i1 %66, ptr @.str.8, ptr @.str.2
  %69 = call i32 (ptr, i64, ptr, ...) @snprintf(ptr noundef %21, i64 noundef %23, ptr noundef @.str, ptr noundef %26, ptr noundef %32, ptr noundef %38, ptr noundef %44, ptr noundef %50, ptr noundef %56, ptr noundef %62, ptr noundef %68) #4
  store i32 %69, ptr %4, align 4, !tbaa !9
  %70 = load i32, ptr %4, align 4, !tbaa !9
  %71 = add nsw i32 %70, 1
  store i32 %71, ptr %4, align 4, !tbaa !9
  br label %5, !llvm.loop !19

72:                                               ; preds = %18, %5
  %73 = load ptr, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #4
  ret ptr %73
}

declare ptr @vl_malloc(i64 noundef) #2

; Function Attrs: nounwind
declare i32 @snprintf(ptr noundef, i64 noundef, ptr noundef, ...) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 56}
!12 = !{!"_VlX86CpuInfo", !7, i64 0, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!13 = !{!12, !10, i64 52}
!14 = !{!12, !10, i64 48}
!15 = !{!12, !10, i64 44}
!16 = !{!12, !10, i64 40}
!17 = !{!12, !10, i64 36}
!18 = !{!12, !10, i64 32}
!19 = distinct !{!19, !20}
!20 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@.str = external hidden unnamed_addr constant [17 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [1 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [5 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [6 x i8], align 1
@.str.6 = external hidden unnamed_addr constant [7 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [7 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [5 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @_vl_x86cpu_info_to_string_copy(ptr noundef %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 56
  %3 = getelementptr inbounds i8, ptr %0, i64 52
  %4 = getelementptr inbounds i8, ptr %0, i64 48
  %5 = getelementptr inbounds i8, ptr %0, i64 32
  br label %6

6:                                                ; preds = %1, %12
  %.025 = phi i32 [ 0, %1 ], [ %31, %12 ]
  %7 = icmp sgt i32 %.025, 0
  br i1 %7, label %8, label %12

8:                                                ; preds = %6
  %9 = zext nneg i32 %.025 to i64
  %10 = tail call ptr @vl_malloc(i64 noundef %9) #3
  %11 = icmp eq ptr %10, null
  br i1 %11, label %33, label %12

12:                                               ; preds = %8, %6
  %.1 = phi ptr [ %10, %8 ], [ null, %6 ]
  %13 = sext i32 %.025 to i64
  %14 = load i32, ptr %2, align 4, !tbaa !5
  %.not = icmp eq i32 %14, 0
  %15 = select i1 %.not, ptr @.str.2, ptr @.str.1
  %16 = load i32, ptr %3, align 4, !tbaa !10
  %.not18 = icmp eq i32 %16, 0
  %17 = select i1 %.not18, ptr @.str.2, ptr @.str.3
  %18 = load i32, ptr %4, align 4, !tbaa !11
  %.not19 = icmp eq i32 %18, 0
  %19 = select i1 %.not19, ptr @.str.2, ptr @.str.4
  %20 = load <4 x i32>, ptr %5, align 4, !tbaa !12
  %21 = icmp eq <4 x i32> %20, zeroinitializer
  %22 = extractelement <4 x i1> %21, i64 3
  %23 = select i1 %22, ptr @.str.2, ptr @.str.5
  %24 = extractelement <4 x i1> %21, i64 2
  %25 = select i1 %24, ptr @.str.2, ptr @.str.6
  %26 = extractelement <4 x i1> %21, i64 1
  %27 = select i1 %26, ptr @.str.2, ptr @.str.7
  %28 = extractelement <4 x i1> %21, i64 0
  %29 = select i1 %28, ptr @.str.2, ptr @.str.8
  %30 = tail call i32 (ptr, i64, ptr, ...) @snprintf(ptr noundef %.1, i64 noundef %13, ptr noundef nonnull @.str, ptr noundef %0, ptr noundef nonnull %15, ptr noundef nonnull %17, ptr noundef nonnull %19, ptr noundef nonnull %23, ptr noundef nonnull %25, ptr noundef nonnull %27, ptr noundef nonnull %29) #3
  %31 = add nsw i32 %30, 1
  %32 = icmp eq ptr %.1, null
  br i1 %32, label %6, label %33, !llvm.loop !13

33:                                               ; preds = %8, %12
  %.015.lcssa = phi ptr [ null, %8 ], [ %.1, %12 ]
  ret ptr %.015.lcssa
}

declare ptr @vl_malloc(i64 noundef) local_unnamed_addr #1

; Function Attrs: nofree nounwind
declare noundef i32 @snprintf(ptr noalias nocapture noundef writeonly, i64 noundef, ptr nocapture noundef readonly, ...) local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 56}
!6 = !{!"_VlX86CpuInfo", !7, i64 0, !9, i64 32, !9, i64 36, !9, i64 40, !9, i64 44, !9, i64 48, !9, i64 52, !9, i64 56}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"int", !7, i64 0}
!10 = !{!6, !9, i64 52}
!11 = !{!6, !9, i64 48}
!12 = !{!9, !9, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopRotatePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass