; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/SIM/FPU_funcs.ll (Z20DOOM_approx_inv_sqrtf)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef float @_Z7decodefj(i32 noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef float @_Z20DOOM_approx_inv_sqrtf(float noundef %0) #2 {
  %2 = alloca float, align 4
  %3 = alloca float, align 4
  %4 = alloca i32, align 4
  %5 = alloca float, align 4
  store float %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  %6 = load float, ptr %2, align 4, !tbaa !5
  %7 = fmul float %6, 5.000000e-01
  store float %7, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  %8 = load float, ptr %2, align 4, !tbaa !5
  %9 = call noundef i32 @_Z7encodeff(float noundef %8)
  %10 = lshr i32 %9, 1
  %11 = sub i32 1597463007, %10
  store i32 %11, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %12 = load i32, ptr %4, align 4, !tbaa !9
  %13 = call noundef float @_Z7decodefj(i32 noundef %12)
  store float %13, ptr %5, align 4, !tbaa !5
  %14 = load float, ptr %5, align 4, !tbaa !5
  %15 = load float, ptr %3, align 4, !tbaa !5
  %16 = load float, ptr %5, align 4, !tbaa !5
  %17 = fmul float %15, %16
  %18 = load float, ptr %5, align 4, !tbaa !5
  %19 = fneg float %17
  %20 = call float @llvm.fmuladd.f32(float %19, float %18, float 1.500000e+00)
  %21 = fmul float %14, %20
  store float %21, ptr %5, align 4, !tbaa !5
  %22 = load float, ptr %5, align 4, !tbaa !5
  %23 = load float, ptr %3, align 4, !tbaa !5
  %24 = load float, ptr %5, align 4, !tbaa !5
  %25 = fmul float %23, %24
  %26 = load float, ptr %5, align 4, !tbaa !5
  %27 = fneg float %25
  %28 = call float @llvm.fmuladd.f32(float %27, float %26, float 1.500000e+00)
  %29 = fmul float %22, %28
  store float %29, ptr %5, align 4, !tbaa !5
  %30 = load float, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret float %30
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z7encodeff(float noundef) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"float", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef float @_Z7decodefj(i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local noundef float @_Z20DOOM_approx_inv_sqrtf(float noundef %0) local_unnamed_addr #1 {
  %2 = tail call noundef i32 @_Z7encodeff(float noundef %0)
  %3 = lshr i32 %2, 1
  %4 = sub nsw i32 1597463007, %3
  %5 = tail call noundef float @_Z7decodefj(i32 noundef %4)
  %6 = fmul float %0, -5.000000e-01
  %7 = fmul float %6, %5
  %8 = tail call float @llvm.fmuladd.f32(float %7, float %5, float 1.500000e+00)
  %9 = fmul float %5, %8
  %10 = fmul float %6, %9
  %11 = tail call float @llvm.fmuladd.f32(float %10, float %9, float 1.500000e+00)
  %12 = fmul float %9, %11
  ret float %12
}

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z7encodeff(float noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare float @llvm.fmuladd.f32(float, float, float) #2

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass