; LLVM IR from 2404589803/LowMemoryLLM :: src/hal/gpu (gpu_context)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.GPUContext = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i64, i64 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @clSetKernelArg(ptr noundef, i32 noundef, i64 noundef, ptr noundef) #1

declare i32 @clEnqueueNDRangeKernel(ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @gpu_vector_add(ptr noundef %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, i64 noundef %4) #2 {
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  %13 = alloca i64, align 8
  %14 = alloca i32, align 4
  store ptr %0, ptr %7, align 8, !tbaa !5
  store ptr %1, ptr %8, align 8, !tbaa !5
  store ptr %2, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store i64 %4, ptr %11, align 8, !tbaa !9
  %15 = load ptr, ptr %7, align 8, !tbaa !5
  %16 = icmp ne ptr %15, null
  br i1 %16, label %18, label %17

17:                                               ; preds = %5
  store i32 -1, ptr %6, align 4
  br label %64

18:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #3
  %19 = load i64, ptr %11, align 8, !tbaa !9
  store i64 %19, ptr %13, align 8, !tbaa !9
  %20 = load ptr, ptr %7, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.GPUContext, ptr %20, i32 0, i32 5
  %22 = load ptr, ptr %21, align 8, !tbaa !11
  %23 = call i32 @clSetKernelArg(ptr noundef %22, i32 noundef 0, i64 noundef 8, ptr noundef %8)
  store i32 %23, ptr %12, align 4, !tbaa !13
  %24 = load i32, ptr %12, align 4, !tbaa !13
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %18
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

27:                                               ; preds = %18
  %28 = load ptr, ptr %7, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.GPUContext, ptr %28, i32 0, i32 5
  %30 = load ptr, ptr %29, align 8, !tbaa !11
  %31 = call i32 @clSetKernelArg(ptr noundef %30, i32 noundef 1, i64 noundef 8, ptr noundef %9)
  store i32 %31, ptr %12, align 4, !tbaa !13
  %32 = load i32, ptr %12, align 4, !tbaa !13
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %35

34:                                               ; preds = %27
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

35:                                               ; preds = %27
  %36 = load ptr, ptr %7, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.GPUContext, ptr %36, i32 0, i32 5
  %38 = load ptr, ptr %37, align 8, !tbaa !11
  %39 = call i32 @clSetKernelArg(ptr noundef %38, i32 noundef 2, i64 noundef 8, ptr noundef %10)
  store i32 %39, ptr %12, align 4, !tbaa !13
  %40 = load i32, ptr %12, align 4, !tbaa !13
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %42, label %43

42:                                               ; preds = %35
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

43:                                               ; preds = %35
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.GPUContext, ptr %44, i32 0, i32 5
  %46 = load ptr, ptr %45, align 8, !tbaa !11
  %47 = call i32 @clSetKernelArg(ptr noundef %46, i32 noundef 3, i64 noundef 4, ptr noundef %11)
  store i32 %47, ptr %12, align 4, !tbaa !13
  %48 = load i32, ptr %12, align 4, !tbaa !13
  %49 = icmp ne i32 %48, 0
  br i1 %49, label %50, label %51

50:                                               ; preds = %43
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

51:                                               ; preds = %43
  %52 = load ptr, ptr %7, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.GPUContext, ptr %52, i32 0, i32 1
  %54 = load ptr, ptr %53, align 8, !tbaa !15
  %55 = load ptr, ptr %7, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.GPUContext, ptr %55, i32 0, i32 5
  %57 = load ptr, ptr %56, align 8, !tbaa !11
  %58 = call i32 @clEnqueueNDRangeKernel(ptr noundef %54, ptr noundef %57, i32 noundef 1, ptr noundef null, ptr noundef %13, ptr noundef null, i32 noundef 0, ptr noundef null, ptr noundef null)
  store i32 %58, ptr %12, align 4, !tbaa !13
  %59 = load i32, ptr %12, align 4, !tbaa !13
  %60 = icmp ne i32 %59, 0
  br i1 %60, label %61, label %62

61:                                               ; preds = %51
  store i32 -1, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

62:                                               ; preds = %51
  store i32 0, ptr %6, align 4
  store i32 1, ptr %14, align 4
  br label %63

63:                                               ; preds = %62, %61, %50, %42, %34, %26
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  br label %64

64:                                               ; preds = %63, %17
  %65 = load i32, ptr %6, align 4
  ret i32 %65
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 40}
!12 = !{!"", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !10, i64 56, !10, i64 64}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!12, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @clSetKernelArg(ptr noundef, i32 noundef, i64 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @clEnqueueNDRangeKernel(ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @gpu_vector_add(ptr noundef readonly %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, i64 noundef %4) local_unnamed_addr #2 {
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  store i64 %4, ptr %9, align 8, !tbaa !9
  %.not = icmp eq ptr %0, null
  br i1 %.not, label %30, label %11

11:                                               ; preds = %5
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %10) #3
  store i64 %4, ptr %10, align 8, !tbaa !9
  %12 = getelementptr inbounds i8, ptr %0, i64 40
  %13 = load ptr, ptr %12, align 8, !tbaa !11
  %14 = call i32 @clSetKernelArg(ptr noundef %13, i32 noundef 0, i64 noundef 8, ptr noundef nonnull %6) #3
  %.not13 = icmp eq i32 %14, 0
  br i1 %.not13, label %15, label %29

15:                                               ; preds = %11
  %16 = load ptr, ptr %12, align 8, !tbaa !11
  %17 = call i32 @clSetKernelArg(ptr noundef %16, i32 noundef 1, i64 noundef 8, ptr noundef nonnull %7) #3
  %.not14 = icmp eq i32 %17, 0
  br i1 %.not14, label %18, label %29

18:                                               ; preds = %15
  %19 = load ptr, ptr %12, align 8, !tbaa !11
  %20 = call i32 @clSetKernelArg(ptr noundef %19, i32 noundef 2, i64 noundef 8, ptr noundef nonnull %8) #3
  %.not15 = icmp eq i32 %20, 0
  br i1 %.not15, label %21, label %29

21:                                               ; preds = %18
  %22 = load ptr, ptr %12, align 8, !tbaa !11
  %23 = call i32 @clSetKernelArg(ptr noundef %22, i32 noundef 3, i64 noundef 4, ptr noundef nonnull %9) #3
  %.not16 = icmp eq i32 %23, 0
  br i1 %.not16, label %24, label %29

24:                                               ; preds = %21
  %25 = getelementptr inbounds i8, ptr %0, i64 8
  %26 = load ptr, ptr %25, align 8, !tbaa !13
  %27 = load ptr, ptr %12, align 8, !tbaa !11
  %28 = call i32 @clEnqueueNDRangeKernel(ptr noundef %26, ptr noundef %27, i32 noundef 1, ptr noundef null, ptr noundef nonnull %10, ptr noundef null, i32 noundef 0, ptr noundef null, ptr noundef null) #3
  %.not17 = icmp ne i32 %28, 0
  %. = sext i1 %.not17 to i32
  br label %29

29:                                               ; preds = %24, %21, %18, %15, %11
  %.0 = phi i32 [ -1, %11 ], [ -1, %15 ], [ -1, %18 ], [ -1, %21 ], [ %., %24 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %10) #3
  br label %30

30:                                               ; preds = %5, %29
  %.1 = phi i32 [ %.0, %29 ], [ -1, %5 ]
  ret i32 %.1
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 40}
!12 = !{!"", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !6, i64 48, !10, i64 56, !10, i64 64}
!13 = !{!12, !6, i64 8}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass