; LLVM IR from embeddednirvana/A-Rudimentary-RTOS-for-Satellite-Control :: device (sd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._AT91S_PIO = type { i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [9 x i32], i32, i32, i32 }

@error = external dso_local global i8, align 1
@arguments = external dso_local global [4 x i8], align 1
@response = external dso_local global [8 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @sd_send_command(ptr noundef %0, i8 noundef zeroext %1, i8 noundef zeroext %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca [5 x i8], align 1
  %12 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !9
  store i8 %2, ptr %7, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  store i8 0, ptr %9, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 5, ptr %11) #3
  %13 = load i8, ptr %6, align 1, !tbaa !9
  %14 = zext i8 %13 to i32
  %15 = and i32 %14, 63
  %16 = or i32 %15, 64
  %17 = trunc i32 %16 to i8
  store i8 %17, ptr %6, align 1, !tbaa !9
  %18 = load i8, ptr %6, align 1, !tbaa !9
  %19 = getelementptr inbounds [5 x i8], ptr %11, i64 0, i64 0
  store i8 %18, ptr %19, align 1, !tbaa !9
  %20 = load i8, ptr %6, align 1, !tbaa !9
  %21 = zext i8 %20 to i16
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %21)
  store i8 3, ptr %8, align 1, !tbaa !9
  br label %22

22:                                               ; preds = %32, %3
  %23 = load i8, ptr %8, align 1, !tbaa !9
  %24 = sext i8 %23 to i32
  %25 = icmp sge i32 %24, 0
  br i1 %25, label %26, label %35

26:                                               ; preds = %22
  %27 = load i8, ptr %8, align 1, !tbaa !9
  %28 = sext i8 %27 to i64
  %29 = getelementptr inbounds [4 x i8], ptr @arguments, i64 0, i64 %28
  %30 = load i8, ptr %29, align 1, !tbaa !9
  %31 = zext i8 %30 to i16
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %31)
  br label %32

32:                                               ; preds = %26
  %33 = load i8, ptr %8, align 1, !tbaa !9
  %34 = add i8 %33, -1
  store i8 %34, ptr %8, align 1, !tbaa !9
  br label %22, !llvm.loop !10

35:                                               ; preds = %22
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 149)
  %36 = load i8, ptr %7, align 1, !tbaa !9
  %37 = zext i8 %36 to i32
  switch i32 %37, label %42 [
    i32 1, label %38
    i32 2, label %38
    i32 3, label %39
    i32 4, label %40
    i32 5, label %41
  ]

38:                                               ; preds = %35, %35
  store i8 1, ptr %9, align 1, !tbaa !9
  br label %43

39:                                               ; preds = %35
  store i8 2, ptr %9, align 1, !tbaa !9
  br label %43

40:                                               ; preds = %35
  store i8 6, ptr %9, align 1, !tbaa !9
  br label %43

41:                                               ; preds = %35
  store i8 16, ptr %9, align 1, !tbaa !9
  br label %42

42:                                               ; preds = %41, %35
  br label %43

43:                                               ; preds = %42, %40, %39, %38
  store i8 0, ptr %8, align 1, !tbaa !9
  br label %44

44:                                               ; preds = %58, %43
  %45 = load i8, ptr %8, align 1, !tbaa !9
  %46 = add i8 %45, 1
  store i8 %46, ptr %8, align 1, !tbaa !9
  %47 = call zeroext i16 @SPI_Read(ptr noundef inttoptr (i64 4294836224 to ptr))
  %48 = trunc i16 %47 to i8
  store i8 %48, ptr %10, align 1, !tbaa !9
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  br label %49

49:                                               ; preds = %44
  %50 = load i8, ptr %10, align 1, !tbaa !9
  %51 = zext i8 %50 to i32
  %52 = and i32 %51, 128
  %53 = icmp ne i32 %52, 0
  br i1 %53, label %54, label %58

54:                                               ; preds = %49
  %55 = load i8, ptr %8, align 1, !tbaa !9
  %56 = sext i8 %55 to i32
  %57 = icmp slt i32 %56, 100
  br label %58

58:                                               ; preds = %54, %49
  %59 = phi i1 [ false, %49 ], [ %57, %54 ]
  br i1 %59, label %44, label %60, !llvm.loop !12

60:                                               ; preds = %58
  %61 = load i8, ptr %8, align 1, !tbaa !9
  %62 = sext i8 %61 to i32
  %63 = icmp sge i32 %62, 100
  br i1 %63, label %64, label %71

64:                                               ; preds = %60
  %65 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %66 = or i32 %65, 8192
  store volatile i32 %66, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %67 = load i8, ptr @error, align 1, !tbaa !9
  %68 = zext i8 %67 to i32
  %69 = or i32 %68, 64
  %70 = trunc i32 %69 to i8
  store i8 %70, ptr @error, align 1, !tbaa !9
  store i32 0, ptr %4, align 4
  store i32 1, ptr %12, align 4
  br label %105

71:                                               ; preds = %60
  %72 = load i8, ptr %9, align 1, !tbaa !9
  %73 = zext i8 %72 to i32
  %74 = sub nsw i32 %73, 1
  %75 = trunc i32 %74 to i8
  store i8 %75, ptr %8, align 1, !tbaa !9
  br label %76

76:                                               ; preds = %87, %71
  %77 = load i8, ptr %8, align 1, !tbaa !9
  %78 = sext i8 %77 to i32
  %79 = icmp sge i32 %78, 0
  br i1 %79, label %80, label %90

80:                                               ; preds = %76
  %81 = load i8, ptr %10, align 1, !tbaa !9
  %82 = load i8, ptr %8, align 1, !tbaa !9
  %83 = sext i8 %82 to i64
  %84 = getelementptr inbounds [8 x i8], ptr @response, i64 0, i64 %83
  store i8 %81, ptr %84, align 1, !tbaa !9
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  %85 = call zeroext i16 @SPI_Read(ptr noundef inttoptr (i64 4294836224 to ptr))
  %86 = trunc i16 %85 to i8
  store i8 %86, ptr %10, align 1, !tbaa !9
  br label %87

87:                                               ; preds = %80
  %88 = load i8, ptr %8, align 1, !tbaa !9
  %89 = add i8 %88, -1
  store i8 %89, ptr %8, align 1, !tbaa !9
  br label %76, !llvm.loop !16

90:                                               ; preds = %76
  %91 = load i8, ptr %7, align 1, !tbaa !9
  %92 = zext i8 %91 to i32
  %93 = icmp eq i32 %92, 2
  br i1 %93, label %94, label %104

94:                                               ; preds = %90
  br label %95

95:                                               ; preds = %98, %94
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  %96 = call zeroext i16 @SPI_Read(ptr noundef inttoptr (i64 4294836224 to ptr))
  %97 = trunc i16 %96 to i8
  store i8 %97, ptr %10, align 1, !tbaa !9
  br label %98

98:                                               ; preds = %95
  %99 = load i8, ptr %10, align 1, !tbaa !9
  %100 = zext i8 %99 to i32
  %101 = and i32 %100, 255
  %102 = icmp ne i32 %101, 255
  br i1 %102, label %95, label %103, !llvm.loop !17

103:                                              ; preds = %98
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  br label %104

104:                                              ; preds = %103, %90
  store i32 1, ptr %4, align 4
  store i32 1, ptr %12, align 4
  br label %105

105:                                              ; preds = %104, %64
  call void @llvm.lifetime.end.p0(i64 5, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  %106 = load i32, ptr %4, align 4
  ret i32 %106
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) #2

declare zeroext i16 @SPI_Read(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !11}
!13 = !{!14, !15, i64 56}
!14 = !{!"_AT91S_PIO", !15, i64 0, !15, i64 4, !15, i64 8, !7, i64 12, !15, i64 16, !15, i64 20, !15, i64 24, !7, i64 28, !15, i64 32, !15, i64 36, !15, i64 40, !7, i64 44, !15, i64 48, !15, i64 52, !15, i64 56, !15, i64 60, !15, i64 64, !15, i64 68, !15, i64 72, !15, i64 76, !15, i64 80, !15, i64 84, !15, i64 88, !7, i64 92, !15, i64 96, !15, i64 100, !15, i64 104, !7, i64 108, !15, i64 112, !15, i64 116, !15, i64 120, !7, i64 124, !15, i64 160, !15, i64 164, !15, i64 168}
!15 = !{!"int", !7, i64 0}
!16 = distinct !{!16, !11}
!17 = distinct !{!17, !11}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@error = external dso_local local_unnamed_addr global i8, align 1
@arguments = external dso_local local_unnamed_addr global [4 x i8], align 1
@response = external dso_local local_unnamed_addr global [8 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @sd_send_command(ptr nocapture noundef readnone %0, i8 noundef zeroext %1, i8 noundef zeroext %2) local_unnamed_addr #0 {
  %4 = and i8 %1, 63
  %5 = or disjoint i8 %4, 64
  %6 = zext nneg i8 %5 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %6) #2
  %7 = load i8, ptr getelementptr inbounds (i8, ptr @arguments, i64 3), align 1, !tbaa !5
  %8 = zext i8 %7 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %8) #2
  %9 = load i8, ptr getelementptr inbounds (i8, ptr @arguments, i64 2), align 1, !tbaa !5
  %10 = zext i8 %9 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %10) #2
  %11 = load i8, ptr getelementptr inbounds (i8, ptr @arguments, i64 1), align 1, !tbaa !5
  %12 = zext i8 %11 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %12) #2
  %13 = load i8, ptr @arguments, align 1, !tbaa !5
  %14 = zext i8 %13 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %14) #2
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 149) #2
  switch i8 %2, label %19 [
    i8 1, label %15
    i8 2, label %15
    i8 3, label %16
    i8 4, label %17
    i8 5, label %18
  ]

15:                                               ; preds = %3, %3
  br label %19

16:                                               ; preds = %3
  br label %19

17:                                               ; preds = %3
  br label %19

18:                                               ; preds = %3
  br label %19

19:                                               ; preds = %3, %18, %17, %16, %15
  %20 = phi i1 [ false, %3 ], [ true, %18 ], [ true, %17 ], [ true, %16 ], [ true, %15 ]
  %.021 = phi i64 [ 255, %3 ], [ 15, %18 ], [ 5, %17 ], [ 1, %16 ], [ 0, %15 ]
  br label %21

21:                                               ; preds = %21, %19
  %.1 = phi i8 [ 0, %19 ], [ %22, %21 ]
  %22 = add nuw nsw i8 %.1, 1
  %23 = tail call zeroext i16 @SPI_Read(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  %24 = and i16 %23, 128
  %25 = icmp ne i16 %24, 0
  %26 = icmp ult i8 %.1, 99
  %27 = select i1 %25, i1 %26, i1 false
  br i1 %27, label %21, label %28, !llvm.loop !8

28:                                               ; preds = %21
  %29 = icmp ugt i8 %.1, 98
  br i1 %29, label %30, label %.preheader22

.preheader22:                                     ; preds = %28
  br i1 %20, label %.lr.ph, label %._crit_edge

30:                                               ; preds = %28
  %31 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !10
  %32 = or i32 %31, 8192
  store volatile i32 %32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !10
  %33 = load i8, ptr @error, align 1, !tbaa !5
  %34 = or i8 %33, 64
  store i8 %34, ptr @error, align 1, !tbaa !5
  br label %43

.lr.ph:                                           ; preds = %.preheader22, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %.021, %.preheader22 ]
  %.020.in24 = phi i16 [ %36, %.lr.ph ], [ %23, %.preheader22 ]
  %.020 = trunc i16 %.020.in24 to i8
  %35 = getelementptr inbounds [8 x i8], ptr @response, i64 0, i64 %indvars.iv
  store i8 %.020, ptr %35, align 1, !tbaa !5
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  %36 = tail call zeroext i16 @SPI_Read(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %indvars.iv.next = add nsw i64 %indvars.iv, -1
  %37 = trunc nuw i64 %indvars.iv to i8
  %38 = icmp sgt i8 %37, 0
  br i1 %38, label %.lr.ph, label %._crit_edge, !llvm.loop !13

._crit_edge:                                      ; preds = %.lr.ph, %.preheader22
  %39 = icmp eq i8 %2, 2
  br i1 %39, label %.preheader, label %43

.preheader:                                       ; preds = %._crit_edge, %.preheader
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  %40 = tail call zeroext i16 @SPI_Read(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %41 = and i16 %40, 255
  %.not = icmp eq i16 %41, 255
  br i1 %.not, label %42, label %.preheader, !llvm.loop !14

42:                                               ; preds = %.preheader
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  br label %43

43:                                               ; preds = %._crit_edge, %42, %30
  %.0 = phi i32 [ 0, %30 ], [ 1, %42 ], [ 1, %._crit_edge ]
  ret i32 %.0
}

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #1

declare zeroext i16 @SPI_Read(ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}
!10 = !{!11, !12, i64 56}
!11 = !{!"_AT91S_PIO", !12, i64 0, !12, i64 4, !12, i64 8, !6, i64 12, !12, i64 16, !12, i64 20, !12, i64 24, !6, i64 28, !12, i64 32, !12, i64 36, !12, i64 40, !6, i64 44, !12, i64 48, !12, i64 52, !12, i64 56, !12, i64 60, !12, i64 64, !12, i64 68, !12, i64 72, !12, i64 76, !12, i64 80, !12, i64 84, !12, i64 88, !6, i64 92, !12, i64 96, !12, i64 100, !12, i64 104, !6, i64 108, !12, i64 112, !12, i64 116, !12, i64 120, !6, i64 124, !12, i64 160, !12, i64 164, !12, i64 168}
!12 = !{!"int", !6, i64 0}
!13 = distinct !{!13, !9}
!14 = distinct !{!14, !9}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass