; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/FIRMWARE/LIBFEMTORV32 (spi_sd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @spi_receive() #0 {
  %1 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr %1) #3
  call void @MOSI_H()
  store i8 0, ptr %1, align 1, !tbaa !5
  %2 = call i32 @MISO()
  %3 = icmp ne i32 %2, 0
  br i1 %3, label %4, label %7

4:                                                ; preds = %0
  %5 = load i8, ptr %1, align 1, !tbaa !5
  %6 = add i8 %5, 1
  store i8 %6, ptr %1, align 1, !tbaa !5
  br label %7

7:                                                ; preds = %4, %0
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %8 = load i8, ptr %1, align 1, !tbaa !5
  %9 = zext i8 %8 to i32
  %10 = shl i32 %9, 1
  %11 = trunc i32 %10 to i8
  store i8 %11, ptr %1, align 1, !tbaa !5
  %12 = call i32 @MISO()
  %13 = icmp ne i32 %12, 0
  br i1 %13, label %14, label %17

14:                                               ; preds = %7
  %15 = load i8, ptr %1, align 1, !tbaa !5
  %16 = add i8 %15, 1
  store i8 %16, ptr %1, align 1, !tbaa !5
  br label %17

17:                                               ; preds = %14, %7
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %18 = load i8, ptr %1, align 1, !tbaa !5
  %19 = zext i8 %18 to i32
  %20 = shl i32 %19, 1
  %21 = trunc i32 %20 to i8
  store i8 %21, ptr %1, align 1, !tbaa !5
  %22 = call i32 @MISO()
  %23 = icmp ne i32 %22, 0
  br i1 %23, label %24, label %27

24:                                               ; preds = %17
  %25 = load i8, ptr %1, align 1, !tbaa !5
  %26 = add i8 %25, 1
  store i8 %26, ptr %1, align 1, !tbaa !5
  br label %27

27:                                               ; preds = %24, %17
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %28 = load i8, ptr %1, align 1, !tbaa !5
  %29 = zext i8 %28 to i32
  %30 = shl i32 %29, 1
  %31 = trunc i32 %30 to i8
  store i8 %31, ptr %1, align 1, !tbaa !5
  %32 = call i32 @MISO()
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %37

34:                                               ; preds = %27
  %35 = load i8, ptr %1, align 1, !tbaa !5
  %36 = add i8 %35, 1
  store i8 %36, ptr %1, align 1, !tbaa !5
  br label %37

37:                                               ; preds = %34, %27
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %38 = load i8, ptr %1, align 1, !tbaa !5
  %39 = zext i8 %38 to i32
  %40 = shl i32 %39, 1
  %41 = trunc i32 %40 to i8
  store i8 %41, ptr %1, align 1, !tbaa !5
  %42 = call i32 @MISO()
  %43 = icmp ne i32 %42, 0
  br i1 %43, label %44, label %47

44:                                               ; preds = %37
  %45 = load i8, ptr %1, align 1, !tbaa !5
  %46 = add i8 %45, 1
  store i8 %46, ptr %1, align 1, !tbaa !5
  br label %47

47:                                               ; preds = %44, %37
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %48 = load i8, ptr %1, align 1, !tbaa !5
  %49 = zext i8 %48 to i32
  %50 = shl i32 %49, 1
  %51 = trunc i32 %50 to i8
  store i8 %51, ptr %1, align 1, !tbaa !5
  %52 = call i32 @MISO()
  %53 = icmp ne i32 %52, 0
  br i1 %53, label %54, label %57

54:                                               ; preds = %47
  %55 = load i8, ptr %1, align 1, !tbaa !5
  %56 = add i8 %55, 1
  store i8 %56, ptr %1, align 1, !tbaa !5
  br label %57

57:                                               ; preds = %54, %47
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %58 = load i8, ptr %1, align 1, !tbaa !5
  %59 = zext i8 %58 to i32
  %60 = shl i32 %59, 1
  %61 = trunc i32 %60 to i8
  store i8 %61, ptr %1, align 1, !tbaa !5
  %62 = call i32 @MISO()
  %63 = icmp ne i32 %62, 0
  br i1 %63, label %64, label %67

64:                                               ; preds = %57
  %65 = load i8, ptr %1, align 1, !tbaa !5
  %66 = add i8 %65, 1
  store i8 %66, ptr %1, align 1, !tbaa !5
  br label %67

67:                                               ; preds = %64, %57
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %68 = load i8, ptr %1, align 1, !tbaa !5
  %69 = zext i8 %68 to i32
  %70 = shl i32 %69, 1
  %71 = trunc i32 %70 to i8
  store i8 %71, ptr %1, align 1, !tbaa !5
  %72 = call i32 @MISO()
  %73 = icmp ne i32 %72, 0
  br i1 %73, label %74, label %77

74:                                               ; preds = %67
  %75 = load i8, ptr %1, align 1, !tbaa !5
  %76 = add i8 %75, 1
  store i8 %76, ptr %1, align 1, !tbaa !5
  br label %77

77:                                               ; preds = %74, %67
  call void @CK_H()
  call void @CLK_DELAY()
  call void @CK_L()
  call void @CLK_DELAY()
  %78 = load i8, ptr %1, align 1, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 1, ptr %1) #3
  ret i8 %78
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @MOSI_H() #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CK_H() #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CLK_DELAY() #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CK_L() #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @MISO() #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @spi_receive() local_unnamed_addr #0 {
  tail call void @MOSI_H()
  %1 = tail call i32 @MISO()
  %.not = icmp eq i32 %1, 0
  %spec.select = select i1 %.not, i8 0, i8 2
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %2 = tail call i32 @MISO()
  %.not16 = icmp ne i32 %2, 0
  %3 = zext i1 %.not16 to i8
  %.1 = or disjoint i8 %spec.select, %3
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %4 = tail call i32 @MISO()
  %.not17.not = icmp eq i32 %4, 0
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %5 = shl nuw nsw i8 %.1, 2
  %6 = select i1 %.not17.not, i8 0, i8 2
  %7 = or disjoint i8 %6, %5
  %8 = tail call i32 @MISO()
  %.not18 = icmp ne i32 %8, 0
  %9 = zext i1 %.not18 to i8
  %.3 = or disjoint i8 %7, %9
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %10 = tail call i32 @MISO()
  %.not19.not = icmp eq i32 %10, 0
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %11 = shl nuw nsw i8 %.3, 2
  %12 = select i1 %.not19.not, i8 0, i8 2
  %13 = or disjoint i8 %12, %11
  %14 = tail call i32 @MISO()
  %.not20 = icmp ne i32 %14, 0
  %15 = zext i1 %.not20 to i8
  %.5 = or disjoint i8 %13, %15
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %16 = tail call i32 @MISO()
  %.not21.not = icmp eq i32 %16, 0
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  %17 = shl nuw i8 %.5, 2
  %18 = select i1 %.not21.not, i8 0, i8 2
  %19 = or disjoint i8 %18, %17
  %20 = tail call i32 @MISO()
  %.not22 = icmp ne i32 %20, 0
  %21 = zext i1 %.not22 to i8
  %.7 = or disjoint i8 %19, %21
  tail call void @CK_H()
  tail call void @CLK_DELAY()
  tail call void @CK_L()
  tail call void @CLK_DELAY()
  ret i8 %.7
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @MOSI_H() local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CK_H() local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CLK_DELAY() local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @CK_L() local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @MISO() local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass