; LLVM IR from QiaoLiuHit/LSOTB-TIR :: vlfeat-0.9.19/vl/host.ll (vl_x86cpu_info_init)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._VlX86CpuInfo = type { %union.anon, i32, i32, i32, i32, i32, i32, i32 }
%union.anon = type { [8 x i32] }

; Function Attrs: nounwind uwtable
define dso_local void @_vl_x86cpu_info_init(ptr noundef %0) #0 {
  %2 = alloca ptr, align 8
  %3 = alloca [4 x i32], align 16
  %4 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  %5 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 0
  call void @_vl_cpuid(ptr noundef %5, i32 noundef 0)
  %6 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 0
  %7 = load i32, ptr %6, align 16, !tbaa !9
  store i32 %7, ptr %4, align 4, !tbaa !9
  %8 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 1
  %9 = load i32, ptr %8, align 4, !tbaa !9
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %10, i32 0, i32 0
  %12 = getelementptr inbounds [8 x i32], ptr %11, i64 0, i64 0
  store i32 %9, ptr %12, align 4, !tbaa !11
  %13 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 3
  %14 = load i32, ptr %13, align 4, !tbaa !9
  %15 = load ptr, ptr %2, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %15, i32 0, i32 0
  %17 = getelementptr inbounds [8 x i32], ptr %16, i64 0, i64 1
  store i32 %14, ptr %17, align 4, !tbaa !11
  %18 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 2
  %19 = load i32, ptr %18, align 8, !tbaa !9
  %20 = load ptr, ptr %2, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %20, i32 0, i32 0
  %22 = getelementptr inbounds [8 x i32], ptr %21, i64 0, i64 2
  store i32 %19, ptr %22, align 4, !tbaa !11
  %23 = load i32, ptr %4, align 4, !tbaa !9
  %24 = icmp sge i32 %23, 1
  br i1 %24, label %25, label %62

25:                                               ; preds = %1
  %26 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 0
  call void @_vl_cpuid(ptr noundef %26, i32 noundef 1)
  %27 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 3
  %28 = load i32, ptr %27, align 4, !tbaa !9
  %29 = and i32 %28, 8388608
  %30 = load ptr, ptr %2, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %30, i32 0, i32 7
  store i32 %29, ptr %31, align 4, !tbaa !12
  %32 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 3
  %33 = load i32, ptr %32, align 4, !tbaa !9
  %34 = and i32 %33, 33554432
  %35 = load ptr, ptr %2, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %35, i32 0, i32 6
  store i32 %34, ptr %36, align 4, !tbaa !14
  %37 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 3
  %38 = load i32, ptr %37, align 4, !tbaa !9
  %39 = and i32 %38, 67108864
  %40 = load ptr, ptr %2, align 8, !tbaa !5
  %41 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %40, i32 0, i32 5
  store i32 %39, ptr %41, align 4, !tbaa !15
  %42 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 2
  %43 = load i32, ptr %42, align 8, !tbaa !9
  %44 = and i32 %43, 1
  %45 = load ptr, ptr %2, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %45, i32 0, i32 4
  store i32 %44, ptr %46, align 4, !tbaa !16
  %47 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 2
  %48 = load i32, ptr %47, align 8, !tbaa !9
  %49 = and i32 %48, 524288
  %50 = load ptr, ptr %2, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %50, i32 0, i32 3
  store i32 %49, ptr %51, align 4, !tbaa !17
  %52 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 2
  %53 = load i32, ptr %52, align 8, !tbaa !9
  %54 = and i32 %53, 1048576
  %55 = load ptr, ptr %2, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %55, i32 0, i32 2
  store i32 %54, ptr %56, align 4, !tbaa !18
  %57 = getelementptr inbounds [4 x i32], ptr %3, i64 0, i64 2
  %58 = load i32, ptr %57, align 8, !tbaa !9
  %59 = and i32 %58, 268435456
  %60 = load ptr, ptr %2, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct._VlX86CpuInfo, ptr %60, i32 0, i32 1
  store i32 %59, ptr %61, align 4, !tbaa !19
  br label %62

62:                                               ; preds = %25, %1
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 16, ptr %3) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @_vl_cpuid(ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 56}
!13 = !{!"_VlX86CpuInfo", !7, i64 0, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56}
!14 = !{!13, !10, i64 52}
!15 = !{!13, !10, i64 48}
!16 = !{!13, !10, i64 44}
!17 = !{!13, !10, i64 40}
!18 = !{!13, !10, i64 36}
!19 = !{!13, !10, i64 32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @_vl_x86cpu_info_init(ptr nocapture noundef writeonly %0) local_unnamed_addr #0 {
  %2 = alloca [4 x i32], align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) #3
  call void @_vl_cpuid(ptr noundef nonnull %2, i32 noundef 0)
  %3 = load i32, ptr %2, align 16, !tbaa !5
  %4 = getelementptr inbounds i8, ptr %2, i64 4
  %5 = load i32, ptr %4, align 4, !tbaa !5
  store i32 %5, ptr %0, align 4, !tbaa !9
  %6 = getelementptr inbounds i8, ptr %0, i64 4
  %7 = getelementptr inbounds i8, ptr %2, i64 8
  %8 = load <2 x i32>, ptr %7, align 8, !tbaa !5
  %9 = shufflevector <2 x i32> %8, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
  store <2 x i32> %9, ptr %6, align 4, !tbaa !9
  %10 = icmp sgt i32 %3, 0
  br i1 %10, label %11, label %24

11:                                               ; preds = %1
  %12 = getelementptr inbounds i8, ptr %2, i64 12
  call void @_vl_cpuid(ptr noundef nonnull %2, i32 noundef 1)
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = and i32 %13, 8388608
  %15 = getelementptr inbounds i8, ptr %0, i64 56
  store i32 %14, ptr %15, align 4, !tbaa !10
  %16 = getelementptr inbounds i8, ptr %0, i64 48
  %17 = insertelement <2 x i32> poison, i32 %13, i64 0
  %18 = shufflevector <2 x i32> %17, <2 x i32> poison, <2 x i32> zeroinitializer
  %19 = and <2 x i32> %18, <i32 67108864, i32 33554432>
  store <2 x i32> %19, ptr %16, align 4, !tbaa !5
  %20 = load <4 x i32>, ptr %2, align 16
  %21 = getelementptr inbounds i8, ptr %0, i64 32
  %22 = shufflevector <4 x i32> %20, <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
  %23 = and <4 x i32> %22, <i32 268435456, i32 1048576, i32 524288, i32 1>
  store <4 x i32> %23, ptr %21, align 4, !tbaa !5
  br label %24

24:                                               ; preds = %11, %1
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) #3
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @_vl_cpuid(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !6, i64 56}
!11 = !{!"_VlX86CpuInfo", !7, i64 0, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !6, i64 52, !6, i64 56}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SLPVectorizerPass,SROAPass,VectorCombinePass