; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/FIRMWARE/EXAMPLES (test_ir_remote)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @nec_read_bit() #1

; Function Attrs: nounwind uwtable
define dso_local i32 @sharp_read() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #4
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %6

6:                                                ; preds = %10, %0
  %7 = call i32 @ir_status()
  %8 = icmp ne i32 %7, 0
  %9 = xor i1 %8, true
  br i1 %9, label %10, label %11

10:                                               ; preds = %6
  br label %6, !llvm.loop !9

11:                                               ; preds = %6
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  store i32 0, ptr %3, align 4, !tbaa !5
  br label %12

12:                                               ; preds = %29, %11
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %14 = icmp slt i32 %13, 13
  br i1 %14, label %16, label %15

15:                                               ; preds = %12
  store i32 4, ptr %4, align 4
  br label %32

16:                                               ; preds = %12
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %17 = call i32 @nec_read_bit()
  store i32 %17, ptr %5, align 4, !tbaa !5
  %18 = load i32, ptr %5, align 4, !tbaa !5
  %19 = icmp eq i32 %18, -1
  br i1 %19, label %20, label %21

20:                                               ; preds = %16
  store i32 0, ptr %1, align 4
  store i32 1, ptr %4, align 4
  br label %26

21:                                               ; preds = %16
  %22 = load i32, ptr %2, align 4, !tbaa !5
  %23 = shl i32 %22, 1
  %24 = load i32, ptr %5, align 4, !tbaa !5
  %25 = or i32 %23, %24
  store i32 %25, ptr %2, align 4, !tbaa !5
  store i32 0, ptr %4, align 4
  br label %26

26:                                               ; preds = %21, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  %27 = load i32, ptr %4, align 4
  switch i32 %27, label %32 [
    i32 0, label %28
  ]

28:                                               ; preds = %26
  br label %29

29:                                               ; preds = %28
  %30 = load i32, ptr %3, align 4, !tbaa !5
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %3, align 4, !tbaa !5
  br label %12, !llvm.loop !11

32:                                               ; preds = %26, %15
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  %33 = load i32, ptr %4, align 4
  switch i32 %33, label %44 [
    i32 4, label %34
  ]

34:                                               ; preds = %32
  %35 = call i32 @nec_read_bit()
  %36 = icmp eq i32 %35, -1
  br i1 %36, label %37, label %38

37:                                               ; preds = %34
  store i32 0, ptr %1, align 4
  store i32 1, ptr %4, align 4
  br label %44

38:                                               ; preds = %34
  %39 = call i32 @nec_read_bit()
  %40 = icmp eq i32 %39, -1
  br i1 %40, label %41, label %42

41:                                               ; preds = %38
  store i32 0, ptr %1, align 4
  store i32 1, ptr %4, align 4
  br label %44

42:                                               ; preds = %38
  call void @milliwait(i32 noundef 250)
  %43 = load i32, ptr %2, align 4, !tbaa !5
  store i32 %43, ptr %1, align 4
  store i32 1, ptr %4, align 4
  br label %44

44:                                               ; preds = %42, %41, %37, %32
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #4
  %45 = load i32, ptr %1, align 4
  ret i32 %45
}

declare void @milliwait(i32 noundef) #2

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @ir_status() #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @nec_read_bit() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @sharp_read() local_unnamed_addr #0 {
  br label %1

1:                                                ; preds = %1, %0
  %2 = tail call i32 @ir_status()
  %.not = icmp eq i32 %2, 0
  br i1 %.not, label %1, label %.preheader.preheader, !llvm.loop !5

.preheader.preheader:                             ; preds = %1
  %3 = tail call i32 @nec_read_bit()
  %.not17 = icmp eq i32 %3, -1
  br i1 %.not17, label %.loopexit, label %.preheader.1

.preheader.1:                                     ; preds = %.preheader.preheader
  %4 = tail call i32 @nec_read_bit()
  %.not17.1 = icmp eq i32 %4, -1
  br i1 %.not17.1, label %.loopexit, label %.preheader.2

.preheader.2:                                     ; preds = %.preheader.1
  %5 = tail call i32 @nec_read_bit()
  %.not17.2 = icmp eq i32 %5, -1
  br i1 %.not17.2, label %.loopexit, label %.preheader.3

.preheader.3:                                     ; preds = %.preheader.2
  %6 = tail call i32 @nec_read_bit()
  %.not17.3 = icmp eq i32 %6, -1
  br i1 %.not17.3, label %.loopexit, label %.preheader.4

.preheader.4:                                     ; preds = %.preheader.3
  %7 = tail call i32 @nec_read_bit()
  %.not17.4 = icmp eq i32 %7, -1
  br i1 %.not17.4, label %.loopexit, label %.preheader.5

.preheader.5:                                     ; preds = %.preheader.4
  %8 = tail call i32 @nec_read_bit()
  %.not17.5 = icmp eq i32 %8, -1
  br i1 %.not17.5, label %.loopexit, label %.preheader.6

.preheader.6:                                     ; preds = %.preheader.5
  %9 = tail call i32 @nec_read_bit()
  %.not17.6 = icmp eq i32 %9, -1
  br i1 %.not17.6, label %.loopexit, label %.preheader.7

.preheader.7:                                     ; preds = %.preheader.6
  %10 = tail call i32 @nec_read_bit()
  %.not17.7 = icmp eq i32 %10, -1
  br i1 %.not17.7, label %.loopexit, label %.preheader.8

.preheader.8:                                     ; preds = %.preheader.7
  %11 = tail call i32 @nec_read_bit()
  %.not17.8 = icmp eq i32 %11, -1
  br i1 %.not17.8, label %.loopexit, label %.preheader.9

.preheader.9:                                     ; preds = %.preheader.8
  %12 = tail call i32 @nec_read_bit()
  %.not17.9 = icmp eq i32 %12, -1
  br i1 %.not17.9, label %.loopexit, label %.preheader.10

.preheader.10:                                    ; preds = %.preheader.9
  %13 = tail call i32 @nec_read_bit()
  %.not17.10 = icmp eq i32 %13, -1
  br i1 %.not17.10, label %.loopexit, label %.preheader.11

.preheader.11:                                    ; preds = %.preheader.10
  %14 = tail call i32 @nec_read_bit()
  %.not17.11 = icmp eq i32 %14, -1
  br i1 %.not17.11, label %.loopexit, label %.preheader.12

.preheader.12:                                    ; preds = %.preheader.11
  %15 = tail call i32 @nec_read_bit()
  %.not17.12 = icmp eq i32 %15, -1
  br i1 %.not17.12, label %.loopexit, label %16

16:                                               ; preds = %.preheader.12
  %17 = shl i32 %3, 2
  %18 = shl i32 %4, 1
  %19 = or i32 %17, %18
  %20 = or i32 %5, %19
  %21 = shl i32 %20, 2
  %22 = shl i32 %6, 1
  %23 = or i32 %21, %22
  %24 = or i32 %7, %23
  %25 = shl i32 %24, 2
  %26 = shl i32 %8, 1
  %27 = or i32 %25, %26
  %28 = or i32 %9, %27
  %29 = shl i32 %28, 2
  %30 = shl i32 %10, 1
  %31 = or i32 %29, %30
  %32 = or i32 %11, %31
  %33 = shl i32 %32, 2
  %34 = shl i32 %12, 1
  %35 = or i32 %33, %34
  %36 = or i32 %13, %35
  %37 = shl i32 %36, 2
  %38 = shl i32 %14, 1
  %39 = or i32 %37, %38
  %40 = or i32 %15, %39
  %41 = tail call i32 @nec_read_bit()
  %42 = icmp eq i32 %41, -1
  br i1 %42, label %.loopexit, label %43

43:                                               ; preds = %16
  %44 = tail call i32 @nec_read_bit()
  %45 = icmp eq i32 %44, -1
  br i1 %45, label %.loopexit, label %46

46:                                               ; preds = %43
  tail call void @milliwait(i32 noundef 250) #3
  br label %.loopexit

.loopexit:                                        ; preds = %.preheader.preheader, %.preheader.1, %.preheader.2, %.preheader.3, %.preheader.4, %.preheader.5, %.preheader.6, %.preheader.7, %.preheader.8, %.preheader.9, %.preheader.10, %.preheader.11, %.preheader.12, %43, %16, %46
  %.3 = phi i32 [ %40, %46 ], [ 0, %16 ], [ 0, %43 ], [ 0, %.preheader.12 ], [ 0, %.preheader.11 ], [ 0, %.preheader.10 ], [ 0, %.preheader.9 ], [ 0, %.preheader.8 ], [ 0, %.preheader.7 ], [ 0, %.preheader.6 ], [ 0, %.preheader.5 ], [ 0, %.preheader.4 ], [ 0, %.preheader.3 ], [ 0, %.preheader.2 ], [ 0, %.preheader.1 ], [ 0, %.preheader.preheader ]
  ret i32 %.3
}

declare void @milliwait(i32 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden i32 @ir_status() local_unnamed_addr #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass