; LLVM IR from QiaoLiuHit/LSOTB-TIR :: vlfeat-0.9.19/vl (mathop)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: noreturn nounwind
declare void @abort() #1

declare i32 @vl_cpu_has_sse2() #2

declare i32 @vl_get_simd_enabled() #2

declare i32 @vl_cpu_has_avx() #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_l2_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_l1_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_chi2_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_hellinger_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_js_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_l2_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_l1_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_chi2_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_hellinger_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_js_d(i64 noundef, ptr noundef, ptr noundef) #3

; Function Attrs: nounwind uwtable
define dso_local ptr @vl_get_vector_comparison_function_d(i32 noundef %0) #3 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #4
  store ptr null, ptr %3, align 8, !tbaa !9
  %4 = load i32, ptr %2, align 4, !tbaa !5
  switch i32 %4, label %15 [
    i32 1, label %5
    i32 0, label %6
    i32 2, label %7
    i32 3, label %8
    i32 4, label %9
    i32 7, label %10
    i32 6, label %11
    i32 8, label %12
    i32 9, label %13
    i32 10, label %14
  ]

5:                                                ; preds = %1
  store ptr @_vl_distance_l2_d, ptr %3, align 8, !tbaa !9
  br label %16

6:                                                ; preds = %1
  store ptr @_vl_distance_l1_d, ptr %3, align 8, !tbaa !9
  br label %16

7:                                                ; preds = %1
  store ptr @_vl_distance_chi2_d, ptr %3, align 8, !tbaa !9
  br label %16

8:                                                ; preds = %1
  store ptr @_vl_distance_hellinger_d, ptr %3, align 8, !tbaa !9
  br label %16

9:                                                ; preds = %1
  store ptr @_vl_distance_js_d, ptr %3, align 8, !tbaa !9
  br label %16

10:                                               ; preds = %1
  store ptr @_vl_kernel_l2_d, ptr %3, align 8, !tbaa !9
  br label %16

11:                                               ; preds = %1
  store ptr @_vl_kernel_l1_d, ptr %3, align 8, !tbaa !9
  br label %16

12:                                               ; preds = %1
  store ptr @_vl_kernel_chi2_d, ptr %3, align 8, !tbaa !9
  br label %16

13:                                               ; preds = %1
  store ptr @_vl_kernel_hellinger_d, ptr %3, align 8, !tbaa !9
  br label %16

14:                                               ; preds = %1
  store ptr @_vl_kernel_js_d, ptr %3, align 8, !tbaa !9
  br label %16

15:                                               ; preds = %1
  call void @abort() #5
  unreachable

16:                                               ; preds = %14, %13, %12, %11, %10, %9, %8, %7, %6, %5
  %17 = call i32 @vl_cpu_has_sse2()
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %32

19:                                               ; preds = %16
  %20 = call i32 @vl_get_simd_enabled()
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %32

22:                                               ; preds = %19
  %23 = load i32, ptr %2, align 4, !tbaa !5
  switch i32 %23, label %30 [
    i32 1, label %24
    i32 0, label %25
    i32 2, label %26
    i32 7, label %27
    i32 6, label %28
    i32 8, label %29
  ]

24:                                               ; preds = %22
  store ptr @_vl_distance_l2_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

25:                                               ; preds = %22
  store ptr @_vl_distance_l1_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

26:                                               ; preds = %22
  store ptr @_vl_distance_chi2_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

27:                                               ; preds = %22
  store ptr @_vl_kernel_l2_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

28:                                               ; preds = %22
  store ptr @_vl_kernel_l1_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

29:                                               ; preds = %22
  store ptr @_vl_kernel_chi2_sse2_d, ptr %3, align 8, !tbaa !9
  br label %31

30:                                               ; preds = %22
  br label %31

31:                                               ; preds = %30, %29, %28, %27, %26, %25, %24
  br label %32

32:                                               ; preds = %31, %19, %16
  %33 = call i32 @vl_cpu_has_avx()
  %34 = icmp ne i32 %33, 0
  br i1 %34, label %35, label %43

35:                                               ; preds = %32
  %36 = call i32 @vl_get_simd_enabled()
  %37 = icmp ne i32 %36, 0
  br i1 %37, label %38, label %43

38:                                               ; preds = %35
  %39 = load i32, ptr %2, align 4, !tbaa !5
  switch i32 %39, label %41 [
    i32 1, label %40
  ]

40:                                               ; preds = %38
  store ptr @_vl_distance_l2_avx_d, ptr %3, align 8, !tbaa !9
  br label %42

41:                                               ; preds = %38
  br label %42

42:                                               ; preds = %41, %40
  br label %43

43:                                               ; preds = %42, %35, %32
  %44 = load ptr, ptr %3, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #4
  ret ptr %44
}

declare double @_vl_distance_l2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_distance_l1_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_distance_chi2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_kernel_l2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_kernel_l1_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_kernel_chi2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #2

declare double @_vl_distance_l2_avx_d(i64 noundef, ptr noundef, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table.vl_get_vector_comparison_function_d = private unnamed_addr constant [11 x ptr] [ptr @_vl_distance_l1_d, ptr @_vl_distance_l2_d, ptr @_vl_distance_chi2_d, ptr @_vl_distance_hellinger_d, ptr @_vl_distance_js_d, ptr @_vl_distance_l2_d, ptr @_vl_kernel_l1_d, ptr @_vl_kernel_l2_d, ptr @_vl_kernel_chi2_d, ptr @_vl_kernel_hellinger_d, ptr @_vl_kernel_js_d], align 8
@switch.table.vl_get_vector_comparison_function_d.1 = private unnamed_addr constant [9 x ptr] [ptr @_vl_distance_l1_sse2_d, ptr @_vl_distance_l2_sse2_d, ptr @_vl_distance_chi2_sse2_d, ptr @_vl_distance_l2_sse2_d, ptr @_vl_distance_l2_sse2_d, ptr @_vl_distance_l2_sse2_d, ptr @_vl_kernel_l1_sse2_d, ptr @_vl_kernel_l2_sse2_d, ptr @_vl_kernel_chi2_sse2_d], align 8

; Function Attrs: noreturn nounwind
declare void @abort() local_unnamed_addr #0

declare i32 @vl_cpu_has_sse2() local_unnamed_addr #1

declare i32 @vl_get_simd_enabled() local_unnamed_addr #1

declare i32 @vl_cpu_has_avx() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_l2_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_l1_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_chi2_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_hellinger_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_distance_js_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_l2_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_l1_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_chi2_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_hellinger_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local double @_vl_kernel_js_d(i64 noundef, ptr noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local nonnull ptr @vl_get_vector_comparison_function_d(i32 noundef %0) local_unnamed_addr #2 {
  %2 = icmp ult i32 %0, 11
  br i1 %2, label %switch.hole_check, label %3

3:                                                ; preds = %switch.hole_check, %1
  tail call void @abort() #3
  unreachable

switch.hole_check:                                ; preds = %1
  %switch.maskindex = trunc nuw i32 %0 to i16
  %switch.shifted = lshr i16 2015, %switch.maskindex
  %switch.lobit = trunc i16 %switch.shifted to i1
  br i1 %switch.lobit, label %switch.lookup, label %3

switch.lookup:                                    ; preds = %switch.hole_check
  %4 = zext nneg i32 %0 to i64
  %switch.gep = getelementptr inbounds [11 x ptr], ptr @switch.table.vl_get_vector_comparison_function_d, i64 0, i64 %4
  %switch.load = load ptr, ptr %switch.gep, align 8
  %5 = tail call i32 @vl_cpu_has_sse2() #4
  %.not = icmp eq i32 %5, 0
  br i1 %.not, label %10, label %6

6:                                                ; preds = %switch.lookup
  %7 = tail call i32 @vl_get_simd_enabled() #4
  %.not3 = icmp ne i32 %7, 0
  %8 = icmp ult i32 %0, 9
  %or.cond13 = and i1 %.not3, %8
  br i1 %or.cond13, label %switch.hole_check6, label %10

switch.hole_check6:                               ; preds = %6
  %switch.maskindex8 = trunc nuw i32 %0 to i16
  %switch.shifted9 = lshr i16 455, %switch.maskindex8
  %switch.lobit10 = trunc i16 %switch.shifted9 to i1
  br i1 %switch.lobit10, label %switch.lookup7, label %10

switch.lookup7:                                   ; preds = %switch.hole_check6
  %9 = zext nneg i32 %0 to i64
  %switch.gep11 = getelementptr inbounds [9 x ptr], ptr @switch.table.vl_get_vector_comparison_function_d.1, i64 0, i64 %9
  %switch.load12 = load ptr, ptr %switch.gep11, align 8
  br label %10

10:                                               ; preds = %switch.lookup7, %switch.hole_check6, %6, %switch.lookup
  %.1 = phi ptr [ %switch.load, %6 ], [ %switch.load, %switch.lookup ], [ %switch.load, %switch.hole_check6 ], [ %switch.load12, %switch.lookup7 ]
  %11 = tail call i32 @vl_cpu_has_avx() #4
  %.not4 = icmp eq i32 %11, 0
  br i1 %.not4, label %15, label %12

12:                                               ; preds = %10
  %13 = tail call i32 @vl_get_simd_enabled() #4
  %14 = icmp ne i32 %13, 0
  %cond = icmp eq i32 %0, 1
  %or.cond = and i1 %cond, %14
  %spec.select = select i1 %or.cond, ptr @_vl_distance_l2_avx_d, ptr %.1
  br label %15

15:                                               ; preds = %12, %10
  %.2 = phi ptr [ %.1, %10 ], [ %spec.select, %12 ]
  ret ptr %.2
}

declare double @_vl_distance_l2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_distance_l1_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_distance_chi2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_kernel_l2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_kernel_l1_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_kernel_chi2_sse2_d(i64 noundef, ptr noundef, ptr noundef) #1

declare double @_vl_distance_l2_avx_d(i64 noundef, ptr noundef, ptr noundef) #1

attributes #0 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass