; LLVM IR from embeddednirvana/A-Rudimentary-RTOS-for-Satellite-Control :: device (sd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._AT91S_PIO = type { i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [9 x i32], i32, i32, i32 }
%struct._sd = type { i32, i32, i8 }

@error = external dso_local global i8, align 1
@arguments = external dso_local global [4 x i8], align 1
@response = external dso_local global [8 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @sd_delay(i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @sd_send_command(ptr noundef, i8 noundef zeroext, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @sd_read_block(ptr noundef %0, i32 noundef %1, ptr noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  br label %12

12:                                               ; preds = %15, %3
  %13 = call zeroext i8 @SPI_IsFinished(ptr noundef inttoptr (i64 4294836224 to ptr))
  %14 = icmp ne i8 %13, 0
  br i1 %14, label %15, label %16

15:                                               ; preds = %12
  br label %12, !llvm.loop !11

16:                                               ; preds = %12
  %17 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %18 = and i32 %17, -8193
  store volatile i32 %18, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %19 = load i32, ptr %6, align 4, !tbaa !9
  call void @sd_packarg(ptr noundef @arguments, i32 noundef %19)
  %20 = load ptr, ptr %5, align 8, !tbaa !5
  %21 = call i32 @sd_send_command(ptr noundef %20, i8 noundef zeroext 17, i8 noundef zeroext 1)
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %24, label %23

23:                                               ; preds = %16
  store i32 0, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %98

24:                                               ; preds = %16
  call void @sd_delay(i16 noundef zeroext 1)
  %25 = load i8, ptr @response, align 1, !tbaa !15
  %26 = zext i8 %25 to i32
  %27 = icmp ne i32 %26, 0
  br i1 %27, label %28, label %35

28:                                               ; preds = %24
  %29 = load i8, ptr @error, align 1, !tbaa !15
  %30 = zext i8 %29 to i32
  %31 = or i32 %30, 4
  %32 = trunc i32 %31 to i8
  store i8 %32, ptr @error, align 1, !tbaa !15
  %33 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %34 = or i32 %33, 8192
  store volatile i32 %34, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  store i32 0, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %98

35:                                               ; preds = %24
  store i8 0, ptr %8, align 1, !tbaa !15
  br label %36

36:                                               ; preds = %52, %35
  %37 = load i8, ptr %8, align 1, !tbaa !15
  %38 = add i8 %37, 1
  store i8 %38, ptr %8, align 1, !tbaa !15
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  %39 = call zeroext i16 @SPI_Read(ptr noundef inttoptr (i64 4294836224 to ptr))
  %40 = trunc i16 %39 to i8
  store i8 %40, ptr %9, align 1, !tbaa !15
  br label %41

41:                                               ; preds = %36
  %42 = load i8, ptr %9, align 1, !tbaa !15
  %43 = zext i8 %42 to i32
  %44 = icmp eq i32 %43, 255
  br i1 %44, label %45, label %52

45:                                               ; preds = %41
  %46 = load i8, ptr %8, align 1, !tbaa !15
  %47 = zext i8 %46 to i32
  %48 = load ptr, ptr %5, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct._sd, ptr %48, i32 0, i32 1
  %50 = load i32, ptr %49, align 4, !tbaa !16
  %51 = icmp ule i32 %47, %50
  br label %52

52:                                               ; preds = %45, %41
  %53 = phi i1 [ false, %41 ], [ %51, %45 ]
  br i1 %53, label %36, label %54, !llvm.loop !18

54:                                               ; preds = %52
  %55 = load i8, ptr %8, align 1, !tbaa !15
  %56 = zext i8 %55 to i32
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct._sd, ptr %57, i32 0, i32 1
  %59 = load i32, ptr %58, align 4, !tbaa !16
  %60 = icmp ugt i32 %56, %59
  br i1 %60, label %61, label %68

61:                                               ; preds = %54
  %62 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %63 = or i32 %62, 8192
  store volatile i32 %63, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %64 = load i8, ptr @error, align 1, !tbaa !15
  %65 = zext i8 %64 to i32
  %66 = or i32 %65, 8
  %67 = trunc i32 %66 to i8
  store i8 %67, ptr @error, align 1, !tbaa !15
  store i32 0, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %98

68:                                               ; preds = %54
  %69 = load i8, ptr %9, align 1, !tbaa !15
  %70 = zext i8 %69 to i32
  %71 = and i32 %70, 224
  %72 = icmp eq i32 %71, 0
  br i1 %72, label %73, label %78

73:                                               ; preds = %68
  %74 = load i8, ptr @error, align 1, !tbaa !15
  %75 = zext i8 %74 to i32
  %76 = or i32 %75, 16
  %77 = trunc i32 %76 to i8
  store i8 %77, ptr @error, align 1, !tbaa !15
  br label %78

78:                                               ; preds = %73, %68
  %79 = load i8, ptr %9, align 1, !tbaa !15
  %80 = load ptr, ptr %7, align 8, !tbaa !5
  %81 = getelementptr inbounds i8, ptr %80, i64 0
  store i8 %79, ptr %81, align 1, !tbaa !15
  store i32 0, ptr %10, align 4, !tbaa !9
  br label %82

82:                                               ; preds = %92, %78
  %83 = load i32, ptr %10, align 4, !tbaa !9
  %84 = icmp slt i32 %83, 512
  br i1 %84, label %85, label %95

85:                                               ; preds = %82
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255)
  %86 = call zeroext i16 @SPI_Read(ptr noundef inttoptr (i64 4294836224 to ptr))
  %87 = trunc i16 %86 to i8
  %88 = load ptr, ptr %7, align 8, !tbaa !5
  %89 = load i32, ptr %10, align 4, !tbaa !9
  %90 = sext i32 %89 to i64
  %91 = getelementptr inbounds i8, ptr %88, i64 %90
  store i8 %87, ptr %91, align 1, !tbaa !15
  br label %92

92:                                               ; preds = %85
  %93 = load i32, ptr %10, align 4, !tbaa !9
  %94 = add nsw i32 %93, 1
  store i32 %94, ptr %10, align 4, !tbaa !9
  br label %82, !llvm.loop !19

95:                                               ; preds = %82
  call void @sd_delay(i16 noundef zeroext 4)
  %96 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  %97 = or i32 %96, 8192
  store volatile i32 %97, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !13
  store i32 1, ptr %4, align 4
  store i32 1, ptr %11, align 4
  br label %98

98:                                               ; preds = %95, %61, %28, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  %99 = load i32, ptr %4, align 4
  ret i32 %99
}

declare zeroext i8 @SPI_IsFinished(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @sd_packarg(ptr noundef, i32 noundef) #1

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) #2

declare zeroext i16 @SPI_Read(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !10, i64 56}
!14 = !{!"_AT91S_PIO", !10, i64 0, !10, i64 4, !10, i64 8, !7, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !7, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !7, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !7, i64 92, !10, i64 96, !10, i64 100, !10, i64 104, !7, i64 108, !10, i64 112, !10, i64 116, !10, i64 120, !7, i64 124, !10, i64 160, !10, i64 164, !10, i64 168}
!15 = !{!7, !7, i64 0}
!16 = !{!17, !10, i64 4}
!17 = !{!"_sd", !10, i64 0, !10, i64 4, !7, i64 8}
!18 = distinct !{!18, !12}
!19 = distinct !{!19, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@error = external dso_local local_unnamed_addr global i8, align 1
@arguments = external dso_local global [4 x i8], align 1
@response = external dso_local local_unnamed_addr global [8 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local void @sd_delay(i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @sd_send_command(ptr noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @sd_read_block(ptr noundef %0, i32 noundef %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 {
  br label %4

4:                                                ; preds = %4, %3
  %5 = tail call zeroext i8 @SPI_IsFinished(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %.not = icmp eq i8 %5, 0
  br i1 %.not, label %6, label %4, !llvm.loop !5

6:                                                ; preds = %4
  %7 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %8 = and i32 %7, -8193
  store volatile i32 %8, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  tail call void @sd_packarg(ptr noundef nonnull @arguments, i32 noundef %1)
  %9 = tail call i32 @sd_send_command(ptr noundef %0, i8 noundef zeroext 17, i8 noundef zeroext 1)
  %.not17 = icmp eq i32 %9, 0
  br i1 %.not17, label %44, label %10

10:                                               ; preds = %6
  tail call void @sd_delay(i16 noundef zeroext 1)
  %11 = load i8, ptr @response, align 1, !tbaa !12
  %.not18 = icmp eq i8 %11, 0
  br i1 %.not18, label %.preheader, label %13

.preheader:                                       ; preds = %10
  %12 = getelementptr inbounds i8, ptr %0, i64 4
  br label %18

13:                                               ; preds = %10
  %14 = load i8, ptr @error, align 1, !tbaa !12
  %15 = or i8 %14, 4
  store i8 %15, ptr @error, align 1, !tbaa !12
  %16 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %17 = or i32 %16, 8192
  store volatile i32 %17, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  br label %44

18:                                               ; preds = %18, %.preheader
  %.016 = phi i8 [ 0, %.preheader ], [ %19, %18 ]
  %19 = add i8 %.016, 1
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  %20 = tail call zeroext i16 @SPI_Read(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %.mask = and i16 %20, 255
  %21 = icmp ne i16 %.mask, 255
  %.pre = load i32, ptr %12, align 4, !tbaa !13
  %22 = zext i8 %19 to i32
  %.not19 = icmp ult i32 %.pre, %22
  %or.cond = select i1 %21, i1 true, i1 %.not19
  br i1 %or.cond, label %.critedge, label %18, !llvm.loop !15

.critedge:                                        ; preds = %18
  %23 = trunc i16 %20 to i8
  %24 = icmp ult i32 %.pre, %22
  br i1 %24, label %25, label %30

25:                                               ; preds = %.critedge
  %26 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %27 = or i32 %26, 8192
  store volatile i32 %27, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %28 = load i8, ptr @error, align 1, !tbaa !12
  %29 = or i8 %28, 8
  store i8 %29, ptr @error, align 1, !tbaa !12
  br label %44

30:                                               ; preds = %.critedge
  %31 = and i16 %20, 224
  %32 = icmp eq i16 %31, 0
  br i1 %32, label %33, label %36

33:                                               ; preds = %30
  %34 = load i8, ptr @error, align 1, !tbaa !12
  %35 = or i8 %34, 16
  store i8 %35, ptr @error, align 1, !tbaa !12
  br label %36

36:                                               ; preds = %33, %30
  store i8 %23, ptr %2, align 1, !tbaa !12
  br label %37

37:                                               ; preds = %36, %37
  %indvars.iv = phi i64 [ 0, %36 ], [ %indvars.iv.next, %37 ]
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 255) #2
  %38 = tail call zeroext i16 @SPI_Read(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %39 = trunc i16 %38 to i8
  %40 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv
  store i8 %39, ptr %40, align 1, !tbaa !12
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, 512
  br i1 %exitcond.not, label %41, label %37, !llvm.loop !16

41:                                               ; preds = %37
  tail call void @sd_delay(i16 noundef zeroext 4)
  %42 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %43 = or i32 %42, 8192
  store volatile i32 %43, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  br label %44

44:                                               ; preds = %6, %41, %25, %13
  %.015 = phi i32 [ 0, %13 ], [ 0, %25 ], [ 1, %41 ], [ 0, %6 ]
  ret i32 %.015
}

declare zeroext i8 @SPI_IsFinished(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @sd_packarg(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #1

declare zeroext i16 @SPI_Read(ptr noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !9, i64 56}
!8 = !{!"_AT91S_PIO", !9, i64 0, !9, i64 4, !9, i64 8, !10, i64 12, !9, i64 16, !9, i64 20, !9, i64 24, !10, i64 28, !9, i64 32, !9, i64 36, !9, i64 40, !10, i64 44, !9, i64 48, !9, i64 52, !9, i64 56, !9, i64 60, !9, i64 64, !9, i64 68, !9, i64 72, !9, i64 76, !9, i64 80, !9, i64 84, !9, i64 88, !10, i64 92, !9, i64 96, !9, i64 100, !9, i64 104, !10, i64 108, !9, i64 112, !9, i64 116, !9, i64 120, !10, i64 124, !9, i64 160, !9, i64 164, !9, i64 168}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C/C++ TBAA"}
!12 = !{!10, !10, i64 0}
!13 = !{!14, !9, i64 4}
!14 = !{!"_sd", !9, i64 0, !9, i64 4, !10, i64 8}
!15 = distinct !{!15, !6}
!16 = distinct !{!16, !6}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass