; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/SIM/FPU_funcs.ll (Z17FLT_WITH_SOFT_FPUjj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.IEEE754 = type { %union.anon }
%union.anon = type { i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z17FLT_WITH_SOFT_FPUjj(i32 noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca %class.IEEE754, align 4
  %6 = alloca %class.IEEE754, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %10 = load i32, ptr %3, align 4, !tbaa !5
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %5, i32 noundef %10)
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %11 = load i32, ptr %4, align 4, !tbaa !5
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %11)
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %12 = getelementptr inbounds %class.IEEE754, ptr %5, i32 0, i32 0
  %13 = load i32, ptr %12, align 4
  %14 = lshr i32 %13, 31
  store i32 %14, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %15 = getelementptr inbounds %class.IEEE754, ptr %6, i32 0, i32 0
  %16 = load i32, ptr %15, align 4
  %17 = lshr i32 %16, 31
  store i32 %17, ptr %8, align 4, !tbaa !5
  %18 = getelementptr inbounds %class.IEEE754, ptr %5, i32 0, i32 0
  %19 = load i32, ptr %18, align 4
  %20 = and i32 %19, 2147483647
  %21 = or i32 %20, 0
  store i32 %21, ptr %18, align 4
  %22 = getelementptr inbounds %class.IEEE754, ptr %6, i32 0, i32 0
  %23 = load i32, ptr %22, align 4
  %24 = and i32 %23, 2147483647
  %25 = or i32 %24, 0
  store i32 %25, ptr %22, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %26 = getelementptr inbounds %class.IEEE754, ptr %5, i32 0, i32 0
  %27 = load i32, ptr %26, align 4, !tbaa !9
  %28 = getelementptr inbounds %class.IEEE754, ptr %6, i32 0, i32 0
  %29 = load i32, ptr %28, align 4, !tbaa !9
  %30 = icmp ult i32 %27, %29
  %31 = zext i1 %30 to i32
  store i32 %31, ptr %9, align 4, !tbaa !5
  %32 = load i32, ptr %7, align 4, !tbaa !5
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %38

34:                                               ; preds = %2
  %35 = load i32, ptr %8, align 4, !tbaa !5
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %38, label %37

37:                                               ; preds = %34
  store i32 1, ptr %9, align 4, !tbaa !5
  br label %55

38:                                               ; preds = %34, %2
  %39 = load i32, ptr %7, align 4, !tbaa !5
  %40 = icmp ne i32 %39, 0
  br i1 %40, label %45, label %41

41:                                               ; preds = %38
  %42 = load i32, ptr %8, align 4, !tbaa !5
  %43 = icmp ne i32 %42, 0
  br i1 %43, label %44, label %45

44:                                               ; preds = %41
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %54

45:                                               ; preds = %41, %38
  %46 = load i32, ptr %7, align 4, !tbaa !5
  %47 = icmp ne i32 %46, 0
  br i1 %47, label %48, label %53

48:                                               ; preds = %45
  %49 = load i32, ptr %9, align 4, !tbaa !5
  %50 = icmp ne i32 %49, 0
  %51 = xor i1 %50, true
  %52 = zext i1 %51 to i32
  store i32 %52, ptr %9, align 4, !tbaa !5
  br label %53

53:                                               ; preds = %48, %45
  br label %54

54:                                               ; preds = %53, %44
  br label %55

55:                                               ; preds = %54, %37
  %56 = load i32, ptr %9, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 %56
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.IEEE754 = type { %union.anon }
%union.anon = type { i32 }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef range(i32 0, 2) i32 @_Z17FLT_WITH_SOFT_FPUjj(i32 noundef %0, i32 noundef %1) local_unnamed_addr #1 {
  %3 = alloca %class.IEEE754, align 4
  %4 = alloca %class.IEEE754, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %3) #2
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %3, i32 noundef %0)
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #2
  call void @_ZN7IEEE754C2Ej(ptr noundef nonnull align 4 dereferenceable(4) %4, i32 noundef %1)
  %5 = load i32, ptr %3, align 4
  %6 = load i32, ptr %4, align 4
  %7 = and i32 %5, 2147483647
  %8 = and i32 %6, 2147483647
  %9 = icmp sgt i32 %5, -1
  %10 = icmp slt i32 %6, 0
  %or.cond = select i1 %9, i1 true, i1 %10
  br i1 %or.cond, label %11, label %15

11:                                               ; preds = %2
  %or.cond3 = select i1 %9, i1 %10, i1 false
  br i1 %or.cond3, label %15, label %12

12:                                               ; preds = %11
  %13 = icmp uge i32 %7, %8
  %spec.select = xor i1 %9, %13
  %14 = zext i1 %spec.select to i32
  br label %15

15:                                               ; preds = %12, %11, %2
  %.0.shrunk = phi i32 [ 1, %2 ], [ 0, %11 ], [ %14, %12 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %3) #2
  ret i32 %.0.shrunk
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass