; LLVM IR from embeddednirvana/A-Rudimentary-RTOS-for-Satellite-Control :: device (sd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct._AT91S_PIO = type { i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, i32, [1 x i32], i32, i32, i32, [9 x i32], i32, i32, i32 }

@arguments = external dso_local global [4 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @sd_delay(i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @sd_send_command(ptr noundef, i8 noundef zeroext, i8 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @SPI_IsFinished(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @sd_packarg(ptr noundef, i32 noundef) #1

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @is_card_busy(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @sd_write_multi_block(ptr noundef %0, i32 noundef %1, ptr noundef %2, i8 noundef zeroext %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i8, align 1
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store ptr %2, ptr %8, align 8, !tbaa !5
  store i8 %3, ptr %9, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  br label %13

13:                                               ; preds = %16, %4
  %14 = call zeroext i8 @SPI_IsFinished(ptr noundef inttoptr (i64 4294836224 to ptr))
  %15 = icmp ne i8 %14, 0
  br i1 %15, label %16, label %17

16:                                               ; preds = %13
  br label %13, !llvm.loop !12

17:                                               ; preds = %13
  %18 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !14
  %19 = and i32 %18, -8193
  store volatile i32 %19, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !14
  %20 = load i32, ptr %7, align 4, !tbaa !9
  call void @sd_packarg(ptr noundef @arguments, i32 noundef %20)
  %21 = load ptr, ptr %6, align 8, !tbaa !5
  %22 = call i32 @sd_send_command(ptr noundef %21, i8 noundef zeroext 25, i8 noundef zeroext 1)
  %23 = icmp eq i32 %22, 0
  br i1 %23, label %24, label %25

24:                                               ; preds = %17
  store i32 0, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %66

25:                                               ; preds = %17
  call void @sd_delay(i16 noundef zeroext 2)
  store i32 0, ptr %11, align 4, !tbaa !9
  store i32 1, ptr %10, align 4, !tbaa !9
  br label %26

26:                                               ; preds = %54, %25
  %27 = load i32, ptr %10, align 4, !tbaa !9
  %28 = load i8, ptr %9, align 1, !tbaa !11
  %29 = zext i8 %28 to i32
  %30 = icmp ule i32 %27, %29
  br i1 %30, label %31, label %57

31:                                               ; preds = %26
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 254)
  br label %32

32:                                               ; preds = %44, %31
  %33 = load i32, ptr %11, align 4, !tbaa !9
  %34 = load i32, ptr %10, align 4, !tbaa !9
  %35 = mul i32 512, %34
  %36 = icmp ult i32 %33, %35
  br i1 %36, label %37, label %47

37:                                               ; preds = %32
  %38 = load ptr, ptr %8, align 8, !tbaa !5
  %39 = load i32, ptr %11, align 4, !tbaa !9
  %40 = zext i32 %39 to i64
  %41 = getelementptr inbounds i8, ptr %38, i64 %40
  %42 = load i8, ptr %41, align 1, !tbaa !11
  %43 = zext i8 %42 to i16
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %43)
  br label %44

44:                                               ; preds = %37
  %45 = load i32, ptr %11, align 4, !tbaa !9
  %46 = add i32 %45, 1
  store i32 %46, ptr %11, align 4, !tbaa !9
  br label %32, !llvm.loop !16

47:                                               ; preds = %32
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 149)
  call void @sd_delay(i16 noundef zeroext 1)
  br label %48

48:                                               ; preds = %52, %47
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = call i32 @is_card_busy(ptr noundef %49)
  %51 = icmp ne i32 %50, 255
  br i1 %51, label %52, label %53

52:                                               ; preds = %48
  br label %48, !llvm.loop !17

53:                                               ; preds = %48
  br label %54

54:                                               ; preds = %53
  %55 = load i32, ptr %10, align 4, !tbaa !9
  %56 = add i32 %55, 1
  store i32 %56, ptr %10, align 4, !tbaa !9
  br label %26, !llvm.loop !18

57:                                               ; preds = %26
  call void @sd_delay(i16 noundef zeroext 2)
  call void @SPI_Write(ptr noundef inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 253)
  call void @sd_delay(i16 noundef zeroext 1)
  br label %58

58:                                               ; preds = %62, %57
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = call i32 @is_card_busy(ptr noundef %59)
  %61 = icmp ne i32 %60, 255
  br i1 %61, label %62, label %63

62:                                               ; preds = %58
  br label %58, !llvm.loop !19

63:                                               ; preds = %58
  %64 = load volatile i32, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !14
  %65 = or i32 %64, 8192
  store volatile i32 %65, ptr getelementptr inbounds (%struct._AT91S_PIO, ptr inttoptr (i64 4294964224 to ptr), i32 0, i32 14), align 4, !tbaa !14
  call void @sd_delay(i16 noundef zeroext 4)
  store i32 1, ptr %5, align 4
  store i32 1, ptr %12, align 4
  br label %66

66:                                               ; preds = %63, %24
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  %67 = load i32, ptr %5, align 4
  ret i32 %67
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}
!14 = !{!15, !10, i64 56}
!15 = !{!"_AT91S_PIO", !10, i64 0, !10, i64 4, !10, i64 8, !7, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !7, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !7, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72, !10, i64 76, !10, i64 80, !10, i64 84, !10, i64 88, !7, i64 92, !10, i64 96, !10, i64 100, !10, i64 104, !7, i64 108, !10, i64 112, !10, i64 116, !10, i64 120, !7, i64 124, !10, i64 160, !10, i64 164, !10, i64 168}
!16 = distinct !{!16, !13}
!17 = distinct !{!17, !13}
!18 = distinct !{!18, !13}
!19 = distinct !{!19, !13}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@arguments = external dso_local global [4 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local void @sd_delay(i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @sd_send_command(ptr noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

declare zeroext i8 @SPI_IsFinished(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @sd_packarg(ptr noundef, i32 noundef) local_unnamed_addr #0

declare void @SPI_Write(ptr noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @is_card_busy(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 0, 2) i32 @sd_write_multi_block(ptr noundef %0, i32 noundef %1, ptr nocapture noundef readonly %2, i8 noundef zeroext %3) local_unnamed_addr #0 {
  br label %5

5:                                                ; preds = %5, %4
  %6 = tail call zeroext i8 @SPI_IsFinished(ptr noundef nonnull inttoptr (i64 4294836224 to ptr)) #2
  %.not = icmp eq i8 %6, 0
  br i1 %.not, label %7, label %5, !llvm.loop !5

7:                                                ; preds = %5
  %8 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %9 = and i32 %8, -8193
  store volatile i32 %9, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  tail call void @sd_packarg(ptr noundef nonnull @arguments, i32 noundef %1)
  %10 = tail call i32 @sd_send_command(ptr noundef %0, i8 noundef zeroext 25, i8 noundef zeroext 1)
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %30, label %12

12:                                               ; preds = %7
  tail call void @sd_delay(i16 noundef zeroext 2)
  %.not1418 = icmp eq i8 %3, 0
  br i1 %.not1418, label %._crit_edge23, label %.lr.ph22.preheader

.lr.ph22.preheader:                               ; preds = %12
  %13 = zext i8 %3 to i64
  br label %.lr.ph22

.lr.ph22:                                         ; preds = %.lr.ph22.preheader, %24
  %indvars.iv25 = phi i64 [ 1, %.lr.ph22.preheader ], [ %indvars.iv.next26, %24 ]
  %.020 = phi i32 [ 0, %.lr.ph22.preheader ], [ %.1.lcssa, %24 ]
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 254) #2
  %14 = shl nuw nsw i64 %indvars.iv25, 9
  %15 = zext i32 %.020 to i64
  %16 = icmp ugt i64 %14, %15
  br i1 %16, label %.lr.ph, label %._crit_edge

.lr.ph:                                           ; preds = %.lr.ph22, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ %15, %.lr.ph22 ]
  %17 = getelementptr inbounds i8, ptr %2, i64 %indvars.iv
  %18 = load i8, ptr %17, align 1, !tbaa !12
  %19 = zext i8 %18 to i16
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext %19) #2
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %20 = icmp ult i64 %indvars.iv.next, %14
  br i1 %20, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !13

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %21 = trunc nuw i64 %indvars.iv.next to i32
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %.lr.ph22
  %.1.lcssa = phi i32 [ %.020, %.lr.ph22 ], [ %21, %._crit_edge.loopexit ]
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 149) #2
  tail call void @sd_delay(i16 noundef zeroext 1)
  br label %22

22:                                               ; preds = %22, %._crit_edge
  %23 = tail call i32 @is_card_busy(ptr noundef %0)
  %.not16 = icmp eq i32 %23, 255
  br i1 %.not16, label %24, label %22, !llvm.loop !14

24:                                               ; preds = %22
  %indvars.iv.next26 = add nuw nsw i64 %indvars.iv25, 1
  %exitcond.not = icmp eq i64 %indvars.iv25, %13
  br i1 %exitcond.not, label %._crit_edge23, label %.lr.ph22, !llvm.loop !15

._crit_edge23:                                    ; preds = %24, %12
  tail call void @sd_delay(i16 noundef zeroext 2)
  tail call void @SPI_Write(ptr noundef nonnull inttoptr (i64 4294836224 to ptr), i32 noundef 1, i16 noundef zeroext 253) #2
  tail call void @sd_delay(i16 noundef zeroext 1)
  br label %25

25:                                               ; preds = %25, %._crit_edge23
  %26 = tail call i32 @is_card_busy(ptr noundef %0)
  %.not15 = icmp eq i32 %26, 255
  br i1 %.not15, label %27, label %25, !llvm.loop !16

27:                                               ; preds = %25
  %28 = load volatile i32, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  %29 = or i32 %28, 8192
  store volatile i32 %29, ptr inttoptr (i64 4294964280 to ptr), align 8, !tbaa !7
  tail call void @sd_delay(i16 noundef zeroext 4)
  br label %30

30:                                               ; preds = %7, %27
  %.013 = phi i32 [ 1, %27 ], [ 0, %7 ]
  ret i32 %.013
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !9, i64 56}
!8 = !{!"_AT91S_PIO", !9, i64 0, !9, i64 4, !9, i64 8, !10, i64 12, !9, i64 16, !9, i64 20, !9, i64 24, !10, i64 28, !9, i64 32, !9, i64 36, !9, i64 40, !10, i64 44, !9, i64 48, !9, i64 52, !9, i64 56, !9, i64 60, !9, i64 64, !9, i64 68, !9, i64 72, !9, i64 76, !9, i64 80, !9, i64 84, !9, i64 88, !10, i64 92, !9, i64 96, !9, i64 100, !9, i64 104, !10, i64 108, !9, i64 112, !9, i64 116, !9, i64 120, !10, i64 124, !9, i64 160, !9, i64 164, !9, i64 168}
!9 = !{!"int", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C/C++ TBAA"}
!12 = !{!10, !10, i64 0}
!13 = distinct !{!13, !6}
!14 = distinct !{!14, !6}
!15 = distinct !{!15, !6}
!16 = distinct !{!16, !6}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass