; LLVM IR from IlyaGrebnov/libbsc :: libbsc/platform (platform)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZZ20bsc_get_cpu_featuresE14g_cpu_features = external hidden global i32, align 4

; Function Attrs: mustprogress uwtable
define dso_local i32 @bsc_get_cpu_features() #0 {
  %1 = alloca i32, align 4
  %2 = alloca [4 x i32], align 16
  %3 = alloca i32, align 4
  %4 = load i32, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  %5 = icmp sge i32 %4, 0
  br i1 %5, label %6, label %8

6:                                                ; preds = %0
  %7 = load i32, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 %7, ptr %1, align 4
  br label %118

8:                                                ; preds = %0
  call void @llvm.lifetime.start.p0(i64 16, ptr %2) #4
  call void @llvm.memset.p0.i64(ptr align 16 %2, i8 0, i64 16, i1 false)
  %9 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  call void @_ZL9bsc_cpuidPjj(ptr noundef %9, i32 noundef 0)
  %10 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  %11 = load i32, ptr %10, align 16, !tbaa !5
  %12 = icmp ult i32 %11, 1
  br i1 %12, label %13, label %14

13:                                               ; preds = %8
  store i32 0, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 0, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

14:                                               ; preds = %8
  %15 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  call void @_ZL9bsc_cpuidPjj(ptr noundef %15, i32 noundef 1)
  %16 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 3
  %17 = load i32, ptr %16, align 4, !tbaa !5
  %18 = and i32 %17, 67108864
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %20, label %21

20:                                               ; preds = %14
  store i32 0, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 0, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

21:                                               ; preds = %14
  %22 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %23 = load i32, ptr %22, align 8, !tbaa !5
  %24 = and i32 %23, 1
  %25 = icmp eq i32 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %21
  store i32 2, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 2, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

27:                                               ; preds = %21
  %28 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %29 = load i32, ptr %28, align 8, !tbaa !5
  %30 = and i32 %29, 512
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %33

32:                                               ; preds = %27
  store i32 3, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 3, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

33:                                               ; preds = %27
  %34 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %35 = load i32, ptr %34, align 8, !tbaa !5
  %36 = and i32 %35, 524288
  %37 = icmp eq i32 %36, 0
  br i1 %37, label %38, label %39

38:                                               ; preds = %33
  store i32 4, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 4, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

39:                                               ; preds = %33
  %40 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %41 = load i32, ptr %40, align 8, !tbaa !5
  %42 = and i32 %41, 8388608
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %45

44:                                               ; preds = %39
  store i32 5, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 5, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

45:                                               ; preds = %39
  %46 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %47 = load i32, ptr %46, align 8, !tbaa !5
  %48 = and i32 %47, 1048576
  %49 = icmp eq i32 %48, 0
  br i1 %49, label %50, label %51

50:                                               ; preds = %45
  store i32 5, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 5, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

51:                                               ; preds = %45
  %52 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %53 = load i32, ptr %52, align 8, !tbaa !5
  %54 = and i32 %53, 268435456
  %55 = icmp eq i32 %54, 0
  br i1 %55, label %56, label %57

56:                                               ; preds = %51
  store i32 6, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 6, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

57:                                               ; preds = %51
  %58 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 2
  %59 = load i32, ptr %58, align 8, !tbaa !5
  %60 = and i32 %59, 134217728
  %61 = icmp eq i32 %60, 0
  br i1 %61, label %62, label %63

62:                                               ; preds = %57
  store i32 6, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 6, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

63:                                               ; preds = %57
  %64 = call noundef i64 @_ZL10bsc_xgetbvv()
  %65 = and i64 %64, 6
  %66 = icmp ne i64 %65, 6
  br i1 %66, label %67, label %68

67:                                               ; preds = %63
  store i32 6, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 6, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

68:                                               ; preds = %63
  %69 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  call void @_ZL9bsc_cpuidPjj(ptr noundef %69, i32 noundef 0)
  %70 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  %71 = load i32, ptr %70, align 16, !tbaa !5
  %72 = icmp ult i32 %71, 7
  br i1 %72, label %73, label %74

73:                                               ; preds = %68
  store i32 7, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 7, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

74:                                               ; preds = %68
  %75 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 0
  call void @_ZL9bsc_cpuidPjj(ptr noundef %75, i32 noundef 7)
  %76 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %77 = load i32, ptr %76, align 4, !tbaa !5
  %78 = and i32 %77, 32
  %79 = icmp eq i32 %78, 0
  br i1 %79, label %80, label %81

80:                                               ; preds = %74
  store i32 7, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 7, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

81:                                               ; preds = %74
  %82 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %83 = load i32, ptr %82, align 4, !tbaa !5
  %84 = and i32 %83, 65536
  %85 = icmp eq i32 %84, 0
  br i1 %85, label %86, label %87

86:                                               ; preds = %81
  store i32 8, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 8, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

87:                                               ; preds = %81
  %88 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %89 = load i32, ptr %88, align 4, !tbaa !5
  %90 = and i32 %89, 268435456
  %91 = icmp eq i32 %90, 0
  br i1 %91, label %92, label %93

92:                                               ; preds = %87
  store i32 8, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 8, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

93:                                               ; preds = %87
  %94 = call noundef i64 @_ZL10bsc_xgetbvv()
  %95 = and i64 %94, 224
  %96 = icmp ne i64 %95, 224
  br i1 %96, label %97, label %98

97:                                               ; preds = %93
  store i32 8, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 8, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

98:                                               ; preds = %93
  %99 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %100 = load i32, ptr %99, align 4, !tbaa !5
  %101 = and i32 %100, 131072
  %102 = icmp eq i32 %101, 0
  br i1 %102, label %103, label %104

103:                                              ; preds = %98
  store i32 9, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 9, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

104:                                              ; preds = %98
  %105 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %106 = load i32, ptr %105, align 4, !tbaa !5
  %107 = and i32 %106, -2147483648
  %108 = icmp eq i32 %107, 0
  br i1 %108, label %109, label %110

109:                                              ; preds = %104
  store i32 9, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 9, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

110:                                              ; preds = %104
  %111 = getelementptr inbounds [4 x i32], ptr %2, i64 0, i64 1
  %112 = load i32, ptr %111, align 4, !tbaa !5
  %113 = and i32 %112, 1073741824
  %114 = icmp eq i32 %113, 0
  br i1 %114, label %115, label %116

115:                                              ; preds = %110
  store i32 9, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 9, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

116:                                              ; preds = %110
  store i32 10, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  store i32 10, ptr %1, align 4
  store i32 1, ptr %3, align 4
  br label %117

117:                                              ; preds = %116, %115, %109, %103, %97, %92, %86, %80, %73, %67, %62, %56, %50, %44, %38, %32, %26, %20, %13
  call void @llvm.lifetime.end.p0(i64 16, ptr %2) #4
  br label %118

118:                                              ; preds = %117, %6
  %119 = load i32, ptr %1, align 4
  ret i32 %119
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZL9bsc_cpuidPjj(ptr noundef, i32 noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare hidden noundef i64 @_ZL10bsc_xgetbvv() #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_ZZ20bsc_get_cpu_featuresE14g_cpu_features = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: mustprogress nounwind uwtable
define dso_local range(i32 0, -2147483648) i32 @bsc_get_cpu_features() local_unnamed_addr #0 {
  %1 = alloca [4 x i32], align 16
  %2 = load i32, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  %3 = icmp sgt i32 %2, -1
  br i1 %3, label %50, label %4

4:                                                ; preds = %0
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %1) #3
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(16) %1, i8 0, i64 16, i1 false)
  call void @_ZL9bsc_cpuidPjj(ptr noundef nonnull %1, i32 noundef 0)
  %5 = load i32, ptr %1, align 16, !tbaa !5
  %6 = icmp eq i32 %5, 0
  br i1 %6, label %49, label %7

7:                                                ; preds = %4
  call void @_ZL9bsc_cpuidPjj(ptr noundef nonnull %1, i32 noundef 1)
  %8 = getelementptr inbounds i8, ptr %1, i64 12
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %10 = and i32 %9, 67108864
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %49, label %12

12:                                               ; preds = %7
  %13 = getelementptr inbounds i8, ptr %1, i64 8
  %14 = load i32, ptr %13, align 8, !tbaa !5
  %15 = and i32 %14, 1
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %49, label %17

17:                                               ; preds = %12
  %18 = and i32 %14, 512
  %19 = icmp eq i32 %18, 0
  br i1 %19, label %49, label %20

20:                                               ; preds = %17
  %21 = and i32 %14, 524288
  %22 = icmp eq i32 %21, 0
  br i1 %22, label %49, label %23

23:                                               ; preds = %20
  %24 = and i32 %14, 9437184
  %or.cond.not = icmp eq i32 %24, 9437184
  br i1 %or.cond.not, label %25, label %49

25:                                               ; preds = %23
  %26 = and i32 %14, 402653184
  %or.cond5.not = icmp eq i32 %26, 402653184
  br i1 %or.cond5.not, label %27, label %49

27:                                               ; preds = %25
  %28 = call noundef i64 @_ZL10bsc_xgetbvv()
  %29 = and i64 %28, 6
  %.not = icmp eq i64 %29, 6
  br i1 %.not, label %30, label %49

30:                                               ; preds = %27
  call void @_ZL9bsc_cpuidPjj(ptr noundef nonnull %1, i32 noundef 0)
  %31 = load i32, ptr %1, align 16, !tbaa !5
  %32 = icmp ult i32 %31, 7
  br i1 %32, label %49, label %33

33:                                               ; preds = %30
  call void @_ZL9bsc_cpuidPjj(ptr noundef nonnull %1, i32 noundef 7)
  %34 = getelementptr inbounds i8, ptr %1, i64 4
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = and i32 %35, 32
  %37 = icmp eq i32 %36, 0
  br i1 %37, label %49, label %38

38:                                               ; preds = %33
  %39 = and i32 %35, 268500992
  %or.cond7.not = icmp eq i32 %39, 268500992
  br i1 %or.cond7.not, label %40, label %49

40:                                               ; preds = %38
  %41 = call noundef i64 @_ZL10bsc_xgetbvv()
  %42 = and i64 %41, 224
  %.not2 = icmp eq i64 %42, 224
  br i1 %.not2, label %43, label %49

43:                                               ; preds = %40
  %44 = load i32, ptr %34, align 4, !tbaa !5
  %45 = and i32 %44, -2147352576
  %or.cond8.not = icmp eq i32 %45, -2147352576
  br i1 %or.cond8.not, label %46, label %49

46:                                               ; preds = %43
  %47 = and i32 %44, 1073741824
  %48 = icmp eq i32 %47, 0
  %. = select i1 %48, i32 9, i32 10
  br label %49

49:                                               ; preds = %46, %43, %40, %38, %33, %30, %27, %25, %23, %20, %17, %12, %7, %4
  %.sink = phi i32 [ 0, %4 ], [ 0, %7 ], [ 2, %12 ], [ 3, %17 ], [ 4, %20 ], [ 5, %23 ], [ 6, %25 ], [ 6, %27 ], [ 7, %30 ], [ 7, %33 ], [ 8, %38 ], [ 8, %40 ], [ 9, %43 ], [ %., %46 ]
  store i32 %.sink, ptr @_ZZ20bsc_get_cpu_featuresE14g_cpu_features, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %1) #3
  br label %50

50:                                               ; preds = %0, %49
  %.1 = phi i32 [ %.sink, %49 ], [ %2, %0 ]
  ret i32 %.1
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZL9bsc_cpuidPjj(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare hidden noundef i64 @_ZL10bsc_xgetbvv() local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass