; LLVM IR from dmalyuta/FlyARocket_GNC :: msp430_funcs (MSP430_UART_write_PWM)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@MSP430_UART = external dso_local global i32, align 4
@.str.1 = external hidden unnamed_addr constant [37 x i8], align 1
@PWM_TX_packet = external dso_local global [6 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local void @MSP430_UART_receive() #0

declare void @perror(ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

declare i64 @write(i32 noundef, ptr noundef, i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nounwind uwtable
define dso_local void @MSP430_UART_write_PWM(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !5
  store i8 35, ptr @PWM_TX_packet, align 1, !tbaa !9
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = and i32 %10, 1020
  %12 = lshr i32 %11, 2
  %13 = trunc i32 %12 to i8
  store i8 %13, ptr getelementptr inbounds ([6 x i8], ptr @PWM_TX_packet, i64 0, i64 1), align 1, !tbaa !9
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = and i32 %14, 3
  %16 = shl i32 %15, 6
  %17 = load i32, ptr %6, align 4, !tbaa !5
  %18 = and i32 %17, 1008
  %19 = lshr i32 %18, 4
  %20 = or i32 %16, %19
  %21 = trunc i32 %20 to i8
  store i8 %21, ptr getelementptr inbounds ([6 x i8], ptr @PWM_TX_packet, i64 0, i64 2), align 1, !tbaa !9
  %22 = load i32, ptr %6, align 4, !tbaa !5
  %23 = and i32 %22, 15
  %24 = shl i32 %23, 4
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = and i32 %25, 960
  %27 = lshr i32 %26, 6
  %28 = or i32 %24, %27
  %29 = trunc i32 %28 to i8
  store i8 %29, ptr getelementptr inbounds ([6 x i8], ptr @PWM_TX_packet, i64 0, i64 3), align 1, !tbaa !9
  %30 = load i32, ptr %7, align 4, !tbaa !5
  %31 = and i32 %30, 63
  %32 = shl i32 %31, 2
  %33 = load i32, ptr %8, align 4, !tbaa !5
  %34 = and i32 %33, 768
  %35 = lshr i32 %34, 8
  %36 = or i32 %32, %35
  %37 = trunc i32 %36 to i8
  store i8 %37, ptr getelementptr inbounds ([6 x i8], ptr @PWM_TX_packet, i64 0, i64 4), align 1, !tbaa !9
  %38 = load i32, ptr %8, align 4, !tbaa !5
  %39 = and i32 %38, 255
  %40 = trunc i32 %39 to i8
  store i8 %40, ptr getelementptr inbounds ([6 x i8], ptr @PWM_TX_packet, i64 0, i64 5), align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !5
  br label %41

41:                                               ; preds = %52, %4
  %42 = load i32, ptr @MSP430_UART, align 4, !tbaa !5
  %43 = load i32, ptr %9, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = getelementptr inbounds [6 x i8], ptr @PWM_TX_packet, i64 0, i64 %44
  %46 = call i64 @write(i32 noundef %42, ptr noundef %45, i64 noundef 1)
  %47 = icmp slt i64 %46, 0
  br i1 %47, label %48, label %49

48:                                               ; preds = %41
  call void @perror(ptr noundef @.str.1)
  br label %49

49:                                               ; preds = %48, %41
  call void @MSP430_UART_receive()
  %50 = load i32, ptr %9, align 4, !tbaa !5
  %51 = add nsw i32 %50, 1
  store i32 %51, ptr %9, align 4, !tbaa !5
  br label %52

52:                                               ; preds = %49
  %53 = load i32, ptr %9, align 4, !tbaa !5
  %54 = icmp slt i32 %53, 6
  br i1 %54, label %41, label %55, !llvm.loop !10

55:                                               ; preds = %52
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@MSP430_UART = external dso_local local_unnamed_addr global i32, align 4
@.str.1 = external hidden unnamed_addr constant [37 x i8], align 1
@PWM_TX_packet = external dso_local global [6 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local void @MSP430_UART_receive() local_unnamed_addr #0

; Function Attrs: nofree nounwind
declare void @perror(ptr nocapture noundef readonly) local_unnamed_addr #1

; Function Attrs: nofree
declare noundef i64 @write(i32 noundef, ptr nocapture noundef readonly, i64 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local void @MSP430_UART_write_PWM(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  store i8 35, ptr @PWM_TX_packet, align 1, !tbaa !5
  %5 = lshr i32 %0, 2
  %6 = trunc i32 %5 to i8
  store i8 %6, ptr getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 1), align 1, !tbaa !5
  %7 = shl i32 %0, 6
  %8 = lshr i32 %1, 4
  %9 = and i32 %8, 63
  %10 = or disjoint i32 %9, %7
  %11 = trunc i32 %10 to i8
  store i8 %11, ptr getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 2), align 1, !tbaa !5
  %12 = shl i32 %1, 4
  %13 = lshr i32 %2, 6
  %14 = and i32 %13, 15
  %15 = or disjoint i32 %14, %12
  %16 = trunc i32 %15 to i8
  store i8 %16, ptr getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 3), align 1, !tbaa !5
  %17 = shl i32 %2, 2
  %18 = lshr i32 %3, 8
  %19 = and i32 %18, 3
  %20 = or disjoint i32 %19, %17
  %21 = trunc i32 %20 to i8
  store i8 %21, ptr getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 4), align 1, !tbaa !5
  %22 = trunc i32 %3 to i8
  store i8 %22, ptr getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 5), align 1, !tbaa !5
  %23 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %24 = tail call i64 @write(i32 noundef %23, ptr noundef nonnull @PWM_TX_packet, i64 noundef 1) #3
  %25 = icmp slt i64 %24, 0
  br i1 %25, label %26, label %27

26:                                               ; preds = %4
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %27

27:                                               ; preds = %26, %4
  tail call void @MSP430_UART_receive()
  %28 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %29 = tail call i64 @write(i32 noundef %28, ptr noundef nonnull getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 1), i64 noundef 1) #3
  %30 = icmp slt i64 %29, 0
  br i1 %30, label %31, label %32

31:                                               ; preds = %27
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %32

32:                                               ; preds = %31, %27
  tail call void @MSP430_UART_receive()
  %33 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %34 = tail call i64 @write(i32 noundef %33, ptr noundef nonnull getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 2), i64 noundef 1) #3
  %35 = icmp slt i64 %34, 0
  br i1 %35, label %36, label %37

36:                                               ; preds = %32
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %37

37:                                               ; preds = %36, %32
  tail call void @MSP430_UART_receive()
  %38 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %39 = tail call i64 @write(i32 noundef %38, ptr noundef nonnull getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 3), i64 noundef 1) #3
  %40 = icmp slt i64 %39, 0
  br i1 %40, label %41, label %42

41:                                               ; preds = %37
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %42

42:                                               ; preds = %41, %37
  tail call void @MSP430_UART_receive()
  %43 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %44 = tail call i64 @write(i32 noundef %43, ptr noundef nonnull getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 4), i64 noundef 1) #3
  %45 = icmp slt i64 %44, 0
  br i1 %45, label %46, label %47

46:                                               ; preds = %42
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %47

47:                                               ; preds = %46, %42
  tail call void @MSP430_UART_receive()
  %48 = load i32, ptr @MSP430_UART, align 4, !tbaa !8
  %49 = tail call i64 @write(i32 noundef %48, ptr noundef nonnull getelementptr inbounds (i8, ptr @PWM_TX_packet, i64 5), i64 noundef 1) #3
  %50 = icmp slt i64 %49, 0
  br i1 %50, label %51, label %52

51:                                               ; preds = %47
  tail call void @perror(ptr noundef nonnull @.str.1) #4
  br label %52

52:                                               ; preds = %51, %47
  tail call void @MSP430_UART_receive()
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nofree "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }
attributes #4 = { cold }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass