; LLVM IR from BrunoLevy/learn-fpga :: FemtoRV/FIRMWARE/LIBFEMTORV32 (spi_sd)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@sdhc_card = external hidden global i32, align 4

; Function Attrs: nounwind uwtable
declare dso_local void @spi_send(i8 noundef zeroext) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @spi_receive() #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @sd_send_command(i8 noundef zeroext %0, i32 noundef %1) #0 {
  %3 = alloca i8, align 1
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  store i8 %0, ptr %3, align 1, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  store i8 -1, ptr %5, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #2
  %8 = load i32, ptr @sdhc_card, align 4, !tbaa !8
  %9 = icmp ne i32 %8, 0
  br i1 %9, label %17, label %10

10:                                               ; preds = %2
  %11 = load i8, ptr %3, align 1, !tbaa !5
  %12 = zext i8 %11 to i32
  switch i32 %12, label %16 [
    i32 17, label %13
    i32 24, label %13
    i32 32, label %13
    i32 33, label %13
  ]

13:                                               ; preds = %10, %10, %10, %10
  %14 = load i32, ptr %4, align 4, !tbaa !8
  %15 = mul i32 %14, 512
  store i32 %15, ptr %4, align 4, !tbaa !8
  br label %16

16:                                               ; preds = %13, %10
  br label %17

17:                                               ; preds = %16, %2
  %18 = load i8, ptr %3, align 1, !tbaa !5
  %19 = zext i8 %18 to i32
  %20 = or i32 %19, 64
  %21 = trunc i32 %20 to i8
  call void @spi_send(i8 noundef zeroext %21)
  %22 = load i32, ptr %4, align 4, !tbaa !8
  %23 = lshr i32 %22, 24
  %24 = trunc i32 %23 to i8
  call void @spi_send(i8 noundef zeroext %24)
  %25 = load i32, ptr %4, align 4, !tbaa !8
  %26 = lshr i32 %25, 16
  %27 = trunc i32 %26 to i8
  call void @spi_send(i8 noundef zeroext %27)
  %28 = load i32, ptr %4, align 4, !tbaa !8
  %29 = lshr i32 %28, 8
  %30 = trunc i32 %29 to i8
  call void @spi_send(i8 noundef zeroext %30)
  %31 = load i32, ptr %4, align 4, !tbaa !8
  %32 = lshr i32 %31, 0
  %33 = trunc i32 %32 to i8
  call void @spi_send(i8 noundef zeroext %33)
  %34 = load i8, ptr %3, align 1, !tbaa !5
  %35 = zext i8 %34 to i32
  %36 = icmp eq i32 %35, 8
  %37 = zext i1 %36 to i64
  %38 = select i1 %36, i32 135, i32 149
  %39 = trunc i32 %38 to i8
  call void @spi_send(i8 noundef zeroext %39)
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 0, ptr %7, align 4, !tbaa !8
  br label %40

40:                                               ; preds = %48, %17
  %41 = call zeroext i8 @spi_receive()
  store i8 %41, ptr %5, align 1, !tbaa !5
  %42 = zext i8 %41 to i32
  %43 = icmp eq i32 %42, 255
  br i1 %43, label %44, label %51

44:                                               ; preds = %40
  %45 = load i32, ptr %7, align 4, !tbaa !8
  %46 = icmp sgt i32 %45, 500
  br i1 %46, label %47, label %48

47:                                               ; preds = %44
  br label %51

48:                                               ; preds = %44
  %49 = load i32, ptr %7, align 4, !tbaa !8
  %50 = add nsw i32 %49, 1
  store i32 %50, ptr %7, align 4, !tbaa !8
  br label %40, !llvm.loop !10

51:                                               ; preds = %47, %40
  %52 = load i8, ptr %3, align 1, !tbaa !5
  %53 = zext i8 %52 to i32
  %54 = icmp eq i32 %53, 58
  br i1 %54, label %55, label %71

55:                                               ; preds = %51
  %56 = load i8, ptr %5, align 1, !tbaa !5
  %57 = zext i8 %56 to i32
  %58 = icmp eq i32 %57, 0
  br i1 %58, label %59, label %71

59:                                               ; preds = %55
  %60 = call zeroext i8 @spi_receive()
  store i8 %60, ptr %6, align 1, !tbaa !5
  %61 = load i8, ptr %6, align 1, !tbaa !5
  %62 = zext i8 %61 to i32
  %63 = and i32 %62, 64
  %64 = icmp ne i32 %63, 0
  br i1 %64, label %65, label %66

65:                                               ; preds = %59
  store i32 1, ptr @sdhc_card, align 4, !tbaa !8
  br label %67

66:                                               ; preds = %59
  store i32 0, ptr @sdhc_card, align 4, !tbaa !8
  br label %67

67:                                               ; preds = %66, %65
  %68 = call zeroext i8 @spi_receive()
  %69 = call zeroext i8 @spi_receive()
  %70 = call zeroext i8 @spi_receive()
  br label %71

71:                                               ; preds = %67, %55, %51
  call void @spi_send(i8 noundef zeroext -1)
  %72 = load i8, ptr %5, align 1, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  ret i8 %72
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@sdhc_card = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: nounwind uwtable
declare dso_local void @spi_send(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @spi_receive() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @sd_send_command(i8 noundef zeroext %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = load i32, ptr @sdhc_card, align 4, !tbaa !5
  %.not = icmp eq i32 %3, 0
  br i1 %.not, label %4, label %7

4:                                                ; preds = %2
  switch i8 %0, label %7 [
    i8 17, label %5
    i8 24, label %5
    i8 32, label %5
    i8 33, label %5
  ]

5:                                                ; preds = %4, %4, %4, %4
  %6 = shl i32 %1, 9
  br label %7

7:                                                ; preds = %4, %5, %2
  %.018 = phi i32 [ %1, %2 ], [ %1, %4 ], [ %6, %5 ]
  %8 = or i8 %0, 64
  tail call void @spi_send(i8 noundef zeroext %8)
  %9 = lshr i32 %.018, 24
  %10 = trunc nuw i32 %9 to i8
  tail call void @spi_send(i8 noundef zeroext %10)
  %11 = lshr i32 %.018, 16
  %12 = trunc i32 %11 to i8
  tail call void @spi_send(i8 noundef zeroext %12)
  %13 = lshr i32 %.018, 8
  %14 = trunc i32 %13 to i8
  tail call void @spi_send(i8 noundef zeroext %14)
  %15 = trunc i32 %.018 to i8
  tail call void @spi_send(i8 noundef zeroext %15)
  %16 = icmp eq i8 %0, 8
  %17 = select i1 %16, i8 -121, i8 -107
  tail call void @spi_send(i8 noundef zeroext %17)
  br label %18

18:                                               ; preds = %18, %7
  %.0 = phi i32 [ 0, %7 ], [ %22, %18 ]
  %19 = tail call zeroext i8 @spi_receive()
  %20 = icmp ne i8 %19, -1
  %21 = icmp ugt i32 %.0, 500
  %or.cond4 = select i1 %20, i1 true, i1 %21
  %22 = add nuw nsw i32 %.0, 1
  br i1 %or.cond4, label %23, label %18, !llvm.loop !9

23:                                               ; preds = %18
  %24 = icmp eq i8 %0, 58
  %25 = icmp eq i8 %19, 0
  %or.cond = and i1 %24, %25
  br i1 %or.cond, label %26, label %32

26:                                               ; preds = %23
  %27 = tail call zeroext i8 @spi_receive()
  %28 = lshr i8 %27, 6
  %.lobit = and i8 %28, 1
  %. = zext nneg i8 %.lobit to i32
  store i32 %., ptr @sdhc_card, align 4, !tbaa !5
  %29 = tail call zeroext i8 @spi_receive()
  %30 = tail call zeroext i8 @spi_receive()
  %31 = tail call zeroext i8 @spi_receive()
  br label %32

32:                                               ; preds = %26, %23
  tail call void @spi_send(i8 noundef zeroext -1)
  ret i8 %19
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LoopRotatePass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass