; LLVM IR from ucb-bar/RoSE :: soc/sw/baremetal (spiflashread)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%union.spi_fmt = type { %struct.anon.0 }
%struct.anon.0 = type { i32 }

; Function Attrs: nounwind uwtable
declare dso_local void @spi_data_write(i8 noundef zeroext) #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @reg_write32(i64 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @write_spiflash(ptr noundef %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6) #0 {
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i8, align 1
  %12 = alloca i8, align 1
  %13 = alloca i8, align 1
  %14 = alloca i8, align 1
  %15 = alloca %union.spi_fmt, align 4
  %16 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store i32 %1, ptr %9, align 4, !tbaa !9
  store i32 %2, ptr %10, align 4, !tbaa !9
  store i8 %3, ptr %11, align 1, !tbaa !11
  store i8 %4, ptr %12, align 1, !tbaa !11
  store i8 %5, ptr %13, align 1, !tbaa !11
  store i8 %6, ptr %14, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %17 = load i32, ptr %15, align 4
  %18 = and i32 %17, -4
  %19 = or i32 %18, 0
  store i32 %19, ptr %15, align 4
  %20 = load i32, ptr %15, align 4
  %21 = and i32 %20, -5
  %22 = or i32 %21, 0
  store i32 %22, ptr %15, align 4
  %23 = load i32, ptr %15, align 4
  %24 = and i32 %23, -9
  %25 = or i32 %24, 8
  store i32 %25, ptr %15, align 4
  %26 = load i32, ptr %15, align 4
  %27 = and i32 %26, -983041
  %28 = or i32 %27, 524288
  store i32 %28, ptr %15, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #3
  call void @reg_write32(i64 noundef 268697696, i32 noundef 0)
  %29 = load i32, ptr %15, align 4, !tbaa !11
  call void @reg_write32(i64 noundef 268697664, i32 noundef %29)
  call void @reg_write32(i64 noundef 268697624, i32 noundef 2)
  %30 = load i8, ptr %11, align 1, !tbaa !11
  call void @spi_data_write(i8 noundef zeroext %30)
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %31

31:                                               ; preds = %35, %7
  %32 = load i32, ptr %16, align 4, !tbaa !9
  %33 = icmp ult i32 %32, 256
  br i1 %33, label %34, label %38

34:                                               ; preds = %31
  call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !12
  br label %35

35:                                               ; preds = %34
  %36 = load i32, ptr %16, align 4, !tbaa !9
  %37 = add i32 %36, 1
  store i32 %37, ptr %16, align 4, !tbaa !9
  br label %31, !llvm.loop !13

38:                                               ; preds = %31
  %39 = load i8, ptr %13, align 1, !tbaa !11
  %40 = zext i8 %39 to i32
  %41 = load i32, ptr %15, align 4
  %42 = and i32 %40, 3
  %43 = and i32 %41, -4
  %44 = or i32 %43, %42
  store i32 %44, ptr %15, align 4
  %45 = load i32, ptr %15, align 4, !tbaa !11
  call void @reg_write32(i64 noundef 268697664, i32 noundef %45)
  %46 = load i8, ptr %12, align 1, !tbaa !11
  %47 = zext i8 %46 to i32
  store i32 %47, ptr %16, align 4, !tbaa !9
  br label %48

48:                                               ; preds = %58, %38
  %49 = load i32, ptr %16, align 4, !tbaa !9
  %50 = icmp ugt i32 %49, 0
  br i1 %50, label %51, label %61

51:                                               ; preds = %48
  %52 = load i32, ptr %10, align 4, !tbaa !9
  %53 = load i32, ptr %16, align 4, !tbaa !9
  %54 = mul i32 %53, 8
  %55 = sub i32 %54, 8
  %56 = lshr i32 %52, %55
  %57 = trunc i32 %56 to i8
  call void @spi_data_write(i8 noundef zeroext %57)
  br label %58

58:                                               ; preds = %51
  %59 = load i32, ptr %16, align 4, !tbaa !9
  %60 = add i32 %59, -1
  store i32 %60, ptr %16, align 4, !tbaa !9
  br label %48, !llvm.loop !15

61:                                               ; preds = %48
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %62

62:                                               ; preds = %66, %61
  %63 = load i32, ptr %16, align 4, !tbaa !9
  %64 = icmp ult i32 %63, 256
  br i1 %64, label %65, label %69

65:                                               ; preds = %62
  call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !16
  br label %66

66:                                               ; preds = %65
  %67 = load i32, ptr %16, align 4, !tbaa !9
  %68 = add i32 %67, 1
  store i32 %68, ptr %16, align 4, !tbaa !9
  br label %62, !llvm.loop !17

69:                                               ; preds = %62
  %70 = load i8, ptr %14, align 1, !tbaa !11
  %71 = zext i8 %70 to i32
  %72 = load i32, ptr %15, align 4
  %73 = and i32 %71, 3
  %74 = and i32 %72, -4
  %75 = or i32 %74, %73
  store i32 %75, ptr %15, align 4
  %76 = load i32, ptr %15, align 4, !tbaa !11
  call void @reg_write32(i64 noundef 268697664, i32 noundef %76)
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %77

77:                                               ; preds = %87, %69
  %78 = load i32, ptr %16, align 4, !tbaa !9
  %79 = load i32, ptr %9, align 4, !tbaa !9
  %80 = icmp ult i32 %78, %79
  br i1 %80, label %81, label %90

81:                                               ; preds = %77
  %82 = load ptr, ptr %8, align 8, !tbaa !5
  %83 = load i32, ptr %16, align 4, !tbaa !9
  %84 = zext i32 %83 to i64
  %85 = getelementptr inbounds i8, ptr %82, i64 %84
  %86 = load i8, ptr %85, align 1, !tbaa !11
  call void @spi_data_write(i8 noundef zeroext %86)
  br label %87

87:                                               ; preds = %81
  %88 = load i32, ptr %16, align 4, !tbaa !9
  %89 = add i32 %88, 1
  store i32 %89, ptr %16, align 4, !tbaa !9
  br label %77, !llvm.loop !18

90:                                               ; preds = %77
  store i32 0, ptr %16, align 4, !tbaa !9
  br label %91

91:                                               ; preds = %95, %90
  %92 = load i32, ptr %16, align 4, !tbaa !9
  %93 = icmp ult i32 %92, 256
  br i1 %93, label %94, label %98

94:                                               ; preds = %91
  call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #3, !srcloc !19
  br label %95

95:                                               ; preds = %94
  %96 = load i32, ptr %16, align 4, !tbaa !9
  %97 = add i32 %96, 1
  store i32 %97, ptr %16, align 4, !tbaa !9
  br label %91, !llvm.loop !20

98:                                               ; preds = %91
  call void @reg_write32(i64 noundef 268697624, i32 noundef 3)
  call void @reg_write32(i64 noundef 268697696, i32 noundef 1)
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{i64 343968}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = !{i64 344260}
!17 = distinct !{!17, !14}
!18 = distinct !{!18, !14}
!19 = !{i64 344532}
!20 = distinct !{!20, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @spi_data_write(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @reg_write32(i64 noundef, i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local void @write_spiflash(ptr nocapture noundef readonly %0, i32 noundef %1, i32 noundef %2, i8 noundef zeroext %3, i8 noundef zeroext %4, i8 noundef zeroext %5, i8 noundef zeroext %6) local_unnamed_addr #0 {
  tail call void @reg_write32(i64 noundef 268697696, i32 noundef 0)
  tail call void @reg_write32(i64 noundef 268697664, i32 noundef 524296)
  tail call void @reg_write32(i64 noundef 268697624, i32 noundef 2)
  tail call void @spi_data_write(i8 noundef zeroext %3)
  br label %8

8:                                                ; preds = %7, %8
  %.027 = phi i32 [ 0, %7 ], [ %9, %8 ]
  tail call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !5
  %9 = add nuw nsw i32 %.027, 1
  %exitcond.not = icmp eq i32 %9, 256
  br i1 %exitcond.not, label %10, label %8, !llvm.loop !6

10:                                               ; preds = %8
  %11 = and i8 %5, 3
  %12 = zext nneg i8 %11 to i32
  %13 = or disjoint i32 %12, 524296
  tail call void @reg_write32(i64 noundef 268697664, i32 noundef %13)
  %.not28 = icmp eq i8 %4, 0
  br i1 %.not28, label %.preheader26.preheader, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %10
  %14 = zext i8 %4 to i32
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %.129 = phi i32 [ %19, %.lr.ph ], [ %14, %.lr.ph.preheader ]
  %15 = shl nuw nsw i32 %.129, 3
  %16 = add nsw i32 %15, -8
  %17 = lshr i32 %2, %16
  %18 = trunc i32 %17 to i8
  tail call void @spi_data_write(i8 noundef zeroext %18)
  %19 = add nsw i32 %.129, -1
  %.not = icmp eq i32 %19, 0
  br i1 %.not, label %.preheader26.preheader, label %.lr.ph, !llvm.loop !8

.preheader26.preheader:                           ; preds = %.lr.ph, %10
  br label %.preheader26

.preheader26:                                     ; preds = %.preheader26.preheader, %.preheader26
  %.230 = phi i32 [ %20, %.preheader26 ], [ 0, %.preheader26.preheader ]
  tail call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !9
  %20 = add nuw nsw i32 %.230, 1
  %exitcond35.not = icmp eq i32 %20, 256
  br i1 %exitcond35.not, label %21, label %.preheader26, !llvm.loop !10

21:                                               ; preds = %.preheader26
  %22 = and i8 %6, 3
  %23 = zext nneg i8 %22 to i32
  %24 = or disjoint i32 %23, 524296
  tail call void @reg_write32(i64 noundef 268697664, i32 noundef %24)
  %.not34 = icmp eq i32 %1, 0
  br i1 %.not34, label %.preheader.preheader, label %.lr.ph32.preheader

.lr.ph32.preheader:                               ; preds = %21
  %wide.trip.count = zext i32 %1 to i64
  br label %.lr.ph32

.lr.ph32:                                         ; preds = %.lr.ph32.preheader, %.lr.ph32
  %indvars.iv = phi i64 [ 0, %.lr.ph32.preheader ], [ %indvars.iv.next, %.lr.ph32 ]
  %25 = getelementptr inbounds i8, ptr %0, i64 %indvars.iv
  %26 = load i8, ptr %25, align 1, !tbaa !11
  tail call void @spi_data_write(i8 noundef zeroext %26)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond37.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond37.not, label %.preheader.preheader, label %.lr.ph32, !llvm.loop !14

.preheader.preheader:                             ; preds = %.lr.ph32, %21
  br label %.preheader

.preheader:                                       ; preds = %.preheader.preheader, %.preheader
  %.433 = phi i32 [ %27, %.preheader ], [ 0, %.preheader.preheader ]
  tail call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !15
  %27 = add nuw nsw i32 %.433, 1
  %exitcond38.not = icmp eq i32 %27, 256
  br i1 %exitcond38.not, label %28, label %.preheader, !llvm.loop !16

28:                                               ; preds = %.preheader
  tail call void @reg_write32(i64 noundef 268697624, i32 noundef 3)
  tail call void @reg_write32(i64 noundef 268697696, i32 noundef 1)
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 343968}
!6 = distinct !{!6, !7}
!7 = !{!"llvm.loop.mustprogress"}
!8 = distinct !{!8, !7}
!9 = !{i64 344260}
!10 = distinct !{!10, !7}
!11 = !{!12, !12, i64 0}
!12 = !{!"omnipotent char", !13, i64 0}
!13 = !{!"Simple C/C++ TBAA"}
!14 = distinct !{!14, !7}
!15 = !{i64 344532}
!16 = distinct !{!16, !7}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass