; LLVM IR from intel/qpl :: sources/core-sw/src/filtering (qplc_extract)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @px_qplc_move_8u(ptr noundef, ptr noundef, i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @px_qplc_extract_8u(ptr noundef %0, ptr noundef %1, i32 noundef %2, ptr noundef %3, i32 noundef %4, i32 noundef %5) #2 {
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca ptr, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store ptr %1, ptr %9, align 8, !tbaa !5
  store i32 %2, ptr %10, align 4, !tbaa !9
  store ptr %3, ptr %11, align 8, !tbaa !5
  store i32 %4, ptr %12, align 4, !tbaa !9
  store i32 %5, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  store i32 0, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  store i32 0, ptr %15, align 4, !tbaa !9
  %17 = load ptr, ptr %11, align 8, !tbaa !5
  %18 = load i32, ptr %17, align 4, !tbaa !9
  %19 = load i32, ptr %10, align 4, !tbaa !9
  %20 = add i32 %18, %19
  %21 = load i32, ptr %12, align 4, !tbaa !9
  %22 = icmp ult i32 %20, %21
  br i1 %22, label %23, label %28

23:                                               ; preds = %6
  %24 = load i32, ptr %10, align 4, !tbaa !9
  %25 = load ptr, ptr %11, align 8, !tbaa !5
  %26 = load i32, ptr %25, align 4, !tbaa !9
  %27 = add i32 %26, %24
  store i32 %27, ptr %25, align 4, !tbaa !9
  store i32 0, ptr %7, align 4
  store i32 1, ptr %16, align 4
  br label %79

28:                                               ; preds = %6
  %29 = load ptr, ptr %11, align 8, !tbaa !5
  %30 = load i32, ptr %29, align 4, !tbaa !9
  %31 = load i32, ptr %13, align 4, !tbaa !9
  %32 = icmp ugt i32 %30, %31
  br i1 %32, label %33, label %34

33:                                               ; preds = %28
  store i32 0, ptr %7, align 4
  store i32 1, ptr %16, align 4
  br label %79

34:                                               ; preds = %28
  %35 = load ptr, ptr %11, align 8, !tbaa !5
  %36 = load i32, ptr %35, align 4, !tbaa !9
  %37 = load i32, ptr %12, align 4, !tbaa !9
  %38 = icmp ult i32 %36, %37
  br i1 %38, label %39, label %44

39:                                               ; preds = %34
  %40 = load i32, ptr %12, align 4, !tbaa !9
  %41 = load ptr, ptr %11, align 8, !tbaa !5
  %42 = load i32, ptr %41, align 4, !tbaa !9
  %43 = sub i32 %40, %42
  br label %45

44:                                               ; preds = %34
  br label %45

45:                                               ; preds = %44, %39
  %46 = phi i32 [ %43, %39 ], [ 0, %44 ]
  store i32 %46, ptr %14, align 4, !tbaa !9
  %47 = load ptr, ptr %11, align 8, !tbaa !5
  %48 = load i32, ptr %47, align 4, !tbaa !9
  %49 = load i32, ptr %10, align 4, !tbaa !9
  %50 = add i32 %48, %49
  %51 = load i32, ptr %13, align 4, !tbaa !9
  %52 = icmp ugt i32 %50, %51
  br i1 %52, label %53, label %59

53:                                               ; preds = %45
  %54 = load i32, ptr %13, align 4, !tbaa !9
  %55 = add i32 %54, 1
  %56 = load ptr, ptr %11, align 8, !tbaa !5
  %57 = load i32, ptr %56, align 4, !tbaa !9
  %58 = sub i32 %55, %57
  br label %61

59:                                               ; preds = %45
  %60 = load i32, ptr %10, align 4, !tbaa !9
  br label %61

61:                                               ; preds = %59, %53
  %62 = phi i32 [ %58, %53 ], [ %60, %59 ]
  store i32 %62, ptr %15, align 4, !tbaa !9
  %63 = load i32, ptr %14, align 4, !tbaa !9
  %64 = load ptr, ptr %8, align 8, !tbaa !5
  %65 = zext i32 %63 to i64
  %66 = getelementptr inbounds i8, ptr %64, i64 %65
  store ptr %66, ptr %8, align 8, !tbaa !5
  %67 = load ptr, ptr %8, align 8, !tbaa !5
  %68 = load ptr, ptr %9, align 8, !tbaa !5
  %69 = load i32, ptr %15, align 4, !tbaa !9
  %70 = load i32, ptr %14, align 4, !tbaa !9
  %71 = sub i32 %69, %70
  call void @px_qplc_move_8u(ptr noundef %67, ptr noundef %68, i32 noundef %71)
  %72 = load i32, ptr %10, align 4, !tbaa !9
  %73 = load ptr, ptr %11, align 8, !tbaa !5
  %74 = load i32, ptr %73, align 4, !tbaa !9
  %75 = add i32 %74, %72
  store i32 %75, ptr %73, align 4, !tbaa !9
  %76 = load i32, ptr %15, align 4, !tbaa !9
  %77 = load i32, ptr %14, align 4, !tbaa !9
  %78 = sub i32 %76, %77
  store i32 %78, ptr %7, align 4
  store i32 1, ptr %16, align 4
  br label %79

79:                                               ; preds = %61, %33, %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  %80 = load i32, ptr %7, align 4
  ret i32 %80
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare void @px_qplc_move_8u(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef i32 @px_qplc_extract_8u(ptr noundef %0, ptr noundef %1, i32 noundef %2, ptr nocapture noundef %3, i32 noundef %4, i32 noundef %5) local_unnamed_addr #1 {
  %7 = load i32, ptr %3, align 4, !tbaa !5
  %8 = add i32 %7, %2
  %9 = icmp ult i32 %8, %4
  br i1 %9, label %.sink.split, label %10

10:                                               ; preds = %6
  %11 = icmp ugt i32 %7, %5
  br i1 %11, label %22, label %12

12:                                               ; preds = %10
  %spec.select = tail call i32 @llvm.usub.sat.i32(i32 %4, i32 %7)
  %13 = icmp ugt i32 %8, %5
  %14 = add i32 %5, 1
  %15 = sub i32 %14, %7
  %16 = select i1 %13, i32 %15, i32 %2
  %17 = zext i32 %spec.select to i64
  %18 = getelementptr inbounds i8, ptr %0, i64 %17
  %19 = sub i32 %16, %spec.select
  tail call void @px_qplc_move_8u(ptr noundef %18, ptr noundef %1, i32 noundef %19) #3
  %20 = load i32, ptr %3, align 4, !tbaa !5
  %21 = add i32 %20, %2
  br label %.sink.split

.sink.split:                                      ; preds = %6, %12
  %.sink = phi i32 [ %21, %12 ], [ %8, %6 ]
  %.0.ph = phi i32 [ %19, %12 ], [ 0, %6 ]
  store i32 %.sink, ptr %3, align 4, !tbaa !5
  br label %22

22:                                               ; preds = %.sink.split, %10
  %.0 = phi i32 [ 0, %10 ], [ %.0.ph, %.sink.split ]
  ret i32 %.0
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.usub.sat.i32(i32, i32) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass