; LLVM IR from intel/qpl :: tools/utils/generators/configurators (common_methods)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i8 @_ZN12gz_generator13CommonMethods6bsr_32Ej(i32 noundef %0) #0 align 2 {
  %2 = alloca i32, align 4
  %3 = alloca i8, align 1
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #2
  store i8 0, ptr %3, align 1, !tbaa !9
  %4 = load i32, ptr %2, align 4, !tbaa !5
  %5 = icmp uge i32 %4, 65536
  br i1 %5, label %6, label %9

6:                                                ; preds = %1
  %7 = load i32, ptr %2, align 4, !tbaa !5
  %8 = lshr i32 %7, 16
  store i32 %8, ptr %2, align 4, !tbaa !5
  store i8 16, ptr %3, align 1, !tbaa !9
  br label %9

9:                                                ; preds = %6, %1
  %10 = load i32, ptr %2, align 4, !tbaa !5
  %11 = icmp uge i32 %10, 256
  br i1 %11, label %12, label %19

12:                                               ; preds = %9
  %13 = load i32, ptr %2, align 4, !tbaa !5
  %14 = lshr i32 %13, 8
  store i32 %14, ptr %2, align 4, !tbaa !5
  %15 = load i8, ptr %3, align 1, !tbaa !9
  %16 = zext i8 %15 to i32
  %17 = add nsw i32 %16, 8
  %18 = trunc i32 %17 to i8
  store i8 %18, ptr %3, align 1, !tbaa !9
  br label %19

19:                                               ; preds = %12, %9
  %20 = load i32, ptr %2, align 4, !tbaa !5
  %21 = icmp uge i32 %20, 16
  br i1 %21, label %22, label %29

22:                                               ; preds = %19
  %23 = load i32, ptr %2, align 4, !tbaa !5
  %24 = lshr i32 %23, 4
  store i32 %24, ptr %2, align 4, !tbaa !5
  %25 = load i8, ptr %3, align 1, !tbaa !9
  %26 = zext i8 %25 to i32
  %27 = add nsw i32 %26, 4
  %28 = trunc i32 %27 to i8
  store i8 %28, ptr %3, align 1, !tbaa !9
  br label %29

29:                                               ; preds = %22, %19
  %30 = load i32, ptr %2, align 4, !tbaa !5
  %31 = icmp uge i32 %30, 4
  br i1 %31, label %32, label %39

32:                                               ; preds = %29
  %33 = load i32, ptr %2, align 4, !tbaa !5
  %34 = lshr i32 %33, 2
  store i32 %34, ptr %2, align 4, !tbaa !5
  %35 = load i8, ptr %3, align 1, !tbaa !9
  %36 = zext i8 %35 to i32
  %37 = add nsw i32 %36, 2
  %38 = trunc i32 %37 to i8
  store i8 %38, ptr %3, align 1, !tbaa !9
  br label %39

39:                                               ; preds = %32, %29
  %40 = load i32, ptr %2, align 4, !tbaa !5
  %41 = icmp uge i32 %40, 2
  br i1 %41, label %42, label %49

42:                                               ; preds = %39
  %43 = load i32, ptr %2, align 4, !tbaa !5
  %44 = lshr i32 %43, 1
  store i32 %44, ptr %2, align 4, !tbaa !5
  %45 = load i8, ptr %3, align 1, !tbaa !9
  %46 = zext i8 %45 to i32
  %47 = add nsw i32 %46, 1
  %48 = trunc i32 %47 to i8
  store i8 %48, ptr %3, align 1, !tbaa !9
  br label %49

49:                                               ; preds = %42, %39
  %50 = load i8, ptr %3, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #2
  ret i8 %50
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef zeroext i8 @_ZN12gz_generator13CommonMethods6bsr_32Ej(i32 noundef %0) local_unnamed_addr #0 align 2 {
  %2 = icmp ugt i32 %0, 65535
  %3 = lshr i32 %0, 16
  %spec.select = select i1 %2, i32 %3, i32 %0
  %spec.select21 = select i1 %2, i8 16, i8 0
  %4 = icmp ugt i32 %spec.select, 255
  %5 = lshr i32 %spec.select, 8
  %6 = or disjoint i8 %spec.select21, 8
  %.116 = select i1 %4, i32 %5, i32 %spec.select
  %.1 = select i1 %4, i8 %6, i8 %spec.select21
  %7 = icmp ugt i32 %.116, 15
  %8 = lshr i32 %.116, 4
  %9 = or disjoint i8 %.1, 4
  %.217 = select i1 %7, i32 %8, i32 %.116
  %.2 = select i1 %7, i8 %9, i8 %.1
  %10 = icmp ugt i32 %.217, 3
  %11 = lshr i32 %.217, 2
  %12 = or disjoint i8 %.2, 2
  %.318 = select i1 %10, i32 %11, i32 %.217
  %.3 = select i1 %10, i8 %12, i8 %.2
  %13 = icmp ugt i32 %.318, 1
  %14 = zext i1 %13 to i8
  %.4 = add nuw nsw i8 %.3, %14
  ret i8 %.4
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass