; LLVM IR from ARMmbed/mbed-crypto :: library (aesni)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mbedtls_aesni_has_support.done = external hidden global i32, align 4
@mbedtls_aesni_has_support.c = external hidden global i32, align 4

; Function Attrs: nounwind uwtable
define dso_local i32 @mbedtls_aesni_has_support(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  %3 = load i32, ptr @mbedtls_aesni_has_support.done, align 4, !tbaa !5
  %4 = icmp ne i32 %3, 0
  br i1 %4, label %7, label %5

5:                                                ; preds = %1
  %6 = call i32 asm "movl  $$1, %eax   \0A\09cpuid             \0A\09", "={cx},~{eax},~{ebx},~{edx},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  store i32 %6, ptr @mbedtls_aesni_has_support.c, align 4, !tbaa !5
  store i32 1, ptr @mbedtls_aesni_has_support.done, align 4, !tbaa !5
  br label %7

7:                                                ; preds = %5, %1
  %8 = load i32, ptr @mbedtls_aesni_has_support.c, align 4, !tbaa !5
  %9 = load i32, ptr %2, align 4, !tbaa !5
  %10 = and i32 %8, %9
  %11 = icmp ne i32 %10, 0
  %12 = zext i1 %11 to i32
  ret i32 %12
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 1689, i64 1710, i64 1748}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@mbedtls_aesni_has_support.done = external hidden local_unnamed_addr global i32, align 4
@mbedtls_aesni_has_support.c = external hidden local_unnamed_addr global i32, align 4

; Function Attrs: nounwind memory(readwrite, argmem: none, inaccessiblemem: none) uwtable
define dso_local range(i32 0, 2) i32 @mbedtls_aesni_has_support(i32 noundef %0) local_unnamed_addr #0 {
  %2 = load i32, ptr @mbedtls_aesni_has_support.done, align 4, !tbaa !5
  %.not = icmp eq i32 %2, 0
  br i1 %.not, label %3, label %._crit_edge

._crit_edge:                                      ; preds = %1
  %.pre = load i32, ptr @mbedtls_aesni_has_support.c, align 4, !tbaa !5
  br label %5

3:                                                ; preds = %1
  %4 = tail call i32 asm "movl  $$1, %eax   \0A\09cpuid             \0A\09", "={cx},~{eax},~{ebx},~{edx},~{dirflag},~{fpsr},~{flags}"() #1, !srcloc !9
  store i32 %4, ptr @mbedtls_aesni_has_support.c, align 4, !tbaa !5
  store i32 1, ptr @mbedtls_aesni_has_support.done, align 4, !tbaa !5
  br label %5

5:                                                ; preds = %._crit_edge, %3
  %6 = phi i32 [ %.pre, %._crit_edge ], [ %4, %3 ]
  %7 = and i32 %6, %0
  %8 = icmp ne i32 %7, 0
  %9 = zext i1 %8 to i32
  ret i32 %9
}

attributes #0 = { nounwind memory(readwrite, argmem: none, inaccessiblemem: none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{i64 1689, i64 1710, i64 1748}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,TailCallElimPass