; LLVM IR from fast-pack/SIMDCompressionAndIntersection :: src/integratedbitpacking.ll/ZN18SIMDCompressionLib21 (integratedfastpack1EjPKjPj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_ZN18SIMDCompressionLib21__integratedfastpack1EjPKjPj(i32 noundef %0, ptr noalias noundef %1, ptr noalias noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  store ptr %2, ptr %6, align 8, !tbaa !9
  %8 = load ptr, ptr %5, align 8, !tbaa !9
  %9 = getelementptr inbounds i32, ptr %8, i32 1
  store ptr %9, ptr %5, align 8, !tbaa !9
  %10 = load i32, ptr %8, align 4, !tbaa !5
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = sub i32 %10, %11
  %13 = load ptr, ptr %6, align 8, !tbaa !9
  store i32 %12, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  store i32 1, ptr %7, align 4, !tbaa !5
  br label %14

14:                                               ; preds = %32, %3
  %15 = load i32, ptr %7, align 4, !tbaa !5
  %16 = icmp ult i32 %15, 32
  br i1 %16, label %18, label %17

17:                                               ; preds = %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  br label %35

18:                                               ; preds = %14
  %19 = load ptr, ptr %5, align 8, !tbaa !9
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = load ptr, ptr %5, align 8, !tbaa !9
  %22 = getelementptr inbounds i32, ptr %21, i64 -1
  %23 = load i32, ptr %22, align 4, !tbaa !5
  %24 = sub i32 %20, %23
  %25 = load i32, ptr %7, align 4, !tbaa !5
  %26 = shl i32 %24, %25
  %27 = load ptr, ptr %6, align 8, !tbaa !9
  %28 = load i32, ptr %27, align 4, !tbaa !5
  %29 = or i32 %28, %26
  store i32 %29, ptr %27, align 4, !tbaa !5
  %30 = load ptr, ptr %5, align 8, !tbaa !9
  %31 = getelementptr inbounds i32, ptr %30, i32 1
  store ptr %31, ptr %5, align 8, !tbaa !9
  br label %32

32:                                               ; preds = %18
  %33 = load i32, ptr %7, align 4, !tbaa !5
  %34 = add i32 %33, 1
  store i32 %34, ptr %7, align 4, !tbaa !5
  br label %14, !llvm.loop !11

35:                                               ; preds = %17
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
define dso_local void @_ZN18SIMDCompressionLib21__integratedfastpack1EjPKjPj(i32 noundef %0, ptr noalias nocapture noundef readonly %1, ptr noalias nocapture noundef writeonly %2) local_unnamed_addr #0 {
  %4 = load i32, ptr %1, align 4, !tbaa !5
  %5 = sub i32 %4, %0
  %.09 = getelementptr inbounds i8, ptr %1, i64 4
  %6 = load <16 x i32>, ptr %.09, align 4, !tbaa !5
  %7 = insertelement <16 x i32> poison, i32 %4, i64 0
  %8 = shufflevector <16 x i32> %7, <16 x i32> %6, <16 x i32> <i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
  %9 = sub <16 x i32> %6, %8
  %10 = shl <16 x i32> %9, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
  %.09.16 = getelementptr inbounds i8, ptr %1, i64 68
  %11 = load i32, ptr %.09.16, align 4, !tbaa !5
  %12 = extractelement <16 x i32> %6, i64 15
  %13 = sub i32 %11, %12
  %14 = shl i32 %13, 17
  %.09.17 = getelementptr inbounds i8, ptr %1, i64 72
  %15 = load <8 x i32>, ptr %.09.17, align 4, !tbaa !5
  %16 = insertelement <8 x i32> poison, i32 %11, i64 0
  %17 = shufflevector <8 x i32> %16, <8 x i32> %15, <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
  %18 = sub <8 x i32> %15, %17
  %19 = shl <8 x i32> %18, <i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25>
  %.09.25 = getelementptr inbounds i8, ptr %1, i64 104
  %20 = extractelement <8 x i32> %15, i64 7
  %21 = load <2 x i32>, ptr %.09.25, align 4, !tbaa !5
  %22 = extractelement <2 x i32> %21, i64 0
  %23 = sub i32 %22, %20
  %24 = shl i32 %23, 26
  %shift = shufflevector <2 x i32> %21, <2 x i32> poison, <2 x i32> <i32 1, i32 poison>
  %25 = sub <2 x i32> %shift, %21
  %26 = extractelement <2 x i32> %25, i64 0
  %27 = shl i32 %26, 27
  %.09.27 = getelementptr inbounds i8, ptr %1, i64 112
  %28 = load <4 x i32>, ptr %.09.27, align 4, !tbaa !5
  %29 = shufflevector <2 x i32> %21, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
  %30 = shufflevector <4 x i32> %29, <4 x i32> %28, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
  %31 = sub <4 x i32> %28, %30
  %32 = shl <4 x i32> %31, <i32 28, i32 29, i32 30, i32 31>
  %33 = tail call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %10)
  %34 = tail call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %19)
  %op.rdx = or i32 %33, %34
  %35 = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %32)
  %op.rdx12 = or i32 %op.rdx, %35
  %op.rdx13 = or i32 %op.rdx12, %14
  %op.rdx14 = or i32 %24, %27
  %op.rdx15 = or i32 %op.rdx13, %op.rdx14
  %op.rdx16 = or i32 %op.rdx15, %5
  store i32 %op.rdx16, ptr %2, align 4, !tbaa !5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: DSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopRotatePass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass,VectorCombinePass