; LLVM IR from devantler/software-engineering-f22-shared :: IOT/BudgetManagementExcercise-03-28/ESP-Project/components/components (main)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_Cnt = external dso_local global i32, align 4
@.str = external hidden unnamed_addr constant [35 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [88 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [97 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [50 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [50 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [48 x i8], align 1
@.str.6 = external hidden unnamed_addr constant [45 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: nounwind uwtable
define dso_local void @main() #0 {
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %1) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #3
  br label %3

3:                                                ; preds = %49, %0
  store volatile i32 0, ptr @_Cnt, align 4, !tbaa !5
  %4 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str)
  %5 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.1)
  %6 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.2)
  br label %7

7:                                                ; preds = %15, %3
  %8 = call i32 @SEGGER_RTT_WaitKey()
  store i32 %8, ptr %1, align 4, !tbaa !5
  br label %9

9:                                                ; preds = %7
  %10 = load i32, ptr %1, align 4, !tbaa !5
  %11 = icmp ne i32 %10, 49
  br i1 %11, label %12, label %15

12:                                               ; preds = %9
  %13 = load i32, ptr %1, align 4, !tbaa !5
  %14 = icmp ne i32 %13, 50
  br label %15

15:                                               ; preds = %12, %9
  %16 = phi i1 [ false, %9 ], [ %14, %12 ]
  br i1 %16, label %7, label %17, !llvm.loop !9

17:                                               ; preds = %15
  %18 = load i32, ptr %1, align 4, !tbaa !5
  %19 = icmp eq i32 %18, 49
  br i1 %19, label %20, label %23

20:                                               ; preds = %17
  %21 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.3)
  %22 = call i32 @SEGGER_RTT_ConfigUpBuffer(i32 noundef 0, ptr noundef null, ptr noundef null, i32 noundef 0, i32 noundef 2)
  br label %26

23:                                               ; preds = %17
  %24 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.4)
  %25 = call i32 @SEGGER_RTT_ConfigUpBuffer(i32 noundef 0, ptr noundef null, ptr noundef null, i32 noundef 0, i32 noundef 0)
  br label %26

26:                                               ; preds = %23, %20
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %27

27:                                               ; preds = %45, %26
  %28 = load volatile i32, ptr @_Cnt, align 4, !tbaa !5
  %29 = add nsw i32 %28, 1
  store volatile i32 %29, ptr @_Cnt, align 4, !tbaa !5
  %30 = call i32 (i32, ptr, ...) @SEGGER_RTT_printf(i32 noundef 0, ptr noundef @.str.5, i32 noundef %28)
  %31 = call i32 @SEGGER_RTT_HasKey()
  store i32 %31, ptr %1, align 4, !tbaa !5
  %32 = load i32, ptr %1, align 4, !tbaa !5
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %39

34:                                               ; preds = %27
  %35 = call i32 @SEGGER_RTT_GetKey()
  %36 = icmp eq i32 %35, 32
  %37 = zext i1 %36 to i64
  %38 = select i1 %36, i32 1, i32 0
  store i32 %38, ptr %2, align 4, !tbaa !5
  br label %39

39:                                               ; preds = %34, %27
  %40 = load i32, ptr %2, align 4, !tbaa !5
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %42, label %44

42:                                               ; preds = %39
  %43 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.6)
  br label %46

44:                                               ; preds = %39
  br label %45

45:                                               ; preds = %44
  br i1 true, label %27, label %46

46:                                               ; preds = %45, %42
  %47 = call i32 @SEGGER_RTT_GetKey()
  %48 = call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef @.str.7)
  br label %49

49:                                               ; preds = %46
  br i1 true, label %3, label %50

50:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %1) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @SEGGER_RTT_WriteString(i32 noundef, ptr noundef) #2

declare i32 @SEGGER_RTT_WaitKey() #2

declare i32 @SEGGER_RTT_ConfigUpBuffer(i32 noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) #2

declare i32 @SEGGER_RTT_printf(i32 noundef, ptr noundef, ...) #2

declare i32 @SEGGER_RTT_HasKey() #2

declare i32 @SEGGER_RTT_GetKey() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@_Cnt = external dso_local global i32, align 4
@.str = external hidden unnamed_addr constant [35 x i8], align 1
@.str.1 = external hidden unnamed_addr constant [88 x i8], align 1
@.str.2 = external hidden unnamed_addr constant [97 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [50 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [50 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [48 x i8], align 1
@.str.6 = external hidden unnamed_addr constant [45 x i8], align 1
@.str.7 = external hidden unnamed_addr constant [3 x i8], align 1

; Function Attrs: noreturn nounwind uwtable
define dso_local void @main() local_unnamed_addr #0 {
  br label %1

1:                                                ; preds = %23, %0
  store volatile i32 0, ptr @_Cnt, align 4, !tbaa !5
  %2 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull @.str) #2
  %3 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull @.str.1) #2
  %4 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull @.str.2) #2
  br label %5

5:                                                ; preds = %5, %1
  %6 = tail call i32 @SEGGER_RTT_WaitKey() #2
  %7 = add i32 %6, -51
  %8 = icmp ult i32 %7, -2
  br i1 %8, label %5, label %9, !llvm.loop !9

9:                                                ; preds = %5
  %10 = icmp eq i32 %6, 49
  %.str.3..str.4 = select i1 %10, ptr @.str.3, ptr @.str.4
  %. = select i1 %10, i32 2, i32 0
  %11 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull %.str.3..str.4) #2
  %12 = tail call i32 @SEGGER_RTT_ConfigUpBuffer(i32 noundef 0, ptr noundef null, ptr noundef null, i32 noundef 0, i32 noundef %.) #2
  br label %13

13:                                               ; preds = %22, %9
  %14 = load volatile i32, ptr @_Cnt, align 4, !tbaa !5
  %15 = add nsw i32 %14, 1
  store volatile i32 %15, ptr @_Cnt, align 4, !tbaa !5
  %16 = tail call i32 (i32, ptr, ...) @SEGGER_RTT_printf(i32 noundef 0, ptr noundef nonnull @.str.5, i32 noundef %14) #2
  %17 = tail call i32 @SEGGER_RTT_HasKey() #2
  %.not = icmp eq i32 %17, 0
  br i1 %.not, label %22, label %18

18:                                               ; preds = %13
  %19 = tail call i32 @SEGGER_RTT_GetKey() #2
  %20 = icmp eq i32 %19, 32
  %21 = zext i1 %20 to i32
  br label %22

22:                                               ; preds = %18, %13
  %.1 = phi i32 [ %21, %18 ], [ 0, %13 ]
  %.not5 = icmp eq i32 %.1, 0
  br i1 %.not5, label %13, label %23

23:                                               ; preds = %22
  %24 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull @.str.6) #2
  %25 = tail call i32 @SEGGER_RTT_GetKey() #2
  %26 = tail call i32 @SEGGER_RTT_WriteString(i32 noundef 0, ptr noundef nonnull @.str.7) #2
  br label %1
}

declare i32 @SEGGER_RTT_WriteString(i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @SEGGER_RTT_WaitKey() local_unnamed_addr #1

declare i32 @SEGGER_RTT_ConfigUpBuffer(i32 noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #1

declare i32 @SEGGER_RTT_printf(i32 noundef, ptr noundef, ...) local_unnamed_addr #1

declare i32 @SEGGER_RTT_HasKey() local_unnamed_addr #1

declare i32 @SEGGER_RTT_GetKey() local_unnamed_addr #1

attributes #0 = { noreturn nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass