; LLVM IR from gognl/VMBR :: victim/src/hardware (pci)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%union.pci_device_register_t = type { i32 }
%union.pci_device_t = type { i32 }
%union.pci_config_address_t = type { i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

; Function Attrs: alwaysinline nounwind uwtable
declare void @__outl(i16 noundef zeroext, i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @get_pci_device_register(i32 %0, i8 noundef zeroext %1) #3 {
  %3 = alloca %union.pci_device_register_t, align 4
  %4 = alloca %union.pci_device_t, align 4
  %5 = alloca i8, align 1
  %6 = alloca %union.pci_config_address_t, align 4
  %7 = getelementptr inbounds %union.pci_device_t, ptr %4, i32 0, i32 0
  store i32 %0, ptr %7, align 4
  store i8 %1, ptr %5, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  call void @llvm.memset.p0.i64(ptr align 4 %6, i8 0, i64 4, i1 false)
  %8 = load i32, ptr %4, align 4
  %9 = lshr i32 %8, 16
  %10 = and i32 %9, 255
  %11 = load i32, ptr %6, align 4
  %12 = and i32 %10, 255
  %13 = shl i32 %12, 16
  %14 = and i32 %11, -16711681
  %15 = or i32 %14, %13
  store i32 %15, ptr %6, align 4
  %16 = load i32, ptr %4, align 4
  %17 = lshr i32 %16, 11
  %18 = and i32 %17, 31
  %19 = load i32, ptr %6, align 4
  %20 = and i32 %18, 31
  %21 = shl i32 %20, 11
  %22 = and i32 %19, -63489
  %23 = or i32 %22, %21
  store i32 %23, ptr %6, align 4
  %24 = load i32, ptr %4, align 4
  %25 = lshr i32 %24, 8
  %26 = and i32 %25, 7
  %27 = load i32, ptr %6, align 4
  %28 = and i32 %26, 7
  %29 = shl i32 %28, 8
  %30 = and i32 %27, -1793
  %31 = or i32 %30, %29
  store i32 %31, ptr %6, align 4
  %32 = load i8, ptr %5, align 1, !tbaa !5
  %33 = zext i8 %32 to i32
  %34 = load i32, ptr %6, align 4
  %35 = and i32 %33, 63
  %36 = shl i32 %35, 2
  %37 = and i32 %34, -253
  %38 = or i32 %37, %36
  store i32 %38, ptr %6, align 4
  %39 = load i32, ptr %6, align 4
  %40 = and i32 %39, 2147483647
  %41 = or i32 %40, -2147483648
  store i32 %41, ptr %6, align 4
  %42 = load i32, ptr %6, align 4, !tbaa !5
  call void @__outl(i16 noundef zeroext 3320, i32 noundef %42)
  %43 = call i32 @__inl(i16 noundef zeroext 3324)
  store i32 %43, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  %44 = getelementptr inbounds %union.pci_device_register_t, ptr %3, i32 0, i32 0
  %45 = load i32, ptr %44, align 4
  ret i32 %45
}

; Function Attrs: alwaysinline nounwind uwtable
declare i32 @__inl(i16 noundef zeroext) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #2 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline nounwind uwtable
declare void @__outl(i16 noundef zeroext, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @get_pci_device_register(i32 %0, i8 noundef zeroext %1) local_unnamed_addr #1 {
  %3 = and i32 %0, 16776960
  %4 = shl i8 %1, 2
  %5 = zext i8 %4 to i32
  %6 = or disjoint i32 %3, %5
  %7 = or disjoint i32 %6, -2147483648
  tail call void @__outl(i16 noundef zeroext 3320, i32 noundef %7)
  %8 = tail call i32 @__inl(i16 noundef zeroext 3324)
  ret i32 %8
}

; Function Attrs: alwaysinline nounwind uwtable
declare i32 @__inl(i16 noundef zeroext) local_unnamed_addr #0

attributes #0 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass