; LLVM IR from intel/qpl :: sources/middle-layer/util (topology)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef, i64 noundef, i64 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN3qpl2ml4util26get_cpu_topology_from_apicEPmS2_S2_(ptr noundef %0, ptr noundef %1, ptr noundef %2) #2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i64, align 8
  %19 = alloca i64, align 8
  %20 = alloca i64, align 8
  %21 = alloca i64, align 8
  %22 = alloca i64, align 8
  %23 = alloca i64, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %1, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 0, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  store i32 0, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  store i32 0, ptr %12, align 4, !tbaa !9
  %24 = call noundef i32 @_ZL11__get_cpuidjPjS_S_S_(i32 noundef 31, ptr noundef %8, ptr noundef %9, ptr noundef %10, ptr noundef %11)
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %27, label %26

26:                                               ; preds = %3
  store i32 1, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %98

27:                                               ; preds = %3
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #5
  store i32 0, ptr %14, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #5
  store i32 0, ptr %15, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #5
  store i32 0, ptr %16, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #5
  store i32 0, ptr %17, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #5
  store i64 0, ptr %18, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #5
  store i64 0, ptr %19, align 8, !tbaa !11
  br label %28

28:                                               ; preds = %57, %27
  %29 = load i32, ptr %12, align 4, !tbaa !9
  %30 = call noundef i32 @_ZL17__get_cpuid_countjjPjS_S_S_(i32 noundef 31, i32 noundef %29, ptr noundef %8, ptr noundef %9, ptr noundef %10, ptr noundef %11)
  %31 = load i32, ptr %9, align 4, !tbaa !9
  %32 = icmp eq i32 %31, 0
  br i1 %32, label %33, label %34

33:                                               ; preds = %28
  br label %58

34:                                               ; preds = %28
  %35 = load i32, ptr %10, align 4, !tbaa !9
  %36 = call noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef %35, i64 noundef 8, i64 noundef 15)
  store i32 %36, ptr %14, align 4, !tbaa !9
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = call noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef %37, i64 noundef 0, i64 noundef 4)
  store i32 %38, ptr %15, align 4, !tbaa !9
  %39 = load i32, ptr %14, align 4, !tbaa !9
  %40 = icmp eq i32 %39, 1
  br i1 %40, label %41, label %48

41:                                               ; preds = %34
  %42 = load i32, ptr %15, align 4, !tbaa !9
  %43 = sext i32 %42 to i64
  store i64 %43, ptr %18, align 8, !tbaa !11
  %44 = load i32, ptr %15, align 4, !tbaa !9
  %45 = zext i32 %44 to i64
  %46 = shl i64 1, %45
  %47 = sub i64 %46, 1
  store i64 %47, ptr %19, align 8, !tbaa !11
  store i32 1, ptr %16, align 4, !tbaa !9
  br label %54

48:                                               ; preds = %34
  %49 = load i32, ptr %14, align 4, !tbaa !9
  %50 = icmp eq i32 %49, 2
  br i1 %50, label %51, label %52

51:                                               ; preds = %48
  store i32 1, ptr %17, align 4, !tbaa !9
  br label %53

52:                                               ; preds = %48
  br label %58

53:                                               ; preds = %51
  br label %54

54:                                               ; preds = %53, %41
  %55 = load i32, ptr %12, align 4, !tbaa !9
  %56 = add i32 %55, 1
  store i32 %56, ptr %12, align 4, !tbaa !9
  br label %57

57:                                               ; preds = %54
  br i1 true, label %28, label %58, !llvm.loop !13

58:                                               ; preds = %57, %52, %33
  call void @llvm.lifetime.start.p0(i64 8, ptr %20) #5
  %59 = load i32, ptr %15, align 4, !tbaa !9
  %60 = zext i32 %59 to i64
  %61 = shl i64 1, %60
  %62 = sub i64 %61, 1
  store i64 %62, ptr %20, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %21) #5
  %63 = load i32, ptr %15, align 4, !tbaa !9
  %64 = sext i32 %63 to i64
  store i64 %64, ptr %21, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #5
  %65 = load i64, ptr %20, align 8, !tbaa !11
  %66 = xor i64 -1, %65
  store i64 %66, ptr %22, align 8, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 8, ptr %23) #5
  store i64 0, ptr %23, align 8, !tbaa !11
  %67 = load i32, ptr %16, align 4, !tbaa !9
  %68 = icmp ne i32 %67, 0
  br i1 %68, label %69, label %76

69:                                               ; preds = %58
  %70 = load i32, ptr %17, align 4, !tbaa !9
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %76

72:                                               ; preds = %69
  %73 = load i64, ptr %20, align 8, !tbaa !11
  %74 = load i64, ptr %19, align 8, !tbaa !11
  %75 = xor i64 %73, %74
  store i64 %75, ptr %23, align 8, !tbaa !11
  br label %77

76:                                               ; preds = %69, %58
  store i32 1, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %97

77:                                               ; preds = %72
  %78 = load i32, ptr %11, align 4, !tbaa !9
  %79 = zext i32 %78 to i64
  %80 = load i64, ptr %19, align 8, !tbaa !11
  %81 = and i64 %79, %80
  %82 = load ptr, ptr %5, align 8, !tbaa !5
  store i64 %81, ptr %82, align 8, !tbaa !11
  %83 = load i32, ptr %11, align 4, !tbaa !9
  %84 = zext i32 %83 to i64
  %85 = load i64, ptr %23, align 8, !tbaa !11
  %86 = and i64 %84, %85
  %87 = load i64, ptr %18, align 8, !tbaa !11
  %88 = lshr i64 %86, %87
  %89 = load ptr, ptr %6, align 8, !tbaa !5
  store i64 %88, ptr %89, align 8, !tbaa !11
  %90 = load i32, ptr %11, align 4, !tbaa !9
  %91 = zext i32 %90 to i64
  %92 = load i64, ptr %22, align 8, !tbaa !11
  %93 = and i64 %91, %92
  %94 = load i64, ptr %21, align 8, !tbaa !11
  %95 = lshr i64 %93, %94
  %96 = load ptr, ptr %7, align 8, !tbaa !5
  store i64 %95, ptr %96, align 8, !tbaa !11
  store i32 0, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %97

97:                                               ; preds = %77, %76
  call void @llvm.lifetime.end.p0(i64 8, ptr %23) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %21) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %20) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #5
  br label %98

98:                                               ; preds = %97, %26
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  %99 = load i32, ptr %4, align 4
  ret i32 %99
}

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef i32 @_ZL11__get_cpuidjPjS_S_S_(i32 noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZL17__get_cpuid_countjjPjS_S_S_(i32 noundef, i32 noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef, i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 0, 2) i32 @_ZN3qpl2ml4util26get_cpu_topology_from_apicEPmS2_S2_(ptr nocapture noundef writeonly %0, ptr nocapture noundef writeonly %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #2 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %4) #5
  store i32 0, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #5
  store i32 0, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #5
  store i32 0, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %7) #5
  store i32 0, ptr %7, align 4, !tbaa !5
  %8 = call noundef i32 @_ZL11__get_cpuidjPjS_S_S_(i32 noundef 31, ptr noundef nonnull %4, ptr noundef nonnull %5, ptr noundef nonnull %6, ptr noundef nonnull %7)
  %.not = icmp eq i32 %8, 0
  br i1 %.not, label %._crit_edge.thread, label %.preheader

.preheader:                                       ; preds = %3
  %9 = call noundef i32 @_ZL17__get_cpuid_countjjPjS_S_S_(i32 noundef 31, i32 noundef 0, ptr noundef nonnull %4, ptr noundef nonnull %5, ptr noundef nonnull %6, ptr noundef nonnull %7)
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = icmp eq i32 %10, 0
  br i1 %11, label %._crit_edge.thread, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader, %20
  %.02239 = phi i32 [ %21, %20 ], [ 0, %.preheader ]
  %.02338 = phi i64 [ %.124, %20 ], [ 0, %.preheader ]
  %.02537 = phi i64 [ %.126, %20 ], [ 0, %.preheader ]
  %.02736 = phi i32 [ %.128, %20 ], [ 0, %.preheader ]
  %.02935 = phi i32 [ %.130, %20 ], [ 0, %.preheader ]
  %12 = load i32, ptr %6, align 4, !tbaa !5
  %13 = call noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef %12, i64 noundef 8, i64 noundef 15)
  %14 = load i32, ptr %4, align 4, !tbaa !5
  %15 = call noundef i32 @_ZN3qpl2ml4util17get_selected_bitsEimm(i32 noundef %14, i64 noundef 0, i64 noundef 4)
  switch i32 %13, label %._crit_edge [
    i32 1, label %16
    i32 2, label %20
  ]

16:                                               ; preds = %.lr.ph
  %17 = sext i32 %15 to i64
  %18 = zext nneg i32 %15 to i64
  %notmask = shl nsw i64 -1, %18
  %19 = xor i64 %notmask, -1
  br label %20

20:                                               ; preds = %.lr.ph, %16
  %.130 = phi i32 [ 1, %16 ], [ %.02935, %.lr.ph ]
  %.128 = phi i32 [ %.02736, %16 ], [ 1, %.lr.ph ]
  %.126 = phi i64 [ %17, %16 ], [ %.02537, %.lr.ph ]
  %.124 = phi i64 [ %19, %16 ], [ %.02338, %.lr.ph ]
  %21 = add i32 %.02239, 1
  %22 = call noundef i32 @_ZL17__get_cpuid_countjjPjS_S_S_(i32 noundef 31, i32 noundef %21, ptr noundef nonnull %4, ptr noundef nonnull %5, ptr noundef nonnull %6, ptr noundef nonnull %7)
  %23 = load i32, ptr %5, align 4, !tbaa !5
  %24 = icmp eq i32 %23, 0
  br i1 %24, label %._crit_edge, label %.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %20, %.lr.ph
  %.029.lcssa.ph = phi i32 [ %.130, %20 ], [ %.02935, %.lr.ph ]
  %.027.lcssa.ph = phi i32 [ %.128, %20 ], [ %.02736, %.lr.ph ]
  %.025.lcssa.ph = phi i64 [ %.126, %20 ], [ %.02537, %.lr.ph ]
  %.023.lcssa.ph = phi i64 [ %.124, %20 ], [ %.02338, %.lr.ph ]
  %25 = icmp ne i32 %.029.lcssa.ph, 0
  %26 = icmp ne i32 %.027.lcssa.ph, 0
  %27 = select i1 %25, i1 %26, i1 false
  br i1 %27, label %28, label %._crit_edge.thread

28:                                               ; preds = %._crit_edge
  %29 = zext nneg i32 %15 to i64
  %notmask34 = shl nsw i64 -1, %29
  %30 = xor i64 %.023.lcssa.ph, %notmask34
  %31 = xor i64 %30, -1
  %32 = load i32, ptr %7, align 4, !tbaa !5
  %33 = zext i32 %32 to i64
  %34 = and i64 %.023.lcssa.ph, %33
  store i64 %34, ptr %0, align 8, !tbaa !11
  %35 = and i64 %33, %31
  %36 = lshr i64 %35, %.025.lcssa.ph
  store i64 %36, ptr %1, align 8, !tbaa !11
  %37 = and i64 %notmask34, %33
  %38 = lshr i64 %37, %29
  store i64 %38, ptr %2, align 8, !tbaa !11
  br label %._crit_edge.thread

._crit_edge.thread:                               ; preds = %.preheader, %28, %._crit_edge, %3
  %.1 = phi i32 [ 1, %3 ], [ 0, %28 ], [ 1, %._crit_edge ], [ 1, %.preheader ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %4) #5
  ret i32 %.1
}

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef i32 @_ZL11__get_cpuidjPjS_S_S_(i32 noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i32 @_ZL17__get_cpuid_countjjPjS_S_S_(i32 noundef, i32 noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #4

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass