; LLVM IR from gognl/VMBR :: victim/src/hardware (pci)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%union.pci_device_t = type { i32 }
%union.pci_device_register_t = type { i32 }
%union.pci_config_address_t = type { i32 }

; Function Attrs: nounwind uwtable
define dso_local void @set_pci_device_register(i32 %0, i8 noundef zeroext %1, i32 %2) #0 {
  %4 = alloca %union.pci_device_t, align 4
  %5 = alloca %union.pci_device_register_t, align 4
  %6 = alloca i8, align 1
  %7 = alloca %union.pci_config_address_t, align 4
  %8 = getelementptr inbounds %union.pci_device_t, ptr %4, i32 0, i32 0
  store i32 %0, ptr %8, align 4
  %9 = getelementptr inbounds %union.pci_device_register_t, ptr %5, i32 0, i32 0
  store i32 %2, ptr %9, align 4
  store i8 %1, ptr %6, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  call void @llvm.memset.p0.i64(ptr align 4 %7, i8 0, i64 4, i1 false)
  %10 = load i32, ptr %4, align 4
  %11 = lshr i32 %10, 16
  %12 = and i32 %11, 255
  %13 = load i32, ptr %7, align 4
  %14 = and i32 %12, 255
  %15 = shl i32 %14, 16
  %16 = and i32 %13, -16711681
  %17 = or i32 %16, %15
  store i32 %17, ptr %7, align 4
  %18 = load i32, ptr %4, align 4
  %19 = lshr i32 %18, 11
  %20 = and i32 %19, 31
  %21 = load i32, ptr %7, align 4
  %22 = and i32 %20, 31
  %23 = shl i32 %22, 11
  %24 = and i32 %21, -63489
  %25 = or i32 %24, %23
  store i32 %25, ptr %7, align 4
  %26 = load i32, ptr %4, align 4
  %27 = lshr i32 %26, 8
  %28 = and i32 %27, 7
  %29 = load i32, ptr %7, align 4
  %30 = and i32 %28, 7
  %31 = shl i32 %30, 8
  %32 = and i32 %29, -1793
  %33 = or i32 %32, %31
  store i32 %33, ptr %7, align 4
  %34 = load i8, ptr %6, align 1, !tbaa !5
  %35 = zext i8 %34 to i32
  %36 = load i32, ptr %7, align 4
  %37 = and i32 %35, 63
  %38 = shl i32 %37, 2
  %39 = and i32 %36, -253
  %40 = or i32 %39, %38
  store i32 %40, ptr %7, align 4
  %41 = load i32, ptr %7, align 4
  %42 = and i32 %41, 2147483647
  %43 = or i32 %42, -2147483648
  store i32 %43, ptr %7, align 4
  %44 = load i32, ptr %7, align 4, !tbaa !5
  call void @__outl(i16 noundef zeroext 3320, i32 noundef %44)
  %45 = load i32, ptr %5, align 4, !tbaa !5
  call void @__outl(i16 noundef zeroext 3324, i32 noundef %45)
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: alwaysinline nounwind uwtable
declare void @__outl(i16 noundef zeroext, i32 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local void @set_pci_device_register(i32 %0, i8 noundef zeroext %1, i32 %2) local_unnamed_addr #0 {
  %4 = and i32 %0, 16776960
  %5 = shl i8 %1, 2
  %6 = zext i8 %5 to i32
  %7 = or disjoint i32 %4, %6
  %8 = or disjoint i32 %7, -2147483648
  tail call void @__outl(i16 noundef zeroext 3320, i32 noundef %8)
  tail call void @__outl(i16 noundef zeroext 3324, i32 noundef %2)
  ret void
}

; Function Attrs: alwaysinline nounwind uwtable
declare void @__outl(i16 noundef zeroext, i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,TailCallElimPass