; LLVM IR from fast-pack/SIMDCompressionAndIntersection :: src/simdbitpacking.ll/ZN18SIMDCompressionLib18 (SIMD_fastunpack1EPKDv2_xPj)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef, <2 x i64> noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef, i32 noundef) #1

; Function Attrs: alwaysinline mustprogress uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18SIMDCompressionLib18__SIMD_fastunpack1EPKDv2_xPj(ptr noalias noundef %0, ptr noalias noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca <2 x i64>, align 16
  %7 = alloca <2 x i64>, align 16
  %8 = alloca <2 x i64>, align 16
  %9 = alloca <2 x i64>, align 16
  %10 = alloca <2 x i64>, align 16
  %11 = alloca <2 x i64>, align 16
  %12 = alloca <2 x i64>, align 16
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %15, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #4
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %16)
  store <2 x i64> %17, ptr %6, align 16, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr %7) #4
  %18 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  store <2 x i64> %18, ptr %7, align 16, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr %8) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %12) #4
  %19 = call noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef 1)
  store <2 x i64> %19, ptr %12, align 16, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #4
  store i32 0, ptr %13, align 4, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #4
  store i32 0, ptr %14, align 4, !tbaa !10
  br label %20

20:                                               ; preds = %61, %2
  %21 = load i32, ptr %14, align 4, !tbaa !10
  %22 = icmp ult i32 %21, 8
  br i1 %22, label %24, label %23

23:                                               ; preds = %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #4
  br label %64

24:                                               ; preds = %20
  %25 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  %26 = load i32, ptr %13, align 4, !tbaa !10
  %27 = add i32 %26, 1
  store i32 %27, ptr %13, align 4, !tbaa !10
  %28 = call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %25, i32 noundef %26)
  %29 = load <2 x i64>, ptr %12, align 16, !tbaa !9
  %30 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %28, <2 x i64> noundef %29)
  store <2 x i64> %30, ptr %8, align 16, !tbaa !9
  %31 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  %32 = load i32, ptr %13, align 4, !tbaa !10
  %33 = add i32 %32, 1
  store i32 %33, ptr %13, align 4, !tbaa !10
  %34 = call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %31, i32 noundef %32)
  %35 = load <2 x i64>, ptr %12, align 16, !tbaa !9
  %36 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %34, <2 x i64> noundef %35)
  store <2 x i64> %36, ptr %9, align 16, !tbaa !9
  %37 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  %38 = load i32, ptr %13, align 4, !tbaa !10
  %39 = add i32 %38, 1
  store i32 %39, ptr %13, align 4, !tbaa !10
  %40 = call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %37, i32 noundef %38)
  %41 = load <2 x i64>, ptr %12, align 16, !tbaa !9
  %42 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %40, <2 x i64> noundef %41)
  store <2 x i64> %42, ptr %10, align 16, !tbaa !9
  %43 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  %44 = load i32, ptr %13, align 4, !tbaa !10
  %45 = add i32 %44, 1
  store i32 %45, ptr %13, align 4, !tbaa !10
  %46 = call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %43, i32 noundef %44)
  %47 = load <2 x i64>, ptr %12, align 16, !tbaa !9
  %48 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %46, <2 x i64> noundef %47)
  store <2 x i64> %48, ptr %11, align 16, !tbaa !9
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds <2 x i64>, ptr %49, i32 1
  store ptr %50, ptr %5, align 8, !tbaa !5
  %51 = load <2 x i64>, ptr %8, align 16, !tbaa !9
  call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %49, <2 x i64> noundef %51)
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds <2 x i64>, ptr %52, i32 1
  store ptr %53, ptr %5, align 8, !tbaa !5
  %54 = load <2 x i64>, ptr %9, align 16, !tbaa !9
  call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %52, <2 x i64> noundef %54)
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds <2 x i64>, ptr %55, i32 1
  store ptr %56, ptr %5, align 8, !tbaa !5
  %57 = load <2 x i64>, ptr %10, align 16, !tbaa !9
  call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %55, <2 x i64> noundef %57)
  %58 = load ptr, ptr %5, align 8, !tbaa !5
  %59 = getelementptr inbounds <2 x i64>, ptr %58, i32 1
  store ptr %59, ptr %5, align 8, !tbaa !5
  %60 = load <2 x i64>, ptr %11, align 16, !tbaa !9
  call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %58, <2 x i64> noundef %60)
  br label %61

61:                                               ; preds = %24
  %62 = load i32, ptr %14, align 4, !tbaa !10
  %63 = add i32 %62, 1
  store i32 %63, ptr %14, align 4, !tbaa !10
  br label %20, !llvm.loop !12

64:                                               ; preds = %23
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef, <2 x i64> noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18SIMDCompressionLib18__SIMD_fastunpack1EPKDv2_xPj(ptr noalias noundef %0, ptr noalias noundef %1) local_unnamed_addr #2 {
  %3 = tail call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %0)
  %4 = tail call noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef 1)
  br label %6

5:                                                ; preds = %6
  ret void

6:                                                ; preds = %2, %6
  %.028 = phi i32 [ 0, %2 ], [ %23, %6 ]
  %.02427 = phi i32 [ 0, %2 ], [ %16, %6 ]
  %.02526 = phi ptr [ %1, %2 ], [ %22, %6 ]
  %7 = or disjoint i32 %.02427, 1
  %8 = tail call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %3, i32 noundef %.02427)
  %9 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %8, <2 x i64> noundef %4)
  %10 = or disjoint i32 %.02427, 2
  %11 = tail call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %3, i32 noundef %7)
  %12 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %11, <2 x i64> noundef %4)
  %13 = or disjoint i32 %.02427, 3
  %14 = tail call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %3, i32 noundef %10)
  %15 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %14, <2 x i64> noundef %4)
  %16 = add nuw nsw i32 %.02427, 4
  %17 = tail call noundef <2 x i64> @_ZL14_mm_srli_epi32Dv2_xi(<2 x i64> noundef %3, i32 noundef %13)
  %18 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %17, <2 x i64> noundef %4)
  %19 = getelementptr inbounds i8, ptr %.02526, i64 16
  tail call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %.02526, <2 x i64> noundef %9)
  %20 = getelementptr inbounds i8, ptr %.02526, i64 32
  tail call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef nonnull %19, <2 x i64> noundef %12)
  %21 = getelementptr inbounds i8, ptr %.02526, i64 48
  tail call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef nonnull %20, <2 x i64> noundef %15)
  %22 = getelementptr inbounds i8, ptr %.02526, i64 64
  tail call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef nonnull %21, <2 x i64> noundef %18)
  %23 = add nuw nsw i32 %.028, 1
  %exitcond.not = icmp eq i32 %23, 8
  br i1 %exitcond.not, label %5, label %6, !llvm.loop !5
}

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass