; LLVM IR from kimwalisch/primesieve :: src/api.ll (ZN10primesieve14get_sieve_sizeEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.primesieve::CpuInfo" = type { i64, %"class.primesieve::Array.0", %"class.primesieve::Array.0", %"class.std::__cxx11::basic_string" }
%"class.primesieve::Array.0" = type { [4 x i64] }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

@_ZN12_GLOBAL__N_110sieve_sizeE = external hidden global i32, align 4
@_ZN10primesieve7cpuInfoE = external global %"class.primesieve::CpuInfo", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN10primesieve14get_sieve_sizeEv() #1 {
  %1 = alloca i32, align 4
  %2 = alloca i64, align 8
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = load i32, ptr @_ZN12_GLOBAL__N_110sieve_sizeE, align 4, !tbaa !5
  %15 = icmp ne i32 %14, 0
  br i1 %15, label %16, label %18

16:                                               ; preds = %0
  %17 = load i32, ptr @_ZN12_GLOBAL__N_110sieve_sizeE, align 4, !tbaa !5
  store i32 %17, ptr %1, align 4
  br label %91

18:                                               ; preds = %0
  %19 = call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %19, label %20, label %75

20:                                               ; preds = %18
  %21 = call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL2CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %21, label %22, label %75

22:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
  %23 = call noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %24 = lshr i64 %23, 10
  store i64 %24, ptr %2, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
  %25 = call noundef i64 @_ZNK10primesieve7CpuInfo12l2CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %26 = lshr i64 %25, 10
  store i64 %26, ptr %3, align 8, !tbaa !9
  %27 = call noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %27, label %28, label %60

28:                                               ; preds = %22
  %29 = call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %30 = icmp ugt i64 %29, 1
  br i1 %30, label %36, label %31

31:                                               ; preds = %28
  %32 = call noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL3SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %32, label %33, label %60

33:                                               ; preds = %31
  %34 = call noundef i64 @_ZNK10primesieve7CpuInfo9l3SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %35 = icmp ugt i64 %34, 1
  br i1 %35, label %36, label %60

36:                                               ; preds = %33, %28
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #5
  %37 = load i64, ptr %3, align 8, !tbaa !9
  %38 = call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %39 = udiv i64 %37, %38
  store i64 %39, ptr %4, align 8, !tbaa !9
  %40 = call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %41 = icmp eq i64 %40, 2
  br i1 %41, label %42, label %45

42:                                               ; preds = %36
  %43 = load i64, ptr %4, align 8, !tbaa !9
  %44 = call noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef %43)
  store i64 %44, ptr %4, align 8, !tbaa !9
  br label %49

45:                                               ; preds = %36
  %46 = load i64, ptr %4, align 8, !tbaa !9
  %47 = sub i64 %46, 1
  %48 = call noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef %47)
  store i64 %48, ptr %4, align 8, !tbaa !9
  br label %49

49:                                               ; preds = %45, %42
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %2, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %51 = load i64, ptr %50, align 8, !tbaa !9
  store i64 %51, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #5
  %52 = load i64, ptr %2, align 8, !tbaa !9
  %53 = mul i64 %52, 16
  store i64 %53, ptr %6, align 8, !tbaa !9
  %54 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %55 = load i64, ptr %54, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #5
  store i64 %55, ptr %5, align 8, !tbaa !9
  %56 = load i64, ptr %5, align 8, !tbaa !9
  %57 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %56, i32 noundef 8192)
  store i64 %57, ptr %5, align 8, !tbaa !9
  %58 = load i64, ptr %5, align 8, !tbaa !9
  %59 = trunc i64 %58 to i32
  store i32 %59, ptr %1, align 4
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #5
  br label %74

60:                                               ; preds = %33, %31, %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %61 = load i64, ptr %3, align 8, !tbaa !9
  %62 = sub i64 %61, 1
  %63 = call noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef %62)
  store i64 %63, ptr %8, align 8, !tbaa !9
  %64 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %2, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %65 = load i64, ptr %64, align 8, !tbaa !9
  store i64 %65, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #5
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  %66 = load i64, ptr %2, align 8, !tbaa !9
  %67 = mul i64 %66, 8
  store i64 %67, ptr %10, align 8, !tbaa !9
  %68 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %10, ptr noundef nonnull align 8 dereferenceable(8) %8)
  %69 = load i64, ptr %68, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  store i64 %69, ptr %9, align 8, !tbaa !9
  %70 = load i64, ptr %9, align 8, !tbaa !9
  %71 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %70, i32 noundef 8192)
  store i64 %71, ptr %9, align 8, !tbaa !9
  %72 = load i64, ptr %9, align 8, !tbaa !9
  %73 = trunc i64 %72 to i32
  store i32 %73, ptr %1, align 4
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  br label %74

74:                                               ; preds = %60, %49
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
  br label %91

75:                                               ; preds = %20, %18
  %76 = call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %76, label %77, label %84

77:                                               ; preds = %75
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #5
  %78 = call noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %79 = lshr i64 %78, 10
  store i64 %79, ptr %11, align 8, !tbaa !9
  %80 = load i64, ptr %11, align 8, !tbaa !9
  %81 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %80, i32 noundef 8192)
  store i64 %81, ptr %11, align 8, !tbaa !9
  %82 = load i64, ptr %11, align 8, !tbaa !9
  %83 = trunc i64 %82 to i32
  store i32 %83, ptr %1, align 4
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #5
  br label %91

84:                                               ; preds = %75
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #5
  store i64 32, ptr %12, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #5
  %85 = load i64, ptr %12, align 8, !tbaa !9
  %86 = mul i64 %85, 8
  store i64 %86, ptr %13, align 8, !tbaa !9
  %87 = load i64, ptr %13, align 8, !tbaa !9
  %88 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %87, i32 noundef 8192)
  store i64 %88, ptr %13, align 8, !tbaa !9
  %89 = load i64, ptr %13, align 8, !tbaa !9
  %90 = trunc i64 %89 to i32
  store i32 %90, ptr %1, align 4
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #5
  br label %91

91:                                               ; preds = %84, %77, %74, %16
  %92 = load i32, ptr %1, align 4
  ret i32 %92
}

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL2CacheEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef i64 @_ZNK10primesieve7CpuInfo12l2CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL2SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL3SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

declare noundef i64 @_ZNK10primesieve7CpuInfo9l3SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef, i64 noundef, i32 noundef) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.primesieve::CpuInfo" = type { i64, %"class.primesieve::Array.0", %"class.primesieve::Array.0", %"class.std::__cxx11::basic_string" }
%"class.primesieve::Array.0" = type { [4 x i64] }
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }

@_ZN12_GLOBAL__N_110sieve_sizeE = external hidden local_unnamed_addr global i32, align 4
@_ZN10primesieve7cpuInfoE = external global %"class.primesieve::CpuInfo", align 8

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN10primesieve14get_sieve_sizeEv() local_unnamed_addr #1 {
  %1 = alloca i64, align 8
  %2 = alloca i64, align 8
  %3 = alloca i64, align 8
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = load i32, ptr @_ZN12_GLOBAL__N_110sieve_sizeE, align 4, !tbaa !5
  %.not = icmp eq i32 %6, 0
  br i1 %.not, label %7, label %60

7:                                                ; preds = %0
  %8 = tail call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %8, label %9, label %50

9:                                                ; preds = %7
  %10 = tail call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL2CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %10, label %11, label %50

11:                                               ; preds = %9
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %1) #5
  %12 = tail call noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %13 = lshr i64 %12, 10
  store i64 %13, ptr %1, align 8, !tbaa !9
  %14 = tail call noundef i64 @_ZNK10primesieve7CpuInfo12l2CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %15 = lshr i64 %14, 10
  %16 = tail call noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %16, label %17, label %39

17:                                               ; preds = %11
  %18 = tail call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %19 = icmp ugt i64 %18, 1
  br i1 %19, label %25, label %20

20:                                               ; preds = %17
  %21 = tail call noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL3SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %21, label %22, label %39

22:                                               ; preds = %20
  %23 = tail call noundef i64 @_ZNK10primesieve7CpuInfo9l3SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %24 = icmp ugt i64 %23, 1
  br i1 %24, label %25, label %39

25:                                               ; preds = %22, %17
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %2) #5
  %26 = tail call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %27 = udiv i64 %15, %26
  %28 = tail call noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %29 = icmp ne i64 %28, 2
  %30 = sext i1 %29 to i64
  %.sink = add nsw i64 %27, %30
  %31 = tail call noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef %.sink)
  store i64 %31, ptr %2, align 8, !tbaa !9
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) %2)
  %33 = load i64, ptr %32, align 8, !tbaa !9
  store i64 %33, ptr %2, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %3) #5
  %34 = load i64, ptr %1, align 8, !tbaa !9
  %35 = shl i64 %34, 4
  store i64 %35, ptr %3, align 8, !tbaa !9
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %2)
  %37 = load i64, ptr %36, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %3) #5
  %38 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %37, i32 noundef 8192)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %2) #5
  br label %49

39:                                               ; preds = %22, %20, %11
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %4) #5
  %40 = add nsw i64 %15, -1
  %41 = tail call noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef %40)
  store i64 %41, ptr %4, align 8, !tbaa !9
  %42 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %43 = load i64, ptr %42, align 8, !tbaa !9
  store i64 %43, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %5) #5
  %44 = load i64, ptr %1, align 8, !tbaa !9
  %45 = shl i64 %44, 3
  store i64 %45, ptr %5, align 8, !tbaa !9
  %46 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 8 dereferenceable(8) %4)
  %47 = load i64, ptr %46, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %5) #5
  %48 = call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %47, i32 noundef 8192)
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %4) #5
  br label %49

49:                                               ; preds = %39, %25
  %.0.in = phi i64 [ %38, %25 ], [ %48, %39 ]
  %.0 = trunc i64 %.0.in to i32
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %1) #5
  br label %60

50:                                               ; preds = %9, %7
  %51 = tail call noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  br i1 %51, label %52, label %57

52:                                               ; preds = %50
  %53 = tail call noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104) @_ZN10primesieve7cpuInfoE)
  %54 = lshr i64 %53, 10
  %55 = tail call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef %54, i32 noundef 8192)
  %56 = trunc i64 %55 to i32
  br label %60

57:                                               ; preds = %50
  %58 = tail call noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef 16, i64 noundef 256, i32 noundef 8192)
  %59 = trunc i64 %58 to i32
  br label %60

60:                                               ; preds = %0, %57, %52, %49
  %.1 = phi i32 [ %.0, %49 ], [ %56, %52 ], [ %59, %57 ], [ %6, %0 ]
  ret i32 %.1
}

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL1CacheEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo10hasL2CacheEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef i64 @_ZNK10primesieve7CpuInfo12l1CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef i64 @_ZNK10primesieve7CpuInfo12l2CacheBytesEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL2SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef i64 @_ZNK10primesieve7CpuInfo9l2SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK10primesieve7CpuInfo12hasL3SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

declare noundef i64 @_ZNK10primesieve7CpuInfo9l3SharingEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare hidden noundef i64 @_ZN12_GLOBAL__N_19floorPow2ImEET_S1_(i64 noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef i64 @_ZN12_GLOBAL__N_19inBetweenIimiEET0_T_S1_T1_(i32 noundef, i64 noundef, i32 noundef) local_unnamed_addr #4

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass