; LLVM IR from devantler/software-engineering-f22-shared :: IOT/BudgetManagementExcercise-03-28/ESP-Project/components/components/nghttp (id)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i64 @mrb_float_id(double noundef %0) #1 {
  %2 = alloca double, align 8
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store double %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #2
  store ptr %2, ptr %3, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 8, ptr %4, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !11
  %6 = load double, ptr %2, align 8, !tbaa !5
  %7 = fcmp oeq double %6, 0.000000e+00
  br i1 %7, label %8, label %9

8:                                                ; preds = %1
  store double 0.000000e+00, ptr %2, align 8, !tbaa !5
  br label %9

9:                                                ; preds = %8, %1
  br label %10

10:                                               ; preds = %14, %9
  %11 = load i32, ptr %4, align 4, !tbaa !11
  %12 = add nsw i32 %11, -1
  store i32 %12, ptr %4, align 4, !tbaa !11
  %13 = icmp ne i32 %11, 0
  br i1 %13, label %14, label %23

14:                                               ; preds = %10
  %15 = load i32, ptr %5, align 4, !tbaa !11
  %16 = mul i32 %15, 65599
  %17 = load ptr, ptr %3, align 8, !tbaa !9
  %18 = load i8, ptr %17, align 1, !tbaa !13
  %19 = sext i8 %18 to i32
  %20 = add i32 %16, %19
  store i32 %20, ptr %5, align 4, !tbaa !11
  %21 = load ptr, ptr %3, align 8, !tbaa !9
  %22 = getelementptr inbounds i8, ptr %21, i32 1
  store ptr %22, ptr %3, align 8, !tbaa !9
  br label %10, !llvm.loop !14

23:                                               ; preds = %10
  %24 = load i32, ptr %5, align 4, !tbaa !11
  %25 = load i32, ptr %5, align 4, !tbaa !11
  %26 = lshr i32 %25, 5
  %27 = add i32 %24, %26
  store i32 %27, ptr %5, align 4, !tbaa !11
  %28 = load i32, ptr %5, align 4, !tbaa !11
  %29 = zext i32 %28 to i64
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #2
  ret i64 %29
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local range(i64 0, 4294967296) i64 @mrb_float_id(double noundef %0) local_unnamed_addr #0 {
  %2 = fcmp oeq double %0, 0.000000e+00
  %storemerge = select i1 %2, double 0.000000e+00, double %0
  %3 = bitcast double %storemerge to i64
  %.0.extract.trunc = trunc i64 %3 to i32
  %sext = shl i32 %.0.extract.trunc, 24
  %4 = ashr exact i32 %sext, 24
  %5 = mul nsw i32 %4, 65599
  %6 = trunc i64 %3 to i32
  %7 = shl i32 %6, 16
  %8 = ashr i32 %7, 24
  %9 = add nsw i32 %5, %8
  %10 = mul i32 %9, 65599
  %11 = trunc i64 %3 to i32
  %12 = shl i32 %11, 8
  %13 = ashr i32 %12, 24
  %14 = add i32 %10, %13
  %15 = mul i32 %14, 65599
  %16 = trunc i64 %3 to i32
  %17 = ashr i32 %16, 24
  %18 = add i32 %15, %17
  %19 = mul i32 %18, 65599
  %sh.diff = lshr i64 %3, 8
  %tr.sh.diff = trunc i64 %sh.diff to i32
  %20 = ashr i32 %tr.sh.diff, 24
  %21 = add i32 %19, %20
  %22 = mul i32 %21, 65599
  %sh.diff16 = lshr i64 %3, 16
  %tr.sh.diff17 = trunc i64 %sh.diff16 to i32
  %23 = ashr i32 %tr.sh.diff17, 24
  %24 = add i32 %22, %23
  %25 = mul i32 %24, 65599
  %sh.diff19 = lshr i64 %3, 24
  %tr.sh.diff20 = trunc i64 %sh.diff19 to i32
  %26 = ashr i32 %tr.sh.diff20, 24
  %27 = add i32 %25, %26
  %28 = mul i32 %27, 65599
  %sh.diff22 = lshr i64 %3, 32
  %tr.sh.diff23 = trunc nuw i64 %sh.diff22 to i32
  %29 = ashr i32 %tr.sh.diff23, 24
  %30 = add i32 %28, %29
  %31 = lshr i32 %30, 5
  %32 = add i32 %31, %30
  %33 = zext i32 %32 to i64
  ret i64 %33
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LoopRotatePass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass