; LLVM IR from intel/qpl :: sources/core-sw/dispatcher (dispatcher)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN3qpl7core_sw10dispatcher19get_pack_bits_indexEjjj(i32 noundef %0, i32 noundef %1, i32 noundef %2) #1 {
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !5
  store i32 %2, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %9 = load i32, ptr %5, align 4, !tbaa !5
  %10 = sub i32 %9, 1
  store i32 %10, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #2
  %11 = load i32, ptr %4, align 4, !tbaa !5
  %12 = icmp ne i32 %11, 0
  %13 = zext i1 %12 to i64
  %14 = select i1 %12, i32 35, i32 0
  store i32 %14, ptr %8, align 4, !tbaa !5
  %15 = load i32, ptr %6, align 4, !tbaa !5
  %16 = icmp ne i32 %15, 0
  br i1 %16, label %17, label %40

17:                                               ; preds = %3
  %18 = load i32, ptr %5, align 4, !tbaa !5
  %19 = icmp uge i32 8, %18
  br i1 %19, label %20, label %27

20:                                               ; preds = %17
  %21 = load i32, ptr %6, align 4, !tbaa !5
  switch i32 %21, label %25 [
    i32 1, label %22
    i32 2, label %23
    i32 3, label %24
  ]

22:                                               ; preds = %20
  store i32 7, ptr %7, align 4, !tbaa !5
  br label %26

23:                                               ; preds = %20
  store i32 32, ptr %7, align 4, !tbaa !5
  br label %26

24:                                               ; preds = %20
  store i32 33, ptr %7, align 4, !tbaa !5
  br label %26

25:                                               ; preds = %20
  br label %26

26:                                               ; preds = %25, %24, %23, %22
  br label %39

27:                                               ; preds = %17
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = icmp uge i32 16, %28
  br i1 %29, label %30, label %37

30:                                               ; preds = %27
  %31 = load i32, ptr %6, align 4, !tbaa !5
  switch i32 %31, label %35 [
    i32 1, label %32
    i32 2, label %33
    i32 3, label %34
  ]

32:                                               ; preds = %30
  br label %36

33:                                               ; preds = %30
  store i32 15, ptr %7, align 4, !tbaa !5
  br label %36

34:                                               ; preds = %30
  store i32 34, ptr %7, align 4, !tbaa !5
  br label %36

35:                                               ; preds = %30
  br label %36

36:                                               ; preds = %35, %34, %33, %32
  br label %38

37:                                               ; preds = %27
  store i32 31, ptr %7, align 4, !tbaa !5
  br label %38

38:                                               ; preds = %37, %36
  br label %39

39:                                               ; preds = %38, %26
  br label %40

40:                                               ; preds = %39, %3
  %41 = load i32, ptr %8, align 4, !tbaa !5
  %42 = load i32, ptr %7, align 4, !tbaa !5
  %43 = add i32 %41, %42
  store i32 %43, ptr %7, align 4, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  ret i32 %44
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@switch.table._ZN3qpl7core_sw10dispatcher19get_pack_bits_indexEjjj = private unnamed_addr constant [3 x i32] [i32 7, i32 32, i32 33], align 4

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local noundef i32 @_ZN3qpl7core_sw10dispatcher19get_pack_bits_indexEjjj(i32 noundef %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 {
  %4 = add i32 %1, -1
  %.not12 = icmp eq i32 %2, 0
  br i1 %.not12, label %15, label %5

5:                                                ; preds = %3
  %6 = icmp ult i32 %1, 9
  br i1 %6, label %7, label %9

7:                                                ; preds = %5
  %8 = icmp ult i32 %2, 4
  br i1 %8, label %switch.lookup, label %15

9:                                                ; preds = %5
  %10 = icmp ult i32 %1, 17
  br i1 %10, label %11, label %15

11:                                               ; preds = %9
  switch i32 %2, label %15 [
    i32 3, label %13
    i32 2, label %12
  ]

12:                                               ; preds = %11
  br label %15

13:                                               ; preds = %11
  br label %15

switch.lookup:                                    ; preds = %7
  %switch.tableidx = add nsw i32 %2, -1
  %14 = sext i32 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [3 x i32], ptr @switch.table._ZN3qpl7core_sw10dispatcher19get_pack_bits_indexEjjj, i64 0, i64 %14
  %switch.load = load i32, ptr %switch.gep, align 4
  br label %15

15:                                               ; preds = %switch.lookup, %7, %9, %12, %13, %11, %3
  %.0 = phi i32 [ %4, %7 ], [ %4, %11 ], [ 15, %12 ], [ 34, %13 ], [ %4, %3 ], [ 31, %9 ], [ %switch.load, %switch.lookup ]
  %.not = icmp eq i32 %0, 0
  %16 = select i1 %.not, i32 0, i32 35
  %17 = add i32 %.0, %16
  ret i32 %17
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass