; LLVM IR from fast-pack/SIMDCompressionAndIntersection :: src/simdbitpacking.ll/ZN18SIMDCompressionLib16 (SIMD_fastpack8EPKjPDv2_x)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef, i32 noundef) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef, <2 x i64> noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: alwaysinline mustprogress uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef) #2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18SIMDCompressionLib16__SIMD_fastpack8EPKjPDv2_x(ptr noalias noundef %0, ptr noalias noundef %1) #3 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca <2 x i64>, align 16
  %7 = alloca <2 x i64>, align 16
  %8 = alloca <2 x i64>, align 16
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  %10 = load ptr, ptr %3, align 8, !tbaa !5
  store ptr %10, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %7) #4
  call void @llvm.lifetime.start.p0(i64 16, ptr %8) #4
  %11 = call noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef 255)
  store <2 x i64> %11, ptr %8, align 16, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #4
  store i32 0, ptr %9, align 4, !tbaa !10
  br label %12

12:                                               ; preds = %55, %2
  %13 = load i32, ptr %9, align 4, !tbaa !10
  %14 = icmp ult i32 %13, 8
  br i1 %14, label %16, label %15

15:                                               ; preds = %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #4
  br label %58

16:                                               ; preds = %12
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  %18 = call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %17)
  %19 = load <2 x i64>, ptr %8, align 16, !tbaa !9
  %20 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %18, <2 x i64> noundef %19)
  store <2 x i64> %20, ptr %7, align 16, !tbaa !9
  %21 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  store <2 x i64> %21, ptr %6, align 16, !tbaa !9
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = getelementptr inbounds <2 x i64>, ptr %22, i64 1
  %24 = call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %23)
  %25 = load <2 x i64>, ptr %8, align 16, !tbaa !9
  %26 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %24, <2 x i64> noundef %25)
  store <2 x i64> %26, ptr %7, align 16, !tbaa !9
  %27 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  %28 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  %29 = call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %28, i32 noundef 8)
  %30 = call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %27, <2 x i64> noundef %29)
  store <2 x i64> %30, ptr %6, align 16, !tbaa !9
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds <2 x i64>, ptr %31, i64 2
  %33 = call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %32)
  %34 = load <2 x i64>, ptr %8, align 16, !tbaa !9
  %35 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %33, <2 x i64> noundef %34)
  store <2 x i64> %35, ptr %7, align 16, !tbaa !9
  %36 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  %37 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  %38 = call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %37, i32 noundef 16)
  %39 = call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %36, <2 x i64> noundef %38)
  store <2 x i64> %39, ptr %6, align 16, !tbaa !9
  %40 = load ptr, ptr %5, align 8, !tbaa !5
  %41 = getelementptr inbounds <2 x i64>, ptr %40, i64 3
  %42 = call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %41)
  %43 = load <2 x i64>, ptr %8, align 16, !tbaa !9
  %44 = call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %42, <2 x i64> noundef %43)
  store <2 x i64> %44, ptr %7, align 16, !tbaa !9
  %45 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  %46 = load <2 x i64>, ptr %7, align 16, !tbaa !9
  %47 = call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %46, i32 noundef 24)
  %48 = call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %45, <2 x i64> noundef %47)
  store <2 x i64> %48, ptr %6, align 16, !tbaa !9
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = load <2 x i64>, ptr %6, align 16, !tbaa !9
  call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %49, <2 x i64> noundef %50)
  %51 = load ptr, ptr %4, align 8, !tbaa !5
  %52 = getelementptr inbounds <2 x i64>, ptr %51, i32 1
  store ptr %52, ptr %4, align 8, !tbaa !5
  %53 = load ptr, ptr %5, align 8, !tbaa !5
  %54 = getelementptr inbounds <2 x i64>, ptr %53, i64 4
  store ptr %54, ptr %5, align 8, !tbaa !5
  br label %55

55:                                               ; preds = %16
  %56 = load i32, ptr %9, align 4, !tbaa !10
  %57 = add i32 %56, 1
  store i32 %57, ptr %9, align 4, !tbaa !10
  br label %12, !llvm.loop !12

58:                                               ; preds = %15
  call void @llvm.lifetime.end.p0(i64 16, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 16, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef, <2 x i64> noundef) local_unnamed_addr #0

; Function Attrs: alwaysinline mustprogress uwtable
declare hidden noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef) local_unnamed_addr #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare hidden noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef, <2 x i64> noundef) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN18SIMDCompressionLib16__SIMD_fastpack8EPKjPDv2_x(ptr noalias noundef %0, ptr noalias noundef %1) local_unnamed_addr #2 {
  %3 = tail call noundef <2 x i64> @_ZL14_mm_set1_epi32i(i32 noundef 255)
  br label %5

4:                                                ; preds = %5
  ret void

5:                                                ; preds = %2, %5
  %.025 = phi i32 [ 0, %2 ], [ %25, %5 ]
  %.02124 = phi ptr [ %1, %2 ], [ %23, %5 ]
  %.02223 = phi ptr [ %0, %2 ], [ %24, %5 ]
  %6 = tail call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef %.02223)
  %7 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %6, <2 x i64> noundef %3)
  %8 = getelementptr inbounds i8, ptr %.02223, i64 16
  %9 = tail call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef nonnull %8)
  %10 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %9, <2 x i64> noundef %3)
  %11 = tail call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %10, i32 noundef 8)
  %12 = tail call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %7, <2 x i64> noundef %11)
  %13 = getelementptr inbounds i8, ptr %.02223, i64 32
  %14 = tail call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef nonnull %13)
  %15 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %14, <2 x i64> noundef %3)
  %16 = tail call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %15, i32 noundef 16)
  %17 = tail call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %12, <2 x i64> noundef %16)
  %18 = getelementptr inbounds i8, ptr %.02223, i64 48
  %19 = tail call noundef <2 x i64> @_ZL15_mm_loadu_si128PKDv2_x(ptr noundef nonnull %18)
  %20 = tail call noundef <2 x i64> @_ZL13_mm_and_si128Dv2_xS_(<2 x i64> noundef %19, <2 x i64> noundef %3)
  %21 = tail call noundef <2 x i64> @_ZL14_mm_slli_epi32Dv2_xi(<2 x i64> noundef %20, i32 noundef 24)
  %22 = tail call noundef <2 x i64> @_ZL12_mm_or_si128Dv2_xS_(<2 x i64> noundef %17, <2 x i64> noundef %21)
  tail call void @_ZL16_mm_storeu_si128PDv2_xS_(ptr noundef %.02124, <2 x i64> noundef %22)
  %23 = getelementptr inbounds i8, ptr %.02124, i64 16
  %24 = getelementptr inbounds i8, ptr %.02223, i64 64
  %25 = add nuw nsw i32 %.025, 1
  %exitcond.not = icmp eq i32 %25, 8
  br i1 %exitcond.not, label %4, label %5, !llvm.loop !5
}

attributes #0 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { alwaysinline mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass