; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_sem)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }

@OSIntNesting = external global i8, align 1
@OSEventFreeList = external global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSSemCreate(i16 noundef zeroext %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i16, align 2
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i16 %0, ptr %3, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  %7 = load i8, ptr @OSIntNesting, align 1, !tbaa !11
  %8 = zext i8 %7 to i32
  %9 = icmp ugt i32 %8, 0
  br i1 %9, label %10, label %11

10:                                               ; preds = %1
  store ptr null, ptr %2, align 8
  store i32 1, ptr %6, align 4
  br label %35

11:                                               ; preds = %1
  %12 = call i32 @OS_CPU_SR_Save()
  store i32 %12, ptr %5, align 4, !tbaa !9
  %13 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !12
  store ptr %13, ptr %4, align 8, !tbaa !12
  %14 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !12
  %15 = icmp ne ptr %14, null
  br i1 %15, label %16, label %20

16:                                               ; preds = %11
  %17 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !12
  %18 = getelementptr inbounds %struct.os_event, ptr %17, i32 0, i32 1
  %19 = load ptr, ptr %18, align 8, !tbaa !14
  store ptr %19, ptr @OSEventFreeList, align 8, !tbaa !12
  br label %20

20:                                               ; preds = %16, %11
  %21 = load i32, ptr %5, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %21)
  %22 = load ptr, ptr %4, align 8, !tbaa !12
  %23 = icmp ne ptr %22, null
  br i1 %23, label %24, label %33

24:                                               ; preds = %20
  %25 = load ptr, ptr %4, align 8, !tbaa !12
  %26 = getelementptr inbounds %struct.os_event, ptr %25, i32 0, i32 0
  store i8 3, ptr %26, align 8, !tbaa !16
  %27 = load i16, ptr %3, align 2, !tbaa !5
  %28 = load ptr, ptr %4, align 8, !tbaa !12
  %29 = getelementptr inbounds %struct.os_event, ptr %28, i32 0, i32 2
  store i16 %27, ptr %29, align 8, !tbaa !17
  %30 = load ptr, ptr %4, align 8, !tbaa !12
  %31 = getelementptr inbounds %struct.os_event, ptr %30, i32 0, i32 1
  store ptr null, ptr %31, align 8, !tbaa !14
  %32 = load ptr, ptr %4, align 8, !tbaa !12
  call void @OS_EventWaitListInit(ptr noundef %32)
  br label %33

33:                                               ; preds = %24, %20
  %34 = load ptr, ptr %4, align 8, !tbaa !12
  store ptr %34, ptr %2, align 8
  store i32 1, ptr %6, align 4
  br label %35

35:                                               ; preds = %33, %10
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #3
  %36 = load ptr, ptr %2, align 8
  ret ptr %36
}

declare void @OS_EventWaitListInit(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!15, !13, i64 8}
!15 = !{!"os_event", !7, i64 0, !13, i64 8, !6, i64 16, !7, i64 18, !7, i64 19}
!16 = !{!15, !7, i64 0}
!17 = !{!15, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSEventFreeList = external local_unnamed_addr global ptr, align 8

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSSemCreate(i16 noundef zeroext %0) local_unnamed_addr #1 {
  %2 = load i8, ptr @OSIntNesting, align 1, !tbaa !5
  %.not = icmp eq i8 %2, 0
  br i1 %.not, label %3, label %10

3:                                                ; preds = %1
  %4 = tail call i32 @OS_CPU_SR_Save() #2
  %5 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !8
  %.not9 = icmp eq ptr %5, null
  br i1 %.not9, label %.critedge, label %6

6:                                                ; preds = %3
  %7 = getelementptr inbounds i8, ptr %5, i64 8
  %8 = load ptr, ptr %7, align 8, !tbaa !10
  store ptr %8, ptr @OSEventFreeList, align 8, !tbaa !8
  tail call void @OS_CPU_SR_Restore(i32 noundef %4) #2
  store i8 3, ptr %5, align 8, !tbaa !13
  %9 = getelementptr inbounds i8, ptr %5, i64 16
  store i16 %0, ptr %9, align 8, !tbaa !14
  store ptr null, ptr %7, align 8, !tbaa !10
  tail call void @OS_EventWaitListInit(ptr noundef nonnull %5) #2
  br label %10

.critedge:                                        ; preds = %3
  tail call void @OS_CPU_SR_Restore(i32 noundef %4) #2
  br label %10

10:                                               ; preds = %6, %.critedge, %1
  %.0 = phi ptr [ null, %1 ], [ null, %.critedge ], [ %5, %6 ]
  ret ptr %.0
}

declare void @OS_EventWaitListInit(ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !9, i64 8}
!11 = !{!"os_event", !6, i64 0, !9, i64 8, !12, i64 16, !6, i64 18, !6, i64 19}
!12 = !{!"short", !6, i64 0}
!13 = !{!11, !6, i64 0}
!14 = !{!11, !12, i64 16}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass