; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_mutex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }
%struct.os_tcb = type { ptr, ptr, ptr, i32, i16, i16, ptr, ptr, ptr, ptr, ptr, i16, i32, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, ptr, i32, ptr, [1 x i32] }

@OSIntNesting = external global i8, align 1
@OSTCBCur = external global ptr, align 8

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @OSMutexAccept(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca i8, align 1
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.os_event, ptr %9, i32 0, i32 0
  %11 = load i8, ptr %10, align 8, !tbaa !11
  %12 = zext i8 %11 to i32
  %13 = icmp ne i32 %12, 4
  br i1 %13, label %14, label %16

14:                                               ; preds = %2
  %15 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 1, ptr %15, align 1, !tbaa !14
  store i8 0, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %73

16:                                               ; preds = %2
  %17 = load i8, ptr @OSIntNesting, align 1, !tbaa !14
  %18 = zext i8 %17 to i32
  %19 = icmp ugt i32 %18, 0
  br i1 %19, label %20, label %22

20:                                               ; preds = %16
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 2, ptr %21, align 1, !tbaa !14
  store i8 0, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %73

22:                                               ; preds = %16
  %23 = call i32 @OS_CPU_SR_Save()
  store i32 %23, ptr %7, align 4, !tbaa !9
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.os_event, ptr %24, i32 0, i32 2
  %26 = load i16, ptr %25, align 8, !tbaa !15
  %27 = zext i16 %26 to i32
  %28 = ashr i32 %27, 8
  %29 = trunc i32 %28 to i8
  store i8 %29, ptr %6, align 1, !tbaa !14
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.os_event, ptr %30, i32 0, i32 2
  %32 = load i16, ptr %31, align 8, !tbaa !15
  %33 = zext i16 %32 to i32
  %34 = and i32 %33, 255
  %35 = icmp eq i32 %34, 255
  br i1 %35, label %36, label %70

36:                                               ; preds = %22
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.os_event, ptr %37, i32 0, i32 2
  %39 = load i16, ptr %38, align 8, !tbaa !15
  %40 = zext i16 %39 to i32
  %41 = and i32 %40, 65280
  %42 = trunc i32 %41 to i16
  store i16 %42, ptr %38, align 8, !tbaa !15
  %43 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.os_tcb, ptr %43, i32 0, i32 15
  %45 = load i8, ptr %44, align 2, !tbaa !16
  %46 = zext i8 %45 to i32
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.os_event, ptr %47, i32 0, i32 2
  %49 = load i16, ptr %48, align 8, !tbaa !15
  %50 = zext i16 %49 to i32
  %51 = or i32 %50, %46
  %52 = trunc i32 %51 to i16
  store i16 %52, ptr %48, align 8, !tbaa !15
  %53 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.os_event, ptr %54, i32 0, i32 1
  store ptr %53, ptr %55, align 8, !tbaa !18
  %56 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %57 = getelementptr inbounds %struct.os_tcb, ptr %56, i32 0, i32 15
  %58 = load i8, ptr %57, align 2, !tbaa !16
  %59 = zext i8 %58 to i32
  %60 = load i8, ptr %6, align 1, !tbaa !14
  %61 = zext i8 %60 to i32
  %62 = icmp sle i32 %59, %61
  br i1 %62, label %63, label %66

63:                                               ; preds = %36
  %64 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %64)
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 120, ptr %65, align 1, !tbaa !14
  br label %69

66:                                               ; preds = %36
  %67 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %67)
  %68 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 0, ptr %68, align 1, !tbaa !14
  br label %69

69:                                               ; preds = %66, %63
  store i8 1, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %73

70:                                               ; preds = %22
  %71 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %71)
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  store i8 0, ptr %72, align 1, !tbaa !14
  store i8 0, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %73

73:                                               ; preds = %70, %69, %20, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %6) #3
  %74 = load i8, ptr %3, align 1
  ret i8 %74
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @OS_CPU_SR_Save() #2

declare void @OS_CPU_SR_Restore(i32 noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 0}
!12 = !{!"os_event", !7, i64 0, !6, i64 8, !13, i64 16, !7, i64 18, !7, i64 19}
!13 = !{!"short", !7, i64 0}
!14 = !{!7, !7, i64 0}
!15 = !{!12, !13, i64 16}
!16 = !{!17, !7, i64 82}
!17 = !{!"os_tcb", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !13, i64 28, !13, i64 30, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !13, i64 72, !10, i64 76, !7, i64 80, !7, i64 81, !7, i64 82, !7, i64 83, !7, i64 84, !7, i64 85, !7, i64 86, !7, i64 87, !10, i64 88, !10, i64 92, !10, i64 96, !6, i64 104, !10, i64 112, !6, i64 120, !7, i64 128}
!18 = !{!12, !6, i64 8}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSTCBCur = external local_unnamed_addr global ptr, align 8

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 2) i8 @OSMutexAccept(ptr nocapture noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #0 {
  %3 = load i8, ptr %0, align 8, !tbaa !5
  %.not = icmp eq i8 %3, 4
  br i1 %.not, label %4, label %22

4:                                                ; preds = %2
  %5 = load i8, ptr @OSIntNesting, align 1, !tbaa !11
  %.not15 = icmp eq i8 %5, 0
  br i1 %.not15, label %6, label %22

6:                                                ; preds = %4
  %7 = tail call i32 @OS_CPU_SR_Save() #2
  %8 = getelementptr inbounds i8, ptr %0, i64 16
  %9 = load i16, ptr %8, align 8, !tbaa !12
  %10 = and i16 %9, 255
  %11 = icmp eq i16 %10, 255
  br i1 %11, label %12, label %21

12:                                               ; preds = %6
  %13 = lshr i16 %9, 8
  %14 = and i16 %9, -256
  %15 = load ptr, ptr @OSTCBCur, align 8, !tbaa !13
  %16 = getelementptr inbounds i8, ptr %15, i64 82
  %17 = load i8, ptr %16, align 2, !tbaa !14
  %18 = zext i8 %17 to i16
  %19 = or disjoint i16 %14, %18
  store i16 %19, ptr %8, align 8, !tbaa !12
  %20 = getelementptr inbounds i8, ptr %0, i64 8
  store ptr %15, ptr %20, align 8, !tbaa !17
  %.not16 = icmp ult i16 %13, %18
  tail call void @OS_CPU_SR_Restore(i32 noundef %7) #2
  %. = select i1 %.not16, i8 0, i8 120
  br label %22

21:                                               ; preds = %6
  tail call void @OS_CPU_SR_Restore(i32 noundef %7) #2
  br label %22

22:                                               ; preds = %4, %2, %21, %12
  %.sink = phi i8 [ 0, %21 ], [ %., %12 ], [ 1, %2 ], [ 2, %4 ]
  %.0 = phi i8 [ 0, %21 ], [ 1, %12 ], [ 0, %2 ], [ 0, %4 ]
  store i8 %.sink, ptr %1, align 1, !tbaa !11
  ret i8 %.0
}

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #1

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"os_event", !7, i64 0, !9, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"any pointer", !7, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !10, i64 16}
!13 = !{!9, !9, i64 0}
!14 = !{!15, !7, i64 82}
!15 = !{!"os_tcb", !9, i64 0, !9, i64 8, !9, i64 16, !16, i64 24, !10, i64 28, !10, i64 30, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !9, i64 64, !10, i64 72, !16, i64 76, !7, i64 80, !7, i64 81, !7, i64 82, !7, i64 83, !7, i64 84, !7, i64 85, !7, i64 86, !7, i64 87, !16, i64 88, !16, i64 92, !16, i64 96, !9, i64 104, !16, i64 112, !9, i64 120, !7, i64 128}
!16 = !{!"int", !7, i64 0}
!17 = !{!6, !9, i64 8}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass