; LLVM IR from PaddlePaddle/Paddle :: paddle/phi/backends/cpu/cpu_info.ll (ZN3phi8backends3cpu7MayIUseENS1_9cpu_isa_tE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::array" = type { [4 x i32] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN3phi8backends3cpu7MayIUseENS1_9cpu_isa_tE(i32 noundef %0) #1 {
  %2 = alloca i1, align 1
  %3 = alloca i32, align 4
  %4 = alloca %"struct.std::array", align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  %15 = load i32, ptr %3, align 4, !tbaa !5
  %16 = icmp eq i32 %15, 0
  br i1 %16, label %17, label %18

17:                                               ; preds = %1
  store i1 true, ptr %2, align 1
  br label %101

18:                                               ; preds = %1
  call void @llvm.lifetime.start.p0(i64 16, ptr %4) #5
  %19 = call noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16) %4) #6
  call void @_Z5cpuidPii(ptr noundef %19, i32 noundef 0)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 0) #5
  %21 = load i32, ptr %20, align 4, !tbaa !9
  store i32 %21, ptr %5, align 4, !tbaa !9
  %22 = load i32, ptr %5, align 4, !tbaa !9
  %23 = icmp sge i32 %22, 1
  br i1 %23, label %24, label %35

24:                                               ; preds = %18
  %25 = call noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16) %4) #6
  call void @_Z5cpuidPii(ptr noundef %25, i32 noundef 1)
  %26 = load i32, ptr %3, align 4, !tbaa !5
  %27 = icmp eq i32 %26, 2
  br i1 %27, label %28, label %34

28:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  store i32 268435456, ptr %6, align 4, !tbaa !9
  %29 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 2) #5
  %30 = load i32, ptr %29, align 4, !tbaa !9
  %31 = load i32, ptr %6, align 4, !tbaa !9
  %32 = and i32 %30, %31
  %33 = icmp ne i32 %32, 0
  store i1 %33, ptr %2, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  br label %100

34:                                               ; preds = %24
  br label %35

35:                                               ; preds = %34, %18
  %36 = load i32, ptr %5, align 4, !tbaa !9
  %37 = icmp sge i32 %36, 7
  br i1 %37, label %38, label %99

38:                                               ; preds = %35
  %39 = call noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16) %4) #6
  call void @_Z5cpuidPii(ptr noundef %39, i32 noundef 7)
  %40 = load i32, ptr %3, align 4, !tbaa !5
  %41 = icmp eq i32 %40, 3
  br i1 %41, label %42, label %48

42:                                               ; preds = %38
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  store i32 32, ptr %8, align 4, !tbaa !9
  %43 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %44 = load i32, ptr %43, align 4, !tbaa !9
  %45 = load i32, ptr %8, align 4, !tbaa !9
  %46 = and i32 %44, %45
  %47 = icmp ne i32 %46, 0
  store i1 %47, ptr %2, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  br label %100

48:                                               ; preds = %38
  %49 = load i32, ptr %3, align 4, !tbaa !5
  %50 = icmp eq i32 %49, 4
  br i1 %50, label %51, label %57

51:                                               ; preds = %48
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 65536, ptr %9, align 4, !tbaa !9
  %52 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %53 = load i32, ptr %52, align 4, !tbaa !9
  %54 = load i32, ptr %9, align 4, !tbaa !9
  %55 = and i32 %53, %54
  %56 = icmp ne i32 %55, 0
  store i1 %56, ptr %2, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %100

57:                                               ; preds = %48
  %58 = load i32, ptr %3, align 4, !tbaa !5
  %59 = icmp eq i32 %58, 5
  br i1 %59, label %60, label %86

60:                                               ; preds = %57
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  store i32 65536, ptr %10, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #5
  store i32 131072, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  store i32 1073741824, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  store i32 -2147483648, ptr %13, align 4, !tbaa !9
  %61 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %62 = load i32, ptr %61, align 4, !tbaa !9
  %63 = load i32, ptr %10, align 4, !tbaa !9
  %64 = and i32 %62, %63
  %65 = icmp ne i32 %64, 0
  br i1 %65, label %66, label %84

66:                                               ; preds = %60
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %68 = load i32, ptr %67, align 4, !tbaa !9
  %69 = load i32, ptr %11, align 4, !tbaa !9
  %70 = and i32 %68, %69
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %84

72:                                               ; preds = %66
  %73 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %74 = load i32, ptr %73, align 4, !tbaa !9
  %75 = load i32, ptr %12, align 4, !tbaa !9
  %76 = and i32 %74, %75
  %77 = icmp ne i32 %76, 0
  br i1 %77, label %78, label %84

78:                                               ; preds = %72
  %79 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 1) #5
  %80 = load i32, ptr %79, align 4, !tbaa !9
  %81 = load i32, ptr %13, align 4, !tbaa !9
  %82 = and i32 %80, %81
  %83 = icmp ne i32 %82, 0
  br label %84

84:                                               ; preds = %78, %72, %66, %60
  %85 = phi i1 [ false, %72 ], [ false, %66 ], [ false, %60 ], [ %83, %78 ]
  store i1 %85, ptr %2, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  br label %100

86:                                               ; preds = %57
  br label %87

87:                                               ; preds = %86
  br label %88

88:                                               ; preds = %87
  %89 = call noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16) %4) #6
  call void @_Z5cpuidPii(ptr noundef %89, i32 noundef 65543)
  %90 = load i32, ptr %3, align 4, !tbaa !5
  %91 = icmp eq i32 %90, 9
  br i1 %91, label %92, label %98

92:                                               ; preds = %88
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #5
  store i32 32, ptr %14, align 4, !tbaa !9
  %93 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %4, i64 noundef 0) #5
  %94 = load i32, ptr %93, align 4, !tbaa !9
  %95 = load i32, ptr %14, align 4, !tbaa !9
  %96 = and i32 %94, %95
  %97 = icmp ne i32 %96, 0
  store i1 %97, ptr %2, align 1
  store i32 1, ptr %7, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #5
  br label %100

98:                                               ; preds = %88
  br label %99

99:                                               ; preds = %98, %35
  store i1 false, ptr %2, align 1
  store i32 1, ptr %7, align 4
  br label %100

100:                                              ; preds = %99, %92, %84, %51, %42, %28
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %4) #5
  br label %101

101:                                              ; preds = %100, %17
  %102 = load i1, ptr %2, align 1
  ret i1 %102
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z5cpuidPii(ptr noundef, i32 noundef) #2

; Function Attrs: mustprogress nounwind willreturn memory(none) uwtable
declare dso_local noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef) #4 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { nounwind willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"_ZTSN3phi8backends3cpu9cpu_isa_tE", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.std::array" = type { [4 x i32] }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN3phi8backends3cpu7MayIUseENS1_9cpu_isa_tE(i32 noundef %0) local_unnamed_addr #1 {
  %2 = alloca %"struct.std::array", align 4
  %3 = icmp eq i32 %0, 0
  br i1 %3, label %52, label %4

4:                                                ; preds = %1
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2) #4
  %5 = call noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16) %2) #5
  call void @_Z5cpuidPii(ptr noundef %5, i32 noundef 0)
  %6 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 0) #4
  %7 = load i32, ptr %6, align 4, !tbaa !5
  %8 = icmp sgt i32 %7, 0
  br i1 %8, label %9, label %.thread

9:                                                ; preds = %4
  call void @_Z5cpuidPii(ptr noundef %5, i32 noundef 1)
  %10 = icmp eq i32 %0, 2
  br i1 %10, label %11, label %16

11:                                               ; preds = %9
  %12 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 2) #4
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = and i32 %13, 268435456
  %15 = icmp ne i32 %14, 0
  br label %.thread

16:                                               ; preds = %9
  %17 = icmp ugt i32 %7, 6
  br i1 %17, label %18, label %.thread

18:                                               ; preds = %16
  call void @_Z5cpuidPii(ptr noundef %5, i32 noundef 7)
  switch i32 %0, label %45 [
    i32 3, label %19
    i32 4, label %24
    i32 5, label %29
  ]

19:                                               ; preds = %18
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = and i32 %21, 32
  %23 = icmp ne i32 %22, 0
  br label %.thread

24:                                               ; preds = %18
  %25 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %27 = and i32 %26, 65536
  %28 = icmp ne i32 %27, 0
  br label %.thread

29:                                               ; preds = %18
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %31 = load i32, ptr %30, align 4, !tbaa !5
  %32 = and i32 %31, 65536
  %.not = icmp eq i32 %32, 0
  br i1 %.not, label %.thread, label %33

33:                                               ; preds = %29
  %34 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %35 = load i32, ptr %34, align 4, !tbaa !5
  %36 = and i32 %35, 131072
  %.not17 = icmp eq i32 %36, 0
  br i1 %.not17, label %.thread, label %37

37:                                               ; preds = %33
  %38 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %39 = load i32, ptr %38, align 4, !tbaa !5
  %40 = and i32 %39, 1073741824
  %.not18 = icmp eq i32 %40, 0
  br i1 %.not18, label %.thread, label %41

41:                                               ; preds = %37
  %42 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 1) #4
  %43 = load i32, ptr %42, align 4, !tbaa !5
  %44 = icmp slt i32 %43, 0
  br label %.thread

45:                                               ; preds = %18
  call void @_Z5cpuidPii(ptr noundef %5, i32 noundef 65543)
  %46 = icmp eq i32 %0, 9
  br i1 %46, label %47, label %.thread

47:                                               ; preds = %45
  %48 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16) %2, i64 noundef 0) #4
  %49 = load i32, ptr %48, align 4, !tbaa !5
  %50 = and i32 %49, 32
  %51 = icmp ne i32 %50, 0
  br label %.thread

.thread:                                          ; preds = %4, %16, %45, %29, %33, %37, %41, %47, %24, %19, %11
  %.0 = phi i1 [ %15, %11 ], [ %23, %19 ], [ %28, %24 ], [ %51, %47 ], [ false, %37 ], [ false, %33 ], [ false, %29 ], [ %44, %41 ], [ false, %45 ], [ false, %16 ], [ false, %4 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %2) #4
  br label %52

52:                                               ; preds = %1, %.thread
  %.1 = phi i1 [ %.0, %.thread ], [ true, %1 ]
  ret i1 %.1
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z5cpuidPii(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none) uwtable
declare dso_local noundef ptr @_ZNSt5arrayIiLm4EE4dataEv(ptr noundef nonnull align 4 dereferenceable(16)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt5arrayIiLm4EEixEm(ptr noundef nonnull align 4 dereferenceable(16), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nofree nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { nounwind willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass