; LLVM IR from ADJA/algos :: DataStructures/CartesianTreeImplicitKeys.ll (Z5mergeRP4nodeS0_S0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.node = type { i32, i32, i32, i32, i8, ptr, ptr }

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6updateP4node(ptr noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4pushP4node(ptr noundef) #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5mergeRP4nodeS0_S0_(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1, ptr noundef %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  %7 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_Z4pushP4node(ptr noundef %7)
  %8 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_Z4pushP4node(ptr noundef %8)
  %9 = load ptr, ptr %5, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %11, label %14

11:                                               ; preds = %3
  %12 = load ptr, ptr %6, align 8, !tbaa !5
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %12, ptr %13, align 8, !tbaa !5
  br label %48

14:                                               ; preds = %3
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = icmp eq ptr %15, null
  br i1 %16, label %17, label %20

17:                                               ; preds = %14
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %18, ptr %19, align 8, !tbaa !5
  br label %47

20:                                               ; preds = %14
  %21 = load ptr, ptr %5, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.node, ptr %21, i32 0, i32 0
  %23 = load i32, ptr %22, align 8, !tbaa !9
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.node, ptr %24, i32 0, i32 0
  %26 = load i32, ptr %25, align 8, !tbaa !9
  %27 = icmp sgt i32 %23, %26
  br i1 %27, label %28, label %37

28:                                               ; preds = %20
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.node, ptr %29, i32 0, i32 6
  %31 = load ptr, ptr %5, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.node, ptr %31, i32 0, i32 6
  %33 = load ptr, ptr %32, align 8, !tbaa !13
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_Z5mergeRP4nodeS0_S0_(ptr noundef nonnull align 8 dereferenceable(8) %30, ptr noundef %33, ptr noundef %34)
  %35 = load ptr, ptr %5, align 8, !tbaa !5
  %36 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %35, ptr %36, align 8, !tbaa !5
  br label %46

37:                                               ; preds = %20
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.node, ptr %38, i32 0, i32 5
  %40 = load ptr, ptr %5, align 8, !tbaa !5
  %41 = load ptr, ptr %6, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.node, ptr %41, i32 0, i32 5
  %43 = load ptr, ptr %42, align 8, !tbaa !14
  call void @_Z5mergeRP4nodeS0_S0_(ptr noundef nonnull align 8 dereferenceable(8) %39, ptr noundef %40, ptr noundef %43)
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %44, ptr %45, align 8, !tbaa !5
  br label %46

46:                                               ; preds = %37, %28
  br label %47

47:                                               ; preds = %46, %17
  br label %48

48:                                               ; preds = %47, %11
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = load ptr, ptr %49, align 8, !tbaa !5
  call void @_Z6updateP4node(ptr noundef %50)
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS4node", !11, i64 0, !11, i64 4, !11, i64 8, !11, i64 12, !12, i64 16, !6, i64 24, !6, i64 32}
!11 = !{!"int", !7, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{!10, !6, i64 32}
!14 = !{!10, !6, i64 24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z6updateP4node(ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4pushP4node(ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5mergeRP4nodeS0_S0_(ptr nocapture noundef nonnull writeonly align 8 dereferenceable(8) %0, ptr noundef %1, ptr noundef %2) local_unnamed_addr #0 {
  tail call void @_Z4pushP4node(ptr noundef %1)
  tail call void @_Z4pushP4node(ptr noundef %2)
  %4 = icmp eq ptr %1, null
  br i1 %4, label %17, label %5

5:                                                ; preds = %3
  %6 = icmp eq ptr %2, null
  br i1 %6, label %17, label %7

7:                                                ; preds = %5
  %8 = load i32, ptr %1, align 8, !tbaa !5
  %9 = load i32, ptr %2, align 8, !tbaa !5
  %10 = icmp sgt i32 %8, %9
  br i1 %10, label %11, label %14

11:                                               ; preds = %7
  %12 = getelementptr inbounds i8, ptr %1, i64 32
  %13 = load ptr, ptr %12, align 8, !tbaa !12
  tail call void @_Z5mergeRP4nodeS0_S0_(ptr noundef nonnull align 8 dereferenceable(8) %12, ptr noundef %13, ptr noundef nonnull %2)
  br label %17

14:                                               ; preds = %7
  %15 = getelementptr inbounds i8, ptr %2, i64 24
  %16 = load ptr, ptr %15, align 8, !tbaa !13
  tail call void @_Z5mergeRP4nodeS0_S0_(ptr noundef nonnull align 8 dereferenceable(8) %15, ptr noundef nonnull %1, ptr noundef %16)
  br label %17

17:                                               ; preds = %5, %3, %14, %11
  %.sink = phi ptr [ %2, %14 ], [ %1, %11 ], [ %2, %3 ], [ %1, %5 ]
  store ptr %.sink, ptr %0, align 8, !tbaa !14
  tail call void @_Z6updateP4node(ptr noundef %.sink)
  ret void
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS4node", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !10, i64 16, !11, i64 24, !11, i64 32}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"bool", !8, i64 0}
!11 = !{!"any pointer", !8, i64 0}
!12 = !{!6, !11, i64 32}
!13 = !{!6, !11, i64 24}
!14 = !{!11, !11, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass