; LLVM IR from asllop/AppOS :: net/slip (slip)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @slip_recv(i8 noundef zeroext %0, ptr noundef %1, i32 noundef %2) #0 {
  %4 = alloca i8, align 1
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  store i8 %0, ptr %4, align 1, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !8
  store i32 %2, ptr %6, align 4, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !10
  br label %9

9:                                                ; preds = %41, %3
  br label %10

10:                                               ; preds = %9
  %11 = load i8, ptr %4, align 1, !tbaa !5
  %12 = call zeroext i8 @slip_serial_get(i8 noundef zeroext %11)
  store i8 %12, ptr %7, align 1, !tbaa !5
  %13 = load i8, ptr %7, align 1, !tbaa !5
  %14 = zext i8 %13 to i32
  switch i32 %14, label %29 [
    i32 192, label %15
    i32 219, label %21
  ]

15:                                               ; preds = %10
  %16 = load i32, ptr %8, align 4, !tbaa !10
  %17 = icmp ne i32 %16, 0
  br i1 %17, label %18, label %20

18:                                               ; preds = %15
  %19 = load i32, ptr %8, align 4, !tbaa !10
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  ret i32 %19

20:                                               ; preds = %15
  br label %41

21:                                               ; preds = %10
  %22 = load i8, ptr %4, align 1, !tbaa !5
  %23 = call zeroext i8 @slip_serial_get(i8 noundef zeroext %22)
  store i8 %23, ptr %7, align 1, !tbaa !5
  %24 = load i8, ptr %7, align 1, !tbaa !5
  %25 = zext i8 %24 to i32
  switch i32 %25, label %28 [
    i32 220, label %26
    i32 221, label %27
  ]

26:                                               ; preds = %21
  store i8 -64, ptr %7, align 1, !tbaa !5
  br label %28

27:                                               ; preds = %21
  store i8 -37, ptr %7, align 1, !tbaa !5
  br label %28

28:                                               ; preds = %27, %26, %21
  br label %29

29:                                               ; preds = %28, %10
  %30 = load i32, ptr %8, align 4, !tbaa !10
  %31 = load i32, ptr %6, align 4, !tbaa !10
  %32 = icmp slt i32 %30, %31
  br i1 %32, label %33, label %40

33:                                               ; preds = %29
  %34 = load i8, ptr %7, align 1, !tbaa !5
  %35 = load ptr, ptr %5, align 8, !tbaa !8
  %36 = load i32, ptr %8, align 4, !tbaa !10
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %8, align 4, !tbaa !10
  %38 = sext i32 %36 to i64
  %39 = getelementptr inbounds i8, ptr %35, i64 %38
  store i8 %34, ptr %39, align 1, !tbaa !5
  br label %40

40:                                               ; preds = %33, %29
  br label %41

41:                                               ; preds = %40, %20
  br label %9
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare zeroext i8 @slip_serial_get(i8 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local range(i32 1, 0) i32 @slip_recv(i8 noundef zeroext %0, ptr nocapture noundef writeonly %1, i32 noundef %2) local_unnamed_addr #0 {
  br label %.outer

.outer:                                           ; preds = %.outer.backedge, %3
  %.0.ph = phi i32 [ 0, %3 ], [ %.0.ph.be, %.outer.backedge ]
  %4 = icmp slt i32 %.0.ph, %2
  br label %5

5:                                                ; preds = %.outer, %13
  %6 = tail call zeroext i8 @slip_serial_get(i8 noundef zeroext %0) #2
  switch i8 %6, label %13 [
    i8 -64, label %7
    i8 -37, label %9
  ]

7:                                                ; preds = %5
  %.not = icmp eq i32 %.0.ph, 0
  br i1 %.not, label %.outer.backedge, label %8

8:                                                ; preds = %7
  ret i32 %.0.ph

9:                                                ; preds = %5
  %10 = tail call zeroext i8 @slip_serial_get(i8 noundef zeroext %0) #2
  switch i8 %10, label %13 [
    i8 -36, label %11
    i8 -35, label %12
  ]

11:                                               ; preds = %9
  br label %13

12:                                               ; preds = %9
  br label %13

13:                                               ; preds = %9, %11, %12, %5
  %.010 = phi i8 [ %6, %5 ], [ %10, %9 ], [ -37, %12 ], [ -64, %11 ]
  br i1 %4, label %14, label %5

14:                                               ; preds = %13
  %15 = add nsw i32 %.0.ph, 1
  %16 = sext i32 %.0.ph to i64
  %17 = getelementptr inbounds i8, ptr %1, i64 %16
  store i8 %.010, ptr %17, align 1, !tbaa !5
  br label %.outer.backedge

.outer.backedge:                                  ; preds = %14, %7
  %.0.ph.be = phi i32 [ 0, %7 ], [ %15, %14 ]
  br label %.outer
}

declare zeroext i8 @slip_serial_get(i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass