; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-III2/uC-CPU/ARM-Cortex-M3/GNU (cpu_c)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @CPU_SR_Save() #1

declare void @CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @CPU_IntSrcPendClr(i8 noundef zeroext %0) #2 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  store i8 %0, ptr %2, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !8
  %7 = load i8, ptr %2, align 1, !tbaa !5
  %8 = zext i8 %7 to i32
  switch i32 %8, label %11 [
    i32 0, label %9
    i32 7, label %9
    i32 8, label %9
    i32 9, label %9
    i32 10, label %9
    i32 13, label %9
    i32 1, label %10
    i32 2, label %10
    i32 3, label %10
    i32 4, label %10
    i32 11, label %10
    i32 12, label %10
    i32 14, label %10
    i32 5, label %10
    i32 6, label %10
    i32 15, label %10
  ]

9:                                                ; preds = %1, %1, %1, %1, %1, %1
  br label %58

10:                                               ; preds = %1, %1, %1, %1, %1, %1, %1, %1, %1, %1
  br label %58

11:                                               ; preds = %1
  %12 = load volatile i32, ptr inttoptr (i64 3758153732 to ptr), align 4, !tbaa !8
  %13 = add i32 %12, 1
  %14 = and i32 %13, 31
  %15 = mul i32 %14, 32
  %16 = add i32 %15, 16
  %17 = trunc i32 %16 to i8
  store i8 %17, ptr %5, align 1, !tbaa !5
  %18 = load i8, ptr %2, align 1, !tbaa !5
  %19 = zext i8 %18 to i32
  %20 = load i8, ptr %5, align 1, !tbaa !5
  %21 = zext i8 %20 to i32
  %22 = icmp slt i32 %19, %21
  br i1 %22, label %23, label %57

23:                                               ; preds = %11
  %24 = load i8, ptr %2, align 1, !tbaa !5
  %25 = zext i8 %24 to i32
  %26 = sub nsw i32 %25, 16
  %27 = sdiv i32 %26, 32
  %28 = trunc i32 %27 to i8
  store i8 %28, ptr %3, align 1, !tbaa !5
  %29 = load i8, ptr %2, align 1, !tbaa !5
  %30 = zext i8 %29 to i32
  %31 = sub nsw i32 %30, 16
  %32 = srem i32 %31, 32
  %33 = trunc i32 %32 to i8
  store i8 %33, ptr %4, align 1, !tbaa !5
  br label %34

34:                                               ; preds = %23
  br label %35

35:                                               ; preds = %34
  %36 = call i32 @CPU_SR_Save()
  store i32 %36, ptr %6, align 4, !tbaa !8
  br label %37

37:                                               ; preds = %35
  br label %38

38:                                               ; preds = %37
  br label %39

39:                                               ; preds = %38
  br label %40

40:                                               ; preds = %39
  %41 = load i8, ptr %4, align 1, !tbaa !5
  %42 = zext i8 %41 to i32
  %43 = shl i32 1, %42
  %44 = load i8, ptr %3, align 1, !tbaa !5
  %45 = zext i8 %44 to i32
  %46 = mul i32 %45, 4
  %47 = add i32 -536812928, %46
  %48 = zext i32 %47 to i64
  %49 = inttoptr i64 %48 to ptr
  store volatile i32 %43, ptr %49, align 4, !tbaa !8
  br label %50

50:                                               ; preds = %40
  br label %51

51:                                               ; preds = %50
  %52 = load i32, ptr %6, align 4, !tbaa !8
  call void @CPU_SR_Restore(i32 noundef %52)
  br label %53

53:                                               ; preds = %51
  br label %54

54:                                               ; preds = %53
  br label %55

55:                                               ; preds = %54
  br label %56

56:                                               ; preds = %55
  br label %57

57:                                               ; preds = %56, %11
  br label %58

58:                                               ; preds = %57, %10, %9
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @CPU_SR_Save() local_unnamed_addr #0

declare void @CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @CPU_IntSrcPendClr(i8 noundef zeroext %0) local_unnamed_addr #1 {
  %switch = icmp ult i8 %0, 16
  br i1 %switch, label %19, label %2

2:                                                ; preds = %1
  %3 = zext i8 %0 to i32
  %4 = load volatile i32, ptr inttoptr (i64 3758153732 to ptr), align 4, !tbaa !5
  %5 = shl i32 %4, 5
  %6 = add i32 %5, 48
  %7 = and i32 %6, 240
  %8 = icmp ugt i32 %7, %3
  br i1 %8, label %9, label %19

9:                                                ; preds = %2
  %10 = zext i8 %0 to i16
  %.lhs.trunc = add nsw i16 %10, -16
  %.zext12 = and i16 %.lhs.trunc, 31
  %11 = tail call i32 @CPU_SR_Save() #2
  %12 = zext nneg i16 %.zext12 to i32
  %13 = shl nuw i32 1, %12
  %14 = lshr i16 %.lhs.trunc, 3
  %15 = and i16 %14, 28
  %16 = zext nneg i16 %15 to i64
  %17 = or disjoint i64 %16, 3758154368
  %18 = inttoptr i64 %17 to ptr
  store volatile i32 %13, ptr %18, align 4, !tbaa !5
  tail call void @CPU_SR_Restore(i32 noundef %11) #2
  br label %19

19:                                               ; preds = %1, %2, %9
  ret void
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass