; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_q)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }
%struct.os_q = type { ptr, ptr, ptr, ptr, ptr, i16, i16 }

@OSIntNesting = external global i8, align 1
@OSEventFreeList = external global ptr, align 8
@OSQFreeList = external global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSQDel(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  store i32 0, ptr %11, align 4, !tbaa !10
  %13 = load ptr, ptr %5, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.os_event, ptr %13, i32 0, i32 0
  %15 = load i8, ptr %14, align 8, !tbaa !12
  %16 = zext i8 %15 to i32
  %17 = icmp ne i32 %16, 2
  br i1 %17, label %18, label %21

18:                                               ; preds = %3
  %19 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 1, ptr %19, align 1, !tbaa !9
  %20 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %20, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %106

21:                                               ; preds = %3
  %22 = load i8, ptr @OSIntNesting, align 1, !tbaa !9
  %23 = zext i8 %22 to i32
  %24 = icmp ugt i32 %23, 0
  br i1 %24, label %25, label %28

25:                                               ; preds = %21
  %26 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 15, ptr %26, align 1, !tbaa !9
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %27, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %106

28:                                               ; preds = %21
  %29 = call i32 @OS_CPU_SR_Save()
  store i32 %29, ptr %11, align 4, !tbaa !10
  %30 = load ptr, ptr %5, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.os_event, ptr %30, i32 0, i32 3
  %32 = load i8, ptr %31, align 2, !tbaa !15
  %33 = zext i8 %32 to i32
  %34 = icmp ne i32 %33, 0
  br i1 %34, label %35, label %36

35:                                               ; preds = %28
  store i8 1, ptr %8, align 1, !tbaa !9
  br label %37

36:                                               ; preds = %28
  store i8 0, ptr %8, align 1, !tbaa !9
  br label %37

37:                                               ; preds = %36, %35
  %38 = load i8, ptr %6, align 1, !tbaa !9
  %39 = zext i8 %38 to i32
  switch i32 %39, label %100 [
    i32 0, label %40
    i32 1, label %67
  ]

40:                                               ; preds = %37
  %41 = load i8, ptr %8, align 1, !tbaa !9
  %42 = zext i8 %41 to i32
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %62

44:                                               ; preds = %40
  %45 = load ptr, ptr %5, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.os_event, ptr %45, i32 0, i32 1
  %47 = load ptr, ptr %46, align 8, !tbaa !16
  store ptr %47, ptr %10, align 8, !tbaa !5
  %48 = load ptr, ptr @OSQFreeList, align 8, !tbaa !5
  %49 = load ptr, ptr %10, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.os_q, ptr %49, i32 0, i32 0
  store ptr %48, ptr %50, align 8, !tbaa !17
  %51 = load ptr, ptr %10, align 8, !tbaa !5
  store ptr %51, ptr @OSQFreeList, align 8, !tbaa !5
  %52 = load ptr, ptr %5, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.os_event, ptr %52, i32 0, i32 0
  store i8 0, ptr %53, align 8, !tbaa !12
  %54 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.os_event, ptr %55, i32 0, i32 1
  store ptr %54, ptr %56, align 8, !tbaa !16
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.os_event, ptr %57, i32 0, i32 2
  store i16 0, ptr %58, align 8, !tbaa !19
  %59 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %59, ptr @OSEventFreeList, align 8, !tbaa !5
  %60 = load i32, ptr %11, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %60)
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %61, align 1, !tbaa !9
  store ptr null, ptr %9, align 8, !tbaa !5
  br label %66

62:                                               ; preds = %40
  %63 = load i32, ptr %11, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %63)
  %64 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 73, ptr %64, align 1, !tbaa !9
  %65 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %65, ptr %9, align 8, !tbaa !5
  br label %66

66:                                               ; preds = %62, %44
  br label %104

67:                                               ; preds = %37
  br label %68

68:                                               ; preds = %74, %67
  %69 = load ptr, ptr %5, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.os_event, ptr %69, i32 0, i32 3
  %71 = load i8, ptr %70, align 2, !tbaa !15
  %72 = zext i8 %71 to i32
  %73 = icmp ne i32 %72, 0
  br i1 %73, label %74, label %77

74:                                               ; preds = %68
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = call zeroext i8 @OS_EventTaskRdy(ptr noundef %75, ptr noundef null, i8 noundef zeroext 4, i8 noundef zeroext 0)
  br label %68, !llvm.loop !20

77:                                               ; preds = %68
  %78 = load ptr, ptr %5, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.os_event, ptr %78, i32 0, i32 1
  %80 = load ptr, ptr %79, align 8, !tbaa !16
  store ptr %80, ptr %10, align 8, !tbaa !5
  %81 = load ptr, ptr @OSQFreeList, align 8, !tbaa !5
  %82 = load ptr, ptr %10, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.os_q, ptr %82, i32 0, i32 0
  store ptr %81, ptr %83, align 8, !tbaa !17
  %84 = load ptr, ptr %10, align 8, !tbaa !5
  store ptr %84, ptr @OSQFreeList, align 8, !tbaa !5
  %85 = load ptr, ptr %5, align 8, !tbaa !5
  %86 = getelementptr inbounds %struct.os_event, ptr %85, i32 0, i32 0
  store i8 0, ptr %86, align 8, !tbaa !12
  %87 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  %89 = getelementptr inbounds %struct.os_event, ptr %88, i32 0, i32 1
  store ptr %87, ptr %89, align 8, !tbaa !16
  %90 = load ptr, ptr %5, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.os_event, ptr %90, i32 0, i32 2
  store i16 0, ptr %91, align 8, !tbaa !19
  %92 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %92, ptr @OSEventFreeList, align 8, !tbaa !5
  %93 = load i32, ptr %11, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %93)
  %94 = load i8, ptr %8, align 1, !tbaa !9
  %95 = zext i8 %94 to i32
  %96 = icmp eq i32 %95, 1
  br i1 %96, label %97, label %98

97:                                               ; preds = %77
  call void @OS_Sched()
  br label %98

98:                                               ; preds = %97, %77
  %99 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %99, align 1, !tbaa !9
  store ptr null, ptr %9, align 8, !tbaa !5
  br label %104

100:                                              ; preds = %37
  %101 = load i32, ptr %11, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %101)
  %102 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 7, ptr %102, align 1, !tbaa !9
  %103 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %103, ptr %9, align 8, !tbaa !5
  br label %104

104:                                              ; preds = %100, %98, %66
  %105 = load ptr, ptr %9, align 8, !tbaa !5
  store ptr %105, ptr %4, align 8
  store i32 1, ptr %12, align 4
  br label %106

106:                                              ; preds = %104, %25, %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  %107 = load ptr, ptr %4, align 8
  ret ptr %107
}

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) #1

declare void @OS_Sched() #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !7, i64 0}
!13 = !{!"os_event", !7, i64 0, !6, i64 8, !14, i64 16, !7, i64 18, !7, i64 19}
!14 = !{!"short", !7, i64 0}
!15 = !{!13, !7, i64 18}
!16 = !{!13, !6, i64 8}
!17 = !{!18, !6, i64 0}
!18 = !{!"os_q", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !14, i64 40, !14, i64 42}
!19 = !{!13, !14, i64 16}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSEventFreeList = external local_unnamed_addr global ptr, align 8
@OSQFreeList = external local_unnamed_addr global ptr, align 8

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @OSQDel(ptr noundef %0, i8 noundef zeroext %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #1 {
  %4 = load i8, ptr %0, align 8, !tbaa !5
  %.not = icmp eq i8 %4, 2
  br i1 %.not, label %5, label %27

5:                                                ; preds = %3
  %6 = load i8, ptr @OSIntNesting, align 1, !tbaa !11
  %.not38 = icmp eq i8 %6, 0
  br i1 %.not38, label %7, label %27

7:                                                ; preds = %5
  %8 = tail call i32 @OS_CPU_SR_Save() #2
  %9 = getelementptr inbounds i8, ptr %0, i64 18
  %10 = load i8, ptr %9, align 2, !tbaa !12
  %.not39.not = icmp eq i8 %10, 0
  switch i8 %1, label %26 [
    i8 0, label %11
    i8 1, label %.preheader
  ]

.preheader:                                       ; preds = %7
  br i1 %.not39.not, label %._crit_edge, label %.lr.ph

11:                                               ; preds = %7
  br i1 %.not39.not, label %12, label %18

12:                                               ; preds = %11
  %13 = getelementptr inbounds i8, ptr %0, i64 8
  %14 = load ptr, ptr %13, align 8, !tbaa !13
  %15 = load ptr, ptr @OSQFreeList, align 8, !tbaa !14
  store ptr %15, ptr %14, align 8, !tbaa !15
  store ptr %14, ptr @OSQFreeList, align 8, !tbaa !14
  store i8 0, ptr %0, align 8, !tbaa !5
  %16 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !14
  store ptr %16, ptr %13, align 8, !tbaa !13
  %17 = getelementptr inbounds i8, ptr %0, i64 16
  store i16 0, ptr %17, align 8, !tbaa !17
  store ptr %0, ptr @OSEventFreeList, align 8, !tbaa !14
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %27

18:                                               ; preds = %11
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %27

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %19 = tail call zeroext i8 @OS_EventTaskRdy(ptr noundef nonnull %0, ptr noundef null, i8 noundef zeroext 4, i8 noundef zeroext 0) #2
  %.pr = load i8, ptr %9, align 2, !tbaa !12
  %.not40 = icmp eq i8 %.pr, 0
  br i1 %.not40, label %._crit_edge, label %.lr.ph, !llvm.loop !18

._crit_edge:                                      ; preds = %.lr.ph, %.preheader
  %20 = getelementptr inbounds i8, ptr %0, i64 8
  %21 = load ptr, ptr %20, align 8, !tbaa !13
  %22 = load ptr, ptr @OSQFreeList, align 8, !tbaa !14
  store ptr %22, ptr %21, align 8, !tbaa !15
  store ptr %21, ptr @OSQFreeList, align 8, !tbaa !14
  store i8 0, ptr %0, align 8, !tbaa !5
  %23 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !14
  store ptr %23, ptr %20, align 8, !tbaa !13
  %24 = getelementptr inbounds i8, ptr %0, i64 16
  store i16 0, ptr %24, align 8, !tbaa !17
  store ptr %0, ptr @OSEventFreeList, align 8, !tbaa !14
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br i1 %.not39.not, label %27, label %25

25:                                               ; preds = %._crit_edge
  tail call void @OS_Sched() #2
  br label %27

26:                                               ; preds = %7
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %27

27:                                               ; preds = %._crit_edge, %25, %5, %3, %26, %18, %12
  %.sink = phi i8 [ 7, %26 ], [ 73, %18 ], [ 0, %12 ], [ 1, %3 ], [ 15, %5 ], [ 0, %25 ], [ 0, %._crit_edge ]
  %.037 = phi ptr [ %0, %26 ], [ %0, %18 ], [ null, %12 ], [ %0, %3 ], [ %0, %5 ], [ null, %25 ], [ null, %._crit_edge ]
  store i8 %.sink, ptr %2, align 1, !tbaa !11
  ret ptr %.037
}

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

declare void @OS_Sched() local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"os_event", !7, i64 0, !9, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"any pointer", !7, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !7, i64 18}
!13 = !{!6, !9, i64 8}
!14 = !{!9, !9, i64 0}
!15 = !{!16, !9, i64 0}
!16 = !{!"os_q", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !10, i64 40, !10, i64 42}
!17 = !{!6, !10, i64 16}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass