; LLVM IR from ponylang/ponyc :: src/libponyrt/sched (cpu)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.scheduler_t = type { i64, i32, i32, i32, i8, i8, i32, i32, [32 x i8], ptr, %struct.pony_ctx_t, i32, i32, i32, %struct.mutemap_t, [56 x i8], %struct.mpmcq_t, %struct.messageq_t, [48 x i8] }
%struct.pony_ctx_t = type { ptr, ptr, ptr, ptr, ptr, %struct.actormap_t, ptr, i64, %struct.ponyint_serialise_t, ptr, ptr, ptr }
%struct.actormap_t = type { %struct.hashmap_t }
%struct.hashmap_t = type { i64, i64, ptr, ptr }
%struct.ponyint_serialise_t = type { %struct.hashmap_t }
%struct.mutemap_t = type { %struct.hashmap_t }
%struct.mpmcq_t = type { ptr, %union.aba_protected_mpmcq_node_t, [32 x i8] }
%union.aba_protected_mpmcq_node_t = type { i128 }
%struct.messageq_t = type { ptr, ptr }

@avail_cpu_count = external hidden global i32, align 4
@avail_cpu_size = external hidden global i32, align 4
@avail_cpu_list = external hidden global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @ponyint_cpu_assign(i32 noundef %0, ptr noundef %1, i1 noundef zeroext %2, i1 noundef zeroext %3, i1 noundef zeroext %4, i1 noundef zeroext %5, ptr noundef %6) #1 {
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i8, align 1
  %12 = alloca i8, align 1
  %13 = alloca i8, align 1
  %14 = alloca i8, align 1
  %15 = alloca ptr, align 8
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca i32, align 4
  store i32 %0, ptr %9, align 4, !tbaa !5
  store ptr %1, ptr %10, align 8, !tbaa !9
  %22 = zext i1 %2 to i8
  store i8 %22, ptr %11, align 1, !tbaa !11
  %23 = zext i1 %3 to i8
  store i8 %23, ptr %12, align 1, !tbaa !11
  %24 = zext i1 %4 to i8
  store i8 %24, ptr %13, align 1, !tbaa !11
  %25 = zext i1 %5 to i8
  store i8 %25, ptr %14, align 1, !tbaa !11
  store ptr %6, ptr %15, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #3
  store i32 -1, ptr %16, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #3
  store i32 -1, ptr %17, align 4, !tbaa !5
  %26 = load ptr, ptr %15, align 8, !tbaa !9
  store i32 -1, ptr %26, align 4, !tbaa !5
  %27 = load i8, ptr %11, align 1, !tbaa !11, !range !13, !noundef !14
  %28 = trunc i8 %27 to i1
  br i1 %28, label %51, label %29

29:                                               ; preds = %7
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #3
  store i32 0, ptr %18, align 4, !tbaa !5
  br label %30

30:                                               ; preds = %46, %29
  %31 = load i32, ptr %18, align 4, !tbaa !5
  %32 = load i32, ptr %9, align 4, !tbaa !5
  %33 = icmp ult i32 %31, %32
  br i1 %33, label %35, label %34

34:                                               ; preds = %30
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #3
  br label %49

35:                                               ; preds = %30
  %36 = load ptr, ptr %10, align 8, !tbaa !9
  %37 = load i32, ptr %18, align 4, !tbaa !5
  %38 = zext i32 %37 to i64
  %39 = getelementptr inbounds %struct.scheduler_t, ptr %36, i64 %38
  %40 = getelementptr inbounds %struct.scheduler_t, ptr %39, i32 0, i32 2
  store i32 -1, ptr %40, align 4, !tbaa !15
  %41 = load ptr, ptr %10, align 8, !tbaa !9
  %42 = load i32, ptr %18, align 4, !tbaa !5
  %43 = zext i32 %42 to i64
  %44 = getelementptr inbounds %struct.scheduler_t, ptr %41, i64 %43
  %45 = getelementptr inbounds %struct.scheduler_t, ptr %44, i32 0, i32 3
  store i32 0, ptr %45, align 16, !tbaa !25
  br label %46

46:                                               ; preds = %35
  %47 = load i32, ptr %18, align 4, !tbaa !5
  %48 = add i32 %47, 1
  store i32 %48, ptr %18, align 4, !tbaa !5
  br label %30, !llvm.loop !26

49:                                               ; preds = %34
  %50 = load i32, ptr %16, align 4, !tbaa !5
  store i32 %50, ptr %8, align 4
  store i32 1, ptr %19, align 4
  br label %124

51:                                               ; preds = %7
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #3
  store i32 0, ptr %20, align 4, !tbaa !5
  br label %52

52:                                               ; preds = %78, %51
  %53 = load i32, ptr %20, align 4, !tbaa !5
  %54 = load i32, ptr %9, align 4, !tbaa !5
  %55 = icmp ult i32 %53, %54
  br i1 %55, label %57, label %56

56:                                               ; preds = %52
  store i32 5, ptr %19, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #3
  br label %81

57:                                               ; preds = %52
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #3
  %58 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !9
  %59 = load i32, ptr %20, align 4, !tbaa !5
  %60 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %61 = urem i32 %59, %60
  %62 = zext i32 %61 to i64
  %63 = getelementptr inbounds i32, ptr %58, i64 %62
  %64 = load i32, ptr %63, align 4, !tbaa !5
  store i32 %64, ptr %21, align 4, !tbaa !5
  %65 = load i32, ptr %21, align 4, !tbaa !5
  %66 = load ptr, ptr %10, align 8, !tbaa !9
  %67 = load i32, ptr %20, align 4, !tbaa !5
  %68 = zext i32 %67 to i64
  %69 = getelementptr inbounds %struct.scheduler_t, ptr %66, i64 %68
  %70 = getelementptr inbounds %struct.scheduler_t, ptr %69, i32 0, i32 2
  store i32 %65, ptr %70, align 4, !tbaa !15
  %71 = load i32, ptr %21, align 4, !tbaa !5
  %72 = call i32 @ponyint_numa_node_of_cpu(i32 noundef %71)
  %73 = load ptr, ptr %10, align 8, !tbaa !9
  %74 = load i32, ptr %20, align 4, !tbaa !5
  %75 = zext i32 %74 to i64
  %76 = getelementptr inbounds %struct.scheduler_t, ptr %73, i64 %75
  %77 = getelementptr inbounds %struct.scheduler_t, ptr %76, i32 0, i32 3
  store i32 %72, ptr %77, align 16, !tbaa !25
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #3
  br label %78

78:                                               ; preds = %57
  %79 = load i32, ptr %20, align 4, !tbaa !5
  %80 = add i32 %79, 1
  store i32 %80, ptr %20, align 4, !tbaa !5
  br label %52, !llvm.loop !28

81:                                               ; preds = %56
  %82 = load i8, ptr %12, align 1, !tbaa !11, !range !13, !noundef !14
  %83 = trunc i8 %82 to i1
  br i1 %83, label %84, label %92

84:                                               ; preds = %81
  %85 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !9
  %86 = load i32, ptr %9, align 4, !tbaa !5
  %87 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %88 = urem i32 %86, %87
  %89 = zext i32 %88 to i64
  %90 = getelementptr inbounds i32, ptr %85, i64 %89
  %91 = load i32, ptr %90, align 4, !tbaa !5
  store i32 %91, ptr %16, align 4, !tbaa !5
  br label %92

92:                                               ; preds = %84, %81
  %93 = load i8, ptr %13, align 1, !tbaa !11, !range !13, !noundef !14
  %94 = trunc i8 %93 to i1
  br i1 %94, label %95, label %104

95:                                               ; preds = %92
  %96 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !9
  %97 = load i32, ptr %9, align 4, !tbaa !5
  %98 = add i32 %97, 1
  %99 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %100 = urem i32 %98, %99
  %101 = zext i32 %100 to i64
  %102 = getelementptr inbounds i32, ptr %96, i64 %101
  %103 = load i32, ptr %102, align 4, !tbaa !5
  store i32 %103, ptr %17, align 4, !tbaa !5
  br label %104

104:                                              ; preds = %95, %92
  %105 = load i8, ptr %14, align 1, !tbaa !11, !range !13, !noundef !14
  %106 = trunc i8 %105 to i1
  br i1 %106, label %107, label %117

107:                                              ; preds = %104
  %108 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !9
  %109 = load i32, ptr %9, align 4, !tbaa !5
  %110 = add i32 %109, 2
  %111 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %112 = urem i32 %110, %111
  %113 = zext i32 %112 to i64
  %114 = getelementptr inbounds i32, ptr %108, i64 %113
  %115 = load i32, ptr %114, align 4, !tbaa !5
  %116 = load ptr, ptr %15, align 8, !tbaa !9
  store i32 %115, ptr %116, align 4, !tbaa !5
  br label %117

117:                                              ; preds = %107, %104
  %118 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  %119 = zext i32 %118 to i64
  %120 = mul i64 %119, 4
  %121 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !9
  call void @ponyint_pool_free_size(i64 noundef %120, ptr noundef %121)
  store ptr null, ptr @avail_cpu_list, align 8, !tbaa !9
  store i32 0, ptr @avail_cpu_size, align 4, !tbaa !5
  store i32 0, ptr @avail_cpu_count, align 4, !tbaa !5
  %122 = load i32, ptr %17, align 4, !tbaa !5
  call void @ponyint_cpu_affinity(i32 noundef %122)
  %123 = load i32, ptr %16, align 4, !tbaa !5
  store i32 %123, ptr %8, align 4
  store i32 1, ptr %19, align 4
  br label %124

124:                                              ; preds = %117, %49
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #3
  %125 = load i32, ptr %8, align 4
  ret i32 %125
}

declare i32 @ponyint_numa_node_of_cpu(i32 noundef) #2

declare void @ponyint_pool_free_size(i64 noundef, ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local void @ponyint_cpu_affinity(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_Bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!16, !6, i64 12}
!16 = !{!"scheduler_t", !17, i64 0, !6, i64 8, !6, i64 12, !6, i64 16, !12, i64 20, !12, i64 21, !6, i64 24, !6, i64 28, !10, i64 64, !18, i64 72, !6, i64 216, !6, i64 220, !6, i64 224, !22, i64 232, !23, i64 320, !24, i64 384}
!17 = !{!"long", !7, i64 0}
!18 = !{!"pony_ctx_t", !10, i64 0, !10, i64 8, !10, i64 16, !10, i64 24, !10, i64 32, !19, i64 40, !10, i64 72, !17, i64 80, !21, i64 88, !10, i64 120, !10, i64 128, !10, i64 136}
!19 = !{!"actormap_t", !20, i64 0}
!20 = !{!"hashmap_t", !17, i64 0, !17, i64 8, !10, i64 16, !10, i64 24}
!21 = !{!"ponyint_serialise_t", !20, i64 0}
!22 = !{!"mutemap_t", !20, i64 0}
!23 = !{!"mpmcq_t", !7, i64 0, !7, i64 16}
!24 = !{!"messageq_t", !7, i64 0, !10, i64 8}
!25 = !{!16, !6, i64 16}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = distinct !{!28, !27}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.scheduler_t = type { i64, i32, i32, i32, i8, i8, i32, i32, [32 x i8], ptr, %struct.pony_ctx_t, i32, i32, i32, %struct.mutemap_t, [56 x i8], %struct.mpmcq_t, %struct.messageq_t, [48 x i8] }
%struct.pony_ctx_t = type { ptr, ptr, ptr, ptr, ptr, %struct.actormap_t, ptr, i64, %struct.ponyint_serialise_t, ptr, ptr, ptr }
%struct.actormap_t = type { %struct.hashmap_t }
%struct.hashmap_t = type { i64, i64, ptr, ptr }
%struct.ponyint_serialise_t = type { %struct.hashmap_t }
%struct.mutemap_t = type { %struct.hashmap_t }
%struct.mpmcq_t = type { ptr, %union.aba_protected_mpmcq_node_t, [32 x i8] }
%union.aba_protected_mpmcq_node_t = type { i128 }
%struct.messageq_t = type { ptr, ptr }

@avail_cpu_count = external hidden local_unnamed_addr global i32, align 4
@avail_cpu_size = external hidden local_unnamed_addr global i32, align 4
@avail_cpu_list = external hidden local_unnamed_addr global ptr, align 8

; Function Attrs: nounwind uwtable
define dso_local i32 @ponyint_cpu_assign(i32 noundef %0, ptr nocapture noundef writeonly %1, i1 noundef zeroext %2, i1 noundef zeroext %3, i1 noundef zeroext %4, i1 noundef zeroext %5, ptr nocapture noundef writeonly %6) local_unnamed_addr #0 {
  store i32 -1, ptr %6, align 4, !tbaa !5
  %.not38 = icmp eq i32 %0, 0
  br i1 %2, label %.preheader, label %.preheader34

.preheader34:                                     ; preds = %7
  br i1 %.not38, label %.loopexit, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %.preheader34
  %wide.trip.count = zext i32 %0 to i64
  %xtraiter = and i64 %wide.trip.count, 3
  %8 = icmp ult i32 %0, 4
  br i1 %8, label %.loopexit.loopexit.unr-lcssa, label %.lr.ph.preheader.new

.lr.ph.preheader.new:                             ; preds = %.lr.ph.preheader
  %unroll_iter = and i64 %wide.trip.count, 4294967292
  br label %.lr.ph

.preheader:                                       ; preds = %7
  br i1 %.not38, label %._crit_edge, label %.lr.ph37.preheader

.lr.ph37.preheader:                               ; preds = %.preheader
  %wide.trip.count43 = zext i32 %0 to i64
  br label %.lr.ph37

.lr.ph:                                           ; preds = %.lr.ph, %.lr.ph.preheader.new
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader.new ], [ %indvars.iv.next.3, %.lr.ph ]
  %niter = phi i64 [ 0, %.lr.ph.preheader.new ], [ %niter.next.3, %.lr.ph ]
  %9 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv
  %10 = getelementptr inbounds i8, ptr %9, i64 12
  store i32 -1, ptr %10, align 4, !tbaa !9
  %11 = getelementptr inbounds i8, ptr %9, i64 16
  store i32 0, ptr %11, align 16, !tbaa !21
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %12 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv.next
  %13 = getelementptr inbounds i8, ptr %12, i64 12
  store i32 -1, ptr %13, align 4, !tbaa !9
  %14 = getelementptr inbounds i8, ptr %12, i64 16
  store i32 0, ptr %14, align 16, !tbaa !21
  %indvars.iv.next.1 = or disjoint i64 %indvars.iv, 2
  %15 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv.next.1
  %16 = getelementptr inbounds i8, ptr %15, i64 12
  store i32 -1, ptr %16, align 4, !tbaa !9
  %17 = getelementptr inbounds i8, ptr %15, i64 16
  store i32 0, ptr %17, align 16, !tbaa !21
  %indvars.iv.next.2 = or disjoint i64 %indvars.iv, 3
  %18 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv.next.2
  %19 = getelementptr inbounds i8, ptr %18, i64 12
  store i32 -1, ptr %19, align 4, !tbaa !9
  %20 = getelementptr inbounds i8, ptr %18, i64 16
  store i32 0, ptr %20, align 16, !tbaa !21
  %indvars.iv.next.3 = add nuw nsw i64 %indvars.iv, 4
  %niter.next.3 = add i64 %niter, 4
  %niter.ncmp.3 = icmp eq i64 %niter.next.3, %unroll_iter
  br i1 %niter.ncmp.3, label %.loopexit.loopexit.unr-lcssa, label %.lr.ph, !llvm.loop !22

._crit_edge:                                      ; preds = %.lr.ph37, %.preheader
  %.pre.pre.pre = load ptr, ptr @avail_cpu_list, align 8, !tbaa !24
  br i1 %3, label %32, label %38

.lr.ph37:                                         ; preds = %.lr.ph37.preheader, %.lr.ph37
  %indvars.iv40 = phi i64 [ 0, %.lr.ph37.preheader ], [ %indvars.iv.next41, %.lr.ph37 ]
  %21 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !24
  %22 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %23 = trunc nuw i64 %indvars.iv40 to i32
  %24 = urem i32 %23, %22
  %25 = zext i32 %24 to i64
  %26 = getelementptr inbounds i32, ptr %21, i64 %25
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv40
  %29 = getelementptr inbounds i8, ptr %28, i64 12
  store i32 %27, ptr %29, align 4, !tbaa !9
  %30 = tail call i32 @ponyint_numa_node_of_cpu(i32 noundef %27) #2
  %31 = getelementptr inbounds i8, ptr %28, i64 16
  store i32 %30, ptr %31, align 16, !tbaa !21
  %indvars.iv.next41 = add nuw nsw i64 %indvars.iv40, 1
  %exitcond44.not = icmp eq i64 %indvars.iv.next41, %wide.trip.count43
  br i1 %exitcond44.not, label %._crit_edge, label %.lr.ph37, !llvm.loop !25

32:                                               ; preds = %._crit_edge
  %33 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %34 = urem i32 %0, %33
  %35 = zext i32 %34 to i64
  %36 = getelementptr inbounds i32, ptr %.pre.pre.pre, i64 %35
  %37 = load i32, ptr %36, align 4, !tbaa !5
  br label %38

38:                                               ; preds = %32, %._crit_edge
  %.032 = phi i32 [ %37, %32 ], [ -1, %._crit_edge ]
  br i1 %4, label %39, label %46

39:                                               ; preds = %38
  %40 = add i32 %0, 1
  %41 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %42 = urem i32 %40, %41
  %43 = zext i32 %42 to i64
  %44 = getelementptr inbounds i32, ptr %.pre.pre.pre, i64 %43
  %45 = load i32, ptr %44, align 4, !tbaa !5
  br label %46

46:                                               ; preds = %39, %38
  %.031 = phi i32 [ %45, %39 ], [ -1, %38 ]
  br i1 %5, label %47, label %54

47:                                               ; preds = %46
  %48 = add i32 %0, 2
  %49 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %50 = urem i32 %48, %49
  %51 = zext i32 %50 to i64
  %52 = getelementptr inbounds i32, ptr %.pre.pre.pre, i64 %51
  %53 = load i32, ptr %52, align 4, !tbaa !5
  store i32 %53, ptr %6, align 4, !tbaa !5
  br label %54

54:                                               ; preds = %47, %46
  %55 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  %56 = zext i32 %55 to i64
  %57 = shl nuw nsw i64 %56, 2
  tail call void @ponyint_pool_free_size(i64 noundef %57, ptr noundef %.pre.pre.pre) #2
  store ptr null, ptr @avail_cpu_list, align 8, !tbaa !24
  store i32 0, ptr @avail_cpu_size, align 4, !tbaa !5
  store i32 0, ptr @avail_cpu_count, align 4, !tbaa !5
  tail call void @ponyint_cpu_affinity(i32 noundef %.031)
  br label %.loopexit

.loopexit.loopexit.unr-lcssa:                     ; preds = %.lr.ph, %.lr.ph.preheader
  %indvars.iv.unr = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next.3, %.lr.ph ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %.loopexit, label %.lr.ph.epil

.lr.ph.epil:                                      ; preds = %.loopexit.loopexit.unr-lcssa, %.lr.ph.epil
  %indvars.iv.epil = phi i64 [ %indvars.iv.next.epil, %.lr.ph.epil ], [ %indvars.iv.unr, %.loopexit.loopexit.unr-lcssa ]
  %epil.iter = phi i64 [ %epil.iter.next, %.lr.ph.epil ], [ 0, %.loopexit.loopexit.unr-lcssa ]
  %58 = getelementptr inbounds %struct.scheduler_t, ptr %1, i64 %indvars.iv.epil
  %59 = getelementptr inbounds i8, ptr %58, i64 12
  store i32 -1, ptr %59, align 4, !tbaa !9
  %60 = getelementptr inbounds i8, ptr %58, i64 16
  store i32 0, ptr %60, align 16, !tbaa !21
  %indvars.iv.next.epil = add nuw nsw i64 %indvars.iv.epil, 1
  %epil.iter.next = add i64 %epil.iter, 1
  %epil.iter.cmp.not = icmp eq i64 %epil.iter.next, %xtraiter
  br i1 %epil.iter.cmp.not, label %.loopexit, label %.lr.ph.epil, !llvm.loop !26

.loopexit:                                        ; preds = %.loopexit.loopexit.unr-lcssa, %.lr.ph.epil, %.preheader34, %54
  %.0 = phi i32 [ %.032, %54 ], [ -1, %.preheader34 ], [ -1, %.lr.ph.epil ], [ -1, %.loopexit.loopexit.unr-lcssa ]
  ret i32 %.0
}

declare i32 @ponyint_numa_node_of_cpu(i32 noundef) local_unnamed_addr #1

declare void @ponyint_pool_free_size(i64 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local void @ponyint_cpu_affinity(i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !6, i64 12}
!10 = !{!"scheduler_t", !11, i64 0, !6, i64 8, !6, i64 12, !6, i64 16, !12, i64 20, !12, i64 21, !6, i64 24, !6, i64 28, !13, i64 64, !14, i64 72, !6, i64 216, !6, i64 220, !6, i64 224, !18, i64 232, !19, i64 320, !20, i64 384}
!11 = !{!"long", !7, i64 0}
!12 = !{!"_Bool", !7, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"pony_ctx_t", !13, i64 0, !13, i64 8, !13, i64 16, !13, i64 24, !13, i64 32, !15, i64 40, !13, i64 72, !11, i64 80, !17, i64 88, !13, i64 120, !13, i64 128, !13, i64 136}
!15 = !{!"actormap_t", !16, i64 0}
!16 = !{!"hashmap_t", !11, i64 0, !11, i64 8, !13, i64 16, !13, i64 24}
!17 = !{!"ponyint_serialise_t", !16, i64 0}
!18 = !{!"mutemap_t", !16, i64 0}
!19 = !{!"mpmcq_t", !7, i64 0, !7, i64 16}
!20 = !{!"messageq_t", !7, i64 0, !13, i64 8}
!21 = !{!10, !6, i64 16}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}
!24 = !{!13, !13, i64 0}
!25 = distinct !{!25, !23}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.unroll.disable"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass