; LLVM IR from ponylang/ponyc :: src/libponyrt/sched (cpu)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.cpu_set_t = type { [16 x i64] }

@avail_cpu_count = external hidden global i32, align 4
@avail_cpu_size = external hidden global i32, align 4
@hw_cpu_count = external hidden global i32, align 4
@avail_cpu_list = external hidden global ptr, align 8

; Function Attrs: nounwind uwtable
define dso_local void @ponyint_cpu_init() #0 {
  %1 = alloca %struct.cpu_set_t, align 8
  %2 = alloca %struct.cpu_set_t, align 8
  %3 = alloca %struct.cpu_set_t, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 128, ptr %1) #5
  call void @llvm.lifetime.start.p0(i64 128, ptr %2) #5
  call void @llvm.lifetime.start.p0(i64 128, ptr %3) #5
  %14 = call i32 @sched_getaffinity(i32 noundef 0, i64 noundef 128, ptr noundef %1) #5
  br label %15

15:                                               ; preds = %0
  call void @llvm.memset.p0.i64(ptr align 8 %2, i8 0, i64 128, i1 false)
  br label %16

16:                                               ; preds = %15
  br label %17

17:                                               ; preds = %16
  br label %18

18:                                               ; preds = %17
  call void @llvm.memset.p0.i64(ptr align 8 %3, i8 0, i64 128, i1 false)
  br label %19

19:                                               ; preds = %18
  br label %20

20:                                               ; preds = %19
  %21 = call i32 @__sched_cpucount(i64 noundef 128, ptr noundef %1) #5
  store i32 %21, ptr @avail_cpu_count, align 4, !tbaa !5
  store i32 %21, ptr @avail_cpu_size, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #5
  store i32 0, ptr %4, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 0, ptr %5, align 4, !tbaa !5
  br label %22

22:                                               ; preds = %98, %20
  %23 = load i32, ptr %5, align 4, !tbaa !5
  %24 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %25 = icmp ult i32 %23, %24
  br i1 %25, label %26, label %101

26:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #5
  %27 = load i32, ptr %4, align 4, !tbaa !5
  %28 = zext i32 %27 to i64
  store i64 %28, ptr %6, align 8, !tbaa !9
  %29 = load i64, ptr %6, align 8, !tbaa !9
  %30 = udiv i64 %29, 8
  %31 = icmp ult i64 %30, 128
  br i1 %31, label %32, label %45

32:                                               ; preds = %26
  %33 = getelementptr inbounds %struct.cpu_set_t, ptr %1, i32 0, i32 0
  %34 = getelementptr inbounds [16 x i64], ptr %33, i64 0, i64 0
  %35 = load i64, ptr %6, align 8, !tbaa !9
  %36 = udiv i64 %35, 64
  %37 = getelementptr inbounds i64, ptr %34, i64 %36
  %38 = load i64, ptr %37, align 8, !tbaa !9
  %39 = load i64, ptr %6, align 8, !tbaa !9
  %40 = urem i64 %39, 64
  %41 = shl i64 1, %40
  %42 = and i64 %38, %41
  %43 = icmp ne i64 %42, 0
  %44 = zext i1 %43 to i32
  br label %46

45:                                               ; preds = %26
  br label %46

46:                                               ; preds = %45, %32
  %47 = phi i32 [ %44, %32 ], [ 0, %45 ]
  store i32 %47, ptr %7, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #5
  %48 = load i32, ptr %7, align 4, !tbaa !5
  %49 = icmp ne i32 %48, 0
  br i1 %49, label %50, label %98

50:                                               ; preds = %46
  %51 = load i32, ptr %4, align 4, !tbaa !5
  %52 = call zeroext i1 @cpu_physical(i32 noundef %51)
  br i1 %52, label %53, label %74

53:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %54 = load i32, ptr %4, align 4, !tbaa !5
  %55 = zext i32 %54 to i64
  store i64 %55, ptr %8, align 8, !tbaa !9
  %56 = load i64, ptr %8, align 8, !tbaa !9
  %57 = udiv i64 %56, 8
  %58 = icmp ult i64 %57, 128
  br i1 %58, label %59, label %70

59:                                               ; preds = %53
  %60 = load i64, ptr %8, align 8, !tbaa !9
  %61 = urem i64 %60, 64
  %62 = shl i64 1, %61
  %63 = getelementptr inbounds %struct.cpu_set_t, ptr %2, i32 0, i32 0
  %64 = getelementptr inbounds [16 x i64], ptr %63, i64 0, i64 0
  %65 = load i64, ptr %8, align 8, !tbaa !9
  %66 = udiv i64 %65, 64
  %67 = getelementptr inbounds i64, ptr %64, i64 %66
  %68 = load i64, ptr %67, align 8, !tbaa !9
  %69 = or i64 %68, %62
  store i64 %69, ptr %67, align 8, !tbaa !9
  br label %71

70:                                               ; preds = %53
  br label %71

71:                                               ; preds = %70, %59
  %72 = phi i64 [ %69, %59 ], [ 0, %70 ]
  store i64 %72, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  %73 = load i64, ptr %9, align 8, !tbaa !9
  br label %95

74:                                               ; preds = %50
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  %75 = load i32, ptr %4, align 4, !tbaa !5
  %76 = zext i32 %75 to i64
  store i64 %76, ptr %10, align 8, !tbaa !9
  %77 = load i64, ptr %10, align 8, !tbaa !9
  %78 = udiv i64 %77, 8
  %79 = icmp ult i64 %78, 128
  br i1 %79, label %80, label %91

80:                                               ; preds = %74
  %81 = load i64, ptr %10, align 8, !tbaa !9
  %82 = urem i64 %81, 64
  %83 = shl i64 1, %82
  %84 = getelementptr inbounds %struct.cpu_set_t, ptr %3, i32 0, i32 0
  %85 = getelementptr inbounds [16 x i64], ptr %84, i64 0, i64 0
  %86 = load i64, ptr %10, align 8, !tbaa !9
  %87 = udiv i64 %86, 64
  %88 = getelementptr inbounds i64, ptr %85, i64 %87
  %89 = load i64, ptr %88, align 8, !tbaa !9
  %90 = or i64 %89, %83
  store i64 %90, ptr %88, align 8, !tbaa !9
  br label %92

91:                                               ; preds = %74
  br label %92

92:                                               ; preds = %91, %80
  %93 = phi i64 [ %90, %80 ], [ 0, %91 ]
  store i64 %93, ptr %11, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  %94 = load i64, ptr %11, align 8, !tbaa !9
  br label %95

95:                                               ; preds = %92, %71
  %96 = load i32, ptr %5, align 4, !tbaa !5
  %97 = add i32 %96, 1
  store i32 %97, ptr %5, align 4, !tbaa !5
  br label %98

98:                                               ; preds = %95, %46
  %99 = load i32, ptr %4, align 4, !tbaa !5
  %100 = add i32 %99, 1
  store i32 %100, ptr %4, align 4, !tbaa !5
  br label %22, !llvm.loop !11

101:                                              ; preds = %22
  %102 = call i32 @__sched_cpucount(i64 noundef 128, ptr noundef %2) #5
  store i32 %102, ptr @hw_cpu_count, align 4, !tbaa !5
  %103 = call zeroext i1 (...) @ponyint_numa_init()
  br i1 %103, label %104, label %118

104:                                              ; preds = %101
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #5
  %105 = call i32 (...) @ponyint_numa_cores()
  store i32 %105, ptr %12, align 4, !tbaa !5
  %106 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %107 = load i32, ptr %12, align 4, !tbaa !5
  %108 = icmp ugt i32 %106, %107
  br i1 %108, label %109, label %111

109:                                              ; preds = %104
  %110 = load i32, ptr %12, align 4, !tbaa !5
  store i32 %110, ptr @avail_cpu_size, align 4, !tbaa !5
  br label %111

111:                                              ; preds = %109, %104
  %112 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  %113 = zext i32 %112 to i64
  %114 = mul i64 %113, 4
  %115 = call noalias ptr @ponyint_pool_alloc_size(i64 noundef %114)
  store ptr %115, ptr @avail_cpu_list, align 8, !tbaa !13
  %116 = load ptr, ptr @avail_cpu_list, align 8, !tbaa !13
  %117 = call i32 @ponyint_numa_core_list(ptr noundef %2, ptr noundef %3, ptr noundef %116)
  store i32 %117, ptr @avail_cpu_count, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #5
  br label %127

118:                                              ; preds = %101
  %119 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  %120 = zext i32 %119 to i64
  %121 = mul i64 %120, 4
  %122 = call noalias ptr @ponyint_pool_alloc_size(i64 noundef %121)
  store ptr %122, ptr @avail_cpu_list, align 8, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #5
  store i32 0, ptr %13, align 4, !tbaa !5
  %123 = load i32, ptr %13, align 4, !tbaa !5
  %124 = call i32 @cpu_add_mask_to_list(i32 noundef %123, ptr noundef %2)
  store i32 %124, ptr %13, align 4, !tbaa !5
  %125 = load i32, ptr %13, align 4, !tbaa !5
  %126 = call i32 @cpu_add_mask_to_list(i32 noundef %125, ptr noundef %3)
  store i32 %126, ptr %13, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #5
  br label %127

127:                                              ; preds = %118, %111
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr %3) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr %2) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr %1) #5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i32 @sched_getaffinity(i32 noundef, i64 noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: nounwind
declare i32 @__sched_cpucount(i64 noundef, ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden zeroext i1 @cpu_physical(i32 noundef) #0

declare zeroext i1 @ponyint_numa_init(...) #4

declare i32 @ponyint_numa_cores(...) #4

declare noalias ptr @ponyint_pool_alloc_size(i64 noundef) #4

declare i32 @ponyint_numa_core_list(ptr noundef, ptr noundef, ptr noundef) #4

; Function Attrs: nounwind uwtable
declare hidden i32 @cpu_add_mask_to_list(i32 noundef, ptr noundef) #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"any pointer", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.cpu_set_t = type { [16 x i64] }

@avail_cpu_count = external hidden local_unnamed_addr global i32, align 4
@avail_cpu_size = external hidden local_unnamed_addr global i32, align 4
@hw_cpu_count = external hidden local_unnamed_addr global i32, align 4
@avail_cpu_list = external hidden local_unnamed_addr global ptr, align 8

; Function Attrs: nounwind uwtable
define dso_local void @ponyint_cpu_init() local_unnamed_addr #0 {
  %1 = alloca %struct.cpu_set_t, align 8
  %2 = alloca %struct.cpu_set_t, align 8
  %3 = alloca %struct.cpu_set_t, align 8
  call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %1) #5
  call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %2) #5
  call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %3) #5
  %4 = call i32 @sched_getaffinity(i32 noundef 0, i64 noundef 128, ptr noundef nonnull %1) #5
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(128) %2, i8 0, i64 128, i1 false)
  call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(128) %3, i8 0, i64 128, i1 false)
  %5 = call i32 @__sched_cpucount(i64 noundef 128, ptr noundef nonnull %1) #5
  store i32 %5, ptr @avail_cpu_count, align 4, !tbaa !5
  store i32 %5, ptr @avail_cpu_size, align 4, !tbaa !5
  %.not = icmp eq i32 %5, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %0, %.thread
  %6 = phi i32 [ %22, %.thread ], [ %5, %0 ]
  %.028 = phi i32 [ %23, %.thread ], [ 0, %0 ]
  %.02327 = phi i32 [ %.1, %.thread ], [ 0, %0 ]
  %7 = icmp ult i32 %.028, 1024
  br i1 %7, label %8, label %.thread

8:                                                ; preds = %.lr.ph
  %9 = zext nneg i32 %.028 to i64
  %10 = lshr i64 %9, 6
  %11 = getelementptr inbounds i64, ptr %1, i64 %10
  %12 = load i64, ptr %11, align 8, !tbaa !9
  %13 = and i64 %9, 63
  %14 = shl nuw i64 1, %13
  %15 = and i64 %12, %14
  %.not26 = icmp eq i64 %15, 0
  br i1 %.not26, label %.thread, label %16

16:                                               ; preds = %8
  %17 = call zeroext i1 @cpu_physical(i32 noundef %.028)
  %. = select i1 %17, ptr %2, ptr %3
  %18 = getelementptr inbounds i64, ptr %., i64 %10
  %19 = load i64, ptr %18, align 8, !tbaa !9
  %20 = or i64 %19, %14
  store i64 %20, ptr %18, align 8, !tbaa !9
  %21 = add nuw i32 %.02327, 1
  %.pre = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  br label %.thread

.thread:                                          ; preds = %.lr.ph, %16, %8
  %22 = phi i32 [ %.pre, %16 ], [ %6, %8 ], [ %6, %.lr.ph ]
  %.1 = phi i32 [ %21, %16 ], [ %.02327, %8 ], [ %.02327, %.lr.ph ]
  %23 = add i32 %.028, 1
  %24 = icmp ult i32 %.1, %22
  br i1 %24, label %.lr.ph, label %._crit_edge, !llvm.loop !11

._crit_edge:                                      ; preds = %.thread, %0
  %25 = call i32 @__sched_cpucount(i64 noundef 128, ptr noundef nonnull %2) #5
  store i32 %25, ptr @hw_cpu_count, align 4, !tbaa !5
  %26 = call zeroext i1 (...) @ponyint_numa_init() #5
  br i1 %26, label %27, label %38

27:                                               ; preds = %._crit_edge
  %28 = call i32 (...) @ponyint_numa_cores() #5
  %29 = load i32, ptr @avail_cpu_count, align 4, !tbaa !5
  %30 = icmp ugt i32 %29, %28
  br i1 %30, label %31, label %._crit_edge29

._crit_edge29:                                    ; preds = %27
  %.pre30 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  br label %32

31:                                               ; preds = %27
  store i32 %28, ptr @avail_cpu_size, align 4, !tbaa !5
  br label %32

32:                                               ; preds = %._crit_edge29, %31
  %33 = phi i32 [ %.pre30, %._crit_edge29 ], [ %28, %31 ]
  %34 = zext i32 %33 to i64
  %35 = shl nuw nsw i64 %34, 2
  %36 = call noalias ptr @ponyint_pool_alloc_size(i64 noundef %35) #5
  store ptr %36, ptr @avail_cpu_list, align 8, !tbaa !13
  %37 = call i32 @ponyint_numa_core_list(ptr noundef nonnull %2, ptr noundef nonnull %3, ptr noundef %36) #5
  store i32 %37, ptr @avail_cpu_count, align 4, !tbaa !5
  br label %45

38:                                               ; preds = %._crit_edge
  %39 = load i32, ptr @avail_cpu_size, align 4, !tbaa !5
  %40 = zext i32 %39 to i64
  %41 = shl nuw nsw i64 %40, 2
  %42 = call noalias ptr @ponyint_pool_alloc_size(i64 noundef %41) #5
  store ptr %42, ptr @avail_cpu_list, align 8, !tbaa !13
  %43 = call i32 @cpu_add_mask_to_list(i32 noundef 0, ptr noundef nonnull %2)
  %44 = call i32 @cpu_add_mask_to_list(i32 noundef %43, ptr noundef nonnull %3)
  br label %45

45:                                               ; preds = %38, %32
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %3) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %2) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %1) #5
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i32 @sched_getaffinity(i32 noundef, i64 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: nounwind
declare i32 @__sched_cpucount(i64 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind uwtable
declare hidden zeroext i1 @cpu_physical(i32 noundef) local_unnamed_addr #0

declare zeroext i1 @ponyint_numa_init(...) local_unnamed_addr #4

declare i32 @ponyint_numa_cores(...) local_unnamed_addr #4

declare noalias ptr @ponyint_pool_alloc_size(i64 noundef) local_unnamed_addr #4

declare i32 @ponyint_numa_core_list(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #4

; Function Attrs: nounwind uwtable
declare hidden i32 @cpu_add_mask_to_list(i32 noundef, ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"any pointer", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass