; LLVM IR from cvra/robot-software :: uwb-beacon-firmware/src/decadriver (deca_device)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @dwt_setleds(i8 noundef zeroext %0) #1 {
  %2 = alloca i8, align 1
  %3 = alloca i64, align 8
  store i8 %0, ptr %2, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #2
  %4 = load i8, ptr %2, align 1, !tbaa !5
  %5 = zext i8 %4 to i32
  %6 = and i32 %5, 1
  %7 = icmp ne i32 %6, 0
  br i1 %7, label %8, label %37

8:                                                ; preds = %1
  %9 = call i64 @dwt_read32bitoffsetreg(i32 noundef 38, i32 noundef 0)
  store i64 %9, ptr %3, align 8, !tbaa !8
  %10 = load i64, ptr %3, align 8, !tbaa !8
  %11 = and i64 %10, -16321
  store i64 %11, ptr %3, align 8, !tbaa !8
  %12 = load i64, ptr %3, align 8, !tbaa !8
  %13 = or i64 %12, 5440
  store i64 %13, ptr %3, align 8, !tbaa !8
  %14 = load i64, ptr %3, align 8, !tbaa !8
  call void @dwt_write32bitoffsetreg(i32 noundef 38, i32 noundef 0, i64 noundef %14)
  %15 = call i64 @dwt_read32bitoffsetreg(i32 noundef 54, i32 noundef 0)
  store i64 %15, ptr %3, align 8, !tbaa !8
  %16 = load i64, ptr %3, align 8, !tbaa !8
  %17 = or i64 %16, 8650752
  store i64 %17, ptr %3, align 8, !tbaa !8
  %18 = load i64, ptr %3, align 8, !tbaa !8
  call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 0, i64 noundef %18)
  store i64 272, ptr %3, align 8, !tbaa !8
  %19 = load i8, ptr %2, align 1, !tbaa !5
  %20 = zext i8 %19 to i32
  %21 = and i32 %20, 2
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %26

23:                                               ; preds = %8
  %24 = load i64, ptr %3, align 8, !tbaa !8
  %25 = or i64 %24, 983040
  store i64 %25, ptr %3, align 8, !tbaa !8
  br label %26

26:                                               ; preds = %23, %8
  %27 = load i64, ptr %3, align 8, !tbaa !8
  call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 40, i64 noundef %27)
  %28 = load i8, ptr %2, align 1, !tbaa !5
  %29 = zext i8 %28 to i32
  %30 = and i32 %29, 2
  %31 = icmp ne i32 %30, 0
  br i1 %31, label %32, label %36

32:                                               ; preds = %26
  %33 = load i64, ptr %3, align 8, !tbaa !8
  %34 = and i64 %33, -983041
  store i64 %34, ptr %3, align 8, !tbaa !8
  %35 = load i64, ptr %3, align 8, !tbaa !8
  call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 40, i64 noundef %35)
  br label %36

36:                                               ; preds = %32, %26
  br label %42

37:                                               ; preds = %1
  %38 = call i64 @dwt_read32bitoffsetreg(i32 noundef 38, i32 noundef 0)
  store i64 %38, ptr %3, align 8, !tbaa !8
  %39 = load i64, ptr %3, align 8, !tbaa !8
  %40 = and i64 %39, -15361
  store i64 %40, ptr %3, align 8, !tbaa !8
  %41 = load i64, ptr %3, align 8, !tbaa !8
  call void @dwt_write32bitoffsetreg(i32 noundef 38, i32 noundef 0, i64 noundef %41)
  br label %42

42:                                               ; preds = %37, %36
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #2
  ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"long", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @dwt_setleds(i8 noundef zeroext %0) local_unnamed_addr #0 {
  %2 = zext i8 %0 to i32
  %3 = and i32 %2, 1
  %.not = icmp eq i32 %3, 0
  %4 = tail call i64 @dwt_read32bitoffsetreg(i32 noundef 38, i32 noundef 0)
  br i1 %.not, label %12, label %5

5:                                                ; preds = %1
  %6 = and i64 %4, -16321
  %7 = or disjoint i64 %6, 5440
  tail call void @dwt_write32bitoffsetreg(i32 noundef 38, i32 noundef 0, i64 noundef %7)
  %8 = tail call i64 @dwt_read32bitoffsetreg(i32 noundef 54, i32 noundef 0)
  %9 = or i64 %8, 8650752
  tail call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 0, i64 noundef %9)
  %10 = and i32 %2, 2
  %.not14 = icmp eq i32 %10, 0
  %spec.select = select i1 %.not14, i64 272, i64 983312
  tail call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 40, i64 noundef %spec.select)
  br i1 %.not14, label %14, label %11

11:                                               ; preds = %5
  tail call void @dwt_write32bitoffsetreg(i32 noundef 54, i32 noundef 40, i64 noundef 272)
  br label %14

12:                                               ; preds = %1
  %13 = and i64 %4, -15361
  tail call void @dwt_write32bitoffsetreg(i32 noundef 38, i32 noundef 0, i64 noundef %13)
  br label %14

14:                                               ; preds = %5, %11, %12
  ret void
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass