; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_q)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }
%struct.os_q = type { ptr, ptr, ptr, ptr, ptr, i16, i16 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) #1

declare void @OS_Sched() #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i8 @OSQPostFront(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca i8, align 1
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = getelementptr inbounds %struct.os_event, ptr %9, i32 0, i32 0
  %11 = load i8, ptr %10, align 8, !tbaa !11
  %12 = zext i8 %11 to i32
  %13 = icmp ne i32 %12, 2
  br i1 %13, label %14, label %15

14:                                               ; preds = %2
  store i8 1, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %70

15:                                               ; preds = %2
  %16 = call i32 @OS_CPU_SR_Save()
  store i32 %16, ptr %7, align 4, !tbaa !9
  %17 = load ptr, ptr %4, align 8, !tbaa !5
  %18 = getelementptr inbounds %struct.os_event, ptr %17, i32 0, i32 3
  %19 = load i8, ptr %18, align 2, !tbaa !14
  %20 = zext i8 %19 to i32
  %21 = icmp ne i32 %20, 0
  br i1 %21, label %22, label %27

22:                                               ; preds = %15
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = load ptr, ptr %5, align 8, !tbaa !5
  %25 = call zeroext i8 @OS_EventTaskRdy(ptr noundef %23, ptr noundef %24, i8 noundef zeroext 4, i8 noundef zeroext 0)
  %26 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %26)
  call void @OS_Sched()
  store i8 0, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %70

27:                                               ; preds = %15
  %28 = load ptr, ptr %4, align 8, !tbaa !5
  %29 = getelementptr inbounds %struct.os_event, ptr %28, i32 0, i32 1
  %30 = load ptr, ptr %29, align 8, !tbaa !15
  store ptr %30, ptr %6, align 8, !tbaa !5
  %31 = load ptr, ptr %6, align 8, !tbaa !5
  %32 = getelementptr inbounds %struct.os_q, ptr %31, i32 0, i32 6
  %33 = load i16, ptr %32, align 2, !tbaa !16
  %34 = zext i16 %33 to i32
  %35 = load ptr, ptr %6, align 8, !tbaa !5
  %36 = getelementptr inbounds %struct.os_q, ptr %35, i32 0, i32 5
  %37 = load i16, ptr %36, align 8, !tbaa !18
  %38 = zext i16 %37 to i32
  %39 = icmp sge i32 %34, %38
  br i1 %39, label %40, label %42

40:                                               ; preds = %27
  %41 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %41)
  store i8 30, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %70

42:                                               ; preds = %27
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.os_q, ptr %43, i32 0, i32 4
  %45 = load ptr, ptr %44, align 8, !tbaa !19
  %46 = load ptr, ptr %6, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.os_q, ptr %46, i32 0, i32 1
  %48 = load ptr, ptr %47, align 8, !tbaa !20
  %49 = icmp eq ptr %45, %48
  br i1 %49, label %50, label %56

50:                                               ; preds = %42
  %51 = load ptr, ptr %6, align 8, !tbaa !5
  %52 = getelementptr inbounds %struct.os_q, ptr %51, i32 0, i32 2
  %53 = load ptr, ptr %52, align 8, !tbaa !21
  %54 = load ptr, ptr %6, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.os_q, ptr %54, i32 0, i32 4
  store ptr %53, ptr %55, align 8, !tbaa !19
  br label %56

56:                                               ; preds = %50, %42
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.os_q, ptr %57, i32 0, i32 4
  %59 = load ptr, ptr %58, align 8, !tbaa !19
  %60 = getelementptr inbounds ptr, ptr %59, i32 -1
  store ptr %60, ptr %58, align 8, !tbaa !19
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.os_q, ptr %62, i32 0, i32 4
  %64 = load ptr, ptr %63, align 8, !tbaa !19
  store ptr %61, ptr %64, align 8, !tbaa !5
  %65 = load ptr, ptr %6, align 8, !tbaa !5
  %66 = getelementptr inbounds %struct.os_q, ptr %65, i32 0, i32 6
  %67 = load i16, ptr %66, align 2, !tbaa !16
  %68 = add i16 %67, 1
  store i16 %68, ptr %66, align 2, !tbaa !16
  %69 = load i32, ptr %7, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %69)
  store i8 0, ptr %3, align 1
  store i32 1, ptr %8, align 4
  br label %70

70:                                               ; preds = %56, %40, %22, %14
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %71 = load i8, ptr %3, align 1
  ret i8 %71
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 0}
!12 = !{!"os_event", !7, i64 0, !6, i64 8, !13, i64 16, !7, i64 18, !7, i64 19}
!13 = !{!"short", !7, i64 0}
!14 = !{!12, !7, i64 18}
!15 = !{!12, !6, i64 8}
!16 = !{!17, !13, i64 42}
!17 = !{!"os_q", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !13, i64 40, !13, i64 42}
!18 = !{!17, !13, i64 40}
!19 = !{!17, !6, i64 32}
!20 = !{!17, !6, i64 8}
!21 = !{!17, !6, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

declare void @OS_Sched() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local zeroext range(i8 0, 31) i8 @OSQPostFront(ptr noundef %0, ptr noundef %1) local_unnamed_addr #1 {
  %3 = load i8, ptr %0, align 8, !tbaa !5
  %.not = icmp eq i8 %3, 2
  br i1 %.not, label %4, label %31

4:                                                ; preds = %2
  %5 = tail call i32 @OS_CPU_SR_Save() #2
  %6 = getelementptr inbounds i8, ptr %0, i64 18
  %7 = load i8, ptr %6, align 2, !tbaa !11
  %.not18 = icmp eq i8 %7, 0
  br i1 %.not18, label %10, label %8

8:                                                ; preds = %4
  %9 = tail call zeroext i8 @OS_EventTaskRdy(ptr noundef nonnull %0, ptr noundef %1, i8 noundef zeroext 4, i8 noundef zeroext 0) #2
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  tail call void @OS_Sched() #2
  br label %31

10:                                               ; preds = %4
  %11 = getelementptr inbounds i8, ptr %0, i64 8
  %12 = load ptr, ptr %11, align 8, !tbaa !12
  %13 = getelementptr inbounds i8, ptr %12, i64 42
  %14 = load i16, ptr %13, align 2, !tbaa !13
  %15 = getelementptr inbounds i8, ptr %12, i64 40
  %16 = load i16, ptr %15, align 8, !tbaa !15
  %.not19 = icmp ult i16 %14, %16
  br i1 %.not19, label %18, label %17

17:                                               ; preds = %10
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  br label %31

18:                                               ; preds = %10
  %19 = getelementptr inbounds i8, ptr %12, i64 32
  %20 = load ptr, ptr %19, align 8, !tbaa !16
  %21 = getelementptr inbounds i8, ptr %12, i64 8
  %22 = load ptr, ptr %21, align 8, !tbaa !17
  %23 = icmp eq ptr %20, %22
  br i1 %23, label %24, label %27

24:                                               ; preds = %18
  %25 = getelementptr inbounds i8, ptr %12, i64 16
  %26 = load ptr, ptr %25, align 8, !tbaa !18
  br label %27

27:                                               ; preds = %24, %18
  %28 = phi ptr [ %26, %24 ], [ %20, %18 ]
  %29 = getelementptr inbounds i8, ptr %28, i64 -8
  store ptr %29, ptr %19, align 8, !tbaa !16
  store ptr %1, ptr %29, align 8, !tbaa !19
  %30 = add nuw i16 %14, 1
  store i16 %30, ptr %13, align 2, !tbaa !13
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  br label %31

31:                                               ; preds = %2, %27, %17, %8
  %.0 = phi i8 [ 0, %8 ], [ 30, %17 ], [ 0, %27 ], [ 1, %2 ]
  ret i8 %.0
}

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"os_event", !7, i64 0, !9, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"any pointer", !7, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!6, !7, i64 18}
!12 = !{!6, !9, i64 8}
!13 = !{!14, !10, i64 42}
!14 = !{!"os_q", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !10, i64 40, !10, i64 42}
!15 = !{!14, !10, i64 40}
!16 = !{!14, !9, i64 32}
!17 = !{!14, !9, i64 8}
!18 = !{!14, !9, i64 16}
!19 = !{!9, !9, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass