; LLVM IR from cvra/robot-software :: uwb-beacon-firmware/src/decadriver (deca_device)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.agc_cfg_struct = type { i64, [2 x i16] }
%struct.dwt_config_t = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i16 }
%struct.dwt_local_data_t = type { i64, i64, i8, i8, i64, i8, i8, i64, i16, i8, %struct.dwt_cb_data_t, ptr, ptr, ptr, ptr }
%struct.dwt_cb_data_t = type { i64, i16, [2 x i8], i8 }

@pdw1000local = external hidden global ptr, align 8
@lde_replicaCoeff = external constant [25 x i16], align 16
@fs_pll_cfg = external constant [6 x i64], align 16
@chan_idx = external constant [8 x i8], align 1
@fs_pll_tune = external constant [6 x i8], align 1
@rx_config = external constant [2 x i8], align 1
@tx_config = external constant [6 x i64], align 16
@sftsh = external constant [3 x [2 x i16]], align 2
@dtune1 = external constant [2 x i16], align 2
@digital_bb_config = external constant [2 x [4 x i64]], align 16
@agc_config = external constant %struct.agc_cfg_struct, align 8
@dwnsSFDlen = external constant [3 x i8], align 1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local void @dwt_configure(ptr noundef %0) #1 {
  %2 = alloca ptr, align 8
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i64, align 8
  %7 = alloca i16, align 2
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #2
  store i8 0, ptr %3, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %4) #2
  store i8 0, ptr %4, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = getelementptr inbounds %struct.dwt_config_t, ptr %10, i32 0, i32 0
  %12 = load i8, ptr %11, align 2, !tbaa !10
  store i8 %12, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.start.p0(i64 2, ptr %7) #2
  %13 = load ptr, ptr %2, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.dwt_config_t, ptr %13, i32 0, i32 5
  %15 = load i8, ptr %14, align 1, !tbaa !13
  %16 = zext i8 %15 to i64
  %17 = getelementptr inbounds [25 x i16], ptr @lde_replicaCoeff, i64 0, i64 %16
  %18 = load i16, ptr %17, align 2, !tbaa !14
  store i16 %18, ptr %7, align 2, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #2
  %19 = load ptr, ptr %2, align 8, !tbaa !5
  %20 = getelementptr inbounds %struct.dwt_config_t, ptr %19, i32 0, i32 1
  %21 = load i8, ptr %20, align 1, !tbaa !15
  %22 = zext i8 %21 to i32
  %23 = sub nsw i32 %22, 1
  %24 = trunc i32 %23 to i8
  store i8 %24, ptr %8, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #2
  %25 = load i8, ptr %5, align 1, !tbaa !9
  %26 = zext i8 %25 to i32
  %27 = icmp eq i32 %26, 4
  br i1 %27, label %32, label %28

28:                                               ; preds = %1
  %29 = load i8, ptr %5, align 1, !tbaa !9
  %30 = zext i8 %29 to i32
  %31 = icmp eq i32 %30, 7
  br label %32

32:                                               ; preds = %28, %1
  %33 = phi i1 [ true, %1 ], [ %31, %28 ]
  %34 = zext i1 %33 to i64
  %35 = select i1 %33, i32 1, i32 0
  %36 = trunc i32 %35 to i8
  store i8 %36, ptr %9, align 1, !tbaa !9
  %37 = load ptr, ptr %2, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.dwt_config_t, ptr %37, i32 0, i32 7
  %39 = load i8, ptr %38, align 1, !tbaa !16
  %40 = zext i8 %39 to i32
  %41 = icmp eq i32 0, %40
  br i1 %41, label %42, label %51

42:                                               ; preds = %32
  %43 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %44 = getelementptr inbounds %struct.dwt_local_data_t, ptr %43, i32 0, i32 7
  %45 = load i64, ptr %44, align 8, !tbaa !17
  %46 = or i64 %45, 4194304
  store i64 %46, ptr %44, align 8, !tbaa !17
  %47 = load i16, ptr %7, align 2, !tbaa !14
  %48 = zext i16 %47 to i32
  %49 = ashr i32 %48, 3
  %50 = trunc i32 %49 to i16
  store i16 %50, ptr %7, align 2, !tbaa !14
  br label %56

51:                                               ; preds = %32
  %52 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %53 = getelementptr inbounds %struct.dwt_local_data_t, ptr %52, i32 0, i32 7
  %54 = load i64, ptr %53, align 8, !tbaa !17
  %55 = and i64 %54, -4194305
  store i64 %55, ptr %53, align 8, !tbaa !17
  br label %56

56:                                               ; preds = %51, %42
  %57 = load ptr, ptr %2, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.dwt_config_t, ptr %57, i32 0, i32 8
  %59 = load i8, ptr %58, align 2, !tbaa !21
  %60 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.dwt_local_data_t, ptr %60, i32 0, i32 2
  store i8 %59, ptr %61, align 8, !tbaa !22
  %62 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.dwt_local_data_t, ptr %62, i32 0, i32 7
  %64 = load i64, ptr %63, align 8, !tbaa !17
  %65 = and i64 %64, -196609
  store i64 %65, ptr %63, align 8, !tbaa !17
  %66 = load ptr, ptr %2, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.dwt_config_t, ptr %66, i32 0, i32 8
  %68 = load i8, ptr %67, align 2, !tbaa !21
  %69 = zext i8 %68 to i32
  %70 = shl i32 %69, 16
  %71 = sext i32 %70 to i64
  %72 = and i64 196608, %71
  %73 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.dwt_local_data_t, ptr %73, i32 0, i32 7
  %75 = load i64, ptr %74, align 8, !tbaa !17
  %76 = or i64 %75, %72
  store i64 %76, ptr %74, align 8, !tbaa !17
  %77 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.dwt_local_data_t, ptr %77, i32 0, i32 7
  %79 = load i64, ptr %78, align 8, !tbaa !17
  call void @dwt_write32bitoffsetreg(i32 noundef 4, i32 noundef 0, i64 noundef %79)
  %80 = load i16, ptr %7, align 2, !tbaa !14
  call void @dwt_write16bitoffsetreg(i32 noundef 46, i32 noundef 10244, i16 noundef zeroext %80)
  %81 = load i8, ptr %8, align 1, !tbaa !9
  %82 = zext i8 %81 to i32
  call void @_dwt_configlde(i32 noundef %82)
  %83 = load i8, ptr %5, align 1, !tbaa !9
  %84 = zext i8 %83 to i64
  %85 = getelementptr inbounds [8 x i8], ptr @chan_idx, i64 0, i64 %84
  %86 = load i8, ptr %85, align 1, !tbaa !9
  %87 = zext i8 %86 to i64
  %88 = getelementptr inbounds [6 x i64], ptr @fs_pll_cfg, i64 0, i64 %87
  %89 = load i64, ptr %88, align 8, !tbaa !23
  call void @dwt_write32bitoffsetreg(i32 noundef 43, i32 noundef 7, i64 noundef %89)
  %90 = load i8, ptr %5, align 1, !tbaa !9
  %91 = zext i8 %90 to i64
  %92 = getelementptr inbounds [8 x i8], ptr @chan_idx, i64 0, i64 %91
  %93 = load i8, ptr %92, align 1, !tbaa !9
  %94 = zext i8 %93 to i64
  %95 = getelementptr inbounds [6 x i8], ptr @fs_pll_tune, i64 0, i64 %94
  %96 = load i8, ptr %95, align 1, !tbaa !9
  call void @dwt_write8bitoffsetreg(i32 noundef 43, i32 noundef 11, i8 noundef zeroext %96)
  %97 = load i8, ptr %9, align 1, !tbaa !9
  %98 = zext i8 %97 to i64
  %99 = getelementptr inbounds [2 x i8], ptr @rx_config, i64 0, i64 %98
  %100 = load i8, ptr %99, align 1, !tbaa !9
  call void @dwt_write8bitoffsetreg(i32 noundef 40, i32 noundef 11, i8 noundef zeroext %100)
  %101 = load i8, ptr %5, align 1, !tbaa !9
  %102 = zext i8 %101 to i64
  %103 = getelementptr inbounds [8 x i8], ptr @chan_idx, i64 0, i64 %102
  %104 = load i8, ptr %103, align 1, !tbaa !9
  %105 = zext i8 %104 to i64
  %106 = getelementptr inbounds [6 x i64], ptr @tx_config, i64 0, i64 %105
  %107 = load i64, ptr %106, align 8, !tbaa !23
  call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 12, i64 noundef %107)
  %108 = load ptr, ptr %2, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.dwt_config_t, ptr %108, i32 0, i32 7
  %110 = load i8, ptr %109, align 1, !tbaa !16
  %111 = zext i8 %110 to i64
  %112 = getelementptr inbounds [3 x [2 x i16]], ptr @sftsh, i64 0, i64 %111
  %113 = load ptr, ptr %2, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.dwt_config_t, ptr %113, i32 0, i32 6
  %115 = load i8, ptr %114, align 2, !tbaa !24
  %116 = zext i8 %115 to i64
  %117 = getelementptr inbounds [2 x i16], ptr %112, i64 0, i64 %116
  %118 = load i16, ptr %117, align 2, !tbaa !14
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 2, i16 noundef zeroext %118)
  %119 = load i8, ptr %8, align 1, !tbaa !9
  %120 = zext i8 %119 to i64
  %121 = getelementptr inbounds [2 x i16], ptr @dtune1, i64 0, i64 %120
  %122 = load i16, ptr %121, align 2, !tbaa !14
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 4, i16 noundef zeroext %122)
  %123 = load ptr, ptr %2, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.dwt_config_t, ptr %123, i32 0, i32 7
  %125 = load i8, ptr %124, align 1, !tbaa !16
  %126 = zext i8 %125 to i32
  %127 = icmp eq i32 %126, 0
  br i1 %127, label %128, label %129

128:                                              ; preds = %56
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 100)
  br label %138

129:                                              ; preds = %56
  %130 = load ptr, ptr %2, align 8, !tbaa !5
  %131 = getelementptr inbounds %struct.dwt_config_t, ptr %130, i32 0, i32 2
  %132 = load i8, ptr %131, align 2, !tbaa !25
  %133 = zext i8 %132 to i32
  %134 = icmp eq i32 %133, 4
  br i1 %134, label %135, label %136

135:                                              ; preds = %129
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 16)
  call void @dwt_write8bitoffsetreg(i32 noundef 39, i32 noundef 38, i8 noundef zeroext 16)
  br label %137

136:                                              ; preds = %129
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 32)
  call void @dwt_write8bitoffsetreg(i32 noundef 39, i32 noundef 38, i8 noundef zeroext 40)
  br label %137

137:                                              ; preds = %136, %135
  br label %138

138:                                              ; preds = %137, %128
  %139 = load i8, ptr %8, align 1, !tbaa !9
  %140 = zext i8 %139 to i64
  %141 = getelementptr inbounds [2 x [4 x i64]], ptr @digital_bb_config, i64 0, i64 %140
  %142 = load ptr, ptr %2, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.dwt_config_t, ptr %142, i32 0, i32 3
  %144 = load i8, ptr %143, align 1, !tbaa !26
  %145 = zext i8 %144 to i64
  %146 = getelementptr inbounds [4 x i64], ptr %141, i64 0, i64 %145
  %147 = load i64, ptr %146, align 8, !tbaa !23
  call void @dwt_write32bitoffsetreg(i32 noundef 39, i32 noundef 8, i64 noundef %147)
  %148 = load ptr, ptr %2, align 8, !tbaa !5
  %149 = getelementptr inbounds %struct.dwt_config_t, ptr %148, i32 0, i32 9
  %150 = load i16, ptr %149, align 2, !tbaa !27
  %151 = zext i16 %150 to i32
  %152 = icmp eq i32 %151, 0
  br i1 %152, label %153, label %156

153:                                              ; preds = %138
  %154 = load ptr, ptr %2, align 8, !tbaa !5
  %155 = getelementptr inbounds %struct.dwt_config_t, ptr %154, i32 0, i32 9
  store i16 4161, ptr %155, align 2, !tbaa !27
  br label %156

156:                                              ; preds = %153, %138
  %157 = load ptr, ptr %2, align 8, !tbaa !5
  %158 = getelementptr inbounds %struct.dwt_config_t, ptr %157, i32 0, i32 9
  %159 = load i16, ptr %158, align 2, !tbaa !27
  call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 32, i16 noundef zeroext %159)
  %160 = load i64, ptr @agc_config, align 8, !tbaa !28
  call void @dwt_write32bitoffsetreg(i32 noundef 35, i32 noundef 12, i64 noundef %160)
  %161 = load i8, ptr %8, align 1, !tbaa !9
  %162 = zext i8 %161 to i64
  %163 = getelementptr inbounds [2 x i16], ptr getelementptr inbounds (%struct.agc_cfg_struct, ptr @agc_config, i32 0, i32 1), i64 0, i64 %162
  %164 = load i16, ptr %163, align 2, !tbaa !14
  call void @dwt_write16bitoffsetreg(i32 noundef 35, i32 noundef 4, i16 noundef zeroext %164)
  %165 = load ptr, ptr %2, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.dwt_config_t, ptr %165, i32 0, i32 6
  %167 = load i8, ptr %166, align 2, !tbaa !24
  %168 = icmp ne i8 %167, 0
  br i1 %168, label %169, label %176

169:                                              ; preds = %156
  %170 = load ptr, ptr %2, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.dwt_config_t, ptr %170, i32 0, i32 7
  %172 = load i8, ptr %171, align 1, !tbaa !16
  %173 = zext i8 %172 to i64
  %174 = getelementptr inbounds [3 x i8], ptr @dwnsSFDlen, i64 0, i64 %173
  %175 = load i8, ptr %174, align 1, !tbaa !9
  call void @dwt_write8bitoffsetreg(i32 noundef 33, i32 noundef 0, i8 noundef zeroext %175)
  store i8 3, ptr %3, align 1, !tbaa !9
  store i8 1, ptr %4, align 1, !tbaa !9
  br label %176

176:                                              ; preds = %169, %156
  %177 = load i8, ptr %5, align 1, !tbaa !9
  %178 = zext i8 %177 to i32
  %179 = shl i32 %178, 0
  %180 = sext i32 %179 to i64
  %181 = and i64 15, %180
  %182 = load i8, ptr %5, align 1, !tbaa !9
  %183 = zext i8 %182 to i32
  %184 = shl i32 %183, 4
  %185 = sext i32 %184 to i64
  %186 = and i64 240, %185
  %187 = or i64 %181, %186
  %188 = load ptr, ptr %2, align 8, !tbaa !5
  %189 = getelementptr inbounds %struct.dwt_config_t, ptr %188, i32 0, i32 1
  %190 = load i8, ptr %189, align 1, !tbaa !15
  %191 = zext i8 %190 to i32
  %192 = shl i32 %191, 18
  %193 = sext i32 %192 to i64
  %194 = and i64 786432, %193
  %195 = or i64 %187, %194
  %196 = load i8, ptr %3, align 1, !tbaa !9
  %197 = zext i8 %196 to i32
  %198 = shl i32 %197, 20
  %199 = sext i32 %198 to i64
  %200 = and i64 3145728, %199
  %201 = or i64 %195, %200
  %202 = load i8, ptr %4, align 1, !tbaa !9
  %203 = zext i8 %202 to i32
  %204 = shl i32 %203, 17
  %205 = sext i32 %204 to i64
  %206 = and i64 131072, %205
  %207 = or i64 %201, %206
  %208 = load ptr, ptr %2, align 8, !tbaa !5
  %209 = getelementptr inbounds %struct.dwt_config_t, ptr %208, i32 0, i32 4
  %210 = load i8, ptr %209, align 2, !tbaa !30
  %211 = zext i8 %210 to i32
  %212 = shl i32 %211, 22
  %213 = sext i32 %212 to i64
  %214 = and i64 130023424, %213
  %215 = or i64 %207, %214
  %216 = load ptr, ptr %2, align 8, !tbaa !5
  %217 = getelementptr inbounds %struct.dwt_config_t, ptr %216, i32 0, i32 5
  %218 = load i8, ptr %217, align 1, !tbaa !13
  %219 = zext i8 %218 to i32
  %220 = shl i32 %219, 27
  %221 = sext i32 %220 to i64
  %222 = and i64 4160749568, %221
  %223 = or i64 %215, %222
  store i64 %223, ptr %6, align 8, !tbaa !23
  %224 = load i64, ptr %6, align 8, !tbaa !23
  call void @dwt_write32bitoffsetreg(i32 noundef 31, i32 noundef 0, i64 noundef %224)
  %225 = load ptr, ptr %2, align 8, !tbaa !5
  %226 = getelementptr inbounds %struct.dwt_config_t, ptr %225, i32 0, i32 2
  %227 = load i8, ptr %226, align 2, !tbaa !25
  %228 = zext i8 %227 to i32
  %229 = load ptr, ptr %2, align 8, !tbaa !5
  %230 = getelementptr inbounds %struct.dwt_config_t, ptr %229, i32 0, i32 1
  %231 = load i8, ptr %230, align 1, !tbaa !15
  %232 = zext i8 %231 to i32
  %233 = or i32 %228, %232
  %234 = shl i32 %233, 16
  %235 = load ptr, ptr %2, align 8, !tbaa !5
  %236 = getelementptr inbounds %struct.dwt_config_t, ptr %235, i32 0, i32 7
  %237 = load i8, ptr %236, align 1, !tbaa !16
  %238 = zext i8 %237 to i32
  %239 = shl i32 %238, 13
  %240 = or i32 %234, %239
  %241 = sext i32 %240 to i64
  %242 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %243 = getelementptr inbounds %struct.dwt_local_data_t, ptr %242, i32 0, i32 4
  store i64 %241, ptr %243, align 8, !tbaa !31
  %244 = load ptr, ptr @pdw1000local, align 8, !tbaa !5
  %245 = getelementptr inbounds %struct.dwt_local_data_t, ptr %244, i32 0, i32 4
  %246 = load i64, ptr %245, align 8, !tbaa !31
  call void @dwt_write32bitoffsetreg(i32 noundef 8, i32 noundef 0, i64 noundef %246)
  call void @dwt_write8bitoffsetreg(i32 noundef 13, i32 noundef 0, i8 noundef zeroext 66)
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #2
  call void @llvm.lifetime.end.p0(i64 2, ptr %7) #2
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %4) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #2
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @_dwt_configlde(i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !7, i64 0}
!11 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !7, i64 4, !7, i64 5, !7, i64 6, !7, i64 7, !7, i64 8, !12, i64 10}
!12 = !{!"short", !7, i64 0}
!13 = !{!11, !7, i64 5}
!14 = !{!12, !12, i64 0}
!15 = !{!11, !7, i64 1}
!16 = !{!11, !7, i64 7}
!17 = !{!18, !19, i64 40}
!18 = !{!"", !19, i64 0, !19, i64 8, !7, i64 16, !7, i64 17, !19, i64 24, !7, i64 32, !7, i64 33, !19, i64 40, !12, i64 48, !7, i64 50, !20, i64 56, !6, i64 72, !6, i64 80, !6, i64 88, !6, i64 96}
!19 = !{!"long", !7, i64 0}
!20 = !{!"", !19, i64 0, !12, i64 8, !7, i64 10, !7, i64 12}
!21 = !{!11, !7, i64 8}
!22 = !{!18, !7, i64 16}
!23 = !{!19, !19, i64 0}
!24 = !{!11, !7, i64 6}
!25 = !{!11, !7, i64 2}
!26 = !{!11, !7, i64 3}
!27 = !{!11, !12, i64 10}
!28 = !{!29, !19, i64 0}
!29 = !{!"", !19, i64 0, !7, i64 8}
!30 = !{!11, !7, i64 4}
!31 = !{!18, !19, i64 24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.agc_cfg_struct = type { i64, [2 x i16] }

@pdw1000local = external hidden local_unnamed_addr global ptr, align 8
@lde_replicaCoeff = external local_unnamed_addr constant [25 x i16], align 16
@fs_pll_cfg = external local_unnamed_addr constant [6 x i64], align 16
@chan_idx = external local_unnamed_addr constant [8 x i8], align 1
@fs_pll_tune = external local_unnamed_addr constant [6 x i8], align 1
@rx_config = external local_unnamed_addr constant [2 x i8], align 1
@tx_config = external local_unnamed_addr constant [6 x i64], align 16
@sftsh = external local_unnamed_addr constant [3 x [2 x i16]], align 2
@dtune1 = external local_unnamed_addr constant [2 x i16], align 2
@digital_bb_config = external local_unnamed_addr constant [2 x [4 x i64]], align 16
@agc_config = external local_unnamed_addr constant %struct.agc_cfg_struct, align 8
@dwnsSFDlen = external local_unnamed_addr constant [3 x i8], align 1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local void @dwt_configure(ptr nocapture noundef %0) local_unnamed_addr #0 {
  %2 = load i8, ptr %0, align 2, !tbaa !5
  %3 = getelementptr inbounds i8, ptr %0, i64 5
  %4 = load i8, ptr %3, align 1, !tbaa !10
  %5 = zext i8 %4 to i64
  %6 = getelementptr inbounds [25 x i16], ptr @lde_replicaCoeff, i64 0, i64 %5
  %7 = load i16, ptr %6, align 2, !tbaa !11
  %8 = getelementptr inbounds i8, ptr %0, i64 1
  %9 = load i8, ptr %8, align 1, !tbaa !12
  %10 = add i8 %9, -1
  %11 = icmp eq i8 %2, 4
  %12 = icmp eq i8 %2, 7
  %13 = or i1 %11, %12
  %14 = getelementptr inbounds i8, ptr %0, i64 7
  %15 = load i8, ptr %14, align 1, !tbaa !13
  %16 = icmp eq i8 %15, 0
  %17 = load ptr, ptr @pdw1000local, align 8, !tbaa !14
  %18 = getelementptr inbounds i8, ptr %17, i64 40
  %19 = load i64, ptr %18, align 8, !tbaa !16
  br i1 %16, label %20, label %23

20:                                               ; preds = %1
  %21 = or i64 %19, 4194304
  store i64 %21, ptr %18, align 8, !tbaa !16
  %22 = lshr i16 %7, 3
  br label %25

23:                                               ; preds = %1
  %24 = and i64 %19, -4194305
  store i64 %24, ptr %18, align 8, !tbaa !16
  br label %25

25:                                               ; preds = %23, %20
  %26 = phi i64 [ %21, %20 ], [ %24, %23 ]
  %.039 = phi i16 [ %22, %20 ], [ %7, %23 ]
  %27 = getelementptr inbounds i8, ptr %0, i64 8
  %28 = load i8, ptr %27, align 2, !tbaa !20
  %29 = getelementptr inbounds i8, ptr %17, i64 16
  store i8 %28, ptr %29, align 8, !tbaa !21
  %30 = getelementptr inbounds i8, ptr %17, i64 40
  %31 = and i64 %26, -196609
  %32 = zext i8 %28 to i64
  %33 = shl nuw nsw i64 %32, 16
  %34 = and i64 %33, 196608
  %35 = or disjoint i64 %31, %34
  store i64 %35, ptr %30, align 8, !tbaa !16
  tail call void @dwt_write32bitoffsetreg(i32 noundef 4, i32 noundef 0, i64 noundef %35)
  tail call void @dwt_write16bitoffsetreg(i32 noundef 46, i32 noundef 10244, i16 noundef zeroext %.039)
  %36 = zext i8 %10 to i32
  tail call void @_dwt_configlde(i32 noundef %36)
  %37 = zext i8 %2 to i64
  %38 = getelementptr inbounds [8 x i8], ptr @chan_idx, i64 0, i64 %37
  %39 = load i8, ptr %38, align 1, !tbaa !22
  %40 = zext i8 %39 to i64
  %41 = getelementptr inbounds [6 x i64], ptr @fs_pll_cfg, i64 0, i64 %40
  %42 = load i64, ptr %41, align 8, !tbaa !23
  tail call void @dwt_write32bitoffsetreg(i32 noundef 43, i32 noundef 7, i64 noundef %42)
  %43 = getelementptr inbounds [6 x i8], ptr @fs_pll_tune, i64 0, i64 %40
  %44 = load i8, ptr %43, align 1, !tbaa !22
  tail call void @dwt_write8bitoffsetreg(i32 noundef 43, i32 noundef 11, i8 noundef zeroext %44)
  %45 = zext i1 %13 to i64
  %46 = getelementptr inbounds [2 x i8], ptr @rx_config, i64 0, i64 %45
  %47 = load i8, ptr %46, align 1, !tbaa !22
  tail call void @dwt_write8bitoffsetreg(i32 noundef 40, i32 noundef 11, i8 noundef zeroext %47)
  %48 = getelementptr inbounds [6 x i64], ptr @tx_config, i64 0, i64 %40
  %49 = load i64, ptr %48, align 8, !tbaa !23
  tail call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 12, i64 noundef %49)
  %50 = load i8, ptr %14, align 1, !tbaa !13
  %51 = zext i8 %50 to i64
  %52 = getelementptr inbounds i8, ptr %0, i64 6
  %53 = load i8, ptr %52, align 2, !tbaa !24
  %54 = zext i8 %53 to i64
  %55 = getelementptr inbounds [3 x [2 x i16]], ptr @sftsh, i64 0, i64 %51, i64 %54
  %56 = load i16, ptr %55, align 2, !tbaa !11
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 2, i16 noundef zeroext %56)
  %57 = zext i8 %10 to i64
  %58 = getelementptr inbounds [2 x i16], ptr @dtune1, i64 0, i64 %57
  %59 = load i16, ptr %58, align 2, !tbaa !11
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 4, i16 noundef zeroext %59)
  %60 = load i8, ptr %14, align 1, !tbaa !13
  %61 = icmp eq i8 %60, 0
  br i1 %61, label %62, label %63

62:                                               ; preds = %25
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 100)
  br label %69

63:                                               ; preds = %25
  %64 = getelementptr inbounds i8, ptr %0, i64 2
  %65 = load i8, ptr %64, align 2, !tbaa !25
  %66 = icmp eq i8 %65, 4
  br i1 %66, label %67, label %68

67:                                               ; preds = %63
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 16)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 39, i32 noundef 38, i8 noundef zeroext 16)
  br label %69

68:                                               ; preds = %63
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 6, i16 noundef zeroext 32)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 39, i32 noundef 38, i8 noundef zeroext 40)
  br label %69

69:                                               ; preds = %67, %68, %62
  %70 = getelementptr inbounds i8, ptr %0, i64 3
  %71 = load i8, ptr %70, align 1, !tbaa !26
  %72 = zext i8 %71 to i64
  %73 = getelementptr inbounds [2 x [4 x i64]], ptr @digital_bb_config, i64 0, i64 %57, i64 %72
  %74 = load i64, ptr %73, align 8, !tbaa !23
  tail call void @dwt_write32bitoffsetreg(i32 noundef 39, i32 noundef 8, i64 noundef %74)
  %75 = getelementptr inbounds i8, ptr %0, i64 10
  %76 = load i16, ptr %75, align 2, !tbaa !27
  %77 = icmp eq i16 %76, 0
  br i1 %77, label %78, label %79

78:                                               ; preds = %69
  store i16 4161, ptr %75, align 2, !tbaa !27
  br label %79

79:                                               ; preds = %78, %69
  %80 = phi i16 [ 4161, %78 ], [ %76, %69 ]
  tail call void @dwt_write16bitoffsetreg(i32 noundef 39, i32 noundef 32, i16 noundef zeroext %80)
  %81 = load i64, ptr @agc_config, align 8, !tbaa !28
  tail call void @dwt_write32bitoffsetreg(i32 noundef 35, i32 noundef 12, i64 noundef %81)
  %82 = getelementptr inbounds [2 x i16], ptr getelementptr inbounds (i8, ptr @agc_config, i64 8), i64 0, i64 %57
  %83 = load i16, ptr %82, align 2, !tbaa !11
  tail call void @dwt_write16bitoffsetreg(i32 noundef 35, i32 noundef 4, i16 noundef zeroext %83)
  %84 = load i8, ptr %52, align 2, !tbaa !24
  %.not = icmp eq i8 %84, 0
  br i1 %.not, label %90, label %85

85:                                               ; preds = %79
  %86 = load i8, ptr %14, align 1, !tbaa !13
  %87 = zext i8 %86 to i64
  %88 = getelementptr inbounds [3 x i8], ptr @dwnsSFDlen, i64 0, i64 %87
  %89 = load i8, ptr %88, align 1, !tbaa !22
  tail call void @dwt_write8bitoffsetreg(i32 noundef 33, i32 noundef 0, i8 noundef zeroext %89)
  br label %90

90:                                               ; preds = %85, %79
  %.038 = phi i64 [ 131072, %85 ], [ 0, %79 ]
  %.0 = phi i64 [ 3145728, %85 ], [ 0, %79 ]
  %91 = and i8 %2, 15
  %92 = zext nneg i8 %91 to i64
  %93 = shl nuw nsw i64 %37, 4
  %94 = and i64 %93, 240
  %95 = or disjoint i64 %94, %92
  %96 = load i8, ptr %8, align 1, !tbaa !12
  %97 = zext i8 %96 to i64
  %98 = shl nuw nsw i64 %97, 18
  %99 = and i64 %98, 786432
  %100 = getelementptr inbounds i8, ptr %0, i64 4
  %101 = load i8, ptr %100, align 2, !tbaa !30
  %102 = zext i8 %101 to i64
  %103 = shl nuw nsw i64 %102, 22
  %104 = and i64 %103, 130023424
  %105 = load i8, ptr %3, align 1, !tbaa !10
  %106 = zext i8 %105 to i64
  %107 = shl nuw nsw i64 %106, 27
  %108 = and i64 %107, 4160749568
  %109 = or disjoint i64 %95, %.038
  %110 = or disjoint i64 %109, %.0
  %111 = or disjoint i64 %110, %99
  %112 = or disjoint i64 %111, %104
  %113 = or i64 %112, %108
  tail call void @dwt_write32bitoffsetreg(i32 noundef 31, i32 noundef 0, i64 noundef %113)
  %114 = getelementptr inbounds i8, ptr %0, i64 2
  %115 = load i8, ptr %114, align 2, !tbaa !25
  %116 = load i8, ptr %8, align 1, !tbaa !12
  %117 = or i8 %116, %115
  %118 = zext i8 %117 to i64
  %119 = shl nuw nsw i64 %118, 16
  %120 = load i8, ptr %14, align 1, !tbaa !13
  %121 = zext i8 %120 to i64
  %122 = shl nuw nsw i64 %121, 13
  %123 = or i64 %119, %122
  %124 = load ptr, ptr @pdw1000local, align 8, !tbaa !14
  %125 = getelementptr inbounds i8, ptr %124, i64 24
  store i64 %123, ptr %125, align 8, !tbaa !31
  tail call void @dwt_write32bitoffsetreg(i32 noundef 8, i32 noundef 0, i64 noundef %123)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 13, i32 noundef 0, i8 noundef zeroext 66)
  ret void
}

; Function Attrs: nounwind uwtable
declare dso_local void @_dwt_configlde(i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !7, i64 4, !7, i64 5, !7, i64 6, !7, i64 7, !7, i64 8, !9, i64 10}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"short", !7, i64 0}
!10 = !{!6, !7, i64 5}
!11 = !{!9, !9, i64 0}
!12 = !{!6, !7, i64 1}
!13 = !{!6, !7, i64 7}
!14 = !{!15, !15, i64 0}
!15 = !{!"any pointer", !7, i64 0}
!16 = !{!17, !18, i64 40}
!17 = !{!"", !18, i64 0, !18, i64 8, !7, i64 16, !7, i64 17, !18, i64 24, !7, i64 32, !7, i64 33, !18, i64 40, !9, i64 48, !7, i64 50, !19, i64 56, !15, i64 72, !15, i64 80, !15, i64 88, !15, i64 96}
!18 = !{!"long", !7, i64 0}
!19 = !{!"", !18, i64 0, !9, i64 8, !7, i64 10, !7, i64 12}
!20 = !{!6, !7, i64 8}
!21 = !{!17, !7, i64 16}
!22 = !{!7, !7, i64 0}
!23 = !{!18, !18, i64 0}
!24 = !{!6, !7, i64 6}
!25 = !{!6, !7, i64 2}
!26 = !{!6, !7, i64 3}
!27 = !{!6, !9, i64 10}
!28 = !{!29, !18, i64 0}
!29 = !{!"", !18, i64 0, !7, i64 8}
!30 = !{!6, !7, i64 4}
!31 = !{!17, !18, i64 24}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass