; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_q)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }
%struct.os_q = type { ptr, ptr, ptr, ptr, ptr, i16, i16 }

@OSIntNesting = external global i8, align 1
@OSEventFreeList = external global ptr, align 8
@OSQFreeList = external global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSQCreate(ptr noundef %0, i16 noundef zeroext %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i16, align 2
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i16 %1, ptr %5, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !11
  %10 = load i8, ptr @OSIntNesting, align 1, !tbaa !13
  %11 = zext i8 %10 to i32
  %12 = icmp ugt i32 %11, 0
  br i1 %12, label %13, label %14

13:                                               ; preds = %2
  store ptr null, ptr %3, align 8
  store i32 1, ptr %9, align 4
  br label %74

14:                                               ; preds = %2
  %15 = call i32 @OS_CPU_SR_Save()
  store i32 %15, ptr %8, align 4, !tbaa !11
  %16 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  store ptr %16, ptr %6, align 8, !tbaa !5
  %17 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %18 = icmp ne ptr %17, null
  br i1 %18, label %19, label %23

19:                                               ; preds = %14
  %20 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %21 = getelementptr inbounds %struct.os_event, ptr %20, i32 0, i32 1
  %22 = load ptr, ptr %21, align 8, !tbaa !14
  store ptr %22, ptr @OSEventFreeList, align 8, !tbaa !5
  br label %23

23:                                               ; preds = %19, %14
  %24 = load i32, ptr %8, align 4, !tbaa !11
  call void @OS_CPU_SR_Restore(i32 noundef %24)
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = icmp ne ptr %25, null
  br i1 %26, label %27, label %72

27:                                               ; preds = %23
  %28 = call i32 @OS_CPU_SR_Save()
  store i32 %28, ptr %8, align 4, !tbaa !11
  %29 = load ptr, ptr @OSQFreeList, align 8, !tbaa !5
  store ptr %29, ptr %7, align 8, !tbaa !5
  %30 = load ptr, ptr %7, align 8, !tbaa !5
  %31 = icmp ne ptr %30, null
  br i1 %31, label %32, label %65

32:                                               ; preds = %27
  %33 = load ptr, ptr @OSQFreeList, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.os_q, ptr %33, i32 0, i32 0
  %35 = load ptr, ptr %34, align 8, !tbaa !16
  store ptr %35, ptr @OSQFreeList, align 8, !tbaa !5
  %36 = load i32, ptr %8, align 4, !tbaa !11
  call void @OS_CPU_SR_Restore(i32 noundef %36)
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = load ptr, ptr %7, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.os_q, ptr %38, i32 0, i32 1
  store ptr %37, ptr %39, align 8, !tbaa !18
  %40 = load ptr, ptr %4, align 8, !tbaa !5
  %41 = load i16, ptr %5, align 2, !tbaa !9
  %42 = zext i16 %41 to i64
  %43 = getelementptr inbounds ptr, ptr %40, i64 %42
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.os_q, ptr %44, i32 0, i32 2
  store ptr %43, ptr %45, align 8, !tbaa !19
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = load ptr, ptr %7, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.os_q, ptr %47, i32 0, i32 3
  store ptr %46, ptr %48, align 8, !tbaa !20
  %49 = load ptr, ptr %4, align 8, !tbaa !5
  %50 = load ptr, ptr %7, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.os_q, ptr %50, i32 0, i32 4
  store ptr %49, ptr %51, align 8, !tbaa !21
  %52 = load i16, ptr %5, align 2, !tbaa !9
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.os_q, ptr %53, i32 0, i32 5
  store i16 %52, ptr %54, align 8, !tbaa !22
  %55 = load ptr, ptr %7, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.os_q, ptr %55, i32 0, i32 6
  store i16 0, ptr %56, align 2, !tbaa !23
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.os_event, ptr %57, i32 0, i32 0
  store i8 2, ptr %58, align 8, !tbaa !24
  %59 = load ptr, ptr %6, align 8, !tbaa !5
  %60 = getelementptr inbounds %struct.os_event, ptr %59, i32 0, i32 2
  store i16 0, ptr %60, align 8, !tbaa !25
  %61 = load ptr, ptr %7, align 8, !tbaa !5
  %62 = load ptr, ptr %6, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.os_event, ptr %62, i32 0, i32 1
  store ptr %61, ptr %63, align 8, !tbaa !14
  %64 = load ptr, ptr %6, align 8, !tbaa !5
  call void @OS_EventWaitListInit(ptr noundef %64)
  br label %71

65:                                               ; preds = %27
  %66 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %67 = load ptr, ptr %6, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.os_event, ptr %67, i32 0, i32 1
  store ptr %66, ptr %68, align 8, !tbaa !14
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %69, ptr @OSEventFreeList, align 8, !tbaa !5
  %70 = load i32, ptr %8, align 4, !tbaa !11
  call void @OS_CPU_SR_Restore(i32 noundef %70)
  store ptr null, ptr %6, align 8, !tbaa !5
  br label %71

71:                                               ; preds = %65, %32
  br label %72

72:                                               ; preds = %71, %23
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  store ptr %73, ptr %3, align 8
  store i32 1, ptr %9, align 4
  br label %74

74:                                               ; preds = %72, %13
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %75 = load ptr, ptr %3, align 8
  ret ptr %75
}

declare void @OS_EventWaitListInit(ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!7, !7, i64 0}
!14 = !{!15, !6, i64 8}
!15 = !{!"os_event", !7, i64 0, !6, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!16 = !{!17, !6, i64 0}
!17 = !{!"os_q", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !10, i64 40, !10, i64 42}
!18 = !{!17, !6, i64 8}
!19 = !{!17, !6, i64 16}
!20 = !{!17, !6, i64 24}
!21 = !{!17, !6, i64 32}
!22 = !{!17, !10, i64 40}
!23 = !{!17, !10, i64 42}
!24 = !{!15, !7, i64 0}
!25 = !{!15, !10, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSEventFreeList = external local_unnamed_addr global ptr, align 8
@OSQFreeList = external local_unnamed_addr global ptr, align 8

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSQCreate(ptr noundef %0, i16 noundef zeroext %1) local_unnamed_addr #1 {
  %3 = load i8, ptr @OSIntNesting, align 1, !tbaa !5
  %.not = icmp eq i8 %3, 0
  br i1 %.not, label %4, label %25

4:                                                ; preds = %2
  %5 = tail call i32 @OS_CPU_SR_Save() #2
  %6 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !8
  %.not28 = icmp eq ptr %6, null
  br i1 %.not28, label %.critedge, label %7

7:                                                ; preds = %4
  %8 = getelementptr inbounds i8, ptr %6, i64 8
  %9 = load ptr, ptr %8, align 8, !tbaa !10
  store ptr %9, ptr @OSEventFreeList, align 8, !tbaa !8
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  %10 = tail call i32 @OS_CPU_SR_Save() #2
  %11 = load ptr, ptr @OSQFreeList, align 8, !tbaa !8
  %.not29 = icmp eq ptr %11, null
  br i1 %.not29, label %23, label %12

12:                                               ; preds = %7
  %13 = load ptr, ptr %11, align 8, !tbaa !13
  store ptr %13, ptr @OSQFreeList, align 8, !tbaa !8
  tail call void @OS_CPU_SR_Restore(i32 noundef %10) #2
  %14 = getelementptr inbounds i8, ptr %11, i64 8
  store ptr %0, ptr %14, align 8, !tbaa !15
  %15 = zext i16 %1 to i64
  %16 = getelementptr inbounds ptr, ptr %0, i64 %15
  %17 = getelementptr inbounds i8, ptr %11, i64 16
  store ptr %16, ptr %17, align 8, !tbaa !16
  %18 = getelementptr inbounds i8, ptr %11, i64 24
  store ptr %0, ptr %18, align 8, !tbaa !17
  %19 = getelementptr inbounds i8, ptr %11, i64 32
  store ptr %0, ptr %19, align 8, !tbaa !18
  %20 = getelementptr inbounds i8, ptr %11, i64 40
  store i16 %1, ptr %20, align 8, !tbaa !19
  %21 = getelementptr inbounds i8, ptr %11, i64 42
  store i16 0, ptr %21, align 2, !tbaa !20
  store i8 2, ptr %6, align 8, !tbaa !21
  %22 = getelementptr inbounds i8, ptr %6, i64 16
  store i16 0, ptr %22, align 8, !tbaa !22
  store ptr %11, ptr %8, align 8, !tbaa !10
  tail call void @OS_EventWaitListInit(ptr noundef nonnull %6) #2
  br label %25

23:                                               ; preds = %7
  %24 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !8
  store ptr %24, ptr %8, align 8, !tbaa !10
  store ptr %6, ptr @OSEventFreeList, align 8, !tbaa !8
  tail call void @OS_CPU_SR_Restore(i32 noundef %10) #2
  br label %25

.critedge:                                        ; preds = %4
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  br label %25

25:                                               ; preds = %23, %12, %.critedge, %2
  %.0 = phi ptr [ null, %2 ], [ %6, %12 ], [ null, %23 ], [ null, %.critedge ]
  ret ptr %.0
}

declare void @OS_EventWaitListInit(ptr noundef) local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !9, i64 8}
!11 = !{!"os_event", !6, i64 0, !9, i64 8, !12, i64 16, !6, i64 18, !6, i64 19}
!12 = !{!"short", !6, i64 0}
!13 = !{!14, !9, i64 0}
!14 = !{!"os_q", !9, i64 0, !9, i64 8, !9, i64 16, !9, i64 24, !9, i64 32, !12, i64 40, !12, i64 42}
!15 = !{!14, !9, i64 8}
!16 = !{!14, !9, i64 16}
!17 = !{!14, !9, i64 24}
!18 = !{!14, !9, i64 32}
!19 = !{!14, !12, i64 40}
!20 = !{!14, !12, i64 42}
!21 = !{!11, !6, i64 0}
!22 = !{!11, !12, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass