; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_mbox)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }
%struct.os_tcb = type { ptr, ptr, ptr, i32, i16, i16, ptr, ptr, ptr, ptr, ptr, i16, i32, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, ptr, i32, ptr, [1 x i32] }

@OSIntNesting = external global i8, align 1
@OSLockNesting = external global i8, align 1
@OSTCBCur = external global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare void @OS_Sched() #1

; Function Attrs: nounwind uwtable
define dso_local ptr @OSMboxPend(ptr noundef %0, i32 noundef %1, ptr noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  store i32 0, ptr %9, align 4, !tbaa !9
  %11 = load ptr, ptr %5, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.os_event, ptr %11, i32 0, i32 0
  %13 = load i8, ptr %12, align 8, !tbaa !11
  %14 = zext i8 %13 to i32
  %15 = icmp ne i32 %14, 1
  br i1 %15, label %16, label %18

16:                                               ; preds = %3
  %17 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 1, ptr %17, align 1, !tbaa !14
  store ptr null, ptr %4, align 8
  store i32 1, ptr %10, align 4
  br label %85

18:                                               ; preds = %3
  %19 = load i8, ptr @OSIntNesting, align 1, !tbaa !14
  %20 = zext i8 %19 to i32
  %21 = icmp ugt i32 %20, 0
  br i1 %21, label %22, label %24

22:                                               ; preds = %18
  %23 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 2, ptr %23, align 1, !tbaa !14
  store ptr null, ptr %4, align 8
  store i32 1, ptr %10, align 4
  br label %85

24:                                               ; preds = %18
  %25 = load i8, ptr @OSLockNesting, align 1, !tbaa !14
  %26 = zext i8 %25 to i32
  %27 = icmp ugt i32 %26, 0
  br i1 %27, label %28, label %30

28:                                               ; preds = %24
  %29 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 13, ptr %29, align 1, !tbaa !14
  store ptr null, ptr %4, align 8
  store i32 1, ptr %10, align 4
  br label %85

30:                                               ; preds = %24
  %31 = call i32 @OS_CPU_SR_Save()
  store i32 %31, ptr %9, align 4, !tbaa !9
  %32 = load ptr, ptr %5, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.os_event, ptr %32, i32 0, i32 1
  %34 = load ptr, ptr %33, align 8, !tbaa !15
  store ptr %34, ptr %8, align 8, !tbaa !5
  %35 = load ptr, ptr %8, align 8, !tbaa !5
  %36 = icmp ne ptr %35, null
  br i1 %36, label %37, label %43

37:                                               ; preds = %30
  %38 = load ptr, ptr %5, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.os_event, ptr %38, i32 0, i32 1
  store ptr null, ptr %39, align 8, !tbaa !15
  %40 = load i32, ptr %9, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %40)
  %41 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %41, align 1, !tbaa !14
  %42 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %42, ptr %4, align 8
  store i32 1, ptr %10, align 4
  br label %85

43:                                               ; preds = %30
  %44 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.os_tcb, ptr %44, i32 0, i32 13
  %46 = load i8, ptr %45, align 8, !tbaa !16
  %47 = zext i8 %46 to i32
  %48 = or i32 %47, 2
  %49 = trunc i32 %48 to i8
  store i8 %49, ptr %45, align 8, !tbaa !16
  %50 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %51 = getelementptr inbounds %struct.os_tcb, ptr %50, i32 0, i32 14
  store i8 0, ptr %51, align 1, !tbaa !18
  %52 = load i32, ptr %6, align 4, !tbaa !9
  %53 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %54 = getelementptr inbounds %struct.os_tcb, ptr %53, i32 0, i32 12
  store i32 %52, ptr %54, align 4, !tbaa !19
  %55 = load ptr, ptr %5, align 8, !tbaa !5
  call void @OS_EventTaskWait(ptr noundef %55)
  %56 = load i32, ptr %9, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %56)
  call void @OS_Sched()
  %57 = call i32 @OS_CPU_SR_Save()
  store i32 %57, ptr %9, align 4, !tbaa !9
  %58 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.os_tcb, ptr %58, i32 0, i32 14
  %60 = load i8, ptr %59, align 1, !tbaa !18
  %61 = zext i8 %60 to i32
  switch i32 %61, label %70 [
    i32 0, label %62
    i32 2, label %67
    i32 1, label %69
  ]

62:                                               ; preds = %43
  %63 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.os_tcb, ptr %63, i32 0, i32 9
  %65 = load ptr, ptr %64, align 8, !tbaa !20
  store ptr %65, ptr %8, align 8, !tbaa !5
  %66 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %66, align 1, !tbaa !14
  br label %74

67:                                               ; preds = %43
  store ptr null, ptr %8, align 8, !tbaa !5
  %68 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 14, ptr %68, align 1, !tbaa !14
  br label %74

69:                                               ; preds = %43
  br label %70

70:                                               ; preds = %69, %43
  %71 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %72 = load ptr, ptr %5, align 8, !tbaa !5
  call void @OS_EventTaskRemove(ptr noundef %71, ptr noundef %72)
  store ptr null, ptr %8, align 8, !tbaa !5
  %73 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 10, ptr %73, align 1, !tbaa !14
  br label %74

74:                                               ; preds = %70, %67, %62
  %75 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.os_tcb, ptr %75, i32 0, i32 13
  store i8 0, ptr %76, align 8, !tbaa !16
  %77 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %78 = getelementptr inbounds %struct.os_tcb, ptr %77, i32 0, i32 14
  store i8 0, ptr %78, align 1, !tbaa !18
  %79 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.os_tcb, ptr %79, i32 0, i32 8
  store ptr null, ptr %80, align 8, !tbaa !21
  %81 = load ptr, ptr @OSTCBCur, align 8, !tbaa !5
  %82 = getelementptr inbounds %struct.os_tcb, ptr %81, i32 0, i32 9
  store ptr null, ptr %82, align 8, !tbaa !20
  %83 = load i32, ptr %9, align 4, !tbaa !9
  call void @OS_CPU_SR_Restore(i32 noundef %83)
  %84 = load ptr, ptr %8, align 8, !tbaa !5
  store ptr %84, ptr %4, align 8
  store i32 1, ptr %10, align 4
  br label %85

85:                                               ; preds = %74, %37, %28, %22, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #3
  %86 = load ptr, ptr %4, align 8
  ret ptr %86
}

declare void @OS_EventTaskWait(ptr noundef) #1

declare void @OS_EventTaskRemove(ptr noundef, ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 0}
!12 = !{!"os_event", !7, i64 0, !6, i64 8, !13, i64 16, !7, i64 18, !7, i64 19}
!13 = !{!"short", !7, i64 0}
!14 = !{!7, !7, i64 0}
!15 = !{!12, !6, i64 8}
!16 = !{!17, !7, i64 80}
!17 = !{!"os_tcb", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !13, i64 28, !13, i64 30, !6, i64 32, !6, i64 40, !6, i64 48, !6, i64 56, !6, i64 64, !13, i64 72, !10, i64 76, !7, i64 80, !7, i64 81, !7, i64 82, !7, i64 83, !7, i64 84, !7, i64 85, !7, i64 86, !7, i64 87, !10, i64 88, !10, i64 92, !10, i64 96, !6, i64 104, !10, i64 112, !6, i64 120, !7, i64 128}
!18 = !{!17, !7, i64 81}
!19 = !{!17, !10, i64 76}
!20 = !{!17, !6, i64 56}
!21 = !{!17, !6, i64 48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSLockNesting = external local_unnamed_addr global i8, align 1
@OSTCBCur = external local_unnamed_addr global ptr, align 8

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

declare void @OS_Sched() local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSMboxPend(ptr noundef %0, i32 noundef %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #1 {
  %4 = load i8, ptr %0, align 8, !tbaa !5
  %.not = icmp eq i8 %4, 1
  br i1 %.not, label %6, label %5

5:                                                ; preds = %3
  store i8 1, ptr %2, align 1, !tbaa !11
  br label %37

6:                                                ; preds = %3
  %7 = load i8, ptr @OSIntNesting, align 1, !tbaa !11
  %.not21 = icmp eq i8 %7, 0
  br i1 %.not21, label %9, label %8

8:                                                ; preds = %6
  store i8 2, ptr %2, align 1, !tbaa !11
  br label %37

9:                                                ; preds = %6
  %10 = load i8, ptr @OSLockNesting, align 1, !tbaa !11
  %.not22 = icmp eq i8 %10, 0
  br i1 %.not22, label %12, label %11

11:                                               ; preds = %9
  store i8 13, ptr %2, align 1, !tbaa !11
  br label %37

12:                                               ; preds = %9
  %13 = tail call i32 @OS_CPU_SR_Save() #3
  %14 = getelementptr inbounds i8, ptr %0, i64 8
  %15 = load ptr, ptr %14, align 8, !tbaa !12
  %.not23 = icmp eq ptr %15, null
  br i1 %.not23, label %17, label %16

16:                                               ; preds = %12
  store ptr null, ptr %14, align 8, !tbaa !12
  tail call void @OS_CPU_SR_Restore(i32 noundef %13) #3
  store i8 0, ptr %2, align 1, !tbaa !11
  br label %37

17:                                               ; preds = %12
  %18 = load ptr, ptr @OSTCBCur, align 8, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %18, i64 80
  %20 = load i8, ptr %19, align 8, !tbaa !14
  %21 = or i8 %20, 2
  store i8 %21, ptr %19, align 8, !tbaa !14
  %22 = getelementptr inbounds i8, ptr %18, i64 81
  store i8 0, ptr %22, align 1, !tbaa !17
  %23 = getelementptr inbounds i8, ptr %18, i64 76
  store i32 %1, ptr %23, align 4, !tbaa !18
  tail call void @OS_EventTaskWait(ptr noundef nonnull %0) #3
  tail call void @OS_CPU_SR_Restore(i32 noundef %13) #3
  tail call void @OS_Sched() #3
  %24 = tail call i32 @OS_CPU_SR_Save() #3
  %25 = load ptr, ptr @OSTCBCur, align 8, !tbaa !13
  %26 = getelementptr inbounds i8, ptr %25, i64 81
  %27 = load i8, ptr %26, align 1, !tbaa !17
  switch i8 %27, label %31 [
    i8 0, label %28
    i8 2, label %32
  ]

28:                                               ; preds = %17
  %29 = getelementptr inbounds i8, ptr %25, i64 56
  %30 = load ptr, ptr %29, align 8, !tbaa !19
  br label %32

31:                                               ; preds = %17
  tail call void @OS_EventTaskRemove(ptr noundef nonnull %25, ptr noundef nonnull %0) #3
  br label %32

32:                                               ; preds = %17, %31, %28
  %.sink = phi i8 [ 10, %31 ], [ 0, %28 ], [ 14, %17 ]
  %.0 = phi ptr [ null, %31 ], [ %30, %28 ], [ null, %17 ]
  store i8 %.sink, ptr %2, align 1, !tbaa !11
  %33 = load ptr, ptr @OSTCBCur, align 8, !tbaa !13
  %34 = getelementptr inbounds i8, ptr %33, i64 80
  store i8 0, ptr %34, align 8, !tbaa !14
  %35 = getelementptr inbounds i8, ptr %33, i64 81
  store i8 0, ptr %35, align 1, !tbaa !17
  %36 = getelementptr inbounds i8, ptr %33, i64 48
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(16) %36, i8 0, i64 16, i1 false)
  tail call void @OS_CPU_SR_Restore(i32 noundef %24) #3
  br label %37

37:                                               ; preds = %32, %16, %11, %8, %5
  %.019 = phi ptr [ null, %5 ], [ null, %8 ], [ null, %11 ], [ %15, %16 ], [ %.0, %32 ]
  ret ptr %.019
}

declare void @OS_EventTaskWait(ptr noundef) local_unnamed_addr #0

declare void @OS_EventTaskRemove(ptr noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"os_event", !7, i64 0, !9, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"any pointer", !7, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !9, i64 8}
!13 = !{!9, !9, i64 0}
!14 = !{!15, !7, i64 80}
!15 = !{!"os_tcb", !9, i64 0, !9, i64 8, !9, i64 16, !16, i64 24, !10, i64 28, !10, i64 30, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !9, i64 64, !10, i64 72, !16, i64 76, !7, i64 80, !7, i64 81, !7, i64 82, !7, i64 83, !7, i64 84, !7, i64 85, !7, i64 86, !7, i64 87, !16, i64 88, !16, i64 92, !16, i64 96, !9, i64 104, !16, i64 112, !9, i64 120, !7, i64 128}
!16 = !{!"int", !7, i64 0}
!17 = !{!15, !7, i64 81}
!18 = !{!15, !16, i64 76}
!19 = !{!15, !9, i64 56}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass