; LLVM IR from cvra/robot-software :: uwb-beacon-firmware/src/decadriver (deca_device)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @_dwt_enableclocks(i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpread(i64 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpsetmrregs(i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpprogword32(i64 noundef, i16 noundef zeroext) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @dwt_otpwriteandverify(i64 noundef %0, i16 noundef zeroext %1) #1 {
  %3 = alloca i64, align 8
  %4 = alloca i16, align 2
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i64 %0, ptr %3, align 8, !tbaa !5
  store i16 %1, ptr %4, align 2, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !11
  call void @_dwt_enableclocks(i32 noundef 0)
  %7 = call i64 @_dwt_otpsetmrregs(i32 noundef 1)
  br label %8

8:                                                ; preds = %25, %2
  br label %9

9:                                                ; preds = %8
  %10 = load i64, ptr %3, align 8, !tbaa !5
  %11 = load i16, ptr %4, align 2, !tbaa !9
  %12 = call i64 @_dwt_otpprogword32(i64 noundef %10, i16 noundef zeroext %11)
  %13 = load i16, ptr %4, align 2, !tbaa !9
  %14 = zext i16 %13 to i64
  %15 = call i64 @_dwt_otpread(i64 noundef %14)
  %16 = load i64, ptr %3, align 8, !tbaa !5
  %17 = icmp eq i64 %15, %16
  br i1 %17, label %18, label %19

18:                                               ; preds = %9
  br label %26

19:                                               ; preds = %9
  %20 = load i32, ptr %6, align 4, !tbaa !11
  %21 = add nsw i32 %20, 1
  store i32 %21, ptr %6, align 4, !tbaa !11
  %22 = load i32, ptr %6, align 4, !tbaa !11
  %23 = icmp eq i32 %22, 5
  br i1 %23, label %24, label %25

24:                                               ; preds = %19
  br label %26

25:                                               ; preds = %19
  br label %8

26:                                               ; preds = %24, %18
  %27 = call i64 @_dwt_otpsetmrregs(i32 noundef 4)
  %28 = load i16, ptr %4, align 2, !tbaa !9
  %29 = zext i16 %28 to i64
  %30 = call i64 @_dwt_otpread(i64 noundef %29)
  %31 = load i64, ptr %3, align 8, !tbaa !5
  %32 = icmp ne i64 %30, %31
  br i1 %32, label %33, label %34

33:                                               ; preds = %26
  store i32 -1, ptr %5, align 4, !tbaa !11
  br label %34

34:                                               ; preds = %33, %26
  %35 = call i64 @_dwt_otpsetmrregs(i32 noundef 0)
  %36 = load i32, ptr %5, align 4, !tbaa !11
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret i32 %36
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @_dwt_enableclocks(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpread(i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpsetmrregs(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @_dwt_otpprogword32(i64 noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 -1, 1) i32 @dwt_otpwriteandverify(i64 noundef %0, i16 noundef zeroext %1) local_unnamed_addr #0 {
  tail call void @_dwt_enableclocks(i32 noundef 0)
  %3 = tail call i64 @_dwt_otpsetmrregs(i32 noundef 1)
  %4 = zext i16 %1 to i64
  br label %5

5:                                                ; preds = %5, %2
  %.0 = phi i32 [ 0, %2 ], [ %9, %5 ]
  %6 = tail call i64 @_dwt_otpprogword32(i64 noundef %0, i16 noundef zeroext %1)
  %7 = tail call i64 @_dwt_otpread(i64 noundef %4)
  %8 = icmp eq i64 %7, %0
  %9 = add nuw nsw i32 %.0, 1
  %10 = icmp eq i32 %9, 5
  %or.cond = select i1 %8, i1 true, i1 %10
  br i1 %or.cond, label %11, label %5

11:                                               ; preds = %5
  %12 = tail call i64 @_dwt_otpsetmrregs(i32 noundef 4)
  %13 = tail call i64 @_dwt_otpread(i64 noundef %4)
  %.not = icmp ne i64 %13, %0
  %spec.select = sext i1 %.not to i32
  %14 = tail call i64 @_dwt_otpsetmrregs(i32 noundef 0)
  ret i32 %spec.select
}

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,SROAPass,SimplifyCFGPass,TailCallElimPass