; LLVM IR from cvra/robot-software :: uwb-beacon-firmware/src/decadriver (deca_device)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @dwt_read16bitoffsetreg(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @dwt_read8bitoffsetreg(i32 noundef, i32 noundef) #1

declare void @deca_sleep(i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i64 @dwt_calcbandwidthtempadj(i16 noundef zeroext %0) #1 {
  %2 = alloca i16, align 2
  %3 = alloca i32, align 4
  %4 = alloca i64, align 8
  %5 = alloca i64, align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca i16, align 2
  %9 = alloca i64, align 8
  %10 = alloca i8, align 1
  %11 = alloca i16, align 2
  %12 = alloca i64, align 8
  store i16 %0, ptr %2, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  store i64 0, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #4
  store i16 0, ptr %8, align 2, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.start.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #4
  %13 = call zeroext i8 @dwt_read8bitoffsetreg(i32 noundef 54, i32 noundef 0)
  store i8 %13, ptr %10, align 1, !tbaa !11
  %14 = call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 54, i32 noundef 4)
  store i16 %14, ptr %11, align 2, !tbaa !5
  %15 = call i64 @dwt_read32bitoffsetreg(i32 noundef 40, i32 noundef 0)
  store i64 %15, ptr %12, align 8, !tbaa !9
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 1)
  call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext 0)
  call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef 2074368)
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 34)
  store i64 128, ptr %5, align 8, !tbaa !9
  store i64 128, ptr %4, align 8, !tbaa !9
  store i64 300, ptr %9, align 8, !tbaa !9
  store i32 0, ptr %3, align 4, !tbaa !12
  br label %16

16:                                               ; preds = %60, %1
  %17 = load i32, ptr %3, align 4, !tbaa !12
  %18 = icmp slt i32 %17, 7
  br i1 %18, label %19, label %63

19:                                               ; preds = %16
  %20 = load i64, ptr %4, align 8, !tbaa !9
  %21 = lshr i64 %20, 1
  store i64 %21, ptr %4, align 8, !tbaa !9
  %22 = load i64, ptr %5, align 8, !tbaa !9
  %23 = load i64, ptr %4, align 8, !tbaa !9
  %24 = or i64 %22, %23
  store i64 %24, ptr %5, align 8, !tbaa !9
  %25 = load i64, ptr %5, align 8, !tbaa !9
  %26 = trunc i64 %25 to i8
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %26)
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  call void @deca_sleep(i32 noundef 100)
  %27 = call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %28 = zext i16 %27 to i32
  %29 = and i32 %28, 4095
  %30 = trunc i32 %29 to i16
  store i16 %30, ptr %8, align 2, !tbaa !5
  %31 = load i16, ptr %8, align 2, !tbaa !5
  %32 = zext i16 %31 to i32
  %33 = load i16, ptr %2, align 2, !tbaa !5
  %34 = zext i16 %33 to i32
  %35 = sub nsw i32 %32, %34
  %36 = call i32 @llvm.abs.i32(i32 %35, i1 true)
  %37 = sext i32 %36 to i64
  store i64 %37, ptr %6, align 8, !tbaa !9
  %38 = load i64, ptr %6, align 8, !tbaa !9
  %39 = load i64, ptr %9, align 8, !tbaa !9
  %40 = icmp slt i64 %38, %39
  br i1 %40, label %41, label %44

41:                                               ; preds = %19
  %42 = load i64, ptr %6, align 8, !tbaa !9
  store i64 %42, ptr %9, align 8, !tbaa !9
  %43 = load i64, ptr %5, align 8, !tbaa !9
  store i64 %43, ptr %7, align 8, !tbaa !9
  br label %44

44:                                               ; preds = %41, %19
  %45 = load i16, ptr %8, align 2, !tbaa !5
  %46 = zext i16 %45 to i32
  %47 = load i16, ptr %2, align 2, !tbaa !5
  %48 = zext i16 %47 to i32
  %49 = icmp sgt i32 %46, %48
  br i1 %49, label %50, label %54

50:                                               ; preds = %44
  %51 = load i64, ptr %5, align 8, !tbaa !9
  %52 = load i64, ptr %4, align 8, !tbaa !9
  %53 = or i64 %51, %52
  store i64 %53, ptr %5, align 8, !tbaa !9
  br label %59

54:                                               ; preds = %44
  %55 = load i64, ptr %5, align 8, !tbaa !9
  %56 = load i64, ptr %4, align 8, !tbaa !9
  %57 = xor i64 %56, -1
  %58 = and i64 %55, %57
  store i64 %58, ptr %5, align 8, !tbaa !9
  br label %59

59:                                               ; preds = %54, %50
  br label %60

60:                                               ; preds = %59
  %61 = load i32, ptr %3, align 4, !tbaa !12
  %62 = add nsw i32 %61, 1
  store i32 %62, ptr %3, align 4, !tbaa !12
  br label %16, !llvm.loop !14

63:                                               ; preds = %16
  %64 = load i8, ptr %10, align 1, !tbaa !11
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext %64)
  %65 = load i16, ptr %11, align 2, !tbaa !5
  call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext %65)
  %66 = load i64, ptr %12, align 8, !tbaa !9
  call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef %66)
  %67 = load i64, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %11) #4
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret i64 %67
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.abs.i32(i32, i1 immarg) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"short", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"int", !7, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @dwt_read16bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @dwt_read8bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @deca_sleep(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i64 @dwt_calcbandwidthtempadj(i16 noundef zeroext %0) local_unnamed_addr #0 {
  %2 = tail call zeroext i8 @dwt_read8bitoffsetreg(i32 noundef 54, i32 noundef 0)
  %3 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 54, i32 noundef 4)
  %4 = tail call i64 @dwt_read32bitoffsetreg(i32 noundef 40, i32 noundef 0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 1)
  tail call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext 0)
  tail call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef 2074368)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 34)
  %5 = zext i16 %0 to i32
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext -64)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %6 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %7 = and i16 %6, 4095
  %8 = zext nneg i16 %7 to i32
  %9 = sub nsw i32 %8, %5
  %10 = tail call i32 @llvm.abs.i32(i32 %9, i1 true)
  %11 = icmp ult i32 %10, 300
  %spec.select = select i1 %11, i64 192, i64 0
  %12 = tail call i32 @llvm.umin.i32(i32 %10, i32 300)
  %13 = icmp ugt i16 %7, %0
  %.1 = select i1 %13, i64 192, i64 128
  %14 = or disjoint i64 %.1, 32
  %15 = trunc nuw i64 %14 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %15)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %16 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %17 = and i16 %16, 4095
  %18 = zext nneg i16 %17 to i32
  %19 = sub nsw i32 %18, %5
  %20 = tail call i32 @llvm.abs.i32(i32 %19, i1 true)
  %21 = icmp ugt i32 %12, %20
  %spec.select.1 = select i1 %21, i64 %14, i64 %spec.select
  %22 = tail call i32 @llvm.umin.i32(i32 %12, i32 %20)
  %23 = icmp ugt i16 %17, %0
  %.1.1 = select i1 %23, i64 %14, i64 %.1
  %24 = or disjoint i64 %.1.1, 16
  %25 = trunc nuw i64 %24 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %25)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %26 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %27 = and i16 %26, 4095
  %28 = zext nneg i16 %27 to i32
  %29 = sub nsw i32 %28, %5
  %30 = tail call i32 @llvm.abs.i32(i32 %29, i1 true)
  %31 = icmp ugt i32 %22, %30
  %spec.select.2 = select i1 %31, i64 %24, i64 %spec.select.1
  %32 = tail call i32 @llvm.umin.i32(i32 %22, i32 %30)
  %33 = icmp ugt i16 %27, %0
  %.1.2 = select i1 %33, i64 %24, i64 %.1.1
  %34 = or disjoint i64 %.1.2, 8
  %35 = trunc nuw i64 %34 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %35)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %36 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %37 = and i16 %36, 4095
  %38 = zext nneg i16 %37 to i32
  %39 = sub nsw i32 %38, %5
  %40 = tail call i32 @llvm.abs.i32(i32 %39, i1 true)
  %41 = icmp ugt i32 %32, %40
  %spec.select.3 = select i1 %41, i64 %34, i64 %spec.select.2
  %42 = tail call i32 @llvm.umin.i32(i32 %32, i32 %40)
  %43 = icmp ugt i16 %37, %0
  %.1.3 = select i1 %43, i64 %34, i64 %.1.2
  %44 = or i64 %.1.3, 4
  %45 = trunc nuw i64 %44 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %45)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %46 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %47 = and i16 %46, 4095
  %48 = zext nneg i16 %47 to i32
  %49 = sub nsw i32 %48, %5
  %50 = tail call i32 @llvm.abs.i32(i32 %49, i1 true)
  %51 = icmp ugt i32 %42, %50
  %spec.select.4 = select i1 %51, i64 %44, i64 %spec.select.3
  %52 = tail call i32 @llvm.umin.i32(i32 %42, i32 %50)
  %53 = icmp ugt i16 %47, %0
  %54 = and i64 %.1.3, -5
  %.1.4 = select i1 %53, i64 %44, i64 %54
  %55 = or i64 %.1.4, 2
  %56 = trunc nuw i64 %55 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %56)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %57 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %58 = and i16 %57, 4095
  %59 = zext nneg i16 %58 to i32
  %60 = sub nsw i32 %59, %5
  %61 = tail call i32 @llvm.abs.i32(i32 %60, i1 true)
  %62 = icmp ugt i32 %52, %61
  %spec.select.5 = select i1 %62, i64 %55, i64 %spec.select.4
  %63 = tail call i32 @llvm.umin.i32(i32 %52, i32 %61)
  %64 = icmp ugt i16 %58, %0
  %65 = and i64 %.1.4, -4
  %.1.5 = select i1 %64, i64 %55, i64 %65
  %66 = or i64 %.1.5, 1
  %67 = trunc nuw i64 %66 to i8
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %67)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #4
  %68 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %69 = and i16 %68, 4095
  %70 = zext nneg i16 %69 to i32
  %71 = sub nsw i32 %70, %5
  %72 = tail call i32 @llvm.abs.i32(i32 %71, i1 true)
  %73 = icmp ugt i32 %63, %72
  %spec.select.6 = select i1 %73, i64 %66, i64 %spec.select.5
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext %2)
  tail call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext %3)
  tail call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef %4)
  ret i64 %spec.select.6
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.abs.i32(i32, i1 immarg) #2

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #3

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LICMPass,LoopRotatePass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass