; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_mbox)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_event = type { i8, ptr, i16, i8, [8 x i8] }

@OSIntNesting = external global i8, align 1
@OSEventFreeList = external global ptr, align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @OS_CPU_SR_Save() #1

declare void @OS_CPU_SR_Restore(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local ptr @OSMboxDel(ptr noundef %0, i8 noundef zeroext %1, ptr noundef %2) #2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i8, align 1
  %7 = alloca ptr, align 8
  %8 = alloca i8, align 1
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i8 %1, ptr %6, align 1, !tbaa !9
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #3
  store i32 0, ptr %10, align 4, !tbaa !10
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = getelementptr inbounds %struct.os_event, ptr %12, i32 0, i32 0
  %14 = load i8, ptr %13, align 8, !tbaa !12
  %15 = zext i8 %14 to i32
  %16 = icmp ne i32 %15, 1
  br i1 %16, label %17, label %20

17:                                               ; preds = %3
  %18 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 1, ptr %18, align 1, !tbaa !9
  %19 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %19, ptr %4, align 8
  store i32 1, ptr %11, align 4
  br label %91

20:                                               ; preds = %3
  %21 = load i8, ptr @OSIntNesting, align 1, !tbaa !9
  %22 = zext i8 %21 to i32
  %23 = icmp ugt i32 %22, 0
  br i1 %23, label %24, label %27

24:                                               ; preds = %20
  %25 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 15, ptr %25, align 1, !tbaa !9
  %26 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %26, ptr %4, align 8
  store i32 1, ptr %11, align 4
  br label %91

27:                                               ; preds = %20
  %28 = call i32 @OS_CPU_SR_Save()
  store i32 %28, ptr %10, align 4, !tbaa !10
  %29 = load ptr, ptr %5, align 8, !tbaa !5
  %30 = getelementptr inbounds %struct.os_event, ptr %29, i32 0, i32 3
  %31 = load i8, ptr %30, align 2, !tbaa !15
  %32 = zext i8 %31 to i32
  %33 = icmp ne i32 %32, 0
  br i1 %33, label %34, label %35

34:                                               ; preds = %27
  store i8 1, ptr %8, align 1, !tbaa !9
  br label %36

35:                                               ; preds = %27
  store i8 0, ptr %8, align 1, !tbaa !9
  br label %36

36:                                               ; preds = %35, %34
  %37 = load i8, ptr %6, align 1, !tbaa !9
  %38 = zext i8 %37 to i32
  switch i32 %38, label %85 [
    i32 0, label %39
    i32 1, label %59
  ]

39:                                               ; preds = %36
  %40 = load i8, ptr %8, align 1, !tbaa !9
  %41 = zext i8 %40 to i32
  %42 = icmp eq i32 %41, 0
  br i1 %42, label %43, label %54

43:                                               ; preds = %39
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  %45 = getelementptr inbounds %struct.os_event, ptr %44, i32 0, i32 0
  store i8 0, ptr %45, align 8, !tbaa !12
  %46 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %47 = load ptr, ptr %5, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.os_event, ptr %47, i32 0, i32 1
  store ptr %46, ptr %48, align 8, !tbaa !16
  %49 = load ptr, ptr %5, align 8, !tbaa !5
  %50 = getelementptr inbounds %struct.os_event, ptr %49, i32 0, i32 2
  store i16 0, ptr %50, align 8, !tbaa !17
  %51 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %51, ptr @OSEventFreeList, align 8, !tbaa !5
  %52 = load i32, ptr %10, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %52)
  %53 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %53, align 1, !tbaa !9
  store ptr null, ptr %9, align 8, !tbaa !5
  br label %58

54:                                               ; preds = %39
  %55 = load i32, ptr %10, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %55)
  %56 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 73, ptr %56, align 1, !tbaa !9
  %57 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %57, ptr %9, align 8, !tbaa !5
  br label %58

58:                                               ; preds = %54, %43
  br label %89

59:                                               ; preds = %36
  br label %60

60:                                               ; preds = %66, %59
  %61 = load ptr, ptr %5, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.os_event, ptr %61, i32 0, i32 3
  %63 = load i8, ptr %62, align 2, !tbaa !15
  %64 = zext i8 %63 to i32
  %65 = icmp ne i32 %64, 0
  br i1 %65, label %66, label %69

66:                                               ; preds = %60
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = call zeroext i8 @OS_EventTaskRdy(ptr noundef %67, ptr noundef null, i8 noundef zeroext 2, i8 noundef zeroext 0)
  br label %60, !llvm.loop !18

69:                                               ; preds = %60
  %70 = load ptr, ptr %5, align 8, !tbaa !5
  %71 = getelementptr inbounds %struct.os_event, ptr %70, i32 0, i32 0
  store i8 0, ptr %71, align 8, !tbaa !12
  %72 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !5
  %73 = load ptr, ptr %5, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.os_event, ptr %73, i32 0, i32 1
  store ptr %72, ptr %74, align 8, !tbaa !16
  %75 = load ptr, ptr %5, align 8, !tbaa !5
  %76 = getelementptr inbounds %struct.os_event, ptr %75, i32 0, i32 2
  store i16 0, ptr %76, align 8, !tbaa !17
  %77 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %77, ptr @OSEventFreeList, align 8, !tbaa !5
  %78 = load i32, ptr %10, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %78)
  %79 = load i8, ptr %8, align 1, !tbaa !9
  %80 = zext i8 %79 to i32
  %81 = icmp eq i32 %80, 1
  br i1 %81, label %82, label %83

82:                                               ; preds = %69
  call void @OS_Sched()
  br label %83

83:                                               ; preds = %82, %69
  %84 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 0, ptr %84, align 1, !tbaa !9
  store ptr null, ptr %9, align 8, !tbaa !5
  br label %89

85:                                               ; preds = %36
  %86 = load i32, ptr %10, align 4, !tbaa !10
  call void @OS_CPU_SR_Restore(i32 noundef %86)
  %87 = load ptr, ptr %7, align 8, !tbaa !5
  store i8 7, ptr %87, align 1, !tbaa !9
  %88 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %88, ptr %9, align 8, !tbaa !5
  br label %89

89:                                               ; preds = %85, %83, %58
  %90 = load ptr, ptr %9, align 8, !tbaa !5
  store ptr %90, ptr %4, align 8
  store i32 1, ptr %11, align 4
  br label %91

91:                                               ; preds = %89, %24, %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  %92 = load ptr, ptr %4, align 8
  ret ptr %92
}

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) #1

declare void @OS_Sched() #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !7, i64 0}
!13 = !{!"os_event", !7, i64 0, !6, i64 8, !14, i64 16, !7, i64 18, !7, i64 19}
!14 = !{!"short", !7, i64 0}
!15 = !{!13, !7, i64 18}
!16 = !{!13, !6, i64 8}
!17 = !{!13, !14, i64 16}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSEventFreeList = external local_unnamed_addr global ptr, align 8

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #0

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local noundef ptr @OSMboxDel(ptr noundef %0, i8 noundef zeroext %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #1 {
  %4 = load i8, ptr %0, align 8, !tbaa !5
  %.not = icmp eq i8 %4, 1
  br i1 %.not, label %5, label %26

5:                                                ; preds = %3
  %6 = load i8, ptr @OSIntNesting, align 1, !tbaa !11
  %.not32 = icmp eq i8 %6, 0
  br i1 %.not32, label %7, label %26

7:                                                ; preds = %5
  %8 = tail call i32 @OS_CPU_SR_Save() #2
  %9 = getelementptr inbounds i8, ptr %0, i64 18
  %10 = load i8, ptr %9, align 2, !tbaa !12
  %.not33.not = icmp eq i8 %10, 0
  switch i8 %1, label %25 [
    i8 0, label %11
    i8 1, label %.preheader
  ]

.preheader:                                       ; preds = %7
  br i1 %.not33.not, label %.critedge, label %.lr.ph

11:                                               ; preds = %7
  br i1 %.not33.not, label %12, label %16

12:                                               ; preds = %11
  store i8 0, ptr %0, align 8, !tbaa !5
  %13 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !13
  %14 = getelementptr inbounds i8, ptr %0, i64 8
  store ptr %13, ptr %14, align 8, !tbaa !14
  %15 = getelementptr inbounds i8, ptr %0, i64 16
  store i16 0, ptr %15, align 8, !tbaa !15
  store ptr %0, ptr @OSEventFreeList, align 8, !tbaa !13
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %26

16:                                               ; preds = %11
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %26

.lr.ph:                                           ; preds = %.preheader, %.lr.ph
  %17 = tail call zeroext i8 @OS_EventTaskRdy(ptr noundef nonnull %0, ptr noundef null, i8 noundef zeroext 2, i8 noundef zeroext 0) #2
  %.pr = load i8, ptr %9, align 2, !tbaa !12
  %.not34 = icmp eq i8 %.pr, 0
  br i1 %.not34, label %._crit_edge, label %.lr.ph, !llvm.loop !16

._crit_edge:                                      ; preds = %.lr.ph
  store i8 0, ptr %0, align 8, !tbaa !5
  %18 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !13
  %19 = getelementptr inbounds i8, ptr %0, i64 8
  store ptr %18, ptr %19, align 8, !tbaa !14
  %20 = getelementptr inbounds i8, ptr %0, i64 16
  store i16 0, ptr %20, align 8, !tbaa !15
  store ptr %0, ptr @OSEventFreeList, align 8, !tbaa !13
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br i1 %.not33.not, label %26, label %21

21:                                               ; preds = %._crit_edge
  tail call void @OS_Sched() #2
  br label %26

.critedge:                                        ; preds = %.preheader
  store i8 0, ptr %0, align 8, !tbaa !5
  %22 = load ptr, ptr @OSEventFreeList, align 8, !tbaa !13
  %23 = getelementptr inbounds i8, ptr %0, i64 8
  store ptr %22, ptr %23, align 8, !tbaa !14
  %24 = getelementptr inbounds i8, ptr %0, i64 16
  store i16 0, ptr %24, align 8, !tbaa !15
  store ptr %0, ptr @OSEventFreeList, align 8, !tbaa !13
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %26

25:                                               ; preds = %7
  tail call void @OS_CPU_SR_Restore(i32 noundef %8) #2
  br label %26

26:                                               ; preds = %._crit_edge, %21, %.critedge, %5, %3, %25, %16, %12
  %.sink = phi i8 [ 7, %25 ], [ 73, %16 ], [ 0, %12 ], [ 1, %3 ], [ 15, %5 ], [ 0, %.critedge ], [ 0, %21 ], [ 0, %._crit_edge ]
  %.031 = phi ptr [ %0, %25 ], [ %0, %16 ], [ null, %12 ], [ %0, %3 ], [ %0, %5 ], [ null, %.critedge ], [ null, %21 ], [ null, %._crit_edge ]
  store i8 %.sink, ptr %2, align 1, !tbaa !11
  ret ptr %.031
}

declare zeroext i8 @OS_EventTaskRdy(ptr noundef, ptr noundef, i8 noundef zeroext, i8 noundef zeroext) local_unnamed_addr #0

declare void @OS_Sched() local_unnamed_addr #0

attributes #0 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"os_event", !7, i64 0, !9, i64 8, !10, i64 16, !7, i64 18, !7, i64 19}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!"any pointer", !7, i64 0}
!10 = !{!"short", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!6, !7, i64 18}
!13 = !{!9, !9, i64 0}
!14 = !{!6, !9, i64 8}
!15 = !{!6, !10, i64 16}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass