; LLVM IR from HANDS-FREE/OpenRE :: 3_OS/STM32F1/RTOS/uCOS-II/CORE (os_time)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.os_tcb = type { ptr, ptr, ptr, i32, i16, i16, ptr, ptr, ptr, ptr, ptr, i16, i32, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, ptr, i32, ptr, [1 x i32] }

@OSIntNesting = external global i8, align 1
@OSLockNesting = external global i8, align 1
@OSTCBCur = external global ptr, align 8
@OSRdyTbl = external global [8 x i8], align 1
@OSRdyGrp = external global i8, align 1

; Function Attrs: nounwind uwtable
define dso_local void @OSTimeDly(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i8, align 1
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr %3) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !5
  %6 = load i8, ptr @OSIntNesting, align 1, !tbaa !9
  %7 = zext i8 %6 to i32
  %8 = icmp ugt i32 %7, 0
  br i1 %8, label %9, label %10

9:                                                ; preds = %1
  store i32 1, ptr %5, align 4
  br label %61

10:                                               ; preds = %1
  %11 = load i8, ptr @OSLockNesting, align 1, !tbaa !9
  %12 = zext i8 %11 to i32
  %13 = icmp ugt i32 %12, 0
  br i1 %13, label %14, label %15

14:                                               ; preds = %10
  store i32 1, ptr %5, align 4
  br label %61

15:                                               ; preds = %10
  %16 = load i32, ptr %2, align 4, !tbaa !5
  %17 = icmp ugt i32 %16, 0
  br i1 %17, label %18, label %60

18:                                               ; preds = %15
  %19 = call i32 @OS_CPU_SR_Save()
  store i32 %19, ptr %4, align 4, !tbaa !5
  %20 = load ptr, ptr @OSTCBCur, align 8, !tbaa !10
  %21 = getelementptr inbounds %struct.os_tcb, ptr %20, i32 0, i32 17
  %22 = load i8, ptr %21, align 4, !tbaa !12
  store i8 %22, ptr %3, align 1, !tbaa !9
  %23 = load ptr, ptr @OSTCBCur, align 8, !tbaa !10
  %24 = getelementptr inbounds %struct.os_tcb, ptr %23, i32 0, i32 18
  %25 = load i8, ptr %24, align 1, !tbaa !15
  %26 = zext i8 %25 to i32
  %27 = xor i32 %26, -1
  %28 = trunc i32 %27 to i8
  %29 = zext i8 %28 to i32
  %30 = load i8, ptr %3, align 1, !tbaa !9
  %31 = zext i8 %30 to i64
  %32 = getelementptr inbounds [8 x i8], ptr @OSRdyTbl, i64 0, i64 %31
  %33 = load i8, ptr %32, align 1, !tbaa !9
  %34 = zext i8 %33 to i32
  %35 = and i32 %34, %29
  %36 = trunc i32 %35 to i8
  store i8 %36, ptr %32, align 1, !tbaa !9
  %37 = load i8, ptr %3, align 1, !tbaa !9
  %38 = zext i8 %37 to i64
  %39 = getelementptr inbounds [8 x i8], ptr @OSRdyTbl, i64 0, i64 %38
  %40 = load i8, ptr %39, align 1, !tbaa !9
  %41 = zext i8 %40 to i32
  %42 = icmp eq i32 %41, 0
  br i1 %42, label %43, label %55

43:                                               ; preds = %18
  %44 = load ptr, ptr @OSTCBCur, align 8, !tbaa !10
  %45 = getelementptr inbounds %struct.os_tcb, ptr %44, i32 0, i32 19
  %46 = load i8, ptr %45, align 2, !tbaa !16
  %47 = zext i8 %46 to i32
  %48 = xor i32 %47, -1
  %49 = trunc i32 %48 to i8
  %50 = zext i8 %49 to i32
  %51 = load i8, ptr @OSRdyGrp, align 1, !tbaa !9
  %52 = zext i8 %51 to i32
  %53 = and i32 %52, %50
  %54 = trunc i32 %53 to i8
  store i8 %54, ptr @OSRdyGrp, align 1, !tbaa !9
  br label %55

55:                                               ; preds = %43, %18
  %56 = load i32, ptr %2, align 4, !tbaa !5
  %57 = load ptr, ptr @OSTCBCur, align 8, !tbaa !10
  %58 = getelementptr inbounds %struct.os_tcb, ptr %57, i32 0, i32 12
  store i32 %56, ptr %58, align 4, !tbaa !17
  %59 = load i32, ptr %4, align 4, !tbaa !5
  call void @OS_CPU_SR_Restore(i32 noundef %59)
  call void @OS_Sched()
  br label %60

60:                                               ; preds = %55, %15
  store i32 0, ptr %5, align 4
  br label %61

61:                                               ; preds = %60, %14, %9
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %3) #3
  %62 = load i32, ptr %5, align 4
  switch i32 %62, label %64 [
    i32 0, label %63
    i32 1, label %63
  ]

63:                                               ; preds = %61, %61
  ret void

64:                                               ; preds = %61
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @OS_CPU_SR_Save() #2

declare void @OS_CPU_SR_Restore(i32 noundef) #2

declare void @OS_Sched() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"any pointer", !7, i64 0}
!12 = !{!13, !7, i64 84}
!13 = !{!"os_tcb", !11, i64 0, !11, i64 8, !11, i64 16, !6, i64 24, !14, i64 28, !14, i64 30, !11, i64 32, !11, i64 40, !11, i64 48, !11, i64 56, !11, i64 64, !14, i64 72, !6, i64 76, !7, i64 80, !7, i64 81, !7, i64 82, !7, i64 83, !7, i64 84, !7, i64 85, !7, i64 86, !7, i64 87, !6, i64 88, !6, i64 92, !6, i64 96, !11, i64 104, !6, i64 112, !11, i64 120, !7, i64 128}
!14 = !{!"short", !7, i64 0}
!15 = !{!13, !7, i64 85}
!16 = !{!13, !7, i64 86}
!17 = !{!13, !6, i64 76}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@OSIntNesting = external local_unnamed_addr global i8, align 1
@OSLockNesting = external local_unnamed_addr global i8, align 1
@OSTCBCur = external local_unnamed_addr global ptr, align 8
@OSRdyTbl = external local_unnamed_addr global [8 x i8], align 1
@OSRdyGrp = external local_unnamed_addr global i8, align 1

; Function Attrs: nounwind uwtable
define dso_local void @OSTimeDly(i32 noundef %0) local_unnamed_addr #0 {
  %2 = load i8, ptr @OSIntNesting, align 1, !tbaa !5
  %.not = icmp ne i8 %2, 0
  %3 = load i8, ptr @OSLockNesting, align 1
  %.not5 = icmp ne i8 %3, 0
  %or.cond.not8 = select i1 %.not, i1 true, i1 %.not5
  %.not6 = icmp eq i32 %0, 0
  %or.cond7 = or i1 %.not6, %or.cond.not8
  br i1 %or.cond7, label %25, label %4

4:                                                ; preds = %1
  %5 = tail call i32 @OS_CPU_SR_Save() #2
  %6 = load ptr, ptr @OSTCBCur, align 8, !tbaa !8
  %7 = getelementptr inbounds i8, ptr %6, i64 84
  %8 = load i8, ptr %7, align 4, !tbaa !10
  %9 = getelementptr inbounds i8, ptr %6, i64 85
  %10 = load i8, ptr %9, align 1, !tbaa !14
  %11 = xor i8 %10, -1
  %12 = zext i8 %8 to i64
  %13 = getelementptr inbounds [8 x i8], ptr @OSRdyTbl, i64 0, i64 %12
  %14 = load i8, ptr %13, align 1, !tbaa !5
  %15 = and i8 %14, %11
  store i8 %15, ptr %13, align 1, !tbaa !5
  %16 = icmp eq i8 %15, 0
  br i1 %16, label %17, label %23

17:                                               ; preds = %4
  %18 = getelementptr inbounds i8, ptr %6, i64 86
  %19 = load i8, ptr %18, align 2, !tbaa !15
  %20 = xor i8 %19, -1
  %21 = load i8, ptr @OSRdyGrp, align 1, !tbaa !5
  %22 = and i8 %21, %20
  store i8 %22, ptr @OSRdyGrp, align 1, !tbaa !5
  br label %23

23:                                               ; preds = %17, %4
  %24 = getelementptr inbounds i8, ptr %6, i64 76
  store i32 %0, ptr %24, align 4, !tbaa !16
  tail call void @OS_CPU_SR_Restore(i32 noundef %5) #2
  tail call void @OS_Sched() #2
  br label %25

25:                                               ; preds = %23, %1
  ret void
}

declare i32 @OS_CPU_SR_Save() local_unnamed_addr #1

declare void @OS_CPU_SR_Restore(i32 noundef) local_unnamed_addr #1

declare void @OS_Sched() local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !6, i64 0}
!10 = !{!11, !6, i64 84}
!11 = !{!"os_tcb", !9, i64 0, !9, i64 8, !9, i64 16, !12, i64 24, !13, i64 28, !13, i64 30, !9, i64 32, !9, i64 40, !9, i64 48, !9, i64 56, !9, i64 64, !13, i64 72, !12, i64 76, !6, i64 80, !6, i64 81, !6, i64 82, !6, i64 83, !6, i64 84, !6, i64 85, !6, i64 86, !6, i64 87, !12, i64 88, !12, i64 92, !12, i64 96, !9, i64 104, !12, i64 112, !9, i64 120, !6, i64 128}
!12 = !{!"int", !6, i64 0}
!13 = !{!"short", !6, i64 0}
!14 = !{!11, !6, i64 85}
!15 = !{!11, !6, i64 86}
!16 = !{!11, !12, i64 76}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass