; LLVM IR from asllop/AppOS :: serial/arch/pc32 (serial_arch)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @port_address(i8 noundef zeroext) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_databits(i32 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_stopbits(i32 noundef) #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_parity(i32 noundef) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @serial_init(i8 noundef zeroext %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i16, align 2
  %13 = alloca i32, align 4
  %14 = alloca i8, align 1
  store i8 %0, ptr %7, align 1, !tbaa !5
  store i32 %1, ptr %8, align 4, !tbaa !8
  store i32 %2, ptr %9, align 4, !tbaa !8
  store i32 %3, ptr %10, align 4, !tbaa !8
  store i32 %4, ptr %11, align 4, !tbaa !8
  %15 = load i32, ptr %11, align 4, !tbaa !8
  %16 = srem i32 115200, %15
  %17 = icmp ne i32 %16, 0
  br i1 %17, label %21, label %18

18:                                               ; preds = %5
  %19 = load i32, ptr %11, align 4, !tbaa !8
  %20 = icmp sle i32 %19, 0
  br i1 %20, label %21, label %22

21:                                               ; preds = %18, %5
  store i32 -506, ptr %6, align 4
  br label %64

22:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 2, ptr %12) #3
  %23 = load i32, ptr %11, align 4, !tbaa !8
  %24 = sdiv i32 115200, %23
  %25 = trunc i32 %24 to i16
  store i16 %25, ptr %12, align 2, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %26 = load i8, ptr %7, align 1, !tbaa !5
  %27 = call i32 @port_address(i8 noundef zeroext %26)
  store i32 %27, ptr %13, align 4, !tbaa !8
  %28 = load i32, ptr %13, align 4, !tbaa !8
  %29 = add i32 %28, 1
  call void @outportb(i32 noundef %29, i8 noundef zeroext 0)
  %30 = load i32, ptr %13, align 4, !tbaa !8
  %31 = add i32 %30, 3
  call void @outportb(i32 noundef %31, i8 noundef zeroext -128)
  %32 = load i32, ptr %13, align 4, !tbaa !8
  %33 = add i32 %32, 0
  %34 = load i16, ptr %12, align 2, !tbaa !10
  %35 = zext i16 %34 to i32
  %36 = and i32 %35, 255
  %37 = trunc i32 %36 to i8
  call void @outportb(i32 noundef %33, i8 noundef zeroext %37)
  %38 = load i32, ptr %13, align 4, !tbaa !8
  %39 = add i32 %38, 1
  %40 = load i16, ptr %12, align 2, !tbaa !10
  %41 = zext i16 %40 to i32
  %42 = ashr i32 %41, 8
  %43 = and i32 %42, 255
  %44 = trunc i32 %43 to i8
  call void @outportb(i32 noundef %39, i8 noundef zeroext %44)
  call void @llvm.lifetime.start.p0(i64 1, ptr %14) #3
  %45 = load i32, ptr %8, align 4, !tbaa !8
  %46 = call zeroext i8 @port_databits(i32 noundef %45)
  %47 = zext i8 %46 to i32
  %48 = load i32, ptr %10, align 4, !tbaa !8
  %49 = call zeroext i8 @port_stopbits(i32 noundef %48)
  %50 = zext i8 %49 to i32
  %51 = or i32 %47, %50
  %52 = load i32, ptr %9, align 4, !tbaa !8
  %53 = call zeroext i8 @port_parity(i32 noundef %52)
  %54 = zext i8 %53 to i32
  %55 = or i32 %51, %54
  %56 = trunc i32 %55 to i8
  store i8 %56, ptr %14, align 1, !tbaa !5
  %57 = load i32, ptr %13, align 4, !tbaa !8
  %58 = add i32 %57, 3
  %59 = load i8, ptr %14, align 1, !tbaa !5
  call void @outportb(i32 noundef %58, i8 noundef zeroext %59)
  %60 = load i32, ptr %13, align 4, !tbaa !8
  %61 = add i32 %60, 2
  call void @outportb(i32 noundef %61, i8 noundef zeroext -57)
  %62 = load i32, ptr %13, align 4, !tbaa !8
  %63 = add i32 %62, 4
  call void @outportb(i32 noundef %63, i8 noundef zeroext 11)
  store i32 0, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 1, ptr %14) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %12) #3
  br label %64

64:                                               ; preds = %22, %21
  %65 = load i32, ptr %6, align 4
  ret i32 %65
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @outportb(i32 noundef, i8 noundef zeroext) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"short", !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local i32 @port_address(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_databits(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_stopbits(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @port_parity(i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local range(i32 -506, 1) i32 @serial_init(i8 noundef zeroext %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4) local_unnamed_addr #0 {
  %6 = srem i32 115200, %4
  %7 = icmp ne i32 %6, 0
  %8 = icmp slt i32 %4, 1
  %or.cond = or i1 %8, %7
  br i1 %or.cond, label %24, label %9

9:                                                ; preds = %5
  %10 = udiv i32 115200, %4
  %11 = tail call i32 @port_address(i8 noundef zeroext %0)
  %12 = add i32 %11, 1
  tail call void @outportb(i32 noundef %12, i8 noundef zeroext 0)
  %13 = add i32 %11, 3
  tail call void @outportb(i32 noundef %13, i8 noundef zeroext -128)
  %14 = trunc i32 %10 to i8
  tail call void @outportb(i32 noundef %11, i8 noundef zeroext %14)
  %15 = lshr i32 %10, 8
  %16 = trunc i32 %15 to i8
  tail call void @outportb(i32 noundef %12, i8 noundef zeroext %16)
  %17 = tail call zeroext i8 @port_databits(i32 noundef %1)
  %18 = tail call zeroext i8 @port_stopbits(i32 noundef %3)
  %19 = or i8 %18, %17
  %20 = tail call zeroext i8 @port_parity(i32 noundef %2)
  %21 = or i8 %19, %20
  tail call void @outportb(i32 noundef %13, i8 noundef zeroext %21)
  %22 = add i32 %11, 2
  tail call void @outportb(i32 noundef %22, i8 noundef zeroext -57)
  %23 = add i32 %11, 4
  tail call void @outportb(i32 noundef %23, i8 noundef zeroext 11)
  br label %24

24:                                               ; preds = %5, %9
  %.0 = phi i32 [ 0, %9 ], [ -506, %5 ]
  ret i32 %.0
}

; Function Attrs: inlinehint nounwind uwtable
declare hidden void @outportb(i32 noundef, i8 noundef zeroext) local_unnamed_addr #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass