; LLVM IR from cvra/robot-software :: uwb-beacon-firmware/src/decadriver (deca_device)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @dwt_read16bitoffsetreg(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @dwt_read8bitoffsetreg(i32 noundef, i32 noundef) #1

declare void @deca_sleep(i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @dwt_calcpgcount(i8 noundef zeroext %0) #1 {
  %2 = alloca i8, align 1
  %3 = alloca i32, align 4
  %4 = alloca i64, align 8
  %5 = alloca i16, align 2
  %6 = alloca i16, align 2
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i16, align 2
  %10 = alloca i64, align 8
  store i8 %0, ptr %2, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 10, ptr %3, align 4, !tbaa !8
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #3
  store i64 0, ptr %4, align 8, !tbaa !10
  call void @llvm.lifetime.start.p0(i64 2, ptr %5) #3
  store i16 0, ptr %5, align 2, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 2, ptr %6) #3
  store i16 0, ptr %6, align 2, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !8
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #3
  %11 = call zeroext i8 @dwt_read8bitoffsetreg(i32 noundef 54, i32 noundef 0)
  store i8 %11, ptr %8, align 1, !tbaa !5
  %12 = call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 54, i32 noundef 4)
  store i16 %12, ptr %9, align 2, !tbaa !12
  %13 = call i64 @dwt_read32bitoffsetreg(i32 noundef 40, i32 noundef 0)
  store i64 %13, ptr %10, align 8, !tbaa !10
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 1)
  call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext 0)
  call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef 2074368)
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 34)
  store i32 0, ptr %7, align 4, !tbaa !8
  br label %14

14:                                               ; preds = %27, %1
  %15 = load i32, ptr %7, align 4, !tbaa !8
  %16 = icmp slt i32 %15, 10
  br i1 %16, label %17, label %30

17:                                               ; preds = %14
  %18 = load i8, ptr %2, align 1, !tbaa !5
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %18)
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  call void @deca_sleep(i32 noundef 100)
  %19 = call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %20 = zext i16 %19 to i32
  %21 = and i32 %20, 4095
  %22 = trunc i32 %21 to i16
  store i16 %22, ptr %6, align 2, !tbaa !12
  %23 = load i16, ptr %6, align 2, !tbaa !12
  %24 = zext i16 %23 to i64
  %25 = load i64, ptr %4, align 8, !tbaa !10
  %26 = add i64 %25, %24
  store i64 %26, ptr %4, align 8, !tbaa !10
  br label %27

27:                                               ; preds = %17
  %28 = load i32, ptr %7, align 4, !tbaa !8
  %29 = add nsw i32 %28, 1
  store i32 %29, ptr %7, align 4, !tbaa !8
  br label %14, !llvm.loop !14

30:                                               ; preds = %14
  %31 = load i8, ptr %8, align 1, !tbaa !5
  call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext %31)
  %32 = load i16, ptr %9, align 2, !tbaa !12
  call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext %32)
  %33 = load i64, ptr %10, align 8, !tbaa !10
  call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef %33)
  %34 = load i64, ptr %4, align 8, !tbaa !10
  %35 = udiv i64 %34, 10
  %36 = trunc i64 %35 to i32
  %37 = trunc i32 %36 to i16
  store i16 %37, ptr %5, align 2, !tbaa !12
  %38 = load i16, ptr %5, align 2, !tbaa !12
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 2, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i16 %38
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !6, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !6, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"short", !6, i64 0}
!14 = distinct !{!14, !15}
!15 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write8bitoffsetreg(i32 noundef, i32 noundef, i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i16 @dwt_read16bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write16bitoffsetreg(i32 noundef, i32 noundef, i16 noundef zeroext) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local i64 @dwt_read32bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local void @dwt_write32bitoffsetreg(i32 noundef, i32 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare dso_local zeroext i8 @dwt_read8bitoffsetreg(i32 noundef, i32 noundef) local_unnamed_addr #0

declare void @deca_sleep(i32 noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local zeroext i16 @dwt_calcpgcount(i8 noundef zeroext %0) local_unnamed_addr #0 {
  %2 = tail call zeroext i8 @dwt_read8bitoffsetreg(i32 noundef 54, i32 noundef 0)
  %3 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 54, i32 noundef 4)
  %4 = tail call i64 @dwt_read32bitoffsetreg(i32 noundef 40, i32 noundef 0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 1)
  tail call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext 0)
  tail call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef 2074368)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext 34)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %5 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %6 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %7 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %8 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %9 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %10 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %11 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %12 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %13 = insertelement <8 x i16> poison, i16 %5, i64 0
  %14 = insertelement <8 x i16> %13, i16 %6, i64 1
  %15 = insertelement <8 x i16> %14, i16 %7, i64 2
  %16 = insertelement <8 x i16> %15, i16 %8, i64 3
  %17 = insertelement <8 x i16> %16, i16 %9, i64 4
  %18 = insertelement <8 x i16> %17, i16 %10, i64 5
  %19 = insertelement <8 x i16> %18, i16 %11, i64 6
  %20 = insertelement <8 x i16> %19, i16 %12, i64 7
  %21 = and <8 x i16> %20, <i16 4095, i16 4095, i16 4095, i16 4095, i16 4095, i16 4095, i16 4095, i16 4095>
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %22 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %23 = and i16 %22, 4095
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 11, i8 noundef zeroext %0)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -68)
  tail call void @dwt_write8bitoffsetreg(i32 noundef 42, i32 noundef 8, i8 noundef zeroext -67)
  tail call void @deca_sleep(i32 noundef 100) #3
  %24 = tail call zeroext i16 @dwt_read16bitoffsetreg(i32 noundef 42, i32 noundef 9)
  %25 = and i16 %24, 4095
  %26 = tail call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %21)
  %op.rdx = add i16 %26, %23
  %op.rdx17 = add i16 %op.rdx, %25
  tail call void @dwt_write8bitoffsetreg(i32 noundef 54, i32 noundef 0, i8 noundef zeroext %2)
  tail call void @dwt_write16bitoffsetreg(i32 noundef 54, i32 noundef 4, i16 noundef zeroext %3)
  tail call void @dwt_write32bitoffsetreg(i32 noundef 40, i32 noundef 0, i64 noundef %4)
  %27 = udiv i16 %op.rdx17, 10
  ret i16 %27
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #2

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: CorrelatedValuePropagationPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LCSSAPass,LoopRotatePass,ReassociatePass,SCCPPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass,TailCallElimPass