; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_driver)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_device = type { %struct.inv_imu_transport, ptr, [4128 x i8], i8, i8, i8, i32, i64, i64 }
%struct.inv_imu_transport = type { %struct.inv_imu_serif, %struct.register_cache, i8 }
%struct.inv_imu_serif = type { ptr, ptr, ptr, i32, i32, i32 }
%struct.register_cache = type { i8, i8, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_rcosc(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_wuosc(ptr noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_reset_fifo(ptr noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_disable_gyro(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  %14 = load ptr, ptr %2, align 8, !tbaa !5
  %15 = call i32 @inv_imu_read_reg(ptr noundef %14, i32 noundef 65569, i32 noundef 1, ptr noundef %9)
  %16 = load i32, ptr %3, align 4, !tbaa !9
  %17 = or i32 %16, %15
  store i32 %17, ptr %3, align 4, !tbaa !9
  %18 = load i8, ptr %9, align 1, !tbaa !11
  %19 = zext i8 %18 to i32
  %20 = and i32 %19, 15
  store i32 %20, ptr %5, align 4, !tbaa !9
  %21 = load i32, ptr %5, align 4, !tbaa !9
  %22 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %21)
  store i32 %22, ptr %6, align 4, !tbaa !9
  %23 = load ptr, ptr %2, align 8, !tbaa !5
  %24 = call i32 @inv_imu_read_reg(ptr noundef %23, i32 noundef 65567, i32 noundef 1, ptr noundef %8)
  %25 = load i32, ptr %3, align 4, !tbaa !9
  %26 = or i32 %25, %24
  store i32 %26, ptr %3, align 4, !tbaa !9
  %27 = load i8, ptr %8, align 1, !tbaa !11
  %28 = zext i8 %27 to i32
  %29 = and i32 %28, 3
  store i32 %29, ptr %7, align 4, !tbaa !9
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = icmp eq i32 %30, 0
  br i1 %31, label %32, label %38

32:                                               ; preds = %1
  %33 = load ptr, ptr %2, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.inv_imu_device, ptr %33, i32 0, i32 6
  %35 = load i32, ptr %34, align 4, !tbaa !12
  %36 = icmp ne i32 %35, 0
  br i1 %36, label %37, label %38

37:                                               ; preds = %32
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %38

38:                                               ; preds = %37, %32, %1
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = icmp eq i32 %39, 2
  br i1 %40, label %41, label %46

41:                                               ; preds = %38
  %42 = load ptr, ptr %2, align 8, !tbaa !5
  %43 = call i32 @select_rcosc(ptr noundef %42)
  %44 = load i32, ptr %3, align 4, !tbaa !9
  %45 = or i32 %44, %43
  store i32 %45, ptr %3, align 4, !tbaa !9
  br label %46

46:                                               ; preds = %41, %38
  %47 = load ptr, ptr %2, align 8, !tbaa !5
  %48 = call i32 @inv_imu_read_reg(ptr noundef %47, i32 noundef 2, i32 noundef 1, ptr noundef %10)
  %49 = load i32, ptr %3, align 4, !tbaa !9
  %50 = or i32 %49, %48
  store i32 %50, ptr %3, align 4, !tbaa !9
  %51 = load i32, ptr %7, align 4, !tbaa !9
  %52 = icmp eq i32 %51, 0
  br i1 %52, label %53, label %77

53:                                               ; preds = %46
  %54 = load i8, ptr %10, align 1, !tbaa !11
  %55 = zext i8 %54 to i32
  %56 = and i32 %55, 1
  %57 = icmp eq i32 %56, 0
  br i1 %57, label %58, label %77

58:                                               ; preds = %53
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %13) #3
  %59 = load ptr, ptr %2, align 8, !tbaa !5
  %60 = call i32 @inv_imu_read_reg(ptr noundef %59, i32 noundef 65568, i32 noundef 1, ptr noundef %13)
  %61 = load i32, ptr %3, align 4, !tbaa !9
  %62 = or i32 %61, %60
  store i32 %62, ptr %3, align 4, !tbaa !9
  %63 = load i8, ptr %13, align 1, !tbaa !11
  %64 = zext i8 %63 to i32
  %65 = and i32 %64, 15
  store i32 %65, ptr %11, align 4, !tbaa !9
  %66 = load i32, ptr %11, align 4, !tbaa !9
  %67 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %66)
  store i32 %67, ptr %12, align 4, !tbaa !9
  %68 = load i8, ptr %10, align 1, !tbaa !11
  %69 = zext i8 %68 to i32
  %70 = or i32 %69, 1
  %71 = trunc i32 %70 to i8
  store i8 %71, ptr %10, align 1, !tbaa !11
  %72 = load ptr, ptr %2, align 8, !tbaa !5
  %73 = call i32 @inv_imu_write_reg(ptr noundef %72, i32 noundef 2, i32 noundef 1, ptr noundef %10)
  %74 = load i32, ptr %3, align 4, !tbaa !9
  %75 = or i32 %74, %73
  store i32 %75, ptr %3, align 4, !tbaa !9
  %76 = load i32, ptr %12, align 4, !tbaa !9
  call void @inv_imu_sleep_us(i32 noundef %76)
  call void @llvm.lifetime.end.p0(i64 1, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %77

77:                                               ; preds = %58, %53, %46
  %78 = load ptr, ptr %2, align 8, !tbaa !5
  %79 = call i32 @inv_imu_read_reg(ptr noundef %78, i32 noundef 65567, i32 noundef 1, ptr noundef %8)
  %80 = load i32, ptr %3, align 4, !tbaa !9
  %81 = or i32 %80, %79
  store i32 %81, ptr %3, align 4, !tbaa !9
  %82 = load i8, ptr %8, align 1, !tbaa !11
  %83 = zext i8 %82 to i32
  %84 = and i32 %83, -13
  %85 = trunc i32 %84 to i8
  store i8 %85, ptr %8, align 1, !tbaa !11
  %86 = load i8, ptr %8, align 1, !tbaa !11
  %87 = zext i8 %86 to i32
  %88 = or i32 %87, 0
  %89 = trunc i32 %88 to i8
  store i8 %89, ptr %8, align 1, !tbaa !11
  %90 = load ptr, ptr %2, align 8, !tbaa !5
  %91 = call i32 @inv_imu_write_reg(ptr noundef %90, i32 noundef 65567, i32 noundef 1, ptr noundef %8)
  %92 = load i32, ptr %3, align 4, !tbaa !9
  %93 = or i32 %92, %91
  store i32 %93, ptr %3, align 4, !tbaa !9
  %94 = load i32, ptr %7, align 4, !tbaa !9
  %95 = icmp eq i32 %94, 2
  br i1 %95, label %96, label %103

96:                                               ; preds = %77
  %97 = load i32, ptr %6, align 4, !tbaa !9
  %98 = mul i32 2, %97
  call void @inv_imu_sleep_us(i32 noundef %98)
  %99 = load ptr, ptr %2, align 8, !tbaa !5
  %100 = call i32 @select_wuosc(ptr noundef %99)
  %101 = load i32, ptr %3, align 4, !tbaa !9
  %102 = or i32 %101, %100
  store i32 %102, ptr %3, align 4, !tbaa !9
  br label %103

103:                                              ; preds = %96, %77
  %104 = load i32, ptr %4, align 4, !tbaa !9
  %105 = icmp ne i32 %104, 0
  br i1 %105, label %106, label %116

106:                                              ; preds = %103
  %107 = load ptr, ptr %2, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.inv_imu_device, ptr %107, i32 0, i32 6
  %109 = load i32, ptr %108, align 4, !tbaa !12
  %110 = icmp ne i32 %109, 0
  br i1 %110, label %111, label %116

111:                                              ; preds = %106
  %112 = load ptr, ptr %2, align 8, !tbaa !5
  %113 = call i32 @inv_imu_reset_fifo(ptr noundef %112)
  %114 = load i32, ptr %3, align 4, !tbaa !9
  %115 = or i32 %114, %113
  store i32 %115, ptr %3, align 4, !tbaa !9
  br label %116

116:                                              ; preds = %111, %106, %103
  %117 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i32 %117
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 4188}
!13 = !{!"inv_imu_device", !14, i64 0, !6, i64 48, !7, i64 56, !7, i64 4184, !7, i64 4185, !7, i64 4186, !10, i64 4188, !17, i64 4192, !17, i64 4200}
!14 = !{!"inv_imu_transport", !15, i64 0, !16, i64 40, !7, i64 44}
!15 = !{!"inv_imu_serif", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !10, i64 32}
!16 = !{!"register_cache", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!17 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_rcosc(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_wuosc(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_reset_fifo(ptr noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_disable_gyro(ptr noundef %0) local_unnamed_addr #2 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  %6 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65569, i32 noundef 1, ptr noundef nonnull %3) #3
  %7 = load i8, ptr %3, align 1, !tbaa !5
  %8 = and i8 %7, 15
  %9 = zext nneg i8 %8 to i32
  %10 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %9)
  %11 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %12 = or i32 %11, %6
  %13 = load i8, ptr %2, align 1, !tbaa !5
  %14 = and i8 %13, 3
  %15 = icmp eq i8 %14, 0
  br i1 %15, label %23, label %16

16:                                               ; preds = %1
  %17 = icmp eq i8 %14, 2
  br i1 %17, label %18, label %.thread36

18:                                               ; preds = %16
  %19 = call i32 @select_rcosc(ptr noundef %0)
  %20 = or i32 %19, %12
  br label %.thread36

.thread36:                                        ; preds = %18, %16
  %.0.ph = phi i32 [ %12, %16 ], [ %20, %18 ]
  %21 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 2, i32 noundef 1, ptr noundef nonnull %4) #3
  %22 = or i32 %21, %.0.ph
  br label %42

23:                                               ; preds = %1
  %24 = getelementptr inbounds i8, ptr %0, i64 4188
  %25 = load i32, ptr %24, align 4, !tbaa !8
  %.not = icmp eq i32 %25, 0
  %26 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 2, i32 noundef 1, ptr noundef nonnull %4) #3
  %27 = or i32 %26, %12
  %28 = load i8, ptr %4, align 1, !tbaa !5
  %29 = and i8 %28, 1
  %30 = icmp eq i8 %29, 0
  br i1 %30, label %31, label %42

31:                                               ; preds = %23
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #3
  %32 = call i32 @inv_imu_read_reg(ptr noundef nonnull %0, i32 noundef 65568, i32 noundef 1, ptr noundef nonnull %5) #3
  %33 = load i8, ptr %5, align 1, !tbaa !5
  %34 = and i8 %33, 15
  %35 = zext nneg i8 %34 to i32
  %36 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %35)
  %37 = load i8, ptr %4, align 1, !tbaa !5
  %38 = or i8 %37, 1
  store i8 %38, ptr %4, align 1, !tbaa !5
  %39 = call i32 @inv_imu_write_reg(ptr noundef nonnull %0, i32 noundef 2, i32 noundef 1, ptr noundef nonnull %4) #3
  %40 = or i32 %32, %39
  %41 = or i32 %40, %27
  call void @inv_imu_sleep_us(i32 noundef %36) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #3
  br label %42

42:                                               ; preds = %.thread36, %31, %23
  %.not323539 = phi i1 [ %.not, %31 ], [ %.not, %23 ], [ true, %.thread36 ]
  %43 = phi i1 [ false, %31 ], [ false, %23 ], [ %17, %.thread36 ]
  %.1 = phi i32 [ %41, %31 ], [ %27, %23 ], [ %22, %.thread36 ]
  %44 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %45 = or i32 %44, %.1
  %46 = load i8, ptr %2, align 1, !tbaa !5
  %47 = and i8 %46, -13
  store i8 %47, ptr %2, align 1, !tbaa !5
  %48 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %49 = or i32 %45, %48
  br i1 %43, label %50, label %54

50:                                               ; preds = %42
  %51 = shl i32 %10, 1
  call void @inv_imu_sleep_us(i32 noundef %51) #3
  %52 = call i32 @select_wuosc(ptr noundef %0)
  %53 = or i32 %52, %49
  br label %54

54:                                               ; preds = %50, %42
  %.2 = phi i32 [ %53, %50 ], [ %49, %42 ]
  br i1 %.not323539, label %61, label %55

55:                                               ; preds = %54
  %56 = getelementptr inbounds i8, ptr %0, i64 4188
  %57 = load i32, ptr %56, align 4, !tbaa !8
  %.not33 = icmp eq i32 %57, 0
  br i1 %.not33, label %61, label %58

58:                                               ; preds = %55
  %59 = call i32 @inv_imu_reset_fifo(ptr noundef nonnull %0)
  %60 = or i32 %59, %.2
  br label %61

61:                                               ; preds = %58, %55, %54
  %.3 = phi i32 [ %60, %58 ], [ %.2, %55 ], [ %.2, %54 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  ret i32 %.3
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !13, i64 4188}
!9 = !{!"inv_imu_device", !10, i64 0, !12, i64 48, !6, i64 56, !6, i64 4184, !6, i64 4185, !6, i64 4186, !13, i64 4188, !15, i64 4192, !15, i64 4200}
!10 = !{!"inv_imu_transport", !11, i64 0, !14, i64 40, !6, i64 44}
!11 = !{!"inv_imu_serif", !12, i64 0, !12, i64 8, !12, i64 16, !13, i64 24, !13, i64 28, !13, i64 32}
!12 = !{!"any pointer", !6, i64 0}
!13 = !{!"int", !6, i64 0}
!14 = !{!"register_cache", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3}
!15 = !{!"long", !6, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,ReassociatePass,SROAPass,SimplifyCFGPass