; LLVM IR from epicf/ef :: vec3d.ll (Z19vec3d_cross_product5Vec3dS_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Vec3d = type { [3 x double] }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z10vec3d_initddd(ptr dead_on_unwind noalias writable sret(%struct.Vec3d) align 8, double noundef, double noundef, double noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z19vec3d_cross_product5Vec3dS_(ptr dead_on_unwind noalias writable sret(%struct.Vec3d) align 8 %0, ptr noundef byval(%struct.Vec3d) align 8 %1, ptr noundef byval(%struct.Vec3d) align 8 %2) #0 {
  %4 = alloca double, align 8
  %5 = alloca %struct.Vec3d, align 8
  %6 = alloca %struct.Vec3d, align 8
  %7 = alloca %struct.Vec3d, align 8
  %8 = alloca %struct.Vec3d, align 8
  %9 = alloca double, align 8
  %10 = alloca %struct.Vec3d, align 8
  %11 = alloca %struct.Vec3d, align 8
  %12 = alloca %struct.Vec3d, align 8
  %13 = alloca %struct.Vec3d, align 8
  %14 = alloca double, align 8
  %15 = alloca %struct.Vec3d, align 8
  %16 = alloca %struct.Vec3d, align 8
  %17 = alloca %struct.Vec3d, align 8
  %18 = alloca %struct.Vec3d, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %5, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %19 = call noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %5)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %6, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %20 = call noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %6)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %7, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %21 = call noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %7)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %8, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %22 = call noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %8)
  %23 = fmul double %21, %22
  %24 = fneg double %23
  %25 = call double @llvm.fmuladd.f64(double %19, double %20, double %24)
  store double %25, ptr %4, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %10, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %26 = call noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %10)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %11, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %27 = call noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %11)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %12, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %28 = call noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %12)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %13, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %29 = call noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %13)
  %30 = fmul double %28, %29
  %31 = fneg double %30
  %32 = call double @llvm.fmuladd.f64(double %26, double %27, double %31)
  store double %32, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %15, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %33 = call noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %15)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %16, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %34 = call noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %16)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %17, ptr align 8 %1, i64 24, i1 false), !tbaa.struct !5
  %35 = call noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %17)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %18, ptr align 8 %2, i64 24, i1 false), !tbaa.struct !5
  %36 = call noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8 %18)
  %37 = fmul double %35, %36
  %38 = fneg double %37
  %39 = call double @llvm.fmuladd.f64(double %33, double %34, double %38)
  store double %39, ptr %14, align 8, !tbaa !9
  %40 = load double, ptr %4, align 8, !tbaa !9
  %41 = load double, ptr %9, align 8, !tbaa !9
  %42 = load double, ptr %14, align 8, !tbaa !9
  call void @_Z10vec3d_initddd(ptr dead_on_unwind writable sret(%struct.Vec3d) align 8 %0, double noundef %40, double noundef %41, double noundef %42)
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 0, i64 24, !6}
!6 = !{!7, !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"double", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Vec3d = type { [3 x double] }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z10vec3d_initddd(ptr dead_on_unwind noalias writable sret(%struct.Vec3d) align 8, double noundef, double noundef, double noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_x5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_y5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef double @_Z7vec3d_z5Vec3d(ptr noundef byval(%struct.Vec3d) align 8) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z19vec3d_cross_product5Vec3dS_(ptr dead_on_unwind noalias writable sret(%struct.Vec3d) align 8 %0, ptr nocapture noundef readonly byval(%struct.Vec3d) align 8 %1, ptr nocapture noundef readonly byval(%struct.Vec3d) align 8 %2) local_unnamed_addr #0 {
  %4 = tail call noundef double @_Z7vec3d_y5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %5 = tail call noundef double @_Z7vec3d_z5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %6 = tail call noundef double @_Z7vec3d_z5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %7 = tail call noundef double @_Z7vec3d_y5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %8 = fneg double %6
  %9 = fmul double %7, %8
  %10 = tail call double @llvm.fmuladd.f64(double %4, double %5, double %9)
  %11 = tail call noundef double @_Z7vec3d_z5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %12 = tail call noundef double @_Z7vec3d_x5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %13 = tail call noundef double @_Z7vec3d_x5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %14 = tail call noundef double @_Z7vec3d_z5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %15 = fneg double %13
  %16 = fmul double %14, %15
  %17 = tail call double @llvm.fmuladd.f64(double %11, double %12, double %16)
  %18 = tail call noundef double @_Z7vec3d_x5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %19 = tail call noundef double @_Z7vec3d_y5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %20 = tail call noundef double @_Z7vec3d_y5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %1)
  %21 = tail call noundef double @_Z7vec3d_x5Vec3d(ptr noundef nonnull byval(%struct.Vec3d) align 8 %2)
  %22 = fneg double %20
  %23 = fmul double %21, %22
  %24 = tail call double @llvm.fmuladd.f64(double %18, double %19, double %23)
  tail call void @_Z10vec3d_initddd(ptr dead_on_unwind writable sret(%struct.Vec3d) align 8 %0, double noundef %10, double noundef %17, double noundef %24)
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: DSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass