; LLVM IR from bqi343/cp-notebook :: Implementations/content/geometry (13)/3D/death_conveyor.ll (ZmIRSt5arrayIeLm4EERKS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef nonnull align 16 dereferenceable(64) ptr @_ZmIRSt5arrayIeLm4EERKS0_(ptr noundef nonnull align 16 dereferenceable(64) %0, ptr noundef nonnull align 16 dereferenceable(64) %1) #1 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !9
  br label %6

6:                                                ; preds = %22, %2
  %7 = load i32, ptr %5, align 4, !tbaa !9
  %8 = icmp slt i32 %7, 4
  br i1 %8, label %10, label %9

9:                                                ; preds = %6
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  br label %25

10:                                               ; preds = %6
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = sext i32 %12 to i64
  %14 = call noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %11, i64 noundef %13) #2
  %15 = load x86_fp80, ptr %14, align 16, !tbaa !11
  %16 = load ptr, ptr %3, align 8, !tbaa !5
  %17 = load i32, ptr %5, align 4, !tbaa !9
  %18 = sext i32 %17 to i64
  %19 = call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %16, i64 noundef %18) #2
  %20 = load x86_fp80, ptr %19, align 16, !tbaa !11
  %21 = fsub x86_fp80 %20, %15
  store x86_fp80 %21, ptr %19, align 16, !tbaa !11
  br label %22

22:                                               ; preds = %10
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = add nsw i32 %23, 1
  store i32 %24, ptr %5, align 4, !tbaa !9
  br label %6, !llvm.loop !13

25:                                               ; preds = %9
  %26 = load ptr, ptr %3, align 8, !tbaa !5
  ret ptr %26
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long double", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef nonnull align 16 dereferenceable(64) ptr @_ZmIRSt5arrayIeLm4EERKS0_(ptr noundef nonnull returned align 16 dereferenceable(64) %0, ptr noundef nonnull align 16 dereferenceable(64) %1) local_unnamed_addr #0 {
  %3 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %1, i64 noundef 0) #1
  %4 = load x86_fp80, ptr %3, align 16, !tbaa !5
  %5 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 0) #1
  %6 = load x86_fp80, ptr %5, align 16, !tbaa !5
  %7 = fsub x86_fp80 %6, %4
  store x86_fp80 %7, ptr %5, align 16, !tbaa !5
  %8 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %1, i64 noundef 1) #1
  %9 = load x86_fp80, ptr %8, align 16, !tbaa !5
  %10 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 1) #1
  %11 = load x86_fp80, ptr %10, align 16, !tbaa !5
  %12 = fsub x86_fp80 %11, %9
  store x86_fp80 %12, ptr %10, align 16, !tbaa !5
  %13 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %1, i64 noundef 2) #1
  %14 = load x86_fp80, ptr %13, align 16, !tbaa !5
  %15 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 2) #1
  %16 = load x86_fp80, ptr %15, align 16, !tbaa !5
  %17 = fsub x86_fp80 %16, %14
  store x86_fp80 %17, ptr %15, align 16, !tbaa !5
  %18 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNKSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %1, i64 noundef 3) #1
  %19 = load x86_fp80, ptr %18, align 16, !tbaa !5
  %20 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 3) #1
  %21 = load x86_fp80, ptr %20, align 16, !tbaa !5
  %22 = fsub x86_fp80 %21, %19
  store x86_fp80 %22, ptr %20, align 16, !tbaa !5
  ret ptr %0
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass