; LLVM IR from tfhe/spqlios-arithmetic :: test/testlib/ntt120_dft.ll (ZN11q120_nttvec6randomEm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.q120_nttvec = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.mod_q120 = type { [4 x i64] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorI8mod_q120SaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN11q120_nttvecD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11q120_nttvec6randomEm(ptr dead_on_unwind noalias writable sret(%class.q120_nttvec) align 8 %0, i64 noundef %1) #4 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca i64, align 8
  %5 = alloca i1, align 1
  %6 = alloca i64, align 8
  %7 = alloca %class.mod_q120, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8
  store i64 %1, ptr %4, align 8, !tbaa !5
  store i1 false, ptr %5, align 1
  %10 = load i64, ptr %4, align 8, !tbaa !5
  call void @_ZN11q120_nttvecC1Em(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %10)
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #6
  store i64 0, ptr %6, align 8, !tbaa !5
  br label %11

11:                                               ; preds = %21, %2
  %12 = load i64, ptr %6, align 8, !tbaa !5
  %13 = load i64, ptr %4, align 8, !tbaa !5
  %14 = icmp ult i64 %12, %13
  br i1 %14, label %16, label %15

15:                                               ; preds = %11
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #6
  br label %28

16:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 32, ptr %7) #6
  invoke void @_Z12uniform_q120v(ptr dead_on_unwind writable sret(%class.mod_q120) align 8 %7)
          to label %17 unwind label %24

17:                                               ; preds = %16
  %18 = getelementptr inbounds %class.q120_nttvec, ptr %0, i32 0, i32 0
  %19 = load i64, ptr %6, align 8, !tbaa !5
  %20 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorI8mod_q120SaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %19) #6
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %20, ptr align 8 %7, i64 32, i1 false), !tbaa.struct !9
  call void @llvm.lifetime.end.p0(i64 32, ptr %7) #6
  br label %21

21:                                               ; preds = %17
  %22 = load i64, ptr %6, align 8, !tbaa !5
  %23 = add i64 %22, 1
  store i64 %23, ptr %6, align 8, !tbaa !5
  br label %11, !llvm.loop !11

24:                                               ; preds = %16
  %25 = landingpad { ptr, i32 }
          cleanup
  %26 = extractvalue { ptr, i32 } %25, 0
  store ptr %26, ptr %8, align 8
  %27 = extractvalue { ptr, i32 } %25, 1
  store i32 %27, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 32, ptr %7) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #6
  call void @_ZN11q120_nttvecD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #6
  br label %32

28:                                               ; preds = %15
  store i1 true, ptr %5, align 1
  %29 = load i1, ptr %5, align 1
  br i1 %29, label %31, label %30

30:                                               ; preds = %28
  call void @_ZN11q120_nttvecD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #6
  br label %31

31:                                               ; preds = %30, %28
  ret void

32:                                               ; preds = %24
  %33 = load ptr, ptr %8, align 8
  %34 = load i32, ptr %9, align 4
  %35 = insertvalue { ptr, i32 } poison, ptr %33, 0
  %36 = insertvalue { ptr, i32 } %35, i32 %34, 1
  resume { ptr, i32 } %36
}

declare void @_Z12uniform_q120v(ptr dead_on_unwind writable sret(%class.mod_q120) align 8) #5

declare void @_ZN11q120_nttvecC1Em(ptr, i64)

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i64 0, i64 32, !10}
!10 = !{!7, !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.q120_nttvec = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.mod_q120 = type { [4 x i64] }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorI8mod_q120SaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN11q120_nttvecD2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN11q120_nttvec6randomEm(ptr dead_on_unwind noalias writable sret(%class.q120_nttvec) align 8 %0, i64 noundef %1) local_unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  %3 = alloca %class.mod_q120, align 8
  tail call void @_ZN11q120_nttvecC1Em(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %1)
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2, %4
  %.07 = phi i64 [ %6, %4 ], [ 0, %2 ]
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %3) #6
  invoke void @_Z12uniform_q120v(ptr dead_on_unwind nonnull writable sret(%class.mod_q120) align 8 %3)
          to label %4 unwind label %7

4:                                                ; preds = %.lr.ph
  %5 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNSt6vectorI8mod_q120SaIS0_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.07) #6
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %5, ptr noundef nonnull align 8 dereferenceable(32) %3, i64 32, i1 false), !tbaa.struct !5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %3) #6
  %6 = add nuw i64 %.07, 1
  %exitcond.not = icmp eq i64 %6, %1
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

7:                                                ; preds = %.lr.ph
  %8 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %3) #6
  call void @_ZN11q120_nttvecD2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #6
  resume { ptr, i32 } %8

._crit_edge:                                      ; preds = %4, %2
  ret void
}

declare void @_Z12uniform_q120v(ptr dead_on_unwind writable sret(%class.mod_q120) align 8) local_unnamed_addr #5

declare void @_ZN11q120_nttvecC1Em(ptr, i64) local_unnamed_addr

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 0, i64 32, !6}
!6 = !{!7, !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass