; LLVM IR from bqi343/cp-notebook :: Implementations/content/graphs (12)/Advanced/DirectedMSTtest.ll (Z5mergeP4NodeS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Node = type { %struct.Edge, ptr, ptr, i64 }
%struct.Edge = type { i32, i32, i64 }

; Function Attrs: mustprogress uwtable
define dso_local noundef ptr @_Z5mergeP4NodeS0_(ptr noundef %0, ptr noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  %6 = load ptr, ptr %4, align 8, !tbaa !5
  %7 = icmp ne ptr %6, null
  br i1 %7, label %8, label %11

8:                                                ; preds = %2
  %9 = load ptr, ptr %5, align 8, !tbaa !5
  %10 = icmp ne ptr %9, null
  br i1 %10, label %20, label %11

11:                                               ; preds = %8, %2
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = icmp ne ptr %12, null
  br i1 %13, label %14, label %16

14:                                               ; preds = %11
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  br label %18

16:                                               ; preds = %11
  %17 = load ptr, ptr %5, align 8, !tbaa !5
  br label %18

18:                                               ; preds = %16, %14
  %19 = phi ptr [ %15, %14 ], [ %17, %16 ]
  store ptr %19, ptr %3, align 8
  br label %44

20:                                               ; preds = %8
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40) %21)
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40) %22)
  %23 = load ptr, ptr %4, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.Node, ptr %23, i32 0, i32 0
  %25 = getelementptr inbounds %struct.Edge, ptr %24, i32 0, i32 2
  %26 = load i64, ptr %25, align 8, !tbaa !9
  %27 = load ptr, ptr %5, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.Node, ptr %27, i32 0, i32 0
  %29 = getelementptr inbounds %struct.Edge, ptr %28, i32 0, i32 2
  %30 = load i64, ptr %29, align 8, !tbaa !9
  %31 = icmp sgt i64 %26, %30
  br i1 %31, label %32, label %33

32:                                               ; preds = %20
  call void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8) %4, ptr noundef nonnull align 8 dereferenceable(8) %5) #3
  br label %33

33:                                               ; preds = %32, %20
  %34 = load ptr, ptr %4, align 8, !tbaa !5
  %35 = getelementptr inbounds %struct.Node, ptr %34, i32 0, i32 1
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %struct.Node, ptr %37, i32 0, i32 2
  %39 = load ptr, ptr %38, align 8, !tbaa !14
  %40 = call noundef ptr @_Z5mergeP4NodeS0_(ptr noundef %36, ptr noundef %39)
  %41 = load ptr, ptr %4, align 8, !tbaa !5
  %42 = getelementptr inbounds %struct.Node, ptr %41, i32 0, i32 2
  store ptr %40, ptr %42, align 8, !tbaa !14
  call void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8) %35, ptr noundef nonnull align 8 dereferenceable(8) %42) #3
  %43 = load ptr, ptr %4, align 8, !tbaa !5
  store ptr %43, ptr %3, align 8
  br label %44

44:                                               ; preds = %33, %18
  %45 = load ptr, ptr %3, align 8
  ret ptr %45
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40)) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 8}
!10 = !{!"_ZTS4Node", !11, i64 0, !6, i64 16, !6, i64 24, !13, i64 32}
!11 = !{!"_ZTS4Edge", !12, i64 0, !12, i64 4, !13, i64 8}
!12 = !{!"int", !7, i64 0}
!13 = !{!"long long", !7, i64 0}
!14 = !{!10, !6, i64 24}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_Z5mergeP4NodeS0_(ptr noundef %0, ptr noundef %1) local_unnamed_addr #0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %5 = icmp ne ptr %0, null
  %6 = icmp ne ptr %1, null
  %or.cond = and i1 %5, %6
  br i1 %or.cond, label %9, label %7

7:                                                ; preds = %2
  %8 = select i1 %5, ptr %0, ptr %1
  br label %26

9:                                                ; preds = %2
  tail call void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40) %0)
  tail call void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40) %1)
  %10 = getelementptr inbounds i8, ptr %0, i64 8
  %11 = load i64, ptr %10, align 8, !tbaa !9
  %12 = getelementptr inbounds i8, ptr %1, i64 8
  %13 = load i64, ptr %12, align 8, !tbaa !9
  %14 = icmp sgt i64 %11, %13
  br i1 %14, label %15, label %16

15:                                               ; preds = %9
  call void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef nonnull align 8 dereferenceable(8) %4) #2
  %.pre = load ptr, ptr %3, align 8, !tbaa !5
  %.pre3 = load ptr, ptr %4, align 8, !tbaa !5
  br label %16

16:                                               ; preds = %15, %9
  %17 = phi ptr [ %.pre3, %15 ], [ %1, %9 ]
  %18 = phi ptr [ %.pre, %15 ], [ %0, %9 ]
  %19 = getelementptr inbounds i8, ptr %18, i64 16
  %20 = getelementptr inbounds i8, ptr %18, i64 24
  %21 = load ptr, ptr %20, align 8, !tbaa !14
  %22 = call noundef ptr @_Z5mergeP4NodeS0_(ptr noundef %17, ptr noundef %21)
  %23 = load ptr, ptr %3, align 8, !tbaa !5
  %24 = getelementptr inbounds i8, ptr %23, i64 24
  store ptr %22, ptr %24, align 8, !tbaa !14
  call void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8) %19, ptr noundef nonnull align 8 dereferenceable(8) %24) #2
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  br label %26

26:                                               ; preds = %16, %7
  %.0 = phi ptr [ %25, %16 ], [ %8, %7 ]
  ret ptr %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4Node4propEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIP4NodeENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS5_ESt18is_move_assignableIS5_EEE5valueEvE4typeERS5_SE_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !13, i64 8}
!10 = !{!"_ZTS4Node", !11, i64 0, !6, i64 16, !6, i64 24, !13, i64 32}
!11 = !{!"_ZTS4Edge", !12, i64 0, !12, i64 4, !13, i64 8}
!12 = !{!"int", !7, i64 0}
!13 = !{!"long long", !7, i64 0}
!14 = !{!10, !6, i64 24}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass