; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_selftest)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_selftest_parameters_t = type { i32, i32 }
%struct.inv_imu_device = type { %struct.inv_imu_transport, ptr, [4128 x i8], i8, i8, i8, i32, i64, i64 }
%struct.inv_imu_transport = type { %struct.inv_imu_serif, %struct.register_cache, i8 }
%struct.inv_imu_serif = type { ptr, ptr, ptr, i32, i32, i32 }
%struct.register_cache = type { i8, i8, i8, i8 }
%struct.inv_imu_selftest_output_t = type { i8, i8, i8, i8, i8, i8, i8, i8 }

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_run_selftest(ptr noundef %0, i64 %1, ptr noundef %2) #0 {
  %4 = alloca i32, align 4
  %5 = alloca %struct.inv_imu_selftest_parameters_t, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i8, align 1
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  store i64 %1, ptr %5, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  store i8 0, ptr %10, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #3
  store i8 0, ptr %11, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 1000, ptr %12, align 4, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = call i32 @inv_imu_read_reg(ptr noundef %14, i32 noundef 65567, i32 noundef 1, ptr noundef %9)
  %16 = load i32, ptr %8, align 4, !tbaa !9
  %17 = or i32 %16, %15
  store i32 %17, ptr %8, align 4, !tbaa !9
  %18 = load i8, ptr %9, align 1, !tbaa !11
  %19 = zext i8 %18 to i32
  %20 = and i32 %19, -4
  %21 = trunc i32 %20 to i8
  store i8 %21, ptr %9, align 1, !tbaa !11
  %22 = load i8, ptr %9, align 1, !tbaa !11
  %23 = zext i8 %22 to i32
  %24 = and i32 %23, -13
  %25 = trunc i32 %24 to i8
  store i8 %25, ptr %9, align 1, !tbaa !11
  %26 = load ptr, ptr %6, align 8, !tbaa !5
  %27 = call i32 @inv_imu_write_reg(ptr noundef %26, i32 noundef 65567, i32 noundef 1, ptr noundef %9)
  %28 = load i32, ptr %8, align 4, !tbaa !9
  %29 = or i32 %28, %27
  store i32 %29, ptr %8, align 4, !tbaa !9
  %30 = load ptr, ptr %6, align 8, !tbaa !5
  %31 = call i32 @inv_imu_switch_on_mclk(ptr noundef %30)
  %32 = load i32, ptr %8, align 4, !tbaa !9
  %33 = or i32 %32, %31
  store i32 %33, ptr %8, align 4, !tbaa !9
  %34 = load ptr, ptr %6, align 8, !tbaa !5
  %35 = call i32 @inv_imu_reset_dmp(ptr noundef %34, i32 noundef 1)
  %36 = load i32, ptr %8, align 4, !tbaa !9
  %37 = or i32 %36, %35
  store i32 %37, ptr %8, align 4, !tbaa !9
  %38 = load ptr, ptr %6, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.inv_imu_device, ptr %38, i32 0, i32 3
  store i8 0, ptr %39, align 8, !tbaa !12
  %40 = load ptr, ptr %6, align 8, !tbaa !5
  %41 = call i32 @inv_imu_load_selftest_data(ptr noundef %40)
  %42 = load i32, ptr %8, align 4, !tbaa !9
  %43 = or i32 %42, %41
  store i32 %43, ptr %8, align 4, !tbaa !9
  %44 = load ptr, ptr %6, align 8, !tbaa !5
  %45 = load i64, ptr %5, align 4
  %46 = call i32 @configure_selftest_parameters(ptr noundef %44, i64 %45)
  %47 = load i32, ptr %8, align 4, !tbaa !9
  %48 = or i32 %47, %46
  store i32 %48, ptr %8, align 4, !tbaa !9
  %49 = load ptr, ptr %6, align 8, !tbaa !5
  %50 = call i32 @inv_imu_read_reg(ptr noundef %49, i32 noundef 20, i32 noundef 1, ptr noundef %9)
  %51 = load i32, ptr %8, align 4, !tbaa !9
  %52 = or i32 %51, %50
  store i32 %52, ptr %8, align 4, !tbaa !9
  %53 = load i8, ptr %9, align 1, !tbaa !11
  %54 = zext i8 %53 to i32
  %55 = and i32 %54, -65
  %56 = trunc i32 %55 to i8
  store i8 %56, ptr %9, align 1, !tbaa !11
  %57 = load i8, ptr %9, align 1, !tbaa !11
  %58 = zext i8 %57 to i32
  %59 = and i32 %58, -129
  %60 = trunc i32 %59 to i8
  store i8 %60, ptr %9, align 1, !tbaa !11
  %61 = getelementptr inbounds %struct.inv_imu_selftest_parameters_t, ptr %5, i32 0, i32 1
  %62 = load i32, ptr %61, align 4, !tbaa !18
  %63 = trunc i32 %62 to i8
  %64 = zext i8 %63 to i32
  %65 = load i8, ptr %9, align 1, !tbaa !11
  %66 = zext i8 %65 to i32
  %67 = or i32 %66, %64
  %68 = trunc i32 %67 to i8
  store i8 %68, ptr %9, align 1, !tbaa !11
  %69 = load ptr, ptr %6, align 8, !tbaa !5
  %70 = call i32 @inv_imu_write_reg(ptr noundef %69, i32 noundef 20, i32 noundef 1, ptr noundef %9)
  %71 = load i32, ptr %8, align 4, !tbaa !9
  %72 = or i32 %71, %70
  store i32 %72, ptr %8, align 4, !tbaa !9
  br label %73

73:                                               ; preds = %96, %3
  call void @inv_imu_sleep_us(i32 noundef 1000)
  %74 = load ptr, ptr %6, align 8, !tbaa !5
  %75 = call i32 @inv_imu_read_reg(ptr noundef %74, i32 noundef 65594, i32 noundef 1, ptr noundef %11)
  %76 = load i32, ptr %8, align 4, !tbaa !9
  %77 = or i32 %76, %75
  store i32 %77, ptr %8, align 4, !tbaa !9
  %78 = load i8, ptr %11, align 1, !tbaa !11
  %79 = zext i8 %78 to i32
  %80 = and i32 %79, 128
  %81 = trunc i32 %80 to i8
  store i8 %81, ptr %11, align 1, !tbaa !11
  %82 = load i32, ptr %12, align 4, !tbaa !9
  %83 = add nsw i32 %82, -1
  store i32 %83, ptr %12, align 4, !tbaa !9
  %84 = icmp eq i32 0, %83
  br i1 %84, label %85, label %88

85:                                               ; preds = %73
  %86 = load i32, ptr %8, align 4, !tbaa !9
  %87 = or i32 %86, -1
  store i32 %87, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %203

88:                                               ; preds = %73
  br label %89

89:                                               ; preds = %88
  %90 = load i8, ptr %11, align 1, !tbaa !11
  %91 = icmp ne i8 %90, 0
  br i1 %91, label %96, label %92

92:                                               ; preds = %89
  %93 = load i32, ptr %8, align 4, !tbaa !9
  %94 = icmp ne i32 %93, 0
  %95 = xor i1 %94, true
  br label %96

96:                                               ; preds = %92, %89
  %97 = phi i1 [ false, %89 ], [ %95, %92 ]
  br i1 %97, label %73, label %98, !llvm.loop !20

98:                                               ; preds = %96
  %99 = load ptr, ptr %6, align 8, !tbaa !5
  %100 = call i32 @inv_imu_read_reg(ptr noundef %99, i32 noundef 100, i32 noundef 1, ptr noundef %10)
  %101 = load i32, ptr %8, align 4, !tbaa !9
  %102 = or i32 %101, %100
  store i32 %102, ptr %8, align 4, !tbaa !9
  %103 = load i8, ptr %10, align 1, !tbaa !11
  %104 = zext i8 %103 to i32
  %105 = and i32 %104, 32
  %106 = ashr i32 %105, 5
  %107 = trunc i32 %106 to i8
  %108 = load ptr, ptr %7, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %108, i32 0, i32 4
  store i8 %107, ptr %109, align 1, !tbaa !22
  %110 = load i8, ptr %10, align 1, !tbaa !11
  %111 = zext i8 %110 to i32
  %112 = and i32 %111, 64
  %113 = ashr i32 %112, 6
  %114 = shl i32 %113, 1
  %115 = load ptr, ptr %7, align 8, !tbaa !5
  %116 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %115, i32 0, i32 4
  %117 = load i8, ptr %116, align 1, !tbaa !22
  %118 = sext i8 %117 to i32
  %119 = or i32 %118, %114
  %120 = trunc i32 %119 to i8
  store i8 %120, ptr %116, align 1, !tbaa !22
  %121 = load i8, ptr %10, align 1, !tbaa !11
  %122 = zext i8 %121 to i32
  %123 = and i32 %122, 2
  %124 = ashr i32 %123, 1
  %125 = trunc i32 %124 to i8
  %126 = load ptr, ptr %7, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %126, i32 0, i32 5
  store i8 %125, ptr %127, align 1, !tbaa !24
  %128 = load i8, ptr %10, align 1, !tbaa !11
  %129 = zext i8 %128 to i32
  %130 = and i32 %129, 4
  %131 = ashr i32 %130, 2
  %132 = trunc i32 %131 to i8
  %133 = load ptr, ptr %7, align 8, !tbaa !5
  %134 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %133, i32 0, i32 6
  store i8 %132, ptr %134, align 1, !tbaa !25
  %135 = load i8, ptr %10, align 1, !tbaa !11
  %136 = zext i8 %135 to i32
  %137 = and i32 %136, 8
  %138 = ashr i32 %137, 3
  %139 = trunc i32 %138 to i8
  %140 = load ptr, ptr %7, align 8, !tbaa !5
  %141 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %140, i32 0, i32 7
  store i8 %139, ptr %141, align 1, !tbaa !26
  %142 = load ptr, ptr %6, align 8, !tbaa !5
  %143 = call i32 @inv_imu_read_reg(ptr noundef %142, i32 noundef 99, i32 noundef 1, ptr noundef %10)
  %144 = load i32, ptr %8, align 4, !tbaa !9
  %145 = or i32 %144, %143
  store i32 %145, ptr %8, align 4, !tbaa !9
  %146 = load i8, ptr %10, align 1, !tbaa !11
  %147 = zext i8 %146 to i32
  %148 = and i32 %147, 32
  %149 = ashr i32 %148, 5
  %150 = trunc i32 %149 to i8
  %151 = load ptr, ptr %7, align 8, !tbaa !5
  %152 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %151, i32 0, i32 0
  store i8 %150, ptr %152, align 1, !tbaa !27
  %153 = load i8, ptr %10, align 1, !tbaa !11
  %154 = zext i8 %153 to i32
  %155 = and i32 %154, 2
  %156 = ashr i32 %155, 1
  %157 = trunc i32 %156 to i8
  %158 = load ptr, ptr %7, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %158, i32 0, i32 1
  store i8 %157, ptr %159, align 1, !tbaa !28
  %160 = load i8, ptr %10, align 1, !tbaa !11
  %161 = zext i8 %160 to i32
  %162 = and i32 %161, 4
  %163 = ashr i32 %162, 2
  %164 = trunc i32 %163 to i8
  %165 = load ptr, ptr %7, align 8, !tbaa !5
  %166 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %165, i32 0, i32 2
  store i8 %164, ptr %166, align 1, !tbaa !29
  %167 = load i8, ptr %10, align 1, !tbaa !11
  %168 = zext i8 %167 to i32
  %169 = and i32 %168, 8
  %170 = ashr i32 %169, 3
  %171 = trunc i32 %170 to i8
  %172 = load ptr, ptr %7, align 8, !tbaa !5
  %173 = getelementptr inbounds %struct.inv_imu_selftest_output_t, ptr %172, i32 0, i32 3
  store i8 %171, ptr %173, align 1, !tbaa !30
  %174 = load ptr, ptr %6, align 8, !tbaa !5
  %175 = call i32 @inv_imu_read_reg(ptr noundef %174, i32 noundef 20, i32 noundef 1, ptr noundef %9)
  %176 = load i32, ptr %8, align 4, !tbaa !9
  %177 = or i32 %176, %175
  store i32 %177, ptr %8, align 4, !tbaa !9
  %178 = load i8, ptr %9, align 1, !tbaa !11
  %179 = zext i8 %178 to i32
  %180 = and i32 %179, -65
  %181 = trunc i32 %180 to i8
  store i8 %181, ptr %9, align 1, !tbaa !11
  %182 = load i8, ptr %9, align 1, !tbaa !11
  %183 = zext i8 %182 to i32
  %184 = and i32 %183, -129
  %185 = trunc i32 %184 to i8
  store i8 %185, ptr %9, align 1, !tbaa !11
  %186 = load i8, ptr %9, align 1, !tbaa !11
  %187 = zext i8 %186 to i32
  %188 = or i32 %187, 0
  %189 = trunc i32 %188 to i8
  store i8 %189, ptr %9, align 1, !tbaa !11
  %190 = load ptr, ptr %6, align 8, !tbaa !5
  %191 = call i32 @inv_imu_write_reg(ptr noundef %190, i32 noundef 20, i32 noundef 1, ptr noundef %9)
  %192 = load i32, ptr %8, align 4, !tbaa !9
  %193 = or i32 %192, %191
  store i32 %193, ptr %8, align 4, !tbaa !9
  %194 = load ptr, ptr %6, align 8, !tbaa !5
  %195 = call i32 @inv_imu_reset_fifo(ptr noundef %194)
  %196 = load i32, ptr %8, align 4, !tbaa !9
  %197 = or i32 %196, %195
  store i32 %197, ptr %8, align 4, !tbaa !9
  %198 = load ptr, ptr %6, align 8, !tbaa !5
  %199 = call i32 @inv_imu_switch_off_mclk(ptr noundef %198)
  %200 = load i32, ptr %8, align 4, !tbaa !9
  %201 = or i32 %200, %199
  store i32 %201, ptr %8, align 4, !tbaa !9
  %202 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %202, ptr %4, align 4
  store i32 1, ptr %13, align 4
  br label %203

203:                                              ; preds = %98, %85
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %204 = load i32, ptr %4, align 4
  ret i32 %204
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #2

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #2

declare i32 @inv_imu_switch_on_mclk(ptr noundef) #2

declare i32 @inv_imu_reset_dmp(ptr noundef, i32 noundef) #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_load_selftest_data(ptr noundef) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @configure_selftest_parameters(ptr noundef, i64) #0

declare void @inv_imu_sleep_us(i32 noundef) #2

declare i32 @inv_imu_reset_fifo(ptr noundef) #2

declare i32 @inv_imu_switch_off_mclk(ptr noundef) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !7, i64 4184}
!13 = !{!"inv_imu_device", !14, i64 0, !6, i64 48, !7, i64 56, !7, i64 4184, !7, i64 4185, !7, i64 4186, !10, i64 4188, !17, i64 4192, !17, i64 4200}
!14 = !{!"inv_imu_transport", !15, i64 0, !16, i64 40, !7, i64 44}
!15 = !{!"inv_imu_serif", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !10, i64 32}
!16 = !{!"register_cache", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!17 = !{!"long", !7, i64 0}
!18 = !{!19, !10, i64 4}
!19 = !{!"", !10, i64 0, !10, i64 4}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}
!22 = !{!23, !7, i64 4}
!23 = !{!"", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3, !7, i64 4, !7, i64 5, !7, i64 6, !7, i64 7}
!24 = !{!23, !7, i64 5}
!25 = !{!23, !7, i64 6}
!26 = !{!23, !7, i64 7}
!27 = !{!23, !7, i64 0}
!28 = !{!23, !7, i64 1}
!29 = !{!23, !7, i64 2}
!30 = !{!23, !7, i64 3}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_run_selftest(ptr noundef %0, i64 %1, ptr nocapture noundef writeonly %2) local_unnamed_addr #0 {
  %4 = alloca i8, align 1
  %5 = alloca i8, align 1
  %6 = alloca i8, align 1
  %.sroa.2.0.extract.shift = lshr i64 %1, 32
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #3
  store i8 0, ptr %5, align 1, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %6) #3
  store i8 0, ptr %6, align 1, !tbaa !5
  %7 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %4) #3
  %8 = load i8, ptr %4, align 1, !tbaa !5
  %9 = and i8 %8, -16
  store i8 %9, ptr %4, align 1, !tbaa !5
  %10 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %4) #3
  %11 = call i32 @inv_imu_switch_on_mclk(ptr noundef %0) #3
  %12 = call i32 @inv_imu_reset_dmp(ptr noundef %0, i32 noundef 1) #3
  %13 = getelementptr inbounds i8, ptr %0, i64 4184
  store i8 0, ptr %13, align 8, !tbaa !8
  %14 = call i32 @inv_imu_load_selftest_data(ptr noundef %0)
  %15 = call i32 @configure_selftest_parameters(ptr noundef %0, i64 %1)
  %16 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 20, i32 noundef 1, ptr noundef nonnull %4) #3
  %17 = load i8, ptr %4, align 1, !tbaa !5
  %18 = and i8 %17, 63
  %19 = trunc i64 %.sroa.2.0.extract.shift to i8
  %20 = or i8 %18, %19
  store i8 %20, ptr %4, align 1, !tbaa !5
  %21 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 20, i32 noundef 1, ptr noundef nonnull %4) #3
  call void @inv_imu_sleep_us(i32 noundef 1000) #3
  %22 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65594, i32 noundef 1, ptr noundef nonnull %6) #3
  %23 = load i8, ptr %6, align 1, !tbaa !5
  %24 = and i8 %23, -128
  store i8 %24, ptr %6, align 1, !tbaa !5
  %25 = or i32 %10, %7
  %26 = or i32 %25, %11
  %27 = or i32 %26, %12
  %28 = or i32 %27, %14
  %29 = or i32 %28, %15
  %30 = or i32 %29, %16
  %31 = or i32 %30, %21
  %32 = or i32 %22, %31
  %.not.peel = icmp eq i8 %24, 0
  %.not47.peel = icmp eq i32 %32, 0
  %33 = select i1 %.not.peel, i1 %.not47.peel, i1 false
  br i1 %33, label %.peel.next, label %.loopexit50

.peel.next:                                       ; preds = %3, %39
  %.0 = phi i32 [ %37, %39 ], [ 999, %3 ]
  call void @inv_imu_sleep_us(i32 noundef 1000) #3
  %34 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65594, i32 noundef 1, ptr noundef nonnull %6) #3
  %35 = load i8, ptr %6, align 1, !tbaa !5
  %36 = and i8 %35, -128
  store i8 %36, ptr %6, align 1, !tbaa !5
  %37 = add nsw i32 %.0, -1
  %38 = icmp eq i32 %37, 0
  br i1 %38, label %.loopexit, label %39

39:                                               ; preds = %.peel.next
  %.not = icmp eq i8 %36, 0
  %.not47 = icmp eq i32 %34, 0
  %40 = select i1 %.not, i1 %.not47, i1 false
  br i1 %40, label %.peel.next, label %.loopexit50, !llvm.loop !16

.loopexit50:                                      ; preds = %39, %3
  %.lcssa = phi i32 [ %32, %3 ], [ %34, %39 ]
  %41 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 100, i32 noundef 1, ptr noundef nonnull %5) #3
  %42 = load i8, ptr %5, align 1, !tbaa !5
  %43 = lshr i8 %42, 5
  %44 = getelementptr inbounds i8, ptr %2, i64 4
  %45 = and i8 %43, 3
  store i8 %45, ptr %44, align 1, !tbaa !19
  %46 = lshr i8 %42, 1
  %47 = and i8 %46, 1
  %48 = getelementptr inbounds i8, ptr %2, i64 5
  store i8 %47, ptr %48, align 1, !tbaa !21
  %49 = lshr i8 %42, 2
  %50 = and i8 %49, 1
  %51 = getelementptr inbounds i8, ptr %2, i64 6
  store i8 %50, ptr %51, align 1, !tbaa !22
  %52 = lshr i8 %42, 3
  %53 = and i8 %52, 1
  %54 = getelementptr inbounds i8, ptr %2, i64 7
  store i8 %53, ptr %54, align 1, !tbaa !23
  %55 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 99, i32 noundef 1, ptr noundef nonnull %5) #3
  %56 = load i8, ptr %5, align 1, !tbaa !5
  %57 = lshr i8 %56, 5
  %58 = and i8 %57, 1
  store i8 %58, ptr %2, align 1, !tbaa !24
  %59 = lshr i8 %56, 1
  %60 = and i8 %59, 1
  %61 = getelementptr inbounds i8, ptr %2, i64 1
  store i8 %60, ptr %61, align 1, !tbaa !25
  %62 = lshr i8 %56, 2
  %63 = and i8 %62, 1
  %64 = getelementptr inbounds i8, ptr %2, i64 2
  store i8 %63, ptr %64, align 1, !tbaa !26
  %65 = lshr i8 %56, 3
  %66 = and i8 %65, 1
  %67 = getelementptr inbounds i8, ptr %2, i64 3
  store i8 %66, ptr %67, align 1, !tbaa !27
  %68 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 20, i32 noundef 1, ptr noundef nonnull %4) #3
  %69 = load i8, ptr %4, align 1, !tbaa !5
  %70 = and i8 %69, 63
  store i8 %70, ptr %4, align 1, !tbaa !5
  %71 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 20, i32 noundef 1, ptr noundef nonnull %4) #3
  %72 = call i32 @inv_imu_reset_fifo(ptr noundef %0) #3
  %73 = call i32 @inv_imu_switch_off_mclk(ptr noundef %0) #3
  %74 = or i32 %41, %55
  %75 = or i32 %74, %68
  %76 = or i32 %75, %71
  %77 = or i32 %76, %72
  %78 = or i32 %77, %73
  %79 = or i32 %78, %.lcssa
  br label %.loopexit

.loopexit:                                        ; preds = %.peel.next, %.loopexit50
  %.045 = phi i32 [ %79, %.loopexit50 ], [ -1, %.peel.next ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  ret i32 %.045
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

declare i32 @inv_imu_switch_on_mclk(ptr noundef) local_unnamed_addr #2

declare i32 @inv_imu_reset_dmp(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_load_selftest_data(ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @configure_selftest_parameters(ptr noundef, i64) local_unnamed_addr #0

declare void @inv_imu_sleep_us(i32 noundef) local_unnamed_addr #2

declare i32 @inv_imu_reset_fifo(ptr noundef) local_unnamed_addr #2

declare i32 @inv_imu_switch_off_mclk(ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !6, i64 4184}
!9 = !{!"inv_imu_device", !10, i64 0, !12, i64 48, !6, i64 56, !6, i64 4184, !6, i64 4185, !6, i64 4186, !13, i64 4188, !15, i64 4192, !15, i64 4200}
!10 = !{!"inv_imu_transport", !11, i64 0, !14, i64 40, !6, i64 44}
!11 = !{!"inv_imu_serif", !12, i64 0, !12, i64 8, !12, i64 16, !13, i64 24, !13, i64 28, !13, i64 32}
!12 = !{!"any pointer", !6, i64 0}
!13 = !{!"int", !6, i64 0}
!14 = !{!"register_cache", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3}
!15 = !{!"long", !6, i64 0}
!16 = distinct !{!16, !17, !18}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!"llvm.loop.peeled.count", i32 1}
!19 = !{!20, !6, i64 4}
!20 = !{!"", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3, !6, i64 4, !6, i64 5, !6, i64 6, !6, i64 7}
!21 = !{!20, !6, i64 5}
!22 = !{!20, !6, i64 6}
!23 = !{!20, !6, i64 7}
!24 = !{!20, !6, i64 0}
!25 = !{!20, !6, i64 1}
!26 = !{!20, !6, i64 2}
!27 = !{!20, !6, i64 3}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopFullUnrollPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass