; LLVM IR from div-bargali/Data-Structures-and-Algorithms :: C++/Algorithms/Sorting-Algorithms/3-Way Quick Sort (3_Way_Quick_Sort)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z9partitionPiiiRiS0_(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4) #0 {
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !5
  %16 = load i32, ptr %7, align 4, !tbaa !9
  %17 = sub nsw i32 %16, 1
  %18 = load ptr, ptr %9, align 8, !tbaa !5
  store i32 %17, ptr %18, align 4, !tbaa !9
  %19 = load i32, ptr %8, align 4, !tbaa !9
  %20 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %19, ptr %20, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %21 = load i32, ptr %7, align 4, !tbaa !9
  %22 = sub nsw i32 %21, 1
  store i32 %22, ptr %11, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  %23 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %23, ptr %12, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #3
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = load i32, ptr %8, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = getelementptr inbounds i32, ptr %24, i64 %26
  %28 = load i32, ptr %27, align 4, !tbaa !9
  store i32 %28, ptr %13, align 4, !tbaa !9
  br label %29

29:                                               ; preds = %119, %5
  br label %30

30:                                               ; preds = %29
  br label %31

31:                                               ; preds = %41, %30
  %32 = load ptr, ptr %6, align 8, !tbaa !5
  %33 = load ptr, ptr %9, align 8, !tbaa !5
  %34 = load i32, ptr %33, align 4, !tbaa !9
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %33, align 4, !tbaa !9
  %36 = sext i32 %35 to i64
  %37 = getelementptr inbounds i32, ptr %32, i64 %36
  %38 = load i32, ptr %37, align 4, !tbaa !9
  %39 = load i32, ptr %13, align 4, !tbaa !9
  %40 = icmp slt i32 %38, %39
  br i1 %40, label %41, label %42

41:                                               ; preds = %31
  br label %31, !llvm.loop !11

42:                                               ; preds = %31
  br label %43

43:                                               ; preds = %59, %42
  %44 = load i32, ptr %13, align 4, !tbaa !9
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  %46 = load ptr, ptr %10, align 8, !tbaa !5
  %47 = load i32, ptr %46, align 4, !tbaa !9
  %48 = add nsw i32 %47, -1
  store i32 %48, ptr %46, align 4, !tbaa !9
  %49 = sext i32 %48 to i64
  %50 = getelementptr inbounds i32, ptr %45, i64 %49
  %51 = load i32, ptr %50, align 4, !tbaa !9
  %52 = icmp slt i32 %44, %51
  br i1 %52, label %53, label %60

53:                                               ; preds = %43
  %54 = load ptr, ptr %10, align 8, !tbaa !5
  %55 = load i32, ptr %54, align 4, !tbaa !9
  %56 = load i32, ptr %7, align 4, !tbaa !9
  %57 = icmp eq i32 %55, %56
  br i1 %57, label %58, label %59

58:                                               ; preds = %53
  br label %60

59:                                               ; preds = %53
  br label %43, !llvm.loop !13

60:                                               ; preds = %58, %43
  %61 = load ptr, ptr %9, align 8, !tbaa !5
  %62 = load i32, ptr %61, align 4, !tbaa !9
  %63 = load ptr, ptr %10, align 8, !tbaa !5
  %64 = load i32, ptr %63, align 4, !tbaa !9
  %65 = icmp sge i32 %62, %64
  br i1 %65, label %66, label %67

66:                                               ; preds = %60
  br label %120

67:                                               ; preds = %60
  %68 = load ptr, ptr %6, align 8, !tbaa !5
  %69 = load ptr, ptr %9, align 8, !tbaa !5
  %70 = load i32, ptr %69, align 4, !tbaa !9
  %71 = sext i32 %70 to i64
  %72 = getelementptr inbounds i32, ptr %68, i64 %71
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  %74 = load ptr, ptr %10, align 8, !tbaa !5
  %75 = load i32, ptr %74, align 4, !tbaa !9
  %76 = sext i32 %75 to i64
  %77 = getelementptr inbounds i32, ptr %73, i64 %76
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %72, ptr noundef nonnull align 4 dereferenceable(4) %77) #3
  %78 = load ptr, ptr %6, align 8, !tbaa !5
  %79 = load ptr, ptr %9, align 8, !tbaa !5
  %80 = load i32, ptr %79, align 4, !tbaa !9
  %81 = sext i32 %80 to i64
  %82 = getelementptr inbounds i32, ptr %78, i64 %81
  %83 = load i32, ptr %82, align 4, !tbaa !9
  %84 = load i32, ptr %13, align 4, !tbaa !9
  %85 = icmp eq i32 %83, %84
  br i1 %85, label %86, label %98

86:                                               ; preds = %67
  %87 = load i32, ptr %11, align 4, !tbaa !9
  %88 = add nsw i32 %87, 1
  store i32 %88, ptr %11, align 4, !tbaa !9
  %89 = load ptr, ptr %6, align 8, !tbaa !5
  %90 = load i32, ptr %11, align 4, !tbaa !9
  %91 = sext i32 %90 to i64
  %92 = getelementptr inbounds i32, ptr %89, i64 %91
  %93 = load ptr, ptr %6, align 8, !tbaa !5
  %94 = load ptr, ptr %9, align 8, !tbaa !5
  %95 = load i32, ptr %94, align 4, !tbaa !9
  %96 = sext i32 %95 to i64
  %97 = getelementptr inbounds i32, ptr %93, i64 %96
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %92, ptr noundef nonnull align 4 dereferenceable(4) %97) #3
  br label %98

98:                                               ; preds = %86, %67
  %99 = load ptr, ptr %6, align 8, !tbaa !5
  %100 = load ptr, ptr %10, align 8, !tbaa !5
  %101 = load i32, ptr %100, align 4, !tbaa !9
  %102 = sext i32 %101 to i64
  %103 = getelementptr inbounds i32, ptr %99, i64 %102
  %104 = load i32, ptr %103, align 4, !tbaa !9
  %105 = load i32, ptr %13, align 4, !tbaa !9
  %106 = icmp eq i32 %104, %105
  br i1 %106, label %107, label %119

107:                                              ; preds = %98
  %108 = load i32, ptr %12, align 4, !tbaa !9
  %109 = add nsw i32 %108, -1
  store i32 %109, ptr %12, align 4, !tbaa !9
  %110 = load ptr, ptr %6, align 8, !tbaa !5
  %111 = load ptr, ptr %10, align 8, !tbaa !5
  %112 = load i32, ptr %111, align 4, !tbaa !9
  %113 = sext i32 %112 to i64
  %114 = getelementptr inbounds i32, ptr %110, i64 %113
  %115 = load ptr, ptr %6, align 8, !tbaa !5
  %116 = load i32, ptr %12, align 4, !tbaa !9
  %117 = sext i32 %116 to i64
  %118 = getelementptr inbounds i32, ptr %115, i64 %117
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %114, ptr noundef nonnull align 4 dereferenceable(4) %118) #3
  br label %119

119:                                              ; preds = %107, %98
  br label %29, !llvm.loop !14

120:                                              ; preds = %66
  %121 = load ptr, ptr %6, align 8, !tbaa !5
  %122 = load ptr, ptr %9, align 8, !tbaa !5
  %123 = load i32, ptr %122, align 4, !tbaa !9
  %124 = sext i32 %123 to i64
  %125 = getelementptr inbounds i32, ptr %121, i64 %124
  %126 = load ptr, ptr %6, align 8, !tbaa !5
  %127 = load i32, ptr %8, align 4, !tbaa !9
  %128 = sext i32 %127 to i64
  %129 = getelementptr inbounds i32, ptr %126, i64 %128
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %125, ptr noundef nonnull align 4 dereferenceable(4) %129) #3
  %130 = load ptr, ptr %9, align 8, !tbaa !5
  %131 = load i32, ptr %130, align 4, !tbaa !9
  %132 = sub nsw i32 %131, 1
  %133 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 %132, ptr %133, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #3
  %134 = load i32, ptr %7, align 4, !tbaa !9
  store i32 %134, ptr %14, align 4, !tbaa !9
  br label %135

135:                                              ; preds = %150, %120
  %136 = load i32, ptr %14, align 4, !tbaa !9
  %137 = load i32, ptr %11, align 4, !tbaa !9
  %138 = icmp slt i32 %136, %137
  br i1 %138, label %140, label %139

139:                                              ; preds = %135
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #3
  br label %156

140:                                              ; preds = %135
  %141 = load ptr, ptr %6, align 8, !tbaa !5
  %142 = load i32, ptr %14, align 4, !tbaa !9
  %143 = sext i32 %142 to i64
  %144 = getelementptr inbounds i32, ptr %141, i64 %143
  %145 = load ptr, ptr %6, align 8, !tbaa !5
  %146 = load ptr, ptr %10, align 8, !tbaa !5
  %147 = load i32, ptr %146, align 4, !tbaa !9
  %148 = sext i32 %147 to i64
  %149 = getelementptr inbounds i32, ptr %145, i64 %148
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %144, ptr noundef nonnull align 4 dereferenceable(4) %149) #3
  br label %150

150:                                              ; preds = %140
  %151 = load i32, ptr %14, align 4, !tbaa !9
  %152 = add nsw i32 %151, 1
  store i32 %152, ptr %14, align 4, !tbaa !9
  %153 = load ptr, ptr %10, align 8, !tbaa !5
  %154 = load i32, ptr %153, align 4, !tbaa !9
  %155 = add nsw i32 %154, -1
  store i32 %155, ptr %153, align 4, !tbaa !9
  br label %135, !llvm.loop !15

156:                                              ; preds = %139
  %157 = load ptr, ptr %9, align 8, !tbaa !5
  %158 = load i32, ptr %157, align 4, !tbaa !9
  %159 = add nsw i32 %158, 1
  %160 = load ptr, ptr %9, align 8, !tbaa !5
  store i32 %159, ptr %160, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #3
  %161 = load i32, ptr %8, align 4, !tbaa !9
  %162 = sub nsw i32 %161, 1
  store i32 %162, ptr %15, align 4, !tbaa !9
  br label %163

163:                                              ; preds = %178, %156
  %164 = load i32, ptr %15, align 4, !tbaa !9
  %165 = load i32, ptr %12, align 4, !tbaa !9
  %166 = icmp sgt i32 %164, %165
  br i1 %166, label %168, label %167

167:                                              ; preds = %163
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #3
  br label %184

168:                                              ; preds = %163
  %169 = load ptr, ptr %6, align 8, !tbaa !5
  %170 = load ptr, ptr %9, align 8, !tbaa !5
  %171 = load i32, ptr %170, align 4, !tbaa !9
  %172 = sext i32 %171 to i64
  %173 = getelementptr inbounds i32, ptr %169, i64 %172
  %174 = load ptr, ptr %6, align 8, !tbaa !5
  %175 = load i32, ptr %15, align 4, !tbaa !9
  %176 = sext i32 %175 to i64
  %177 = getelementptr inbounds i32, ptr %174, i64 %176
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %173, ptr noundef nonnull align 4 dereferenceable(4) %177) #3
  br label %178

178:                                              ; preds = %168
  %179 = load i32, ptr %15, align 4, !tbaa !9
  %180 = add nsw i32 %179, -1
  store i32 %180, ptr %15, align 4, !tbaa !9
  %181 = load ptr, ptr %9, align 8, !tbaa !5
  %182 = load i32, ptr %181, align 4, !tbaa !9
  %183 = add nsw i32 %182, 1
  store i32 %183, ptr %181, align 4, !tbaa !9
  br label %163, !llvm.loop !16

184:                                              ; preds = %167
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}
!15 = distinct !{!15, !12}
!16 = distinct !{!16, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z9partitionPiiiRiS0_(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr nocapture noundef nonnull align 4 dereferenceable(4) %3, ptr nocapture noundef nonnull align 4 dereferenceable(4) %4) local_unnamed_addr #0 {
  %6 = add nsw i32 %1, -1
  store i32 %6, ptr %3, align 4, !tbaa !5
  store i32 %2, ptr %4, align 4, !tbaa !5
  %7 = sext i32 %2 to i64
  %8 = getelementptr inbounds i32, ptr %0, i64 %7
  %9 = load i32, ptr %8, align 4, !tbaa !5
  %sext = sext i32 %1 to i64
  br label %.outer

.outer:                                           ; preds = %45, %5
  %.065.ph = phi i32 [ %47, %45 ], [ %2, %5 ]
  %.064.ph = phi i32 [ %.1, %45 ], [ %6, %5 ]
  br label %10

10:                                               ; preds = %.outer, %39
  %.064 = phi i32 [ %.1, %39 ], [ %.064.ph, %.outer ]
  %.promoted = load i32, ptr %3, align 4, !tbaa !5
  %11 = sext i32 %.promoted to i64
  br label %12

12:                                               ; preds = %12, %10
  %indvars.iv = phi i64 [ %indvars.iv.next, %12 ], [ %11, %10 ]
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %13 = trunc nsw i64 %indvars.iv.next to i32
  store i32 %13, ptr %3, align 4, !tbaa !5
  %14 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = icmp slt i32 %15, %9
  br i1 %16, label %12, label %.preheader71, !llvm.loop !9

.preheader71:                                     ; preds = %12
  %.promoted75 = load i32, ptr %4, align 4, !tbaa !5
  %17 = sext i32 %.promoted75 to i64
  br label %18

18:                                               ; preds = %.preheader71, %18
  %indvars.iv89 = phi i64 [ %17, %.preheader71 ], [ %indvars.iv.next90, %18 ]
  %indvars.iv.next90 = add nsw i64 %indvars.iv89, -1
  %19 = trunc nsw i64 %indvars.iv.next90 to i32
  store i32 %19, ptr %4, align 4, !tbaa !5
  %20 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next90
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = icmp sge i32 %9, %21
  %23 = icmp eq i64 %indvars.iv.next90, %sext
  %or.cond = or i1 %23, %22
  br i1 %or.cond, label %24, label %18, !llvm.loop !11

24:                                               ; preds = %18
  %25 = load i32, ptr %3, align 4, !tbaa !5
  %.not = icmp slt i32 %25, %19
  br i1 %.not, label %26, label %50

26:                                               ; preds = %24
  %27 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next90
  %28 = sext i32 %25 to i64
  %29 = getelementptr inbounds i32, ptr %0, i64 %28
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %29, ptr noundef nonnull align 4 dereferenceable(4) %27) #2
  %30 = load i32, ptr %3, align 4, !tbaa !5
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds i32, ptr %0, i64 %31
  %33 = load i32, ptr %32, align 4, !tbaa !5
  %34 = icmp eq i32 %33, %9
  br i1 %34, label %35, label %39

35:                                               ; preds = %26
  %36 = add nsw i32 %.064, 1
  %37 = sext i32 %36 to i64
  %38 = getelementptr inbounds i32, ptr %0, i64 %37
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %38, ptr noundef nonnull align 4 dereferenceable(4) %32) #2
  br label %39

39:                                               ; preds = %35, %26
  %.1 = phi i32 [ %36, %35 ], [ %.064, %26 ]
  %40 = load i32, ptr %4, align 4, !tbaa !5
  %41 = sext i32 %40 to i64
  %42 = getelementptr inbounds i32, ptr %0, i64 %41
  %43 = load i32, ptr %42, align 4, !tbaa !5
  %44 = icmp eq i32 %43, %9
  br i1 %44, label %45, label %10, !llvm.loop !12

45:                                               ; preds = %39
  %46 = getelementptr inbounds i32, ptr %0, i64 %41
  %47 = add nsw i32 %.065.ph, -1
  %48 = sext i32 %47 to i64
  %49 = getelementptr inbounds i32, ptr %0, i64 %48
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %46, ptr noundef nonnull align 4 dereferenceable(4) %49) #2
  br label %.outer, !llvm.loop !12

50:                                               ; preds = %24
  %51 = sext i32 %25 to i64
  %52 = getelementptr inbounds i32, ptr %0, i64 %51
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %52, ptr noundef nonnull align 4 dereferenceable(4) %8) #2
  %storemerge.in76 = load i32, ptr %3, align 4, !tbaa !5
  %storemerge77 = add nsw i32 %storemerge.in76, -1
  store i32 %storemerge77, ptr %4, align 4, !tbaa !5
  %53 = icmp sgt i32 %.064, %1
  br i1 %53, label %.lr.ph, label %.preheader

.preheader:                                       ; preds = %.lr.ph, %50
  %storemerge70.in80 = load i32, ptr %3, align 4, !tbaa !5
  %storemerge7081 = add nsw i32 %storemerge70.in80, 1
  store i32 %storemerge7081, ptr %3, align 4, !tbaa !5
  %.082 = add nsw i32 %2, -1
  %54 = icmp sgt i32 %.082, %.065.ph
  br i1 %54, label %.lr.ph85.preheader, label %._crit_edge

.lr.ph85.preheader:                               ; preds = %.preheader
  %55 = sext i32 %.082 to i64
  %56 = sext i32 %.065.ph to i64
  br label %.lr.ph85

.lr.ph:                                           ; preds = %50, %.lr.ph
  %indvars.iv92 = phi i64 [ %indvars.iv.next93, %.lr.ph ], [ %sext, %50 ]
  %storemerge79 = phi i32 [ %storemerge, %.lr.ph ], [ %storemerge77, %50 ]
  %57 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv92
  %58 = sext i32 %storemerge79 to i64
  %59 = getelementptr inbounds i32, ptr %0, i64 %58
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %57, ptr noundef nonnull align 4 dereferenceable(4) %59) #2
  %indvars.iv.next93 = add nsw i64 %indvars.iv92, 1
  %storemerge.in = load i32, ptr %4, align 4, !tbaa !5
  %storemerge = add nsw i32 %storemerge.in, -1
  store i32 %storemerge, ptr %4, align 4, !tbaa !5
  %lftr.wideiv = trunc i64 %indvars.iv.next93 to i32
  %exitcond.not = icmp eq i32 %.064, %lftr.wideiv
  br i1 %exitcond.not, label %.preheader, label %.lr.ph, !llvm.loop !13

._crit_edge:                                      ; preds = %.lr.ph85, %.preheader
  ret void

.lr.ph85:                                         ; preds = %.lr.ph85.preheader, %.lr.ph85
  %indvars.iv95 = phi i64 [ %55, %.lr.ph85.preheader ], [ %indvars.iv.next96, %.lr.ph85 ]
  %storemerge7083 = phi i32 [ %storemerge7081, %.lr.ph85.preheader ], [ %storemerge70, %.lr.ph85 ]
  %60 = sext i32 %storemerge7083 to i64
  %61 = getelementptr inbounds i32, ptr %0, i64 %60
  %62 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv95
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %61, ptr noundef nonnull align 4 dereferenceable(4) %62) #2
  %storemerge70.in = load i32, ptr %3, align 4, !tbaa !5
  %storemerge70 = add nsw i32 %storemerge70.in, 1
  store i32 %storemerge70, ptr %3, align 4, !tbaa !5
  %indvars.iv.next96 = add nsw i64 %indvars.iv95, -1
  %63 = icmp sgt i64 %indvars.iv.next96, %56
  br i1 %63, label %.lr.ph85, label %._crit_edge, !llvm.loop !14
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}
!14 = distinct !{!14, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass