; LLVM IR from bqi343/cp-notebook :: Contests/USACO Solutions/2017-18/Feb 2018/Plat (gymnast)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"struct.std::pair" = type { i64, i64 }

@n = external dso_local global i64, align 8
@N = external dso_local global i64, align 8
@ans = external dso_local global i64, align 8
@z = external dso_local global %"class.std::vector", align 8
@.str = external hidden unnamed_addr constant [12 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [2 x i8], align 1
@stdin = external global ptr, align 8
@.str.4 = external hidden unnamed_addr constant [13 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [2 x i8], align 1
@stdout = external global ptr, align 8
@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5solveixx(i32 noundef, i64 noundef, i64 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() #2 {
  %1 = alloca i32, align 4
  %2 = alloca i64, align 8
  %3 = alloca i32, align 4
  %4 = alloca %"struct.std::pair", align 8
  %5 = alloca %"struct.std::pair", align 8
  %6 = alloca i32, align 4
  store i32 0, ptr %1, align 4
  %7 = load ptr, ptr @stdin, align 8, !tbaa !5
  %8 = call ptr @freopen(ptr noundef @.str, ptr noundef @.str.3, ptr noundef %7)
  %9 = load ptr, ptr @stdout, align 8, !tbaa !5
  %10 = call ptr @freopen(ptr noundef @.str.4, ptr noundef @.str.5, ptr noundef %9)
  %11 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERx(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 8 dereferenceable(8) @n)
  %12 = load i64, ptr @n, align 8, !tbaa !9
  store i64 %12, ptr @N, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %2) #5
  store i64 2, ptr %2, align 8, !tbaa !9
  br label %13

13:                                               ; preds = %39, %0
  %14 = load i64, ptr %2, align 8, !tbaa !9
  %15 = load i64, ptr %2, align 8, !tbaa !9
  %16 = mul nsw i64 %14, %15
  %17 = load i64, ptr @N, align 8, !tbaa !9
  %18 = icmp sle i64 %16, %17
  br i1 %18, label %20, label %19

19:                                               ; preds = %13
  call void @llvm.lifetime.end.p0(i64 8, ptr %2) #5
  br label %42

20:                                               ; preds = %13
  %21 = load i64, ptr @N, align 8, !tbaa !9
  %22 = load i64, ptr %2, align 8, !tbaa !9
  %23 = srem i64 %21, %22
  %24 = icmp eq i64 %23, 0
  br i1 %24, label %25, label %38

25:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #5
  store i32 0, ptr %3, align 4, !tbaa !11
  br label %26

26:                                               ; preds = %31, %25
  %27 = load i64, ptr @N, align 8, !tbaa !9
  %28 = load i64, ptr %2, align 8, !tbaa !9
  %29 = srem i64 %27, %28
  %30 = icmp eq i64 %29, 0
  br i1 %30, label %31, label %37

31:                                               ; preds = %26
  %32 = load i32, ptr %3, align 4, !tbaa !11
  %33 = add nsw i32 %32, 1
  store i32 %33, ptr %3, align 4, !tbaa !11
  %34 = load i64, ptr %2, align 8, !tbaa !9
  %35 = load i64, ptr @N, align 8, !tbaa !9
  %36 = sdiv i64 %35, %34
  store i64 %36, ptr @N, align 8, !tbaa !9
  br label %26, !llvm.loop !13

37:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 16, ptr %4) #5
  call void @_ZNSt4pairIxxEC2IRxRiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS5_S6_EEEbE4typeELb1EEEOS5_OS6_(ptr noundef nonnull align 8 dereferenceable(16) %4, ptr noundef nonnull align 8 dereferenceable(8) %2, ptr noundef nonnull align 4 dereferenceable(4) %3)
  call void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24) @z, ptr noundef nonnull align 8 dereferenceable(16) %4)
  call void @llvm.lifetime.end.p0(i64 16, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #5
  br label %38

38:                                               ; preds = %37, %20
  br label %39

39:                                               ; preds = %38
  %40 = load i64, ptr %2, align 8, !tbaa !9
  %41 = add nsw i64 %40, 1
  store i64 %41, ptr %2, align 8, !tbaa !9
  br label %13, !llvm.loop !15

42:                                               ; preds = %19
  %43 = load i64, ptr @N, align 8, !tbaa !9
  %44 = icmp sgt i64 %43, 1
  br i1 %44, label %45, label %46

45:                                               ; preds = %42
  call void @llvm.lifetime.start.p0(i64 16, ptr %5) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  store i32 1, ptr %6, align 4, !tbaa !11
  call void @_ZNSt4pairIxxEC2IRxiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS4_S5_EEEbE4typeELb1EEEOS4_OS5_(ptr noundef nonnull align 8 dereferenceable(16) %5, ptr noundef nonnull align 8 dereferenceable(8) @N, ptr noundef nonnull align 4 dereferenceable(4) %6)
  call void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24) @z, ptr noundef nonnull align 8 dereferenceable(16) %5)
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %5) #5
  br label %46

46:                                               ; preds = %45, %42
  %47 = load i64, ptr @n, align 8, !tbaa !9
  call void @_Z5solveixx(i32 noundef 0, i64 noundef 1, i64 noundef %47)
  %48 = load i64, ptr @ans, align 8, !tbaa !9
  %49 = load i64, ptr @n, align 8, !tbaa !9
  %50 = sub nsw i64 %48, %49
  %51 = add nsw i64 %50, 2
  %52 = srem i64 %51, 1000000007
  store i64 %52, ptr @ans, align 8, !tbaa !9
  %53 = load i64, ptr @ans, align 8, !tbaa !9
  %54 = add nsw i64 %53, 1000000007
  %55 = srem i64 %54, 1000000007
  store i64 %55, ptr @ans, align 8, !tbaa !9
  %56 = load i64, ptr @ans, align 8, !tbaa !9
  %57 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEx(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i64 noundef %56)
  %58 = load i32, ptr %1, align 4
  ret i32 %58
}

declare ptr @freopen(ptr noundef, ptr noundef, ptr noundef) #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERx(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(16)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIxxEC2IRxRiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS5_S6_EEEbE4typeELb1EEEOS5_OS6_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIxxEC2IRxiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS4_S5_EEEbE4typeELb1EEEOS4_OS5_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEx(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::pair<long long, long long>, std::allocator<std::pair<long long, long long>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::basic_istream" = type { ptr, i64, %"class.std::basic_ios" }
%"class.std::basic_ios" = type { %"class.std::ios_base", ptr, i8, i8, ptr, ptr, ptr, ptr }
%"class.std::ios_base" = type { ptr, i64, i64, i32, i32, i32, ptr, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, ptr, %"class.std::locale" }
%"struct.std::ios_base::_Words" = type { ptr, i64 }
%"class.std::locale" = type { ptr }
%"class.std::basic_ostream" = type { ptr, %"class.std::basic_ios" }
%"struct.std::pair" = type { i64, i64 }

@n = external dso_local global i64, align 8
@N = external dso_local global i64, align 8
@ans = external dso_local local_unnamed_addr global i64, align 8
@z = external dso_local global %"class.std::vector", align 8
@.str = external hidden unnamed_addr constant [12 x i8], align 1
@.str.3 = external hidden unnamed_addr constant [2 x i8], align 1
@stdin = external local_unnamed_addr global ptr, align 8
@.str.4 = external hidden unnamed_addr constant [13 x i8], align 1
@.str.5 = external hidden unnamed_addr constant [2 x i8], align 1
@stdout = external local_unnamed_addr global ptr, align 8
@_ZSt3cin = external global %"class.std::basic_istream", align 8
@_ZSt4cout = external global %"class.std::basic_ostream", align 8

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z5solveixx(i32 noundef, i64 noundef, i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main() local_unnamed_addr #2 {
  %1 = alloca i64, align 8
  %2 = alloca i32, align 4
  %3 = alloca %"struct.std::pair", align 8
  %4 = alloca %"struct.std::pair", align 8
  %5 = alloca i32, align 4
  %6 = load ptr, ptr @stdin, align 8, !tbaa !5
  %7 = tail call ptr @freopen(ptr noundef nonnull @.str, ptr noundef nonnull @.str.3, ptr noundef %6)
  %8 = load ptr, ptr @stdout, align 8, !tbaa !5
  %9 = tail call ptr @freopen(ptr noundef nonnull @.str.4, ptr noundef nonnull @.str.5, ptr noundef %8)
  %10 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERx(ptr noundef nonnull align 8 dereferenceable(16) @_ZSt3cin, ptr noundef nonnull align 8 dereferenceable(8) @n)
  %11 = load i64, ptr @n, align 8, !tbaa !9
  store i64 %11, ptr @N, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %1) #5
  store i64 2, ptr %1, align 8, !tbaa !9
  %.not4 = icmp slt i64 %11, 4
  br i1 %.not4, label %._crit_edge8, label %.lr.ph7

._crit_edge8:                                     ; preds = %22, %0
  %.lcssa = phi i64 [ %11, %0 ], [ %.pr, %22 ]
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %1) #5
  %12 = icmp sgt i64 %.lcssa, 1
  br i1 %12, label %26, label %27

.lr.ph7:                                          ; preds = %0, %22
  %.pr12 = phi i64 [ %.pr, %22 ], [ %11, %0 ]
  %storemerge5 = phi i64 [ %24, %22 ], [ 2, %0 ]
  %13 = srem i64 %.pr12, %storemerge5
  %14 = icmp eq i64 %13, 0
  br i1 %14, label %.lr.ph.preheader, label %22

.lr.ph.preheader:                                 ; preds = %.lr.ph7
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #5
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph.preheader, %.lr.ph
  %15 = phi i64 [ %18, %.lr.ph ], [ %.pr12, %.lr.ph.preheader ]
  %16 = phi i32 [ %17, %.lr.ph ], [ 0, %.lr.ph.preheader ]
  %17 = add nuw nsw i32 %16, 1
  %18 = sdiv i64 %15, %storemerge5
  %19 = srem i64 %18, %storemerge5
  %20 = icmp eq i64 %19, 0
  br i1 %20, label %.lr.ph, label %21, !llvm.loop !11

21:                                               ; preds = %.lr.ph
  store i32 %17, ptr %2, align 4, !tbaa !13
  store i64 %18, ptr @N, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3) #5
  call void @_ZNSt4pairIxxEC2IRxRiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS5_S6_EEEbE4typeELb1EEEOS5_OS6_(ptr noundef nonnull align 8 dereferenceable(16) %3, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 4 dereferenceable(4) %2)
  call void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24) @z, ptr noundef nonnull align 8 dereferenceable(16) %3)
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %3) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #5
  %.pre = load i64, ptr %1, align 8, !tbaa !9
  %.pr.pre = load i64, ptr @N, align 8, !tbaa !9
  br label %22

22:                                               ; preds = %.lr.ph7, %21
  %.pr = phi i64 [ %.pr12, %.lr.ph7 ], [ %.pr.pre, %21 ]
  %23 = phi i64 [ %storemerge5, %.lr.ph7 ], [ %.pre, %21 ]
  %24 = add nsw i64 %23, 1
  store i64 %24, ptr %1, align 8, !tbaa !9
  %25 = mul nsw i64 %24, %24
  %.not = icmp sgt i64 %25, %.pr
  br i1 %.not, label %._crit_edge8, label %.lr.ph7, !llvm.loop !15

26:                                               ; preds = %._crit_edge8
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %5) #5
  store i32 1, ptr %5, align 4, !tbaa !13
  call void @_ZNSt4pairIxxEC2IRxiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS4_S5_EEEbE4typeELb1EEEOS4_OS5_(ptr noundef nonnull align 8 dereferenceable(16) %4, ptr noundef nonnull align 8 dereferenceable(8) @N, ptr noundef nonnull align 4 dereferenceable(4) %5)
  call void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24) @z, ptr noundef nonnull align 8 dereferenceable(16) %4)
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %5) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #5
  br label %27

27:                                               ; preds = %26, %._crit_edge8
  %28 = load i64, ptr @n, align 8, !tbaa !9
  call void @_Z5solveixx(i32 noundef 0, i64 noundef 1, i64 noundef %28)
  %29 = load i64, ptr @ans, align 8, !tbaa !9
  %30 = load i64, ptr @n, align 8, !tbaa !9
  %31 = sub nsw i64 %29, %30
  %.fr = freeze i64 %31
  %32 = add i64 %.fr, 2
  %33 = srem i64 %32, 1000000007
  %34 = add nsw i64 %33, 1000000007
  %.cmp = icmp ugt i64 %33, -1000000008
  %35 = select i1 %.cmp, i64 %34, i64 %33
  store i64 %35, ptr @ans, align 8, !tbaa !9
  %36 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEx(ptr noundef nonnull align 8 dereferenceable(8) @_ZSt4cout, i64 noundef %35)
  ret i32 0
}

declare ptr @freopen(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #3

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(16) ptr @_ZNSirsERx(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt4pairIxxESaIS1_EE9push_backEOS1_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIxxEC2IRxRiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS5_S6_EEEbE4typeELb1EEEOS5_OS6_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt4pairIxxEC2IRxiTnNSt9enable_ifIXaaclsr5_PCCPE22_MoveConstructiblePairIT_T0_EEclsr5_PCCPE30_ImplicitlyMoveConvertiblePairIS4_S5_EEEbE4typeELb1EEEOS4_OS5_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 4 dereferenceable(4)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare noundef nonnull align 8 dereferenceable(8) ptr @_ZNSolsEx(ptr noundef nonnull align 8 dereferenceable(8), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = distinct !{!15, !12}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass