; LLVM IR from tfhe/spqlios-arithmetic :: test/testlib/ntt120_layouts.ll (ZN25ntt120_vec_znx_dft_layout13get_copy_zextEm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.q120_nttvec = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%struct.ntt120_vec_znx_dft_layout = type { i64, i64, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN25ntt120_vec_znx_dft_layout13get_copy_zextEm(ptr dead_on_unwind noalias writable sret(%class.q120_nttvec) align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %2) #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  store ptr %0, ptr %4, align 8
  store ptr %1, ptr %5, align 8, !tbaa !5
  store i64 %2, ptr %6, align 8, !tbaa !9
  %9 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #3
  %10 = getelementptr inbounds %struct.ntt120_vec_znx_dft_layout, ptr %9, i32 0, i32 2
  %11 = load ptr, ptr %10, align 8, !tbaa !11
  store ptr %11, ptr %7, align 8, !tbaa !5
  %12 = load i64, ptr %6, align 8, !tbaa !9
  %13 = getelementptr inbounds %struct.ntt120_vec_znx_dft_layout, ptr %9, i32 0, i32 1
  %14 = load i64, ptr %13, align 8, !tbaa !13
  %15 = icmp ult i64 %12, %14
  br i1 %15, label %16, label %26

16:                                               ; preds = %3
  %17 = getelementptr inbounds %struct.ntt120_vec_znx_dft_layout, ptr %9, i32 0, i32 0
  %18 = load i64, ptr %17, align 8, !tbaa !14
  %19 = load ptr, ptr %7, align 8, !tbaa !5
  %20 = load i64, ptr %6, align 8, !tbaa !9
  %21 = getelementptr inbounds %struct.ntt120_vec_znx_dft_layout, ptr %9, i32 0, i32 0
  %22 = load i64, ptr %21, align 8, !tbaa !14
  %23 = mul i64 %20, %22
  %24 = mul i64 %23, 4
  %25 = getelementptr inbounds i64, ptr %19, i64 %24
  call void @_ZN11q120_nttvecC1EmPK6_q120b(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %18, ptr noundef %25)
  store i32 1, ptr %8, align 4
  br label %29

26:                                               ; preds = %3
  %27 = getelementptr inbounds %struct.ntt120_vec_znx_dft_layout, ptr %9, i32 0, i32 0
  %28 = load i64, ptr %27, align 8, !tbaa !14
  call void @_ZN11q120_nttvec4zeroEm(ptr dead_on_unwind writable sret(%class.q120_nttvec) align 8 %0, i64 noundef %28)
  store i32 1, ptr %8, align 4
  br label %29

29:                                               ; preds = %26, %16
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #3
  ret void
}

declare void @_ZN11q120_nttvecC1EmPK6_q120b(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef) unnamed_addr #2

declare void @_ZN11q120_nttvec4zeroEm(ptr dead_on_unwind writable sret(%class.q120_nttvec) align 8, i64 noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 16}
!12 = !{!"_ZTS25ntt120_vec_znx_dft_layout", !10, i64 0, !10, i64 8, !6, i64 16}
!13 = !{!12, !10, i64 8}
!14 = !{!12, !10, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.q120_nttvec = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN25ntt120_vec_znx_dft_layout13get_copy_zextEm(ptr dead_on_unwind noalias writable sret(%class.q120_nttvec) align 8 %0, ptr nocapture noundef nonnull readonly align 8 dereferenceable(24) %1, i64 noundef %2) local_unnamed_addr #0 align 2 {
  %4 = getelementptr inbounds i8, ptr %1, i64 8
  %5 = load i64, ptr %4, align 8, !tbaa !5
  %6 = icmp ugt i64 %5, %2
  br i1 %6, label %7, label %13

7:                                                ; preds = %3
  %8 = getelementptr inbounds i8, ptr %1, i64 16
  %9 = load ptr, ptr %8, align 8, !tbaa !11
  %10 = load i64, ptr %1, align 8, !tbaa !12
  %11 = shl i64 %2, 5
  %.idx = mul i64 %11, %10
  %12 = getelementptr inbounds i8, ptr %9, i64 %.idx
  tail call void @_ZN11q120_nttvecC1EmPK6_q120b(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %10, ptr noundef %12)
  br label %15

13:                                               ; preds = %3
  %14 = load i64, ptr %1, align 8, !tbaa !12
  tail call void @_ZN11q120_nttvec4zeroEm(ptr dead_on_unwind writable sret(%class.q120_nttvec) align 8 %0, i64 noundef %14)
  br label %15

15:                                               ; preds = %13, %7
  ret void
}

declare void @_ZN11q120_nttvecC1EmPK6_q120b(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef) unnamed_addr #1

declare void @_ZN11q120_nttvec4zeroEm(ptr dead_on_unwind writable sret(%class.q120_nttvec) align 8, i64 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTS25ntt120_vec_znx_dft_layout", !7, i64 0, !7, i64 8, !10, i64 16}
!7 = !{!"long", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}
!11 = !{!6, !10, i64 16}
!12 = !{!6, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,TailCallElimPass