; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_apex)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_apex_parameters_t = type { i32, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_apex_get_parameters(ptr noundef %0, ptr noundef %1) #2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca [7 x i8], align 1
  %7 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  store i32 0, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 7, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  %9 = call i32 @inv_imu_read_reg(ptr noundef %8, i32 noundef 65573, i32 noundef 1, ptr noundef %7)
  %10 = load i32, ptr %5, align 4, !tbaa !9
  %11 = or i32 %10, %9
  store i32 %11, ptr %5, align 4, !tbaa !9
  %12 = load i8, ptr %7, align 1, !tbaa !11
  %13 = zext i8 %12 to i32
  %14 = and i32 %13, 8
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %15, i32 0, i32 7
  store i32 %14, ptr %16, align 4, !tbaa !12
  %17 = load ptr, ptr %3, align 8, !tbaa !5
  %18 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %19 = call i32 @inv_imu_read_reg(ptr noundef %17, i32 noundef 68, i32 noundef 7, ptr noundef %18)
  %20 = load i32, ptr %5, align 4, !tbaa !9
  %21 = or i32 %20, %19
  store i32 %21, ptr %5, align 4, !tbaa !9
  %22 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %23 = load i8, ptr %22, align 1, !tbaa !11
  %24 = zext i8 %23 to i32
  %25 = and i32 %24, 15
  %26 = load ptr, ptr %4, align 8, !tbaa !5
  %27 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %26, i32 0, i32 6
  store i32 %25, ptr %27, align 4, !tbaa !14
  %28 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %29 = load i8, ptr %28, align 1, !tbaa !11
  %30 = zext i8 %29 to i32
  %31 = and i32 %30, 240
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %32, i32 0, i32 9
  store i32 %31, ptr %33, align 4, !tbaa !15
  %34 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 1
  %35 = load i8, ptr %34, align 1, !tbaa !11
  %36 = zext i8 %35 to i32
  %37 = and i32 %36, 240
  %38 = load ptr, ptr %4, align 8, !tbaa !5
  %39 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %38, i32 0, i32 0
  store i32 %37, ptr %39, align 4, !tbaa !16
  %40 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 1
  %41 = load i8, ptr %40, align 1, !tbaa !11
  %42 = zext i8 %41 to i32
  %43 = and i32 %42, 15
  %44 = ashr i32 %43, 0
  %45 = trunc i32 %44 to i8
  %46 = load ptr, ptr %4, align 8, !tbaa !5
  %47 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %46, i32 0, i32 1
  store i8 %45, ptr %47, align 4, !tbaa !17
  %48 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 2
  %49 = load i8, ptr %48, align 1, !tbaa !11
  %50 = zext i8 %49 to i32
  %51 = and i32 %50, 224
  %52 = ashr i32 %51, 5
  %53 = trunc i32 %52 to i8
  %54 = load ptr, ptr %4, align 8, !tbaa !5
  %55 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %54, i32 0, i32 2
  store i8 %53, ptr %55, align 1, !tbaa !18
  %56 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 2
  %57 = load i8, ptr %56, align 1, !tbaa !11
  %58 = zext i8 %57 to i32
  %59 = and i32 %58, 28
  %60 = load ptr, ptr %4, align 8, !tbaa !5
  %61 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %60, i32 0, i32 3
  store i32 %59, ptr %61, align 4, !tbaa !19
  %62 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 2
  %63 = load i8, ptr %62, align 1, !tbaa !11
  %64 = zext i8 %63 to i32
  %65 = and i32 %64, 3
  %66 = load ptr, ptr %4, align 8, !tbaa !5
  %67 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %66, i32 0, i32 4
  store i32 %65, ptr %67, align 4, !tbaa !20
  %68 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 3
  %69 = load i8, ptr %68, align 1, !tbaa !11
  %70 = zext i8 %69 to i32
  %71 = and i32 %70, 192
  %72 = load ptr, ptr %4, align 8, !tbaa !5
  %73 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %72, i32 0, i32 5
  store i32 %71, ptr %73, align 4, !tbaa !21
  %74 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 3
  %75 = load i8, ptr %74, align 1, !tbaa !11
  %76 = zext i8 %75 to i32
  %77 = and i32 %76, 56
  %78 = load ptr, ptr %4, align 8, !tbaa !5
  %79 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %78, i32 0, i32 15
  store i32 %77, ptr %79, align 4, !tbaa !22
  %80 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 3
  %81 = load i8, ptr %80, align 1, !tbaa !11
  %82 = zext i8 %81 to i32
  %83 = and i32 %82, 7
  %84 = load ptr, ptr %4, align 8, !tbaa !5
  %85 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %84, i32 0, i32 18
  store i32 %83, ptr %85, align 4, !tbaa !23
  %86 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 4
  %87 = load i8, ptr %86, align 1, !tbaa !11
  %88 = zext i8 %87 to i32
  %89 = and i32 %88, 240
  %90 = load ptr, ptr %4, align 8, !tbaa !5
  %91 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %90, i32 0, i32 11
  store i32 %89, ptr %91, align 4, !tbaa !24
  %92 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 4
  %93 = load i8, ptr %92, align 1, !tbaa !11
  %94 = zext i8 %93 to i32
  %95 = and i32 %94, 14
  %96 = load ptr, ptr %4, align 8, !tbaa !5
  %97 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %96, i32 0, i32 10
  store i32 %95, ptr %97, align 4, !tbaa !25
  %98 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 4
  %99 = load i8, ptr %98, align 1, !tbaa !11
  %100 = zext i8 %99 to i32
  %101 = and i32 %100, 1
  %102 = load ptr, ptr %4, align 8, !tbaa !5
  %103 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %102, i32 0, i32 8
  store i32 %101, ptr %103, align 4, !tbaa !26
  %104 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 5
  %105 = load i8, ptr %104, align 1, !tbaa !11
  %106 = zext i8 %105 to i32
  %107 = and i32 %106, 248
  %108 = load ptr, ptr %4, align 8, !tbaa !5
  %109 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %108, i32 0, i32 14
  store i32 %107, ptr %109, align 4, !tbaa !27
  %110 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 5
  %111 = load i8, ptr %110, align 1, !tbaa !11
  %112 = zext i8 %111 to i32
  %113 = and i32 %112, 7
  %114 = load ptr, ptr %4, align 8, !tbaa !5
  %115 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %114, i32 0, i32 16
  store i32 %113, ptr %115, align 4, !tbaa !28
  %116 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 6
  %117 = load i8, ptr %116, align 1, !tbaa !11
  %118 = zext i8 %117 to i32
  %119 = and i32 %118, 248
  %120 = load ptr, ptr %4, align 8, !tbaa !5
  %121 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %120, i32 0, i32 17
  store i32 %119, ptr %121, align 4, !tbaa !29
  %122 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 6
  %123 = load i8, ptr %122, align 1, !tbaa !11
  %124 = zext i8 %123 to i32
  %125 = and i32 %124, 7
  %126 = load ptr, ptr %4, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %126, i32 0, i32 19
  store i32 %125, ptr %127, align 4, !tbaa !30
  %128 = load ptr, ptr %3, align 8, !tbaa !5
  %129 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %130 = call i32 @inv_imu_read_reg(ptr noundef %128, i32 noundef 103, i32 noundef 1, ptr noundef %129)
  %131 = load i32, ptr %5, align 4, !tbaa !9
  %132 = or i32 %131, %130
  store i32 %132, ptr %5, align 4, !tbaa !9
  %133 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %134 = load i8, ptr %133, align 1, !tbaa !11
  %135 = zext i8 %134 to i32
  %136 = and i32 %135, 240
  %137 = load ptr, ptr %4, align 8, !tbaa !5
  %138 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %137, i32 0, i32 12
  store i32 %136, ptr %138, align 4, !tbaa !31
  %139 = getelementptr inbounds [7 x i8], ptr %6, i64 0, i64 0
  %140 = load i8, ptr %139, align 1, !tbaa !11
  %141 = zext i8 %140 to i32
  %142 = and i32 %141, 15
  %143 = load ptr, ptr %4, align 8, !tbaa !5
  %144 = getelementptr inbounds %struct.inv_imu_apex_parameters_t, ptr %143, i32 0, i32 13
  store i32 %142, ptr %144, align 4, !tbaa !32
  %145 = load i32, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 7, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  ret i32 %145
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 24}
!13 = !{!"", !10, i64 0, !7, i64 4, !7, i64 5, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72}
!14 = !{!13, !10, i64 20}
!15 = !{!13, !10, i64 32}
!16 = !{!13, !10, i64 0}
!17 = !{!13, !7, i64 4}
!18 = !{!13, !7, i64 5}
!19 = !{!13, !10, i64 8}
!20 = !{!13, !10, i64 12}
!21 = !{!13, !10, i64 16}
!22 = !{!13, !10, i64 56}
!23 = !{!13, !10, i64 68}
!24 = !{!13, !10, i64 40}
!25 = !{!13, !10, i64 36}
!26 = !{!13, !10, i64 28}
!27 = !{!13, !10, i64 52}
!28 = !{!13, !10, i64 60}
!29 = !{!13, !10, i64 64}
!30 = !{!13, !10, i64 72}
!31 = !{!13, !10, i64 44}
!32 = !{!13, !10, i64 48}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_apex_get_parameters(ptr noundef %0, ptr nocapture noundef writeonly %1) local_unnamed_addr #2 {
  %3 = alloca [7 x i8], align 1
  %4 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 7, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  %5 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65573, i32 noundef 1, ptr noundef nonnull %4) #3
  %6 = load i8, ptr %4, align 1, !tbaa !5
  %7 = and i8 %6, 8
  %8 = zext nneg i8 %7 to i32
  %9 = getelementptr inbounds i8, ptr %1, i64 24
  store i32 %8, ptr %9, align 4, !tbaa !8
  %10 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 68, i32 noundef 7, ptr noundef nonnull %3) #3
  %11 = or i32 %10, %5
  %12 = load i8, ptr %3, align 1, !tbaa !5
  %13 = getelementptr inbounds i8, ptr %3, i64 1
  %14 = load i8, ptr %13, align 1, !tbaa !5
  %15 = and i8 %14, -16
  %16 = zext i8 %15 to i32
  store i32 %16, ptr %1, align 4, !tbaa !11
  %17 = and i8 %14, 15
  %18 = getelementptr inbounds i8, ptr %1, i64 4
  store i8 %17, ptr %18, align 4, !tbaa !12
  %19 = getelementptr inbounds i8, ptr %3, i64 2
  %20 = getelementptr inbounds i8, ptr %1, i64 5
  %21 = getelementptr inbounds i8, ptr %1, i64 8
  %22 = load <2 x i8>, ptr %19, align 1, !tbaa !5
  %23 = extractelement <2 x i8> %22, i64 0
  %24 = lshr i8 %23, 5
  store i8 %24, ptr %20, align 1, !tbaa !13
  %25 = shufflevector <2 x i8> %22, <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 poison>
  %26 = insertelement <4 x i8> %25, i8 %12, i64 3
  %27 = shufflevector <4 x i8> %26, <4 x i8> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
  %28 = and <4 x i8> %27, <i8 28, i8 3, i8 -64, i8 15>
  %29 = zext <4 x i8> %28 to <4 x i32>
  store <4 x i32> %29, ptr %21, align 4, !tbaa !14
  %30 = getelementptr inbounds i8, ptr %1, i64 68
  %31 = getelementptr inbounds i8, ptr %3, i64 4
  %32 = load i8, ptr %31, align 1, !tbaa !5
  %33 = getelementptr inbounds i8, ptr %1, i64 28
  %34 = insertelement <4 x i8> poison, i8 %32, i64 0
  %35 = insertelement <4 x i8> %34, i8 %12, i64 1
  %36 = shufflevector <4 x i8> %35, <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
  %37 = and <4 x i8> %36, <i8 1, i8 -16, i8 14, i8 -16>
  %38 = zext <4 x i8> %37 to <4 x i32>
  store <4 x i32> %38, ptr %33, align 4, !tbaa !14
  %39 = getelementptr inbounds i8, ptr %3, i64 5
  %40 = load i8, ptr %39, align 1, !tbaa !5
  %41 = getelementptr inbounds i8, ptr %1, i64 52
  %42 = getelementptr inbounds i8, ptr %3, i64 6
  %43 = load i8, ptr %42, align 1, !tbaa !5
  %44 = insertelement <4 x i8> %25, i8 %40, i64 0
  %45 = insertelement <4 x i8> %44, i8 %43, i64 3
  %46 = shufflevector <4 x i8> %45, <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
  %47 = and <4 x i8> %46, <i8 -8, i8 56, i8 7, i8 -8>
  %48 = zext <4 x i8> %47 to <4 x i32>
  store <4 x i32> %48, ptr %41, align 4, !tbaa !14
  %49 = shufflevector <2 x i8> %22, <2 x i8> poison, <2 x i32> <i32 1, i32 poison>
  %50 = insertelement <2 x i8> %49, i8 %43, i64 1
  %51 = and <2 x i8> %50, <i8 7, i8 7>
  %52 = zext nneg <2 x i8> %51 to <2 x i32>
  store <2 x i32> %52, ptr %30, align 4, !tbaa !14
  %53 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 103, i32 noundef 1, ptr noundef nonnull %3) #3
  %54 = or i32 %11, %53
  %55 = load i8, ptr %3, align 1, !tbaa !5
  %56 = getelementptr inbounds i8, ptr %1, i64 44
  %57 = insertelement <2 x i8> poison, i8 %55, i64 0
  %58 = shufflevector <2 x i8> %57, <2 x i8> poison, <2 x i32> zeroinitializer
  %59 = and <2 x i8> %58, <i8 -16, i8 15>
  %60 = zext <2 x i8> %59 to <2 x i32>
  store <2 x i32> %60, ptr %56, align 4, !tbaa !14
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 7, ptr nonnull %3) #3
  ret i32 %54
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !10, i64 24}
!9 = !{!"", !10, i64 0, !6, i64 4, !6, i64 5, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !10, i64 44, !10, i64 48, !10, i64 52, !10, i64 56, !10, i64 60, !10, i64 64, !10, i64 68, !10, i64 72}
!10 = !{!"int", !6, i64 0}
!11 = !{!9, !10, i64 0}
!12 = !{!9, !6, i64 4}
!13 = !{!9, !6, i64 5}
!14 = !{!10, !10, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SLPVectorizerPass,SROAPass