; LLVM IR from div-bargali/Data-Structures-and-Algorithms :: C++/Algorithms/Sorting-Algorithms/Cocktail Shaker Sort (Cocktail_Shaker_Sort)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z12CocktailSortPii(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  store i8 1, ptr %5, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 0, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  %10 = load i32, ptr %4, align 4, !tbaa !9
  %11 = sub nsw i32 %10, 1
  store i32 %11, ptr %7, align 4, !tbaa !9
  br label %12

12:                                               ; preds = %90, %2
  %13 = load i8, ptr %5, align 1, !tbaa !11, !range !13, !noundef !14
  %14 = trunc i8 %13 to i1
  br i1 %14, label %15, label %93

15:                                               ; preds = %12
  store i8 0, ptr %5, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  %16 = load i32, ptr %6, align 4, !tbaa !9
  store i32 %16, ptr %8, align 4, !tbaa !9
  br label %17

17:                                               ; preds = %46, %15
  %18 = load i32, ptr %8, align 4, !tbaa !9
  %19 = load i32, ptr %7, align 4, !tbaa !9
  %20 = icmp slt i32 %18, %19
  br i1 %20, label %22, label %21

21:                                               ; preds = %17
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  br label %49

22:                                               ; preds = %17
  %23 = load ptr, ptr %3, align 8, !tbaa !5
  %24 = load i32, ptr %8, align 4, !tbaa !9
  %25 = sext i32 %24 to i64
  %26 = getelementptr inbounds i32, ptr %23, i64 %25
  %27 = load i32, ptr %26, align 4, !tbaa !9
  %28 = load ptr, ptr %3, align 8, !tbaa !5
  %29 = load i32, ptr %8, align 4, !tbaa !9
  %30 = add nsw i32 %29, 1
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds i32, ptr %28, i64 %31
  %33 = load i32, ptr %32, align 4, !tbaa !9
  %34 = icmp sgt i32 %27, %33
  br i1 %34, label %35, label %45

35:                                               ; preds = %22
  %36 = load ptr, ptr %3, align 8, !tbaa !5
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds i32, ptr %36, i64 %38
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = load i32, ptr %8, align 4, !tbaa !9
  %42 = add nsw i32 %41, 1
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds i32, ptr %40, i64 %43
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %39, ptr noundef nonnull align 4 dereferenceable(4) %44) #3
  store i8 1, ptr %5, align 1, !tbaa !11
  br label %45

45:                                               ; preds = %35, %22
  br label %46

46:                                               ; preds = %45
  %47 = load i32, ptr %8, align 4, !tbaa !9
  %48 = add nsw i32 %47, 1
  store i32 %48, ptr %8, align 4, !tbaa !9
  br label %17, !llvm.loop !15

49:                                               ; preds = %21
  %50 = load i8, ptr %5, align 1, !tbaa !11, !range !13, !noundef !14
  %51 = trunc i8 %50 to i1
  br i1 %51, label %53, label %52

52:                                               ; preds = %49
  br label %93

53:                                               ; preds = %49
  store i8 0, ptr %5, align 1, !tbaa !11
  %54 = load i32, ptr %7, align 4, !tbaa !9
  %55 = add nsw i32 %54, -1
  store i32 %55, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %56 = load i32, ptr %7, align 4, !tbaa !9
  %57 = sub nsw i32 %56, 1
  store i32 %57, ptr %9, align 4, !tbaa !9
  br label %58

58:                                               ; preds = %87, %53
  %59 = load i32, ptr %9, align 4, !tbaa !9
  %60 = load i32, ptr %6, align 4, !tbaa !9
  %61 = icmp sge i32 %59, %60
  br i1 %61, label %63, label %62

62:                                               ; preds = %58
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %90

63:                                               ; preds = %58
  %64 = load ptr, ptr %3, align 8, !tbaa !5
  %65 = load i32, ptr %9, align 4, !tbaa !9
  %66 = sext i32 %65 to i64
  %67 = getelementptr inbounds i32, ptr %64, i64 %66
  %68 = load i32, ptr %67, align 4, !tbaa !9
  %69 = load ptr, ptr %3, align 8, !tbaa !5
  %70 = load i32, ptr %9, align 4, !tbaa !9
  %71 = add nsw i32 %70, 1
  %72 = sext i32 %71 to i64
  %73 = getelementptr inbounds i32, ptr %69, i64 %72
  %74 = load i32, ptr %73, align 4, !tbaa !9
  %75 = icmp sgt i32 %68, %74
  br i1 %75, label %76, label %86

76:                                               ; preds = %63
  %77 = load ptr, ptr %3, align 8, !tbaa !5
  %78 = load i32, ptr %9, align 4, !tbaa !9
  %79 = sext i32 %78 to i64
  %80 = getelementptr inbounds i32, ptr %77, i64 %79
  %81 = load ptr, ptr %3, align 8, !tbaa !5
  %82 = load i32, ptr %9, align 4, !tbaa !9
  %83 = add nsw i32 %82, 1
  %84 = sext i32 %83 to i64
  %85 = getelementptr inbounds i32, ptr %81, i64 %84
  call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %80, ptr noundef nonnull align 4 dereferenceable(4) %85) #3
  store i8 1, ptr %5, align 1, !tbaa !11
  br label %86

86:                                               ; preds = %76, %63
  br label %87

87:                                               ; preds = %86
  %88 = load i32, ptr %9, align 4, !tbaa !9
  %89 = add nsw i32 %88, -1
  store i32 %89, ptr %9, align 4, !tbaa !9
  br label %58, !llvm.loop !17

90:                                               ; preds = %62
  %91 = load i32, ptr %6, align 4, !tbaa !9
  %92 = add nsw i32 %91, 1
  store i32 %92, ptr %6, align 4, !tbaa !9
  br label %12, !llvm.loop !18

93:                                               ; preds = %52, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = distinct !{!15, !16}
!16 = !{!"llvm.loop.mustprogress"}
!17 = distinct !{!17, !16}
!18 = distinct !{!18, !16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z12CocktailSortPii(ptr noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = add nsw i32 %1, -1
  %4 = add i32 %1, -3
  %5 = zext i32 %3 to i64
  br label %.preheader

.preheader:                                       ; preds = %2, %._crit_edge39
  %indvars.iv53 = phi i64 [ %5, %2 ], [ %indvars.iv.next54, %._crit_edge39 ]
  %indvars.iv49 = phi i32 [ %4, %2 ], [ %indvars.iv.next50, %._crit_edge39 ]
  %indvars.iv = phi i64 [ 0, %2 ], [ %indvars.iv.next, %._crit_edge39 ]
  %.029.in43 = phi i32 [ %1, %2 ], [ %.02944, %._crit_edge39 ]
  %6 = sext i32 %indvars.iv49 to i64
  %.02944 = add nsw i32 %.029.in43, -1
  %7 = sext i32 %.02944 to i64
  %8 = icmp slt i64 %indvars.iv, %7
  br i1 %8, label %.lr.ph.outer, label %.critedge

.lr.ph.outer:                                     ; preds = %.preheader, %.thread
  %indvars.iv45.ph = phi i64 [ %indvars.iv.next46, %.thread ], [ %indvars.iv, %.preheader ]
  %.132.ph = phi i1 [ true, %.thread ], [ false, %.preheader ]
  br label %.lr.ph

._crit_edge:                                      ; preds = %14
  br i1 %.132.ph, label %._crit_edge.thread, label %.critedge

.lr.ph:                                           ; preds = %.lr.ph.outer, %14
  %indvars.iv45 = phi i64 [ %indvars.iv.next46, %14 ], [ %indvars.iv45.ph, %.lr.ph.outer ]
  %9 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv45
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %indvars.iv.next46 = add nuw nsw i64 %indvars.iv45, 1
  %11 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next46
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %13 = icmp sgt i32 %10, %12
  br i1 %13, label %.thread, label %14

14:                                               ; preds = %.lr.ph
  %exitcond.not = icmp eq i64 %indvars.iv.next46, %indvars.iv53
  br i1 %exitcond.not, label %._crit_edge, label %.lr.ph, !llvm.loop !9

.thread:                                          ; preds = %.lr.ph
  %15 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv45
  %16 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next46
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %15, ptr noundef nonnull align 4 dereferenceable(4) %16) #2
  %exitcond.not59 = icmp eq i64 %indvars.iv.next46, %indvars.iv53
  br i1 %exitcond.not59, label %._crit_edge.thread, label %.lr.ph.outer, !llvm.loop !9

._crit_edge.thread:                               ; preds = %.thread, %._crit_edge
  %17 = add nsw i32 %.029.in43, -3
  %18 = sext i32 %17 to i64
  %.not34 = icmp sgt i64 %indvars.iv, %18
  br i1 %.not34, label %.critedge, label %.lr.ph38

._crit_edge39:                                    ; preds = %25
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %indvars.iv.next54 = add nsw i64 %indvars.iv53, -1
  %indvars.iv.next50 = add i32 %indvars.iv49, -1
  br i1 %.4, label %.preheader, label %.critedge, !llvm.loop !11

.lr.ph38:                                         ; preds = %._crit_edge.thread, %25
  %indvars.iv51 = phi i64 [ %indvars.iv.next52, %25 ], [ %6, %._crit_edge.thread ]
  %.335 = phi i1 [ %.4, %25 ], [ false, %._crit_edge.thread ]
  %19 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv51
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %21 = getelementptr i8, ptr %19, i64 4
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = icmp sgt i32 %20, %22
  br i1 %23, label %24, label %25

24:                                               ; preds = %.lr.ph38
  tail call void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4) %19, ptr noundef nonnull align 4 dereferenceable(4) %21) #2
  br label %25

25:                                               ; preds = %.lr.ph38, %24
  %.4 = phi i1 [ true, %24 ], [ %.335, %.lr.ph38 ]
  %indvars.iv.next52 = add nsw i64 %indvars.iv51, -1
  %.not.not = icmp sgt i64 %indvars.iv51, %indvars.iv
  br i1 %.not.not, label %.lr.ph38, label %._crit_edge39, !llvm.loop !12

.critedge:                                        ; preds = %._crit_edge.thread, %.preheader, %._crit_edge, %._crit_edge39
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZSt4swapIiENSt9enable_ifIXsr6__and_ISt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS3_ESt18is_move_assignableIS3_EEE5valueEvE4typeERS3_SC_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass