; LLVM IR from bqi343/cp-notebook :: Contests/USACO Solutions/2015-16/Jan 2016/Bronze/16 Jan B2.ll (Z4testi)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@ans = external dso_local global i32, align 4
@N = external dso_local global i32, align 4
@x = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_Z4testi(i32 noundef %0) #0 {
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  store i32 %0, ptr %2, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #4
  %9 = load i32, ptr %2, align 4, !tbaa !5
  store i32 %9, ptr %3, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  store i32 1, ptr %5, align 4, !tbaa !5
  br label %10

10:                                               ; preds = %41, %1
  br label %11

11:                                               ; preds = %10
  %12 = load i32, ptr %3, align 4, !tbaa !5
  store i32 %12, ptr %4, align 4, !tbaa !5
  br label %13

13:                                               ; preds = %33, %11
  %14 = load i32, ptr %3, align 4, !tbaa !5
  %15 = load i32, ptr @N, align 4, !tbaa !5
  %16 = sub nsw i32 %15, 1
  %17 = icmp slt i32 %14, %16
  br i1 %17, label %18, label %31

18:                                               ; preds = %13
  %19 = load i32, ptr %3, align 4, !tbaa !5
  %20 = add nsw i32 %19, 1
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %21) #4
  %23 = load i32, ptr %22, align 4, !tbaa !5
  %24 = load i32, ptr %4, align 4, !tbaa !5
  %25 = sext i32 %24 to i64
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %25) #4
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = sub nsw i32 %23, %27
  %29 = load i32, ptr %5, align 4, !tbaa !5
  %30 = icmp sle i32 %28, %29
  br label %31

31:                                               ; preds = %18, %13
  %32 = phi i1 [ false, %13 ], [ %30, %18 ]
  br i1 %32, label %33, label %36

33:                                               ; preds = %31
  %34 = load i32, ptr %3, align 4, !tbaa !5
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %3, align 4, !tbaa !5
  br label %13, !llvm.loop !9

36:                                               ; preds = %31
  %37 = load i32, ptr %3, align 4, !tbaa !5
  %38 = load i32, ptr %4, align 4, !tbaa !5
  %39 = icmp eq i32 %37, %38
  br i1 %39, label %40, label %41

40:                                               ; preds = %36
  br label %44

41:                                               ; preds = %36
  %42 = load i32, ptr %5, align 4, !tbaa !5
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %5, align 4, !tbaa !5
  br label %10, !llvm.loop !11

44:                                               ; preds = %40
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %45 = load i32, ptr %2, align 4, !tbaa !5
  store i32 %45, ptr %6, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 1, ptr %5, align 4, !tbaa !5
  br label %46

46:                                               ; preds = %75, %44
  br label %47

47:                                               ; preds = %46
  %48 = load i32, ptr %6, align 4, !tbaa !5
  store i32 %48, ptr %7, align 4, !tbaa !5
  br label %49

49:                                               ; preds = %67, %47
  %50 = load i32, ptr %6, align 4, !tbaa !5
  %51 = icmp sgt i32 %50, 0
  br i1 %51, label %52, label %65

52:                                               ; preds = %49
  %53 = load i32, ptr %7, align 4, !tbaa !5
  %54 = sext i32 %53 to i64
  %55 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %54) #4
  %56 = load i32, ptr %55, align 4, !tbaa !5
  %57 = load i32, ptr %6, align 4, !tbaa !5
  %58 = sub nsw i32 %57, 1
  %59 = sext i32 %58 to i64
  %60 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %59) #4
  %61 = load i32, ptr %60, align 4, !tbaa !5
  %62 = sub nsw i32 %56, %61
  %63 = load i32, ptr %5, align 4, !tbaa !5
  %64 = icmp sle i32 %62, %63
  br label %65

65:                                               ; preds = %52, %49
  %66 = phi i1 [ false, %49 ], [ %64, %52 ]
  br i1 %66, label %67, label %70

67:                                               ; preds = %65
  %68 = load i32, ptr %6, align 4, !tbaa !5
  %69 = add nsw i32 %68, -1
  store i32 %69, ptr %6, align 4, !tbaa !5
  br label %49, !llvm.loop !12

70:                                               ; preds = %65
  %71 = load i32, ptr %6, align 4, !tbaa !5
  %72 = load i32, ptr %7, align 4, !tbaa !5
  %73 = icmp eq i32 %71, %72
  br i1 %73, label %74, label %75

74:                                               ; preds = %70
  br label %78

75:                                               ; preds = %70
  %76 = load i32, ptr %5, align 4, !tbaa !5
  %77 = add nsw i32 %76, 1
  store i32 %77, ptr %5, align 4, !tbaa !5
  br label %46, !llvm.loop !13

78:                                               ; preds = %74
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #4
  %79 = load i32, ptr %3, align 4, !tbaa !5
  %80 = load i32, ptr %6, align 4, !tbaa !5
  %81 = sub nsw i32 %79, %80
  %82 = add nsw i32 %81, 1
  store i32 %82, ptr %8, align 4, !tbaa !5
  %83 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) @ans, ptr noundef nonnull align 4 dereferenceable(4) %8)
  %84 = load i32, ptr %83, align 4, !tbaa !5
  store i32 %84, ptr @ans, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #4
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@ans = external dso_local global i32, align 4
@N = external dso_local local_unnamed_addr global i32, align 4
@x = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z4testi(i32 noundef %0) local_unnamed_addr #0 {
  %2 = alloca i32, align 4
  br label %3

3:                                                ; preds = %.critedge, %1
  %.026 = phi i32 [ 1, %1 ], [ %18, %.critedge ]
  %.0 = phi i32 [ %0, %1 ], [ %16, %.critedge ]
  %4 = sext i32 %.0 to i64
  br label %5

5:                                                ; preds = %10, %3
  %indvars.iv = phi i64 [ %indvars.iv.next, %10 ], [ %4, %3 ]
  %6 = load i32, ptr @N, align 4, !tbaa !5
  %7 = add nsw i32 %6, -1
  %8 = sext i32 %7 to i64
  %9 = icmp slt i64 %indvars.iv, %8
  br i1 %9, label %10, label %.critedge

10:                                               ; preds = %5
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %11 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %indvars.iv.next) #4
  %12 = load i32, ptr %11, align 4, !tbaa !5
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %4) #4
  %14 = load i32, ptr %13, align 4, !tbaa !5
  %15 = sub nsw i32 %12, %14
  %.not = icmp sgt i32 %15, %.026
  br i1 %.not, label %.critedge, label %5, !llvm.loop !9

.critedge:                                        ; preds = %5, %10
  %16 = trunc nsw i64 %indvars.iv to i32
  %17 = icmp eq i32 %.0, %16
  %18 = add nuw nsw i32 %.026, 1
  br i1 %17, label %.preheader, label %3, !llvm.loop !11

.preheader:                                       ; preds = %.critedge, %.critedge2
  %.127 = phi i32 [ %32, %.critedge2 ], [ 1, %.critedge ]
  %.024 = phi i32 [ %.125.lcssa, %.critedge2 ], [ %0, %.critedge ]
  %19 = sext i32 %.024 to i64
  %20 = zext i32 %.024 to i64
  %smin = tail call i32 @llvm.smin.i32(i32 %.024, i32 0)
  br label %21

21:                                               ; preds = %24, %.preheader
  %indvars.iv30 = phi i64 [ %27, %24 ], [ %20, %.preheader ]
  %22 = trunc nuw i64 %indvars.iv30 to i32
  %23 = icmp sgt i32 %22, 0
  br i1 %23, label %24, label %.critedge2

24:                                               ; preds = %21
  %25 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %19) #4
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %27 = add nsw i64 %indvars.iv30, -1
  %28 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @x, i64 noundef %27) #4
  %29 = load i32, ptr %28, align 4, !tbaa !5
  %30 = sub nsw i32 %26, %29
  %.not28 = icmp sgt i32 %30, %.127
  br i1 %.not28, label %.critedge2, label %21, !llvm.loop !12

.critedge2:                                       ; preds = %21, %24
  %.125.lcssa = phi i32 [ %smin, %21 ], [ %22, %24 ]
  %31 = icmp eq i32 %.125.lcssa, %.024
  %32 = add nuw nsw i32 %.127, 1
  br i1 %31, label %33, label %.preheader, !llvm.loop !13

33:                                               ; preds = %.critedge2
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2) #4
  %34 = add i32 %.0, 1
  %35 = sub i32 %34, %.024
  store i32 %35, ptr %2, align 4, !tbaa !5
  %36 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) @ans, ptr noundef nonnull align 4 dereferenceable(4) %2)
  %37 = load i32, ptr %36, align 4, !tbaa !5
  store i32 %37, ptr @ans, align 4, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2) #4
  ret void
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3maxIiERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.smin.i32(i32, i32) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = distinct !{!11, !10}
!12 = distinct !{!12, !10}
!13 = distinct !{!13, !10}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass