; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_transport)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden ptr @get_register_cache_addr(ptr noundef, i32 noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 -11, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %75

17:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %57, %17
  %19 = load i32, ptr %12, align 4, !tbaa !9
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = icmp ult i32 %19, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  store i32 2, ptr %11, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %60

23:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #2
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = load i32, ptr %7, align 4, !tbaa !9
  %26 = load i32, ptr %12, align 4, !tbaa !9
  %27 = add i32 %25, %26
  %28 = call ptr @get_register_cache_addr(ptr noundef %24, i32 noundef %27)
  store ptr %28, ptr %13, align 8, !tbaa !5
  %29 = load ptr, ptr %13, align 8, !tbaa !5
  %30 = icmp ne ptr %29, null
  br i1 %30, label %31, label %38

31:                                               ; preds = %23
  %32 = load ptr, ptr %9, align 8, !tbaa !5
  %33 = load i32, ptr %12, align 4, !tbaa !9
  %34 = zext i32 %33 to i64
  %35 = getelementptr inbounds i8, ptr %32, i64 %34
  %36 = load i8, ptr %35, align 1, !tbaa !11
  %37 = load ptr, ptr %13, align 8, !tbaa !5
  store i8 %36, ptr %37, align 1, !tbaa !11
  br label %38

38:                                               ; preds = %31, %23
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = and i32 %39, 65536
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %56, label %42

42:                                               ; preds = %38
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !9
  %45 = load i32, ptr %12, align 4, !tbaa !9
  %46 = add i32 %44, %45
  %47 = and i32 %46, 65535
  %48 = trunc i32 %47 to i16
  %49 = load ptr, ptr %9, align 8, !tbaa !5
  %50 = load i32, ptr %12, align 4, !tbaa !9
  %51 = zext i32 %50 to i64
  %52 = getelementptr inbounds i8, ptr %49, i64 %51
  %53 = call i32 @write_mclk_reg(ptr noundef %43, i16 noundef zeroext %48, i8 noundef zeroext 1, ptr noundef %52)
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = or i32 %54, %53
  store i32 %55, ptr %10, align 4, !tbaa !9
  br label %56

56:                                               ; preds = %42, %38
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #2
  br label %57

57:                                               ; preds = %56
  %58 = load i32, ptr %12, align 4, !tbaa !9
  %59 = add i32 %58, 1
  store i32 %59, ptr %12, align 4, !tbaa !9
  br label %18, !llvm.loop !12

60:                                               ; preds = %22
  %61 = load i32, ptr %7, align 4, !tbaa !9
  %62 = and i32 %61, 65536
  %63 = icmp ne i32 %62, 0
  br i1 %63, label %64, label %73

64:                                               ; preds = %60
  %65 = load ptr, ptr %6, align 8, !tbaa !5
  %66 = load i32, ptr %7, align 4, !tbaa !9
  %67 = trunc i32 %66 to i8
  %68 = load i32, ptr %8, align 4, !tbaa !9
  %69 = load ptr, ptr %9, align 8, !tbaa !5
  %70 = call i32 @write_sreg(ptr noundef %65, i8 noundef zeroext %67, i32 noundef %68, ptr noundef %69)
  %71 = load i32, ptr %10, align 4, !tbaa !9
  %72 = or i32 %71, %70
  store i32 %72, ptr %10, align 4, !tbaa !9
  br label %73

73:                                               ; preds = %64, %60
  %74 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %74, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %75

75:                                               ; preds = %73, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %76 = load i32, ptr %5, align 4
  ret i32 %76
}

; Function Attrs: nounwind uwtable
declare hidden i32 @write_mclk_reg(ptr noundef, i16 noundef zeroext, i8 noundef zeroext, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @write_sreg(ptr noundef, i8 noundef zeroext, i32 noundef, ptr noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden ptr @get_register_cache_addr(ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) local_unnamed_addr #0 {
  %5 = icmp eq ptr %0, null
  br i1 %5, label %._crit_edge.thread, label %.preheader

.preheader:                                       ; preds = %4
  %.not34 = icmp eq i32 %2, 0
  %.pre = and i32 %1, 65536
  %6 = icmp eq i32 %.pre, 0
  br i1 %.not34, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader
  %wide.trip.count40 = zext i32 %2 to i64
  br i1 %6, label %.lr.ph.split.us, label %.lr.ph.split

.lr.ph.split.us:                                  ; preds = %.lr.ph, %13
  %indvars.iv37 = phi i64 [ %indvars.iv.next38, %13 ], [ 0, %.lr.ph ]
  %.02632.us = phi i32 [ %17, %13 ], [ 0, %.lr.ph ]
  %7 = trunc nuw i64 %indvars.iv37 to i32
  %8 = add i32 %7, %1
  %9 = tail call ptr @get_register_cache_addr(ptr noundef nonnull %0, i32 noundef %8)
  %.not30.us = icmp eq ptr %9, null
  br i1 %.not30.us, label %13, label %10

10:                                               ; preds = %.lr.ph.split.us
  %11 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv37
  %12 = load i8, ptr %11, align 1, !tbaa !5
  store i8 %12, ptr %9, align 1, !tbaa !5
  br label %13

13:                                               ; preds = %10, %.lr.ph.split.us
  %14 = trunc i32 %8 to i16
  %15 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv37
  %16 = tail call i32 @write_mclk_reg(ptr noundef nonnull %0, i16 noundef zeroext %14, i8 noundef zeroext 1, ptr noundef %15)
  %17 = or i32 %16, %.02632.us
  %indvars.iv.next38 = add nuw nsw i64 %indvars.iv37, 1
  %exitcond41.not = icmp eq i64 %indvars.iv.next38, %wide.trip.count40
  br i1 %exitcond41.not, label %._crit_edge.thread, label %.lr.ph.split.us, !llvm.loop !8

._crit_edge:                                      ; preds = %.preheader
  br i1 %6, label %._crit_edge.thread, label %._crit_edge.thread44

.lr.ph.split:                                     ; preds = %.lr.ph, %24
  %indvars.iv = phi i64 [ %indvars.iv.next, %24 ], [ 0, %.lr.ph ]
  %18 = trunc nuw i64 %indvars.iv to i32
  %19 = add i32 %18, %1
  %20 = tail call ptr @get_register_cache_addr(ptr noundef nonnull %0, i32 noundef %19)
  %.not30 = icmp eq ptr %20, null
  br i1 %.not30, label %24, label %21

21:                                               ; preds = %.lr.ph.split
  %22 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv
  %23 = load i8, ptr %22, align 1, !tbaa !5
  store i8 %23, ptr %20, align 1, !tbaa !5
  br label %24

24:                                               ; preds = %21, %.lr.ph.split
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count40
  br i1 %exitcond.not, label %._crit_edge.thread44, label %.lr.ph.split, !llvm.loop !8

._crit_edge.thread44:                             ; preds = %24, %._crit_edge
  %25 = trunc i32 %1 to i8
  %26 = tail call i32 @write_sreg(ptr noundef nonnull %0, i8 noundef zeroext %25, i32 noundef %2, ptr noundef %3)
  br label %._crit_edge.thread

._crit_edge.thread:                               ; preds = %13, %._crit_edge, %._crit_edge.thread44, %4
  %.0 = phi i32 [ -11, %4 ], [ %26, %._crit_edge.thread44 ], [ 0, %._crit_edge ], [ %17, %13 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden i32 @write_mclk_reg(ptr noundef, i16 noundef zeroext, i8 noundef zeroext, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @write_sreg(ptr noundef, i8 noundef zeroext, i32 noundef, ptr noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass