; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_driver)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_device = type { %struct.inv_imu_transport, ptr, [4128 x i8], i8, i8, i8, i32, i64, i64 }
%struct.inv_imu_transport = type { %struct.inv_imu_serif, %struct.register_cache, i8 }
%struct.inv_imu_serif = type { ptr, ptr, ptr, i32, i32, i32 }
%struct.register_cache = type { i8, i8, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_rcosc(ptr noundef) #2

declare i64 @inv_imu_get_time_us() #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_enable_accel_low_noise_mode(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i8, align 1
  %8 = alloca i8, align 1
  %9 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  %10 = load ptr, ptr %2, align 8, !tbaa !5
  %11 = call i32 @inv_imu_read_reg(ptr noundef %10, i32 noundef 65567, i32 noundef 1, ptr noundef %7)
  %12 = load i32, ptr %3, align 4, !tbaa !9
  %13 = or i32 %12, %11
  store i32 %13, ptr %3, align 4, !tbaa !9
  %14 = load i8, ptr %7, align 1, !tbaa !11
  %15 = zext i8 %14 to i32
  %16 = and i32 %15, 3
  store i32 %16, ptr %4, align 4, !tbaa !9
  %17 = load i8, ptr %7, align 1, !tbaa !11
  %18 = zext i8 %17 to i32
  %19 = and i32 %18, 12
  store i32 %19, ptr %5, align 4, !tbaa !9
  %20 = load i32, ptr %4, align 4, !tbaa !9
  %21 = icmp eq i32 %20, 2
  br i1 %21, label %22, label %43

22:                                               ; preds = %1
  %23 = load i32, ptr %5, align 4, !tbaa !9
  %24 = icmp eq i32 %23, 0
  br i1 %24, label %28, label %25

25:                                               ; preds = %22
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = icmp eq i32 %26, 4
  br i1 %27, label %28, label %43

28:                                               ; preds = %25, %22
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %29 = load ptr, ptr %2, align 8, !tbaa !5
  %30 = call i32 @inv_imu_read_reg(ptr noundef %29, i32 noundef 65569, i32 noundef 1, ptr noundef %8)
  %31 = load i32, ptr %3, align 4, !tbaa !9
  %32 = or i32 %31, %30
  store i32 %32, ptr %3, align 4, !tbaa !9
  %33 = load i8, ptr %8, align 1, !tbaa !11
  %34 = zext i8 %33 to i32
  %35 = and i32 %34, 15
  store i32 %35, ptr %6, align 4, !tbaa !9
  %36 = load i32, ptr %6, align 4, !tbaa !9
  %37 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %36)
  store i32 %37, ptr %9, align 4, !tbaa !9
  %38 = load ptr, ptr %2, align 8, !tbaa !5
  %39 = call i32 @select_rcosc(ptr noundef %38)
  %40 = load i32, ptr %3, align 4, !tbaa !9
  %41 = or i32 %40, %39
  store i32 %41, ptr %3, align 4, !tbaa !9
  %42 = load i32, ptr %9, align 4, !tbaa !9
  call void @inv_imu_sleep_us(i32 noundef %42)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %43

43:                                               ; preds = %28, %25, %1
  %44 = load ptr, ptr %2, align 8, !tbaa !5
  %45 = call i32 @inv_imu_read_reg(ptr noundef %44, i32 noundef 65567, i32 noundef 1, ptr noundef %7)
  %46 = load i32, ptr %3, align 4, !tbaa !9
  %47 = or i32 %46, %45
  store i32 %47, ptr %3, align 4, !tbaa !9
  %48 = load i8, ptr %7, align 1, !tbaa !11
  %49 = zext i8 %48 to i32
  %50 = and i32 %49, -4
  %51 = trunc i32 %50 to i8
  store i8 %51, ptr %7, align 1, !tbaa !11
  %52 = load i8, ptr %7, align 1, !tbaa !11
  %53 = zext i8 %52 to i32
  %54 = or i32 %53, 3
  %55 = trunc i32 %54 to i8
  store i8 %55, ptr %7, align 1, !tbaa !11
  %56 = load ptr, ptr %2, align 8, !tbaa !5
  %57 = call i32 @inv_imu_write_reg(ptr noundef %56, i32 noundef 65567, i32 noundef 1, ptr noundef %7)
  %58 = load i32, ptr %3, align 4, !tbaa !9
  %59 = or i32 %58, %57
  store i32 %59, ptr %3, align 4, !tbaa !9
  call void @inv_imu_sleep_us(i32 noundef 200)
  %60 = load i32, ptr %4, align 4, !tbaa !9
  %61 = icmp eq i32 %60, 0
  br i1 %61, label %62, label %71

62:                                               ; preds = %43
  %63 = load ptr, ptr %2, align 8, !tbaa !5
  %64 = getelementptr inbounds %struct.inv_imu_device, ptr %63, i32 0, i32 6
  %65 = load i32, ptr %64, align 4, !tbaa !12
  %66 = icmp ne i32 %65, 0
  br i1 %66, label %67, label %71

67:                                               ; preds = %62
  %68 = call i64 @inv_imu_get_time_us()
  %69 = load ptr, ptr %2, align 8, !tbaa !5
  %70 = getelementptr inbounds %struct.inv_imu_device, ptr %69, i32 0, i32 8
  store i64 %68, ptr %70, align 8, !tbaa !18
  br label %71

71:                                               ; preds = %67, %62, %43
  %72 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i32 %72
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 4188}
!13 = !{!"inv_imu_device", !14, i64 0, !6, i64 48, !7, i64 56, !7, i64 4184, !7, i64 4185, !7, i64 4186, !10, i64 4188, !17, i64 4192, !17, i64 4200}
!14 = !{!"inv_imu_transport", !15, i64 0, !16, i64 40, !7, i64 44}
!15 = !{!"inv_imu_serif", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !10, i64 32}
!16 = !{!"register_cache", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!17 = !{!"long", !7, i64 0}
!18 = !{!13, !17, i64 4200}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
declare hidden i32 @select_rcosc(ptr noundef) local_unnamed_addr #2

declare i64 @inv_imu_get_time_us() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_enable_accel_low_noise_mode(ptr noundef %0) local_unnamed_addr #2 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  %4 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %5 = load i8, ptr %2, align 1, !tbaa !5
  %6 = zext i8 %5 to i32
  %7 = and i32 %6, 3
  %8 = and i32 %6, 11
  %or.cond19 = icmp eq i32 %8, 2
  br i1 %or.cond19, label %9, label %18

9:                                                ; preds = %1
  %10 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65569, i32 noundef 1, ptr noundef nonnull %3) #3
  %11 = load i8, ptr %3, align 1, !tbaa !5
  %12 = and i8 %11, 15
  %13 = zext nneg i8 %12 to i32
  %14 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %13)
  %15 = call i32 @select_rcosc(ptr noundef %0)
  %16 = or i32 %10, %15
  %17 = or i32 %16, %4
  call void @inv_imu_sleep_us(i32 noundef %14) #3
  br label %18

18:                                               ; preds = %9, %1
  %.0 = phi i32 [ %17, %9 ], [ %4, %1 ]
  %19 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %20 = load i8, ptr %2, align 1, !tbaa !5
  %21 = or i8 %20, 3
  store i8 %21, ptr %2, align 1, !tbaa !5
  %22 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  call void @inv_imu_sleep_us(i32 noundef 200) #3
  %23 = icmp eq i32 %7, 0
  br i1 %23, label %24, label %30

24:                                               ; preds = %18
  %25 = getelementptr inbounds i8, ptr %0, i64 4188
  %26 = load i32, ptr %25, align 4, !tbaa !8
  %.not = icmp eq i32 %26, 0
  br i1 %.not, label %30, label %27

27:                                               ; preds = %24
  %28 = call i64 @inv_imu_get_time_us() #3
  %29 = getelementptr inbounds i8, ptr %0, i64 4200
  store i64 %28, ptr %29, align 8, !tbaa !16
  br label %30

30:                                               ; preds = %27, %24, %18
  %31 = or i32 %19, %.0
  %32 = or i32 %31, %22
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  ret i32 %32
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !13, i64 4188}
!9 = !{!"inv_imu_device", !10, i64 0, !12, i64 48, !6, i64 56, !6, i64 4184, !6, i64 4185, !6, i64 4186, !13, i64 4188, !15, i64 4192, !15, i64 4200}
!10 = !{!"inv_imu_transport", !11, i64 0, !14, i64 40, !6, i64 44}
!11 = !{!"inv_imu_serif", !12, i64 0, !12, i64 8, !12, i64 16, !13, i64 24, !13, i64 28, !13, i64 32}
!12 = !{!"any pointer", !6, i64 0}
!13 = !{!"int", !6, i64 0}
!14 = !{!"register_cache", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3}
!15 = !{!"long", !6, i64 0}
!16 = !{!9, !15, i64 4200}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass