; LLVM IR from bqi343/cp-notebook :: Implementations/content/geometry (13)/3D/death_conveyor.ll (Z5vrandv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::mersenne_twister_engine" = type { [624 x i64], i64 }
%"struct.std::array" = type { [4 x x86_fp80] }

@rng = external dso_local global %"class.std::mersenne_twister_engine", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5vrandv(ptr dead_on_unwind noalias writable sret(%"struct.std::array") align 16 %0) #2 {
  %2 = alloca i32, align 4
  call void @llvm.memset.p0.i64(ptr align 16 %0, i8 0, i64 64, i1 false)
  call void @llvm.lifetime.start.p0(i64 4, ptr %2) #4
  store i32 0, ptr %2, align 4, !tbaa !5
  br label %3

3:                                                ; preds = %15, %1
  %4 = load i32, ptr %2, align 4, !tbaa !5
  %5 = icmp slt i32 %4, 3
  br i1 %5, label %7, label %6

6:                                                ; preds = %3
  call void @llvm.lifetime.end.p0(i64 4, ptr %2) #4
  br label %18

7:                                                ; preds = %3
  %8 = call noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000) @rng)
  %9 = urem i64 %8, 2000000014
  %10 = sub i64 %9, 1000000007
  %11 = uitofp i64 %10 to x86_fp80
  %12 = load i32, ptr %2, align 4, !tbaa !5
  %13 = sext i32 %12 to i64
  %14 = call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef %13) #4
  store x86_fp80 %11, ptr %14, align 16, !tbaa !9
  br label %15

15:                                               ; preds = %7
  %16 = load i32, ptr %2, align 4, !tbaa !5
  %17 = add nsw i32 %16, 1
  store i32 %17, ptr %2, align 4, !tbaa !5
  br label %3, !llvm.loop !11

18:                                               ; preds = %6
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000)) #2 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long double", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::mersenne_twister_engine" = type { [624 x i64], i64 }
%"struct.std::array" = type { [4 x x86_fp80] }

@rng = external dso_local global %"class.std::mersenne_twister_engine", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5vrandv(ptr dead_on_unwind noalias writable sret(%"struct.std::array") align 16 %0) local_unnamed_addr #1 {
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(64) %0, i8 0, i64 64, i1 false)
  %2 = tail call noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000) @rng)
  %3 = urem i64 %2, 2000000014
  %4 = add nsw i64 %3, -1000000007
  %5 = uitofp i64 %4 to x86_fp80
  %6 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 0) #3
  store x86_fp80 %5, ptr %6, align 16, !tbaa !5
  %7 = tail call noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000) @rng)
  %8 = urem i64 %7, 2000000014
  %9 = add nsw i64 %8, -1000000007
  %10 = uitofp i64 %9 to x86_fp80
  %11 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 1) #3
  store x86_fp80 %10, ptr %11, align 16, !tbaa !5
  %12 = tail call noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000) @rng)
  %13 = urem i64 %12, 2000000014
  %14 = add nsw i64 %13, -1000000007
  %15 = uitofp i64 %14 to x86_fp80
  %16 = tail call noundef nonnull align 16 dereferenceable(16) ptr @_ZNSt5arrayIeLm4EEixEm(ptr noundef nonnull align 16 dereferenceable(64) %0, i64 noundef 2) #3
  store x86_fp80 %15, ptr %16, align 16, !tbaa !5
  ret void
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv(ptr noundef nonnull align 8 dereferenceable(5000)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long double", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass