; LLVM IR from facebook/redex :: service/regalloc (Interference)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZNK13IRInstruction6opcodeEv(ptr noundef nonnull align 8 dereferenceable(32)) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN8regalloc12interference13src_bit_widthEPK13IRInstructioni(ptr noundef, i32 noundef) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i16 @_ZN8regalloc12interference17max_value_for_srcEPK13IRInstructionmb(ptr noundef %0, i64 noundef %1, i1 noundef zeroext %2) #3 {
  %4 = alloca i16, align 2
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i8, align 1
  %8 = alloca i16, align 2
  %9 = alloca i16, align 2
  %10 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  %11 = zext i1 %2 to i8
  store i8 %11, ptr %7, align 1, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 2, ptr %8) #5
  %12 = load ptr, ptr %5, align 8, !tbaa !5
  %13 = load i64, ptr %6, align 8, !tbaa !9
  %14 = trunc i64 %13 to i32
  %15 = call noundef i64 @_ZN8regalloc12interference13src_bit_widthEPK13IRInstructioni(ptr noundef %12, i32 noundef %14)
  %16 = trunc i64 %15 to i8
  %17 = call noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext %16)
  store i16 %17, ptr %8, align 2, !tbaa !13
  call void @llvm.lifetime.start.p0(i64 2, ptr %9) #5
  %18 = load ptr, ptr %5, align 8, !tbaa !5
  %19 = call noundef zeroext i16 @_ZNK13IRInstruction6opcodeEv(ptr noundef nonnull align 8 dereferenceable(32) %18)
  store i16 %19, ptr %9, align 2, !tbaa !15
  %20 = load i16, ptr %9, align 2, !tbaa !15
  %21 = call noundef zeroext i1 @_ZN6opcode14has_range_formE8IROpcode(i16 noundef zeroext %20)
  br i1 %21, label %22, label %28

22:                                               ; preds = %3
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = call noundef i64 @_ZNK13IRInstruction9srcs_sizeEv(ptr noundef nonnull align 8 dereferenceable(32) %23)
  %25 = icmp eq i64 %24, 1
  br i1 %25, label %26, label %28

26:                                               ; preds = %22
  %27 = call noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext 16)
  store i16 %27, ptr %4, align 2
  store i32 1, ptr %10, align 4
  br label %40

28:                                               ; preds = %22, %3
  %29 = load i16, ptr %9, align 2, !tbaa !15
  %30 = call noundef zeroext i1 @_ZN6opcode12is_an_invokeE8IROpcode(i16 noundef zeroext %29)
  br i1 %30, label %31, label %37

31:                                               ; preds = %28
  %32 = load i8, ptr %7, align 1, !tbaa !11, !range !17, !noundef !18
  %33 = trunc i8 %32 to i1
  br i1 %33, label %34, label %37

34:                                               ; preds = %31
  %35 = load i16, ptr %8, align 2, !tbaa !13
  %36 = add i16 %35, -1
  store i16 %36, ptr %8, align 2, !tbaa !13
  br label %37

37:                                               ; preds = %34, %31, %28
  br label %38

38:                                               ; preds = %37
  %39 = load i16, ptr %8, align 2, !tbaa !13
  store i16 %39, ptr %4, align 2
  store i32 1, ptr %10, align 4
  br label %40

40:                                               ; preds = %38, %26
  call void @llvm.lifetime.end.p0(i64 2, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 2, ptr %8) #5
  %41 = load i16, ptr %4, align 2
  ret i16 %41
}

declare noundef zeroext i1 @_ZN6opcode14has_range_formE8IROpcode(i16 noundef zeroext) #4

declare noundef i64 @_ZNK13IRInstruction9srcs_sizeEv(ptr noundef nonnull align 8 dereferenceable(32)) #4

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6opcode12is_an_invokeE8IROpcode(i16 noundef zeroext) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"short", !7, i64 0}
!15 = !{!16, !16, i64 0}
!16 = !{!"_ZTS8IROpcode", !7, i64 0}
!17 = !{i8 0, i8 2}
!18 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef zeroext i16 @_ZNK13IRInstruction6opcodeEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef i64 @_ZN8regalloc12interference13src_bit_widthEPK13IRInstructioni(ptr noundef, i32 noundef) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i16 @_ZN8regalloc12interference17max_value_for_srcEPK13IRInstructionmb(ptr noundef %0, i64 noundef %1, i1 noundef zeroext %2) local_unnamed_addr #2 {
  %4 = trunc i64 %1 to i32
  %5 = tail call noundef i64 @_ZN8regalloc12interference13src_bit_widthEPK13IRInstructioni(ptr noundef %0, i32 noundef %4)
  %6 = trunc i64 %5 to i8
  %7 = tail call noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext %6)
  %8 = tail call noundef zeroext i16 @_ZNK13IRInstruction6opcodeEv(ptr noundef nonnull align 8 dereferenceable(32) %0)
  %9 = tail call noundef zeroext i1 @_ZN6opcode14has_range_formE8IROpcode(i16 noundef zeroext %8)
  br i1 %9, label %10, label %15

10:                                               ; preds = %3
  %11 = tail call noundef i64 @_ZNK13IRInstruction9srcs_sizeEv(ptr noundef nonnull align 8 dereferenceable(32) %0)
  %12 = icmp eq i64 %11, 1
  br i1 %12, label %13, label %15

13:                                               ; preds = %10
  %14 = tail call noundef zeroext i16 @_ZN8regalloc18max_unsigned_valueEh(i8 noundef zeroext 16)
  br label %19

15:                                               ; preds = %10, %3
  %16 = tail call noundef zeroext i1 @_ZN6opcode12is_an_invokeE8IROpcode(i16 noundef zeroext %8)
  br i1 %16, label %17, label %19

17:                                               ; preds = %15
  %18 = sext i1 %2 to i16
  %spec.select = add i16 %7, %18
  br label %19

19:                                               ; preds = %17, %15, %13
  %.0 = phi i16 [ %14, %13 ], [ %7, %15 ], [ %spec.select, %17 ]
  ret i16 %.0
}

declare noundef zeroext i1 @_ZN6opcode14has_range_formE8IROpcode(i16 noundef zeroext) local_unnamed_addr #3

declare noundef i64 @_ZNK13IRInstruction9srcs_sizeEv(ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef zeroext i1 @_ZN6opcode12is_an_invokeE8IROpcode(i16 noundef zeroext) local_unnamed_addr #0

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass,TailCallElimPass