; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_driver)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

declare i32 @inv_imu_switch_on_mclk(ptr noundef) #1

declare i32 @inv_imu_switch_off_mclk(ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_reset_dmp(ptr noundef %0, i32 noundef %1) #2 {
  %3 = alloca i32, align 4
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  %11 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  store i32 5000, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  store i32 0, ptr %7, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 5000, ptr %8, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  store i8 0, ptr %10, align 1, !tbaa !11
  %12 = load ptr, ptr %4, align 8, !tbaa !5
  %13 = call i32 @inv_imu_switch_on_mclk(ptr noundef %12)
  %14 = load i32, ptr %7, align 4, !tbaa !9
  %15 = or i32 %14, %13
  store i32 %15, ptr %7, align 4, !tbaa !9
  %16 = load ptr, ptr %4, align 8, !tbaa !5
  %17 = call i32 @inv_imu_read_reg(ptr noundef %16, i32 noundef 65573, i32 noundef 1, ptr noundef %10)
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = or i32 %18, %17
  store i32 %19, ptr %7, align 4, !tbaa !9
  %20 = load i8, ptr %10, align 1, !tbaa !11
  %21 = zext i8 %20 to i32
  %22 = and i32 %21, -4
  %23 = trunc i32 %22 to i8
  store i8 %23, ptr %10, align 1, !tbaa !11
  %24 = load i32, ptr %5, align 4, !tbaa !9
  %25 = and i32 %24, 3
  %26 = load i8, ptr %10, align 1, !tbaa !11
  %27 = zext i8 %26 to i32
  %28 = or i32 %27, %25
  %29 = trunc i32 %28 to i8
  store i8 %29, ptr %10, align 1, !tbaa !11
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = call i32 @inv_imu_write_reg(ptr noundef %30, i32 noundef 65573, i32 noundef 1, ptr noundef %10)
  %32 = load i32, ptr %7, align 4, !tbaa !9
  %33 = or i32 %32, %31
  store i32 %33, ptr %7, align 4, !tbaa !9
  call void @inv_imu_sleep_us(i32 noundef 1000)
  br label %34

34:                                               ; preds = %52, %2
  call void @inv_imu_sleep_us(i32 noundef 10)
  %35 = load ptr, ptr %4, align 8, !tbaa !5
  %36 = call i32 @inv_imu_read_reg(ptr noundef %35, i32 noundef 65573, i32 noundef 1, ptr noundef %9)
  %37 = load i32, ptr %7, align 4, !tbaa !9
  %38 = or i32 %37, %36
  store i32 %38, ptr %7, align 4, !tbaa !9
  br label %39

39:                                               ; preds = %34
  %40 = load i8, ptr %9, align 1, !tbaa !11
  %41 = zext i8 %40 to i32
  %42 = and i32 %41, 3
  %43 = icmp ne i32 %42, 0
  br i1 %43, label %44, label %52

44:                                               ; preds = %39
  %45 = load i32, ptr %8, align 4, !tbaa !9
  %46 = add nsw i32 %45, -1
  store i32 %46, ptr %8, align 4, !tbaa !9
  %47 = icmp ne i32 %45, 0
  br i1 %47, label %48, label %52

48:                                               ; preds = %44
  %49 = load i32, ptr %7, align 4, !tbaa !9
  %50 = icmp ne i32 %49, 0
  %51 = xor i1 %50, true
  br label %52

52:                                               ; preds = %48, %44, %39
  %53 = phi i1 [ false, %44 ], [ false, %39 ], [ %51, %48 ]
  br i1 %53, label %34, label %54, !llvm.loop !12

54:                                               ; preds = %52
  %55 = load ptr, ptr %4, align 8, !tbaa !5
  %56 = call i32 @inv_imu_switch_off_mclk(ptr noundef %55)
  %57 = load i32, ptr %7, align 4, !tbaa !9
  %58 = or i32 %57, %56
  store i32 %58, ptr %7, align 4, !tbaa !9
  %59 = load i32, ptr %8, align 4, !tbaa !9
  %60 = icmp sle i32 %59, 0
  br i1 %60, label %61, label %62

61:                                               ; preds = %54
  store i32 -4, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %64

62:                                               ; preds = %54
  %63 = load i32, ptr %7, align 4, !tbaa !9
  store i32 %63, ptr %3, align 4
  store i32 1, ptr %11, align 4
  br label %64

64:                                               ; preds = %62, %61
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  %65 = load i32, ptr %3, align 4
  ret i32 %65
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_switch_on_mclk(ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_switch_off_mclk(ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_reset_dmp(ptr noundef %0, i32 noundef %1) local_unnamed_addr #2 {
.peel.begin:
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  store i8 0, ptr %3, align 1, !tbaa !5
  %4 = tail call i32 @inv_imu_switch_on_mclk(ptr noundef %0) #3
  %5 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65573, i32 noundef 1, ptr noundef nonnull %3) #3
  %6 = or i32 %5, %4
  %7 = load i8, ptr %3, align 1, !tbaa !5
  %8 = and i8 %7, -4
  %9 = trunc i32 %1 to i8
  %10 = and i8 %9, 3
  %11 = or disjoint i8 %8, %10
  store i8 %11, ptr %3, align 1, !tbaa !5
  %12 = call i32 @inv_imu_write_reg(ptr noundef %0, i32 noundef 65573, i32 noundef 1, ptr noundef nonnull %3) #3
  %13 = or i32 %6, %12
  call void @inv_imu_sleep_us(i32 noundef 1000) #3
  call void @inv_imu_sleep_us(i32 noundef 10) #3
  %14 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65573, i32 noundef 1, ptr noundef nonnull %2) #3
  %15 = or i32 %14, %13
  %16 = load i8, ptr %2, align 1, !tbaa !5
  %17 = and i8 %16, 3
  %.not.peel = icmp ne i8 %17, 0
  %.not18.peel = icmp eq i32 %15, 0
  %or.cond23 = select i1 %.not.peel, i1 %.not18.peel, i1 false
  br i1 %or.cond23, label %.peel.next, label %.critedge.thread

.peel.next:                                       ; preds = %.peel.begin, %21
  %.0 = phi i32 [ %22, %21 ], [ 4999, %.peel.begin ]
  call void @inv_imu_sleep_us(i32 noundef 10) #3
  %18 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65573, i32 noundef 1, ptr noundef nonnull %2) #3
  %19 = load i8, ptr %2, align 1, !tbaa !5
  %20 = and i8 %19, 3
  %.not = icmp eq i8 %20, 0
  br i1 %.not, label %.critedge, label %21

21:                                               ; preds = %.peel.next
  %22 = add nsw i32 %.0, -1
  %.not17 = icmp ne i32 %.0, 0
  %.not18 = icmp eq i32 %18, 0
  %or.cond = select i1 %.not17, i1 %.not18, i1 false
  br i1 %or.cond, label %.peel.next, label %.critedge, !llvm.loop !8

.critedge.thread:                                 ; preds = %.peel.begin
  %23 = call i32 @inv_imu_switch_off_mclk(ptr noundef %0) #3
  %24 = or i32 %23, %15
  br label %28

.critedge:                                        ; preds = %21, %.peel.next
  %.1.ph = phi i32 [ %.0, %.peel.next ], [ %22, %21 ]
  %.1.ph.fr = freeze i32 %.1.ph
  %25 = icmp slt i32 %.1.ph.fr, 1
  %26 = call i32 @inv_imu_switch_off_mclk(ptr noundef %0) #3
  %27 = or i32 %26, %18
  %spec.select = select i1 %25, i32 -4, i32 %27
  br label %28

28:                                               ; preds = %.critedge, %.critedge.thread
  %29 = phi i32 [ %24, %.critedge.thread ], [ %spec.select, %.critedge ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  ret i32 %29
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9, !10}
!9 = !{!"llvm.loop.mustprogress"}
!10 = !{!"llvm.loop.peeled.count", i32 1}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopFullUnrollPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass