; LLVM IR from div-bargali/Data-Structures-and-Algorithms :: C++/Data-Structures/Array/move_all_zeroes.ll (Z14pushZerosToEndPii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z14pushZerosToEndPii(ptr noundef %0, i32 noundef %1) #0 {
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #2
  store i32 0, ptr %5, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !9
  br label %7

7:                                                ; preds = %31, %2
  %8 = load i32, ptr %6, align 4, !tbaa !9
  %9 = load i32, ptr %4, align 4, !tbaa !9
  %10 = icmp slt i32 %8, %9
  br i1 %10, label %12, label %11

11:                                               ; preds = %7
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  br label %34

12:                                               ; preds = %7
  %13 = load ptr, ptr %3, align 8, !tbaa !5
  %14 = load i32, ptr %6, align 4, !tbaa !9
  %15 = sext i32 %14 to i64
  %16 = getelementptr inbounds i32, ptr %13, i64 %15
  %17 = load i32, ptr %16, align 4, !tbaa !9
  %18 = icmp ne i32 %17, 0
  br i1 %18, label %19, label %30

19:                                               ; preds = %12
  %20 = load ptr, ptr %3, align 8, !tbaa !5
  %21 = load i32, ptr %6, align 4, !tbaa !9
  %22 = sext i32 %21 to i64
  %23 = getelementptr inbounds i32, ptr %20, i64 %22
  %24 = load i32, ptr %23, align 4, !tbaa !9
  %25 = load ptr, ptr %3, align 8, !tbaa !5
  %26 = load i32, ptr %5, align 4, !tbaa !9
  %27 = add nsw i32 %26, 1
  store i32 %27, ptr %5, align 4, !tbaa !9
  %28 = sext i32 %26 to i64
  %29 = getelementptr inbounds i32, ptr %25, i64 %28
  store i32 %24, ptr %29, align 4, !tbaa !9
  br label %30

30:                                               ; preds = %19, %12
  br label %31

31:                                               ; preds = %30
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = add nsw i32 %32, 1
  store i32 %33, ptr %6, align 4, !tbaa !9
  br label %7, !llvm.loop !11

34:                                               ; preds = %11
  br label %35

35:                                               ; preds = %39, %34
  %36 = load i32, ptr %5, align 4, !tbaa !9
  %37 = load i32, ptr %4, align 4, !tbaa !9
  %38 = icmp slt i32 %36, %37
  br i1 %38, label %39, label %45

39:                                               ; preds = %35
  %40 = load ptr, ptr %3, align 8, !tbaa !5
  %41 = load i32, ptr %5, align 4, !tbaa !9
  %42 = add nsw i32 %41, 1
  store i32 %42, ptr %5, align 4, !tbaa !9
  %43 = sext i32 %41 to i64
  %44 = getelementptr inbounds i32, ptr %40, i64 %43
  store i32 0, ptr %44, align 4, !tbaa !9
  br label %35, !llvm.loop !13

45:                                               ; preds = %35
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #2
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable
define dso_local void @_Z14pushZerosToEndPii(ptr nocapture noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = icmp sgt i32 %1, 0
  br i1 %3, label %.lr.ph.preheader, label %.preheader

.lr.ph.preheader:                                 ; preds = %2
  %wide.trip.count = zext nneg i32 %1 to i64
  %xtraiter = and i64 %wide.trip.count, 1
  %4 = icmp eq i32 %1, 1
  br i1 %4, label %.preheader.loopexit.unr-lcssa, label %.lr.ph.preheader.new

.lr.ph.preheader.new:                             ; preds = %.lr.ph.preheader
  %unroll_iter = and i64 %wide.trip.count, 2147483646
  br label %.lr.ph

.preheader.loopexit.unr-lcssa:                    ; preds = %31, %.lr.ph.preheader
  %.1.lcssa.ph = phi i32 [ poison, %.lr.ph.preheader ], [ %.1.1, %31 ]
  %indvars.iv.unr = phi i64 [ 0, %.lr.ph.preheader ], [ %indvars.iv.next.1, %31 ]
  %.01215.unr = phi i32 [ 0, %.lr.ph.preheader ], [ %.1.1, %31 ]
  %lcmp.mod.not = icmp eq i64 %xtraiter, 0
  br i1 %lcmp.mod.not, label %.preheader, label %.lr.ph.epil

.lr.ph.epil:                                      ; preds = %.preheader.loopexit.unr-lcssa
  %5 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.unr
  %6 = load i32, ptr %5, align 4, !tbaa !5
  %.not.epil = icmp eq i32 %6, 0
  br i1 %.not.epil, label %.preheader, label %7

7:                                                ; preds = %.lr.ph.epil
  %8 = add nsw i32 %.01215.unr, 1
  %9 = sext i32 %.01215.unr to i64
  %10 = getelementptr inbounds i32, ptr %0, i64 %9
  store i32 %6, ptr %10, align 4, !tbaa !5
  br label %.preheader

.preheader:                                       ; preds = %.preheader.loopexit.unr-lcssa, %7, %.lr.ph.epil, %2
  %.012.lcssa = phi i32 [ 0, %2 ], [ %.1.lcssa.ph, %.preheader.loopexit.unr-lcssa ], [ %8, %7 ], [ %.01215.unr, %.lr.ph.epil ]
  %11 = icmp slt i32 %.012.lcssa, %1
  br i1 %11, label %.lr.ph18.preheader, label %._crit_edge

.lr.ph18.preheader:                               ; preds = %.preheader
  %12 = sext i32 %.012.lcssa to i64
  %13 = shl nsw i64 %12, 2
  %scevgep = getelementptr i8, ptr %0, i64 %13
  %14 = xor i32 %.012.lcssa, -1
  %15 = add i32 %14, %1
  %16 = zext i32 %15 to i64
  %17 = shl nuw nsw i64 %16, 2
  %18 = add nuw nsw i64 %17, 4
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(1) %scevgep, i8 0, i64 %18, i1 false), !tbaa !5
  br label %._crit_edge

.lr.ph:                                           ; preds = %31, %.lr.ph.preheader.new
  %indvars.iv = phi i64 [ 0, %.lr.ph.preheader.new ], [ %indvars.iv.next.1, %31 ]
  %.01215 = phi i32 [ 0, %.lr.ph.preheader.new ], [ %.1.1, %31 ]
  %niter = phi i64 [ 0, %.lr.ph.preheader.new ], [ %niter.next.1, %31 ]
  %19 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv
  %20 = load i32, ptr %19, align 4, !tbaa !5
  %.not = icmp eq i32 %20, 0
  br i1 %.not, label %.lr.ph.1, label %21

21:                                               ; preds = %.lr.ph
  %22 = add nsw i32 %.01215, 1
  %23 = sext i32 %.01215 to i64
  %24 = getelementptr inbounds i32, ptr %0, i64 %23
  store i32 %20, ptr %24, align 4, !tbaa !5
  br label %.lr.ph.1

.lr.ph.1:                                         ; preds = %.lr.ph, %21
  %.1 = phi i32 [ %22, %21 ], [ %.01215, %.lr.ph ]
  %indvars.iv.next = or disjoint i64 %indvars.iv, 1
  %25 = getelementptr inbounds i32, ptr %0, i64 %indvars.iv.next
  %26 = load i32, ptr %25, align 4, !tbaa !5
  %.not.1 = icmp eq i32 %26, 0
  br i1 %.not.1, label %31, label %27

27:                                               ; preds = %.lr.ph.1
  %28 = add nsw i32 %.1, 1
  %29 = sext i32 %.1 to i64
  %30 = getelementptr inbounds i32, ptr %0, i64 %29
  store i32 %26, ptr %30, align 4, !tbaa !5
  br label %31

31:                                               ; preds = %27, %.lr.ph.1
  %.1.1 = phi i32 [ %28, %27 ], [ %.1, %.lr.ph.1 ]
  %indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
  %niter.next.1 = add i64 %niter, 2
  %niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
  br i1 %niter.ncmp.1, label %.preheader.loopexit.unr-lcssa, label %.lr.ph, !llvm.loop !9

._crit_edge:                                      ; preds = %.lr.ph18.preheader, %.preheader
  ret void
}

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #1

attributes #0 = { mustprogress nofree norecurse nosync nounwind memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: write) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopIdiomRecognizePass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass