; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_transport)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare hidden i32 @read_sreg(ptr noundef, i8 noundef zeroext, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare hidden i32 @read_mclk_reg(ptr noundef, i16 noundef zeroext, i8 noundef zeroext, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) #1 {
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca ptr, align 8
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca ptr, align 8
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store ptr %3, ptr %9, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #2
  store i32 0, ptr %10, align 4, !tbaa !9
  %14 = load ptr, ptr %6, align 8, !tbaa !5
  %15 = icmp eq ptr %14, null
  br i1 %15, label %16, label %17

16:                                               ; preds = %4
  store i32 -11, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %83

17:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #2
  store i32 0, ptr %12, align 4, !tbaa !9
  br label %18

18:                                               ; preds = %77, %17
  %19 = load i32, ptr %12, align 4, !tbaa !9
  %20 = load i32, ptr %8, align 4, !tbaa !9
  %21 = icmp ult i32 %19, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %18
  store i32 2, ptr %11, align 4
  br label %80

23:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #2
  %24 = load ptr, ptr %6, align 8, !tbaa !5
  %25 = load i32, ptr %7, align 4, !tbaa !9
  %26 = load i32, ptr %12, align 4, !tbaa !9
  %27 = add i32 %25, %26
  %28 = call ptr @get_register_cache_addr(ptr noundef %24, i32 noundef %27)
  store ptr %28, ptr %13, align 8, !tbaa !5
  %29 = load ptr, ptr %13, align 8, !tbaa !5
  %30 = icmp ne ptr %29, null
  br i1 %30, label %31, label %38

31:                                               ; preds = %23
  %32 = load ptr, ptr %13, align 8, !tbaa !5
  %33 = load i8, ptr %32, align 1, !tbaa !11
  %34 = load ptr, ptr %9, align 8, !tbaa !5
  %35 = load i32, ptr %12, align 4, !tbaa !9
  %36 = zext i32 %35 to i64
  %37 = getelementptr inbounds i8, ptr %34, i64 %36
  store i8 %33, ptr %37, align 1, !tbaa !11
  br label %73

38:                                               ; preds = %23
  %39 = load i32, ptr %7, align 4, !tbaa !9
  %40 = and i32 %39, 65536
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %56, label %42

42:                                               ; preds = %38
  %43 = load ptr, ptr %6, align 8, !tbaa !5
  %44 = load i32, ptr %7, align 4, !tbaa !9
  %45 = load i32, ptr %12, align 4, !tbaa !9
  %46 = add i32 %44, %45
  %47 = and i32 %46, 65535
  %48 = trunc i32 %47 to i16
  %49 = load ptr, ptr %9, align 8, !tbaa !5
  %50 = load i32, ptr %12, align 4, !tbaa !9
  %51 = zext i32 %50 to i64
  %52 = getelementptr inbounds i8, ptr %49, i64 %51
  %53 = call i32 @read_mclk_reg(ptr noundef %43, i16 noundef zeroext %48, i8 noundef zeroext 1, ptr noundef %52)
  %54 = load i32, ptr %10, align 4, !tbaa !9
  %55 = or i32 %54, %53
  store i32 %55, ptr %10, align 4, !tbaa !9
  br label %72

56:                                               ; preds = %38
  %57 = load ptr, ptr %6, align 8, !tbaa !5
  %58 = load i32, ptr %7, align 4, !tbaa !9
  %59 = load i32, ptr %12, align 4, !tbaa !9
  %60 = add i32 %58, %59
  %61 = trunc i32 %60 to i8
  %62 = load i32, ptr %8, align 4, !tbaa !9
  %63 = load i32, ptr %12, align 4, !tbaa !9
  %64 = sub i32 %62, %63
  %65 = load ptr, ptr %9, align 8, !tbaa !5
  %66 = load i32, ptr %12, align 4, !tbaa !9
  %67 = zext i32 %66 to i64
  %68 = getelementptr inbounds i8, ptr %65, i64 %67
  %69 = call i32 @read_sreg(ptr noundef %57, i8 noundef zeroext %61, i32 noundef %64, ptr noundef %68)
  %70 = load i32, ptr %10, align 4, !tbaa !9
  %71 = or i32 %70, %69
  store i32 %71, ptr %10, align 4, !tbaa !9
  store i32 2, ptr %11, align 4
  br label %74

72:                                               ; preds = %42
  br label %73

73:                                               ; preds = %72, %31
  store i32 0, ptr %11, align 4
  br label %74

74:                                               ; preds = %73, %56
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #2
  %75 = load i32, ptr %11, align 4
  switch i32 %75, label %80 [
    i32 0, label %76
  ]

76:                                               ; preds = %74
  br label %77

77:                                               ; preds = %76
  %78 = load i32, ptr %12, align 4, !tbaa !9
  %79 = add i32 %78, 1
  store i32 %79, ptr %12, align 4, !tbaa !9
  br label %18, !llvm.loop !12

80:                                               ; preds = %74, %22
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #2
  br label %81

81:                                               ; preds = %80
  %82 = load i32, ptr %10, align 4, !tbaa !9
  store i32 %82, ptr %5, align 4
  store i32 1, ptr %11, align 4
  br label %83

83:                                               ; preds = %81, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #2
  %84 = load i32, ptr %5, align 4
  ret i32 %84
}

; Function Attrs: nounwind uwtable
declare hidden ptr @get_register_cache_addr(ptr noundef, i32 noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: nounwind uwtable
declare hidden i32 @read_sreg(ptr noundef, i8 noundef zeroext, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
declare hidden i32 @read_mclk_reg(ptr noundef, i16 noundef zeroext, i8 noundef zeroext, ptr noundef) local_unnamed_addr #0

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef %1, i32 noundef %2, ptr noundef %3) local_unnamed_addr #0 {
  %5 = icmp eq ptr %0, null
  br i1 %5, label %.loopexit, label %.preheader

.preheader:                                       ; preds = %4
  %.not46 = icmp eq i32 %2, 0
  br i1 %.not46, label %.loopexit, label %.lr.ph

.lr.ph:                                           ; preds = %.preheader
  %6 = and i32 %1, 65536
  %.not34 = icmp eq i32 %6, 0
  %wide.trip.count54 = zext i32 %2 to i64
  br i1 %.not34, label %.lr.ph.split.us, label %.lr.ph.split

.lr.ph.split.us:                                  ; preds = %.lr.ph, %17
  %indvars.iv51 = phi i64 [ %indvars.iv.next52, %17 ], [ 0, %.lr.ph ]
  %.03040.us = phi i32 [ %.2.ph.us, %17 ], [ 0, %.lr.ph ]
  %7 = trunc nuw i64 %indvars.iv51 to i32
  %8 = add i32 %7, %1
  %9 = tail call ptr @get_register_cache_addr(ptr noundef nonnull %0, i32 noundef %8)
  %.not.us = icmp eq ptr %9, null
  %10 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv51
  br i1 %.not.us, label %13, label %11

11:                                               ; preds = %.lr.ph.split.us
  %12 = load i8, ptr %9, align 1, !tbaa !5
  store i8 %12, ptr %10, align 1, !tbaa !5
  br label %17

13:                                               ; preds = %.lr.ph.split.us
  %14 = trunc i32 %8 to i16
  %15 = tail call i32 @read_mclk_reg(ptr noundef nonnull %0, i16 noundef zeroext %14, i8 noundef zeroext 1, ptr noundef %10)
  %16 = or i32 %15, %.03040.us
  br label %17

17:                                               ; preds = %13, %11
  %.2.ph.us = phi i32 [ %16, %13 ], [ %.03040.us, %11 ]
  %indvars.iv.next52 = add nuw nsw i64 %indvars.iv51, 1
  %exitcond55.not = icmp eq i64 %indvars.iv.next52, %wide.trip.count54
  br i1 %exitcond55.not, label %.loopexit, label %.lr.ph.split.us, !llvm.loop !8

.lr.ph.split:                                     ; preds = %.lr.ph, %21
  %indvars.iv = phi i64 [ %indvars.iv.next, %21 ], [ 0, %.lr.ph ]
  %18 = trunc nuw i64 %indvars.iv to i32
  %19 = add i32 %18, %1
  %20 = tail call ptr @get_register_cache_addr(ptr noundef nonnull %0, i32 noundef %19)
  %.not = icmp eq ptr %20, null
  br i1 %.not, label %24, label %21

21:                                               ; preds = %.lr.ph.split
  %22 = load i8, ptr %20, align 1, !tbaa !5
  %23 = getelementptr inbounds i8, ptr %3, i64 %indvars.iv
  store i8 %22, ptr %23, align 1, !tbaa !5
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count54
  br i1 %exitcond.not, label %.loopexit, label %.lr.ph.split, !llvm.loop !8

24:                                               ; preds = %.lr.ph.split
  %25 = trunc i32 %19 to i8
  %26 = sub i32 %2, %18
  %27 = and i64 %indvars.iv, 4294967295
  %28 = getelementptr inbounds i8, ptr %3, i64 %27
  %29 = tail call i32 @read_sreg(ptr noundef nonnull %0, i8 noundef zeroext %25, i32 noundef %26, ptr noundef %28)
  br label %.loopexit

.loopexit:                                        ; preds = %21, %17, %.preheader, %24, %4
  %.0 = phi i32 [ -11, %4 ], [ %29, %24 ], [ 0, %.preheader ], [ %.2.ph.us, %17 ], [ 0, %21 ]
  ret i32 %.0
}

; Function Attrs: nounwind uwtable
declare hidden ptr @get_register_cache_addr(ptr noundef, i32 noundef) local_unnamed_addr #0

attributes #0 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = distinct !{!8, !9}
!9 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass