; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_transport)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_transport = type { %struct.inv_imu_serif, %struct.register_cache, i8 }
%struct.inv_imu_serif = type { ptr, ptr, ptr, i32, i32, i32 }
%struct.register_cache = type { i8, i8, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_switch_off_mclk(ptr noundef %0) #1 {
  %2 = alloca i32, align 4
  %3 = alloca ptr, align 8
  %4 = alloca i32, align 4
  %5 = alloca i8, align 1
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #2
  %8 = load ptr, ptr %3, align 8, !tbaa !5
  store ptr %8, ptr %6, align 8, !tbaa !5
  %9 = load ptr, ptr %6, align 8, !tbaa !5
  %10 = icmp eq ptr %9, null
  br i1 %10, label %11, label %12

11:                                               ; preds = %1
  store i32 -11, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %52

12:                                               ; preds = %1
  %13 = load ptr, ptr %6, align 8, !tbaa !5
  %14 = getelementptr inbounds %struct.inv_imu_transport, ptr %13, i32 0, i32 2
  %15 = load i8, ptr %14, align 4, !tbaa !11
  %16 = zext i8 %15 to i32
  %17 = icmp eq i32 %16, 1
  br i1 %17, label %18, label %31

18:                                               ; preds = %12
  %19 = load ptr, ptr %3, align 8, !tbaa !5
  %20 = call i32 @inv_imu_read_reg(ptr noundef %19, i32 noundef 65567, i32 noundef 1, ptr noundef %5)
  %21 = load i32, ptr %4, align 4, !tbaa !9
  %22 = or i32 %21, %20
  store i32 %22, ptr %4, align 4, !tbaa !9
  %23 = load i8, ptr %5, align 1, !tbaa !15
  %24 = zext i8 %23 to i32
  %25 = and i32 %24, -17
  %26 = trunc i32 %25 to i8
  store i8 %26, ptr %5, align 1, !tbaa !15
  %27 = load ptr, ptr %3, align 8, !tbaa !5
  %28 = call i32 @inv_imu_write_reg(ptr noundef %27, i32 noundef 65567, i32 noundef 1, ptr noundef %5)
  %29 = load i32, ptr %4, align 4, !tbaa !9
  %30 = or i32 %29, %28
  store i32 %30, ptr %4, align 4, !tbaa !9
  br label %46

31:                                               ; preds = %12
  %32 = load ptr, ptr %3, align 8, !tbaa !5
  %33 = call i32 @inv_imu_read_reg(ptr noundef %32, i32 noundef 65567, i32 noundef 1, ptr noundef %5)
  %34 = load i32, ptr %4, align 4, !tbaa !9
  %35 = or i32 %34, %33
  store i32 %35, ptr %4, align 4, !tbaa !9
  %36 = load i8, ptr %5, align 1, !tbaa !15
  %37 = zext i8 %36 to i32
  %38 = and i32 %37, 16
  %39 = trunc i32 %38 to i8
  store i8 %39, ptr %5, align 1, !tbaa !15
  %40 = zext i8 %39 to i32
  %41 = icmp eq i32 0, %40
  br i1 %41, label %42, label %45

42:                                               ; preds = %31
  %43 = load i32, ptr %4, align 4, !tbaa !9
  %44 = or i32 %43, -1
  store i32 %44, ptr %4, align 4, !tbaa !9
  br label %45

45:                                               ; preds = %42, %31
  br label %46

46:                                               ; preds = %45, %18
  %47 = load ptr, ptr %6, align 8, !tbaa !5
  %48 = getelementptr inbounds %struct.inv_imu_transport, ptr %47, i32 0, i32 2
  %49 = load i8, ptr %48, align 4, !tbaa !11
  %50 = add i8 %49, -1
  store i8 %50, ptr %48, align 4, !tbaa !11
  %51 = load i32, ptr %4, align 4, !tbaa !9
  store i32 %51, ptr %2, align 4
  store i32 1, ptr %7, align 4
  br label %52

52:                                               ; preds = %46, %11
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #2
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #2
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  %53 = load i32, ptr %2, align 4
  ret i32 %53
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !7, i64 44}
!12 = !{!"inv_imu_transport", !13, i64 0, !14, i64 40, !7, i64 44}
!13 = !{!"inv_imu_serif", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !10, i64 32}
!14 = !{!"register_cache", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!15 = !{!7, !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_switch_off_mclk(ptr noundef %0) local_unnamed_addr #1 {
  %2 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #2
  %3 = icmp eq ptr %0, null
  br i1 %3, label %20, label %4

4:                                                ; preds = %1
  %5 = getelementptr inbounds i8, ptr %0, i64 44
  %6 = load i8, ptr %5, align 4, !tbaa !5
  %7 = icmp eq i8 %6, 1
  %8 = call i32 @inv_imu_read_reg(ptr noundef nonnull %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2)
  %9 = load i8, ptr %2, align 1, !tbaa !13
  br i1 %7, label %10, label %14

10:                                               ; preds = %4
  %11 = and i8 %9, -17
  store i8 %11, ptr %2, align 1, !tbaa !13
  %12 = call i32 @inv_imu_write_reg(ptr noundef nonnull %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2)
  %13 = or i32 %12, %8
  br label %17

14:                                               ; preds = %4
  %15 = and i8 %9, 16
  %16 = icmp eq i8 %15, 0
  %spec.select = select i1 %16, i32 -1, i32 %8
  br label %17

17:                                               ; preds = %14, %10
  %.012 = phi i32 [ %13, %10 ], [ %spec.select, %14 ]
  %18 = load i8, ptr %5, align 4, !tbaa !5
  %19 = add i8 %18, -1
  store i8 %19, ptr %5, align 4, !tbaa !5
  br label %20

20:                                               ; preds = %1, %17
  %.0 = phi i32 [ %.012, %17 ], [ -11, %1 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #2
  ret i32 %.0
}

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !9, i64 44}
!6 = !{!"inv_imu_transport", !7, i64 0, !12, i64 40, !9, i64 44}
!7 = !{!"inv_imu_serif", !8, i64 0, !8, i64 8, !8, i64 16, !11, i64 24, !11, i64 28, !11, i64 32}
!8 = !{!"any pointer", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"register_cache", !9, i64 0, !9, i64 1, !9, i64 2, !9, i64 3}
!13 = !{!9, !9, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass