; LLVM IR from div-bargali/Data-Structures-and-Algorithms :: C++/Data-Structures/Tree/Segment_Tree_with_Lazy_Propagation.ll (Z6updatexxxxxx)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@tree = external dso_local global %"class.std::vector", align 8
@lazy = external dso_local global %"class.std::vector", align 8

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4pushx(i64 noundef) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) #2 {
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca i64, align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  store i64 %0, ptr %7, align 8, !tbaa !5
  store i64 %1, ptr %8, align 8, !tbaa !5
  store i64 %2, ptr %9, align 8, !tbaa !5
  store i64 %3, ptr %10, align 8, !tbaa !5
  store i64 %4, ptr %11, align 8, !tbaa !5
  store i64 %5, ptr %12, align 8, !tbaa !5
  %14 = load i64, ptr %11, align 8, !tbaa !5
  %15 = load i64, ptr %8, align 8, !tbaa !5
  %16 = icmp slt i64 %14, %15
  br i1 %16, label %21, label %17

17:                                               ; preds = %6
  %18 = load i64, ptr %9, align 8, !tbaa !5
  %19 = load i64, ptr %10, align 8, !tbaa !5
  %20 = icmp slt i64 %18, %19
  br i1 %20, label %21, label %22

21:                                               ; preds = %17, %6
  br label %74

22:                                               ; preds = %17
  %23 = load i64, ptr %7, align 8, !tbaa !5
  call void @_Z4pushx(i64 noundef %23)
  %24 = load i64, ptr %10, align 8, !tbaa !5
  %25 = load i64, ptr %8, align 8, !tbaa !5
  %26 = icmp sle i64 %24, %25
  br i1 %26, label %27, label %42

27:                                               ; preds = %22
  %28 = load i64, ptr %11, align 8, !tbaa !5
  %29 = load i64, ptr %9, align 8, !tbaa !5
  %30 = icmp sge i64 %28, %29
  br i1 %30, label %31, label %42

31:                                               ; preds = %27
  %32 = load i64, ptr %12, align 8, !tbaa !5
  %33 = load i64, ptr %7, align 8, !tbaa !5
  %34 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %33) #4
  %35 = load i64, ptr %34, align 8, !tbaa !5
  %36 = add nsw i64 %35, %32
  store i64 %36, ptr %34, align 8, !tbaa !5
  %37 = load i64, ptr %12, align 8, !tbaa !5
  %38 = load i64, ptr %7, align 8, !tbaa !5
  %39 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @lazy, i64 noundef %38) #4
  %40 = load i64, ptr %39, align 8, !tbaa !5
  %41 = add nsw i64 %40, %37
  store i64 %41, ptr %39, align 8, !tbaa !5
  br label %74

42:                                               ; preds = %27, %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %43 = load i64, ptr %8, align 8, !tbaa !5
  %44 = load i64, ptr %9, align 8, !tbaa !5
  %45 = add nsw i64 %43, %44
  %46 = sdiv i64 %45, 2
  store i64 %46, ptr %13, align 8, !tbaa !5
  %47 = load i64, ptr %7, align 8, !tbaa !5
  %48 = mul nsw i64 2, %47
  %49 = load i64, ptr %8, align 8, !tbaa !5
  %50 = load i64, ptr %13, align 8, !tbaa !5
  %51 = load i64, ptr %10, align 8, !tbaa !5
  %52 = load i64, ptr %11, align 8, !tbaa !5
  %53 = load i64, ptr %12, align 8, !tbaa !5
  call void @_Z6updatexxxxxx(i64 noundef %48, i64 noundef %49, i64 noundef %50, i64 noundef %51, i64 noundef %52, i64 noundef %53)
  %54 = load i64, ptr %7, align 8, !tbaa !5
  %55 = mul nsw i64 2, %54
  %56 = add nsw i64 %55, 1
  %57 = load i64, ptr %13, align 8, !tbaa !5
  %58 = add nsw i64 %57, 1
  %59 = load i64, ptr %9, align 8, !tbaa !5
  %60 = load i64, ptr %10, align 8, !tbaa !5
  %61 = load i64, ptr %11, align 8, !tbaa !5
  %62 = load i64, ptr %12, align 8, !tbaa !5
  call void @_Z6updatexxxxxx(i64 noundef %56, i64 noundef %58, i64 noundef %59, i64 noundef %60, i64 noundef %61, i64 noundef %62)
  %63 = load i64, ptr %7, align 8, !tbaa !5
  %64 = mul nsw i64 %63, 2
  %65 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %64) #4
  %66 = load i64, ptr %7, align 8, !tbaa !5
  %67 = mul nsw i64 %66, 2
  %68 = add nsw i64 %67, 1
  %69 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %68) #4
  %70 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %65, ptr noundef nonnull align 8 dereferenceable(8) %69)
  %71 = load i64, ptr %70, align 8, !tbaa !5
  %72 = load i64, ptr %7, align 8, !tbaa !5
  %73 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %72) #4
  store i64 %71, ptr %73, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  br label %74

74:                                               ; preds = %42, %31, %21
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl" = type { %"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<long long, std::allocator<long long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@tree = external dso_local global %"class.std::vector", align 8
@lazy = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_Z4pushx(i64 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z6updatexxxxxx(i64 noundef %0, i64 noundef %1, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5) local_unnamed_addr #0 {
  %7 = icmp slt i64 %4, %1
  %8 = icmp slt i64 %2, %3
  %or.cond = or i1 %8, %7
  br i1 %or.cond, label %common.ret35, label %9

9:                                                ; preds = %6
  tail call void @_Z4pushx(i64 noundef %0)
  %.not = icmp sgt i64 %3, %1
  %.not33 = icmp slt i64 %4, %2
  %or.cond34 = or i1 %.not, %.not33
  br i1 %or.cond34, label %17, label %10

10:                                               ; preds = %9
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %0) #2
  %12 = load i64, ptr %11, align 8, !tbaa !5
  %13 = add nsw i64 %12, %5
  store i64 %13, ptr %11, align 8, !tbaa !5
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @lazy, i64 noundef %0) #2
  %15 = load i64, ptr %14, align 8, !tbaa !5
  %16 = add nsw i64 %15, %5
  store i64 %16, ptr %14, align 8, !tbaa !5
  br label %common.ret35

common.ret35:                                     ; preds = %6, %10, %17
  ret void

17:                                               ; preds = %9
  %18 = add nsw i64 %2, %1
  %19 = sdiv i64 %18, 2
  %20 = shl nsw i64 %0, 1
  tail call void @_Z6updatexxxxxx(i64 noundef %20, i64 noundef %1, i64 noundef %19, i64 noundef %3, i64 noundef %4, i64 noundef %5)
  %21 = or disjoint i64 %20, 1
  %22 = add nsw i64 %19, 1
  tail call void @_Z6updatexxxxxx(i64 noundef %21, i64 noundef %22, i64 noundef %2, i64 noundef %3, i64 noundef %4, i64 noundef %5)
  %23 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %20) #2
  %24 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %21) #2
  %25 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %23, ptr noundef nonnull align 8 dereferenceable(8) %24)
  %26 = load i64, ptr %25, align 8, !tbaa !5
  %27 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIxSaIxEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @tree, i64 noundef %0) #2
  store i64 %26, ptr %27, align 8, !tbaa !5
  br label %common.ret35
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3maxIxERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass