; LLVM IR from tfhe/spqlios-arithmetic :: test/testlib/ntt120_dft.ll (Z14q120_ntt_naiveRKSt6vectorI8mod_q120SaIS0_EE)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare hidden void @_ZL18q120_ntt_naive_recmdP8mod_q120(i64 noundef, double noundef, ptr noundef) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorI8mod_q120SaIS0_EE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z14q120_ntt_naiveRKSt6vectorI8mod_q120SaIS0_EE(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1) #0 personality ptr @__gxx_personality_v0 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i1, align 1
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %3, align 8
  store ptr %1, ptr %4, align 8, !tbaa !5
  store i1 false, ptr %5, align 1
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  call void @_ZNSt6vectorI8mod_q120SaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %8)
  %9 = call noundef i64 @_ZNKSt6vectorI8mod_q120SaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %10 = call noundef ptr @_ZNSt6vectorI8mod_q120SaIS0_EE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  invoke void @_ZL18q120_ntt_naive_recmdP8mod_q120(i64 noundef %9, double noundef 5.000000e-01, ptr noundef %10)
          to label %11 unwind label %13

11:                                               ; preds = %2
  store i1 true, ptr %5, align 1
  %12 = load i1, ptr %5, align 1
  br i1 %12, label %18, label %17

13:                                               ; preds = %2
  %14 = landingpad { ptr, i32 }
          cleanup
  %15 = extractvalue { ptr, i32 } %14, 0
  store ptr %15, ptr %6, align 8
  %16 = extractvalue { ptr, i32 } %14, 1
  store i32 %16, ptr %7, align 4
  call void @_ZNSt6vectorI8mod_q120SaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  br label %19

17:                                               ; preds = %11
  call void @_ZNSt6vectorI8mod_q120SaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  br label %18

18:                                               ; preds = %17, %11
  ret void

19:                                               ; preds = %13
  %20 = load ptr, ptr %6, align 8
  %21 = load i32, ptr %7, align 4
  %22 = insertvalue { ptr, i32 } poison, ptr %20, 0
  %23 = insertvalue { ptr, i32 } %22, i32 %21, 1
  resume { ptr, i32 } %23
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI8mod_q120SaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI8mod_q120SaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI8mod_q120SaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl" = type { %"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" }
%"struct.std::_Vector_base<mod_q120, std::allocator<mod_q120>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress uwtable
declare hidden void @_ZL18q120_ntt_naive_recmdP8mod_q120(i64 noundef, double noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNSt6vectorI8mod_q120SaIS0_EE4dataEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_Z14q120_ntt_naiveRKSt6vectorI8mod_q120SaIS0_EE(ptr dead_on_unwind noalias nonnull writable sret(%"class.std::vector") align 8 %0, ptr noundef nonnull align 8 dereferenceable(24) %1) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
  tail call void @_ZNSt6vectorI8mod_q120SaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1)
  %3 = tail call noundef i64 @_ZNKSt6vectorI8mod_q120SaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  %4 = tail call noundef ptr @_ZNSt6vectorI8mod_q120SaIS0_EE4dataEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  invoke void @_ZL18q120_ntt_naive_recmdP8mod_q120(i64 noundef %3, double noundef 5.000000e-01, ptr noundef %4)
          to label %7 unwind label %5

5:                                                ; preds = %2
  %6 = landingpad { ptr, i32 }
          cleanup
  tail call void @_ZNSt6vectorI8mod_q120SaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %0) #2
  resume { ptr, i32 } %6

7:                                                ; preds = %2
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorI8mod_q120SaIS0_EEC2ERKS2_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorI8mod_q120SaIS0_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorI8mod_q120SaIS0_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass