; LLVM IR from PetoiCamp/OpenCatEsp32 :: src/icm42670 (inv_imu_driver)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.inv_imu_device = type { %struct.inv_imu_transport, ptr, [4128 x i8], i8, i8, i8, i32, i64, i64 }
%struct.inv_imu_transport = type { %struct.inv_imu_serif, %struct.register_cache, i8 }
%struct.inv_imu_serif = type { ptr, ptr, ptr, i32, i32, i32 }
%struct.register_cache = type { i8, i8, i8, i8 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) #2

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_disable_accel(ptr noundef %0) #2 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i8, align 1
  %9 = alloca i8, align 1
  %10 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #3
  store i32 0, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #3
  store i32 0, ptr %4, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #3
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = call i32 @inv_imu_read_reg(ptr noundef %11, i32 noundef 65569, i32 noundef 1, ptr noundef %9)
  %13 = load i32, ptr %3, align 4, !tbaa !9
  %14 = or i32 %13, %12
  store i32 %14, ptr %3, align 4, !tbaa !9
  %15 = load i8, ptr %9, align 1, !tbaa !11
  %16 = zext i8 %15 to i32
  %17 = and i32 %16, 15
  store i32 %17, ptr %7, align 4, !tbaa !9
  %18 = load i32, ptr %7, align 4, !tbaa !9
  %19 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %18)
  store i32 %19, ptr %5, align 4, !tbaa !9
  %20 = load ptr, ptr %2, align 8, !tbaa !5
  %21 = call i32 @inv_imu_read_reg(ptr noundef %20, i32 noundef 65567, i32 noundef 1, ptr noundef %8)
  %22 = load i32, ptr %3, align 4, !tbaa !9
  %23 = or i32 %22, %21
  store i32 %23, ptr %3, align 4, !tbaa !9
  %24 = load i8, ptr %8, align 1, !tbaa !11
  %25 = zext i8 %24 to i32
  %26 = and i32 %25, 12
  store i32 %26, ptr %6, align 4, !tbaa !9
  %27 = load ptr, ptr %2, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.inv_imu_device, ptr %27, i32 0, i32 6
  %29 = load i32, ptr %28, align 4, !tbaa !12
  %30 = icmp ne i32 %29, 0
  br i1 %30, label %31, label %35

31:                                               ; preds = %1
  %32 = load i32, ptr %6, align 4, !tbaa !9
  %33 = icmp eq i32 %32, 0
  br i1 %33, label %34, label %35

34:                                               ; preds = %31
  store i32 1, ptr %4, align 4, !tbaa !9
  br label %35

35:                                               ; preds = %34, %31, %1
  %36 = load ptr, ptr %2, align 8, !tbaa !5
  %37 = call i32 @inv_imu_read_reg(ptr noundef %36, i32 noundef 2, i32 noundef 1, ptr noundef %10)
  %38 = load i32, ptr %3, align 4, !tbaa !9
  %39 = or i32 %38, %37
  store i32 %39, ptr %3, align 4, !tbaa !9
  %40 = load i8, ptr %10, align 1, !tbaa !11
  %41 = zext i8 %40 to i32
  %42 = and i32 %41, 1
  %43 = icmp eq i32 %42, 0
  br i1 %43, label %44, label %57

44:                                               ; preds = %35
  %45 = load i32, ptr %6, align 4, !tbaa !9
  %46 = icmp eq i32 %45, 0
  br i1 %46, label %47, label %57

47:                                               ; preds = %44
  %48 = load i8, ptr %10, align 1, !tbaa !11
  %49 = zext i8 %48 to i32
  %50 = or i32 %49, 1
  %51 = trunc i32 %50 to i8
  store i8 %51, ptr %10, align 1, !tbaa !11
  %52 = load ptr, ptr %2, align 8, !tbaa !5
  %53 = call i32 @inv_imu_write_reg(ptr noundef %52, i32 noundef 2, i32 noundef 1, ptr noundef %10)
  %54 = load i32, ptr %3, align 4, !tbaa !9
  %55 = or i32 %54, %53
  store i32 %55, ptr %3, align 4, !tbaa !9
  %56 = load i32, ptr %5, align 4, !tbaa !9
  call void @inv_imu_sleep_us(i32 noundef %56)
  br label %57

57:                                               ; preds = %47, %44, %35
  %58 = load i8, ptr %8, align 1, !tbaa !11
  %59 = zext i8 %58 to i32
  %60 = and i32 %59, -4
  %61 = trunc i32 %60 to i8
  store i8 %61, ptr %8, align 1, !tbaa !11
  %62 = load i8, ptr %8, align 1, !tbaa !11
  %63 = zext i8 %62 to i32
  %64 = or i32 %63, 0
  %65 = trunc i32 %64 to i8
  store i8 %65, ptr %8, align 1, !tbaa !11
  %66 = load ptr, ptr %2, align 8, !tbaa !5
  %67 = call i32 @inv_imu_write_reg(ptr noundef %66, i32 noundef 65567, i32 noundef 1, ptr noundef %8)
  %68 = load i32, ptr %3, align 4, !tbaa !9
  %69 = or i32 %68, %67
  store i32 %69, ptr %3, align 4, !tbaa !9
  %70 = load i32, ptr %4, align 4, !tbaa !9
  %71 = icmp ne i32 %70, 0
  br i1 %71, label %72, label %82

72:                                               ; preds = %57
  %73 = load ptr, ptr %2, align 8, !tbaa !5
  %74 = getelementptr inbounds %struct.inv_imu_device, ptr %73, i32 0, i32 6
  %75 = load i32, ptr %74, align 4, !tbaa !12
  %76 = icmp ne i32 %75, 0
  br i1 %76, label %77, label %82

77:                                               ; preds = %72
  %78 = load ptr, ptr %2, align 8, !tbaa !5
  %79 = call i32 @inv_imu_reset_fifo(ptr noundef %78)
  %80 = load i32, ptr %3, align 4, !tbaa !9
  %81 = or i32 %80, %79
  store i32 %81, ptr %3, align 4, !tbaa !9
  br label %82

82:                                               ; preds = %77, %72, %57
  %83 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %9) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr %8) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #3
  ret i32 %83
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_reset_fifo(ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C/C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!7, !7, i64 0}
!12 = !{!13, !10, i64 4188}
!13 = !{!"inv_imu_device", !14, i64 0, !6, i64 48, !7, i64 56, !7, i64 4184, !7, i64 4185, !7, i64 4186, !10, i64 4188, !17, i64 4192, !17, i64 4200}
!14 = !{!"inv_imu_transport", !15, i64 0, !16, i64 40, !7, i64 44}
!15 = !{!"inv_imu_serif", !6, i64 0, !6, i64 8, !6, i64 16, !10, i64 24, !10, i64 28, !10, i64 32}
!16 = !{!"register_cache", !7, i64 0, !7, i64 1, !7, i64 2, !7, i64 3}
!17 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare void @inv_imu_sleep_us(i32 noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare i32 @inv_imu_write_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

declare i32 @inv_imu_read_reg(ptr noundef, i32 noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef) local_unnamed_addr #2

; Function Attrs: nounwind uwtable
define dso_local i32 @inv_imu_disable_accel(ptr noundef %0) local_unnamed_addr #2 {
  %2 = alloca i8, align 1
  %3 = alloca i8, align 1
  %4 = alloca i8, align 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %4) #3
  %5 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65569, i32 noundef 1, ptr noundef nonnull %3) #3
  %6 = load i8, ptr %3, align 1, !tbaa !5
  %7 = and i8 %6, 15
  %8 = zext nneg i8 %7 to i32
  %9 = call i32 @inv_imu_convert_odr_bitfield_to_us(i32 noundef %8)
  %10 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %11 = or i32 %10, %5
  %12 = load i8, ptr %2, align 1, !tbaa !5
  %13 = and i8 %12, 12
  %14 = getelementptr inbounds i8, ptr %0, i64 4188
  %15 = load i32, ptr %14, align 4, !tbaa !8
  %16 = icmp ne i32 %15, 0
  %17 = icmp eq i8 %13, 0
  %or.cond = select i1 %16, i1 %17, i1 false
  %18 = call i32 @inv_imu_read_reg(ptr noundef %0, i32 noundef 2, i32 noundef 1, ptr noundef nonnull %4) #3
  %19 = or i32 %11, %18
  %20 = load i8, ptr %4, align 1, !tbaa !5
  %21 = and i8 %20, 1
  %22 = icmp eq i8 %21, 0
  %or.cond3 = select i1 %22, i1 %17, i1 false
  br i1 %or.cond3, label %23, label %27

23:                                               ; preds = %1
  %24 = or disjoint i8 %20, 1
  store i8 %24, ptr %4, align 1, !tbaa !5
  %25 = call i32 @inv_imu_write_reg(ptr noundef nonnull %0, i32 noundef 2, i32 noundef 1, ptr noundef nonnull %4) #3
  %26 = or i32 %25, %19
  call void @inv_imu_sleep_us(i32 noundef %9) #3
  br label %27

27:                                               ; preds = %23, %1
  %.0 = phi i32 [ %26, %23 ], [ %19, %1 ]
  %28 = load i8, ptr %2, align 1, !tbaa !5
  %29 = and i8 %28, -4
  store i8 %29, ptr %2, align 1, !tbaa !5
  %30 = call i32 @inv_imu_write_reg(ptr noundef nonnull %0, i32 noundef 65567, i32 noundef 1, ptr noundef nonnull %2) #3
  %31 = or i32 %30, %.0
  br i1 %or.cond, label %32, label %37

32:                                               ; preds = %27
  %33 = load i32, ptr %14, align 4, !tbaa !8
  %.not = icmp eq i32 %33, 0
  br i1 %.not, label %37, label %34

34:                                               ; preds = %32
  %35 = call i32 @inv_imu_reset_fifo(ptr noundef nonnull %0)
  %36 = or i32 %35, %31
  br label %37

37:                                               ; preds = %34, %32, %27
  %.1 = phi i32 [ %36, %34 ], [ %31, %32 ], [ %31, %27 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %4) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %3) #3
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2) #3
  ret i32 %.1
}

; Function Attrs: nounwind uwtable
declare dso_local i32 @inv_imu_reset_fifo(ptr noundef) local_unnamed_addr #2

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{!9, !13, i64 4188}
!9 = !{!"inv_imu_device", !10, i64 0, !12, i64 48, !6, i64 56, !6, i64 4184, !6, i64 4185, !6, i64 4186, !13, i64 4188, !15, i64 4192, !15, i64 4200}
!10 = !{!"inv_imu_transport", !11, i64 0, !14, i64 40, !6, i64 44}
!11 = !{!"inv_imu_serif", !12, i64 0, !12, i64 8, !12, i64 16, !13, i64 24, !13, i64 28, !13, i64 32}
!12 = !{!"any pointer", !6, i64 0}
!13 = !{!"int", !6, i64 0}
!14 = !{!"register_cache", !6, i64 0, !6, i64 1, !6, i64 2, !6, i64 3}
!15 = !{!"long", !6, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass