; LLVM IR from facebook/redex :: libredex/ControlFlow.ll (ZN3cfg16ControlFlowGraph5clearEv)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.cfg::ControlFlowGraph" = type { %"class.std::map", %class.UnorderedSet, ptr, ptr, ptr, i32, i8, i8, i8, %"class.std::vector" }
%"class.std::map" = type { %"class.std::_Rb_tree" }
%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<unsigned long, std::pair<const unsigned long, cfg::Block *>, std::_Select1st<std::pair<const unsigned long, cfg::Block *>>, std::less<unsigned long>>::_Rb_tree_impl" }
%"struct.std::_Rb_tree<unsigned long, std::pair<const unsigned long, cfg::Block *>, std::_Select1st<std::pair<const unsigned long, cfg::Block *>>, std::less<unsigned long>>::_Rb_tree_impl" = type { [8 x i8], %"struct.std::_Rb_tree_header" }
%"struct.std::_Rb_tree_header" = type { %"struct.std::_Rb_tree_node_base", i64 }
%"struct.std::_Rb_tree_node_base" = type { i32, ptr, ptr, ptr }
%class.UnorderedSet = type { %"class.std::unordered_set" }
%"class.std::unordered_set" = type { %"class.std::_Hashtable" }
%"class.std::_Hashtable" = type { ptr, i64, %"struct.std::__detail::_Hash_node_base", i64, %"struct.std::__detail::_Prime_rehash_policy", ptr }
%"struct.std::__detail::_Hash_node_base" = type { ptr }
%"struct.std::__detail::_Prime_rehash_policy" = type { float, i64 }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<IRInstruction *, std::allocator<IRInstruction *>>::_Vector_impl" }
%"struct.std::_Vector_base<IRInstruction *, std::allocator<IRInstruction *>>::_Vector_impl" = type { %"struct.std::_Vector_base<IRInstruction *, std::allocator<IRInstruction *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<IRInstruction *, std::allocator<IRInstruction *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3cfg16ControlFlowGraph5clearEv(ptr noundef nonnull align 8 dereferenceable(160) %0) #0 align 2 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8
  call void @_ZN3cfg16ControlFlowGraph43free_all_blocks_and_edges_and_removed_insnsEv(ptr noundef nonnull align 8 dereferenceable(160) %3)
  %4 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 0
  call void @_ZNSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48) %4) #2
  %5 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 1
  call void @_ZN12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(56) %5)
  %6 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 5
  store i32 0, ptr %6, align 8, !tbaa !9
  %7 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 3
  store ptr null, ptr %7, align 8, !tbaa !32
  %8 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 4
  store ptr null, ptr %8, align 8, !tbaa !33
  %9 = getelementptr inbounds %"class.cfg::ControlFlowGraph", ptr %3, i32 0, i32 6
  store i8 1, ptr %9, align 4, !tbaa !34
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3cfg16ControlFlowGraph43free_all_blocks_and_edges_and_removed_insnsEv(ptr noundef nonnull align 8 dereferenceable(160)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(56)) #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !26, i64 128}
!10 = !{!"_ZTSN3cfg16ControlFlowGraphE", !11, i64 0, !20, i64 48, !6, i64 104, !6, i64 112, !6, i64 120, !26, i64 128, !27, i64 132, !27, i64 133, !27, i64 134, !28, i64 136}
!11 = !{!"_ZTSSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE", !12, i64 0}
!12 = !{!"_ZTSSt8_Rb_treeImSt4pairIKmPN3cfg5BlockEESt10_Select1stIS5_ESt4lessImESaIS5_EE", !13, i64 0}
!13 = !{!"_ZTSNSt8_Rb_treeImSt4pairIKmPN3cfg5BlockEESt10_Select1stIS5_ESt4lessImESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !14, i64 0, !16, i64 8}
!14 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessImEE", !15, i64 0}
!15 = !{!"_ZTSSt4lessImE"}
!16 = !{!"_ZTSSt15_Rb_tree_header", !17, i64 0, !19, i64 32}
!17 = !{!"_ZTSSt18_Rb_tree_node_base", !18, i64 0, !6, i64 8, !6, i64 16, !6, i64 24}
!18 = !{!"_ZTSSt14_Rb_tree_color", !7, i64 0}
!19 = !{!"long", !7, i64 0}
!20 = !{!"_ZTS12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt13unordered_setIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_ESaIS2_EE", !22, i64 0}
!22 = !{!"_ZTSSt10_HashtableIPN3cfg4EdgeES2_SaIS2_ENSt8__detail9_IdentityESt8equal_toIS2_ESt4hashIS2_ENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb1ELb1EEEE", !6, i64 0, !19, i64 8, !23, i64 16, !19, i64 24, !24, i64 32, !6, i64 48}
!23 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !6, i64 0}
!24 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !25, i64 0, !19, i64 8}
!25 = !{!"float", !7, i64 0}
!26 = !{!"int", !7, i64 0}
!27 = !{!"bool", !7, i64 0}
!28 = !{!"_ZTSSt6vectorIP13IRInstructionSaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSSt12_Vector_baseIP13IRInstructionSaIS1_EE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIP13IRInstructionSaIS1_EE12_Vector_implE", !31, i64 0}
!31 = !{!"_ZTSNSt12_Vector_baseIP13IRInstructionSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!32 = !{!10, !6, i64 112}
!33 = !{!10, !6, i64 120}
!34 = !{!10, !27, i64 132}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3cfg16ControlFlowGraph5clearEv(ptr noundef nonnull align 8 dereferenceable(160) %0) local_unnamed_addr #0 align 2 {
  tail call void @_ZN3cfg16ControlFlowGraph43free_all_blocks_and_edges_and_removed_insnsEv(ptr noundef nonnull align 8 dereferenceable(160) %0)
  tail call void @_ZNSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48) %0) #3
  %2 = getelementptr inbounds i8, ptr %0, i64 48
  tail call void @_ZN12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(56) %2)
  %3 = getelementptr inbounds i8, ptr %0, i64 112
  %4 = getelementptr inbounds i8, ptr %0, i64 132
  tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(20) %3, i8 0, i64 20, i1 false)
  store i8 1, ptr %4, align 4, !tbaa !5
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN3cfg16ControlFlowGraph43free_all_blocks_and_edges_and_removed_insnsEv(ptr noundef nonnull align 8 dereferenceable(160)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE5clearEv(ptr noundef nonnull align 8 dereferenceable(48)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE5clearEv(ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #1 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !26, i64 132}
!6 = !{!"_ZTSN3cfg16ControlFlowGraphE", !7, i64 0, !19, i64 48, !17, i64 104, !17, i64 112, !17, i64 120, !25, i64 128, !26, i64 132, !26, i64 133, !26, i64 134, !27, i64 136}
!7 = !{!"_ZTSSt3mapImPN3cfg5BlockESt4lessImESaISt4pairIKmS2_EEE", !8, i64 0}
!8 = !{!"_ZTSSt8_Rb_treeImSt4pairIKmPN3cfg5BlockEESt10_Select1stIS5_ESt4lessImESaIS5_EE", !9, i64 0}
!9 = !{!"_ZTSNSt8_Rb_treeImSt4pairIKmPN3cfg5BlockEESt10_Select1stIS5_ESt4lessImESaIS5_EE13_Rb_tree_implIS9_Lb1EEE", !10, i64 0, !12, i64 8}
!10 = !{!"_ZTSSt20_Rb_tree_key_compareISt4lessImEE", !11, i64 0}
!11 = !{!"_ZTSSt4lessImE"}
!12 = !{!"_ZTSSt15_Rb_tree_header", !13, i64 0, !18, i64 32}
!13 = !{!"_ZTSSt18_Rb_tree_node_base", !14, i64 0, !17, i64 8, !17, i64 16, !17, i64 24}
!14 = !{!"_ZTSSt14_Rb_tree_color", !15, i64 0}
!15 = !{!"omnipotent char", !16, i64 0}
!16 = !{!"Simple C++ TBAA"}
!17 = !{!"any pointer", !15, i64 0}
!18 = !{!"long", !15, i64 0}
!19 = !{!"_ZTS12UnorderedSetIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_EE", !20, i64 0}
!20 = !{!"_ZTSSt13unordered_setIPN3cfg4EdgeESt4hashIS2_ESt8equal_toIS2_ESaIS2_EE", !21, i64 0}
!21 = !{!"_ZTSSt10_HashtableIPN3cfg4EdgeES2_SaIS2_ENSt8__detail9_IdentityESt8equal_toIS2_ESt4hashIS2_ENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb1ELb1EEEE", !17, i64 0, !18, i64 8, !22, i64 16, !18, i64 24, !23, i64 32, !17, i64 48}
!22 = !{!"_ZTSNSt8__detail15_Hash_node_baseE", !17, i64 0}
!23 = !{!"_ZTSNSt8__detail20_Prime_rehash_policyE", !24, i64 0, !18, i64 8}
!24 = !{!"float", !15, i64 0}
!25 = !{!"int", !15, i64 0}
!26 = !{!"bool", !15, i64 0}
!27 = !{!"_ZTSSt6vectorIP13IRInstructionSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSSt12_Vector_baseIP13IRInstructionSaIS1_EE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP13IRInstructionSaIS1_EE12_Vector_implE", !30, i64 0}
!30 = !{!"_ZTSNSt12_Vector_baseIP13IRInstructionSaIS1_EE17_Vector_impl_dataE", !17, i64 0, !17, i64 8, !17, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InstCombinePass,MemCpyOptPass,SROAPass,TailCallElimPass