; LLVM IR from xtensor-stack/xsimd :: test/doc (explicit_use_of_an_instruction_set_mean_aligned)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.xsimd::batch" = type { %"struct.xsimd::types::simd_register" }
%"struct.xsimd::types::simd_register" = type { <2 x double> }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z4meanRKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEES5_RS3_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) #0 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i64, align 8
  %8 = alloca i64, align 8
  %9 = alloca i64, align 8
  %10 = alloca i64, align 8
  %11 = alloca %"class.xsimd::batch", align 16
  %12 = alloca %"class.xsimd::batch", align 16
  %13 = alloca %"class.xsimd::batch", align 16
  %14 = alloca %"class.xsimd::batch", align 16
  %15 = alloca %"class.xsimd::batch", align 16
  %16 = alloca i64, align 8
  store ptr %0, ptr %4, align 8, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  store i64 2, ptr %7, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #5
  %17 = load ptr, ptr %6, align 8, !tbaa !5
  %18 = call noundef i64 @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #5
  store i64 %18, ptr %8, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %9) #5
  %19 = load i64, ptr %8, align 8, !tbaa !9
  %20 = load i64, ptr %8, align 8, !tbaa !9
  %21 = load i64, ptr %7, align 8, !tbaa !9
  %22 = urem i64 %20, %21
  %23 = sub i64 %19, %22
  store i64 %23, ptr %9, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #5
  store i64 0, ptr %10, align 8, !tbaa !9
  br label %24

24:                                               ; preds = %51, %3
  %25 = load i64, ptr %10, align 8, !tbaa !9
  %26 = load i64, ptr %9, align 8, !tbaa !9
  %27 = icmp ult i64 %25, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #5
  br label %55

29:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 16, ptr %11) #5
  %30 = load ptr, ptr %4, align 8, !tbaa !5
  %31 = load i64, ptr %10, align 8, !tbaa !9
  %32 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %30, i64 noundef %31) #5
  %33 = call <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef %32) #5
  %34 = getelementptr inbounds %"class.xsimd::batch", ptr %11, i32 0, i32 0
  %35 = getelementptr inbounds %"struct.xsimd::types::simd_register", ptr %34, i32 0, i32 0
  store <2 x double> %33, ptr %35, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr %12) #5
  %36 = load ptr, ptr %5, align 8, !tbaa !5
  %37 = load i64, ptr %10, align 8, !tbaa !9
  %38 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %36, i64 noundef %37) #5
  %39 = call <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef %38) #5
  %40 = getelementptr inbounds %"class.xsimd::batch", ptr %12, i32 0, i32 0
  %41 = getelementptr inbounds %"struct.xsimd::types::simd_register", ptr %40, i32 0, i32 0
  store <2 x double> %39, ptr %41, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr %13) #5
  call void @llvm.lifetime.start.p0(i64 16, ptr %14) #5
  %42 = call <2 x double> @_ZN5xsimdplERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16) %11, ptr noundef nonnull align 16 dereferenceable(16) %12) #5
  %43 = getelementptr inbounds %"class.xsimd::batch", ptr %14, i32 0, i32 0
  %44 = getelementptr inbounds %"struct.xsimd::types::simd_register", ptr %43, i32 0, i32 0
  store <2 x double> %42, ptr %44, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr %15) #5
  call void @_ZN5xsimd5batchIdNS_4sse2EEC2Ed(ptr noundef nonnull align 16 dereferenceable(16) %15, double noundef 2.000000e+00) #5
  %45 = call <2 x double> @_ZN5xsimddvERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16) %14, ptr noundef nonnull align 16 dereferenceable(16) %15) #5
  %46 = getelementptr inbounds %"class.xsimd::batch", ptr %13, i32 0, i32 0
  %47 = getelementptr inbounds %"struct.xsimd::types::simd_register", ptr %46, i32 0, i32 0
  store <2 x double> %45, ptr %47, align 16
  call void @llvm.lifetime.end.p0(i64 16, ptr %15) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %14) #5
  %48 = load ptr, ptr %6, align 8, !tbaa !5
  %49 = load i64, ptr %10, align 8, !tbaa !9
  %50 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %48, i64 noundef %49) #5
  call void @_ZNK5xsimd5batchIdNS_4sse2EE13store_alignedIdEEvPT_(ptr noundef nonnull align 16 dereferenceable(16) %13, ptr noundef %50) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr %11) #5
  br label %51

51:                                               ; preds = %29
  %52 = load i64, ptr %7, align 8, !tbaa !9
  %53 = load i64, ptr %10, align 8, !tbaa !9
  %54 = add i64 %53, %52
  store i64 %54, ptr %10, align 8, !tbaa !9
  br label %24, !llvm.loop !11

55:                                               ; preds = %28
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #5
  %56 = load i64, ptr %9, align 8, !tbaa !9
  store i64 %56, ptr %16, align 8, !tbaa !9
  br label %57

57:                                               ; preds = %76, %55
  %58 = load i64, ptr %16, align 8, !tbaa !9
  %59 = load i64, ptr %8, align 8, !tbaa !9
  %60 = icmp ult i64 %58, %59
  br i1 %60, label %62, label %61

61:                                               ; preds = %57
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #5
  br label %79

62:                                               ; preds = %57
  %63 = load ptr, ptr %4, align 8, !tbaa !5
  %64 = load i64, ptr %16, align 8, !tbaa !9
  %65 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %63, i64 noundef %64) #5
  %66 = load double, ptr %65, align 8, !tbaa !13
  %67 = load ptr, ptr %5, align 8, !tbaa !5
  %68 = load i64, ptr %16, align 8, !tbaa !9
  %69 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %67, i64 noundef %68) #5
  %70 = load double, ptr %69, align 8, !tbaa !13
  %71 = fadd double %66, %70
  %72 = fdiv double %71, 2.000000e+00
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  %74 = load i64, ptr %16, align 8, !tbaa !9
  %75 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %73, i64 noundef %74) #5
  store double %72, ptr %75, align 8, !tbaa !13
  br label %76

76:                                               ; preds = %62
  %77 = load i64, ptr %16, align 8, !tbaa !9
  %78 = add i64 %77, 1
  store i64 %78, ptr %16, align 8, !tbaa !9
  br label %57, !llvm.loop !15

79:                                               ; preds = %61
  call void @llvm.lifetime.end.p0(i64 8, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimddvERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef nonnull align 16 dereferenceable(16)) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimdplERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef nonnull align 16 dereferenceable(16)) #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN5xsimd5batchIdNS_4sse2EEC2Ed(ptr noundef nonnull align 16 dereferenceable(16), double noundef) unnamed_addr #3 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZNK5xsimd5batchIdNS_4sse2EE13store_alignedIdEEvPT_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef) #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = !{!14, !14, i64 0}
!14 = !{!"double", !7, i64 0}
!15 = distinct !{!15, !12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.xsimd::batch" = type { %"struct.xsimd::types::simd_register" }
%"struct.xsimd::types::simd_register" = type { <2 x double> }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z4meanRKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEES5_RS3_(ptr noundef nonnull align 8 dereferenceable(24) %0, ptr noundef nonnull align 8 dereferenceable(24) %1, ptr noundef nonnull align 8 dereferenceable(24) %2) local_unnamed_addr #0 {
  %4 = alloca %"class.xsimd::batch", align 16
  %5 = alloca %"class.xsimd::batch", align 16
  %6 = alloca %"class.xsimd::batch", align 16
  %7 = alloca %"class.xsimd::batch", align 16
  %8 = alloca %"class.xsimd::batch", align 16
  %9 = tail call noundef i64 @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2) #5
  %10 = and i64 %9, -2
  %.not = icmp eq i64 %10, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.preheader:                                       ; preds = %.lr.ph, %3
  %.not28 = icmp eq i64 %10, %9
  br i1 %.not28, label %._crit_edge, label %.lr.ph27

.lr.ph:                                           ; preds = %3, %.lr.ph
  %.02325 = phi i64 [ %18, %.lr.ph ], [ 0, %3 ]
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %4) #5
  %11 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.02325) #5
  %12 = call <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef nonnull %11) #5
  store <2 x double> %12, ptr %4, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #5
  %13 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %.02325) #5
  %14 = call <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef nonnull %13) #5
  store <2 x double> %14, ptr %5, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %6) #5
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %7) #5
  %15 = call <2 x double> @_ZN5xsimdplERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16) %4, ptr noundef nonnull align 16 dereferenceable(16) %5) #5
  store <2 x double> %15, ptr %7, align 16
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %8) #5
  call void @_ZN5xsimd5batchIdNS_4sse2EEC2Ed(ptr noundef nonnull align 16 dereferenceable(16) %8, double noundef 2.000000e+00) #5
  %16 = call <2 x double> @_ZN5xsimddvERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16) %7, ptr noundef nonnull align 16 dereferenceable(16) %8) #5
  store <2 x double> %16, ptr %6, align 16
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %7) #5
  %17 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %.02325) #5
  call void @_ZNK5xsimd5batchIdNS_4sse2EE13store_alignedIdEEvPT_(ptr noundef nonnull align 16 dereferenceable(16) %6, ptr noundef nonnull %17) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %6) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %4) #5
  %18 = add nuw i64 %.02325, 2
  %19 = icmp ult i64 %18, %10
  br i1 %19, label %.lr.ph, label %.preheader, !llvm.loop !5

._crit_edge:                                      ; preds = %.lr.ph27, %.preheader
  ret void

.lr.ph27:                                         ; preds = %.preheader, %.lr.ph27
  %.026 = phi i64 [ %27, %.lr.ph27 ], [ %10, %.preheader ]
  %20 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %.026) #5
  %21 = load double, ptr %20, align 8, !tbaa !7
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %1, i64 noundef %.026) #5
  %23 = load double, ptr %22, align 8, !tbaa !7
  %24 = fadd double %21, %23
  %25 = fmul double %24, 5.000000e-01
  %26 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %2, i64 noundef %.026) #5
  store double %25, ptr %26, align 8, !tbaa !7
  %27 = add nuw i64 %.026, 1
  %28 = icmp ult i64 %27, %9
  br i1 %28, label %.lr.ph27, label %._crit_edge, !llvm.loop !11
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimd5batchIdNS_4sse2EE12load_alignedIdEES2_PKT_(ptr noundef) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNKSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimddvERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef nonnull align 16 dereferenceable(16)) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local <2 x double> @_ZN5xsimdplERKNS_5batchIdNS_4sse2EEES4_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef nonnull align 16 dereferenceable(16)) local_unnamed_addr #3

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZN5xsimd5batchIdNS_4sse2EEC2Ed(ptr noundef nonnull align 16 dereferenceable(16), double noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: alwaysinline mustprogress nounwind uwtable
declare dso_local void @_ZNK5xsimd5batchIdNS_4sse2EE13store_alignedIdEEvPT_(ptr noundef nonnull align 16 dereferenceable(16), ptr noundef) local_unnamed_addr #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIdN5xsimd17aligned_allocatorIdLm16EEEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #2 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { alwaysinline mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = !{!8, !8, i64 0}
!8 = !{!"double", !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = distinct !{!11, !6}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass