; LLVM IR from quantumlib/qsim :: apps (qsimh_base)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::vector", i64, i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter" = type <{ %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", [4 x i8], i64, i32, i32, i32, [4 x i8] }>
%"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter" = type { i32 }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::complex" = type { { float, float } }
%"class.std::allocator.15" = type { i8 }
%struct.Factory = type { i32 }

@_ZZ4mainE4bits = external hidden constant [8 x ptr], align 16
@.str.11 = external hidden unnamed_addr constant [23 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(85)) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8, i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main(i32 noundef %0, ptr noundef %1) #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca %struct.Options, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %"struct.qsim::Circuit", align 8
  %11 = alloca %"class.std::vector", align 8
  %12 = alloca i64, align 8
  %13 = alloca i64, align 8
  %14 = alloca i64, align 8
  %15 = alloca %"class.std::vector.8", align 8
  %16 = alloca i64, align 8
  %17 = alloca %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", align 8
  %18 = alloca %"class.std::vector.13", align 8
  %19 = alloca %"class.std::complex", align 4
  %20 = alloca %"class.std::allocator.15", align 1
  %21 = alloca %struct.Factory, align 4
  %22 = alloca i32, align 4
  %23 = alloca i32, align 4
  %24 = alloca i64, align 8
  %25 = alloca ptr, align 8
  store i32 0, ptr %3, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 88, ptr %6) #6
  %26 = load i32, ptr %4, align 4, !tbaa !5
  %27 = load ptr, ptr %5, align 8, !tbaa !9
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind writable sret(%struct.Options) align 8 %6, i32 noundef %26, ptr noundef %27)
  %28 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(85) %6)
          to label %29 unwind label %31

29:                                               ; preds = %2
  br i1 %28, label %35, label %30

30:                                               ; preds = %29
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %195

31:                                               ; preds = %2
  %32 = landingpad { ptr, i32 }
          cleanup
  %33 = extractvalue { ptr, i32 } %32, 0
  store ptr %33, ptr %7, align 8
  %34 = extractvalue { ptr, i32 } %32, 1
  store i32 %34, ptr %8, align 4
  br label %197

35:                                               ; preds = %29
  call void @llvm.lifetime.start.p0(i64 32, ptr %10) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  %36 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 3
  %37 = load i32, ptr %36, align 8, !tbaa !11
  %38 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 0
  %39 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %37, ptr noundef nonnull align 8 dereferenceable(32) %38, ptr noundef nonnull align 8 dereferenceable(32) %10)
          to label %40 unwind label %42

40:                                               ; preds = %35
  br i1 %39, label %46, label %41

41:                                               ; preds = %40
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %193

42:                                               ; preds = %46, %35
  %43 = landingpad { ptr, i32 }
          cleanup
  %44 = extractvalue { ptr, i32 } %43, 0
  store ptr %44, ptr %7, align 8
  %45 = extractvalue { ptr, i32 } %43, 1
  store i32 %45, ptr %8, align 4
  br label %194

46:                                               ; preds = %40
  %47 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %48 = load i32, ptr %47, align 8, !tbaa !21
  %49 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  %50 = invoke noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef %48, ptr noundef nonnull align 8 dereferenceable(24) %49)
          to label %51 unwind label %42

51:                                               ; preds = %46
  br i1 %50, label %53, label %52

52:                                               ; preds = %51
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %193

53:                                               ; preds = %51
  call void @llvm.lifetime.start.p0(i64 24, ptr %11) #6
  %54 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %55 = load i32, ptr %54, align 8, !tbaa !21
  %56 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  invoke void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind writable sret(%"class.std::vector") align 8 %11, i32 noundef %55, ptr noundef nonnull align 8 dereferenceable(24) %56)
          to label %57 unwind label %63

57:                                               ; preds = %53
  %58 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 8
  %59 = load i8, ptr %58, align 4, !tbaa !27, !range !28, !noundef !29
  %60 = trunc i8 %59 to i1
  br i1 %60, label %61, label %71

61:                                               ; preds = %57
  invoke void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
          to label %62 unwind label %67

62:                                               ; preds = %61
  br label %71

63:                                               ; preds = %53
  %64 = landingpad { ptr, i32 }
          cleanup
  %65 = extractvalue { ptr, i32 } %64, 0
  store ptr %65, ptr %7, align 8
  %66 = extractvalue { ptr, i32 } %64, 1
  store i32 %66, ptr %8, align 4
  br label %192

67:                                               ; preds = %61
  %68 = landingpad { ptr, i32 }
          cleanup
  %69 = extractvalue { ptr, i32 } %68, 0
  store ptr %69, ptr %7, align 8
  %70 = extractvalue { ptr, i32 } %68, 1
  store i32 %70, ptr %8, align 4
  br label %191

71:                                               ; preds = %62, %57
  call void @llvm.lifetime.start.p0(i64 8, ptr %12) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #6
  store i64 8, ptr %13, align 8, !tbaa !30
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #6
  %72 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %73 = load i32, ptr %72, align 8, !tbaa !21
  %74 = zext i32 %73 to i64
  %75 = shl i64 1, %74
  store i64 %75, ptr %14, align 8, !tbaa !30
  %76 = invoke noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %13, ptr noundef nonnull align 8 dereferenceable(8) %14)
          to label %77 unwind label %86

77:                                               ; preds = %71
  %78 = load i64, ptr %76, align 8, !tbaa !30
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #6
  store i64 %78, ptr %12, align 8, !tbaa !30
  call void @llvm.lifetime.start.p0(i64 24, ptr %15) #6
  call void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #6
  %79 = load i64, ptr %12, align 8, !tbaa !30
  invoke void @_ZNSt6vectorImSaImEE7reserveEm(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %79)
          to label %80 unwind label %90

80:                                               ; preds = %77
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #6
  store i64 0, ptr %16, align 8, !tbaa !30
  br label %81

81:                                               ; preds = %96, %80
  %82 = load i64, ptr %16, align 8, !tbaa !30
  %83 = load i64, ptr %12, align 8, !tbaa !30
  %84 = icmp ult i64 %82, %83
  br i1 %84, label %94, label %85

85:                                               ; preds = %81
  store i32 2, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #6
  br label %103

86:                                               ; preds = %71
  %87 = landingpad { ptr, i32 }
          cleanup
  %88 = extractvalue { ptr, i32 } %87, 0
  store ptr %88, ptr %7, align 8
  %89 = extractvalue { ptr, i32 } %87, 1
  store i32 %89, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #6
  br label %190

90:                                               ; preds = %77
  %91 = landingpad { ptr, i32 }
          cleanup
  %92 = extractvalue { ptr, i32 } %91, 0
  store ptr %92, ptr %7, align 8
  %93 = extractvalue { ptr, i32 } %91, 1
  store i32 %93, ptr %8, align 4
  br label %189

94:                                               ; preds = %81
  invoke void @_ZNSt6vectorImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef nonnull align 8 dereferenceable(8) %16)
          to label %95 unwind label %99

95:                                               ; preds = %94
  br label %96

96:                                               ; preds = %95
  %97 = load i64, ptr %16, align 8, !tbaa !30
  %98 = add i64 %97, 1
  store i64 %98, ptr %16, align 8, !tbaa !30
  br label %81, !llvm.loop !31

99:                                               ; preds = %94
  %100 = landingpad { ptr, i32 }
          cleanup
  %101 = extractvalue { ptr, i32 } %100, 0
  store ptr %101, ptr %7, align 8
  %102 = extractvalue { ptr, i32 } %100, 1
  store i32 %102, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #6
  br label %189

103:                                              ; preds = %85
  call void @llvm.lifetime.start.p0(i64 32, ptr %17) #6
  call void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28) %17) #6
  %104 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 2
  %105 = load i64, ptr %104, align 8, !tbaa !33
  %106 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %17, i32 0, i32 2
  store i64 %105, ptr %106, align 8, !tbaa !34
  %107 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 4
  %108 = load i32, ptr %107, align 4, !tbaa !37
  %109 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %17, i32 0, i32 3
  store i32 %108, ptr %109, align 8, !tbaa !38
  %110 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 5
  %111 = load i32, ptr %110, align 8, !tbaa !39
  %112 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %17, i32 0, i32 4
  store i32 %111, ptr %112, align 4, !tbaa !40
  %113 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 6
  %114 = load i32, ptr %113, align 4, !tbaa !41
  %115 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %17, i32 0, i32 5
  store i32 %114, ptr %115, align 8, !tbaa !42
  %116 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 7
  %117 = load i32, ptr %116, align 8, !tbaa !43
  %118 = getelementptr inbounds %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", ptr %17, i32 0, i32 0
  store i32 %117, ptr %118, align 8, !tbaa !44
  call void @llvm.lifetime.start.p0(i64 24, ptr %18) #6
  %119 = load i64, ptr %12, align 8, !tbaa !30
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #6
  invoke void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8) %19, float noundef 0.000000e+00, float noundef 0.000000e+00)
          to label %120 unwind label %138

120:                                              ; preds = %103
  call void @llvm.lifetime.start.p0(i64 1, ptr %20) #6
  call void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %20) #6
  invoke void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %119, ptr noundef nonnull align 4 dereferenceable(8) %19, ptr noundef nonnull align 1 dereferenceable(1) %20)
          to label %121 unwind label %142

121:                                              ; preds = %120
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %20) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr %20) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #6
  %122 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 6
  %123 = load i32, ptr %122, align 4, !tbaa !41
  invoke void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %21, i32 noundef %123)
          to label %124 unwind label %147

124:                                              ; preds = %121
  %125 = invoke noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28) %17, ptr noundef nonnull align 4 dereferenceable(4) %21, ptr noundef nonnull align 8 dereferenceable(32) %10, ptr noundef nonnull align 8 dereferenceable(24) %11, ptr noundef nonnull align 8 dereferenceable(24) %15, ptr noundef nonnull align 8 dereferenceable(24) %18)
          to label %126 unwind label %147

126:                                              ; preds = %124
  br i1 %125, label %127, label %186

127:                                              ; preds = %126
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #6
  store i32 3, ptr %23, align 4, !tbaa !5
  %128 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %129 = invoke noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIjERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %23, ptr noundef nonnull align 4 dereferenceable(4) %128)
          to label %130 unwind label %151

130:                                              ; preds = %127
  %131 = load i32, ptr %129, align 4, !tbaa !5
  %132 = sub i32 3, %131
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #6
  store i32 %132, ptr %22, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %24) #6
  store i64 0, ptr %24, align 8, !tbaa !30
  br label %133

133:                                              ; preds = %177, %130
  %134 = load i64, ptr %24, align 8, !tbaa !30
  %135 = load i64, ptr %12, align 8, !tbaa !30
  %136 = icmp ult i64 %134, %135
  br i1 %136, label %155, label %137

137:                                              ; preds = %133
  store i32 5, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %24) #6
  br label %184

138:                                              ; preds = %103
  %139 = landingpad { ptr, i32 }
          cleanup
  %140 = extractvalue { ptr, i32 } %139, 0
  store ptr %140, ptr %7, align 8
  %141 = extractvalue { ptr, i32 } %139, 1
  store i32 %141, ptr %8, align 4
  br label %146

142:                                              ; preds = %120
  %143 = landingpad { ptr, i32 }
          cleanup
  %144 = extractvalue { ptr, i32 } %143, 0
  store ptr %144, ptr %7, align 8
  %145 = extractvalue { ptr, i32 } %143, 1
  store i32 %145, ptr %8, align 4
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %20) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr %20) #6
  br label %146

146:                                              ; preds = %142, %138
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #6
  br label %188

147:                                              ; preds = %124, %121
  %148 = landingpad { ptr, i32 }
          cleanup
  %149 = extractvalue { ptr, i32 } %148, 0
  store ptr %149, ptr %7, align 8
  %150 = extractvalue { ptr, i32 } %148, 1
  store i32 %150, ptr %8, align 4
  br label %187

151:                                              ; preds = %127
  %152 = landingpad { ptr, i32 }
          cleanup
  %153 = extractvalue { ptr, i32 } %152, 0
  store ptr %153, ptr %7, align 8
  %154 = extractvalue { ptr, i32 } %152, 1
  store i32 %154, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %23) #6
  br label %185

155:                                              ; preds = %133
  call void @llvm.lifetime.start.p0(i64 8, ptr %25) #6
  %156 = load i64, ptr %24, align 8, !tbaa !30
  %157 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorISt7complexIfESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %156) #6
  store ptr %157, ptr %25, align 8, !tbaa !9
  %158 = load i64, ptr %24, align 8, !tbaa !30
  %159 = getelementptr inbounds [8 x ptr], ptr @_ZZ4mainE4bits, i64 0, i64 %158
  %160 = load ptr, ptr %159, align 8, !tbaa !9
  %161 = load i32, ptr %22, align 4, !tbaa !5
  %162 = zext i32 %161 to i64
  %163 = getelementptr inbounds i8, ptr %160, i64 %162
  %164 = load ptr, ptr %25, align 8, !tbaa !9
  %165 = invoke noundef float @_ZSt4realIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %164)
          to label %166 unwind label %180

166:                                              ; preds = %155
  %167 = fpext float %165 to double
  %168 = load ptr, ptr %25, align 8, !tbaa !9
  %169 = invoke noundef float @_ZSt4imagIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %168)
          to label %170 unwind label %180

170:                                              ; preds = %166
  %171 = fpext float %169 to double
  %172 = load ptr, ptr %25, align 8, !tbaa !9
  %173 = invoke noundef float @_ZSt4normIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %172)
          to label %174 unwind label %180

174:                                              ; preds = %170
  %175 = fpext float %173 to double
  invoke void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef @.str.11, ptr noundef %163, double noundef %167, double noundef %171, double noundef %175)
          to label %176 unwind label %180

176:                                              ; preds = %174
  call void @llvm.lifetime.end.p0(i64 8, ptr %25) #6
  br label %177

177:                                              ; preds = %176
  %178 = load i64, ptr %24, align 8, !tbaa !30
  %179 = add i64 %178, 1
  store i64 %179, ptr %24, align 8, !tbaa !30
  br label %133, !llvm.loop !45

180:                                              ; preds = %174, %170, %166, %155
  %181 = landingpad { ptr, i32 }
          cleanup
  %182 = extractvalue { ptr, i32 } %181, 0
  store ptr %182, ptr %7, align 8
  %183 = extractvalue { ptr, i32 } %181, 1
  store i32 %183, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 8, ptr %25) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %24) #6
  br label %185

184:                                              ; preds = %137
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #6
  br label %186

185:                                              ; preds = %180, %151
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #6
  br label %187

186:                                              ; preds = %184, %126
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %18) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %17) #6
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #6
  br label %193

187:                                              ; preds = %185, %147
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %18) #6
  br label %188

188:                                              ; preds = %187, %146
  call void @llvm.lifetime.end.p0(i64 24, ptr %18) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %17) #6
  br label %189

189:                                              ; preds = %188, %99, %90
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #6
  br label %190

190:                                              ; preds = %189, %86
  call void @llvm.lifetime.end.p0(i64 8, ptr %12) #6
  br label %191

191:                                              ; preds = %190, %67
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  br label %192

192:                                              ; preds = %191, %63
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #6
  br label %194

193:                                              ; preds = %186, %52, %41
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %195

194:                                              ; preds = %192, %42
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %197

195:                                              ; preds = %193, %30
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85) %6) #6
  call void @llvm.lifetime.end.p0(i64 88, ptr %6) #6
  %196 = load i32, ptr %3, align 4
  ret i32 %196

197:                                              ; preds = %194, %31
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85) %6) #6
  call void @llvm.lifetime.end.p0(i64 88, ptr %6) #6
  br label %198

198:                                              ; preds = %197
  %199 = load ptr, ptr %7, align 8
  %200 = load i32, ptr %8, align 4
  %201 = insertvalue { ptr, i32 } poison, ptr %199, 0
  %202 = insertvalue { ptr, i32 } %201, i32 %200, 1
  resume { ptr, i32 } %202
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorImSaImEE7reserveEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8), float noundef, float noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIjERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorISt7complexIfESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZSt4realIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZSt4imagIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef float @_ZSt4normIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !6, i64 64}
!12 = !{!"_ZTS7Options", !13, i64 0, !16, i64 32, !15, i64 56, !6, i64 64, !6, i64 68, !6, i64 72, !6, i64 76, !6, i64 80, !20, i64 84}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIjSaIjEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!22, !6, i64 0}
!22 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !6, i64 0, !23, i64 8}
!23 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!27 = !{!12, !20, i64 84}
!28 = !{i8 0, i8 2}
!29 = !{}
!30 = !{!15, !15, i64 0}
!31 = distinct !{!31, !32}
!32 = !{!"llvm.loop.mustprogress"}
!33 = !{!12, !15, i64 56}
!34 = !{!35, !15, i64 8}
!35 = !{!"_ZTSN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterE", !36, i64 0, !15, i64 8, !6, i64 16, !6, i64 20, !6, i64 24}
!36 = !{!"_ZTSN4qsim14BasicGateFuserINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEES0_NS_13SequentialForEE10GateHybridEE9ParameterE", !6, i64 0}
!37 = !{!12, !6, i64 68}
!38 = !{!35, !6, i64 16}
!39 = !{!12, !6, i64 72}
!40 = !{!35, !6, i64 20}
!41 = !{!12, !6, i64 76}
!42 = !{!35, !6, i64 24}
!43 = !{!12, !6, i64 80}
!44 = !{!36, !6, i64 0}
!45 = distinct !{!45, !32}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::vector", i64, i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter" = type <{ %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", [4 x i8], i64, i32, i32, i32, [4 x i8] }>
%"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter" = type { i32 }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::complex" = type { { float, float } }
%"class.std::allocator.15" = type { i8 }
%struct.Factory = type { i32 }

@_ZZ4mainE4bits = external hidden local_unnamed_addr constant [8 x ptr], align 16
@.str.11 = external hidden unnamed_addr constant [23 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(85)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8, i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef range(i32 0, 2) i32 @main(i32 noundef %0, ptr noundef %1) local_unnamed_addr #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca %struct.Options, align 8
  %4 = alloca %"struct.qsim::Circuit", align 8
  %5 = alloca %"class.std::vector", align 8
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  %8 = alloca %"class.std::vector.8", align 8
  %9 = alloca i64, align 8
  %10 = alloca %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", align 8
  %11 = alloca %"class.std::vector.13", align 8
  %12 = alloca %"class.std::complex", align 4
  %13 = alloca %"class.std::allocator.15", align 1
  %14 = alloca %struct.Factory, align 4
  %15 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 88, ptr nonnull %3) #6
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind nonnull writable sret(%struct.Options) align 8 %3, i32 noundef %0, ptr noundef %1)
  %16 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(85) %3)
          to label %17 unwind label %18

17:                                               ; preds = %2
  br i1 %16, label %20, label %103

18:                                               ; preds = %2
  %19 = landingpad { ptr, i32 }
          cleanup
  br label %104

20:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %4) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  %21 = getelementptr inbounds i8, ptr %3, i64 64
  %22 = load i32, ptr %21, align 8, !tbaa !5
  %23 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %22, ptr noundef nonnull align 8 dereferenceable(32) %3, ptr noundef nonnull align 8 dereferenceable(32) %4)
          to label %24 unwind label %25

24:                                               ; preds = %20
  br i1 %23, label %27, label %101

25:                                               ; preds = %27, %20
  %26 = landingpad { ptr, i32 }
          cleanup
  br label %102

27:                                               ; preds = %24
  %28 = load i32, ptr %4, align 8, !tbaa !19
  %29 = getelementptr inbounds i8, ptr %3, i64 32
  %30 = invoke noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef %28, ptr noundef nonnull align 8 dereferenceable(24) %29)
          to label %31 unwind label %25

31:                                               ; preds = %27
  br i1 %30, label %32, label %101

32:                                               ; preds = %31
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %5) #6
  %33 = load i32, ptr %4, align 8, !tbaa !19
  invoke void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind nonnull writable sret(%"class.std::vector") align 8 %5, i32 noundef %33, ptr noundef nonnull align 8 dereferenceable(24) %29)
          to label %34 unwind label %39

34:                                               ; preds = %32
  %35 = getelementptr inbounds i8, ptr %3, i64 84
  %36 = load i8, ptr %35, align 4, !tbaa !25, !range !26, !noundef !27
  %37 = trunc nuw i8 %36 to i1
  br i1 %37, label %38, label %41

38:                                               ; preds = %34
  call void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
  br label %41

39:                                               ; preds = %32
  %40 = landingpad { ptr, i32 }
          cleanup
  br label %100

41:                                               ; preds = %38, %34
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %6) #6
  store i64 8, ptr %6, align 8, !tbaa !28
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %7) #6
  %42 = load i32, ptr %4, align 8, !tbaa !19
  %43 = zext nneg i32 %42 to i64
  %44 = shl nuw i64 1, %43
  store i64 %44, ptr %7, align 8, !tbaa !28
  %45 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %7)
  %46 = load i64, ptr %45, align 8, !tbaa !28
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %7) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %6) #6
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %8) #6
  call void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  invoke void @_ZNSt6vectorImSaImEE7reserveEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %46)
          to label %47 unwind label %59

47:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %9) #6
  store i64 0, ptr %9, align 8, !tbaa !28
  %.not = icmp eq i64 %46, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %61, %47
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %9) #6
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %10) #6
  call void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28) %10) #6
  %48 = getelementptr inbounds i8, ptr %3, i64 56
  %49 = load i64, ptr %48, align 8, !tbaa !29
  %50 = getelementptr inbounds i8, ptr %10, i64 8
  store i64 %49, ptr %50, align 8, !tbaa !30
  %51 = getelementptr inbounds i8, ptr %3, i64 68
  %52 = getelementptr inbounds i8, ptr %10, i64 16
  %53 = load <2 x i32>, ptr %51, align 4, !tbaa !33
  store <2 x i32> %53, ptr %52, align 8, !tbaa !33
  %54 = getelementptr inbounds i8, ptr %3, i64 76
  %55 = load i32, ptr %54, align 4, !tbaa !34
  %56 = getelementptr inbounds i8, ptr %10, i64 24
  store i32 %55, ptr %56, align 8, !tbaa !35
  %57 = getelementptr inbounds i8, ptr %3, i64 80
  %58 = load i32, ptr %57, align 8, !tbaa !36
  store i32 %58, ptr %10, align 8, !tbaa !37
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %11) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %12) #6
  call void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8) %12, float noundef 0.000000e+00, float noundef 0.000000e+00)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %13) #6
  call void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %13) #6
  invoke void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %46, ptr noundef nonnull align 4 dereferenceable(8) %12, ptr noundef nonnull align 1 dereferenceable(1) %13)
          to label %67 unwind label %76

59:                                               ; preds = %41
  %60 = landingpad { ptr, i32 }
          cleanup
  br label %99

.lr.ph:                                           ; preds = %47, %61
  invoke void @_ZNSt6vectorImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(24) %8, ptr noundef nonnull align 8 dereferenceable(8) %9)
          to label %61 unwind label %65

61:                                               ; preds = %.lr.ph
  %62 = load i64, ptr %9, align 8, !tbaa !28
  %63 = add i64 %62, 1
  store i64 %63, ptr %9, align 8, !tbaa !28
  %64 = icmp ult i64 %63, %46
  br i1 %64, label %.lr.ph, label %._crit_edge, !llvm.loop !38

65:                                               ; preds = %.lr.ph
  %66 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %9) #6
  br label %99

67:                                               ; preds = %._crit_edge
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %13) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %13) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %12) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %14) #6
  %68 = load i32, ptr %54, align 4, !tbaa !34
  call void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %14, i32 noundef %68)
  %69 = invoke noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28) %10, ptr noundef nonnull align 4 dereferenceable(4) %14, ptr noundef nonnull align 8 dereferenceable(32) %4, ptr noundef nonnull align 8 dereferenceable(24) %5, ptr noundef nonnull align 8 dereferenceable(24) %8, ptr noundef nonnull align 8 dereferenceable(24) %11)
          to label %70 unwind label %78

70:                                               ; preds = %67
  br i1 %69, label %71, label %.loopexit

71:                                               ; preds = %70
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %15) #6
  store i32 3, ptr %15, align 4, !tbaa !33
  %72 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIjERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4) %15, ptr noundef nonnull align 4 dereferenceable(4) %4)
  %73 = load i32, ptr %72, align 4, !tbaa !33
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %15) #6
  br i1 %.not, label %.loopexit, label %.lr.ph35

.lr.ph35:                                         ; preds = %71
  %74 = sub i32 3, %73
  %75 = zext i32 %74 to i64
  br label %80

76:                                               ; preds = %._crit_edge
  %77 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %13) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %13) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %12) #6
  br label %98

78:                                               ; preds = %67
  %79 = landingpad { ptr, i32 }
          cleanup
  br label %97

80:                                               ; preds = %.lr.ph35, %91
  %.01633 = phi i64 [ 0, %.lr.ph35 ], [ %94, %91 ]
  %81 = call noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorISt7complexIfESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %11, i64 noundef %.01633) #6
  %82 = getelementptr inbounds [8 x ptr], ptr @_ZZ4mainE4bits, i64 0, i64 %.01633
  %83 = load ptr, ptr %82, align 8, !tbaa !40
  %84 = getelementptr inbounds i8, ptr %83, i64 %75
  %85 = invoke noundef float @_ZSt4realIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %81)
          to label %86 unwind label %95

86:                                               ; preds = %80
  %87 = fpext float %85 to double
  %88 = invoke noundef float @_ZSt4imagIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %81)
          to label %89 unwind label %95

89:                                               ; preds = %86
  %90 = invoke noundef float @_ZSt4normIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8) %81)
          to label %91 unwind label %95

91:                                               ; preds = %89
  %92 = fpext float %88 to double
  %93 = fpext float %90 to double
  call void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef nonnull @.str.11, ptr noundef %84, double noundef %87, double noundef %92, double noundef %93)
  %94 = add nuw i64 %.01633, 1
  %exitcond.not = icmp eq i64 %94, %46
  br i1 %exitcond.not, label %.loopexit, label %80, !llvm.loop !41

95:                                               ; preds = %89, %86, %80
  %96 = landingpad { ptr, i32 }
          cleanup
  br label %97

.loopexit:                                        ; preds = %91, %71, %70
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %14) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %11) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %10) #6
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %8) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %5) #6
  br label %101

97:                                               ; preds = %95, %78
  %.pn = phi { ptr, i32 } [ %96, %95 ], [ %79, %78 ]
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %14) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  br label %98

98:                                               ; preds = %97, %76
  %.pn.pn = phi { ptr, i32 } [ %.pn, %97 ], [ %77, %76 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %11) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %10) #6
  br label %99

99:                                               ; preds = %98, %65, %59
  %.pn28 = phi { ptr, i32 } [ %66, %65 ], [ %.pn.pn, %98 ], [ %60, %59 ]
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %8) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  br label %100

100:                                              ; preds = %99, %39
  %.pn28.pn = phi { ptr, i32 } [ %.pn28, %99 ], [ %40, %39 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %5) #6
  br label %102

101:                                              ; preds = %31, %24, %.loopexit
  %.0 = phi i32 [ 0, %.loopexit ], [ 1, %24 ], [ 1, %31 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %103

102:                                              ; preds = %100, %25
  %.pn28.pn.pn = phi { ptr, i32 } [ %.pn28.pn, %100 ], [ %26, %25 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %104

103:                                              ; preds = %17, %101
  %.1 = phi i32 [ %.0, %101 ], [ 1, %17 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85) %3) #6
  call void @llvm.lifetime.end.p0(i64 88, ptr nonnull %3) #6
  ret i32 %.1

104:                                              ; preds = %102, %18
  %.pn28.pn.pn.pn = phi { ptr, i32 } [ %.pn28.pn.pn, %102 ], [ %19, %18 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(85) %3) #6
  call void @llvm.lifetime.end.p0(i64 88, ptr nonnull %3) #6
  resume { ptr, i32 } %.pn28.pn.pn.pn
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZSt3minImERKT_S2_S2_(ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorImSaImEE7reserveEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorImSaImEE9push_backERKm(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8), float noundef, float noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZSt3minIjERKT_S2_S2_(ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(8) ptr @_ZNSt6vectorISt7complexIfESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZSt4realIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef float @_ZSt4imagIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #0

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef float @_ZSt4normIfET_RKSt7complexIS0_E(ptr noundef nonnull align 4 dereferenceable(8)) local_unnamed_addr #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !17, i64 64}
!6 = !{!"_ZTS7Options", !7, i64 0, !13, i64 32, !12, i64 56, !17, i64 64, !17, i64 68, !17, i64 72, !17, i64 76, !17, i64 80, !18, i64 84}
!7 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !8, i64 0, !12, i64 8, !10, i64 16}
!8 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"long", !10, i64 0}
!13 = !{!"_ZTSSt6vectorIjSaIjEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!17 = !{!"int", !10, i64 0}
!18 = !{!"bool", !10, i64 0}
!19 = !{!20, !17, i64 0}
!20 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !17, i64 0, !21, i64 8}
!21 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!25 = !{!6, !18, i64 84}
!26 = !{i8 0, i8 2}
!27 = !{}
!28 = !{!12, !12, i64 0}
!29 = !{!6, !12, i64 56}
!30 = !{!31, !12, i64 8}
!31 = !{!"_ZTSN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterE", !32, i64 0, !12, i64 8, !17, i64 16, !17, i64 20, !17, i64 24}
!32 = !{!"_ZTSN4qsim14BasicGateFuserINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEES0_NS_13SequentialForEE10GateHybridEE9ParameterE", !17, i64 0}
!33 = !{!17, !17, i64 0}
!34 = !{!6, !17, i64 76}
!35 = !{!31, !17, i64 24}
!36 = !{!6, !17, i64 80}
!37 = !{!32, !17, i64 0}
!38 = distinct !{!38, !39}
!39 = !{!"llvm.loop.mustprogress"}
!40 = !{!9, !9, i64 0}
!41 = distinct !{!41, !39}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SLPVectorizerPass,SROAPass,SimplifyCFGPass