; LLVM IR from huawei-noah/bolt :: compute/tensor/src (pooling)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.PoolingParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ArchInfo = type { i32, ptr }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z25pooling_infer_output_sizeP6Tensor16PoolingParamSpecS0_P8ArchInfo(ptr noundef %0, ptr noundef byval(%struct.PoolingParamSpec) align 8 %1, ptr noundef %2, ptr noundef %3) #0 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %struct.TensorDesc, align 4
  %11 = alloca %struct.TensorDesc, align 4
  %12 = alloca %struct.TensorDesc, align 8
  %13 = alloca %struct.TensorDesc, align 4
  %14 = alloca %struct.PoolingParamSpec, align 4
  %15 = alloca %struct.TensorDesc, align 8
  %16 = alloca %struct.PoolingParamSpec, align 8
  %17 = alloca i32, align 4
  %18 = alloca %struct.TensorDesc, align 8
  %19 = alloca %struct.PoolingParamSpec, align 8
  %20 = alloca i32, align 4
  %21 = alloca %struct.TensorDesc, align 8
  store ptr %0, ptr %5, align 8, !tbaa !5
  store ptr %2, ptr %6, align 8, !tbaa !5
  store ptr %3, ptr %7, align 8, !tbaa !5
  %22 = load ptr, ptr %5, align 8, !tbaa !5
  %23 = icmp eq ptr %22, null
  br i1 %23, label %27, label %24

24:                                               ; preds = %4
  %25 = load ptr, ptr %6, align 8, !tbaa !5
  %26 = icmp eq ptr %25, null
  br i1 %26, label %27, label %43

27:                                               ; preds = %24, %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #8
  store i32 1, ptr %8, align 4, !tbaa !9
  %28 = load i32, ptr %8, align 4, !tbaa !9
  %29 = icmp ne i32 %28, 0
  br i1 %29, label %30, label %42

30:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #8
  %31 = call i64 (i64, ...) @syscall(i64 noundef 186) #8
  %32 = trunc i64 %31 to i32
  store i32 %32, ptr %9, align 4, !tbaa !11
  %33 = load i32, ptr %9, align 4, !tbaa !11
  %34 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %33)
  %35 = load ptr, ptr @stdout, align 8, !tbaa !5
  %36 = call i32 @fflush(ptr noundef %35)
  %37 = load i32, ptr %8, align 4, !tbaa !9
  %38 = call ptr @ee2str(i32 noundef %37)
  %39 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, ptr noundef %38)
  %40 = load ptr, ptr @stdout, align 8, !tbaa !5
  %41 = call i32 @fflush(ptr noundef %40)
  call void @exit(i32 noundef 1) #9
  unreachable

42:                                               ; preds = %27
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #8
  br label %43

43:                                               ; preds = %42, %24
  call void @llvm.lifetime.start.p0(i64 92, ptr %10) #8
  %44 = load ptr, ptr %5, align 8, !tbaa !5
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind writable sret(%struct.TensorDesc) align 4 %10, ptr noundef nonnull align 8 dereferenceable(32) %44)
  call void @llvm.lifetime.start.p0(i64 92, ptr %11) #8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %12, ptr align 4 %10, i64 92, i1 false), !tbaa.struct !13
  call void @_Z17transformDescTo4d10TensorDesc(ptr dead_on_unwind writable sret(%struct.TensorDesc) align 4 %11, ptr noundef byval(%struct.TensorDesc) align 8 %12)
  call void @llvm.lifetime.start.p0(i64 92, ptr %13) #8
  %45 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind writable sret(%struct.TensorDesc) align 4 %13, ptr noundef nonnull align 8 dereferenceable(32) %45)
  call void @llvm.lifetime.start.p0(i64 60, ptr %14) #8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %15, ptr align 4 %11, i64 92, i1 false), !tbaa.struct !13
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %16, ptr align 8 %1, i64 60, i1 false), !tbaa.struct !19
  call void @_ZL12update_param10TensorDesc16PoolingParamSpec(ptr dead_on_unwind writable sret(%struct.PoolingParamSpec) align 4 %14, ptr noundef byval(%struct.TensorDesc) align 8 %15, ptr noundef byval(%struct.PoolingParamSpec) align 8 %16)
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %1, ptr align 4 %14, i64 60, i1 false), !tbaa.struct !19
  call void @llvm.lifetime.end.p0(i64 60, ptr %14) #8
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #8
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %18, ptr align 4 %10, i64 92, i1 false), !tbaa.struct !13
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %19, ptr align 8 %1, i64 60, i1 false), !tbaa.struct !19
  %46 = call noundef i32 @_Z29pooling_infer_output_size_cpu10TensorDesc16PoolingParamSpecPS_(ptr noundef byval(%struct.TensorDesc) align 8 %18, ptr noundef byval(%struct.PoolingParamSpec) align 8 %19, ptr noundef %13)
  store i32 %46, ptr %17, align 4, !tbaa !9
  %47 = load i32, ptr %17, align 4, !tbaa !9
  %48 = icmp ne i32 %47, 0
  br i1 %48, label %49, label %61

49:                                               ; preds = %43
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #8
  %50 = call i64 (i64, ...) @syscall(i64 noundef 186) #8
  %51 = trunc i64 %50 to i32
  store i32 %51, ptr %20, align 4, !tbaa !11
  %52 = load i32, ptr %20, align 4, !tbaa !11
  %53 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %52)
  %54 = load ptr, ptr @stdout, align 8, !tbaa !5
  %55 = call i32 @fflush(ptr noundef %54)
  %56 = load i32, ptr %17, align 4, !tbaa !9
  %57 = call ptr @ee2str(i32 noundef %56)
  %58 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, ptr noundef %57)
  %59 = load ptr, ptr @stdout, align 8, !tbaa !5
  %60 = call i32 @fflush(ptr noundef %59)
  call void @exit(i32 noundef 1) #9
  unreachable

61:                                               ; preds = %43
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #8
  %62 = load ptr, ptr %7, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.ArchInfo, ptr %62, i32 0, i32 0
  %64 = load i32, ptr %63, align 8, !tbaa !26
  %65 = icmp eq i32 %64, 2
  br i1 %65, label %71, label %66

66:                                               ; preds = %61
  %67 = load ptr, ptr %7, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.ArchInfo, ptr %67, i32 0, i32 0
  %69 = load i32, ptr %68, align 8, !tbaa !26
  %70 = icmp eq i32 %69, 7
  br i1 %70, label %71, label %72

71:                                               ; preds = %66, %61
  br label %72

72:                                               ; preds = %71, %66
  %73 = load ptr, ptr %6, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %21, ptr align 4 %13, i64 92, i1 false), !tbaa.struct !13
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %73, ptr noundef byval(%struct.TensorDesc) align 8 %21)
  call void @llvm.lifetime.end.p0(i64 92, ptr %13) #8
  call void @llvm.lifetime.end.p0(i64 92, ptr %11) #8
  call void @llvm.lifetime.end.p0(i64 92, ptr %10) #8
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) #2

declare i32 @printf(ptr noundef, ...) #3

declare i32 @fflush(ptr noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) #4

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) #5

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z17transformDescTo4d10TensorDesc(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef byval(%struct.TensorDesc) align 8) #6

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #7

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZL12update_param10TensorDesc16PoolingParamSpec(ptr dead_on_unwind noalias writable sret(%struct.PoolingParamSpec) align 4, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.PoolingParamSpec) align 8) #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z29pooling_infer_output_size_cpu10TensorDesc16PoolingParamSpecPS_(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.PoolingParamSpec) align 8, ptr noundef) #6

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #8 = { nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS2EE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{i64 0, i64 4, !14, i64 4, i64 4, !16, i64 8, i64 4, !11, i64 12, i64 80, !18}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS8DataType", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"_ZTS10DataFormat", !7, i64 0}
!18 = !{!7, !7, i64 0}
!19 = !{i64 0, i64 4, !11, i64 4, i64 4, !11, i64 8, i64 4, !11, i64 12, i64 4, !11, i64 16, i64 4, !11, i64 20, i64 4, !11, i64 24, i64 4, !11, i64 28, i64 4, !11, i64 32, i64 4, !11, i64 36, i64 4, !11, i64 40, i64 4, !11, i64 44, i64 4, !11, i64 48, i64 4, !20, i64 52, i64 4, !22, i64 56, i64 1, !24}
!20 = !{!21, !21, i64 0}
!21 = !{!"_ZTS9RoundMode", !7, i64 0}
!22 = !{!23, !23, i64 0}
!23 = !{!"_ZTS11PoolingMode", !7, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"bool", !7, i64 0}
!26 = !{!27, !28, i64 0}
!27 = !{!"_ZTS8ArchInfo", !28, i64 0, !6, i64 8}
!28 = !{!"_ZTS4Arch", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.PoolingParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8 }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external local_unnamed_addr global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z25pooling_infer_output_sizeP6Tensor16PoolingParamSpecS0_P8ArchInfo(ptr noundef %0, ptr nocapture noundef byval(%struct.PoolingParamSpec) align 8 %1, ptr noundef %2, ptr nocapture noundef readnone %3) local_unnamed_addr #0 {
  %5 = alloca %struct.TensorDesc, align 8
  %6 = alloca %struct.TensorDesc, align 8
  %7 = alloca %struct.TensorDesc, align 8
  %8 = alloca %struct.PoolingParamSpec, align 8
  %9 = icmp eq ptr %0, null
  %10 = icmp eq ptr %2, null
  %or.cond = or i1 %9, %10
  br i1 %or.cond, label %11, label %21

11:                                               ; preds = %4
  %12 = tail call i64 (i64, ...) @syscall(i64 noundef 186) #8
  %13 = trunc i64 %12 to i32
  %14 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %13)
  %15 = load ptr, ptr @stdout, align 8, !tbaa !5
  %16 = tail call i32 @fflush(ptr noundef %15)
  %17 = tail call ptr @ee2str(i32 noundef 1)
  %18 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.1, ptr noundef %17)
  %19 = load ptr, ptr @stdout, align 8, !tbaa !5
  %20 = tail call i32 @fflush(ptr noundef %19)
  tail call void @exit(i32 noundef 1) #9
  unreachable

21:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 92, ptr nonnull %5) #8
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind nonnull writable sret(%struct.TensorDesc) align 4 %5, ptr noundef nonnull align 8 dereferenceable(32) %0)
  call void @llvm.lifetime.start.p0(i64 92, ptr nonnull %6) #8
  call void @_Z17transformDescTo4d10TensorDesc(ptr dead_on_unwind nonnull writable sret(%struct.TensorDesc) align 4 %6, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %5)
  call void @llvm.lifetime.start.p0(i64 92, ptr nonnull %7) #8
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind nonnull writable sret(%struct.TensorDesc) align 4 %7, ptr noundef nonnull align 8 dereferenceable(32) %2)
  call void @llvm.lifetime.start.p0(i64 60, ptr nonnull %8) #8
  call void @_ZL12update_param10TensorDesc16PoolingParamSpec(ptr dead_on_unwind nonnull writable sret(%struct.PoolingParamSpec) align 4 %8, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %6, ptr noundef nonnull byval(%struct.PoolingParamSpec) align 8 %1)
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(60) %1, ptr noundef nonnull align 8 dereferenceable(60) %8, i64 60, i1 false), !tbaa.struct !9
  call void @llvm.lifetime.end.p0(i64 60, ptr nonnull %8) #8
  %22 = call noundef i32 @_Z29pooling_infer_output_size_cpu10TensorDesc16PoolingParamSpecPS_(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %5, ptr noundef nonnull byval(%struct.PoolingParamSpec) align 8 %1, ptr noundef nonnull %7)
  %.not = icmp eq i32 %22, 0
  br i1 %.not, label %33, label %23

23:                                               ; preds = %21
  %24 = call i64 (i64, ...) @syscall(i64 noundef 186) #8
  %25 = trunc i64 %24 to i32
  %26 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %25)
  %27 = load ptr, ptr @stdout, align 8, !tbaa !5
  %28 = call i32 @fflush(ptr noundef %27)
  %29 = call ptr @ee2str(i32 noundef %22)
  %30 = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.1, ptr noundef %29)
  %31 = load ptr, ptr @stdout, align 8, !tbaa !5
  %32 = call i32 @fflush(ptr noundef %31)
  call void @exit(i32 noundef 1) #9
  unreachable

33:                                               ; preds = %21
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %7)
  call void @llvm.lifetime.end.p0(i64 92, ptr nonnull %7) #8
  call void @llvm.lifetime.end.p0(i64 92, ptr nonnull %6) #8
  call void @llvm.lifetime.end.p0(i64 92, ptr nonnull %5) #8
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) local_unnamed_addr #2

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: nofree nounwind
declare noundef i32 @fflush(ptr nocapture noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) local_unnamed_addr #4

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) local_unnamed_addr #5

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z17transformDescTo4d10TensorDesc(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #6

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #7

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZL12update_param10TensorDesc16PoolingParamSpec(ptr dead_on_unwind noalias writable sret(%struct.PoolingParamSpec) align 4, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.PoolingParamSpec) align 8) local_unnamed_addr #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z29pooling_infer_output_size_cpu10TensorDesc16PoolingParamSpecPS_(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.PoolingParamSpec) align 8, ptr noundef) local_unnamed_addr #6

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #8 = { nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i64 0, i64 4, !10, i64 4, i64 4, !10, i64 8, i64 4, !10, i64 12, i64 4, !10, i64 16, i64 4, !10, i64 20, i64 4, !10, i64 24, i64 4, !10, i64 28, i64 4, !10, i64 32, i64 4, !10, i64 36, i64 4, !10, i64 40, i64 4, !10, i64 44, i64 4, !10, i64 48, i64 4, !12, i64 52, i64 4, !14, i64 56, i64 1, !16}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"_ZTS9RoundMode", !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS11PoolingMode", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"bool", !7, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass