; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis6 (VariableDatum)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::VariableDatum" = type <{ ptr, i32, i32, %"class.std::vector", i32, [4 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl" = type { %"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" }
%"struct.std::_Vector_base<char, std::allocator<char>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIcSaIcEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3DIS13VariableDatum9unmarshalERNS_10DataStreamE(ptr noundef nonnull align 8 dereferenceable(44) %0, ptr noundef nonnull align 8 dereferenceable(48) %1) unnamed_addr #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %9 = load ptr, ptr %3, align 8
  %10 = load ptr, ptr %4, align 8, !tbaa !5
  %11 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 1
  %12 = call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48) %10, ptr noundef nonnull align 4 dereferenceable(4) %11)
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 2
  %15 = call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48) %13, ptr noundef nonnull align 4 dereferenceable(4) %14)
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #4
  %16 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 2
  %17 = load i32, ptr %16, align 4, !tbaa !9
  %18 = udiv i32 %17, 8
  store i32 %18, ptr %5, align 4, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #4
  %19 = load i32, ptr %5, align 4, !tbaa !16
  %20 = sdiv i32 %19, 8
  store i32 %20, ptr %6, align 4, !tbaa !16
  %21 = load i32, ptr %5, align 4, !tbaa !16
  %22 = srem i32 %21, 8
  %23 = icmp sgt i32 %22, 0
  br i1 %23, label %24, label %27

24:                                               ; preds = %2
  %25 = load i32, ptr %6, align 4, !tbaa !16
  %26 = add nsw i32 %25, 1
  store i32 %26, ptr %6, align 4, !tbaa !16
  br label %27

27:                                               ; preds = %24, %2
  %28 = load i32, ptr %6, align 4, !tbaa !16
  %29 = mul nsw i32 %28, 8
  %30 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 4
  store i32 %29, ptr %30, align 8, !tbaa !17
  %31 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 3
  %32 = call noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %31) #4
  %33 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 4
  %34 = load i32, ptr %33, align 8, !tbaa !17
  %35 = zext i32 %34 to i64
  %36 = icmp ult i64 %32, %35
  br i1 %36, label %37, label %42

37:                                               ; preds = %27
  %38 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 3
  %39 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 4
  %40 = load i32, ptr %39, align 8, !tbaa !17
  %41 = zext i32 %40 to i64
  call void @_ZNSt6vectorIcSaIcEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %41)
  br label %42

42:                                               ; preds = %37, %27
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #4
  store i32 0, ptr %7, align 4, !tbaa !16
  br label %43

43:                                               ; preds = %56, %42
  %44 = load i32, ptr %7, align 4, !tbaa !16
  %45 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 4
  %46 = load i32, ptr %45, align 8, !tbaa !17
  %47 = icmp ult i32 %44, %46
  br i1 %47, label %49, label %48

48:                                               ; preds = %43
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #4
  br label %59

49:                                               ; preds = %43
  %50 = load ptr, ptr %4, align 8, !tbaa !5
  %51 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 3
  %52 = load i32, ptr %7, align 4, !tbaa !16
  %53 = zext i32 %52 to i64
  %54 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %51, i64 noundef %53) #4
  %55 = call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERc(ptr noundef nonnull align 8 dereferenceable(48) %50, ptr noundef nonnull align 1 dereferenceable(1) %54)
  br label %56

56:                                               ; preds = %49
  %57 = load i32, ptr %7, align 4, !tbaa !16
  %58 = add i32 %57, 1
  store i32 %58, ptr %7, align 4, !tbaa !16
  br label %43, !llvm.loop !18

59:                                               ; preds = %48
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #4
  %60 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 4
  %61 = load i32, ptr %60, align 8, !tbaa !17
  %62 = zext i32 %61 to i64
  store i64 %62, ptr %8, align 8, !tbaa !20
  br label %63

63:                                               ; preds = %73, %59
  %64 = load i64, ptr %8, align 8, !tbaa !20
  %65 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 3
  %66 = call noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %65) #4
  %67 = icmp ult i64 %64, %66
  br i1 %67, label %69, label %68

68:                                               ; preds = %63
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #4
  br label %76

69:                                               ; preds = %63
  %70 = getelementptr inbounds %"class.DIS::VariableDatum", ptr %9, i32 0, i32 3
  %71 = load i64, ptr %8, align 8, !tbaa !20
  %72 = call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %70, i64 noundef %71) #4
  store i8 0, ptr %72, align 1, !tbaa !22
  br label %73

73:                                               ; preds = %69
  %74 = load i64, ptr %8, align 8, !tbaa !20
  %75 = add i64 %74, 1
  store i64 %75, ptr %8, align 8, !tbaa !20
  br label %63, !llvm.loop !23

76:                                               ; preds = %68
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #4
  ret void
}

declare noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef nonnull align 4 dereferenceable(4)) #3

declare noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERc(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef nonnull align 1 dereferenceable(1)) #3

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 12}
!10 = !{!"_ZTSN3DIS13VariableDatumE", !11, i64 8, !11, i64 12, !12, i64 16, !11, i64 40}
!11 = !{!"int", !7, i64 0}
!12 = !{!"_ZTSSt6vectorIcSaIcEE", !13, i64 0}
!13 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!16 = !{!11, !11, i64 0}
!17 = !{!10, !11, i64 40}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = !{!21, !21, i64 0}
!21 = !{!"long long", !7, i64 0}
!22 = !{!7, !7, i64 0}
!23 = distinct !{!23, !19}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIcSaIcEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN3DIS13VariableDatum9unmarshalERNS_10DataStreamE(ptr noundef nonnull align 8 dereferenceable(44) %0, ptr noundef nonnull align 8 dereferenceable(48) %1) unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = tail call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48) %1, ptr noundef nonnull align 4 dereferenceable(4) %3)
  %5 = getelementptr inbounds i8, ptr %0, i64 12
  %6 = tail call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48) %1, ptr noundef nonnull align 4 dereferenceable(4) %5)
  %7 = load i32, ptr %5, align 4, !tbaa !5
  %8 = lshr i32 %7, 6
  %9 = and i32 %7, 56
  %.not = icmp ne i32 %9, 0
  %10 = zext i1 %.not to i32
  %spec.select = add nuw nsw i32 %8, %10
  %11 = shl nuw nsw i32 %spec.select, 3
  %12 = getelementptr inbounds i8, ptr %0, i64 40
  store i32 %11, ptr %12, align 8, !tbaa !15
  %13 = getelementptr inbounds i8, ptr %0, i64 16
  %14 = tail call noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  %15 = load i32, ptr %12, align 8, !tbaa !15
  %16 = zext i32 %15 to i64
  %17 = icmp ult i64 %14, %16
  br i1 %17, label %18, label %19

18:                                               ; preds = %2
  tail call void @_ZNSt6vectorIcSaIcEE6resizeEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %16)
  %.pre = load i32, ptr %12, align 8, !tbaa !15
  br label %19

19:                                               ; preds = %18, %2
  %20 = phi i32 [ %.pre, %18 ], [ %15, %2 ]
  %.not22 = icmp eq i32 %20, 0
  br i1 %.not22, label %._crit_edge, label %.lr.ph

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %21 = zext i32 %26 to i64
  br label %._crit_edge

._crit_edge:                                      ; preds = %19, %._crit_edge.loopexit
  %.lcssa = phi i64 [ %21, %._crit_edge.loopexit ], [ 0, %19 ]
  %22 = tail call noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  %23 = icmp ugt i64 %22, %.lcssa
  br i1 %23, label %.lr.ph20, label %._crit_edge21

.lr.ph:                                           ; preds = %19, %.lr.ph
  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %19 ]
  %24 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %indvars.iv) #3
  %25 = tail call noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERc(ptr noundef nonnull align 8 dereferenceable(48) %1, ptr noundef nonnull align 1 dereferenceable(1) %24)
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %26 = load i32, ptr %12, align 8, !tbaa !15
  %27 = zext i32 %26 to i64
  %28 = icmp ult i64 %indvars.iv.next, %27
  br i1 %28, label %.lr.ph, label %._crit_edge.loopexit, !llvm.loop !16

._crit_edge21:                                    ; preds = %.lr.ph20, %._crit_edge
  ret void

.lr.ph20:                                         ; preds = %._crit_edge, %.lr.ph20
  %.018 = phi i64 [ %30, %.lr.ph20 ], [ %.lcssa, %._crit_edge ]
  %29 = tail call noundef nonnull align 1 dereferenceable(1) ptr @_ZNSt6vectorIcSaIcEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %.018) #3
  store i8 0, ptr %29, align 1, !tbaa !18
  %30 = add nuw i64 %.018, 1
  %31 = tail call noundef i64 @_ZNKSt6vectorIcSaIcEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #3
  %32 = icmp ult i64 %30, %31
  br i1 %32, label %.lr.ph20, label %._crit_edge21, !llvm.loop !19
}

declare noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERj(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #2

declare noundef nonnull align 8 dereferenceable(48) ptr @_ZN3DIS10DataStreamrsERc(ptr noundef nonnull align 8 dereferenceable(48), ptr noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 12}
!6 = !{!"_ZTSN3DIS13VariableDatumE", !7, i64 8, !7, i64 12, !10, i64 16, !7, i64 40}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIcSaIcEE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIcSaIcEE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIcSaIcEE17_Vector_impl_dataE", !14, i64 0, !14, i64 8, !14, i64 16}
!14 = !{!"any pointer", !8, i64 0}
!15 = !{!6, !7, i64 40}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = !{!8, !8, i64 0}
!19 = distinct !{!19, !17}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass