; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/pcuda (pcuda_device_topology)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }
%"class.hipsycl::rt::pcuda::device_topology" = type { %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::backend, std::allocator<hipsycl::rt::pcuda::device_topology::backend>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::backend, std::allocator<hipsycl::rt::pcuda::device_topology::backend>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::backend, std::allocator<hipsycl::rt::pcuda::device_topology::backend>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::backend, std::allocator<hipsycl::rt::pcuda::device_topology::backend>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.hipsycl::rt::pcuda::device_topology::backend" = type { i32, i32, ptr, %"class.std::vector.36" }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.hipsycl::rt::pcuda::device_topology::platform" = type { i32, %"class.std::vector.41" }
%"class.std::vector.41" = type { %"struct.std::_Vector_base.42" }
%"struct.std::_Vector_base.42" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.hipsycl::rt::pcuda::device_topology::device" = type { i32, %"class.hipsycl::rt::device_id", ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK7hipsycl2rt5pcuda15device_topology25device_id_to_index_tripleENS0_9device_idERiS4_S4_(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 %1, i64 %2, ptr noundef nonnull align 4 dereferenceable(4) %3, ptr noundef nonnull align 4 dereferenceable(4) %4, ptr noundef nonnull align 4 dereferenceable(4) %5) #2 align 2 {
  %7 = alloca i1, align 1
  %8 = alloca %"class.hipsycl::rt::device_id", align 4
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca i32, align 4
  %16 = getelementptr inbounds { i64, i64 }, ptr %8, i32 0, i32 0
  store i64 %1, ptr %16, align 4
  %17 = getelementptr inbounds { i64, i64 }, ptr %8, i32 0, i32 1
  store i64 %2, ptr %17, align 4
  store ptr %0, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store ptr %4, ptr %11, align 8, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !5
  %18 = load ptr, ptr %9, align 8
  %19 = load ptr, ptr %10, align 8, !tbaa !5
  store i32 0, ptr %19, align 4, !tbaa !9
  br label %20

20:                                               ; preds = %94, %6
  %21 = load ptr, ptr %10, align 8, !tbaa !5
  %22 = load i32, ptr %21, align 4, !tbaa !9
  %23 = sext i32 %22 to i64
  %24 = getelementptr inbounds %"class.hipsycl::rt::pcuda::device_topology", ptr %18, i32 0, i32 0
  %25 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %24) #4
  %26 = icmp ult i64 %23, %25
  br i1 %26, label %27, label %98

27:                                               ; preds = %20
  %28 = getelementptr inbounds %"class.hipsycl::rt::pcuda::device_topology", ptr %18, i32 0, i32 0
  %29 = load ptr, ptr %10, align 8, !tbaa !5
  %30 = load i32, ptr %29, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %31) #4
  %33 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::backend", ptr %32, i32 0, i32 1
  %34 = load i32, ptr %33, align 4, !tbaa !11
  %35 = call noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16) %8)
  %36 = icmp eq i32 %34, %35
  br i1 %36, label %37, label %93

37:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #4
  %38 = getelementptr inbounds %"class.hipsycl::rt::pcuda::device_topology", ptr %18, i32 0, i32 0
  %39 = load ptr, ptr %10, align 8, !tbaa !5
  %40 = load i32, ptr %39, align 4, !tbaa !9
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %38, i64 noundef %41) #4
  %43 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::backend", ptr %42, i32 0, i32 3
  store ptr %43, ptr %13, align 8, !tbaa !5
  %44 = load ptr, ptr %11, align 8, !tbaa !5
  store i32 0, ptr %44, align 4, !tbaa !9
  br label %45

45:                                               ; preds = %85, %37
  %46 = load ptr, ptr %11, align 8, !tbaa !5
  %47 = load i32, ptr %46, align 4, !tbaa !9
  %48 = sext i32 %47 to i64
  %49 = load ptr, ptr %13, align 8, !tbaa !5
  %50 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %49) #4
  %51 = icmp ult i64 %48, %50
  br i1 %51, label %52, label %89

52:                                               ; preds = %45
  call void @llvm.lifetime.start.p0(i64 8, ptr %14) #4
  %53 = load ptr, ptr %13, align 8, !tbaa !5
  %54 = load ptr, ptr %11, align 8, !tbaa !5
  %55 = load i32, ptr %54, align 4, !tbaa !9
  %56 = sext i32 %55 to i64
  %57 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %53, i64 noundef %56) #4
  %58 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::platform", ptr %57, i32 0, i32 1
  store ptr %58, ptr %14, align 8, !tbaa !5
  %59 = load ptr, ptr %12, align 8, !tbaa !5
  store i32 0, ptr %59, align 4, !tbaa !9
  br label %60

60:                                               ; preds = %77, %52
  %61 = load ptr, ptr %12, align 8, !tbaa !5
  %62 = load i32, ptr %61, align 4, !tbaa !9
  %63 = sext i32 %62 to i64
  %64 = load ptr, ptr %14, align 8, !tbaa !5
  %65 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %64) #4
  %66 = icmp ult i64 %63, %65
  br i1 %66, label %67, label %81

67:                                               ; preds = %60
  %68 = load ptr, ptr %14, align 8, !tbaa !5
  %69 = load ptr, ptr %12, align 8, !tbaa !5
  %70 = load i32, ptr %69, align 4, !tbaa !9
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %68, i64 noundef %71) #4
  %73 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::device", ptr %72, i32 0, i32 1
  %74 = call noundef zeroext i1 @_ZN7hipsycl2rteqERKNS0_9device_idES3_(ptr noundef nonnull align 4 dereferenceable(16) %73, ptr noundef nonnull align 4 dereferenceable(16) %8)
  br i1 %74, label %75, label %76

75:                                               ; preds = %67
  store i1 true, ptr %7, align 1
  store i32 1, ptr %15, align 4
  br label %82

76:                                               ; preds = %67
  br label %77

77:                                               ; preds = %76
  %78 = load ptr, ptr %12, align 8, !tbaa !5
  %79 = load i32, ptr %78, align 4, !tbaa !9
  %80 = add nsw i32 %79, 1
  store i32 %80, ptr %78, align 4, !tbaa !9
  br label %60, !llvm.loop !18

81:                                               ; preds = %60
  store i32 0, ptr %15, align 4
  br label %82

82:                                               ; preds = %81, %75
  call void @llvm.lifetime.end.p0(i64 8, ptr %14) #4
  %83 = load i32, ptr %15, align 4
  switch i32 %83, label %90 [
    i32 0, label %84
  ]

84:                                               ; preds = %82
  br label %85

85:                                               ; preds = %84
  %86 = load ptr, ptr %11, align 8, !tbaa !5
  %87 = load i32, ptr %86, align 4, !tbaa !9
  %88 = add nsw i32 %87, 1
  store i32 %88, ptr %86, align 4, !tbaa !9
  br label %45, !llvm.loop !20

89:                                               ; preds = %45
  store i32 0, ptr %15, align 4
  br label %90

90:                                               ; preds = %89, %82
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #4
  %91 = load i32, ptr %15, align 4
  switch i32 %91, label %101 [
    i32 0, label %92
    i32 1, label %99
  ]

92:                                               ; preds = %90
  br label %93

93:                                               ; preds = %92, %27
  br label %94

94:                                               ; preds = %93
  %95 = load ptr, ptr %10, align 8, !tbaa !5
  %96 = load i32, ptr %95, align 4, !tbaa !9
  %97 = add nsw i32 %96, 1
  store i32 %97, ptr %95, align 4, !tbaa !9
  br label %20, !llvm.loop !21

98:                                               ; preds = %20
  store i1 false, ptr %7, align 1
  br label %99

99:                                               ; preds = %98, %90
  %100 = load i1, ptr %7, align 1
  ret i1 %100

101:                                              ; preds = %90
  unreachable
}

declare noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16)) #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN7hipsycl2rteqERKNS0_9device_idES3_(ptr noundef nonnull align 4 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(16)) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 4}
!12 = !{!"_ZTSN7hipsycl2rt5pcuda15device_topology7backendE", !10, i64 0, !13, i64 4, !6, i64 8, !14, i64 16}
!13 = !{!"_ZTSN7hipsycl2rt10backend_idE", !7, i64 0}
!14 = !{!"_ZTSSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = distinct !{!18, !19}
!19 = !{!"llvm.loop.mustprogress"}
!20 = distinct !{!20, !19}
!21 = distinct !{!21, !19}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK7hipsycl2rt5pcuda15device_topology25device_id_to_index_tripleENS0_9device_idERiS4_S4_(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 %1, i64 %2, ptr nocapture noundef nonnull align 4 dereferenceable(4) %3, ptr nocapture noundef nonnull align 4 dereferenceable(4) %4, ptr nocapture noundef nonnull align 4 dereferenceable(4) %5) local_unnamed_addr #1 align 2 {
  %7 = alloca %"class.hipsycl::rt::device_id", align 8
  store i64 %1, ptr %7, align 8
  %8 = getelementptr inbounds i8, ptr %7, i64 8
  store i64 %2, ptr %8, align 8
  store i32 0, ptr %3, align 4, !tbaa !5
  %9 = tail call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %.not35 = icmp eq i64 %9, 0
  br i1 %.not35, label %._crit_edge, label %.lr.ph31

.lr.ph31:                                         ; preds = %6, %.thread
  %10 = load i32, ptr %3, align 4, !tbaa !5
  %11 = sext i32 %10 to i64
  %12 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %11) #3
  %13 = getelementptr inbounds i8, ptr %12, i64 4
  %14 = load i32, ptr %13, align 4, !tbaa !9
  %15 = call noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16) %7)
  %16 = icmp eq i32 %14, %15
  br i1 %16, label %17, label %.thread

17:                                               ; preds = %.lr.ph31
  %18 = load i32, ptr %3, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %0, i64 noundef %19) #3
  %21 = getelementptr inbounds i8, ptr %20, i64 16
  store i32 0, ptr %4, align 4, !tbaa !5
  %22 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #3
  %.not2528.not = icmp eq i64 %22, 0
  br i1 %.not2528.not, label %.thread, label %.lr.ph30

.lr.ph30:                                         ; preds = %17, %.critedge
  %23 = load i32, ptr %4, align 4, !tbaa !5
  %24 = sext i32 %23 to i64
  %25 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %21, i64 noundef %24) #3
  %26 = getelementptr inbounds i8, ptr %25, i64 8
  store i32 0, ptr %5, align 4, !tbaa !5
  %27 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %.not27.not = icmp eq i64 %27, 0
  br i1 %.not27.not, label %.critedge, label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph30, %33
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = sext i32 %28 to i64
  %30 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %29) #3
  %31 = getelementptr inbounds i8, ptr %30, i64 4
  %32 = call noundef zeroext i1 @_ZN7hipsycl2rteqERKNS0_9device_idES3_(ptr noundef nonnull align 4 dereferenceable(16) %31, ptr noundef nonnull align 4 dereferenceable(16) %7)
  br i1 %32, label %._crit_edge, label %33

33:                                               ; preds = %.lr.ph
  %34 = load i32, ptr %5, align 4, !tbaa !5
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %5, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %.not = icmp ugt i64 %37, %36
  br i1 %.not, label %.lr.ph, label %.critedge, !llvm.loop !17

.critedge:                                        ; preds = %33, %.lr.ph30
  %38 = load i32, ptr %4, align 4, !tbaa !5
  %39 = add nsw i32 %38, 1
  store i32 %39, ptr %4, align 4, !tbaa !5
  %40 = sext i32 %39 to i64
  %41 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %21) #3
  %.not25 = icmp ugt i64 %41, %40
  br i1 %.not25, label %.lr.ph30, label %.thread, !llvm.loop !19

.thread:                                          ; preds = %.critedge, %17, %.lr.ph31
  %42 = load i32, ptr %3, align 4, !tbaa !5
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %3, align 4, !tbaa !5
  %44 = sext i32 %43 to i64
  %45 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %0) #3
  %46 = icmp ugt i64 %45, %44
  br i1 %46, label %.lr.ph31, label %._crit_edge, !llvm.loop !20

._crit_edge:                                      ; preds = %.thread, %.lr.ph, %6
  %.lcssa = phi i1 [ false, %6 ], [ true, %.lr.ph ], [ false, %.thread ]
  ret i1 %.lcssa
}

declare noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16)) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN7hipsycl2rteqERKNS0_9device_idES3_(ptr noundef nonnull align 4 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(16)) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 4}
!10 = !{!"_ZTSN7hipsycl2rt5pcuda15device_topology7backendE", !6, i64 0, !11, i64 4, !12, i64 8, !13, i64 16}
!11 = !{!"_ZTSN7hipsycl2rt10backend_idE", !7, i64 0}
!12 = !{!"any pointer", !7, i64 0}
!13 = !{!"_ZTSSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}
!20 = distinct !{!20, !18}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LCSSAPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass