; LLVM IR from quantumlib/qsim :: apps (qsim_base)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.qsim::StateSpaceBasic" = type { i8 }
%struct.Factory = type { i32 }
%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector" = type <{ %"class.std::unique_ptr", i32, [4 x i8] }>
%"class.std::unique_ptr" = type { %"struct.std::__uniq_ptr_data" }
%"struct.std::__uniq_ptr_data" = type { %"class.std::__uniq_ptr_impl" }
%"class.std::__uniq_ptr_impl" = type { %"class.std::tuple" }
%"class.std::tuple" = type { %"struct.std::_Tuple_impl" }
%"struct.std::_Tuple_impl" = type { %"struct.std::_Tuple_impl.3", %"struct.std::_Head_base.4" }
%"struct.std::_Tuple_impl.3" = type { %"struct.std::_Head_base" }
%"struct.std::_Head_base" = type { ptr }
%"struct.std::_Head_base.4" = type { ptr }
%"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter" = type { %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", i64 }
%"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter" = type { i32, i32 }

@.str.2 = external hidden unnamed_addr constant [55 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO6errorfEPKcz(ptr noundef, ...) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(53)) #0

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main(i32 noundef %0, ptr noundef %1) #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca %struct.Options, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %"struct.qsim::Circuit", align 8
  %11 = alloca %"class.qsim::StateSpaceBasic", align 1
  %12 = alloca %struct.Factory, align 4
  %13 = alloca %"class.qsim::StateSpaceBasic", align 1
  %14 = alloca %"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector", align 8
  %15 = alloca %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", align 8
  %16 = alloca %struct.Factory, align 4
  store i32 0, ptr %3, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 56, ptr %6) #6
  %17 = load i32, ptr %4, align 4, !tbaa !5
  %18 = load ptr, ptr %5, align 8, !tbaa !9
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind writable sret(%struct.Options) align 8 %6, i32 noundef %17, ptr noundef %18)
  %19 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(53) %6)
          to label %20 unwind label %22

20:                                               ; preds = %2
  br i1 %19, label %26, label %21

21:                                               ; preds = %20
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %104

22:                                               ; preds = %2
  %23 = landingpad { ptr, i32 }
          cleanup
  %24 = extractvalue { ptr, i32 } %23, 0
  store ptr %24, ptr %7, align 8
  %25 = extractvalue { ptr, i32 } %23, 1
  store i32 %25, ptr %8, align 4
  br label %106

26:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 32, ptr %10) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  %27 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  %28 = load i32, ptr %27, align 8, !tbaa !11
  %29 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 0
  %30 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %28, ptr noundef nonnull align 8 dereferenceable(32) %29, ptr noundef nonnull align 8 dereferenceable(32) %10)
          to label %31 unwind label %33

31:                                               ; preds = %26
  br i1 %30, label %37, label %32

32:                                               ; preds = %31
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %102

33:                                               ; preds = %41, %26
  %34 = landingpad { ptr, i32 }
          cleanup
  %35 = extractvalue { ptr, i32 } %34, 0
  store ptr %35, ptr %7, align 8
  %36 = extractvalue { ptr, i32 } %34, 1
  store i32 %36, ptr %8, align 4
  br label %103

37:                                               ; preds = %31
  %38 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 6
  %39 = load i8, ptr %38, align 4, !tbaa !17, !range !18, !noundef !19
  %40 = trunc i8 %39 to i1
  br i1 %40, label %41, label %43

41:                                               ; preds = %37
  invoke void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
          to label %42 unwind label %33

42:                                               ; preds = %41
  br label %43

43:                                               ; preds = %42, %37
  call void @llvm.lifetime.start.p0(i64 1, ptr %11) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #6
  %44 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 3
  %45 = load i32, ptr %44, align 8, !tbaa !20
  invoke void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %12, i32 noundef %45)
          to label %46 unwind label %55

46:                                               ; preds = %43
  invoke void @_ZZ4mainENK7Factory16CreateStateSpaceEv(ptr noundef nonnull align 4 dereferenceable(4) %12)
          to label %47 unwind label %55

47:                                               ; preds = %46
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #6
  call void @llvm.lifetime.start.p0(i64 24, ptr %14) #6
  %48 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %49 = load i32, ptr %48, align 8, !tbaa !21
  invoke void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6CreateEj(ptr dead_on_unwind writable sret(%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector") align 8 %14, i32 noundef %49)
          to label %50 unwind label %59

50:                                               ; preds = %47
  %51 = invoke noundef zeroext i1 @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6IsNullERKNS4_6VectorE(ptr noundef nonnull align 8 dereferenceable(20) %14)
          to label %52 unwind label %63

52:                                               ; preds = %50
  br i1 %51, label %53, label %67

53:                                               ; preds = %52
  invoke void (ptr, ...) @_ZN4qsim2IO6errorfEPKcz(ptr noundef @.str.2)
          to label %54 unwind label %63

54:                                               ; preds = %53
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %98

55:                                               ; preds = %46, %43
  %56 = landingpad { ptr, i32 }
          cleanup
  %57 = extractvalue { ptr, i32 } %56, 0
  store ptr %57, ptr %7, align 8
  %58 = extractvalue { ptr, i32 } %56, 1
  store i32 %58, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #6
  br label %101

59:                                               ; preds = %47
  %60 = landingpad { ptr, i32 }
          cleanup
  %61 = extractvalue { ptr, i32 } %60, 0
  store ptr %61, ptr %7, align 8
  %62 = extractvalue { ptr, i32 } %60, 1
  store i32 %62, ptr %8, align 4
  br label %100

63:                                               ; preds = %67, %53, %50
  %64 = landingpad { ptr, i32 }
          cleanup
  %65 = extractvalue { ptr, i32 } %64, 0
  store ptr %65, ptr %7, align 8
  %66 = extractvalue { ptr, i32 } %64, 1
  store i32 %66, ptr %8, align 4
  br label %99

67:                                               ; preds = %52
  invoke void @_ZNK4qsim15StateSpaceBasicINS_13SequentialForEfE12SetStateZeroERNS_11VectorSpaceIS2_S1_fE6VectorE(ptr noundef nonnull align 1 dereferenceable(1) %11, ptr noundef nonnull align 8 dereferenceable(20) %14)
          to label %68 unwind label %63

68:                                               ; preds = %67
  call void @llvm.lifetime.start.p0(i64 16, ptr %15) #6
  call void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16) %15) #6
  %69 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 4
  %70 = load i32, ptr %69, align 4, !tbaa !27
  %71 = getelementptr inbounds %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", ptr %15, i32 0, i32 0
  store i32 %70, ptr %71, align 8, !tbaa !28
  %72 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 2
  %73 = load i32, ptr %72, align 4, !tbaa !30
  %74 = zext i32 %73 to i64
  %75 = getelementptr inbounds %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", ptr %15, i32 0, i32 1
  store i64 %74, ptr %75, align 8, !tbaa !31
  %76 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 5
  %77 = load i32, ptr %76, align 8, !tbaa !33
  %78 = getelementptr inbounds %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", ptr %15, i32 0, i32 1
  store i32 %77, ptr %78, align 4, !tbaa !34
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #6
  %79 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 3
  %80 = load i32, ptr %79, align 8, !tbaa !20
  invoke void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %16, i32 noundef %80)
          to label %81 unwind label %88

81:                                               ; preds = %68
  %82 = invoke noundef zeroext i1 @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEEEbRKNSA_9ParameterERKS7_RKT_RNS_11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEESO_fE6VectorE(ptr noundef nonnull align 8 dereferenceable(16) %15, ptr noundef nonnull align 4 dereferenceable(4) %16, ptr noundef nonnull align 8 dereferenceable(32) %10, ptr noundef nonnull align 8 dereferenceable(20) %14)
          to label %83 unwind label %88

83:                                               ; preds = %81
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #6
  br i1 %82, label %84, label %96

84:                                               ; preds = %83
  %85 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %86 = load i32, ptr %85, align 8, !tbaa !21
  invoke void @_Z15PrintAmplitudesIN4qsim15StateSpaceBasicINS0_13SequentialForEfEENS0_11VectorSpaceIS3_S2_fE6VectorEEvjRKT_RKT0_(i32 noundef %86, ptr noundef nonnull align 1 dereferenceable(1) %11, ptr noundef nonnull align 8 dereferenceable(20) %14)
          to label %87 unwind label %92

87:                                               ; preds = %84
  br label %96

88:                                               ; preds = %81, %68
  %89 = landingpad { ptr, i32 }
          cleanup
  %90 = extractvalue { ptr, i32 } %89, 0
  store ptr %90, ptr %7, align 8
  %91 = extractvalue { ptr, i32 } %89, 1
  store i32 %91, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #6
  br label %97

92:                                               ; preds = %84
  %93 = landingpad { ptr, i32 }
          cleanup
  %94 = extractvalue { ptr, i32 } %93, 0
  store ptr %94, ptr %7, align 8
  %95 = extractvalue { ptr, i32 } %93, 1
  store i32 %95, ptr %8, align 4
  br label %97

96:                                               ; preds = %87, %83
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 16, ptr %15) #6
  br label %98

97:                                               ; preds = %92, %88
  call void @llvm.lifetime.end.p0(i64 16, ptr %15) #6
  br label %99

98:                                               ; preds = %96, %54
  call void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20) %14) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %14) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #6
  br label %102

99:                                               ; preds = %97, %63
  call void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20) %14) #6
  br label %100

100:                                              ; preds = %99, %59
  call void @llvm.lifetime.end.p0(i64 24, ptr %14) #6
  br label %101

101:                                              ; preds = %100, %55
  call void @llvm.lifetime.end.p0(i64 1, ptr %11) #6
  br label %103

102:                                              ; preds = %98, %32
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %104

103:                                              ; preds = %101, %33
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %106

104:                                              ; preds = %102, %21
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53) %6) #6
  call void @llvm.lifetime.end.p0(i64 56, ptr %6) #6
  %105 = load i32, ptr %3, align 4
  ret i32 %105

106:                                              ; preds = %103, %22
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53) %6) #6
  call void @llvm.lifetime.end.p0(i64 56, ptr %6) #6
  br label %107

107:                                              ; preds = %106
  %108 = load ptr, ptr %7, align 8
  %109 = load i32, ptr %8, align 4
  %110 = insertvalue { ptr, i32 } poison, ptr %108, 0
  %111 = insertvalue { ptr, i32 } %110, i32 %109, 1
  resume { ptr, i32 } %111
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() #3

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare hidden void @_ZZ4mainENK7Factory16CreateStateSpaceEv(ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6CreateEj(ptr dead_on_unwind noalias writable sret(%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector") align 8, i32 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6IsNullERKNS4_6VectorE(ptr noundef nonnull align 8 dereferenceable(20)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK4qsim15StateSpaceBasicINS_13SequentialForEfE12SetStateZeroERNS_11VectorSpaceIS2_S1_fE6VectorE(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 8 dereferenceable(20)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEEEbRKNSA_9ParameterERKS7_RKT_RNS_11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEESO_fE6VectorE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(20)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z15PrintAmplitudesIN4qsim15StateSpaceBasicINS0_13SequentialForEfEENS0_11VectorSpaceIS3_S2_fE6VectorEEvjRKT_RKT0_(i32 noundef, ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 8 dereferenceable(20)) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !6, i64 32}
!12 = !{!"_ZTS7Options", !13, i64 0, !6, i64 32, !6, i64 36, !6, i64 40, !6, i64 44, !6, i64 48, !16, i64 52}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"bool", !7, i64 0}
!17 = !{!12, !16, i64 52}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = !{!12, !6, i64 40}
!21 = !{!22, !6, i64 0}
!22 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !6, i64 0, !23, i64 8}
!23 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!27 = !{!12, !6, i64 44}
!28 = !{!29, !6, i64 0}
!29 = !{!"_ZTSN4qsim19MultiQubitGateFuserINS_2IOENS_4GateIfNS_8GateKindEEEE9ParameterE", !6, i64 0, !6, i64 4}
!30 = !{!12, !6, i64 36}
!31 = !{!32, !15, i64 8}
!32 = !{!"_ZTSN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterE", !29, i64 0, !15, i64 8}
!33 = !{!12, !6, i64 48}
!34 = !{!29, !6, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.qsim::StateSpaceBasic" = type { i8 }
%struct.Factory = type { i32 }
%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector" = type <{ %"class.std::unique_ptr", i32, [4 x i8] }>
%"class.std::unique_ptr" = type { %"struct.std::__uniq_ptr_data" }
%"struct.std::__uniq_ptr_data" = type { %"class.std::__uniq_ptr_impl" }
%"class.std::__uniq_ptr_impl" = type { %"class.std::tuple" }
%"class.std::tuple" = type { %"struct.std::_Tuple_impl" }
%"struct.std::_Tuple_impl" = type { %"struct.std::_Tuple_impl.3", %"struct.std::_Head_base.4" }
%"struct.std::_Tuple_impl.3" = type { %"struct.std::_Head_base" }
%"struct.std::_Head_base" = type { ptr }
%"struct.std::_Head_base.4" = type { ptr }
%"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter" = type { %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", i64 }
%"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter" = type { i32, i32 }

@.str.2 = external hidden unnamed_addr constant [55 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO6errorfEPKcz(ptr noundef, ...) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(53)) local_unnamed_addr #0

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef range(i32 0, 2) i32 @main(i32 noundef %0, ptr noundef %1) local_unnamed_addr #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca %struct.Options, align 8
  %4 = alloca %"struct.qsim::Circuit", align 8
  %5 = alloca %"class.qsim::StateSpaceBasic", align 1
  %6 = alloca %struct.Factory, align 4
  %7 = alloca %"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector", align 8
  %8 = alloca %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", align 8
  %9 = alloca %struct.Factory, align 4
  call void @llvm.lifetime.start.p0(i64 56, ptr nonnull %3) #6
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind nonnull writable sret(%struct.Options) align 8 %3, i32 noundef %0, ptr noundef %1)
  %10 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(53) %3)
          to label %11 unwind label %12

11:                                               ; preds = %2
  br i1 %10, label %14, label %66

12:                                               ; preds = %2
  %13 = landingpad { ptr, i32 }
          cleanup
  br label %67

14:                                               ; preds = %11
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %4) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  %15 = getelementptr inbounds i8, ptr %3, i64 32
  %16 = load i32, ptr %15, align 8, !tbaa !5
  %17 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %16, ptr noundef nonnull align 8 dereferenceable(32) %3, ptr noundef nonnull align 8 dereferenceable(32) %4)
          to label %18 unwind label %19

18:                                               ; preds = %14
  br i1 %17, label %21, label %64

19:                                               ; preds = %14
  %20 = landingpad { ptr, i32 }
          cleanup
  br label %65

21:                                               ; preds = %18
  %22 = getelementptr inbounds i8, ptr %3, i64 52
  %23 = load i8, ptr %22, align 4, !tbaa !15, !range !16, !noundef !17
  %24 = trunc nuw i8 %23 to i1
  br i1 %24, label %25, label %26

25:                                               ; preds = %21
  call void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
  br label %26

26:                                               ; preds = %25, %21
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %5) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #6
  %27 = getelementptr inbounds i8, ptr %3, i64 40
  %28 = load i32, ptr %27, align 8, !tbaa !18
  call void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %28)
  invoke void @_ZZ4mainENK7Factory16CreateStateSpaceEv(ptr noundef nonnull align 4 dereferenceable(4) %6)
          to label %29 unwind label %35

29:                                               ; preds = %26
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #6
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %7) #6
  %30 = load i32, ptr %4, align 8, !tbaa !19
  invoke void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6CreateEj(ptr dead_on_unwind nonnull writable sret(%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector") align 8 %7, i32 noundef %30)
          to label %31 unwind label %37

31:                                               ; preds = %29
  %32 = invoke noundef zeroext i1 @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6IsNullERKNS4_6VectorE(ptr noundef nonnull align 8 dereferenceable(20) %7)
          to label %33 unwind label %39

33:                                               ; preds = %31
  br i1 %32, label %34, label %41

34:                                               ; preds = %33
  call void (ptr, ...) @_ZN4qsim2IO6errorfEPKcz(ptr noundef nonnull @.str.2)
  br label %60

35:                                               ; preds = %26
  %36 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #6
  br label %63

37:                                               ; preds = %29
  %38 = landingpad { ptr, i32 }
          cleanup
  br label %62

39:                                               ; preds = %41, %31
  %40 = landingpad { ptr, i32 }
          cleanup
  br label %61

41:                                               ; preds = %33
  invoke void @_ZNK4qsim15StateSpaceBasicINS_13SequentialForEfE12SetStateZeroERNS_11VectorSpaceIS2_S1_fE6VectorE(ptr noundef nonnull align 1 dereferenceable(1) %5, ptr noundef nonnull align 8 dereferenceable(20) %7)
          to label %42 unwind label %39

42:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %8) #6
  call void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16) %8) #6
  %43 = getelementptr inbounds i8, ptr %3, i64 44
  %44 = getelementptr inbounds i8, ptr %3, i64 36
  %45 = load i32, ptr %44, align 4, !tbaa !25
  %46 = zext i32 %45 to i64
  %47 = getelementptr inbounds i8, ptr %8, i64 8
  store i64 %46, ptr %47, align 8, !tbaa !26
  %48 = load <2 x i32>, ptr %43, align 4, !tbaa !29
  store <2 x i32> %48, ptr %8, align 8, !tbaa !29
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %9) #6
  %49 = load i32, ptr %27, align 8, !tbaa !18
  call void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %9, i32 noundef %49)
  %50 = invoke noundef zeroext i1 @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEEEbRKNSA_9ParameterERKS7_RKT_RNS_11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEESO_fE6VectorE(ptr noundef nonnull align 8 dereferenceable(16) %8, ptr noundef nonnull align 4 dereferenceable(4) %9, ptr noundef nonnull align 8 dereferenceable(32) %4, ptr noundef nonnull align 8 dereferenceable(20) %7)
          to label %51 unwind label %54

51:                                               ; preds = %42
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %9) #6
  br i1 %50, label %52, label %58

52:                                               ; preds = %51
  %53 = load i32, ptr %4, align 8, !tbaa !19
  invoke void @_Z15PrintAmplitudesIN4qsim15StateSpaceBasicINS0_13SequentialForEfEENS0_11VectorSpaceIS3_S2_fE6VectorEEvjRKT_RKT0_(i32 noundef %53, ptr noundef nonnull align 1 dereferenceable(1) %5, ptr noundef nonnull align 8 dereferenceable(20) %7)
          to label %58 unwind label %56

54:                                               ; preds = %42
  %55 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %9) #6
  br label %59

56:                                               ; preds = %52
  %57 = landingpad { ptr, i32 }
          cleanup
  br label %59

58:                                               ; preds = %52, %51
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #6
  br label %60

59:                                               ; preds = %56, %54
  %.pn = phi { ptr, i32 } [ %57, %56 ], [ %55, %54 ]
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %8) #6
  br label %61

60:                                               ; preds = %58, %34
  %.010 = phi i32 [ 1, %34 ], [ 0, %58 ]
  call void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20) %7) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %7) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #6
  br label %64

61:                                               ; preds = %59, %39
  %.pn.pn = phi { ptr, i32 } [ %.pn, %59 ], [ %40, %39 ]
  call void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20) %7) #6
  br label %62

62:                                               ; preds = %61, %37
  %.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn, %61 ], [ %38, %37 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %7) #6
  br label %63

63:                                               ; preds = %62, %35
  %.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn, %62 ], [ %36, %35 ]
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %5) #6
  br label %65

64:                                               ; preds = %18, %60
  %.111 = phi i32 [ %.010, %60 ], [ 1, %18 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %66

65:                                               ; preds = %63, %19
  %.pn.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn.pn, %63 ], [ %20, %19 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %67

66:                                               ; preds = %11, %64
  %.212 = phi i32 [ %.111, %64 ], [ 1, %11 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53) %3) #6
  call void @llvm.lifetime.end.p0(i64 56, ptr nonnull %3) #6
  ret i32 %.212

67:                                               ; preds = %65, %12
  %.pn.pn.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn.pn.pn, %65 ], [ %13, %12 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(53) %3) #6
  call void @llvm.lifetime.end.p0(i64 56, ptr nonnull %3) #6
  resume { ptr, i32 } %.pn.pn.pn.pn.pn.pn
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() local_unnamed_addr #3

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare hidden void @_ZZ4mainENK7Factory16CreateStateSpaceEv(ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6CreateEj(ptr dead_on_unwind noalias writable sret(%"class.qsim::VectorSpace<qsim::StateSpaceBasic<qsim::SequentialFor, float>, qsim::SequentialFor, float>::Vector") align 8, i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6IsNullERKNS4_6VectorE(ptr noundef nonnull align 8 dereferenceable(20)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNK4qsim15StateSpaceBasicINS_13SequentialForEfE12SetStateZeroERNS_11VectorSpaceIS2_S1_fE6VectorE(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 8 dereferenceable(20)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEEEbRKNSA_9ParameterERKS7_RKT_RNS_11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEESO_fE6VectorE(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(20)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z15PrintAmplitudesIN4qsim15StateSpaceBasicINS0_13SequentialForEfEENS0_11VectorSpaceIS3_S2_fE6VectorEEvjRKT_RKT0_(i32 noundef, ptr noundef nonnull align 1 dereferenceable(1), ptr noundef nonnull align 8 dereferenceable(20)) local_unnamed_addr #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim11VectorSpaceINS_15StateSpaceBasicINS_13SequentialForEfEES2_fE6VectorD2Ev(ptr noundef nonnull align 8 dereferenceable(20)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !13, i64 32}
!6 = !{!"_ZTS7Options", !7, i64 0, !13, i64 32, !13, i64 36, !13, i64 40, !13, i64 44, !13, i64 48, !14, i64 52}
!7 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !8, i64 0, !12, i64 8, !10, i64 16}
!8 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"long", !10, i64 0}
!13 = !{!"int", !10, i64 0}
!14 = !{!"bool", !10, i64 0}
!15 = !{!6, !14, i64 52}
!16 = !{i8 0, i8 2}
!17 = !{}
!18 = !{!6, !13, i64 40}
!19 = !{!20, !13, i64 0}
!20 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !13, i64 0, !21, i64 8}
!21 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!25 = !{!6, !13, i64 36}
!26 = !{!27, !12, i64 8}
!27 = !{!"_ZTSN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterE", !28, i64 0, !12, i64 8}
!28 = !{!"_ZTSN4qsim19MultiQubitGateFuserINS_2IOENS_4GateIfNS_8GateKindEEEE9ParameterE", !13, i64 0, !13, i64 4}
!29 = !{!13, !13, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass