; LLVM IR from huawei-noah/bolt :: compute/tensor/src (softmax)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.SoftmaxParamSpec = type { i32 }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ArchInfo = type { i32, ptr }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z25softmax_infer_output_sizeP6Tensor16SoftmaxParamSpecS0_P8ArchInfo(ptr noundef %0, i32 %1, ptr noundef %2, ptr noundef %3) #0 {
  %5 = alloca %struct.SoftmaxParamSpec, align 4
  %6 = alloca ptr, align 8
  %7 = alloca ptr, align 8
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca %struct.TensorDesc, align 4
  %14 = alloca %struct.TensorDesc, align 4
  %15 = alloca i32, align 4
  %16 = alloca %struct.TensorDesc, align 8
  %17 = getelementptr inbounds %struct.SoftmaxParamSpec, ptr %5, i32 0, i32 0
  store i32 %1, ptr %17, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store ptr %2, ptr %7, align 8, !tbaa !5
  store ptr %3, ptr %8, align 8, !tbaa !5
  %18 = load ptr, ptr %6, align 8, !tbaa !5
  %19 = icmp eq ptr %18, null
  br i1 %19, label %20, label %36

20:                                               ; preds = %4
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #7
  store i32 1, ptr %9, align 4, !tbaa !9
  %21 = load i32, ptr %9, align 4, !tbaa !9
  %22 = icmp ne i32 %21, 0
  br i1 %22, label %23, label %35

23:                                               ; preds = %20
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #7
  %24 = call i64 (i64, ...) @syscall(i64 noundef 186) #7
  %25 = trunc i64 %24 to i32
  store i32 %25, ptr %10, align 4, !tbaa !11
  %26 = load i32, ptr %10, align 4, !tbaa !11
  %27 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %26)
  %28 = load ptr, ptr @stdout, align 8, !tbaa !5
  %29 = call i32 @fflush(ptr noundef %28)
  %30 = load i32, ptr %9, align 4, !tbaa !9
  %31 = call ptr @ee2str(i32 noundef %30)
  %32 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, ptr noundef %31)
  %33 = load ptr, ptr @stdout, align 8, !tbaa !5
  %34 = call i32 @fflush(ptr noundef %33)
  call void @exit(i32 noundef 1) #8
  unreachable

35:                                               ; preds = %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #7
  br label %36

36:                                               ; preds = %35, %4
  %37 = load ptr, ptr %7, align 8, !tbaa !5
  %38 = icmp eq ptr %37, null
  br i1 %38, label %39, label %55

39:                                               ; preds = %36
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #7
  store i32 1, ptr %11, align 4, !tbaa !9
  %40 = load i32, ptr %11, align 4, !tbaa !9
  %41 = icmp ne i32 %40, 0
  br i1 %41, label %42, label %54

42:                                               ; preds = %39
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #7
  %43 = call i64 (i64, ...) @syscall(i64 noundef 186) #7
  %44 = trunc i64 %43 to i32
  store i32 %44, ptr %12, align 4, !tbaa !11
  %45 = load i32, ptr %12, align 4, !tbaa !11
  %46 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %45)
  %47 = load ptr, ptr @stdout, align 8, !tbaa !5
  %48 = call i32 @fflush(ptr noundef %47)
  %49 = load i32, ptr %11, align 4, !tbaa !9
  %50 = call ptr @ee2str(i32 noundef %49)
  %51 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, ptr noundef %50)
  %52 = load ptr, ptr @stdout, align 8, !tbaa !5
  %53 = call i32 @fflush(ptr noundef %52)
  call void @exit(i32 noundef 1) #8
  unreachable

54:                                               ; preds = %39
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #7
  br label %55

55:                                               ; preds = %54, %36
  call void @llvm.lifetime.start.p0(i64 92, ptr %13) #7
  %56 = load ptr, ptr %6, align 8, !tbaa !5
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind writable sret(%struct.TensorDesc) align 4 %13, ptr noundef nonnull align 8 dereferenceable(32) %56)
  call void @llvm.lifetime.start.p0(i64 92, ptr %14) #7
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %14, ptr align 4 %13, i64 92, i1 false), !tbaa.struct !13
  %57 = load ptr, ptr %8, align 8, !tbaa !5
  %58 = getelementptr inbounds %struct.ArchInfo, ptr %57, i32 0, i32 0
  %59 = load i32, ptr %58, align 8, !tbaa !19
  %60 = icmp eq i32 %59, 2
  br i1 %60, label %66, label %61

61:                                               ; preds = %55
  %62 = load ptr, ptr %8, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.ArchInfo, ptr %62, i32 0, i32 0
  %64 = load i32, ptr %63, align 8, !tbaa !19
  %65 = icmp eq i32 %64, 7
  br i1 %65, label %66, label %67

66:                                               ; preds = %61, %55
  br label %86

67:                                               ; preds = %61
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #7
  %68 = getelementptr inbounds %struct.SoftmaxParamSpec, ptr %5, i32 0, i32 0
  %69 = load i32, ptr %68, align 4, !tbaa !22
  %70 = getelementptr inbounds %struct.TensorDesc, ptr %13, i32 0, i32 2
  %71 = load i32, ptr %70, align 4, !tbaa !24
  %72 = add i32 %69, %71
  %73 = getelementptr inbounds %struct.TensorDesc, ptr %13, i32 0, i32 2
  %74 = load i32, ptr %73, align 4, !tbaa !24
  %75 = urem i32 %72, %74
  store i32 %75, ptr %15, align 4, !tbaa !11
  %76 = getelementptr inbounds %struct.TensorDesc, ptr %14, i32 0, i32 1
  %77 = load i32, ptr %76, align 4, !tbaa !26
  %78 = icmp eq i32 2, %77
  br i1 %78, label %79, label %84

79:                                               ; preds = %67
  %80 = load i32, ptr %15, align 4, !tbaa !11
  %81 = icmp eq i32 %80, 1
  br i1 %81, label %82, label %84

82:                                               ; preds = %79
  %83 = getelementptr inbounds %struct.TensorDesc, ptr %14, i32 0, i32 1
  store i32 0, ptr %83, align 4, !tbaa !26
  br label %84

84:                                               ; preds = %82, %79, %67
  %85 = load ptr, ptr %7, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %16, ptr align 4 %14, i64 92, i1 false), !tbaa.struct !13
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %85, ptr noundef byval(%struct.TensorDesc) align 8 %16)
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #7
  br label %86

86:                                               ; preds = %84, %66
  call void @llvm.lifetime.end.p0(i64 92, ptr %14) #7
  call void @llvm.lifetime.end.p0(i64 92, ptr %13) #7
  ret i32 0
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) #2

declare i32 @printf(ptr noundef, ...) #3

declare i32 @fflush(ptr noundef) #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) #4

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) #5

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #6

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #7 = { nounwind }
attributes #8 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS2EE", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{i64 0, i64 4, !14, i64 4, i64 4, !16, i64 8, i64 4, !11, i64 12, i64 80, !18}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS8DataType", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"_ZTS10DataFormat", !7, i64 0}
!18 = !{!7, !7, i64 0}
!19 = !{!20, !21, i64 0}
!20 = !{!"_ZTS8ArchInfo", !21, i64 0, !6, i64 8}
!21 = !{!"_ZTS4Arch", !7, i64 0}
!22 = !{!23, !12, i64 0}
!23 = !{!"_ZTS16SoftmaxParamSpec", !12, i64 0}
!24 = !{!25, !12, i64 8}
!25 = !{!"_ZTS10TensorDesc", !15, i64 0, !17, i64 4, !12, i64 8, !7, i64 12}
!26 = !{!25, !17, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external local_unnamed_addr global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z25softmax_infer_output_sizeP6Tensor16SoftmaxParamSpecS0_P8ArchInfo(ptr noundef %0, i32 %1, ptr noundef %2, ptr nocapture noundef readonly %3) local_unnamed_addr #0 {
  %5 = alloca %struct.TensorDesc, align 4
  %6 = alloca %struct.TensorDesc, align 8
  %7 = icmp eq ptr %0, null
  br i1 %7, label %8, label %18

8:                                                ; preds = %4
  %9 = tail call i64 (i64, ...) @syscall(i64 noundef 186) #7
  %10 = trunc i64 %9 to i32
  %11 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %10)
  %12 = load ptr, ptr @stdout, align 8, !tbaa !5
  %13 = tail call i32 @fflush(ptr noundef %12)
  %14 = tail call ptr @ee2str(i32 noundef 1)
  %15 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.1, ptr noundef %14)
  %16 = load ptr, ptr @stdout, align 8, !tbaa !5
  %17 = tail call i32 @fflush(ptr noundef %16)
  tail call void @exit(i32 noundef 1) #8
  unreachable

18:                                               ; preds = %4
  %19 = icmp eq ptr %2, null
  br i1 %19, label %20, label %30

20:                                               ; preds = %18
  %21 = tail call i64 (i64, ...) @syscall(i64 noundef 186) #7
  %22 = trunc i64 %21 to i32
  %23 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %22)
  %24 = load ptr, ptr @stdout, align 8, !tbaa !5
  %25 = tail call i32 @fflush(ptr noundef %24)
  %26 = tail call ptr @ee2str(i32 noundef 1)
  %27 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.1, ptr noundef %26)
  %28 = load ptr, ptr @stdout, align 8, !tbaa !5
  %29 = tail call i32 @fflush(ptr noundef %28)
  tail call void @exit(i32 noundef 1) #8
  unreachable

30:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 92, ptr nonnull %5) #7
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind nonnull writable sret(%struct.TensorDesc) align 4 %5, ptr noundef nonnull align 8 dereferenceable(32) %0)
  %31 = load i32, ptr %3, align 8, !tbaa !9
  switch i32 %31, label %32 [
    i32 2, label %38
    i32 7, label %38
  ]

32:                                               ; preds = %30
  %.sroa.6.0..sroa_idx = getelementptr inbounds i8, ptr %5, i64 8
  %.sroa.4.0..sroa_idx = getelementptr inbounds i8, ptr %5, i64 4
  %.sroa.4.0.copyload = load i32, ptr %.sroa.4.0..sroa_idx, align 4, !tbaa !12
  %.sroa.0.0.copyload = load i32, ptr %5, align 4, !tbaa !14
  %33 = load i32, ptr %.sroa.6.0..sroa_idx, align 4, !tbaa !16
  %34 = add i32 %33, %1
  %35 = urem i32 %34, %33
  %36 = icmp eq i32 %.sroa.4.0.copyload, 2
  %37 = icmp eq i32 %35, 1
  %or.cond = select i1 %36, i1 %37, i1 false
  %spec.select = select i1 %or.cond, i32 0, i32 %.sroa.4.0.copyload
  store i32 %.sroa.0.0.copyload, ptr %6, align 8, !tbaa !14
  %.sroa.4.0..sroa_idx3 = getelementptr inbounds i8, ptr %6, i64 4
  store i32 %spec.select, ptr %.sroa.4.0..sroa_idx3, align 4, !tbaa !12
  %.sroa.6.0..sroa_idx5 = getelementptr inbounds i8, ptr %6, i64 8
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(84) %.sroa.6.0..sroa_idx5, ptr noundef nonnull align 4 dereferenceable(84) %.sroa.6.0..sroa_idx, i64 84, i1 false)
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %2, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %6)
  br label %38

38:                                               ; preds = %30, %30, %32
  call void @llvm.lifetime.end.p0(i64 92, ptr nonnull %5) #7
  ret i32 0
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) local_unnamed_addr #2

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: nofree nounwind
declare noundef i32 @fflush(ptr nocapture noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) local_unnamed_addr #4

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) local_unnamed_addr #5

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #6

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #7 = { nounwind }
attributes #8 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS8ArchInfo", !11, i64 0, !6, i64 8}
!11 = !{!"_ZTS4Arch", !7, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"_ZTS10DataFormat", !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS8DataType", !7, i64 0}
!16 = !{!17, !18, i64 8}
!17 = !{!"_ZTS10TensorDesc", !15, i64 0, !13, i64 4, !18, i64 8, !7, i64 12}
!18 = !{!"int", !7, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass