; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu/x86/int8/avx512 (convolution_direct)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ConvController = type { ptr, ptr, ptr, ptr, ptr, ptr, i64, i64, i64, ptr, i64, i64, i64, i64, i64, i64, i64, i64, ptr, i8, i64, i64, ptr }

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z20Avx512ConvKernel5x32R14ConvController(ptr noundef nonnull align 8 dereferenceable(184) %0) #0 {
  %2 = alloca ptr, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %3 = load ptr, ptr %2, align 8, !tbaa !5
  %4 = getelementptr inbounds %struct.ConvController, ptr %3, i32 0, i32 19
  %5 = load i8, ptr %4, align 8, !tbaa !9, !range !13, !noundef !14
  %6 = trunc i8 %5 to i1
  br i1 %6, label %7, label %70

7:                                                ; preds = %1
  %8 = load ptr, ptr %2, align 8, !tbaa !5
  %9 = getelementptr inbounds %struct.ConvController, ptr %8, i32 0, i32 1
  %10 = load ptr, ptr %9, align 8, !tbaa !15
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  %12 = getelementptr inbounds %struct.ConvController, ptr %11, i32 0, i32 5
  %13 = load ptr, ptr %12, align 8, !tbaa !16
  %14 = load ptr, ptr %2, align 8, !tbaa !5
  %15 = getelementptr inbounds %struct.ConvController, ptr %14, i32 0, i32 13
  %16 = load i64, ptr %15, align 8, !tbaa !17
  %17 = call ptr asm sideeffect "vmovups ($0), %zmm24         \0A\09vmovups 0x40($0), %zmm25     \0A\09addq $$0x80, $0                \0A\09mov $$1, %eax                        \0A\09vmovd %eax, %xmm0                  \0A\09vpbroadcastw %xmm0, %zmm31         \0A\09movq $2, %rax                 \0A\09andq $$0x1, %rax                     \0A\09jne 0f                               \0A\09vmovups ($1), %zmm0                       \0A\09vmovups 0x40($1), %zmm1                   \0A\09vmovups %zmm0, %zmm2                   \0A\09vmovups %zmm1, %zmm3                   \0A\09vmovups %zmm0, %zmm4                   \0A\09vmovups %zmm1, %zmm5                   \0A\09vmovups %zmm0, %zmm6                   \0A\09vmovups %zmm1, %zmm7                   \0A\09vmovups %zmm0, %zmm8                   \0A\09vmovups %zmm1, %zmm9                   \0A\09jmp 1f                               \0A\09.align 16                            \0A\090:                                   \0A\09vxorps %zmm0, %zmm0, %zmm0    \0A\09vxorps %zmm1, %zmm1, %zmm1    \0A\09vxorps %zmm2, %zmm2, %zmm2    \0A\09vxorps %zmm3, %zmm3, %zmm3    \0A\09vxorps %zmm4, %zmm4, %zmm4    \0A\09vxorps %zmm5, %zmm5, %zmm5    \0A\09vxorps %zmm6, %zmm6, %zmm6    \0A\09vxorps %zmm7, %zmm7, %zmm7    \0A\09vxorps %zmm8, %zmm8, %zmm8    \0A\09vxorps %zmm9, %zmm9, %zmm9    \0A\09.align 16                            \0A\091:                                   \0A\09", "=r,r,r,0,~{rax},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %13, i64 %16, ptr %10) #1, !srcloc !18
  store ptr %17, ptr %9, align 8, !tbaa !15
  %18 = load ptr, ptr %2, align 8, !tbaa !5
  %19 = getelementptr inbounds %struct.ConvController, ptr %18, i32 0, i32 6
  %20 = load i64, ptr %19, align 8, !tbaa !19
  %21 = load ptr, ptr %2, align 8, !tbaa !5
  %22 = getelementptr inbounds %struct.ConvController, ptr %21, i32 0, i32 0
  %23 = load ptr, ptr %22, align 8, !tbaa !20
  %24 = load ptr, ptr %2, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.ConvController, ptr %24, i32 0, i32 1
  %26 = load ptr, ptr %25, align 8, !tbaa !15
  %27 = load ptr, ptr %2, align 8, !tbaa !5
  %28 = getelementptr inbounds %struct.ConvController, ptr %27, i32 0, i32 8
  %29 = load i64, ptr %28, align 8, !tbaa !21
  %30 = load ptr, ptr %2, align 8, !tbaa !5
  %31 = getelementptr inbounds %struct.ConvController, ptr %30, i32 0, i32 7
  %32 = load i64, ptr %31, align 8, !tbaa !22
  %33 = load ptr, ptr %2, align 8, !tbaa !5
  %34 = getelementptr inbounds %struct.ConvController, ptr %33, i32 0, i32 9
  %35 = load ptr, ptr %34, align 8, !tbaa !23
  %36 = load ptr, ptr %2, align 8, !tbaa !5
  %37 = getelementptr inbounds %struct.ConvController, ptr %36, i32 0, i32 10
  %38 = load i64, ptr %37, align 8, !tbaa !24
  %39 = load ptr, ptr %2, align 8, !tbaa !5
  %40 = getelementptr inbounds %struct.ConvController, ptr %39, i32 0, i32 11
  %41 = load i64, ptr %40, align 8, !tbaa !25
  %42 = load ptr, ptr %2, align 8, !tbaa !5
  %43 = getelementptr inbounds %struct.ConvController, ptr %42, i32 0, i32 14
  %44 = load i64, ptr %43, align 8, !tbaa !26
  %45 = load ptr, ptr %2, align 8, !tbaa !5
  %46 = getelementptr inbounds %struct.ConvController, ptr %45, i32 0, i32 21
  %47 = load i64, ptr %46, align 8, !tbaa !27
  %48 = load ptr, ptr %2, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.ConvController, ptr %48, i32 0, i32 15
  %50 = load i64, ptr %49, align 8, !tbaa !28
  %51 = call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x0($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x80($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x100($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x180($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %29, i64 %32, ptr %35, i64 %38, i64 %41, i64 %44, i64 %47, i64 %50, i64 %20, ptr %23, ptr %26) #1, !srcloc !29
  %52 = extractvalue { i64, ptr, ptr } %51, 0
  %53 = extractvalue { i64, ptr, ptr } %51, 1
  %54 = extractvalue { i64, ptr, ptr } %51, 2
  store i64 %52, ptr %19, align 8, !tbaa !19
  store ptr %53, ptr %22, align 8, !tbaa !20
  store ptr %54, ptr %25, align 8, !tbaa !15
  %55 = load ptr, ptr %2, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.ConvController, ptr %55, i32 0, i32 2
  %57 = load ptr, ptr %56, align 8, !tbaa !30
  %58 = load ptr, ptr %2, align 8, !tbaa !5
  %59 = getelementptr inbounds %struct.ConvController, ptr %58, i32 0, i32 3
  %60 = load ptr, ptr %59, align 8, !tbaa !31
  %61 = load ptr, ptr %2, align 8, !tbaa !5
  %62 = getelementptr inbounds %struct.ConvController, ptr %61, i32 0, i32 12
  %63 = load i64, ptr %62, align 8, !tbaa !32
  %64 = load ptr, ptr %2, align 8, !tbaa !5
  %65 = getelementptr inbounds %struct.ConvController, ptr %64, i32 0, i32 13
  %66 = load i64, ptr %65, align 8, !tbaa !17
  %67 = load ptr, ptr %2, align 8, !tbaa !5
  %68 = getelementptr inbounds %struct.ConvController, ptr %67, i32 0, i32 18
  %69 = load ptr, ptr %68, align 8, !tbaa !33
  call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %57, ptr %60, i64 %63, i64 %66, ptr %69) #1, !srcloc !34
  br label %202

70:                                               ; preds = %1
  %71 = load ptr, ptr %2, align 8, !tbaa !5
  %72 = getelementptr inbounds %struct.ConvController, ptr %71, i32 0, i32 17
  %73 = load i64, ptr %72, align 8, !tbaa !35
  %74 = icmp sgt i64 %73, 1
  br i1 %74, label %75, label %138

75:                                               ; preds = %70
  %76 = load ptr, ptr %2, align 8, !tbaa !5
  %77 = getelementptr inbounds %struct.ConvController, ptr %76, i32 0, i32 1
  %78 = load ptr, ptr %77, align 8, !tbaa !15
  %79 = load ptr, ptr %2, align 8, !tbaa !5
  %80 = getelementptr inbounds %struct.ConvController, ptr %79, i32 0, i32 5
  %81 = load ptr, ptr %80, align 8, !tbaa !16
  %82 = load ptr, ptr %2, align 8, !tbaa !5
  %83 = getelementptr inbounds %struct.ConvController, ptr %82, i32 0, i32 13
  %84 = load i64, ptr %83, align 8, !tbaa !17
  %85 = call ptr asm sideeffect "vmovups ($0), %zmm24         \0A\09vmovups 0x40($0), %zmm25     \0A\09addq $$0x80, $0                \0A\09mov $$1, %eax                        \0A\09vmovd %eax, %xmm0                  \0A\09vpbroadcastw %xmm0, %zmm31         \0A\09movq $2, %rax                 \0A\09andq $$0x1, %rax                     \0A\09jne 0f                               \0A\09vmovups ($1), %zmm0                       \0A\09vmovups 0x40($1), %zmm1                   \0A\09vmovups %zmm0, %zmm2                   \0A\09vmovups %zmm1, %zmm3                   \0A\09vmovups %zmm0, %zmm4                   \0A\09vmovups %zmm1, %zmm5                   \0A\09vmovups %zmm0, %zmm6                   \0A\09vmovups %zmm1, %zmm7                   \0A\09vmovups %zmm0, %zmm8                   \0A\09vmovups %zmm1, %zmm9                   \0A\09jmp 1f                               \0A\09.align 16                            \0A\090:                                   \0A\09vxorps %zmm0, %zmm0, %zmm0    \0A\09vxorps %zmm1, %zmm1, %zmm1    \0A\09vxorps %zmm2, %zmm2, %zmm2    \0A\09vxorps %zmm3, %zmm3, %zmm3    \0A\09vxorps %zmm4, %zmm4, %zmm4    \0A\09vxorps %zmm5, %zmm5, %zmm5    \0A\09vxorps %zmm6, %zmm6, %zmm6    \0A\09vxorps %zmm7, %zmm7, %zmm7    \0A\09vxorps %zmm8, %zmm8, %zmm8    \0A\09vxorps %zmm9, %zmm9, %zmm9    \0A\09.align 16                            \0A\091:                                   \0A\09", "=r,r,r,0,~{rax},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %81, i64 %84, ptr %78) #1, !srcloc !36
  store ptr %85, ptr %77, align 8, !tbaa !15
  %86 = load ptr, ptr %2, align 8, !tbaa !5
  %87 = getelementptr inbounds %struct.ConvController, ptr %86, i32 0, i32 6
  %88 = load i64, ptr %87, align 8, !tbaa !19
  %89 = load ptr, ptr %2, align 8, !tbaa !5
  %90 = getelementptr inbounds %struct.ConvController, ptr %89, i32 0, i32 0
  %91 = load ptr, ptr %90, align 8, !tbaa !20
  %92 = load ptr, ptr %2, align 8, !tbaa !5
  %93 = getelementptr inbounds %struct.ConvController, ptr %92, i32 0, i32 1
  %94 = load ptr, ptr %93, align 8, !tbaa !15
  %95 = load ptr, ptr %2, align 8, !tbaa !5
  %96 = getelementptr inbounds %struct.ConvController, ptr %95, i32 0, i32 8
  %97 = load i64, ptr %96, align 8, !tbaa !21
  %98 = load ptr, ptr %2, align 8, !tbaa !5
  %99 = getelementptr inbounds %struct.ConvController, ptr %98, i32 0, i32 7
  %100 = load i64, ptr %99, align 8, !tbaa !22
  %101 = load ptr, ptr %2, align 8, !tbaa !5
  %102 = getelementptr inbounds %struct.ConvController, ptr %101, i32 0, i32 9
  %103 = load ptr, ptr %102, align 8, !tbaa !23
  %104 = load ptr, ptr %2, align 8, !tbaa !5
  %105 = getelementptr inbounds %struct.ConvController, ptr %104, i32 0, i32 10
  %106 = load i64, ptr %105, align 8, !tbaa !24
  %107 = load ptr, ptr %2, align 8, !tbaa !5
  %108 = getelementptr inbounds %struct.ConvController, ptr %107, i32 0, i32 11
  %109 = load i64, ptr %108, align 8, !tbaa !25
  %110 = load ptr, ptr %2, align 8, !tbaa !5
  %111 = getelementptr inbounds %struct.ConvController, ptr %110, i32 0, i32 14
  %112 = load i64, ptr %111, align 8, !tbaa !26
  %113 = load ptr, ptr %2, align 8, !tbaa !5
  %114 = getelementptr inbounds %struct.ConvController, ptr %113, i32 0, i32 21
  %115 = load i64, ptr %114, align 8, !tbaa !27
  %116 = load ptr, ptr %2, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.ConvController, ptr %116, i32 0, i32 15
  %118 = load i64, ptr %117, align 8, !tbaa !28
  %119 = call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x0($2), %zmm26         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x80($2), %zmm24         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x100($2), %zmm26         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x180($2), %zmm24         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %97, i64 %100, ptr %103, i64 %106, i64 %109, i64 %112, i64 %115, i64 %118, i64 %88, ptr %91, ptr %94) #1, !srcloc !37
  %120 = extractvalue { i64, ptr, ptr } %119, 0
  %121 = extractvalue { i64, ptr, ptr } %119, 1
  %122 = extractvalue { i64, ptr, ptr } %119, 2
  store i64 %120, ptr %87, align 8, !tbaa !19
  store ptr %121, ptr %90, align 8, !tbaa !20
  store ptr %122, ptr %93, align 8, !tbaa !15
  %123 = load ptr, ptr %2, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.ConvController, ptr %123, i32 0, i32 2
  %125 = load ptr, ptr %124, align 8, !tbaa !30
  %126 = load ptr, ptr %2, align 8, !tbaa !5
  %127 = getelementptr inbounds %struct.ConvController, ptr %126, i32 0, i32 3
  %128 = load ptr, ptr %127, align 8, !tbaa !31
  %129 = load ptr, ptr %2, align 8, !tbaa !5
  %130 = getelementptr inbounds %struct.ConvController, ptr %129, i32 0, i32 12
  %131 = load i64, ptr %130, align 8, !tbaa !32
  %132 = load ptr, ptr %2, align 8, !tbaa !5
  %133 = getelementptr inbounds %struct.ConvController, ptr %132, i32 0, i32 13
  %134 = load i64, ptr %133, align 8, !tbaa !17
  %135 = load ptr, ptr %2, align 8, !tbaa !5
  %136 = getelementptr inbounds %struct.ConvController, ptr %135, i32 0, i32 18
  %137 = load ptr, ptr %136, align 8, !tbaa !33
  call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %125, ptr %128, i64 %131, i64 %134, ptr %137) #1, !srcloc !38
  br label %201

138:                                              ; preds = %70
  %139 = load ptr, ptr %2, align 8, !tbaa !5
  %140 = getelementptr inbounds %struct.ConvController, ptr %139, i32 0, i32 1
  %141 = load ptr, ptr %140, align 8, !tbaa !15
  %142 = load ptr, ptr %2, align 8, !tbaa !5
  %143 = getelementptr inbounds %struct.ConvController, ptr %142, i32 0, i32 5
  %144 = load ptr, ptr %143, align 8, !tbaa !16
  %145 = load ptr, ptr %2, align 8, !tbaa !5
  %146 = getelementptr inbounds %struct.ConvController, ptr %145, i32 0, i32 13
  %147 = load i64, ptr %146, align 8, !tbaa !17
  %148 = call ptr asm sideeffect "vmovups ($0), %zmm24         \0A\09vmovups 0x40($0), %zmm25     \0A\09addq $$0x80, $0                \0A\09mov $$1, %eax                        \0A\09vmovd %eax, %xmm0                  \0A\09vpbroadcastw %xmm0, %zmm31         \0A\09movq $2, %rax                 \0A\09andq $$0x1, %rax                     \0A\09jne 0f                               \0A\09vmovups ($1), %zmm0                       \0A\09vmovups 0x40($1), %zmm1                   \0A\09vmovups %zmm0, %zmm2                   \0A\09vmovups %zmm1, %zmm3                   \0A\09vmovups %zmm0, %zmm4                   \0A\09vmovups %zmm1, %zmm5                   \0A\09vmovups %zmm0, %zmm6                   \0A\09vmovups %zmm1, %zmm7                   \0A\09vmovups %zmm0, %zmm8                   \0A\09vmovups %zmm1, %zmm9                   \0A\09jmp 1f                               \0A\09.align 16                            \0A\090:                                   \0A\09vxorps %zmm0, %zmm0, %zmm0    \0A\09vxorps %zmm1, %zmm1, %zmm1    \0A\09vxorps %zmm2, %zmm2, %zmm2    \0A\09vxorps %zmm3, %zmm3, %zmm3    \0A\09vxorps %zmm4, %zmm4, %zmm4    \0A\09vxorps %zmm5, %zmm5, %zmm5    \0A\09vxorps %zmm6, %zmm6, %zmm6    \0A\09vxorps %zmm7, %zmm7, %zmm7    \0A\09vxorps %zmm8, %zmm8, %zmm8    \0A\09vxorps %zmm9, %zmm9, %zmm9    \0A\09.align 16                            \0A\091:                                   \0A\09", "=r,r,r,0,~{rax},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %144, i64 %147, ptr %141) #1, !srcloc !39
  store ptr %148, ptr %140, align 8, !tbaa !15
  %149 = load ptr, ptr %2, align 8, !tbaa !5
  %150 = getelementptr inbounds %struct.ConvController, ptr %149, i32 0, i32 6
  %151 = load i64, ptr %150, align 8, !tbaa !19
  %152 = load ptr, ptr %2, align 8, !tbaa !5
  %153 = getelementptr inbounds %struct.ConvController, ptr %152, i32 0, i32 0
  %154 = load ptr, ptr %153, align 8, !tbaa !20
  %155 = load ptr, ptr %2, align 8, !tbaa !5
  %156 = getelementptr inbounds %struct.ConvController, ptr %155, i32 0, i32 1
  %157 = load ptr, ptr %156, align 8, !tbaa !15
  %158 = load ptr, ptr %2, align 8, !tbaa !5
  %159 = getelementptr inbounds %struct.ConvController, ptr %158, i32 0, i32 8
  %160 = load i64, ptr %159, align 8, !tbaa !21
  %161 = load ptr, ptr %2, align 8, !tbaa !5
  %162 = getelementptr inbounds %struct.ConvController, ptr %161, i32 0, i32 7
  %163 = load i64, ptr %162, align 8, !tbaa !22
  %164 = load ptr, ptr %2, align 8, !tbaa !5
  %165 = getelementptr inbounds %struct.ConvController, ptr %164, i32 0, i32 9
  %166 = load ptr, ptr %165, align 8, !tbaa !23
  %167 = load ptr, ptr %2, align 8, !tbaa !5
  %168 = getelementptr inbounds %struct.ConvController, ptr %167, i32 0, i32 10
  %169 = load i64, ptr %168, align 8, !tbaa !24
  %170 = load ptr, ptr %2, align 8, !tbaa !5
  %171 = getelementptr inbounds %struct.ConvController, ptr %170, i32 0, i32 11
  %172 = load i64, ptr %171, align 8, !tbaa !25
  %173 = load ptr, ptr %2, align 8, !tbaa !5
  %174 = getelementptr inbounds %struct.ConvController, ptr %173, i32 0, i32 14
  %175 = load i64, ptr %174, align 8, !tbaa !26
  %176 = load ptr, ptr %2, align 8, !tbaa !5
  %177 = getelementptr inbounds %struct.ConvController, ptr %176, i32 0, i32 21
  %178 = load i64, ptr %177, align 8, !tbaa !27
  %179 = load ptr, ptr %2, align 8, !tbaa !5
  %180 = getelementptr inbounds %struct.ConvController, ptr %179, i32 0, i32 15
  %181 = load i64, ptr %180, align 8, !tbaa !28
  %182 = call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x0($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x80($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x100($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x180($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %160, i64 %163, ptr %166, i64 %169, i64 %172, i64 %175, i64 %178, i64 %181, i64 %151, ptr %154, ptr %157) #1, !srcloc !40
  %183 = extractvalue { i64, ptr, ptr } %182, 0
  %184 = extractvalue { i64, ptr, ptr } %182, 1
  %185 = extractvalue { i64, ptr, ptr } %182, 2
  store i64 %183, ptr %150, align 8, !tbaa !19
  store ptr %184, ptr %153, align 8, !tbaa !20
  store ptr %185, ptr %156, align 8, !tbaa !15
  %186 = load ptr, ptr %2, align 8, !tbaa !5
  %187 = getelementptr inbounds %struct.ConvController, ptr %186, i32 0, i32 2
  %188 = load ptr, ptr %187, align 8, !tbaa !30
  %189 = load ptr, ptr %2, align 8, !tbaa !5
  %190 = getelementptr inbounds %struct.ConvController, ptr %189, i32 0, i32 3
  %191 = load ptr, ptr %190, align 8, !tbaa !31
  %192 = load ptr, ptr %2, align 8, !tbaa !5
  %193 = getelementptr inbounds %struct.ConvController, ptr %192, i32 0, i32 12
  %194 = load i64, ptr %193, align 8, !tbaa !32
  %195 = load ptr, ptr %2, align 8, !tbaa !5
  %196 = getelementptr inbounds %struct.ConvController, ptr %195, i32 0, i32 13
  %197 = load i64, ptr %196, align 8, !tbaa !17
  %198 = load ptr, ptr %2, align 8, !tbaa !5
  %199 = getelementptr inbounds %struct.ConvController, ptr %198, i32 0, i32 18
  %200 = load ptr, ptr %199, align 8, !tbaa !33
  call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %188, ptr %191, i64 %194, i64 %197, ptr %200) #1, !srcloc !41
  br label %201

201:                                              ; preds = %138, %75
  br label %202

202:                                              ; preds = %201, %7
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !12, i64 152}
!10 = !{!"_ZTS14ConvController", !6, i64 0, !6, i64 8, !6, i64 16, !6, i64 24, !6, i64 32, !6, i64 40, !11, i64 48, !11, i64 56, !11, i64 64, !6, i64 72, !11, i64 80, !11, i64 88, !11, i64 96, !11, i64 104, !11, i64 112, !11, i64 120, !11, i64 128, !11, i64 136, !6, i64 144, !12, i64 152, !11, i64 160, !11, i64 168, !6, i64 176}
!11 = !{!"long", !7, i64 0}
!12 = !{!"bool", !7, i64 0}
!13 = !{i8 0, i8 2}
!14 = !{}
!15 = !{!10, !6, i64 8}
!16 = !{!10, !6, i64 40}
!17 = !{!10, !11, i64 104}
!18 = !{i64 2153649704, i64 2153649744, i64 2153649817, i64 2153649890, i64 2153649963, i64 2153650036, i64 2153650109, i64 2153650182, i64 2153650255, i64 2153650328, i64 2153661056, i64 2153661118, i64 2153660836, i64 2153660901, i64 2153660640, i64 2153660705, i64 2153660444, i64 2153660509, i64 2153660248, i64 2153660313, i64 2153650476, i64 2153650549, i64 2153650622, i64 2153662135, i64 2153662056, i64 2153661952, i64 2153661848, i64 2153661744, i64 2153661640, i64 2153661536, i64 2153661432, i64 2153661328, i64 2153661224, i64 2153650768, i64 2153650841}
!19 = !{!10, !11, i64 48}
!20 = !{!10, !6, i64 0}
!21 = !{!10, !11, i64 64}
!22 = !{!10, !11, i64 56}
!23 = !{!10, !6, i64 72}
!24 = !{!10, !11, i64 80}
!25 = !{!10, !11, i64 88}
!26 = !{!10, !11, i64 112}
!27 = !{!10, !11, i64 168}
!28 = !{!10, !11, i64 120}
!29 = !{i64 2153651578, i64 2153651630, i64 2153651717, i64 2153651805, i64 2153651893, i64 2153651981, i64 2153652069, i64 2153652157, i64 2153652245, i64 2153652333, i64 2153652421, i64 2153652509, i64 2153652597, i64 2153663248, i64 2153663307, i64 2153663366, i64 2153663425, i64 2153663484, i64 2153663543, i64 2153663602, i64 2153663661, i64 2153663720, i64 2153663779, i64 2153663838, i64 2153663897, i64 2153663956, i64 2153662868, i64 2153662927, i64 2153662986, i64 2153663045, i64 2153663104, i64 2153662315, i64 2153662374, i64 2153662433, i64 2153662492, i64 2153662551, i64 2153662610, i64 2153652874, i64 2153652962, i64 2153665151, i64 2153665210, i64 2153665269, i64 2153665328, i64 2153665387, i64 2153665446, i64 2153665505, i64 2153665564, i64 2153665623, i64 2153665682, i64 2153665741, i64 2153665800, i64 2153665859, i64 2153664770, i64 2153664829, i64 2153664888, i64 2153664947, i64 2153665006, i64 2153664216, i64 2153664275, i64 2153664334, i64 2153664393, i64 2153664452, i64 2153664511, i64 2153653239, i64 2153653327, i64 2153667060, i64 2153667119, i64 2153667178, i64 2153667237, i64 2153667296, i64 2153667355, i64 2153667414, i64 2153667473, i64 2153667532, i64 2153667591, i64 2153667650, i64 2153667709, i64 2153667768, i64 2153666677, i64 2153666736, i64 2153666795, i64 2153666854, i64 2153666913, i64 2153666120, i64 2153666179, i64 2153666238, i64 2153666297, i64 2153666356, i64 2153666415, i64 2153653604, i64 2153653692, i64 2153668970, i64 2153669029, i64 2153669088, i64 2153669147, i64 2153669206, i64 2153669265, i64 2153669324, i64 2153669383, i64 2153669442, i64 2153669501, i64 2153669560, i64 2153669619, i64 2153669678, i64 2153668587, i64 2153668646, i64 2153668705, i64 2153668764, i64 2153668823, i64 2153668030, i64 2153668089, i64 2153668148, i64 2153668207, i64 2153668266, i64 2153668325, i64 2153653969, i64 2153654057, i64 2153654145, i64 2153654233, i64 2153654321, i64 2153654409, i64 2153654497, i64 2153654585, i64 2153654673, i64 2153654761, i64 2153654849, i64 2153654937, i64 2153655025, i64 2153655113, i64 2153655201}
!30 = !{!10, !6, i64 16}
!31 = !{!10, !6, i64 24}
!32 = !{!10, !11, i64 96}
!33 = !{!10, !6, i64 144}
!34 = !{i64 2153656504, i64 2153656557, i64 2153656642, i64 2153656727, i64 2153656812, i64 2153656897, i64 2153670904, i64 2153670799, i64 2153670570, i64 2153670640, i64 2153670343, i64 2153670413, i64 2153670116, i64 2153670186, i64 2153669889, i64 2153669959, i64 2153657049, i64 2153657134, i64 2153657219, i64 2153657304, i64 2153657389, i64 2153657474, i64 2153657559, i64 2153672403, i64 2153672476, i64 2153672281, i64 2153672125, i64 2153671969, i64 2153671813, i64 2153671657, i64 2153671501, i64 2153671345, i64 2153671189, i64 2153671033, i64 2153657713, i64 2153657798, i64 2153657883, i64 2153678010, i64 2153678077, i64 2153678144, i64 2153678211, i64 2153678278, i64 2153678345, i64 2153678412, i64 2153677480, i64 2153677547, i64 2153677614, i64 2153677681, i64 2153677748, i64 2153677815, i64 2153672670, i64 2153672737, i64 2153672804, i64 2153672871, i64 2153672938, i64 2153673005, i64 2153673072, i64 2153673139, i64 2153658041, i64 2153658126, i64 2153658211, i64 2153658296, i64 2153658381, i64 2153679741, i64 2153679626, i64 2153679382, i64 2153679452, i64 2153679140, i64 2153679210, i64 2153678898, i64 2153678968, i64 2153678656, i64 2153678726, i64 2153658538, i64 2153658623, i64 2153658708, i64 2153658793, i64 2153658878, i64 2153681227, i64 2153681300, i64 2153681107, i64 2153680953, i64 2153680799, i64 2153680645, i64 2153680491, i64 2153680337, i64 2153680183, i64 2153680029, i64 2153679875, i64 2153659031, i64 2153659116, i64 2153682234, i64 2153682304, i64 2153682067, i64 2153682137, i64 2153681868, i64 2153681938, i64 2153681669, i64 2153681739, i64 2153681470, i64 2153681540}
!35 = !{!10, !11, i64 136}
!36 = !{i64 2153682353, i64 2153682393, i64 2153682466, i64 2153682539, i64 2153682612, i64 2153682685, i64 2153682758, i64 2153682831, i64 2153682904, i64 2153682977, i64 2153693705, i64 2153693767, i64 2153693485, i64 2153693550, i64 2153693289, i64 2153693354, i64 2153693093, i64 2153693158, i64 2153692897, i64 2153692962, i64 2153683125, i64 2153683198, i64 2153683271, i64 2153694784, i64 2153694705, i64 2153694601, i64 2153694497, i64 2153694393, i64 2153694289, i64 2153694185, i64 2153694081, i64 2153693977, i64 2153693873, i64 2153683417, i64 2153683490}
!37 = !{i64 2153684227, i64 2153684279, i64 2153684366, i64 2153684454, i64 2153684542, i64 2153684630, i64 2153684718, i64 2153684806, i64 2153684894, i64 2153684982, i64 2153685070, i64 2153685158, i64 2153685246, i64 2153695915, i64 2153695974, i64 2153696033, i64 2153696092, i64 2153696151, i64 2153696210, i64 2153696269, i64 2153696328, i64 2153696387, i64 2153696446, i64 2153695519, i64 2153695578, i64 2153695637, i64 2153695696, i64 2153695755, i64 2153694965, i64 2153695024, i64 2153695083, i64 2153695142, i64 2153695201, i64 2153695260, i64 2153685523, i64 2153685611, i64 2153697644, i64 2153697703, i64 2153697762, i64 2153697821, i64 2153697880, i64 2153697939, i64 2153697998, i64 2153698057, i64 2153698116, i64 2153698175, i64 2153697246, i64 2153697305, i64 2153697364, i64 2153697423, i64 2153697482, i64 2153696691, i64 2153696750, i64 2153696809, i64 2153696868, i64 2153696927, i64 2153696986, i64 2153685888, i64 2153685976, i64 2153699379, i64 2153699438, i64 2153699497, i64 2153699556, i64 2153699615, i64 2153699674, i64 2153699733, i64 2153699792, i64 2153699851, i64 2153699910, i64 2153698978, i64 2153699037, i64 2153699096, i64 2153699155, i64 2153699214, i64 2153698420, i64 2153698479, i64 2153698538, i64 2153698597, i64 2153698656, i64 2153698715, i64 2153686253, i64 2153686341, i64 2153701114, i64 2153701173, i64 2153701232, i64 2153701291, i64 2153701350, i64 2153701409, i64 2153701468, i64 2153701527, i64 2153701586, i64 2153701645, i64 2153700713, i64 2153700772, i64 2153700831, i64 2153700890, i64 2153700949, i64 2153700155, i64 2153700214, i64 2153700273, i64 2153700332, i64 2153700391, i64 2153700450, i64 2153686618, i64 2153686706, i64 2153686794, i64 2153686882, i64 2153686970, i64 2153687058, i64 2153687146, i64 2153687234, i64 2153687322, i64 2153687410, i64 2153687498, i64 2153687586, i64 2153687674, i64 2153687762, i64 2153687850}
!38 = !{i64 2153689153, i64 2153689206, i64 2153689291, i64 2153689376, i64 2153689461, i64 2153689546, i64 2153702853, i64 2153702748, i64 2153702519, i64 2153702589, i64 2153702292, i64 2153702362, i64 2153702065, i64 2153702135, i64 2153701838, i64 2153701908, i64 2153689698, i64 2153689783, i64 2153689868, i64 2153689953, i64 2153690038, i64 2153690123, i64 2153690208, i64 2153704352, i64 2153704425, i64 2153704230, i64 2153704074, i64 2153703918, i64 2153703762, i64 2153703606, i64 2153703450, i64 2153703294, i64 2153703138, i64 2153702982, i64 2153690362, i64 2153690447, i64 2153690532, i64 2153705898, i64 2153705965, i64 2153706032, i64 2153706099, i64 2153706166, i64 2153706233, i64 2153706300, i64 2153705368, i64 2153705435, i64 2153705502, i64 2153705569, i64 2153705636, i64 2153705703, i64 2153704619, i64 2153704686, i64 2153704753, i64 2153704820, i64 2153704887, i64 2153704954, i64 2153705021, i64 2153705088, i64 2153690690, i64 2153690775, i64 2153690860, i64 2153690945, i64 2153691030, i64 2153711690, i64 2153711575, i64 2153711331, i64 2153711401, i64 2153711089, i64 2153711159, i64 2153710847, i64 2153710917, i64 2153710605, i64 2153710675, i64 2153691187, i64 2153691272, i64 2153691357, i64 2153691442, i64 2153691527, i64 2153713176, i64 2153713249, i64 2153713056, i64 2153712902, i64 2153712748, i64 2153712594, i64 2153712440, i64 2153712286, i64 2153712132, i64 2153711978, i64 2153711824, i64 2153691680, i64 2153691765, i64 2153714183, i64 2153714253, i64 2153714016, i64 2153714086, i64 2153713817, i64 2153713887, i64 2153713618, i64 2153713688, i64 2153713419, i64 2153713489}
!39 = !{i64 2153714302, i64 2153714342, i64 2153714415, i64 2153714488, i64 2153714561, i64 2153714634, i64 2153714707, i64 2153714780, i64 2153714853, i64 2153714926, i64 2153725654, i64 2153725716, i64 2153725434, i64 2153725499, i64 2153725238, i64 2153725303, i64 2153725042, i64 2153725107, i64 2153724846, i64 2153724911, i64 2153715074, i64 2153715147, i64 2153715220, i64 2153726733, i64 2153726654, i64 2153726550, i64 2153726446, i64 2153726342, i64 2153726238, i64 2153726134, i64 2153726030, i64 2153725926, i64 2153725822, i64 2153715366, i64 2153715439}
!40 = !{i64 2153716176, i64 2153716228, i64 2153716315, i64 2153716403, i64 2153716491, i64 2153716579, i64 2153716667, i64 2153716755, i64 2153716843, i64 2153716931, i64 2153717019, i64 2153717107, i64 2153717195, i64 2153728413, i64 2153728470, i64 2153728529, i64 2153728588, i64 2153728672, i64 2153728729, i64 2153728788, i64 2153728847, i64 2153728906, i64 2153728965, i64 2153729024, i64 2153729144, i64 2153726916, i64 2153726975, i64 2153727034, i64 2153727093, i64 2153727152, i64 2153717472, i64 2153717560, i64 2153730817, i64 2153730874, i64 2153730933, i64 2153730992, i64 2153731076, i64 2153731133, i64 2153731192, i64 2153731251, i64 2153731310, i64 2153731369, i64 2153731428, i64 2153731549, i64 2153729311, i64 2153729370, i64 2153729429, i64 2153729488, i64 2153729547, i64 2153717837, i64 2153717925, i64 2153733241, i64 2153733298, i64 2153733357, i64 2153733416, i64 2153733500, i64 2153733557, i64 2153733616, i64 2153733675, i64 2153733734, i64 2153733793, i64 2153733852, i64 2153733974, i64 2153731716, i64 2153731775, i64 2153731834, i64 2153731893, i64 2153731952, i64 2153718202, i64 2153718290, i64 2153735666, i64 2153735723, i64 2153735782, i64 2153735841, i64 2153735925, i64 2153735982, i64 2153736041, i64 2153736100, i64 2153736159, i64 2153736218, i64 2153736277, i64 2153736399, i64 2153734141, i64 2153734200, i64 2153734259, i64 2153734318, i64 2153734377, i64 2153718567, i64 2153718655, i64 2153718743, i64 2153718831, i64 2153718919, i64 2153719007, i64 2153719095, i64 2153719183, i64 2153719271, i64 2153719359, i64 2153719447, i64 2153719535, i64 2153719623, i64 2153719711, i64 2153719799}
!41 = !{i64 2153721102, i64 2153721155, i64 2153721240, i64 2153721325, i64 2153721410, i64 2153721495, i64 2153737527, i64 2153737422, i64 2153737193, i64 2153737263, i64 2153736966, i64 2153737036, i64 2153736739, i64 2153736809, i64 2153736512, i64 2153736582, i64 2153721647, i64 2153721732, i64 2153721817, i64 2153721902, i64 2153721987, i64 2153722072, i64 2153722157, i64 2153739026, i64 2153739099, i64 2153738904, i64 2153738748, i64 2153738592, i64 2153738436, i64 2153738280, i64 2153738124, i64 2153737968, i64 2153737812, i64 2153737656, i64 2153722311, i64 2153722396, i64 2153722481, i64 2153740572, i64 2153740639, i64 2153740706, i64 2153740773, i64 2153740840, i64 2153740907, i64 2153740974, i64 2153740042, i64 2153740109, i64 2153740176, i64 2153740243, i64 2153740310, i64 2153740377, i64 2153739293, i64 2153739360, i64 2153739427, i64 2153739494, i64 2153739561, i64 2153739628, i64 2153739695, i64 2153739762, i64 2153722639, i64 2153722724, i64 2153722809, i64 2153722894, i64 2153722979, i64 2153742303, i64 2153742188, i64 2153741944, i64 2153742014, i64 2153741702, i64 2153741772, i64 2153741460, i64 2153741530, i64 2153741218, i64 2153741288, i64 2153723136, i64 2153723221, i64 2153723306, i64 2153723391, i64 2153723476, i64 2153747850, i64 2153747923, i64 2153747730, i64 2153747576, i64 2153747422, i64 2153747268, i64 2153747114, i64 2153742899, i64 2153742745, i64 2153742591, i64 2153742437, i64 2153723629, i64 2153723714, i64 2153748857, i64 2153748927, i64 2153748690, i64 2153748760, i64 2153748491, i64 2153748561, i64 2153748292, i64 2153748362, i64 2153748093, i64 2153748163}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
define dso_local void @_Z20Avx512ConvKernel5x32R14ConvController(ptr nocapture noundef nonnull align 8 dereferenceable(184) %0) local_unnamed_addr #0 {
  %2 = getelementptr inbounds i8, ptr %0, i64 152
  %3 = load i8, ptr %2, align 8, !tbaa !5, !range !12, !noundef !13
  %4 = trunc nuw i8 %3 to i1
  br i1 %4, label %5, label %45

5:                                                ; preds = %1
  %6 = getelementptr inbounds i8, ptr %0, i64 8
  %7 = load ptr, ptr %6, align 8, !tbaa !14
  %8 = getelementptr inbounds i8, ptr %0, i64 40
  %9 = load ptr, ptr %8, align 8, !tbaa !15
  %10 = getelementptr inbounds i8, ptr %0, i64 104
  %11 = load i64, ptr %10, align 8, !tbaa !16
  %12 = tail call ptr asm sideeffect "vmovups ($0), %zmm24         \0A\09vmovups 0x40($0), %zmm25     \0A\09addq $$0x80, $0                \0A\09mov $$1, %eax                        \0A\09vmovd %eax, %xmm0                  \0A\09vpbroadcastw %xmm0, %zmm31         \0A\09movq $2, %rax                 \0A\09andq $$0x1, %rax                     \0A\09jne 0f                               \0A\09vmovups ($1), %zmm0                       \0A\09vmovups 0x40($1), %zmm1                   \0A\09vmovups %zmm0, %zmm2                   \0A\09vmovups %zmm1, %zmm3                   \0A\09vmovups %zmm0, %zmm4                   \0A\09vmovups %zmm1, %zmm5                   \0A\09vmovups %zmm0, %zmm6                   \0A\09vmovups %zmm1, %zmm7                   \0A\09vmovups %zmm0, %zmm8                   \0A\09vmovups %zmm1, %zmm9                   \0A\09jmp 1f                               \0A\09.align 16                            \0A\090:                                   \0A\09vxorps %zmm0, %zmm0, %zmm0    \0A\09vxorps %zmm1, %zmm1, %zmm1    \0A\09vxorps %zmm2, %zmm2, %zmm2    \0A\09vxorps %zmm3, %zmm3, %zmm3    \0A\09vxorps %zmm4, %zmm4, %zmm4    \0A\09vxorps %zmm5, %zmm5, %zmm5    \0A\09vxorps %zmm6, %zmm6, %zmm6    \0A\09vxorps %zmm7, %zmm7, %zmm7    \0A\09vxorps %zmm8, %zmm8, %zmm8    \0A\09vxorps %zmm9, %zmm9, %zmm9    \0A\09.align 16                            \0A\091:                                   \0A\09", "=r,r,r,0,~{rax},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %9, i64 %11, ptr %7) #1, !srcloc !17
  store ptr %12, ptr %6, align 8, !tbaa !14
  %13 = getelementptr inbounds i8, ptr %0, i64 48
  %14 = load i64, ptr %13, align 8, !tbaa !18
  %15 = load ptr, ptr %0, align 8, !tbaa !19
  %16 = getelementptr inbounds i8, ptr %0, i64 64
  %17 = load i64, ptr %16, align 8, !tbaa !20
  %18 = getelementptr inbounds i8, ptr %0, i64 56
  %19 = load i64, ptr %18, align 8, !tbaa !21
  %20 = getelementptr inbounds i8, ptr %0, i64 72
  %21 = load ptr, ptr %20, align 8, !tbaa !22
  %22 = getelementptr inbounds i8, ptr %0, i64 80
  %23 = load i64, ptr %22, align 8, !tbaa !23
  %24 = getelementptr inbounds i8, ptr %0, i64 88
  %25 = load i64, ptr %24, align 8, !tbaa !24
  %26 = getelementptr inbounds i8, ptr %0, i64 112
  %27 = load i64, ptr %26, align 8, !tbaa !25
  %28 = getelementptr inbounds i8, ptr %0, i64 168
  %29 = load i64, ptr %28, align 8, !tbaa !26
  %30 = getelementptr inbounds i8, ptr %0, i64 120
  %31 = load i64, ptr %30, align 8, !tbaa !27
  %32 = tail call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x0($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x80($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x100($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09movq ($5), %r10                     \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq 0x8($5), %rax               \0A\09movq 0x10($5), %r10                 \0A\09vmovups 0x180($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09addq %r10, %rax                         \0A\09addq 0x18($5), %rax              \0A\09movq 0x20($5), %r10                 \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %17, i64 %19, ptr %21, i64 %23, i64 %25, i64 %27, i64 %29, i64 %31, i64 %14, ptr %15, ptr %12) #1, !srcloc !28
  %33 = extractvalue { i64, ptr, ptr } %32, 0
  %34 = extractvalue { i64, ptr, ptr } %32, 1
  %35 = extractvalue { i64, ptr, ptr } %32, 2
  store i64 %33, ptr %13, align 8, !tbaa !18
  store ptr %34, ptr %0, align 8, !tbaa !19
  store ptr %35, ptr %6, align 8, !tbaa !14
  %36 = getelementptr inbounds i8, ptr %0, i64 16
  %37 = load ptr, ptr %36, align 8, !tbaa !29
  %38 = getelementptr inbounds i8, ptr %0, i64 24
  %39 = load ptr, ptr %38, align 8, !tbaa !30
  %40 = getelementptr inbounds i8, ptr %0, i64 96
  %41 = load i64, ptr %40, align 8, !tbaa !31
  %42 = load i64, ptr %10, align 8, !tbaa !16
  %43 = getelementptr inbounds i8, ptr %0, i64 144
  %44 = load ptr, ptr %43, align 8, !tbaa !32
  tail call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %37, ptr %39, i64 %41, i64 %42, ptr %44) #1, !srcloc !33
  br label %99

45:                                               ; preds = %1
  %46 = getelementptr inbounds i8, ptr %0, i64 136
  %47 = load i64, ptr %46, align 8, !tbaa !34
  %48 = icmp sgt i64 %47, 1
  %49 = getelementptr inbounds i8, ptr %0, i64 8
  %50 = load ptr, ptr %49, align 8, !tbaa !14
  %51 = getelementptr inbounds i8, ptr %0, i64 40
  %52 = load ptr, ptr %51, align 8, !tbaa !15
  %53 = getelementptr inbounds i8, ptr %0, i64 104
  %54 = load i64, ptr %53, align 8, !tbaa !16
  %55 = tail call ptr asm sideeffect "vmovups ($0), %zmm24         \0A\09vmovups 0x40($0), %zmm25     \0A\09addq $$0x80, $0                \0A\09mov $$1, %eax                        \0A\09vmovd %eax, %xmm0                  \0A\09vpbroadcastw %xmm0, %zmm31         \0A\09movq $2, %rax                 \0A\09andq $$0x1, %rax                     \0A\09jne 0f                               \0A\09vmovups ($1), %zmm0                       \0A\09vmovups 0x40($1), %zmm1                   \0A\09vmovups %zmm0, %zmm2                   \0A\09vmovups %zmm1, %zmm3                   \0A\09vmovups %zmm0, %zmm4                   \0A\09vmovups %zmm1, %zmm5                   \0A\09vmovups %zmm0, %zmm6                   \0A\09vmovups %zmm1, %zmm7                   \0A\09vmovups %zmm0, %zmm8                   \0A\09vmovups %zmm1, %zmm9                   \0A\09jmp 1f                               \0A\09.align 16                            \0A\090:                                   \0A\09vxorps %zmm0, %zmm0, %zmm0    \0A\09vxorps %zmm1, %zmm1, %zmm1    \0A\09vxorps %zmm2, %zmm2, %zmm2    \0A\09vxorps %zmm3, %zmm3, %zmm3    \0A\09vxorps %zmm4, %zmm4, %zmm4    \0A\09vxorps %zmm5, %zmm5, %zmm5    \0A\09vxorps %zmm6, %zmm6, %zmm6    \0A\09vxorps %zmm7, %zmm7, %zmm7    \0A\09vxorps %zmm8, %zmm8, %zmm8    \0A\09vxorps %zmm9, %zmm9, %zmm9    \0A\09.align 16                            \0A\091:                                   \0A\09", "=r,r,r,0,~{rax},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %52, i64 %54, ptr %50) #1
  store ptr %55, ptr %49, align 8, !tbaa !14
  %56 = getelementptr inbounds i8, ptr %0, i64 48
  %57 = load i64, ptr %56, align 8, !tbaa !18
  %58 = load ptr, ptr %0, align 8, !tbaa !19
  %59 = getelementptr inbounds i8, ptr %0, i64 64
  %60 = load i64, ptr %59, align 8, !tbaa !20
  %61 = getelementptr inbounds i8, ptr %0, i64 56
  %62 = load i64, ptr %61, align 8, !tbaa !21
  %63 = getelementptr inbounds i8, ptr %0, i64 72
  %64 = load ptr, ptr %63, align 8, !tbaa !22
  %65 = getelementptr inbounds i8, ptr %0, i64 80
  %66 = load i64, ptr %65, align 8, !tbaa !23
  %67 = getelementptr inbounds i8, ptr %0, i64 88
  %68 = load i64, ptr %67, align 8, !tbaa !24
  %69 = getelementptr inbounds i8, ptr %0, i64 112
  %70 = load i64, ptr %69, align 8, !tbaa !25
  %71 = getelementptr inbounds i8, ptr %0, i64 168
  %72 = load i64, ptr %71, align 8, !tbaa !26
  %73 = getelementptr inbounds i8, ptr %0, i64 120
  %74 = load i64, ptr %73, align 8, !tbaa !27
  %75 = getelementptr inbounds i8, ptr %0, i64 16
  %76 = getelementptr inbounds i8, ptr %0, i64 24
  %77 = getelementptr inbounds i8, ptr %0, i64 96
  %78 = getelementptr inbounds i8, ptr %0, i64 144
  br i1 %48, label %79, label %89

79:                                               ; preds = %45
  %80 = tail call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x0($2), %zmm26         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x80($2), %zmm24         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x100($2), %zmm26         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd (%rax, %r10), %zmm29      \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd (%rax), %zmm30             \0A\09vpbroadcastd (%rax, %r10), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x180($2), %zmm24         \0A\09addq %r10, %rax                         \0A\09addq %r10, %rax                         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %60, i64 %62, ptr %64, i64 %66, i64 %68, i64 %70, i64 %72, i64 %74, i64 %57, ptr %58, ptr %55) #1, !srcloc !35
  %81 = extractvalue { i64, ptr, ptr } %80, 0
  %82 = extractvalue { i64, ptr, ptr } %80, 1
  %83 = extractvalue { i64, ptr, ptr } %80, 2
  store i64 %81, ptr %56, align 8, !tbaa !18
  store ptr %82, ptr %0, align 8, !tbaa !19
  store ptr %83, ptr %49, align 8, !tbaa !14
  %84 = load ptr, ptr %75, align 8, !tbaa !29
  %85 = load ptr, ptr %76, align 8, !tbaa !30
  %86 = load i64, ptr %77, align 8, !tbaa !31
  %87 = load i64, ptr %53, align 8, !tbaa !16
  %88 = load ptr, ptr %78, align 8, !tbaa !32
  tail call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %84, ptr %85, i64 %86, i64 %87, ptr %88) #1, !srcloc !36
  br label %99

89:                                               ; preds = %45
  %90 = tail call { i64, ptr, ptr } asm sideeffect "cmpq $$0, %rcx                                   \0A\09je 4f                                              \0A\09movq ($5), %r10                            \0A\09.align 16                                           \0A\091:                                                  \0A\09mov $3, %rbx                                    \0A\09.align 16                                           \0A\092:                                                  \0A\09mov $4, %r9                                     \0A\09.align 16                                           \0A\093:                                                  \0A\09movq $1, %rax                                \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x0($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x40($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x4, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x80($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0xC0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0x8, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm24, %zmm28, %zmm0           \0A\09vpdpbusd %zmm25, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm24, %zmm29, %zmm2           \0A\09vpdpbusd %zmm25, %zmm29, %zmm3           \0A\09vmovups 0x100($2), %zmm26         \0A\09vpdpbusd %zmm24, %zmm30, %zmm4           \0A\09vpdpbusd %zmm25, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm24, %zmm31, %zmm6           \0A\09vpdpbusd %zmm25, %zmm31, %zmm7           \0A\09vmovups 0x140($2), %zmm27         \0A\09vpdpbusd %zmm24, %zmm28, %zmm8           \0A\09vpdpbusd %zmm25, %zmm28, %zmm9           \0A\09movq $1, %rax                                \0A\09addq $$0xC, %rax                                    \0A\09vpbroadcastd (%rax), %zmm28             \0A\09vpbroadcastd 0x10(%rax), %zmm29      \0A\09vpdpbusd %zmm26, %zmm28, %zmm0           \0A\09vpdpbusd %zmm27, %zmm28, %zmm1           \0A\09vpbroadcastd 0x20(%rax), %zmm30             \0A\09vpbroadcastd 0x30(%rax), %zmm31      \0A\09vpdpbusd %zmm26, %zmm29, %zmm2           \0A\09vpdpbusd %zmm27, %zmm29, %zmm3           \0A\09vmovups 0x180($2), %zmm24         \0A\09vpdpbusd %zmm26, %zmm30, %zmm4           \0A\09vpdpbusd %zmm27, %zmm30, %zmm5           \0A\09vpbroadcastd 0x40(%rax), %zmm28             \0A\09vpdpbusd %zmm26, %zmm31, %zmm6           \0A\09vpdpbusd %zmm27, %zmm31, %zmm7           \0A\09vmovups 0x1C0($2), %zmm25         \0A\09vpdpbusd %zmm26, %zmm28, %zmm8           \0A\09vpdpbusd %zmm27, %zmm28, %zmm9           \0A\09addq $$0x200, $2                              \0A\09addq $6, $1                           \0A\09dec %r9                                            \0A\09jg 3b                                               \0A\09addq $7, $1                           \0A\09dec %rbx                                           \0A\09jg 2b                                               \0A\09addq $8, $1                             \0A\09subq $$0x10, %rcx                                   \0A\09cmpq $$0x10, %rcx                                   \0A\09jge 1b                                              \0A\09subq $8, $1                             \0A\09addq $10, $1                            \0A\09.align 16                                           \0A\094:                                                  \0A\09", "={cx},=r,=r,r,r,r,r,r,r,r,r,0,1,2,~{rax},~{rbx},~{r9},~{r10},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64 %60, i64 %62, ptr %64, i64 %66, i64 %68, i64 %70, i64 %72, i64 %74, i64 %57, ptr %58, ptr %55) #1, !srcloc !37
  %91 = extractvalue { i64, ptr, ptr } %90, 0
  %92 = extractvalue { i64, ptr, ptr } %90, 1
  %93 = extractvalue { i64, ptr, ptr } %90, 2
  store i64 %91, ptr %56, align 8, !tbaa !18
  store ptr %92, ptr %0, align 8, !tbaa !19
  store ptr %93, ptr %49, align 8, !tbaa !14
  %94 = load ptr, ptr %75, align 8, !tbaa !29
  %95 = load ptr, ptr %76, align 8, !tbaa !30
  %96 = load i64, ptr %77, align 8, !tbaa !31
  %97 = load i64, ptr %53, align 8, !tbaa !16
  %98 = load ptr, ptr %78, align 8, !tbaa !32
  tail call void asm sideeffect "movq $0, %rax                             \0A\09movq $2, %rbx                           \0A\09movq $3, %rcx                              \0A\09and $$0x1, %rcx                                   \0A\09je 0f                                             \0A\09vpaddd (%rax), %zmm0, %zmm0                    \0A\09vpaddd (%rax, %rbx), %zmm1, %zmm1             \0A\09vpaddd 0x40(%rax), %zmm2, %zmm2                \0A\09vpaddd 0x40(%rax, %rbx), %zmm3, %zmm3         \0A\09vpaddd 0x80(%rax), %zmm4, %zmm4                \0A\09vpaddd 0x80(%rax, %rbx), %zmm5, %zmm5         \0A\09vpaddd 0xC0(%rax), %zmm6, %zmm6                \0A\09vpaddd 0xC0(%rax, %rbx), %zmm7, %zmm7         \0A\09vpaddd 0x100(%rax), %zmm8, %zmm8               \0A\09vpaddd 0x100(%rax, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\090:                                                \0A\09cmpq $$0x0, $4                               \0A\09jne 1f                                            \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vpxord %zmm15, %zmm15, %zmm15                  \0A\09vpmaxsd %zmm15, %zmm0, %zmm0                    \0A\09vpmaxsd %zmm15, %zmm1, %zmm1                    \0A\09vpmaxsd %zmm15, %zmm2, %zmm2                    \0A\09vpmaxsd %zmm15, %zmm3, %zmm3                    \0A\09vpmaxsd %zmm15, %zmm4, %zmm4                    \0A\09vpmaxsd %zmm15, %zmm5, %zmm5                    \0A\09vpmaxsd %zmm15, %zmm6, %zmm6                    \0A\09vpmaxsd %zmm15, %zmm7, %zmm7                    \0A\09vpmaxsd %zmm15, %zmm8, %zmm8                    \0A\09vpmaxsd %zmm15, %zmm9, %zmm9                    \0A\09jmp 4f                                            \0A\09.align 16                                         \0A\091:                                                \0A\09vbroadcastss ($4), %zmm15               \0A\09vcvtdq2ps %zmm0, %zmm0                       \0A\09vcvtdq2ps %zmm1, %zmm1                       \0A\09vcvtdq2ps %zmm2, %zmm2                       \0A\09vmulps %zmm0, %zmm15, %zmm0              \0A\09vmulps %zmm1, %zmm15, %zmm1              \0A\09vmulps %zmm2, %zmm15, %zmm2              \0A\09vcvtdq2ps %zmm3, %zmm3                       \0A\09vcvtdq2ps %zmm4, %zmm4                       \0A\09vcvtdq2ps %zmm5, %zmm5                       \0A\09vmulps %zmm3, %zmm15, %zmm3              \0A\09vmulps %zmm4, %zmm15, %zmm4              \0A\09vmulps %zmm5, %zmm15, %zmm5              \0A\09vcvtdq2ps %zmm6, %zmm6                       \0A\09vcvtdq2ps %zmm7, %zmm7                       \0A\09vcvtdq2ps %zmm8, %zmm8                       \0A\09vcvtdq2ps %zmm9, %zmm9                       \0A\09vmulps %zmm6, %zmm15, %zmm6              \0A\09vmulps %zmm7, %zmm15, %zmm7              \0A\09vmulps %zmm8, %zmm15, %zmm8              \0A\09vmulps %zmm9, %zmm15, %zmm9              \0A\09.align 16                                         \0A\092:                                                \0A\09movq $3, %rcx                              \0A\09and $$0x2, %rcx                                   \0A\09je 3f                                             \0A\09vaddps ($1), %zmm0, %zmm0                    \0A\09vaddps ($1, %rbx), %zmm1, %zmm1             \0A\09vaddps 0x40($1), %zmm2, %zmm2                \0A\09vaddps 0x40($1, %rbx), %zmm3, %zmm3         \0A\09vaddps 0x80($1), %zmm4, %zmm4                \0A\09vaddps 0x80($1, %rbx), %zmm5, %zmm5         \0A\09vaddps 0xC0($1), %zmm6, %zmm6                \0A\09vaddps 0xC0($1, %rbx), %zmm7, %zmm7         \0A\09vaddps 0x100($1), %zmm8, %zmm8               \0A\09vaddps 0x100($1, %rbx), %zmm9, %zmm9        \0A\09.align 16                                         \0A\093:                                                \0A\09movq $3, %rcx                              \0A\09and $$0xC, %rcx                                   \0A\09je 4f                                             \0A\09vxorps %zmm15, %zmm15, %zmm15                  \0A\09vmaxps %zmm15, %zmm0, %zmm0                    \0A\09vmaxps %zmm15, %zmm1, %zmm1                    \0A\09vmaxps %zmm15, %zmm2, %zmm2                    \0A\09vmaxps %zmm15, %zmm3, %zmm3                    \0A\09vmaxps %zmm15, %zmm4, %zmm4                    \0A\09vmaxps %zmm15, %zmm5, %zmm5                    \0A\09vmaxps %zmm15, %zmm6, %zmm6                    \0A\09vmaxps %zmm15, %zmm7, %zmm7                    \0A\09vmaxps %zmm15, %zmm8, %zmm8                    \0A\09vmaxps %zmm15, %zmm9, %zmm9                    \0A\09.align 16                                         \0A\094:                                                \0A\09vmovups %zmm0, (%rax)                           \0A\09vmovups %zmm1, (%rax, %rbx)                    \0A\09vmovups %zmm2, 0x40(%rax)                       \0A\09vmovups %zmm3, 0x40(%rax, %rbx)                \0A\09vmovups %zmm4, 0x80(%rax)                       \0A\09vmovups %zmm5, 0x80(%rax, %rbx)                \0A\09vmovups %zmm6, 0xC0(%rax)                       \0A\09vmovups %zmm7, 0xC0(%rax, %rbx)                \0A\09vmovups %zmm8, 0x100(%rax)                      \0A\09vmovups %zmm9, 0x100(%rax, %rbx)               \0A\09", "r,r,r,r,r,~{rax},~{rbx},~{rcx},~{zmm0},~{zmm1},~{zmm2},~{zmm3},~{zmm4},~{zmm5},~{zmm6},~{zmm7},~{zmm8},~{zmm9},~{zmm10},~{zmm11},~{zmm12},~{zmm13},~{zmm14},~{zmm15},~{zmm16},~{zmm17},~{zmm18},~{zmm19},~{zmm20},~{zmm21},~{zmm22},~{zmm23},~{zmm24},~{zmm25},~{zmm26},~{zmm27},~{zmm28},~{zmm29},~{zmm30},~{zmm31},~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(ptr %94, ptr %95, i64 %96, i64 %97, ptr %98) #1, !srcloc !38
  br label %99

99:                                               ; preds = %79, %89, %5
  ret void
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 152}
!6 = !{!"_ZTS14ConvController", !7, i64 0, !7, i64 8, !7, i64 16, !7, i64 24, !7, i64 32, !7, i64 40, !10, i64 48, !10, i64 56, !10, i64 64, !7, i64 72, !10, i64 80, !10, i64 88, !10, i64 96, !10, i64 104, !10, i64 112, !10, i64 120, !10, i64 128, !10, i64 136, !7, i64 144, !11, i64 152, !10, i64 160, !10, i64 168, !7, i64 176}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"long", !8, i64 0}
!11 = !{!"bool", !8, i64 0}
!12 = !{i8 0, i8 2}
!13 = !{}
!14 = !{!6, !7, i64 8}
!15 = !{!6, !7, i64 40}
!16 = !{!6, !10, i64 104}
!17 = !{i64 2153649704, i64 2153649744, i64 2153649817, i64 2153649890, i64 2153649963, i64 2153650036, i64 2153650109, i64 2153650182, i64 2153650255, i64 2153650328, i64 2153661056, i64 2153661118, i64 2153660836, i64 2153660901, i64 2153660640, i64 2153660705, i64 2153660444, i64 2153660509, i64 2153660248, i64 2153660313, i64 2153650476, i64 2153650549, i64 2153650622, i64 2153662135, i64 2153662056, i64 2153661952, i64 2153661848, i64 2153661744, i64 2153661640, i64 2153661536, i64 2153661432, i64 2153661328, i64 2153661224, i64 2153650768, i64 2153650841}
!18 = !{!6, !10, i64 48}
!19 = !{!6, !7, i64 0}
!20 = !{!6, !10, i64 64}
!21 = !{!6, !10, i64 56}
!22 = !{!6, !7, i64 72}
!23 = !{!6, !10, i64 80}
!24 = !{!6, !10, i64 88}
!25 = !{!6, !10, i64 112}
!26 = !{!6, !10, i64 168}
!27 = !{!6, !10, i64 120}
!28 = !{i64 2153651578, i64 2153651630, i64 2153651717, i64 2153651805, i64 2153651893, i64 2153651981, i64 2153652069, i64 2153652157, i64 2153652245, i64 2153652333, i64 2153652421, i64 2153652509, i64 2153652597, i64 2153663248, i64 2153663307, i64 2153663366, i64 2153663425, i64 2153663484, i64 2153663543, i64 2153663602, i64 2153663661, i64 2153663720, i64 2153663779, i64 2153663838, i64 2153663897, i64 2153663956, i64 2153662868, i64 2153662927, i64 2153662986, i64 2153663045, i64 2153663104, i64 2153662315, i64 2153662374, i64 2153662433, i64 2153662492, i64 2153662551, i64 2153662610, i64 2153652874, i64 2153652962, i64 2153665151, i64 2153665210, i64 2153665269, i64 2153665328, i64 2153665387, i64 2153665446, i64 2153665505, i64 2153665564, i64 2153665623, i64 2153665682, i64 2153665741, i64 2153665800, i64 2153665859, i64 2153664770, i64 2153664829, i64 2153664888, i64 2153664947, i64 2153665006, i64 2153664216, i64 2153664275, i64 2153664334, i64 2153664393, i64 2153664452, i64 2153664511, i64 2153653239, i64 2153653327, i64 2153667060, i64 2153667119, i64 2153667178, i64 2153667237, i64 2153667296, i64 2153667355, i64 2153667414, i64 2153667473, i64 2153667532, i64 2153667591, i64 2153667650, i64 2153667709, i64 2153667768, i64 2153666677, i64 2153666736, i64 2153666795, i64 2153666854, i64 2153666913, i64 2153666120, i64 2153666179, i64 2153666238, i64 2153666297, i64 2153666356, i64 2153666415, i64 2153653604, i64 2153653692, i64 2153668970, i64 2153669029, i64 2153669088, i64 2153669147, i64 2153669206, i64 2153669265, i64 2153669324, i64 2153669383, i64 2153669442, i64 2153669501, i64 2153669560, i64 2153669619, i64 2153669678, i64 2153668587, i64 2153668646, i64 2153668705, i64 2153668764, i64 2153668823, i64 2153668030, i64 2153668089, i64 2153668148, i64 2153668207, i64 2153668266, i64 2153668325, i64 2153653969, i64 2153654057, i64 2153654145, i64 2153654233, i64 2153654321, i64 2153654409, i64 2153654497, i64 2153654585, i64 2153654673, i64 2153654761, i64 2153654849, i64 2153654937, i64 2153655025, i64 2153655113, i64 2153655201}
!29 = !{!6, !7, i64 16}
!30 = !{!6, !7, i64 24}
!31 = !{!6, !10, i64 96}
!32 = !{!6, !7, i64 144}
!33 = !{i64 2153656504, i64 2153656557, i64 2153656642, i64 2153656727, i64 2153656812, i64 2153656897, i64 2153670904, i64 2153670799, i64 2153670570, i64 2153670640, i64 2153670343, i64 2153670413, i64 2153670116, i64 2153670186, i64 2153669889, i64 2153669959, i64 2153657049, i64 2153657134, i64 2153657219, i64 2153657304, i64 2153657389, i64 2153657474, i64 2153657559, i64 2153672403, i64 2153672476, i64 2153672281, i64 2153672125, i64 2153671969, i64 2153671813, i64 2153671657, i64 2153671501, i64 2153671345, i64 2153671189, i64 2153671033, i64 2153657713, i64 2153657798, i64 2153657883, i64 2153678010, i64 2153678077, i64 2153678144, i64 2153678211, i64 2153678278, i64 2153678345, i64 2153678412, i64 2153677480, i64 2153677547, i64 2153677614, i64 2153677681, i64 2153677748, i64 2153677815, i64 2153672670, i64 2153672737, i64 2153672804, i64 2153672871, i64 2153672938, i64 2153673005, i64 2153673072, i64 2153673139, i64 2153658041, i64 2153658126, i64 2153658211, i64 2153658296, i64 2153658381, i64 2153679741, i64 2153679626, i64 2153679382, i64 2153679452, i64 2153679140, i64 2153679210, i64 2153678898, i64 2153678968, i64 2153678656, i64 2153678726, i64 2153658538, i64 2153658623, i64 2153658708, i64 2153658793, i64 2153658878, i64 2153681227, i64 2153681300, i64 2153681107, i64 2153680953, i64 2153680799, i64 2153680645, i64 2153680491, i64 2153680337, i64 2153680183, i64 2153680029, i64 2153679875, i64 2153659031, i64 2153659116, i64 2153682234, i64 2153682304, i64 2153682067, i64 2153682137, i64 2153681868, i64 2153681938, i64 2153681669, i64 2153681739, i64 2153681470, i64 2153681540}
!34 = !{!6, !10, i64 136}
!35 = !{i64 2153684227, i64 2153684279, i64 2153684366, i64 2153684454, i64 2153684542, i64 2153684630, i64 2153684718, i64 2153684806, i64 2153684894, i64 2153684982, i64 2153685070, i64 2153685158, i64 2153685246, i64 2153695915, i64 2153695974, i64 2153696033, i64 2153696092, i64 2153696151, i64 2153696210, i64 2153696269, i64 2153696328, i64 2153696387, i64 2153696446, i64 2153695519, i64 2153695578, i64 2153695637, i64 2153695696, i64 2153695755, i64 2153694965, i64 2153695024, i64 2153695083, i64 2153695142, i64 2153695201, i64 2153695260, i64 2153685523, i64 2153685611, i64 2153697644, i64 2153697703, i64 2153697762, i64 2153697821, i64 2153697880, i64 2153697939, i64 2153697998, i64 2153698057, i64 2153698116, i64 2153698175, i64 2153697246, i64 2153697305, i64 2153697364, i64 2153697423, i64 2153697482, i64 2153696691, i64 2153696750, i64 2153696809, i64 2153696868, i64 2153696927, i64 2153696986, i64 2153685888, i64 2153685976, i64 2153699379, i64 2153699438, i64 2153699497, i64 2153699556, i64 2153699615, i64 2153699674, i64 2153699733, i64 2153699792, i64 2153699851, i64 2153699910, i64 2153698978, i64 2153699037, i64 2153699096, i64 2153699155, i64 2153699214, i64 2153698420, i64 2153698479, i64 2153698538, i64 2153698597, i64 2153698656, i64 2153698715, i64 2153686253, i64 2153686341, i64 2153701114, i64 2153701173, i64 2153701232, i64 2153701291, i64 2153701350, i64 2153701409, i64 2153701468, i64 2153701527, i64 2153701586, i64 2153701645, i64 2153700713, i64 2153700772, i64 2153700831, i64 2153700890, i64 2153700949, i64 2153700155, i64 2153700214, i64 2153700273, i64 2153700332, i64 2153700391, i64 2153700450, i64 2153686618, i64 2153686706, i64 2153686794, i64 2153686882, i64 2153686970, i64 2153687058, i64 2153687146, i64 2153687234, i64 2153687322, i64 2153687410, i64 2153687498, i64 2153687586, i64 2153687674, i64 2153687762, i64 2153687850}
!36 = !{i64 2153689153, i64 2153689206, i64 2153689291, i64 2153689376, i64 2153689461, i64 2153689546, i64 2153702853, i64 2153702748, i64 2153702519, i64 2153702589, i64 2153702292, i64 2153702362, i64 2153702065, i64 2153702135, i64 2153701838, i64 2153701908, i64 2153689698, i64 2153689783, i64 2153689868, i64 2153689953, i64 2153690038, i64 2153690123, i64 2153690208, i64 2153704352, i64 2153704425, i64 2153704230, i64 2153704074, i64 2153703918, i64 2153703762, i64 2153703606, i64 2153703450, i64 2153703294, i64 2153703138, i64 2153702982, i64 2153690362, i64 2153690447, i64 2153690532, i64 2153705898, i64 2153705965, i64 2153706032, i64 2153706099, i64 2153706166, i64 2153706233, i64 2153706300, i64 2153705368, i64 2153705435, i64 2153705502, i64 2153705569, i64 2153705636, i64 2153705703, i64 2153704619, i64 2153704686, i64 2153704753, i64 2153704820, i64 2153704887, i64 2153704954, i64 2153705021, i64 2153705088, i64 2153690690, i64 2153690775, i64 2153690860, i64 2153690945, i64 2153691030, i64 2153711690, i64 2153711575, i64 2153711331, i64 2153711401, i64 2153711089, i64 2153711159, i64 2153710847, i64 2153710917, i64 2153710605, i64 2153710675, i64 2153691187, i64 2153691272, i64 2153691357, i64 2153691442, i64 2153691527, i64 2153713176, i64 2153713249, i64 2153713056, i64 2153712902, i64 2153712748, i64 2153712594, i64 2153712440, i64 2153712286, i64 2153712132, i64 2153711978, i64 2153711824, i64 2153691680, i64 2153691765, i64 2153714183, i64 2153714253, i64 2153714016, i64 2153714086, i64 2153713817, i64 2153713887, i64 2153713618, i64 2153713688, i64 2153713419, i64 2153713489}
!37 = !{i64 2153716176, i64 2153716228, i64 2153716315, i64 2153716403, i64 2153716491, i64 2153716579, i64 2153716667, i64 2153716755, i64 2153716843, i64 2153716931, i64 2153717019, i64 2153717107, i64 2153717195, i64 2153728413, i64 2153728470, i64 2153728529, i64 2153728588, i64 2153728672, i64 2153728729, i64 2153728788, i64 2153728847, i64 2153728906, i64 2153728965, i64 2153729024, i64 2153729144, i64 2153726916, i64 2153726975, i64 2153727034, i64 2153727093, i64 2153727152, i64 2153717472, i64 2153717560, i64 2153730817, i64 2153730874, i64 2153730933, i64 2153730992, i64 2153731076, i64 2153731133, i64 2153731192, i64 2153731251, i64 2153731310, i64 2153731369, i64 2153731428, i64 2153731549, i64 2153729311, i64 2153729370, i64 2153729429, i64 2153729488, i64 2153729547, i64 2153717837, i64 2153717925, i64 2153733241, i64 2153733298, i64 2153733357, i64 2153733416, i64 2153733500, i64 2153733557, i64 2153733616, i64 2153733675, i64 2153733734, i64 2153733793, i64 2153733852, i64 2153733974, i64 2153731716, i64 2153731775, i64 2153731834, i64 2153731893, i64 2153731952, i64 2153718202, i64 2153718290, i64 2153735666, i64 2153735723, i64 2153735782, i64 2153735841, i64 2153735925, i64 2153735982, i64 2153736041, i64 2153736100, i64 2153736159, i64 2153736218, i64 2153736277, i64 2153736399, i64 2153734141, i64 2153734200, i64 2153734259, i64 2153734318, i64 2153734377, i64 2153718567, i64 2153718655, i64 2153718743, i64 2153718831, i64 2153718919, i64 2153719007, i64 2153719095, i64 2153719183, i64 2153719271, i64 2153719359, i64 2153719447, i64 2153719535, i64 2153719623, i64 2153719711, i64 2153719799}
!38 = !{i64 2153721102, i64 2153721155, i64 2153721240, i64 2153721325, i64 2153721410, i64 2153721495, i64 2153737527, i64 2153737422, i64 2153737193, i64 2153737263, i64 2153736966, i64 2153737036, i64 2153736739, i64 2153736809, i64 2153736512, i64 2153736582, i64 2153721647, i64 2153721732, i64 2153721817, i64 2153721902, i64 2153721987, i64 2153722072, i64 2153722157, i64 2153739026, i64 2153739099, i64 2153738904, i64 2153738748, i64 2153738592, i64 2153738436, i64 2153738280, i64 2153738124, i64 2153737968, i64 2153737812, i64 2153737656, i64 2153722311, i64 2153722396, i64 2153722481, i64 2153740572, i64 2153740639, i64 2153740706, i64 2153740773, i64 2153740840, i64 2153740907, i64 2153740974, i64 2153740042, i64 2153740109, i64 2153740176, i64 2153740243, i64 2153740310, i64 2153740377, i64 2153739293, i64 2153739360, i64 2153739427, i64 2153739494, i64 2153739561, i64 2153739628, i64 2153739695, i64 2153739762, i64 2153722639, i64 2153722724, i64 2153722809, i64 2153722894, i64 2153722979, i64 2153742303, i64 2153742188, i64 2153741944, i64 2153742014, i64 2153741702, i64 2153741772, i64 2153741460, i64 2153741530, i64 2153741218, i64 2153741288, i64 2153723136, i64 2153723221, i64 2153723306, i64 2153723391, i64 2153723476, i64 2153747850, i64 2153747923, i64 2153747730, i64 2153747576, i64 2153747422, i64 2153747268, i64 2153747114, i64 2153742899, i64 2153742745, i64 2153742591, i64 2153742437, i64 2153723629, i64 2153723714, i64 2153748857, i64 2153748927, i64 2153748690, i64 2153748760, i64 2153748491, i64 2153748561, i64 2153748292, i64 2153748362, i64 2153748093, i64 2153748163}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass