; LLVM IR from facebookresearch/habitat-sim :: src/deps/basis-universal/encoder (basisu_backend)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.basisu::basisu_backend" = type { ptr, %"struct.basisu::basisu_backend_params", %"class.basisu::vector", %"struct.basisu::basisu_backend_output", ptr, %"class.basisu::vector.6", %"class.basisu::vector.8", %"class.basisu::vector.10", %"class.basisu::vector.12", %"class.basisu::vector.14", %"class.basisu::vector.14", %"class.basisu::vector.16", %"class.basisu::vector.16", %"class.basisu::vector.14", %"class.basisu::vector.14" }
%"struct.basisu::basisu_backend_params" = type <{ i8, i8, i8, i8, float, float, i32, i8, [3 x i8], i32, i32, i8, i8, [2 x i8] }>
%"class.basisu::vector" = type { ptr, i32, i32 }
%"struct.basisu::basisu_backend_output" = type { i32, i8, i8, i8, i32, i32, %"class.basisu::vector.0", %"class.basisu::vector.0", %"class.basisu::vector", %"class.basisu::vector.0", %"class.basisu::vector.2", %"class.basisu::vector.4" }
%"class.basisu::vector.0" = type { ptr, i32, i32 }
%"class.basisu::vector.2" = type { ptr, i32, i32 }
%"class.basisu::vector.4" = type { ptr, i32, i32 }
%"class.basisu::vector.6" = type { ptr, i32, i32 }
%"class.basisu::vector.8" = type { ptr, i32, i32 }
%"class.basisu::vector.10" = type { ptr, i32, i32 }
%"class.basisu::vector.12" = type { ptr, i32, i32 }
%"class.basisu::vector.16" = type { ptr, i32, i32 }
%"class.basisu::vector.14" = type { ptr, i32, i32 }
%"struct.basisu::basisu_backend_slice_desc" = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, [2 x i8] }>

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK6basisu6vectorINS_25basisu_backend_slice_descEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZN6basisu14basisu_backend16find_video_frameEii(ptr noundef nonnull align 8 dereferenceable(336) %0, i32 noundef %1, i32 noundef %2) #2 align 2 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #3
  store i32 0, ptr %8, align 4, !tbaa !9
  br label %11

11:                                               ; preds = %100, %3
  %12 = load i32, ptr %8, align 4, !tbaa !9
  %13 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %14 = call noundef i32 @_ZNK6basisu6vectorINS_25basisu_backend_slice_descEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %13)
  %15 = icmp ult i32 %12, %14
  br i1 %15, label %17, label %16

16:                                               ; preds = %11
  store i32 2, ptr %9, align 4
  br label %103

17:                                               ; preds = %11
  %18 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %19 = load i32, ptr %8, align 4, !tbaa !9
  %20 = zext i32 %19 to i64
  %21 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %18, i64 noundef %20)
  %22 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %21, i32 0, i32 9
  %23 = load i32, ptr %22, align 4, !tbaa !11
  %24 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %25 = load i32, ptr %6, align 4, !tbaa !9
  %26 = sext i32 %25 to i64
  %27 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %24, i64 noundef %26)
  %28 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %27, i32 0, i32 9
  %29 = load i32, ptr %28, align 4, !tbaa !11
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = add nsw i32 %29, %30
  %32 = icmp ne i32 %23, %31
  br i1 %32, label %33, label %34

33:                                               ; preds = %17
  br label %100

34:                                               ; preds = %17
  %35 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %36 = load i32, ptr %8, align 4, !tbaa !9
  %37 = zext i32 %36 to i64
  %38 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %35, i64 noundef %37)
  %39 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %38, i32 0, i32 10
  %40 = load i32, ptr %39, align 4, !tbaa !14
  %41 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %42 = load i32, ptr %6, align 4, !tbaa !9
  %43 = sext i32 %42 to i64
  %44 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %41, i64 noundef %43)
  %45 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %44, i32 0, i32 10
  %46 = load i32, ptr %45, align 4, !tbaa !14
  %47 = icmp ne i32 %40, %46
  br i1 %47, label %48, label %49

48:                                               ; preds = %34
  br label %100

49:                                               ; preds = %34
  %50 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %51 = load i32, ptr %8, align 4, !tbaa !9
  %52 = zext i32 %51 to i64
  %53 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %50, i64 noundef %52)
  %54 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %53, i32 0, i32 5
  %55 = load i32, ptr %54, align 4, !tbaa !15
  %56 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %57 = load i32, ptr %6, align 4, !tbaa !9
  %58 = sext i32 %57 to i64
  %59 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %56, i64 noundef %58)
  %60 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %59, i32 0, i32 5
  %61 = load i32, ptr %60, align 4, !tbaa !15
  %62 = icmp ne i32 %55, %61
  br i1 %62, label %63, label %64

63:                                               ; preds = %49
  br label %100

64:                                               ; preds = %49
  %65 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %66 = load i32, ptr %8, align 4, !tbaa !9
  %67 = zext i32 %66 to i64
  %68 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %65, i64 noundef %67)
  %69 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %68, i32 0, i32 6
  %70 = load i32, ptr %69, align 4, !tbaa !16
  %71 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %72 = load i32, ptr %6, align 4, !tbaa !9
  %73 = sext i32 %72 to i64
  %74 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %71, i64 noundef %73)
  %75 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %74, i32 0, i32 6
  %76 = load i32, ptr %75, align 4, !tbaa !16
  %77 = icmp ne i32 %70, %76
  br i1 %77, label %78, label %79

78:                                               ; preds = %64
  br label %100

79:                                               ; preds = %64
  %80 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %81 = load i32, ptr %8, align 4, !tbaa !9
  %82 = zext i32 %81 to i64
  %83 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %80, i64 noundef %82)
  %84 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %83, i32 0, i32 11
  %85 = load i8, ptr %84, align 4, !tbaa !17, !range !18, !noundef !19
  %86 = trunc i8 %85 to i1
  %87 = zext i1 %86 to i32
  %88 = getelementptr inbounds %"class.basisu::basisu_backend", ptr %10, i32 0, i32 2
  %89 = load i32, ptr %6, align 4, !tbaa !9
  %90 = sext i32 %89 to i64
  %91 = call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %88, i64 noundef %90)
  %92 = getelementptr inbounds %"struct.basisu::basisu_backend_slice_desc", ptr %91, i32 0, i32 11
  %93 = load i8, ptr %92, align 4, !tbaa !17, !range !18, !noundef !19
  %94 = trunc i8 %93 to i1
  %95 = zext i1 %94 to i32
  %96 = icmp ne i32 %87, %95
  br i1 %96, label %97, label %98

97:                                               ; preds = %79
  br label %100

98:                                               ; preds = %79
  %99 = load i32, ptr %8, align 4, !tbaa !9
  store i32 %99, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %103

100:                                              ; preds = %97, %78, %63, %48, %33
  %101 = load i32, ptr %8, align 4, !tbaa !9
  %102 = add i32 %101, 1
  store i32 %102, ptr %8, align 4, !tbaa !9
  br label %11, !llvm.loop !20

103:                                              ; preds = %98, %16
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #3
  %104 = load i32, ptr %9, align 4
  switch i32 %104, label %108 [
    i32 2, label %105
    i32 1, label %106
  ]

105:                                              ; preds = %103
  store i32 -1, ptr %4, align 4
  br label %106

106:                                              ; preds = %105, %103
  %107 = load i32, ptr %4, align 4
  ret i32 %107

108:                                              ; preds = %103
  unreachable
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 36}
!12 = !{!"_ZTSN6basisu25basisu_backend_slice_descE", !10, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !10, i64 16, !10, i64 20, !10, i64 24, !10, i64 28, !10, i64 32, !10, i64 36, !10, i64 40, !13, i64 44, !13, i64 45}
!13 = !{!"bool", !7, i64 0}
!14 = !{!12, !10, i64 40}
!15 = !{!12, !10, i64 20}
!16 = !{!12, !10, i64 24}
!17 = !{!12, !13, i64 44}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = distinct !{!20, !21}
!21 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef i32 @_ZNK6basisu6vectorINS_25basisu_backend_slice_descEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_ZN6basisu14basisu_backend16find_video_frameEii(ptr noundef nonnull align 8 dereferenceable(336) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #1 align 2 {
  %4 = getelementptr inbounds i8, ptr %0, i64 40
  %5 = tail call noundef i32 @_ZNK6basisu6vectorINS_25basisu_backend_slice_descEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %4)
  %.not2223.not = icmp eq i32 %5, 0
  br i1 %.not2223.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %3
  %6 = sext i32 %1 to i64
  br label %7

7:                                                ; preds = %.lr.ph, %43
  %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %43 ]
  %8 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %indvars.iv)
  %9 = getelementptr inbounds i8, ptr %8, i64 36
  %10 = load i32, ptr %9, align 4, !tbaa !5
  %11 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %6)
  %12 = getelementptr inbounds i8, ptr %11, i64 36
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = add nsw i32 %13, %2
  %.not = icmp eq i32 %10, %14
  br i1 %.not, label %15, label %43

15:                                               ; preds = %7
  %16 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %indvars.iv)
  %17 = getelementptr inbounds i8, ptr %16, i64 40
  %18 = load i32, ptr %17, align 4, !tbaa !11
  %19 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %6)
  %20 = getelementptr inbounds i8, ptr %19, i64 40
  %21 = load i32, ptr %20, align 4, !tbaa !11
  %.not18 = icmp eq i32 %18, %21
  br i1 %.not18, label %22, label %43

22:                                               ; preds = %15
  %23 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %indvars.iv)
  %24 = getelementptr inbounds i8, ptr %23, i64 20
  %25 = load i32, ptr %24, align 4, !tbaa !12
  %26 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %6)
  %27 = getelementptr inbounds i8, ptr %26, i64 20
  %28 = load i32, ptr %27, align 4, !tbaa !12
  %.not19 = icmp eq i32 %25, %28
  br i1 %.not19, label %29, label %43

29:                                               ; preds = %22
  %30 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %indvars.iv)
  %31 = getelementptr inbounds i8, ptr %30, i64 24
  %32 = load i32, ptr %31, align 4, !tbaa !13
  %33 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %6)
  %34 = getelementptr inbounds i8, ptr %33, i64 24
  %35 = load i32, ptr %34, align 4, !tbaa !13
  %.not20 = icmp eq i32 %32, %35
  br i1 %.not20, label %36, label %43

36:                                               ; preds = %29
  %37 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %indvars.iv)
  %38 = getelementptr inbounds i8, ptr %37, i64 44
  %39 = load i8, ptr %38, align 4, !tbaa !14, !range !15, !noundef !16
  %40 = tail call noundef nonnull align 4 dereferenceable(46) ptr @_ZN6basisu6vectorINS_25basisu_backend_slice_descEEixEm(ptr noundef nonnull align 8 dereferenceable(16) %4, i64 noundef %6)
  %41 = getelementptr inbounds i8, ptr %40, i64 44
  %42 = load i8, ptr %41, align 4, !tbaa !14, !range !15, !noundef !16
  %.not21 = icmp eq i8 %39, %42
  br i1 %.not21, label %._crit_edge.loopexit.split.loop.exit, label %43

43:                                               ; preds = %36, %29, %22, %15, %7
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %44 = tail call noundef i32 @_ZNK6basisu6vectorINS_25basisu_backend_slice_descEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(16) %4)
  %45 = zext i32 %44 to i64
  %.not22 = icmp ult i64 %indvars.iv.next, %45
  br i1 %.not22, label %7, label %._crit_edge, !llvm.loop !17

._crit_edge.loopexit.split.loop.exit:             ; preds = %36
  %46 = trunc nuw i64 %indvars.iv to i32
  br label %._crit_edge

._crit_edge:                                      ; preds = %43, %._crit_edge.loopexit.split.loop.exit, %3
  %spec.select = phi i32 [ -1, %3 ], [ %46, %._crit_edge.loopexit.split.loop.exit ], [ -1, %43 ]
  ret i32 %spec.select
}

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 36}
!6 = !{!"_ZTSN6basisu25basisu_backend_slice_descE", !7, i64 0, !7, i64 4, !7, i64 8, !7, i64 12, !7, i64 16, !7, i64 20, !7, i64 24, !7, i64 28, !7, i64 32, !7, i64 36, !7, i64 40, !10, i64 44, !10, i64 45}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"bool", !8, i64 0}
!11 = !{!6, !7, i64 40}
!12 = !{!6, !7, i64 20}
!13 = !{!6, !7, i64 24}
!14 = !{!6, !10, i64 44}
!15 = !{i8 0, i8 2}
!16 = !{}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass