; LLVM IR from facebookresearch/habitat-sim :: src/deps/basis-universal/encoder (basisu_pvrtc1_4)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.basisu::color_rgba" = type { %union.anon }
%union.anon = type { [4 x i8] }
%"struct.basisu::pvrtc4_block" = type { i32, i32 }

@.str.3 = external hidden unnamed_addr constant [115 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@__PRETTY_FUNCTION__._ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej = external hidden unnamed_addr constant [67 x i8], align 1
@.str.6 = external hidden unnamed_addr constant [45 x i8], align 1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN6basisu10color_rgbaC2Eiiii(ptr noundef nonnull align 1 dereferenceable(4), i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: mustprogress uwtable
define dso_local i32 @_ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej(ptr noundef nonnull align 4 dereferenceable(8) %0, i32 noundef %1) #3 align 2 {
  %3 = alloca %"class.basisu::color_rgba", align 1
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %11 = load ptr, ptr %4, align 8
  %12 = load i32, ptr %5, align 4, !tbaa !9
  %13 = icmp ult i32 %12, 2
  br i1 %13, label %14, label %15

14:                                               ; preds = %2
  br label %17

15:                                               ; preds = %2
  call void @__assert_fail(ptr noundef @.str.4, ptr noundef @.str.3, i32 noundef 240, ptr noundef @__PRETTY_FUNCTION__._ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej) #4
  unreachable

16:                                               ; No predecessors!
  br label %17

17:                                               ; preds = %16, %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #5
  %18 = getelementptr inbounds %"struct.basisu::pvrtc4_block", ptr %11, i32 0, i32 1
  %19 = load i32, ptr %18, align 4, !tbaa !11
  %20 = load i32, ptr %5, align 4, !tbaa !9
  %21 = mul i32 %20, 16
  %22 = lshr i32 %19, %21
  store i32 %22, ptr %6, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.start.p0(i64 4, ptr %10) #5
  %23 = load i32, ptr %6, align 4, !tbaa !9
  %24 = and i32 %23, 32768
  %25 = icmp ne i32 %24, 0
  br i1 %25, label %26, label %54

26:                                               ; preds = %17
  %27 = load i32, ptr %5, align 4, !tbaa !9
  %28 = icmp ne i32 %27, 0
  br i1 %28, label %44, label %29

29:                                               ; preds = %26
  %30 = load i32, ptr %6, align 4, !tbaa !9
  %31 = lshr i32 %30, 10
  %32 = and i32 %31, 31
  store i32 %32, ptr %7, align 4, !tbaa !9
  %33 = load i32, ptr %6, align 4, !tbaa !9
  %34 = lshr i32 %33, 5
  %35 = and i32 %34, 31
  store i32 %35, ptr %8, align 4, !tbaa !9
  %36 = load i32, ptr %6, align 4, !tbaa !9
  %37 = lshr i32 %36, 1
  %38 = and i32 %37, 15
  store i32 %38, ptr %9, align 4, !tbaa !9
  %39 = load i32, ptr %9, align 4, !tbaa !9
  %40 = shl i32 %39, 1
  %41 = load i32, ptr %9, align 4, !tbaa !9
  %42 = lshr i32 %41, 3
  %43 = or i32 %40, %42
  store i32 %43, ptr %9, align 4, !tbaa !9
  br label %53

44:                                               ; preds = %26
  %45 = load i32, ptr %6, align 4, !tbaa !9
  %46 = lshr i32 %45, 10
  %47 = and i32 %46, 31
  store i32 %47, ptr %7, align 4, !tbaa !9
  %48 = load i32, ptr %6, align 4, !tbaa !9
  %49 = lshr i32 %48, 5
  %50 = and i32 %49, 31
  store i32 %50, ptr %8, align 4, !tbaa !9
  %51 = load i32, ptr %6, align 4, !tbaa !9
  %52 = and i32 %51, 31
  store i32 %52, ptr %9, align 4, !tbaa !9
  br label %53

53:                                               ; preds = %44, %29
  store i32 15, ptr %10, align 4, !tbaa !9
  br label %117

54:                                               ; preds = %17
  %55 = load i32, ptr %5, align 4, !tbaa !9
  %56 = icmp ne i32 %55, 0
  br i1 %56, label %87, label %57

57:                                               ; preds = %54
  %58 = load i32, ptr %6, align 4, !tbaa !9
  %59 = lshr i32 %58, 12
  %60 = and i32 %59, 7
  store i32 %60, ptr %10, align 4, !tbaa !9
  %61 = load i32, ptr %6, align 4, !tbaa !9
  %62 = lshr i32 %61, 8
  %63 = and i32 %62, 15
  store i32 %63, ptr %7, align 4, !tbaa !9
  %64 = load i32, ptr %6, align 4, !tbaa !9
  %65 = lshr i32 %64, 4
  %66 = and i32 %65, 15
  store i32 %66, ptr %8, align 4, !tbaa !9
  %67 = load i32, ptr %6, align 4, !tbaa !9
  %68 = lshr i32 %67, 1
  %69 = and i32 %68, 7
  store i32 %69, ptr %9, align 4, !tbaa !9
  %70 = load i32, ptr %10, align 4, !tbaa !9
  %71 = shl i32 %70, 1
  store i32 %71, ptr %10, align 4, !tbaa !9
  %72 = load i32, ptr %7, align 4, !tbaa !9
  %73 = shl i32 %72, 1
  %74 = load i32, ptr %7, align 4, !tbaa !9
  %75 = lshr i32 %74, 3
  %76 = or i32 %73, %75
  store i32 %76, ptr %7, align 4, !tbaa !9
  %77 = load i32, ptr %8, align 4, !tbaa !9
  %78 = shl i32 %77, 1
  %79 = load i32, ptr %8, align 4, !tbaa !9
  %80 = lshr i32 %79, 3
  %81 = or i32 %78, %80
  store i32 %81, ptr %8, align 4, !tbaa !9
  %82 = load i32, ptr %9, align 4, !tbaa !9
  %83 = shl i32 %82, 2
  %84 = load i32, ptr %9, align 4, !tbaa !9
  %85 = lshr i32 %84, 1
  %86 = or i32 %83, %85
  store i32 %86, ptr %9, align 4, !tbaa !9
  br label %116

87:                                               ; preds = %54
  %88 = load i32, ptr %6, align 4, !tbaa !9
  %89 = lshr i32 %88, 12
  %90 = and i32 %89, 7
  store i32 %90, ptr %10, align 4, !tbaa !9
  %91 = load i32, ptr %6, align 4, !tbaa !9
  %92 = lshr i32 %91, 8
  %93 = and i32 %92, 15
  store i32 %93, ptr %7, align 4, !tbaa !9
  %94 = load i32, ptr %6, align 4, !tbaa !9
  %95 = lshr i32 %94, 4
  %96 = and i32 %95, 15
  store i32 %96, ptr %8, align 4, !tbaa !9
  %97 = load i32, ptr %6, align 4, !tbaa !9
  %98 = and i32 %97, 15
  store i32 %98, ptr %9, align 4, !tbaa !9
  %99 = load i32, ptr %10, align 4, !tbaa !9
  %100 = shl i32 %99, 1
  store i32 %100, ptr %10, align 4, !tbaa !9
  %101 = load i32, ptr %7, align 4, !tbaa !9
  %102 = shl i32 %101, 1
  %103 = load i32, ptr %7, align 4, !tbaa !9
  %104 = lshr i32 %103, 3
  %105 = or i32 %102, %104
  store i32 %105, ptr %7, align 4, !tbaa !9
  %106 = load i32, ptr %8, align 4, !tbaa !9
  %107 = shl i32 %106, 1
  %108 = load i32, ptr %8, align 4, !tbaa !9
  %109 = lshr i32 %108, 3
  %110 = or i32 %107, %109
  store i32 %110, ptr %8, align 4, !tbaa !9
  %111 = load i32, ptr %9, align 4, !tbaa !9
  %112 = shl i32 %111, 1
  %113 = load i32, ptr %9, align 4, !tbaa !9
  %114 = lshr i32 %113, 3
  %115 = or i32 %112, %114
  store i32 %115, ptr %9, align 4, !tbaa !9
  br label %116

116:                                              ; preds = %87, %57
  br label %117

117:                                              ; preds = %116, %53
  %118 = load i32, ptr %7, align 4, !tbaa !9
  %119 = icmp ult i32 %118, 32
  br i1 %119, label %120, label %129

120:                                              ; preds = %117
  %121 = load i32, ptr %8, align 4, !tbaa !9
  %122 = icmp ult i32 %121, 32
  br i1 %122, label %123, label %129

123:                                              ; preds = %120
  %124 = load i32, ptr %9, align 4, !tbaa !9
  %125 = icmp ult i32 %124, 32
  br i1 %125, label %126, label %129

126:                                              ; preds = %123
  %127 = load i32, ptr %10, align 4, !tbaa !9
  %128 = icmp ult i32 %127, 16
  br label %129

129:                                              ; preds = %126, %123, %120, %117
  %130 = phi i1 [ false, %123 ], [ false, %120 ], [ false, %117 ], [ %128, %126 ]
  br i1 %130, label %131, label %132

131:                                              ; preds = %129
  br label %134

132:                                              ; preds = %129
  call void @__assert_fail(ptr noundef @.str.6, ptr noundef @.str.3, i32 noundef 295, ptr noundef @__PRETTY_FUNCTION__._ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej) #4
  unreachable

133:                                              ; No predecessors!
  br label %134

134:                                              ; preds = %133, %131
  %135 = load i32, ptr %7, align 4, !tbaa !9
  %136 = load i32, ptr %8, align 4, !tbaa !9
  %137 = load i32, ptr %9, align 4, !tbaa !9
  %138 = load i32, ptr %10, align 4, !tbaa !9
  call void @_ZN6basisu10color_rgbaC2Eiiii(ptr noundef nonnull align 1 dereferenceable(4) %3, i32 noundef %135, i32 noundef %136, i32 noundef %137, i32 noundef %138)
  call void @llvm.lifetime.end.p0(i64 4, ptr %10) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #5
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #5
  %139 = getelementptr inbounds %"class.basisu::color_rgba", ptr %3, i32 0, i32 0
  %140 = getelementptr inbounds %union.anon, ptr %139, i32 0, i32 0
  %141 = load i32, ptr %140, align 1
  ret i32 %141
}

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { noreturn nounwind }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !10, i64 4}
!12 = !{!"_ZTSN6basisu12pvrtc4_blockE", !10, i64 0, !10, i64 4}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.basisu::color_rgba" = type { %union.anon }
%union.anon = type { [4 x i8] }

@.str.3 = external hidden unnamed_addr constant [115 x i8], align 1
@.str.4 = external hidden unnamed_addr constant [19 x i8], align 1
@__PRETTY_FUNCTION__._ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej = external hidden unnamed_addr constant [67 x i8], align 1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_ZN6basisu10color_rgbaC2Eiiii(ptr noundef nonnull align 1 dereferenceable(4), i32 noundef, i32 noundef, i32 noundef, i32 noundef) unnamed_addr #0 align 2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local i32 @_ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej(ptr nocapture noundef nonnull readonly align 4 dereferenceable(8) %0, i32 noundef %1) local_unnamed_addr #2 align 2 {
  %3 = alloca %"class.basisu::color_rgba", align 4
  %4 = icmp ult i32 %1, 2
  br i1 %4, label %6, label %5

5:                                                ; preds = %2
  tail call void @__assert_fail(ptr noundef nonnull @.str.4, ptr noundef nonnull @.str.3, i32 noundef 240, ptr noundef nonnull @__PRETTY_FUNCTION__._ZNK6basisu12pvrtc4_block17get_endpoint_5554Ej) #3
  unreachable

6:                                                ; preds = %2
  %7 = getelementptr inbounds i8, ptr %0, i64 4
  %8 = load i32, ptr %7, align 4, !tbaa !5
  %9 = shl nuw nsw i32 %1, 4
  %10 = lshr i32 %8, %9
  %11 = and i32 %10, 32768
  %.not = icmp eq i32 %11, 0
  %.not54 = icmp eq i32 %1, 0
  br i1 %.not, label %22, label %12

12:                                               ; preds = %6
  br i1 %.not54, label %13, label %19

13:                                               ; preds = %12
  %14 = lshr i32 %10, 1
  %15 = and i32 %14, 15
  %16 = shl nuw nsw i32 %15, 1
  %17 = lshr i32 %15, 3
  %18 = or disjoint i32 %16, %17
  br label %21

19:                                               ; preds = %12
  %20 = and i32 %10, 31
  br label %21

21:                                               ; preds = %19, %13
  %.048 = phi i32 [ %20, %19 ], [ %18, %13 ]
  %.049.in = lshr i32 %10, 5
  %.049 = and i32 %.049.in, 31
  %.051.in = lshr i32 %10, 10
  %.051 = and i32 %.051.in, 31
  br label %54

22:                                               ; preds = %6
  %23 = lshr i32 %10, 8
  %24 = and i32 %23, 15
  %25 = lshr i32 %10, 4
  %26 = and i32 %25, 15
  br i1 %.not54, label %27, label %41

27:                                               ; preds = %22
  %28 = lshr i32 %10, 1
  %29 = and i32 %28, 7
  %30 = lshr i32 %10, 11
  %31 = and i32 %30, 14
  %32 = shl nuw nsw i32 %24, 1
  %33 = lshr i32 %24, 3
  %34 = or disjoint i32 %32, %33
  %35 = shl nuw nsw i32 %26, 1
  %36 = lshr i32 %26, 3
  %37 = or disjoint i32 %35, %36
  %38 = shl nuw nsw i32 %29, 2
  %39 = lshr i32 %29, 1
  %40 = or disjoint i32 %38, %39
  br label %54

41:                                               ; preds = %22
  %42 = and i32 %10, 15
  %43 = lshr i32 %10, 11
  %44 = and i32 %43, 14
  %45 = shl nuw nsw i32 %24, 1
  %46 = lshr i32 %24, 3
  %47 = or disjoint i32 %45, %46
  %48 = shl nuw nsw i32 %26, 1
  %49 = lshr i32 %26, 3
  %50 = or disjoint i32 %48, %49
  %51 = shl nuw nsw i32 %42, 1
  %52 = lshr i32 %42, 3
  %53 = or disjoint i32 %51, %52
  br label %54

54:                                               ; preds = %21, %41, %27
  %.152 = phi i32 [ %.051, %21 ], [ %47, %41 ], [ %34, %27 ]
  %.150 = phi i32 [ %.049, %21 ], [ %50, %41 ], [ %37, %27 ]
  %.1 = phi i32 [ %.048, %21 ], [ %53, %41 ], [ %40, %27 ]
  %.0 = phi i32 [ 15, %21 ], [ %44, %41 ], [ %31, %27 ]
  call void @_ZN6basisu10color_rgbaC2Eiiii(ptr noundef nonnull align 1 dereferenceable(4) %3, i32 noundef %.152, i32 noundef %.150, i32 noundef %.1, i32 noundef %.0)
  %55 = load i32, ptr %3, align 4
  ret i32 %55
}

attributes #0 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 4}
!6 = !{!"_ZTSN6basisu12pvrtc4_blockE", !7, i64 0, !7, i64 4}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass