; LLVM IR from khushmmehta/Scorch-V :: src/ScorchVkEngine/Abstractions/Rendering (BufferManager)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.BufferManager = type { ptr, %"class.std::vector.0", %class.VulkanMemoryAllocator, ptr, ptr, ptr, ptr, ptr, %"class.std::vector.5", %"class.std::vector.10", ptr, ptr, ptr, ptr, %"class.std::vector.15", ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<VkDescriptorSet_T *, std::allocator<VkDescriptorSet_T *>>::_Vector_impl" }
%"struct.std::_Vector_base<VkDescriptorSet_T *, std::allocator<VkDescriptorSet_T *>>::_Vector_impl" = type { %"struct.std::_Vector_base<VkDescriptorSet_T *, std::allocator<VkDescriptorSet_T *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<VkDescriptorSet_T *, std::allocator<VkDescriptorSet_T *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.VulkanMemoryAllocator = type { ptr, ptr }
%"class.std::vector.5" = type { %"struct.std::_Vector_base.6" }
%"struct.std::_Vector_base.6" = type { %"struct.std::_Vector_base<VkBuffer_T *, std::allocator<VkBuffer_T *>>::_Vector_impl" }
%"struct.std::_Vector_base<VkBuffer_T *, std::allocator<VkBuffer_T *>>::_Vector_impl" = type { %"struct.std::_Vector_base<VkBuffer_T *, std::allocator<VkBuffer_T *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<VkBuffer_T *, std::allocator<VkBuffer_T *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.10" = type { %"struct.std::_Vector_base.11" }
%"struct.std::_Vector_base.11" = type { %"struct.std::_Vector_base<void *, std::allocator<void *>>::_Vector_impl" }
%"struct.std::_Vector_base<void *, std::allocator<void *>>::_Vector_impl" = type { %"struct.std::_Vector_base<void *, std::allocator<void *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<void *, std::allocator<void *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.15" = type { %"struct.std::_Vector_base.16" }
%"struct.std::_Vector_base.16" = type { %"struct.std::_Vector_base<VmaAllocation_T *, std::allocator<VmaAllocation_T *>>::_Vector_impl" }
%"struct.std::_Vector_base<VmaAllocation_T *, std::allocator<VmaAllocation_T *>>::_Vector_impl" = type { %"struct.std::_Vector_base<VmaAllocation_T *, std::allocator<VmaAllocation_T *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<VmaAllocation_T *, std::allocator<VmaAllocation_T *>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10VkBuffer_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

declare void @vmaDestroyBuffer(ptr noundef, ptr noundef, ptr noundef) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN13BufferManager21destroyUniformBuffersEv(ptr noundef nonnull align 8 dereferenceable(216) %0) #3 align 2 {
  %2 = alloca ptr, align 8
  %3 = alloca i64, align 8
  store ptr %0, ptr %2, align 8, !tbaa !5
  %4 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #4
  store i64 0, ptr %3, align 8, !tbaa !9
  br label %5

5:                                                ; preds = %28, %1
  %6 = load i64, ptr %3, align 8, !tbaa !9
  %7 = icmp ult i64 %6, 2
  br i1 %7, label %9, label %8

8:                                                ; preds = %5
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #4
  br label %31

9:                                                ; preds = %5
  %10 = getelementptr inbounds %class.BufferManager, ptr %4, i32 0, i32 2
  %11 = getelementptr inbounds %class.VulkanMemoryAllocator, ptr %10, i32 0, i32 0
  %12 = load ptr, ptr %11, align 8, !tbaa !11
  %13 = getelementptr inbounds %class.BufferManager, ptr %4, i32 0, i32 14
  %14 = load i64, ptr %3, align 8, !tbaa !9
  %15 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %13, i64 noundef %14) #4
  %16 = load ptr, ptr %15, align 8, !tbaa !5
  call void @vmaUnmapMemory(ptr noundef %12, ptr noundef %16)
  %17 = getelementptr inbounds %class.BufferManager, ptr %4, i32 0, i32 2
  %18 = getelementptr inbounds %class.VulkanMemoryAllocator, ptr %17, i32 0, i32 0
  %19 = load ptr, ptr %18, align 8, !tbaa !11
  %20 = getelementptr inbounds %class.BufferManager, ptr %4, i32 0, i32 8
  %21 = load i64, ptr %3, align 8, !tbaa !9
  %22 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10VkBuffer_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %21) #4
  %23 = load ptr, ptr %22, align 8, !tbaa !5
  %24 = getelementptr inbounds %class.BufferManager, ptr %4, i32 0, i32 14
  %25 = load i64, ptr %3, align 8, !tbaa !9
  %26 = call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %24, i64 noundef %25) #4
  %27 = load ptr, ptr %26, align 8, !tbaa !5
  call void @vmaDestroyBuffer(ptr noundef %19, ptr noundef %23, ptr noundef %27)
  br label %28

28:                                               ; preds = %9
  %29 = load i64, ptr %3, align 8, !tbaa !9
  %30 = add i64 %29, 1
  store i64 %30, ptr %3, align 8, !tbaa !9
  br label %5, !llvm.loop !30

31:                                               ; preds = %8
  ret void
}

declare void @vmaUnmapMemory(ptr noundef, ptr noundef) #2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !6, i64 32}
!12 = !{!"_ZTS13BufferManager", !6, i64 0, !13, i64 8, !17, i64 32, !6, i64 48, !6, i64 56, !6, i64 64, !6, i64 72, !6, i64 80, !18, i64 88, !22, i64 112, !6, i64 136, !6, i64 144, !6, i64 152, !6, i64 160, !26, i64 168, !6, i64 192, !6, i64 200, !6, i64 208}
!13 = !{!"_ZTSSt6vectorIP17VkDescriptorSet_TSaIS1_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTS21VulkanMemoryAllocator", !6, i64 0, !6, i64 8}
!18 = !{!"_ZTSSt6vectorIP10VkBuffer_TSaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIP10VkBuffer_TSaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIP10VkBuffer_TSaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIP10VkBuffer_TSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIPvSaIS0_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIPvSaIS0_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIPvSaIS0_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIPvSaIS0_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!"_ZTSSt6vectorIP15VmaAllocation_TSaIS1_EE", !27, i64 0}
!27 = !{!"_ZTSSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE", !28, i64 0}
!28 = !{!"_ZTSNSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE12_Vector_implE", !29, i64 0}
!29 = !{!"_ZTSNSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!30 = distinct !{!30, !31}
!31 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10VkBuffer_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

declare void @vmaDestroyBuffer(ptr noundef, ptr noundef, ptr noundef) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN13BufferManager21destroyUniformBuffersEv(ptr noundef nonnull align 8 dereferenceable(216) %0) local_unnamed_addr #2 align 2 {
  %2 = getelementptr inbounds i8, ptr %0, i64 32
  %3 = getelementptr inbounds i8, ptr %0, i64 168
  %4 = getelementptr inbounds i8, ptr %0, i64 88
  %5 = load ptr, ptr %2, align 8, !tbaa !5
  %6 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef 0) #3
  %7 = load ptr, ptr %6, align 8, !tbaa !27
  tail call void @vmaUnmapMemory(ptr noundef %5, ptr noundef %7)
  %8 = load ptr, ptr %2, align 8, !tbaa !5
  %9 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10VkBuffer_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef 0) #3
  %10 = load ptr, ptr %9, align 8, !tbaa !27
  %11 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef 0) #3
  %12 = load ptr, ptr %11, align 8, !tbaa !27
  tail call void @vmaDestroyBuffer(ptr noundef %8, ptr noundef %10, ptr noundef %12)
  %13 = load ptr, ptr %2, align 8, !tbaa !5
  %14 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef 1) #3
  %15 = load ptr, ptr %14, align 8, !tbaa !27
  tail call void @vmaUnmapMemory(ptr noundef %13, ptr noundef %15)
  %16 = load ptr, ptr %2, align 8, !tbaa !5
  %17 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP10VkBuffer_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef 1) #3
  %18 = load ptr, ptr %17, align 8, !tbaa !27
  %19 = tail call noundef nonnull align 8 dereferenceable(8) ptr @_ZNSt6vectorIP15VmaAllocation_TSaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef 1) #3
  %20 = load ptr, ptr %19, align 8, !tbaa !27
  tail call void @vmaDestroyBuffer(ptr noundef %16, ptr noundef %18, ptr noundef %20)
  ret void
}

declare void @vmaUnmapMemory(ptr noundef, ptr noundef) local_unnamed_addr #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 32}
!6 = !{!"_ZTS13BufferManager", !7, i64 0, !10, i64 8, !14, i64 32, !7, i64 48, !7, i64 56, !7, i64 64, !7, i64 72, !7, i64 80, !15, i64 88, !19, i64 112, !7, i64 136, !7, i64 144, !7, i64 152, !7, i64 160, !23, i64 168, !7, i64 192, !7, i64 200, !7, i64 208}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTSSt6vectorIP17VkDescriptorSet_TSaIS1_EE", !11, i64 0}
!11 = !{!"_ZTSSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE", !12, i64 0}
!12 = !{!"_ZTSNSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE12_Vector_implE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseIP17VkDescriptorSet_TSaIS1_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!14 = !{!"_ZTS21VulkanMemoryAllocator", !7, i64 0, !7, i64 8}
!15 = !{!"_ZTSSt6vectorIP10VkBuffer_TSaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIP10VkBuffer_TSaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIP10VkBuffer_TSaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIP10VkBuffer_TSaIS1_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!19 = !{!"_ZTSSt6vectorIPvSaIS0_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIPvSaIS0_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIPvSaIS0_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIPvSaIS0_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!23 = !{!"_ZTSSt6vectorIP15VmaAllocation_TSaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIP15VmaAllocation_TSaIS1_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!27 = !{!7, !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,LICMPass,LoopRotatePass,SROAPass,SimplifyCFGPass,TailCallElimPass