; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis7/AttributePdu.ll (ZNK3DIS12AttributePdueqERKS0_)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::AttributePdu" = type { %"class.DIS::EntityInformationFamilyPdu.base", [4 x i8], %"class.DIS::SimulationAddress", i32, i16, i8, i8, i32, i8, i8, i16 }
%"class.DIS::EntityInformationFamilyPdu.base" = type { %"class.DIS::Pdu.base" }
%"class.DIS::Pdu.base" = type { %"class.DIS::PduSuperclass.base", i8, i8 }
%"class.DIS::PduSuperclass.base" = type <{ ptr, i8, i8, i8, i8, i32, i16 }>
%"class.DIS::SimulationAddress" = type <{ ptr, i16, i16, [4 x i8] }>

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS12AttributePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) #0 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %6 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #3
  store i8 1, ptr %5, align 1, !tbaa !9
  %7 = load ptr, ptr %4, align 8, !tbaa !5
  %8 = call noundef zeroext i1 @_ZNK3DIS26EntityInformationFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(20) %6, ptr noundef nonnull align 8 dereferenceable(20) %7)
  %9 = zext i1 %8 to i8
  store i8 %9, ptr %5, align 1, !tbaa !9
  %10 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 2
  %11 = load ptr, ptr %4, align 8, !tbaa !5
  %12 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %11, i32 0, i32 2
  %13 = call noundef zeroext i1 @_ZNK3DIS17SimulationAddresseqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %10, ptr noundef nonnull align 8 dereferenceable(12) %12)
  br i1 %13, label %15, label %14

14:                                               ; preds = %2
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %15

15:                                               ; preds = %14, %2
  %16 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 3
  %17 = load i32, ptr %16, align 8, !tbaa !11
  %18 = load ptr, ptr %4, align 8, !tbaa !5
  %19 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %18, i32 0, i32 3
  %20 = load i32, ptr %19, align 8, !tbaa !11
  %21 = icmp eq i32 %17, %20
  br i1 %21, label %23, label %22

22:                                               ; preds = %15
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %23

23:                                               ; preds = %22, %15
  %24 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 4
  %25 = load i16, ptr %24, align 4, !tbaa !19
  %26 = sext i16 %25 to i32
  %27 = load ptr, ptr %4, align 8, !tbaa !5
  %28 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %27, i32 0, i32 4
  %29 = load i16, ptr %28, align 4, !tbaa !19
  %30 = sext i16 %29 to i32
  %31 = icmp eq i32 %26, %30
  br i1 %31, label %33, label %32

32:                                               ; preds = %23
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %33

33:                                               ; preds = %32, %23
  %34 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 5
  %35 = load i8, ptr %34, align 2, !tbaa !20
  %36 = zext i8 %35 to i32
  %37 = load ptr, ptr %4, align 8, !tbaa !5
  %38 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %37, i32 0, i32 5
  %39 = load i8, ptr %38, align 2, !tbaa !20
  %40 = zext i8 %39 to i32
  %41 = icmp eq i32 %36, %40
  br i1 %41, label %43, label %42

42:                                               ; preds = %33
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %43

43:                                               ; preds = %42, %33
  %44 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 6
  %45 = load i8, ptr %44, align 1, !tbaa !21
  %46 = zext i8 %45 to i32
  %47 = load ptr, ptr %4, align 8, !tbaa !5
  %48 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %47, i32 0, i32 6
  %49 = load i8, ptr %48, align 1, !tbaa !21
  %50 = zext i8 %49 to i32
  %51 = icmp eq i32 %46, %50
  br i1 %51, label %53, label %52

52:                                               ; preds = %43
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %53

53:                                               ; preds = %52, %43
  %54 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 7
  %55 = load i32, ptr %54, align 8, !tbaa !22
  %56 = load ptr, ptr %4, align 8, !tbaa !5
  %57 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %56, i32 0, i32 7
  %58 = load i32, ptr %57, align 8, !tbaa !22
  %59 = icmp eq i32 %55, %58
  br i1 %59, label %61, label %60

60:                                               ; preds = %53
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %61

61:                                               ; preds = %60, %53
  %62 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 8
  %63 = load i8, ptr %62, align 4, !tbaa !23
  %64 = zext i8 %63 to i32
  %65 = load ptr, ptr %4, align 8, !tbaa !5
  %66 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %65, i32 0, i32 8
  %67 = load i8, ptr %66, align 4, !tbaa !23
  %68 = zext i8 %67 to i32
  %69 = icmp eq i32 %64, %68
  br i1 %69, label %71, label %70

70:                                               ; preds = %61
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %71

71:                                               ; preds = %70, %61
  %72 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 9
  %73 = load i8, ptr %72, align 1, !tbaa !24
  %74 = sext i8 %73 to i32
  %75 = load ptr, ptr %4, align 8, !tbaa !5
  %76 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %75, i32 0, i32 9
  %77 = load i8, ptr %76, align 1, !tbaa !24
  %78 = sext i8 %77 to i32
  %79 = icmp eq i32 %74, %78
  br i1 %79, label %81, label %80

80:                                               ; preds = %71
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %81

81:                                               ; preds = %80, %71
  %82 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %6, i32 0, i32 10
  %83 = load i16, ptr %82, align 2, !tbaa !25
  %84 = zext i16 %83 to i32
  %85 = load ptr, ptr %4, align 8, !tbaa !5
  %86 = getelementptr inbounds %"class.DIS::AttributePdu", ptr %85, i32 0, i32 10
  %87 = load i16, ptr %86, align 2, !tbaa !25
  %88 = zext i16 %87 to i32
  %89 = icmp eq i32 %84, %88
  br i1 %89, label %91, label %90

90:                                               ; preds = %81
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %91

91:                                               ; preds = %90, %81
  %92 = load i8, ptr %5, align 1, !tbaa !9, !range !26, !noundef !27
  %93 = trunc i8 %92 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #3
  ret i1 %93
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef zeroext i1 @_ZNK3DIS26EntityInformationFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(20), ptr noundef nonnull align 8 dereferenceable(20)) #2

declare noundef zeroext i1 @_ZNK3DIS17SimulationAddresseqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !16, i64 40}
!12 = !{!"_ZTSN3DIS12AttributePduE", !13, i64 0, !18, i64 24, !16, i64 40, !17, i64 44, !7, i64 46, !7, i64 47, !16, i64 48, !7, i64 52, !7, i64 53, !17, i64 54}
!13 = !{!"_ZTSN3DIS26EntityInformationFamilyPduE", !14, i64 0}
!14 = !{!"_ZTSN3DIS3PduE", !15, i64 0, !7, i64 18, !7, i64 19}
!15 = !{!"_ZTSN3DIS13PduSuperclassE", !7, i64 8, !7, i64 9, !7, i64 10, !7, i64 11, !16, i64 12, !17, i64 16}
!16 = !{!"int", !7, i64 0}
!17 = !{!"short", !7, i64 0}
!18 = !{!"_ZTSN3DIS17SimulationAddressE", !17, i64 8, !17, i64 10}
!19 = !{!12, !17, i64 44}
!20 = !{!12, !7, i64 46}
!21 = !{!12, !7, i64 47}
!22 = !{!12, !16, i64 48}
!23 = !{!12, !7, i64 52}
!24 = !{!12, !7, i64 53}
!25 = !{!12, !17, i64 54}
!26 = !{i8 0, i8 2}
!27 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS12AttributePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull align 8 dereferenceable(56) %1) local_unnamed_addr #0 align 2 {
  %3 = tail call noundef zeroext i1 @_ZNK3DIS26EntityInformationFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(20) %0, ptr noundef nonnull align 8 dereferenceable(20) %1)
  %4 = getelementptr inbounds i8, ptr %0, i64 24
  %5 = getelementptr inbounds i8, ptr %1, i64 24
  %6 = tail call noundef zeroext i1 @_ZNK3DIS17SimulationAddresseqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %4, ptr noundef nonnull align 8 dereferenceable(12) %5)
  %spec.select = and i1 %3, %6
  %7 = getelementptr inbounds i8, ptr %0, i64 40
  %8 = load i32, ptr %7, align 8, !tbaa !5
  %9 = getelementptr inbounds i8, ptr %1, i64 40
  %10 = load i32, ptr %9, align 8, !tbaa !5
  %11 = icmp eq i32 %8, %10
  %spec.select15 = and i1 %spec.select, %11
  %12 = getelementptr inbounds i8, ptr %0, i64 44
  %13 = load i16, ptr %12, align 4, !tbaa !15
  %14 = getelementptr inbounds i8, ptr %1, i64 44
  %15 = load i16, ptr %14, align 4, !tbaa !15
  %16 = icmp eq i16 %13, %15
  %17 = getelementptr inbounds i8, ptr %0, i64 46
  %18 = load i8, ptr %17, align 2, !tbaa !16
  %19 = getelementptr inbounds i8, ptr %1, i64 46
  %20 = load i8, ptr %19, align 2, !tbaa !16
  %21 = icmp eq i8 %18, %20
  %22 = getelementptr inbounds i8, ptr %0, i64 47
  %23 = load i8, ptr %22, align 1, !tbaa !17
  %24 = getelementptr inbounds i8, ptr %1, i64 47
  %25 = load i8, ptr %24, align 1, !tbaa !17
  %26 = icmp eq i8 %23, %25
  %27 = getelementptr inbounds i8, ptr %0, i64 48
  %28 = load i32, ptr %27, align 8, !tbaa !18
  %29 = getelementptr inbounds i8, ptr %1, i64 48
  %30 = load i32, ptr %29, align 8, !tbaa !18
  %31 = icmp eq i32 %28, %30
  %32 = getelementptr inbounds i8, ptr %0, i64 52
  %33 = load i8, ptr %32, align 4, !tbaa !19
  %34 = getelementptr inbounds i8, ptr %1, i64 52
  %35 = load i8, ptr %34, align 4, !tbaa !19
  %36 = icmp eq i8 %33, %35
  %37 = getelementptr inbounds i8, ptr %0, i64 53
  %38 = load i8, ptr %37, align 1, !tbaa !20
  %39 = getelementptr inbounds i8, ptr %1, i64 53
  %40 = load i8, ptr %39, align 1, !tbaa !20
  %41 = icmp eq i8 %38, %40
  %42 = getelementptr inbounds i8, ptr %0, i64 54
  %43 = load i16, ptr %42, align 2, !tbaa !21
  %44 = getelementptr inbounds i8, ptr %1, i64 54
  %45 = load i16, ptr %44, align 2, !tbaa !21
  %46 = icmp eq i16 %43, %45
  %47 = select i1 %46, i1 %41, i1 false
  %48 = select i1 %47, i1 %36, i1 false
  %49 = select i1 %48, i1 %31, i1 false
  %50 = select i1 %49, i1 %26, i1 false
  %51 = select i1 %50, i1 %21, i1 false
  %52 = select i1 %51, i1 %16, i1 false
  %spec.select14 = select i1 %52, i1 %spec.select15, i1 false
  ret i1 %spec.select14
}

declare noundef zeroext i1 @_ZNK3DIS26EntityInformationFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(20), ptr noundef nonnull align 8 dereferenceable(20)) local_unnamed_addr #1

declare noundef zeroext i1 @_ZNK3DIS17SimulationAddresseqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 40}
!6 = !{!"_ZTSN3DIS12AttributePduE", !7, i64 0, !14, i64 24, !12, i64 40, !13, i64 44, !10, i64 46, !10, i64 47, !12, i64 48, !10, i64 52, !10, i64 53, !13, i64 54}
!7 = !{!"_ZTSN3DIS26EntityInformationFamilyPduE", !8, i64 0}
!8 = !{!"_ZTSN3DIS3PduE", !9, i64 0, !10, i64 18, !10, i64 19}
!9 = !{!"_ZTSN3DIS13PduSuperclassE", !10, i64 8, !10, i64 9, !10, i64 10, !10, i64 11, !12, i64 12, !13, i64 16}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"int", !10, i64 0}
!13 = !{!"short", !10, i64 0}
!14 = !{!"_ZTSN3DIS17SimulationAddressE", !13, i64 8, !13, i64 10}
!15 = !{!6, !13, i64 44}
!16 = !{!6, !10, i64 46}
!17 = !{!6, !10, i64 47}
!18 = !{!6, !12, i64 48}
!19 = !{!6, !10, i64 52}
!20 = !{!6, !10, i64 53}
!21 = !{!6, !13, i64 54}


; Effective O3 passes: GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass