; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu/x86/int8 (rnn)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.RNNParamSpec = type { i32, i32, i32, i32, float, float, i8, float, i32 }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z12rnncell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, i32 noundef %8, ptr noundef %9, ptr noundef byval(%struct.RNNParamSpec) align 8 %10, i32 noundef %11, i32 noundef %12, ptr noundef byval(%struct.TensorDesc) align 8 %13, ptr noundef %14, i32 noundef %15) #0 {
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca ptr, align 8
  %21 = alloca ptr, align 8
  %22 = alloca ptr, align 8
  %23 = alloca ptr, align 8
  %24 = alloca i32, align 4
  %25 = alloca ptr, align 8
  %26 = alloca i32, align 4
  %27 = alloca i32, align 4
  %28 = alloca ptr, align 8
  %29 = alloca i32, align 4
  %30 = alloca i32, align 4
  %31 = alloca %struct.TensorDesc, align 8
  %32 = alloca %struct.RNNParamSpec, align 8
  %33 = alloca %struct.TensorDesc, align 8
  store ptr %1, ptr %17, align 8, !tbaa !5
  store ptr %2, ptr %18, align 8, !tbaa !5
  store ptr %3, ptr %19, align 8, !tbaa !5
  store ptr %4, ptr %20, align 8, !tbaa !5
  store ptr %5, ptr %21, align 8, !tbaa !5
  store ptr %6, ptr %22, align 8, !tbaa !5
  store ptr %7, ptr %23, align 8, !tbaa !5
  store i32 %8, ptr %24, align 4, !tbaa !9
  store ptr %9, ptr %25, align 8, !tbaa !5
  store i32 %11, ptr %26, align 4, !tbaa !9
  store i32 %12, ptr %27, align 4, !tbaa !9
  store ptr %14, ptr %28, align 8, !tbaa !5
  store i32 %15, ptr %29, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #4
  store i32 51, ptr %30, align 4, !tbaa !13
  %34 = getelementptr inbounds %struct.RNNParamSpec, ptr %10, i32 0, i32 0
  %35 = load i32, ptr %34, align 8, !tbaa !15
  switch i32 %35, label %51 [
    i32 1, label %36
  ]

36:                                               ; preds = %16
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %31, ptr align 8 %0, i64 92, i1 false), !tbaa.struct !21
  %37 = load ptr, ptr %17, align 8, !tbaa !5
  %38 = load ptr, ptr %18, align 8, !tbaa !5
  %39 = load ptr, ptr %19, align 8, !tbaa !5
  %40 = load ptr, ptr %20, align 8, !tbaa !5
  %41 = load ptr, ptr %21, align 8, !tbaa !5
  %42 = load ptr, ptr %22, align 8, !tbaa !5
  %43 = load ptr, ptr %23, align 8, !tbaa !5
  %44 = load i32, ptr %24, align 4, !tbaa !9
  %45 = load ptr, ptr %25, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %32, ptr align 8 %10, i64 36, i1 false), !tbaa.struct !27
  %46 = load i32, ptr %26, align 4, !tbaa !9
  %47 = load i32, ptr %27, align 4, !tbaa !9
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %33, ptr align 8 %13, i64 92, i1 false), !tbaa.struct !21
  %48 = load ptr, ptr %28, align 8, !tbaa !5
  %49 = load i32, ptr %29, align 4, !tbaa !11
  %50 = call noundef i32 @_Z13lstmcell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %31, ptr noundef %37, ptr noundef %38, ptr noundef %39, ptr noundef %40, ptr noundef %41, ptr noundef %42, ptr noundef %43, i32 noundef %44, ptr noundef %45, ptr noundef byval(%struct.RNNParamSpec) align 8 %32, i32 noundef %46, i32 noundef %47, ptr noundef byval(%struct.TensorDesc) align 8 %33, ptr noundef %48, i32 noundef %49)
  store i32 %50, ptr %30, align 4, !tbaa !13
  br label %52

51:                                               ; preds = %16
  br label %52

52:                                               ; preds = %51, %36
  %53 = load i32, ptr %30, align 4, !tbaa !13
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #4
  ret i32 %53
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef i32 @_Z13lstmcell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef byval(%struct.RNNParamSpec) align 8, i32 noundef, i32 noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"_ZTS4Arch", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS2EE", !7, i64 0}
!15 = !{!16, !17, i64 0}
!16 = !{!"_ZTS12RNNParamSpec", !17, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !18, i64 16, !18, i64 20, !19, i64 24, !18, i64 28, !20, i64 32}
!17 = !{!"_ZTS7RNNMode", !7, i64 0}
!18 = !{!"float", !7, i64 0}
!19 = !{!"bool", !7, i64 0}
!20 = !{!"_ZTS14ActivationMode", !7, i64 0}
!21 = !{i64 0, i64 4, !22, i64 4, i64 4, !24, i64 8, i64 4, !9, i64 12, i64 80, !26}
!22 = !{!23, !23, i64 0}
!23 = !{!"_ZTS8DataType", !7, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"_ZTS10DataFormat", !7, i64 0}
!26 = !{!7, !7, i64 0}
!27 = !{i64 0, i64 4, !28, i64 4, i64 4, !9, i64 8, i64 4, !9, i64 12, i64 4, !9, i64 16, i64 4, !29, i64 20, i64 4, !29, i64 24, i64 1, !30, i64 28, i64 4, !29, i64 32, i64 4, !31}
!28 = !{!17, !17, i64 0}
!29 = !{!18, !18, i64 0}
!30 = !{!19, !19, i64 0}
!31 = !{!20, !20, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.RNNParamSpec = type { i32, i32, i32, i32, float, float, i8, float, i32 }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z12rnncell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, i32 noundef %8, ptr noundef %9, ptr nocapture noundef readonly byval(%struct.RNNParamSpec) align 8 %10, i32 noundef %11, i32 noundef %12, ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %13, ptr noundef %14, i32 noundef %15) local_unnamed_addr #0 {
  %17 = load i32, ptr %10, align 8, !tbaa !5
  %cond = icmp eq i32 %17, 1
  br i1 %cond, label %18, label %20

18:                                               ; preds = %16
  %19 = tail call noundef i32 @_Z13lstmcell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, i32 noundef %8, ptr noundef %9, ptr noundef nonnull byval(%struct.RNNParamSpec) align 8 %10, i32 noundef %11, i32 noundef %12, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %13, ptr noundef %14, i32 noundef %15)
  br label %20

20:                                               ; preds = %16, %18
  %.0 = phi i32 [ %19, %18 ], [ 51, %16 ]
  ret i32 %.0
}

declare noundef i32 @_Z13lstmcell_int810TensorDescPKvPKS_PS1_S3_S4_PfPvjS6_12RNNParamSpecjjS_S6_4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef byval(%struct.RNNParamSpec) align 8, i32 noundef, i32 noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, i32 noundef) local_unnamed_addr #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS12RNNParamSpec", !7, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !11, i64 16, !11, i64 20, !12, i64 24, !11, i64 28, !13, i64 32}
!7 = !{!"_ZTS7RNNMode", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"float", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"_ZTS14ActivationMode", !8, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass