; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/pcuda (pcuda_runtime_api)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }
%"struct.hipsycl::rt::allocation_hints" = type { %"class.std::optional.129" }
%"class.std::optional.129" = type { %"struct.std::_Optional_base.130" }
%"struct.std::_Optional_base.130" = type { %"struct.std::_Optional_payload.132" }
%"struct.std::_Optional_payload.132" = type { %"struct.std::_Optional_payload.base.136", [7 x i8] }
%"struct.std::_Optional_payload.base.136" = type { %"struct.std::_Optional_payload_base.base.135" }
%"struct.std::_Optional_payload_base.base.135" = type <{ %"union.std::_Optional_payload_base<const std::vector<unsigned long>>::_Storage", i8 }>
%"union.std::_Optional_payload_base<const std::vector<unsigned long>>::_Storage" = type { %"class.std::vector.11" }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare noundef nonnull align 8 dereferenceable(104) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application3getEv() #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

declare noundef i32 @_ZN7hipsycl2rt5pcuda27get_most_recent_pcuda_errorEv() #2

declare i32 @__gxx_personality_v0(...)

declare noundef nonnull align 8 dereferenceable(40) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application8pcuda_rtEv(ptr noundef nonnull align 8 dereferenceable(104)) #2

; Function Attrs: mustprogress uwtable
declare hidden noundef ptr @_ZN7hipsycl2rt5pcuda12_GLOBAL__N_121get_current_device_idEv() #3

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime6get_rtEv(ptr noundef nonnull align 8 dereferenceable(40)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(72) ptr @_ZN7hipsycl2rt7runtime8backendsEv(ptr noundef nonnull align 8 dereferenceable(608)) #4 align 2

declare noundef ptr @_ZNK7hipsycl2rt15backend_manager3getENS0_10backend_idE(ptr noundef nonnull align 8 dereferenceable(72), i32 noundef) #2

declare noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16)) #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt8optionalIKSt6vectorImSaImEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #5 align 2

; Function Attrs: mustprogress uwtable
define dso_local i32 @pcudaAllocateShared(ptr noundef %0, i64 noundef %1, i32 noundef %2) #3 personality ptr @__gxx_personality_v0 {
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca i64, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca %"class.hipsycl::rt::device_id", align 4
  %13 = alloca ptr, align 8
  %14 = alloca %"struct.hipsycl::rt::allocation_hints", align 8
  %15 = alloca ptr, align 8
  %16 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i64 %1, ptr %6, align 8, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !11
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #6
  %17 = call noundef i32 @_ZN7hipsycl2rt5pcuda27get_most_recent_pcuda_errorEv()
  store i32 %17, ptr %8, align 4, !tbaa !13
  %18 = load i32, ptr %8, align 4, !tbaa !13
  %19 = icmp ne i32 %18, 0
  br i1 %19, label %20, label %22

20:                                               ; preds = %3
  %21 = load i32, ptr %8, align 4, !tbaa !13
  store i32 %21, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %65

22:                                               ; preds = %3
  %23 = load ptr, ptr %5, align 8, !tbaa !5
  %24 = icmp ne ptr %23, null
  br i1 %24, label %26, label %25

25:                                               ; preds = %22
  store i32 11, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %65

26:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #6
  %27 = call noundef ptr @_ZN7hipsycl2rt5pcuda12_GLOBAL__N_121get_current_device_idEv()
  store ptr %27, ptr %10, align 8, !tbaa !5
  %28 = load ptr, ptr %10, align 8, !tbaa !5
  %29 = icmp ne ptr %28, null
  br i1 %29, label %31, label %30

30:                                               ; preds = %26
  store i32 38, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %64

31:                                               ; preds = %26
  call void @llvm.lifetime.start.p0(i64 8, ptr %11) #6
  %32 = call noundef nonnull align 8 dereferenceable(104) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application3getEv()
  %33 = call noundef nonnull align 8 dereferenceable(40) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application8pcuda_rtEv(ptr noundef nonnull align 8 dereferenceable(104) %32)
  %34 = call noundef ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime6get_rtEv(ptr noundef nonnull align 8 dereferenceable(40) %33)
  %35 = call noundef nonnull align 8 dereferenceable(72) ptr @_ZN7hipsycl2rt7runtime8backendsEv(ptr noundef nonnull align 8 dereferenceable(608) %34)
  %36 = load ptr, ptr %10, align 8, !tbaa !5
  %37 = call noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16) %36)
  %38 = call noundef ptr @_ZNK7hipsycl2rt15backend_manager3getENS0_10backend_idE(ptr noundef nonnull align 8 dereferenceable(72) %35, i32 noundef %37)
  %39 = load ptr, ptr %10, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %12, ptr align 4 %39, i64 16, i1 false), !tbaa.struct !15
  %40 = getelementptr inbounds { i64, i64 }, ptr %12, i32 0, i32 0
  %41 = load i64, ptr %40, align 4
  %42 = getelementptr inbounds { i64, i64 }, ptr %12, i32 0, i32 1
  %43 = load i64, ptr %42, align 4
  %44 = load ptr, ptr %38, align 8, !tbaa !22
  %45 = getelementptr inbounds ptr, ptr %44, i64 5
  %46 = load ptr, ptr %45, align 8
  %47 = call noundef ptr %46(ptr noundef nonnull align 8 dereferenceable(8) %38, i64 %41, i64 %43)
  store ptr %47, ptr %11, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %13) #6
  %48 = load ptr, ptr %11, align 8, !tbaa !5
  %49 = load i64, ptr %6, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 32, ptr %14) #6
  %50 = getelementptr inbounds %"struct.hipsycl::rt::allocation_hints", ptr %14, i32 0, i32 0
  call void @_ZNSt8optionalIKSt6vectorImSaImEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %50) #6
  %51 = invoke noundef ptr @_ZN7hipsycl2rt15allocate_sharedEPNS0_17backend_allocatorEmRKNS0_16allocation_hintsE(ptr noundef %48, i64 noundef %49, ptr noundef nonnull align 8 dereferenceable(32) %14)
          to label %52 unwind label %56

52:                                               ; preds = %31
  call void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %14) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %14) #6
  store ptr %51, ptr %13, align 8, !tbaa !5
  %53 = load ptr, ptr %13, align 8, !tbaa !5
  %54 = icmp ne ptr %53, null
  br i1 %54, label %60, label %55

55:                                               ; preds = %52
  store i32 2, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %63

56:                                               ; preds = %31
  %57 = landingpad { ptr, i32 }
          cleanup
  %58 = extractvalue { ptr, i32 } %57, 0
  store ptr %58, ptr %15, align 8
  %59 = extractvalue { ptr, i32 } %57, 1
  store i32 %59, ptr %16, align 4
  call void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %14) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %14) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #6
  br label %67

60:                                               ; preds = %52
  %61 = load ptr, ptr %13, align 8, !tbaa !5
  %62 = load ptr, ptr %5, align 8, !tbaa !5
  store ptr %61, ptr %62, align 8, !tbaa !5
  store i32 0, ptr %4, align 4
  store i32 1, ptr %9, align 4
  br label %63

63:                                               ; preds = %60, %55
  call void @llvm.lifetime.end.p0(i64 8, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %11) #6
  br label %64

64:                                               ; preds = %63, %30
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #6
  br label %65

65:                                               ; preds = %64, %25, %20
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #6
  %66 = load i32, ptr %4, align 4
  ret i32 %66

67:                                               ; preds = %56
  %68 = load ptr, ptr %15, align 8
  %69 = load i32, ptr %16, align 4
  %70 = insertvalue { ptr, i32 } poison, ptr %68, 0
  %71 = insertvalue { ptr, i32 } %70, i32 %69, 1
  resume { ptr, i32 } %71
}

declare noundef ptr @_ZN7hipsycl2rt15allocate_sharedEPNS0_17backend_allocatorEmRKNS0_16allocation_hintsE(ptr noundef, i64 noundef, ptr noundef nonnull align 8 dereferenceable(32)) #2

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS10pcudaError", !7, i64 0}
!15 = !{i64 0, i64 4, !16, i64 4, i64 4, !18, i64 8, i64 4, !20, i64 12, i64 4, !11}
!16 = !{!17, !17, i64 0}
!17 = !{!"_ZTSN7hipsycl2rt10backend_idE", !7, i64 0}
!18 = !{!19, !19, i64 0}
!19 = !{!"_ZTSN7hipsycl2rt17hardware_platformE", !7, i64 0}
!20 = !{!21, !21, i64 0}
!21 = !{!"_ZTSN7hipsycl2rt12api_platformE", !7, i64 0}
!22 = !{!23, !23, i64 0}
!23 = !{!"vtable pointer", !8, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.hipsycl::rt::allocation_hints" = type { %"class.std::optional.129" }
%"class.std::optional.129" = type { %"struct.std::_Optional_base.130" }
%"struct.std::_Optional_base.130" = type { %"struct.std::_Optional_payload.132" }
%"struct.std::_Optional_payload.132" = type { %"struct.std::_Optional_payload.base.136", [7 x i8] }
%"struct.std::_Optional_payload.base.136" = type { %"struct.std::_Optional_payload_base.base.135" }
%"struct.std::_Optional_payload_base.base.135" = type <{ %"union.std::_Optional_payload_base<const std::vector<unsigned long>>::_Storage", i8 }>
%"union.std::_Optional_payload_base<const std::vector<unsigned long>>::_Storage" = type { %"class.std::vector.11" }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

declare noundef nonnull align 8 dereferenceable(104) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application3getEv() local_unnamed_addr #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

declare noundef i32 @_ZN7hipsycl2rt5pcuda27get_most_recent_pcuda_errorEv() local_unnamed_addr #1

declare i32 @__gxx_personality_v0(...)

declare noundef nonnull align 8 dereferenceable(40) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application8pcuda_rtEv(ptr noundef nonnull align 8 dereferenceable(104)) local_unnamed_addr #1

; Function Attrs: mustprogress uwtable
declare hidden noundef ptr @_ZN7hipsycl2rt5pcuda12_GLOBAL__N_121get_current_device_idEv() local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime6get_rtEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(72) ptr @_ZN7hipsycl2rt7runtime8backendsEv(ptr noundef nonnull align 8 dereferenceable(608)) local_unnamed_addr #3 align 2

declare noundef ptr @_ZNK7hipsycl2rt15backend_manager3getENS0_10backend_idE(ptr noundef nonnull align 8 dereferenceable(72), i32 noundef) local_unnamed_addr #1

declare noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16)) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt8optionalIKSt6vectorImSaImEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @pcudaAllocateShared(ptr noundef writeonly %0, i64 noundef %1, i32 noundef %2) local_unnamed_addr #2 personality ptr @__gxx_personality_v0 {
  %4 = alloca %"struct.hipsycl::rt::allocation_hints", align 8
  %5 = tail call noundef i32 @_ZN7hipsycl2rt5pcuda27get_most_recent_pcuda_errorEv()
  %.not = icmp eq i32 %5, 0
  br i1 %.not, label %6, label %25

6:                                                ; preds = %3
  %.not17 = icmp eq ptr %0, null
  br i1 %.not17, label %25, label %7

7:                                                ; preds = %6
  %8 = tail call noundef ptr @_ZN7hipsycl2rt5pcuda12_GLOBAL__N_121get_current_device_idEv()
  %.not18 = icmp eq ptr %8, null
  br i1 %.not18, label %25, label %9

9:                                                ; preds = %7
  %10 = tail call noundef nonnull align 8 dereferenceable(104) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application3getEv()
  %11 = tail call noundef nonnull align 8 dereferenceable(40) ptr @_ZN7hipsycl2rt5pcuda17pcuda_application8pcuda_rtEv(ptr noundef nonnull align 8 dereferenceable(104) %10)
  %12 = tail call noundef ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime6get_rtEv(ptr noundef nonnull align 8 dereferenceable(40) %11)
  %13 = tail call noundef nonnull align 8 dereferenceable(72) ptr @_ZN7hipsycl2rt7runtime8backendsEv(ptr noundef nonnull align 8 dereferenceable(608) %12)
  %14 = tail call noundef i32 @_ZNK7hipsycl2rt9device_id11get_backendEv(ptr noundef nonnull align 4 dereferenceable(16) %8)
  %15 = tail call noundef ptr @_ZNK7hipsycl2rt15backend_manager3getENS0_10backend_idE(ptr noundef nonnull align 8 dereferenceable(72) %13, i32 noundef %14)
  %.sroa.0.0.copyload = load i64, ptr %8, align 4
  %.sroa.2.0..sroa_idx = getelementptr inbounds i8, ptr %8, i64 8
  %.sroa.2.0.copyload = load i64, ptr %.sroa.2.0..sroa_idx, align 4
  %16 = load ptr, ptr %15, align 8, !tbaa !5
  %17 = getelementptr inbounds i8, ptr %16, i64 40
  %18 = load ptr, ptr %17, align 8
  %19 = tail call noundef ptr %18(ptr noundef nonnull align 8 dereferenceable(8) %15, i64 %.sroa.0.0.copyload, i64 %.sroa.2.0.copyload)
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %4) #5
  call void @_ZNSt8optionalIKSt6vectorImSaImEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  %20 = invoke noundef ptr @_ZN7hipsycl2rt15allocate_sharedEPNS0_17backend_allocatorEmRKNS0_16allocation_hintsE(ptr noundef %19, i64 noundef %1, ptr noundef nonnull align 8 dereferenceable(32) %4)
          to label %21 unwind label %22

21:                                               ; preds = %9
  call void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #5
  %.not19 = icmp eq ptr %20, null
  br i1 %.not19, label %25, label %24

22:                                               ; preds = %9
  %23 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN7hipsycl2rt16allocation_hintsD2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #5
  resume { ptr, i32 } %23

24:                                               ; preds = %21
  store ptr %20, ptr %0, align 8, !tbaa !8
  br label %25

25:                                               ; preds = %7, %21, %24, %6, %3
  %.2 = phi i32 [ %5, %3 ], [ 11, %6 ], [ 38, %7 ], [ 0, %24 ], [ 2, %21 ]
  ret i32 %.2
}

declare noundef ptr @_ZN7hipsycl2rt15allocate_sharedEPNS0_17backend_allocatorEmRKNS0_16allocation_hintsE(ptr noundef, i64 noundef, ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #1

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"vtable pointer", !7, i64 0}
!7 = !{!"Simple C++ TBAA"}
!8 = !{!9, !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass