; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis6 (SetRecordReliablePdu)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::SetRecordReliablePdu" = type { %"class.DIS::SimulationManagementWithReliabilityFamilyPdu", i32, i8, i16, i8, i32, %"class.std::vector" }
%"class.DIS::SimulationManagementWithReliabilityFamilyPdu" = type { %"class.DIS::Pdu.base", [4 x i8], %"class.DIS::EntityID", %"class.DIS::EntityID" }
%"class.DIS::Pdu.base" = type <{ ptr, i8, i8, i8, i8, i32, i16, i16 }>
%"class.DIS::EntityID" = type <{ ptr, i16, i16, i16, [2 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DIS::RecordSet, std::allocator<DIS::RecordSet>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::RecordSet, std::allocator<DIS::RecordSet>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::RecordSet, std::allocator<DIS::RecordSet>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::RecordSet, std::allocator<DIS::RecordSet>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS20SetRecordReliablePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(96) %0, ptr noundef nonnull align 8 dereferenceable(96) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  store i8 1, ptr %5, align 1, !tbaa !9
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = call noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %7, ptr noundef nonnull align 8 dereferenceable(56) %8)
  %10 = zext i1 %9 to i8
  store i8 %10, ptr %5, align 1, !tbaa !9
  %11 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 1
  %12 = load i32, ptr %11, align 8, !tbaa !11
  %13 = load ptr, ptr %4, align 8, !tbaa !5
  %14 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %13, i32 0, i32 1
  %15 = load i32, ptr %14, align 8, !tbaa !11
  %16 = icmp eq i32 %12, %15
  br i1 %16, label %18, label %17

17:                                               ; preds = %2
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %18

18:                                               ; preds = %17, %2
  %19 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 2
  %20 = load i8, ptr %19, align 4, !tbaa !22
  %21 = zext i8 %20 to i32
  %22 = load ptr, ptr %4, align 8, !tbaa !5
  %23 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %22, i32 0, i32 2
  %24 = load i8, ptr %23, align 4, !tbaa !22
  %25 = zext i8 %24 to i32
  %26 = icmp eq i32 %21, %25
  br i1 %26, label %28, label %27

27:                                               ; preds = %18
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %28

28:                                               ; preds = %27, %18
  %29 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 3
  %30 = load i16, ptr %29, align 2, !tbaa !23
  %31 = zext i16 %30 to i32
  %32 = load ptr, ptr %4, align 8, !tbaa !5
  %33 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %32, i32 0, i32 3
  %34 = load i16, ptr %33, align 2, !tbaa !23
  %35 = zext i16 %34 to i32
  %36 = icmp eq i32 %31, %35
  br i1 %36, label %38, label %37

37:                                               ; preds = %28
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %38

38:                                               ; preds = %37, %28
  %39 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 4
  %40 = load i8, ptr %39, align 8, !tbaa !24
  %41 = zext i8 %40 to i32
  %42 = load ptr, ptr %4, align 8, !tbaa !5
  %43 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %42, i32 0, i32 4
  %44 = load i8, ptr %43, align 8, !tbaa !24
  %45 = zext i8 %44 to i32
  %46 = icmp eq i32 %41, %45
  br i1 %46, label %48, label %47

47:                                               ; preds = %38
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %48

48:                                               ; preds = %47, %38
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !25
  br label %49

49:                                               ; preds = %66, %48
  %50 = load i64, ptr %6, align 8, !tbaa !25
  %51 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 6
  %52 = call noundef i64 @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %51) #4
  %53 = icmp ult i64 %50, %52
  br i1 %53, label %55, label %54

54:                                               ; preds = %49
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  br label %69

55:                                               ; preds = %49
  %56 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %7, i32 0, i32 6
  %57 = load i64, ptr %6, align 8, !tbaa !25
  %58 = call noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %56, i64 noundef %57) #4
  %59 = load ptr, ptr %4, align 8, !tbaa !5
  %60 = getelementptr inbounds %"class.DIS::SetRecordReliablePdu", ptr %59, i32 0, i32 6
  %61 = load i64, ptr %6, align 8, !tbaa !25
  %62 = call noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %60, i64 noundef %61) #4
  %63 = call noundef zeroext i1 @_ZNK3DIS9RecordSeteqERKS0_(ptr noundef nonnull align 8 dereferenceable(23) %58, ptr noundef nonnull align 8 dereferenceable(23) %62)
  br i1 %63, label %65, label %64

64:                                               ; preds = %55
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %65

65:                                               ; preds = %64, %55
  br label %66

66:                                               ; preds = %65
  %67 = load i64, ptr %6, align 8, !tbaa !25
  %68 = add i64 %67, 1
  store i64 %68, ptr %6, align 8, !tbaa !25
  br label %49, !llvm.loop !27

69:                                               ; preds = %54
  %70 = load i8, ptr %5, align 1, !tbaa !9, !range !29, !noundef !30
  %71 = trunc i8 %70 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i1 %71
}

declare noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef nonnull align 8 dereferenceable(56)) #3

declare noundef zeroext i1 @_ZNK3DIS9RecordSeteqERKS0_(ptr noundef nonnull align 8 dereferenceable(23), ptr noundef nonnull align 8 dereferenceable(23)) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !15, i64 56}
!12 = !{!"_ZTSN3DIS20SetRecordReliablePduE", !13, i64 0, !15, i64 56, !7, i64 60, !16, i64 62, !7, i64 64, !15, i64 68, !18, i64 72}
!13 = !{!"_ZTSN3DIS44SimulationManagementWithReliabilityFamilyPduE", !14, i64 0, !17, i64 24, !17, i64 40}
!14 = !{!"_ZTSN3DIS3PduE", !7, i64 8, !7, i64 9, !7, i64 10, !7, i64 11, !15, i64 12, !16, i64 16, !16, i64 18}
!15 = !{!"int", !7, i64 0}
!16 = !{!"short", !7, i64 0}
!17 = !{!"_ZTSN3DIS8EntityIDE", !16, i64 8, !16, i64 10, !16, i64 12}
!18 = !{!"_ZTSSt6vectorIN3DIS9RecordSetESaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!12, !7, i64 60}
!23 = !{!12, !16, i64 62}
!24 = !{!12, !7, i64 64}
!25 = !{!26, !26, i64 0}
!26 = !{!"long", !7, i64 0}
!27 = distinct !{!27, !28}
!28 = !{!"llvm.loop.mustprogress"}
!29 = !{i8 0, i8 2}
!30 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS20SetRecordReliablePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(96) %0, ptr noundef nonnull align 8 dereferenceable(96) %1) local_unnamed_addr #1 align 2 {
  %3 = tail call noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull align 8 dereferenceable(56) %1)
  %4 = getelementptr inbounds i8, ptr %0, i64 56
  %5 = load i32, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %1, i64 56
  %7 = load i32, ptr %6, align 8, !tbaa !5
  %8 = icmp eq i32 %5, %7
  %narrow = and i1 %3, %8
  %9 = getelementptr inbounds i8, ptr %0, i64 60
  %10 = load i8, ptr %9, align 4, !tbaa !19
  %11 = getelementptr inbounds i8, ptr %1, i64 60
  %12 = load i8, ptr %11, align 4, !tbaa !19
  %13 = icmp eq i8 %10, %12
  %14 = getelementptr inbounds i8, ptr %0, i64 62
  %15 = load i16, ptr %14, align 2, !tbaa !20
  %16 = getelementptr inbounds i8, ptr %1, i64 62
  %17 = load i16, ptr %16, align 2, !tbaa !20
  %18 = icmp eq i16 %15, %17
  %19 = getelementptr inbounds i8, ptr %0, i64 64
  %20 = load i8, ptr %19, align 8, !tbaa !21
  %21 = getelementptr inbounds i8, ptr %1, i64 64
  %22 = load i8, ptr %21, align 8, !tbaa !21
  %23 = icmp eq i8 %20, %22
  %24 = select i1 %23, i1 %18, i1 false
  %25 = select i1 %24, i1 %13, i1 false
  %narrow15 = select i1 %25, i1 %narrow, i1 false
  %26 = getelementptr inbounds i8, ptr %0, i64 72
  %27 = tail call noundef i64 @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %.not = icmp eq i64 %27, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %28 = getelementptr inbounds i8, ptr %1, i64 72
  br label %29

._crit_edge:                                      ; preds = %29, %2
  %.3.lcssa = phi i1 [ %narrow15, %2 ], [ %spec.select12, %29 ]
  ret i1 %.3.lcssa

29:                                               ; preds = %.lr.ph, %29
  %.017 = phi i64 [ 0, %.lr.ph ], [ %33, %29 ]
  %.316 = phi i1 [ %narrow15, %.lr.ph ], [ %spec.select12, %29 ]
  %30 = tail call noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %26, i64 noundef %.017) #3
  %31 = tail call noundef nonnull align 8 dereferenceable(23) ptr @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %28, i64 noundef %.017) #3
  %32 = tail call noundef zeroext i1 @_ZNK3DIS9RecordSeteqERKS0_(ptr noundef nonnull align 8 dereferenceable(23) %30, ptr noundef nonnull align 8 dereferenceable(23) %31)
  %spec.select12 = select i1 %32, i1 %.316, i1 false
  %33 = add nuw i64 %.017, 1
  %34 = tail call noundef i64 @_ZNKSt6vectorIN3DIS9RecordSetESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #3
  %35 = icmp ult i64 %33, %34
  br i1 %35, label %29, label %._crit_edge, !llvm.loop !22
}

declare noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK3DIS9RecordSeteqERKS0_(ptr noundef nonnull align 8 dereferenceable(23), ptr noundef nonnull align 8 dereferenceable(23)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 56}
!6 = !{!"_ZTSN3DIS20SetRecordReliablePduE", !7, i64 0, !11, i64 56, !9, i64 60, !12, i64 62, !9, i64 64, !11, i64 68, !14, i64 72}
!7 = !{!"_ZTSN3DIS44SimulationManagementWithReliabilityFamilyPduE", !8, i64 0, !13, i64 24, !13, i64 40}
!8 = !{!"_ZTSN3DIS3PduE", !9, i64 8, !9, i64 9, !9, i64 10, !9, i64 11, !11, i64 12, !12, i64 16, !12, i64 18}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"short", !9, i64 0}
!13 = !{!"_ZTSN3DIS8EntityIDE", !12, i64 8, !12, i64 10, !12, i64 12}
!14 = !{!"_ZTSSt6vectorIN3DIS9RecordSetESaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN3DIS9RecordSetESaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!18 = !{!"any pointer", !9, i64 0}
!19 = !{!6, !9, i64 60}
!20 = !{!6, !12, i64 62}
!21 = !{!6, !9, i64 64}
!22 = distinct !{!22, !23}
!23 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass