; LLVM IR from quantumlib/qsim :: apps (qsim_amplitudes)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::vector", %"class.std::vector.3", %"class.std::vector.3", i32, i32, i32, i32, i8, [7 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%class.anon.13 = type { ptr, ptr }
%"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter" = type { %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", i64 }
%"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter" = type { i32, i32 }
%struct.Factory = type { i32 }

@.str.7 = external hidden unnamed_addr constant [11 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(121)) #0

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main(i32 noundef %0, ptr noundef %1) #3 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca %struct.Options, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %"struct.qsim::Circuit", align 8
  %11 = alloca i32, align 4
  %12 = alloca %class.anon.13, align 8
  %13 = alloca %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", align 8
  %14 = alloca %struct.Factory, align 4
  %15 = alloca %class.anon.13, align 8
  store i32 0, ptr %3, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 128, ptr %6) #6
  %16 = load i32, ptr %4, align 4, !tbaa !5
  %17 = load ptr, ptr %5, align 8, !tbaa !9
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind writable sret(%struct.Options) align 8 %6, i32 noundef %16, ptr noundef %17)
  %18 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(121) %6)
          to label %19 unwind label %21

19:                                               ; preds = %2
  br i1 %18, label %25, label %20

20:                                               ; preds = %19
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %79

21:                                               ; preds = %2
  %22 = landingpad { ptr, i32 }
          cleanup
  %23 = extractvalue { ptr, i32 } %22, 0
  store ptr %23, ptr %7, align 8
  %24 = extractvalue { ptr, i32 } %22, 1
  store i32 %24, ptr %8, align 4
  br label %81

25:                                               ; preds = %19
  call void @llvm.lifetime.start.p0(i64 32, ptr %10) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #6
  %26 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  %27 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIjSaIjEE4backEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #6
  %28 = load i32, ptr %27, align 4, !tbaa !5
  store i32 %28, ptr %11, align 4, !tbaa !5
  %29 = load i32, ptr %11, align 4, !tbaa !5
  %30 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 0
  %31 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %29, ptr noundef nonnull align 8 dereferenceable(32) %30, ptr noundef nonnull align 8 dereferenceable(32) %10)
          to label %32 unwind label %34

32:                                               ; preds = %25
  br i1 %31, label %38, label %33

33:                                               ; preds = %32
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %77

34:                                               ; preds = %42, %25
  %35 = landingpad { ptr, i32 }
          cleanup
  %36 = extractvalue { ptr, i32 } %35, 0
  store ptr %36, ptr %7, align 8
  %37 = extractvalue { ptr, i32 } %35, 1
  store i32 %37, ptr %8, align 4
  br label %78

38:                                               ; preds = %32
  %39 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 8
  %40 = load i8, ptr %39, align 8, !tbaa !11, !range !25, !noundef !26
  %41 = trunc i8 %40 to i1
  br i1 %41, label %42, label %44

42:                                               ; preds = %38
  invoke void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
          to label %43 unwind label %34

43:                                               ; preds = %42
  br label %44

44:                                               ; preds = %43, %38
  call void @llvm.lifetime.start.p0(i64 16, ptr %12) #6
  %45 = getelementptr inbounds %class.anon.13, ptr %12, i32 0, i32 0
  store ptr %6, ptr %45, align 8, !tbaa !9
  %46 = getelementptr inbounds %class.anon.13, ptr %12, i32 0, i32 1
  store ptr %10, ptr %46, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 16, ptr %13) #6
  call void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16) %13) #6
  %47 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 6
  %48 = load i32, ptr %47, align 8, !tbaa !27
  %49 = getelementptr inbounds %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", ptr %13, i32 0, i32 0
  store i32 %48, ptr %49, align 8, !tbaa !28
  %50 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 4
  %51 = load i32, ptr %50, align 8, !tbaa !30
  %52 = zext i32 %51 to i64
  %53 = getelementptr inbounds %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", ptr %13, i32 0, i32 1
  store i64 %52, ptr %53, align 8, !tbaa !31
  %54 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 7
  %55 = load i32, ptr %54, align 4, !tbaa !33
  %56 = getelementptr inbounds %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", ptr %13, i32 0, i32 1
  store i32 %55, ptr %56, align 4, !tbaa !34
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #6
  %57 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 5
  %58 = load i32, ptr %57, align 4, !tbaa !35
  invoke void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %14, i32 noundef %58)
          to label %59 unwind label %68

59:                                               ; preds = %44
  %60 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %15, ptr align 8 %12, i64 16, i1 false), !tbaa.struct !36
  %61 = getelementptr inbounds { ptr, ptr }, ptr %15, i32 0, i32 0
  %62 = load ptr, ptr %61, align 8
  %63 = getelementptr inbounds { ptr, ptr }, ptr %15, i32 0, i32 1
  %64 = load ptr, ptr %63, align 8
  %65 = invoke noundef zeroext i1 @"_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEZ4mainE3$_0EEbRKNSA_9ParameterERKS7_RKSt6vectorIjSaIjEERKT_T0_"(ptr noundef nonnull align 8 dereferenceable(16) %13, ptr noundef nonnull align 4 dereferenceable(4) %14, ptr noundef nonnull align 8 dereferenceable(24) %60, ptr noundef nonnull align 8 dereferenceable(32) %10, ptr %62, ptr %64)
          to label %66 unwind label %68

66:                                               ; preds = %59
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #6
  invoke void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef @.str.7)
          to label %67 unwind label %72

67:                                               ; preds = %66
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #6
  br label %77

68:                                               ; preds = %59, %44
  %69 = landingpad { ptr, i32 }
          cleanup
  %70 = extractvalue { ptr, i32 } %69, 0
  store ptr %70, ptr %7, align 8
  %71 = extractvalue { ptr, i32 } %69, 1
  store i32 %71, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #6
  br label %76

72:                                               ; preds = %66
  %73 = landingpad { ptr, i32 }
          cleanup
  %74 = extractvalue { ptr, i32 } %73, 0
  store ptr %74, ptr %7, align 8
  %75 = extractvalue { ptr, i32 } %73, 1
  store i32 %75, ptr %8, align 4
  br label %76

76:                                               ; preds = %72, %68
  call void @llvm.lifetime.end.p0(i64 16, ptr %13) #6
  call void @llvm.lifetime.end.p0(i64 16, ptr %12) #6
  br label %78

77:                                               ; preds = %67, %33
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %79

78:                                               ; preds = %76, %34
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %81

79:                                               ; preds = %77, %20
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121) %6) #6
  call void @llvm.lifetime.end.p0(i64 128, ptr %6) #6
  %80 = load i32, ptr %3, align 4
  ret i32 %80

81:                                               ; preds = %78, %21
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121) %6) #6
  call void @llvm.lifetime.end.p0(i64 128, ptr %6) #6
  br label %82

82:                                               ; preds = %81
  %83 = load ptr, ptr %7, align 8
  %84 = load i32, ptr %8, align 4
  %85 = insertvalue { ptr, i32 } poison, ptr %83, 0
  %86 = insertvalue { ptr, i32 } %85, i32 %84, 1
  resume { ptr, i32 } %86
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIjSaIjEE4backEv(ptr noundef nonnull align 8 dereferenceable(24)) #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @"_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEZ4mainE3$_0EEbRKNSA_9ParameterERKS7_RKSt6vectorIjSaIjEERKT_T0_"(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(32), ptr, ptr) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #4 align 2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #5

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !24, i64 120}
!12 = !{!"_ZTS7Options", !13, i64 0, !16, i64 32, !20, i64 56, !20, i64 80, !6, i64 104, !6, i64 108, !6, i64 112, !6, i64 116, !24, i64 120}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIjSaIjEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!20 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !21, i64 0}
!21 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!24 = !{!"bool", !7, i64 0}
!25 = !{i8 0, i8 2}
!26 = !{}
!27 = !{!12, !6, i64 112}
!28 = !{!29, !6, i64 0}
!29 = !{!"_ZTSN4qsim19MultiQubitGateFuserINS_2IOENS_4GateIfNS_8GateKindEEEE9ParameterE", !6, i64 0, !6, i64 4}
!30 = !{!12, !6, i64 104}
!31 = !{!32, !15, i64 8}
!32 = !{!"_ZTSN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterE", !29, i64 0, !15, i64 8}
!33 = !{!12, !6, i64 116}
!34 = !{!29, !6, i64 4}
!35 = !{!12, !6, i64 108}
!36 = !{i64 0, i64 8, !9, i64 8, i64 8, !9}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::vector", %"class.std::vector.3", %"class.std::vector.3", i32, i32, i32, i32, i8, [7 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::__cxx11::basic_string<char>, std::allocator<std::__cxx11::basic_string<char>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.8" }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter" = type { %"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter", i64 }
%"struct.qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>::Parameter" = type { i32, i32 }
%struct.Factory = type { i32 }

@.str.7 = external hidden unnamed_addr constant [11 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(121)) local_unnamed_addr #0

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef range(i32 0, 2) i32 @main(i32 noundef %0, ptr noundef %1) local_unnamed_addr #3 personality ptr @__gxx_personality_v0 {
  %3 = alloca %struct.Options, align 8
  %4 = alloca %"struct.qsim::Circuit", align 8
  %5 = alloca %"struct.qsim::QSimRunner<qsim::IO, qsim::MultiQubitGateFuser<qsim::IO, qsim::Gate<float, qsim::GateKind>>, Factory>::Parameter", align 8
  %6 = alloca %struct.Factory, align 4
  call void @llvm.lifetime.start.p0(i64 128, ptr nonnull %3) #5
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind nonnull writable sret(%struct.Options) align 8 %3, i32 noundef %0, ptr noundef %1)
  %7 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(121) %3)
          to label %8 unwind label %9

8:                                                ; preds = %2
  br i1 %7, label %11, label %39

9:                                                ; preds = %2
  %10 = landingpad { ptr, i32 }
          cleanup
  br label %40

11:                                               ; preds = %8
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %4) #5
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  %12 = getelementptr inbounds i8, ptr %3, i64 32
  %13 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIjSaIjEE4backEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #5
  %14 = load i32, ptr %13, align 4, !tbaa !5
  %15 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %14, ptr noundef nonnull align 8 dereferenceable(32) %3, ptr noundef nonnull align 8 dereferenceable(32) %4)
          to label %16 unwind label %17

16:                                               ; preds = %11
  br i1 %15, label %19, label %37

17:                                               ; preds = %11
  %18 = landingpad { ptr, i32 }
          cleanup
  br label %38

19:                                               ; preds = %16
  %20 = getelementptr inbounds i8, ptr %3, i64 120
  %21 = load i8, ptr %20, align 8, !tbaa !9, !range !24, !noundef !25
  %22 = trunc nuw i8 %21 to i1
  br i1 %22, label %23, label %24

23:                                               ; preds = %19
  call void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
  br label %24

24:                                               ; preds = %23, %19
  call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %5) #5
  call void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16) %5) #5
  %25 = getelementptr inbounds i8, ptr %3, i64 112
  %26 = getelementptr inbounds i8, ptr %3, i64 104
  %27 = load i32, ptr %26, align 8, !tbaa !26
  %28 = zext i32 %27 to i64
  %29 = getelementptr inbounds i8, ptr %5, i64 8
  store i64 %28, ptr %29, align 8, !tbaa !27
  %30 = load <2 x i32>, ptr %25, align 8, !tbaa !5
  store <2 x i32> %30, ptr %5, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %6) #5
  %31 = getelementptr inbounds i8, ptr %3, i64 108
  %32 = load i32, ptr %31, align 4, !tbaa !30
  call void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %6, i32 noundef %32)
  %33 = invoke noundef zeroext i1 @"_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEZ4mainE3$_0EEbRKNSA_9ParameterERKS7_RKSt6vectorIjSaIjEERKT_T0_"(ptr noundef nonnull align 8 dereferenceable(16) %5, ptr noundef nonnull align 4 dereferenceable(4) %6, ptr noundef nonnull align 8 dereferenceable(24) %12, ptr noundef nonnull align 8 dereferenceable(32) %4, ptr nonnull %3, ptr nonnull %4)
          to label %34 unwind label %35

34:                                               ; preds = %24
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #5
  call void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef nonnull @.str.7)
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #5
  br label %37

35:                                               ; preds = %24
  %36 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %6) #5
  call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %5) #5
  br label %38

37:                                               ; preds = %16, %34
  %.0 = phi i32 [ 0, %34 ], [ 1, %16 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #5
  br label %39

38:                                               ; preds = %35, %17
  %.pn = phi { ptr, i32 } [ %36, %35 ], [ %18, %17 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #5
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #5
  br label %40

39:                                               ; preds = %8, %37
  %.1 = phi i32 [ %.0, %37 ], [ 1, %8 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121) %3) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %3) #5
  ret i32 %.1

40:                                               ; preds = %38, %9
  %.pn.pn = phi { ptr, i32 } [ %.pn, %38 ], [ %10, %9 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(121) %3) #5
  call void @llvm.lifetime.end.p0(i64 128, ptr nonnull %3) #5
  resume { ptr, i32 } %.pn.pn
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIjSaIjEE4backEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #4 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden void @_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(16)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @"_ZN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE3RunINS_7CircuitIS5_EEZ4mainE3$_0EEbRKNSA_9ParameterERKS7_RKSt6vectorIjSaIjEERKT_T0_"(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(32), ptr, ptr) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #4 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) local_unnamed_addr #4 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !23, i64 120}
!10 = !{!"_ZTS7Options", !11, i64 0, !15, i64 32, !19, i64 56, !19, i64 80, !6, i64 104, !6, i64 108, !6, i64 112, !6, i64 116, !23, i64 120}
!11 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !12, i64 0, !14, i64 8, !7, i64 16}
!12 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !13, i64 0}
!13 = !{!"any pointer", !7, i64 0}
!14 = !{!"long", !7, i64 0}
!15 = !{!"_ZTSSt6vectorIjSaIjEE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!19 = !{!"_ZTSSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_Vector_impl_dataE", !13, i64 0, !13, i64 8, !13, i64 16}
!23 = !{!"bool", !7, i64 0}
!24 = !{i8 0, i8 2}
!25 = !{}
!26 = !{!10, !6, i64 104}
!27 = !{!28, !14, i64 8}
!28 = !{!"_ZTSN4qsim10QSimRunnerINS_2IOENS_19MultiQubitGateFuserIS1_NS_4GateIfNS_8GateKindEEEEEZ4mainE7FactorySt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEE9ParameterE", !29, i64 0, !14, i64 8}
!29 = !{!"_ZTSN4qsim19MultiQubitGateFuserINS_2IOENS_4GateIfNS_8GateKindEEEE9ParameterE", !6, i64 0, !6, i64 4}
!30 = !{!10, !6, i64 108}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass