; LLVM IR from quantumlib/qsim :: apps (qsimh_amplitudes)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", %"class.std::vector", i64, i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter" = type <{ %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", [4 x i8], i64, i32, i32, i32, [4 x i8] }>
%"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter" = type { i32 }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::complex" = type { { float, float } }
%"class.std::allocator.15" = type { i8 }
%struct.Factory = type { i32 }

@.str.5 = external hidden unnamed_addr constant [11 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(149)) #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8, i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef i32 @main(i32 noundef %0, ptr noundef %1) #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca ptr, align 8
  %6 = alloca %struct.Options, align 8
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca %"struct.qsim::Circuit", align 8
  %11 = alloca %"class.std::vector", align 8
  %12 = alloca %"class.std::vector.8", align 8
  %13 = alloca i32, align 4
  %14 = alloca %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", align 8
  %15 = alloca %"class.std::vector.13", align 8
  %16 = alloca %"class.std::complex", align 4
  %17 = alloca %"class.std::allocator.15", align 1
  %18 = alloca %struct.Factory, align 4
  store i32 0, ptr %3, align 4
  store i32 %0, ptr %4, align 4, !tbaa !5
  store ptr %1, ptr %5, align 8, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 152, ptr %6) #6
  %19 = load i32, ptr %4, align 4, !tbaa !5
  %20 = load ptr, ptr %5, align 8, !tbaa !9
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind writable sret(%struct.Options) align 8 %6, i32 noundef %19, ptr noundef %20)
  %21 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(149) %6)
          to label %22 unwind label %24

22:                                               ; preds = %2
  br i1 %21, label %28, label %23

23:                                               ; preds = %22
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %126

24:                                               ; preds = %2
  %25 = landingpad { ptr, i32 }
          cleanup
  %26 = extractvalue { ptr, i32 } %25, 0
  store ptr %26, ptr %7, align 8
  %27 = extractvalue { ptr, i32 } %25, 1
  store i32 %27, ptr %8, align 4
  br label %128

28:                                               ; preds = %22
  call void @llvm.lifetime.start.p0(i64 32, ptr %10) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  %29 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 5
  %30 = load i32, ptr %29, align 8, !tbaa !11
  %31 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 0
  %32 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %30, ptr noundef nonnull align 8 dereferenceable(32) %31, ptr noundef nonnull align 8 dereferenceable(32) %10)
          to label %33 unwind label %35

33:                                               ; preds = %28
  br i1 %32, label %39, label %34

34:                                               ; preds = %33
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %124

35:                                               ; preds = %39, %28
  %36 = landingpad { ptr, i32 }
          cleanup
  %37 = extractvalue { ptr, i32 } %36, 0
  store ptr %37, ptr %7, align 8
  %38 = extractvalue { ptr, i32 } %36, 1
  store i32 %38, ptr %8, align 4
  br label %125

39:                                               ; preds = %33
  %40 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %41 = load i32, ptr %40, align 8, !tbaa !21
  %42 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 3
  %43 = invoke noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef %41, ptr noundef nonnull align 8 dereferenceable(24) %42)
          to label %44 unwind label %35

44:                                               ; preds = %39
  br i1 %43, label %46, label %45

45:                                               ; preds = %44
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %124

46:                                               ; preds = %44
  call void @llvm.lifetime.start.p0(i64 24, ptr %11) #6
  %47 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %48 = load i32, ptr %47, align 8, !tbaa !21
  %49 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 3
  invoke void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind writable sret(%"class.std::vector") align 8 %11, i32 noundef %48, ptr noundef nonnull align 8 dereferenceable(24) %49)
          to label %50 unwind label %56

50:                                               ; preds = %46
  %51 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 10
  %52 = load i8, ptr %51, align 4, !tbaa !27, !range !28, !noundef !29
  %53 = trunc i8 %52 to i1
  br i1 %53, label %54, label %64

54:                                               ; preds = %50
  invoke void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
          to label %55 unwind label %60

55:                                               ; preds = %54
  br label %64

56:                                               ; preds = %46
  %57 = landingpad { ptr, i32 }
          cleanup
  %58 = extractvalue { ptr, i32 } %57, 0
  store ptr %58, ptr %7, align 8
  %59 = extractvalue { ptr, i32 } %57, 1
  store i32 %59, ptr %8, align 4
  br label %123

60:                                               ; preds = %54
  %61 = landingpad { ptr, i32 }
          cleanup
  %62 = extractvalue { ptr, i32 } %61, 0
  store ptr %62, ptr %7, align 8
  %63 = extractvalue { ptr, i32 } %61, 1
  store i32 %63, ptr %8, align 4
  br label %122

64:                                               ; preds = %55, %50
  call void @llvm.lifetime.start.p0(i64 24, ptr %12) #6
  call void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %13) #6
  %65 = getelementptr inbounds %"struct.qsim::Circuit", ptr %10, i32 0, i32 0
  %66 = load i32, ptr %65, align 8, !tbaa !21
  store i32 %66, ptr %13, align 4, !tbaa !5
  %67 = load i32, ptr %13, align 4, !tbaa !5
  %68 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 1
  %69 = invoke noundef zeroext i1 @_ZN4qsim18BitstringsFromFileINS_6IOFileEEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorImSaImEE(i32 noundef %67, ptr noundef nonnull align 8 dereferenceable(32) %68, ptr noundef nonnull align 8 dereferenceable(24) %12)
          to label %70 unwind label %72

70:                                               ; preds = %64
  br i1 %69, label %76, label %71

71:                                               ; preds = %70
  store i32 1, ptr %3, align 4
  store i32 1, ptr %9, align 4
  br label %120

72:                                               ; preds = %64
  %73 = landingpad { ptr, i32 }
          cleanup
  %74 = extractvalue { ptr, i32 } %73, 0
  store ptr %74, ptr %7, align 8
  %75 = extractvalue { ptr, i32 } %73, 1
  store i32 %75, ptr %8, align 4
  br label %121

76:                                               ; preds = %70
  call void @llvm.lifetime.start.p0(i64 32, ptr %14) #6
  call void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28) %14) #6
  %77 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 4
  %78 = load i64, ptr %77, align 8, !tbaa !30
  %79 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %14, i32 0, i32 2
  store i64 %78, ptr %79, align 8, !tbaa !31
  %80 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 6
  %81 = load i32, ptr %80, align 4, !tbaa !34
  %82 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %14, i32 0, i32 3
  store i32 %81, ptr %82, align 8, !tbaa !35
  %83 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 7
  %84 = load i32, ptr %83, align 8, !tbaa !36
  %85 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %14, i32 0, i32 4
  store i32 %84, ptr %85, align 4, !tbaa !37
  %86 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 8
  %87 = load i32, ptr %86, align 4, !tbaa !38
  %88 = getelementptr inbounds %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", ptr %14, i32 0, i32 5
  store i32 %87, ptr %88, align 8, !tbaa !39
  %89 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 9
  %90 = load i32, ptr %89, align 8, !tbaa !40
  %91 = getelementptr inbounds %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", ptr %14, i32 0, i32 0
  store i32 %90, ptr %91, align 8, !tbaa !41
  call void @llvm.lifetime.start.p0(i64 24, ptr %15) #6
  %92 = call noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr %16) #6
  invoke void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8) %16, float noundef 0.000000e+00, float noundef 0.000000e+00)
          to label %93 unwind label %105

93:                                               ; preds = %76
  call void @llvm.lifetime.start.p0(i64 1, ptr %17) #6
  call void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %17) #6
  invoke void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24) %15, i64 noundef %92, ptr noundef nonnull align 4 dereferenceable(8) %16, ptr noundef nonnull align 1 dereferenceable(1) %17)
          to label %94 unwind label %109

94:                                               ; preds = %93
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %17) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr %17) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #6
  %95 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 8
  %96 = load i32, ptr %95, align 4, !tbaa !38
  invoke void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %18, i32 noundef %96)
          to label %97 unwind label %114

97:                                               ; preds = %94
  %98 = invoke noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28) %14, ptr noundef nonnull align 4 dereferenceable(4) %18, ptr noundef nonnull align 8 dereferenceable(32) %10, ptr noundef nonnull align 8 dereferenceable(24) %11, ptr noundef nonnull align 8 dereferenceable(24) %12, ptr noundef nonnull align 8 dereferenceable(24) %15)
          to label %99 unwind label %114

99:                                               ; preds = %97
  br i1 %98, label %100, label %118

100:                                              ; preds = %99
  %101 = getelementptr inbounds %struct.Options, ptr %6, i32 0, i32 2
  %102 = invoke noundef zeroext i1 @_Z15WriteAmplitudesImSt7complexIfEEbRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt6vectorIT_SaISB_EERKSA_IT0_SaISG_EE(ptr noundef nonnull align 8 dereferenceable(32) %101, ptr noundef nonnull align 8 dereferenceable(24) %12, ptr noundef nonnull align 8 dereferenceable(24) %15)
          to label %103 unwind label %114

103:                                              ; preds = %100
  invoke void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef @.str.5)
          to label %104 unwind label %114

104:                                              ; preds = %103
  br label %118

105:                                              ; preds = %76
  %106 = landingpad { ptr, i32 }
          cleanup
  %107 = extractvalue { ptr, i32 } %106, 0
  store ptr %107, ptr %7, align 8
  %108 = extractvalue { ptr, i32 } %106, 1
  store i32 %108, ptr %8, align 4
  br label %113

109:                                              ; preds = %93
  %110 = landingpad { ptr, i32 }
          cleanup
  %111 = extractvalue { ptr, i32 } %110, 0
  store ptr %111, ptr %7, align 8
  %112 = extractvalue { ptr, i32 } %110, 1
  store i32 %112, ptr %8, align 4
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %17) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr %17) #6
  br label %113

113:                                              ; preds = %109, %105
  call void @llvm.lifetime.end.p0(i64 8, ptr %16) #6
  br label %119

114:                                              ; preds = %103, %100, %97, %94
  %115 = landingpad { ptr, i32 }
          cleanup
  %116 = extractvalue { ptr, i32 } %115, 0
  store ptr %116, ptr %7, align 8
  %117 = extractvalue { ptr, i32 } %115, 1
  store i32 %117, ptr %8, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #6
  br label %119

118:                                              ; preds = %104, %99
  store i32 0, ptr %3, align 4
  store i32 1, ptr %9, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %15) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %14) #6
  br label %120

119:                                              ; preds = %114, %113
  call void @llvm.lifetime.end.p0(i64 24, ptr %15) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %14) #6
  br label %121

120:                                              ; preds = %118, %71
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #6
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %12) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #6
  br label %124

121:                                              ; preds = %119, %72
  call void @llvm.lifetime.end.p0(i64 4, ptr %13) #6
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %12) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %12) #6
  br label %122

122:                                              ; preds = %121, %60
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %11) #6
  br label %123

123:                                              ; preds = %122, %56
  call void @llvm.lifetime.end.p0(i64 24, ptr %11) #6
  br label %125

124:                                              ; preds = %120, %45, %34
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %126

125:                                              ; preds = %123, %35
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %10) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr %10) #6
  br label %128

126:                                              ; preds = %124, %23
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149) %6) #6
  call void @llvm.lifetime.end.p0(i64 152, ptr %6) #6
  %127 = load i32, ptr %3, align 4
  ret i32 %127

128:                                              ; preds = %125, %24
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149) %6) #6
  call void @llvm.lifetime.end.p0(i64 152, ptr %6) #6
  br label %129

129:                                              ; preds = %128
  %130 = load ptr, ptr %7, align 8
  %131 = load i32, ptr %8, align 4
  %132 = insertvalue { ptr, i32 } poison, ptr %130, 0
  %133 = insertvalue { ptr, i32 } %132, i32 %131, 1
  resume { ptr, i32 } %133
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim18BitstringsFromFileINS_6IOFileEEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorImSaImEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24)) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8), float noundef, float noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15WriteAmplitudesImSt7complexIfEEbRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt6vectorIT_SaISB_EERKSA_IT0_SaISG_EE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"any pointer", !7, i64 0}
!11 = !{!12, !6, i64 128}
!12 = !{!"_ZTS7Options", !13, i64 0, !13, i64 32, !13, i64 64, !16, i64 96, !15, i64 120, !6, i64 128, !6, i64 132, !6, i64 136, !6, i64 140, !6, i64 144, !20, i64 148}
!13 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !14, i64 0, !15, i64 8, !7, i64 16}
!14 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !10, i64 0}
!15 = !{!"long", !7, i64 0}
!16 = !{!"_ZTSSt6vectorIjSaIjEE", !17, i64 0}
!17 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !19, i64 0}
!19 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!20 = !{!"bool", !7, i64 0}
!21 = !{!22, !6, i64 0}
!22 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !6, i64 0, !23, i64 8}
!23 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !24, i64 0}
!24 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !26, i64 0}
!26 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !10, i64 0, !10, i64 8, !10, i64 16}
!27 = !{!12, !20, i64 148}
!28 = !{i8 0, i8 2}
!29 = !{}
!30 = !{!12, !15, i64 120}
!31 = !{!32, !15, i64 8}
!32 = !{!"_ZTSN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterE", !33, i64 0, !15, i64 8, !6, i64 16, !6, i64 20, !6, i64 24}
!33 = !{!"_ZTSN4qsim14BasicGateFuserINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEES0_NS_13SequentialForEE10GateHybridEE9ParameterE", !6, i64 0}
!34 = !{!12, !6, i64 132}
!35 = !{!32, !6, i64 16}
!36 = !{!12, !6, i64 136}
!37 = !{!32, !6, i64 20}
!38 = !{!12, !6, i64 140}
!39 = !{!32, !6, i64 24}
!40 = !{!12, !6, i64 144}
!41 = !{!33, !6, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.Options = type <{ %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", %"class.std::__cxx11::basic_string", %"class.std::vector", i64, i32, i32, i32, i32, i32, i8, [3 x i8] }>
%"class.std::__cxx11::basic_string" = type { %"struct.std::__cxx11::basic_string<char>::_Alloc_hider", i64, %union.anon }
%"struct.std::__cxx11::basic_string<char>::_Alloc_hider" = type { ptr }
%union.anon = type { i64, [8 x i8] }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::Circuit" = type { i32, %"class.std::vector.3" }
%"class.std::vector.3" = type { %"struct.std::_Vector_base.4" }
%"struct.std::_Vector_base.4" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl" = type { %"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<qsim::Gate<float, qsim::GateKind>, std::allocator<qsim::Gate<float, qsim::GateKind>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.8" = type { %"struct.std::_Vector_base.9" }
%"struct.std::_Vector_base.9" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl" = type { %"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" }
%"struct.std::_Vector_base<unsigned long, std::allocator<unsigned long>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter" = type <{ %"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter", [4 x i8], i64, i32, i32, i32, [4 x i8] }>
%"struct.qsim::BasicGateFuser<qsim::IO, qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::GateHybrid>::Parameter" = type { i32 }
%"class.std::vector.13" = type { %"struct.std::_Vector_base.14" }
%"struct.std::_Vector_base.14" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::complex<float>, std::allocator<std::complex<float>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::complex" = type { { float, float } }
%"class.std::allocator.15" = type { i8 }
%struct.Factory = type { i32 }

@.str.5 = external hidden unnamed_addr constant [11 x i8], align 1

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10GetOptionsiPPc(ptr dead_on_unwind noalias writable sret(%struct.Options) align 8, i32 noundef, ptr noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(149)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind noalias writable sret(%"class.std::vector") align 8, i32 noundef, ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress norecurse uwtable
define dso_local noundef range(i32 0, 2) i32 @main(i32 noundef %0, ptr noundef %1) local_unnamed_addr #4 personality ptr @__gxx_personality_v0 {
  %3 = alloca %struct.Options, align 8
  %4 = alloca %"struct.qsim::Circuit", align 8
  %5 = alloca %"class.std::vector", align 8
  %6 = alloca %"class.std::vector.8", align 8
  %7 = alloca %"struct.qsim::HybridSimulator<qsim::IO, qsim::Gate<float, qsim::GateKind>, qsim::BasicGateFuser, qsim::SequentialFor>::Parameter", align 8
  %8 = alloca %"class.std::vector.13", align 8
  %9 = alloca %"class.std::complex", align 4
  %10 = alloca %"class.std::allocator.15", align 1
  %11 = alloca %struct.Factory, align 4
  call void @llvm.lifetime.start.p0(i64 152, ptr nonnull %3) #6
  call void @_Z10GetOptionsiPPc(ptr dead_on_unwind nonnull writable sret(%struct.Options) align 8 %3, i32 noundef %0, ptr noundef %1)
  %12 = invoke noundef zeroext i1 @_Z15ValidateOptionsRK7Options(ptr noundef nonnull align 8 dereferenceable(149) %3)
          to label %13 unwind label %14

13:                                               ; preds = %2
  br i1 %12, label %16, label %76

14:                                               ; preds = %2
  %15 = landingpad { ptr, i32 }
          cleanup
  br label %77

16:                                               ; preds = %13
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %4) #6
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  %17 = getelementptr inbounds i8, ptr %3, i64 128
  %18 = load i32, ptr %17, align 8, !tbaa !5
  %19 = invoke noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef %18, ptr noundef nonnull align 8 dereferenceable(32) %3, ptr noundef nonnull align 8 dereferenceable(32) %4)
          to label %20 unwind label %21

20:                                               ; preds = %16
  br i1 %19, label %23, label %74

21:                                               ; preds = %23, %16
  %22 = landingpad { ptr, i32 }
          cleanup
  br label %75

23:                                               ; preds = %20
  %24 = load i32, ptr %4, align 8, !tbaa !19
  %25 = getelementptr inbounds i8, ptr %3, i64 96
  %26 = invoke noundef zeroext i1 @_Z13ValidatePart1jRKSt6vectorIjSaIjEE(i32 noundef %24, ptr noundef nonnull align 8 dereferenceable(24) %25)
          to label %27 unwind label %21

27:                                               ; preds = %23
  br i1 %26, label %28, label %74

28:                                               ; preds = %27
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %5) #6
  %29 = load i32, ptr %4, align 8, !tbaa !19
  invoke void @_Z8GetPartsjRKSt6vectorIjSaIjEE(ptr dead_on_unwind nonnull writable sret(%"class.std::vector") align 8 %5, i32 noundef %29, ptr noundef nonnull align 8 dereferenceable(24) %25)
          to label %30 unwind label %35

30:                                               ; preds = %28
  %31 = getelementptr inbounds i8, ptr %3, i64 148
  %32 = load i8, ptr %31, align 4, !tbaa !25, !range !26, !noundef !27
  %33 = trunc nuw i8 %32 to i1
  br i1 %33, label %34, label %37

34:                                               ; preds = %30
  call void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv()
  br label %37

35:                                               ; preds = %28
  %36 = landingpad { ptr, i32 }
          cleanup
  br label %73

37:                                               ; preds = %34, %30
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %6) #6
  call void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #6
  %38 = load i32, ptr %4, align 8, !tbaa !19
  %39 = getelementptr inbounds i8, ptr %3, i64 32
  %40 = invoke noundef zeroext i1 @_ZN4qsim18BitstringsFromFileINS_6IOFileEEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorImSaImEE(i32 noundef %38, ptr noundef nonnull align 8 dereferenceable(32) %39, ptr noundef nonnull align 8 dereferenceable(24) %6)
          to label %41 unwind label %42

41:                                               ; preds = %37
  br i1 %40, label %44, label %71

42:                                               ; preds = %37
  %43 = landingpad { ptr, i32 }
          cleanup
  br label %72

44:                                               ; preds = %41
  call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %7) #6
  call void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28) %7) #6
  %45 = getelementptr inbounds i8, ptr %3, i64 120
  %46 = load i64, ptr %45, align 8, !tbaa !28
  %47 = getelementptr inbounds i8, ptr %7, i64 8
  store i64 %46, ptr %47, align 8, !tbaa !29
  %48 = getelementptr inbounds i8, ptr %3, i64 132
  %49 = getelementptr inbounds i8, ptr %7, i64 16
  %50 = load <2 x i32>, ptr %48, align 4, !tbaa !32
  store <2 x i32> %50, ptr %49, align 8, !tbaa !32
  %51 = getelementptr inbounds i8, ptr %3, i64 140
  %52 = load i32, ptr %51, align 4, !tbaa !33
  %53 = getelementptr inbounds i8, ptr %7, i64 24
  store i32 %52, ptr %53, align 8, !tbaa !34
  %54 = getelementptr inbounds i8, ptr %3, i64 144
  %55 = load i32, ptr %54, align 8, !tbaa !35
  store i32 %55, ptr %7, align 8, !tbaa !36
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %8) #6
  %56 = call noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #6
  call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %9) #6
  call void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8) %9, float noundef 0.000000e+00, float noundef 0.000000e+00)
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %10) #6
  call void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1) %10) #6
  invoke void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %56, ptr noundef nonnull align 4 dereferenceable(8) %9, ptr noundef nonnull align 1 dereferenceable(1) %10)
          to label %57 unwind label %65

57:                                               ; preds = %44
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %10) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %10) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %9) #6
  call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %11) #6
  %58 = load i32, ptr %51, align 4, !tbaa !33
  call void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4) %11, i32 noundef %58)
  %59 = invoke noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28) %7, ptr noundef nonnull align 4 dereferenceable(4) %11, ptr noundef nonnull align 8 dereferenceable(32) %4, ptr noundef nonnull align 8 dereferenceable(24) %5, ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %8)
          to label %60 unwind label %67

60:                                               ; preds = %57
  br i1 %59, label %61, label %69

61:                                               ; preds = %60
  %62 = getelementptr inbounds i8, ptr %3, i64 64
  %63 = invoke noundef zeroext i1 @_Z15WriteAmplitudesImSt7complexIfEEbRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt6vectorIT_SaISB_EERKSA_IT0_SaISG_EE(ptr noundef nonnull align 8 dereferenceable(32) %62, ptr noundef nonnull align 8 dereferenceable(24) %6, ptr noundef nonnull align 8 dereferenceable(24) %8)
          to label %64 unwind label %67

64:                                               ; preds = %61
  call void (ptr, ...) @_ZN4qsim2IO8messagefEPKcz(ptr noundef nonnull @.str.5)
  br label %69

65:                                               ; preds = %44
  %66 = landingpad { ptr, i32 }
          cleanup
  call void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1) %10) #6
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %10) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %9) #6
  br label %70

67:                                               ; preds = %61, %57
  %68 = landingpad { ptr, i32 }
          cleanup
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %11) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  br label %70

69:                                               ; preds = %64, %60
  call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %11) #6
  call void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %8) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %8) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %7) #6
  br label %71

70:                                               ; preds = %67, %65
  %.pn = phi { ptr, i32 } [ %68, %67 ], [ %66, %65 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %8) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %7) #6
  br label %72

71:                                               ; preds = %41, %69
  %.0 = phi i32 [ 0, %69 ], [ 1, %41 ]
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %6) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %5) #6
  br label %74

72:                                               ; preds = %70, %42
  %.pn.pn = phi { ptr, i32 } [ %.pn, %70 ], [ %43, %42 ]
  call void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %6) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %6) #6
  call void @_ZNSt6vectorIjSaIjEED2Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  br label %73

73:                                               ; preds = %72, %35
  %.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn, %72 ], [ %36, %35 ]
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %5) #6
  br label %75

74:                                               ; preds = %27, %20, %71
  %.1 = phi i32 [ %.0, %71 ], [ 1, %20 ], [ 1, %27 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %76

75:                                               ; preds = %73, %21
  %.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn, %73 ], [ %22, %21 ]
  call void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32) %4) #6
  call void @llvm.lifetime.end.p0(i64 32, ptr nonnull %4) #6
  br label %77

76:                                               ; preds = %13, %74
  %.2 = phi i32 [ %.1, %74 ], [ 1, %13 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149) %3) #6
  call void @llvm.lifetime.end.p0(i64 152, ptr nonnull %3) #6
  ret i32 %.2

77:                                               ; preds = %75, %14
  %.pn.pn.pn.pn.pn = phi { ptr, i32 } [ %.pn.pn.pn.pn, %75 ], [ %15, %14 ]
  call void @_ZN7OptionsD2Ev(ptr noundef nonnull align 8 dereferenceable(149) %3) #6
  call void @llvm.lifetime.end.p0(i64 152, ptr nonnull %3) #6
  resume { ptr, i32 } %.pn.pn.pn.pn.pn
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEC2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim17CircuitQsimParserINS_6IOFileEE8FromFileIfEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERNS_7CircuitINS_4GateIT_NS_8GateKindEEEEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #0 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim34SetFlushToZeroAndDenormalsAreZerosEv() local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEEC2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef zeroext i1 @_ZN4qsim18BitstringsFromFileINS_6IOFileEEEbjRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorImSaImEE(i32 noundef, ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterC2Ev(ptr noundef nonnull align 8 dereferenceable(28)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorImSaImEE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt7complexIfEC2Eff(ptr noundef nonnull align 4 dereferenceable(8), float noundef, float noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSaISt7complexIfEEC2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EEC2EmRKS1_RKS2_(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef, ptr noundef nonnull align 4 dereferenceable(8), ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare hidden void @_ZZ4mainEN7FactoryC2Ej(ptr noundef nonnull align 4 dereferenceable(4), i32 noundef) unnamed_addr #3 align 2

; Function Attrs: mustprogress uwtable
declare hidden noundef zeroext i1 @_ZN4qsim11QSimHRunnerINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEEEE3RunIZ4mainE7FactoryNS_7CircuitIS5_EEEEbRKNS8_9ParameterERKT_RKT0_RKSt6vectorIjSaIjEERKSN_ImSaImEERSN_ISt7complexIfESaISX_EE(ptr noundef nonnull align 8 dereferenceable(28), ptr noundef nonnull align 4 dereferenceable(4), ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
declare dso_local noundef zeroext i1 @_Z15WriteAmplitudesImSt7complexIfEEbRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKSt6vectorIT_SaISB_EERKSA_IT0_SaISG_EE(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim2IO8messagefEPKcz(ptr noundef, ...) local_unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorISt7complexIfESaIS1_EED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt6vectorImSaImEED2Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN4qsim7CircuitINS_4GateIfNS_8GateKindEEEED2Ev(ptr noundef nonnull align 8 dereferenceable(32)) unnamed_addr #2 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZNSt15__new_allocatorISt7complexIfEED2Ev(ptr noundef nonnull align 1 dereferenceable(1)) unnamed_addr #3 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress norecurse uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !17, i64 128}
!6 = !{!"_ZTS7Options", !7, i64 0, !7, i64 32, !7, i64 64, !13, i64 96, !12, i64 120, !17, i64 128, !17, i64 132, !17, i64 136, !17, i64 140, !17, i64 144, !18, i64 148}
!7 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE", !8, i64 0, !12, i64 8, !10, i64 16}
!8 = !{!"_ZTSNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderE", !9, i64 0}
!9 = !{!"any pointer", !10, i64 0}
!10 = !{!"omnipotent char", !11, i64 0}
!11 = !{!"Simple C++ TBAA"}
!12 = !{!"long", !10, i64 0}
!13 = !{!"_ZTSSt6vectorIjSaIjEE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseIjSaIjEE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIjSaIjEE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!17 = !{!"int", !10, i64 0}
!18 = !{!"bool", !10, i64 0}
!19 = !{!20, !17, i64 0}
!20 = !{!"_ZTSN4qsim7CircuitINS_4GateIfNS_8GateKindEEEEE", !17, i64 0, !21, i64 8}
!21 = !{!"_ZTSSt6vectorIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !22, i64 0}
!22 = !{!"_ZTSSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE", !23, i64 0}
!23 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE12_Vector_implE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN4qsim4GateIfNS0_8GateKindEEESaIS3_EE17_Vector_impl_dataE", !9, i64 0, !9, i64 8, !9, i64 16}
!25 = !{!6, !18, i64 148}
!26 = !{i8 0, i8 2}
!27 = !{}
!28 = !{!6, !12, i64 120}
!29 = !{!30, !12, i64 8}
!30 = !{!"_ZTSN4qsim15HybridSimulatorINS_2IOENS_4GateIfNS_8GateKindEEENS_14BasicGateFuserENS_13SequentialForEE9ParameterE", !31, i64 0, !12, i64 8, !17, i64 16, !17, i64 20, !17, i64 24}
!31 = !{!"_ZTSN4qsim14BasicGateFuserINS_2IOENS_15HybridSimulatorIS1_NS_4GateIfNS_8GateKindEEES0_NS_13SequentialForEE10GateHybridEE9ParameterE", !17, i64 0}
!32 = !{!17, !17, i64 0}
!33 = !{!6, !17, i64 140}
!34 = !{!30, !17, i64 24}
!35 = !{!6, !17, i64 144}
!36 = !{!31, !17, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,SLPVectorizerPass,SROAPass,SimplifyCFGPass