; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis7 (DataQueryDatumSpecification)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::DataQueryDatumSpecification" = type { ptr, i32, i32, %"class.std::vector", %"class.std::vector" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DIS::UnsignedDISInteger, std::allocator<DIS::UnsignedDISInteger>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::UnsignedDISInteger, std::allocator<DIS::UnsignedDISInteger>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::UnsignedDISInteger, std::allocator<DIS::UnsignedDISInteger>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::UnsignedDISInteger, std::allocator<DIS::UnsignedDISInteger>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS27DataQueryDatumSpecificationeqERKS0_(ptr noundef nonnull align 8 dereferenceable(64) %0, ptr noundef nonnull align 8 dereferenceable(64) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  store i8 1, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !11
  br label %9

9:                                                ; preds = %26, %2
  %10 = load i64, ptr %6, align 8, !tbaa !11
  %11 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %8, i32 0, i32 3
  %12 = call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %11) #4
  %13 = icmp ult i64 %10, %12
  br i1 %13, label %15, label %14

14:                                               ; preds = %9
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  br label %29

15:                                               ; preds = %9
  %16 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %8, i32 0, i32 3
  %17 = load i64, ptr %6, align 8, !tbaa !11
  %18 = call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %17) #4
  %19 = load ptr, ptr %4, align 8, !tbaa !5
  %20 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %19, i32 0, i32 3
  %21 = load i64, ptr %6, align 8, !tbaa !11
  %22 = call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %20, i64 noundef %21) #4
  %23 = call noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %18, ptr noundef nonnull align 8 dereferenceable(12) %22)
  br i1 %23, label %25, label %24

24:                                               ; preds = %15
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %25

25:                                               ; preds = %24, %15
  br label %26

26:                                               ; preds = %25
  %27 = load i64, ptr %6, align 8, !tbaa !11
  %28 = add i64 %27, 1
  store i64 %28, ptr %6, align 8, !tbaa !11
  br label %9, !llvm.loop !13

29:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  store i64 0, ptr %7, align 8, !tbaa !11
  br label %30

30:                                               ; preds = %47, %29
  %31 = load i64, ptr %7, align 8, !tbaa !11
  %32 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %8, i32 0, i32 4
  %33 = call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %32) #4
  %34 = icmp ult i64 %31, %33
  br i1 %34, label %36, label %35

35:                                               ; preds = %30
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %50

36:                                               ; preds = %30
  %37 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %8, i32 0, i32 4
  %38 = load i64, ptr %7, align 8, !tbaa !11
  %39 = call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %38) #4
  %40 = load ptr, ptr %4, align 8, !tbaa !5
  %41 = getelementptr inbounds %"class.DIS::DataQueryDatumSpecification", ptr %40, i32 0, i32 4
  %42 = load i64, ptr %7, align 8, !tbaa !11
  %43 = call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %42) #4
  %44 = call noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %39, ptr noundef nonnull align 8 dereferenceable(12) %43)
  br i1 %44, label %46, label %45

45:                                               ; preds = %36
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %46

46:                                               ; preds = %45, %36
  br label %47

47:                                               ; preds = %46
  %48 = load i64, ptr %7, align 8, !tbaa !11
  %49 = add i64 %48, 1
  store i64 %49, ptr %7, align 8, !tbaa !11
  br label %30, !llvm.loop !15

50:                                               ; preds = %35
  %51 = load i8, ptr %5, align 1, !tbaa !9, !range !16, !noundef !17
  %52 = trunc i8 %51 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i1 %52
}

declare noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = !{i8 0, i8 2}
!17 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS27DataQueryDatumSpecificationeqERKS0_(ptr noundef nonnull align 8 dereferenceable(64) %0, ptr noundef nonnull align 8 dereferenceable(64) %1) local_unnamed_addr #1 align 2 {
  %3 = getelementptr inbounds i8, ptr %0, i64 16
  %4 = tail call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  %.not = icmp eq i64 %4, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %5 = getelementptr inbounds i8, ptr %1, i64 16
  br label %9

.preheader:                                       ; preds = %9, %2
  %.012.lcssa = phi i1 [ true, %2 ], [ %spec.select, %9 ]
  %6 = getelementptr inbounds i8, ptr %0, i64 40
  %7 = tail call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %.not20 = icmp eq i64 %7, 0
  br i1 %.not20, label %._crit_edge, label %.lr.ph18

.lr.ph18:                                         ; preds = %.preheader
  %8 = getelementptr inbounds i8, ptr %1, i64 40
  br label %16

9:                                                ; preds = %.lr.ph, %9
  %.01115 = phi i64 [ 0, %.lr.ph ], [ %13, %9 ]
  %.01214 = phi i1 [ true, %.lr.ph ], [ %spec.select, %9 ]
  %10 = tail call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %.01115) #3
  %11 = tail call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %.01115) #3
  %12 = tail call noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %10, ptr noundef nonnull align 8 dereferenceable(12) %11)
  %spec.select = select i1 %12, i1 %.01214, i1 false
  %13 = add nuw i64 %.01115, 1
  %14 = tail call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %3) #3
  %15 = icmp ult i64 %13, %14
  br i1 %15, label %9, label %.preheader, !llvm.loop !5

._crit_edge:                                      ; preds = %16, %.preheader
  %.2.lcssa = phi i1 [ %.012.lcssa, %.preheader ], [ %spec.select13, %16 ]
  ret i1 %.2.lcssa

16:                                               ; preds = %.lr.ph18, %16
  %.017 = phi i64 [ 0, %.lr.ph18 ], [ %20, %16 ]
  %.216 = phi i1 [ %.012.lcssa, %.lr.ph18 ], [ %spec.select13, %16 ]
  %17 = tail call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %.017) #3
  %18 = tail call noundef nonnull align 8 dereferenceable(12) ptr @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %.017) #3
  %19 = tail call noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %17, ptr noundef nonnull align 8 dereferenceable(12) %18)
  %spec.select13 = select i1 %19, i1 %.216, i1 false
  %20 = add nuw i64 %.017, 1
  %21 = tail call noundef i64 @_ZNKSt6vectorIN3DIS18UnsignedDISIntegerESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %6) #3
  %22 = icmp ult i64 %20, %21
  br i1 %22, label %16, label %._crit_edge, !llvm.loop !7
}

declare noundef zeroext i1 @_ZNK3DIS18UnsignedDISIntegereqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}
!7 = distinct !{!7, !6}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass