; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/pcuda (pcuda_device_topology)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.hipsycl::rt::pcuda::device_topology::backend" = type { i32, i32, ptr, %"class.std::vector.36" }
%"class.std::vector.36" = type { %"struct.std::_Vector_base.37" }
%"struct.std::_Vector_base.37" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::platform, std::allocator<hipsycl::rt::pcuda::device_topology::platform>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology11get_backendEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2) #1 align 2 {
  %4 = alloca ptr, align 8
  %5 = alloca ptr, align 8
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  store ptr %0, ptr %5, align 8, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !9
  store i32 %2, ptr %7, align 4, !tbaa !9
  %10 = load ptr, ptr %5, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %8) #2
  %11 = load i32, ptr %6, align 4, !tbaa !9
  %12 = call noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology11get_backendEi(ptr noundef nonnull align 8 dereferenceable(24) %10, i32 noundef %11)
  store ptr %12, ptr %8, align 8, !tbaa !5
  %13 = load ptr, ptr %8, align 8, !tbaa !5
  %14 = icmp ne ptr %13, null
  br i1 %14, label %16, label %15

15:                                               ; preds = %3
  store ptr null, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

16:                                               ; preds = %3
  %17 = load i32, ptr %7, align 4, !tbaa !9
  %18 = icmp slt i32 %17, 0
  br i1 %18, label %26, label %19

19:                                               ; preds = %16
  %20 = load i32, ptr %7, align 4, !tbaa !9
  %21 = sext i32 %20 to i64
  %22 = load ptr, ptr %8, align 8, !tbaa !5
  %23 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::backend", ptr %22, i32 0, i32 3
  %24 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %23) #2
  %25 = icmp uge i64 %21, %24
  br i1 %25, label %26, label %27

26:                                               ; preds = %19, %16
  store ptr null, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

27:                                               ; preds = %19
  %28 = load ptr, ptr %8, align 8, !tbaa !5
  %29 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::backend", ptr %28, i32 0, i32 3
  %30 = load i32, ptr %7, align 4, !tbaa !9
  %31 = sext i32 %30 to i64
  %32 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %29, i64 noundef %31) #2
  store ptr %32, ptr %4, align 8
  store i32 1, ptr %9, align 4
  br label %33

33:                                               ; preds = %27, %26, %15
  call void @llvm.lifetime.end.p0(i64 8, ptr %8) #2
  %34 = load ptr, ptr %4, align 8
  ret ptr %34
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology11get_backendEi(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 align 2 {
  %4 = tail call noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology11get_backendEi(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1)
  %.not = icmp eq ptr %4, null
  %5 = icmp slt i32 %2, 0
  %or.cond = or i1 %5, %.not
  br i1 %or.cond, label %12, label %6

6:                                                ; preds = %3
  %7 = zext nneg i32 %2 to i64
  %8 = getelementptr inbounds i8, ptr %4, i64 16
  %9 = tail call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #1
  %.not11 = icmp ugt i64 %9, %7
  br i1 %.not11, label %10, label %12

10:                                               ; preds = %6
  %11 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %7) #1
  br label %12

12:                                               ; preds = %6, %3, %10
  %.0 = phi ptr [ %11, %10 ], [ null, %3 ], [ null, %6 ]
  ret ptr %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology8platformESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass