; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu (rnn)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.RNNParamSpec = type { i32, i32, i32, i32, float, float, i8, float, i32 }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z24rnn_transform_filter_cpuPK10TensorDescPPKv12RNNParamSpecPS_PPvPf4Arch(ptr noundef %0, ptr noundef %1, ptr noundef byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, i32 noundef %6) #0 {
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca ptr, align 8
  %12 = alloca ptr, align 8
  %13 = alloca i32, align 4
  %14 = alloca i32, align 4
  %15 = alloca i32, align 4
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca i32, align 4
  %19 = alloca i32, align 4
  %20 = alloca i32, align 4
  %21 = alloca %struct.TensorDesc, align 8
  %22 = alloca %struct.RNNParamSpec, align 8
  %23 = alloca i32, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store ptr %1, ptr %9, align 8, !tbaa !5
  store ptr %3, ptr %10, align 8, !tbaa !5
  store ptr %4, ptr %11, align 8, !tbaa !5
  store ptr %5, ptr %12, align 8, !tbaa !5
  store i32 %6, ptr %13, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %14) #8
  %24 = getelementptr inbounds %struct.RNNParamSpec, ptr %2, i32 0, i32 6
  %25 = load i8, ptr %24, align 8, !tbaa !11, !range !18, !noundef !19
  %26 = trunc i8 %25 to i1
  %27 = zext i1 %26 to i64
  %28 = select i1 %26, i32 2, i32 1
  store i32 %28, ptr %14, align 4, !tbaa !20
  call void @llvm.lifetime.start.p0(i64 4, ptr %15) #8
  %29 = getelementptr inbounds %struct.RNNParamSpec, ptr %2, i32 0, i32 3
  %30 = load i32, ptr %29, align 4, !tbaa !21
  %31 = icmp sgt i32 %30, 0
  %32 = zext i1 %31 to i64
  %33 = select i1 %31, i32 2, i32 1
  store i32 %33, ptr %15, align 4, !tbaa !20
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #8
  %34 = load i32, ptr %14, align 4, !tbaa !20
  %35 = load i32, ptr %15, align 4, !tbaa !20
  %36 = mul i32 %34, %35
  store i32 %36, ptr %16, align 4, !tbaa !20
  call void @llvm.lifetime.start.p0(i64 4, ptr %17) #8
  store i32 0, ptr %17, align 4, !tbaa !22
  call void @llvm.lifetime.start.p0(i64 4, ptr %18) #8
  call void @llvm.lifetime.start.p0(i64 4, ptr %19) #8
  store i32 0, ptr %19, align 4, !tbaa !20
  br label %37

37:                                               ; preds = %108, %7
  %38 = load i32, ptr %19, align 4, !tbaa !20
  %39 = load i32, ptr %16, align 4, !tbaa !20
  %40 = icmp ult i32 %38, %39
  br i1 %40, label %42, label %41

41:                                               ; preds = %37
  call void @llvm.lifetime.end.p0(i64 4, ptr %19) #8
  br label %111

42:                                               ; preds = %37
  %43 = load i32, ptr %19, align 4, !tbaa !20
  %44 = urem i32 %43, 2
  %45 = icmp eq i32 %44, 0
  br i1 %45, label %49, label %46

46:                                               ; preds = %42
  %47 = load i32, ptr %15, align 4, !tbaa !20
  %48 = icmp eq i32 %47, 1
  br i1 %48, label %49, label %65

49:                                               ; preds = %46, %42
  %50 = getelementptr inbounds %struct.RNNParamSpec, ptr %2, i32 0, i32 2
  %51 = load i32, ptr %50, align 8, !tbaa !24
  %52 = icmp sge i32 %51, 0
  br i1 %52, label %53, label %65

53:                                               ; preds = %49
  %54 = load ptr, ptr %12, align 8, !tbaa !5
  %55 = icmp eq ptr %54, null
  br i1 %55, label %64, label %56

56:                                               ; preds = %53
  %57 = load ptr, ptr %12, align 8, !tbaa !5
  %58 = load i32, ptr %16, align 4, !tbaa !20
  %59 = add i32 %58, 1
  %60 = zext i32 %59 to i64
  %61 = getelementptr inbounds float, ptr %57, i64 %60
  %62 = load float, ptr %61, align 4, !tbaa !25
  %63 = fcmp une float %62, -3.000000e+00
  br i1 %63, label %64, label %65

64:                                               ; preds = %56, %53
  store i32 40, ptr %18, align 4, !tbaa !26
  br label %66

65:                                               ; preds = %56, %49, %46
  store i32 19, ptr %18, align 4, !tbaa !26
  br label %66

66:                                               ; preds = %65, %64
  call void @llvm.lifetime.start.p0(i64 4, ptr %20) #8
  %67 = load ptr, ptr %8, align 8, !tbaa !5
  %68 = load i32, ptr %19, align 4, !tbaa !20
  %69 = zext i32 %68 to i64
  %70 = getelementptr inbounds %struct.TensorDesc, ptr %67, i64 %69
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %21, ptr align 4 %70, i64 92, i1 false), !tbaa.struct !28
  %71 = load ptr, ptr %9, align 8, !tbaa !5
  %72 = load i32, ptr %19, align 4, !tbaa !20
  %73 = zext i32 %72 to i64
  %74 = getelementptr inbounds ptr, ptr %71, i64 %73
  %75 = load ptr, ptr %74, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %22, ptr align 8 %2, i64 36, i1 false), !tbaa.struct !32
  %76 = load ptr, ptr %10, align 8, !tbaa !5
  %77 = load i32, ptr %19, align 4, !tbaa !20
  %78 = zext i32 %77 to i64
  %79 = getelementptr inbounds %struct.TensorDesc, ptr %76, i64 %78
  %80 = load ptr, ptr %11, align 8, !tbaa !5
  %81 = load i32, ptr %19, align 4, !tbaa !20
  %82 = zext i32 %81 to i64
  %83 = getelementptr inbounds ptr, ptr %80, i64 %82
  %84 = load ptr, ptr %83, align 8, !tbaa !5
  %85 = load ptr, ptr %12, align 8, !tbaa !5
  %86 = load i32, ptr %19, align 4, !tbaa !20
  %87 = zext i32 %86 to i64
  %88 = getelementptr inbounds float, ptr %85, i64 %87
  %89 = getelementptr inbounds float, ptr %88, i64 1
  %90 = load i32, ptr %18, align 4, !tbaa !26
  %91 = load i32, ptr %13, align 4, !tbaa !9
  %92 = call noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %21, ptr noundef %75, ptr noundef byval(%struct.RNNParamSpec) align 8 %22, ptr noundef %79, ptr noundef %84, ptr noundef %89, i32 noundef %90, i32 noundef %91)
  store i32 %92, ptr %20, align 4, !tbaa !22
  %93 = load i32, ptr %20, align 4, !tbaa !22
  %94 = icmp ne i32 %93, 0
  br i1 %94, label %95, label %107

95:                                               ; preds = %66
  call void @llvm.lifetime.start.p0(i64 4, ptr %23) #8
  %96 = call i64 (i64, ...) @syscall(i64 noundef 186) #8
  %97 = trunc i64 %96 to i32
  store i32 %97, ptr %23, align 4, !tbaa !20
  %98 = load i32, ptr %23, align 4, !tbaa !20
  %99 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %98)
  %100 = load ptr, ptr @stdout, align 8, !tbaa !5
  %101 = call i32 @fflush(ptr noundef %100)
  %102 = load i32, ptr %20, align 4, !tbaa !22
  %103 = call ptr @ee2str(i32 noundef %102)
  %104 = call i32 (ptr, ...) @printf(ptr noundef @.str.1, ptr noundef %103)
  %105 = load ptr, ptr @stdout, align 8, !tbaa !5
  %106 = call i32 @fflush(ptr noundef %105)
  call void @exit(i32 noundef 1) #9
  unreachable

107:                                              ; preds = %66
  call void @llvm.lifetime.end.p0(i64 4, ptr %20) #8
  br label %108

108:                                              ; preds = %107
  %109 = load i32, ptr %19, align 4, !tbaa !20
  %110 = add i32 %109, 1
  store i32 %110, ptr %19, align 4, !tbaa !20
  br label %37, !llvm.loop !36

111:                                              ; preds = %41
  %112 = load i32, ptr %17, align 4, !tbaa !22
  call void @llvm.lifetime.end.p0(i64 4, ptr %18) #8
  call void @llvm.lifetime.end.p0(i64 4, ptr %17) #8
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #8
  call void @llvm.lifetime.end.p0(i64 4, ptr %15) #8
  call void @llvm.lifetime.end.p0(i64 4, ptr %14) #8
  ret i32 %112
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare hidden noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef byval(%struct.RNNParamSpec) align 8, ptr noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) #2

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #3

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) #4

declare i32 @printf(ptr noundef, ...) #5

declare i32 @fflush(ptr noundef) #5

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) #6

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) #7

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #4 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #7 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #8 = { nounwind }
attributes #9 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS4Arch", !7, i64 0}
!11 = !{!12, !16, i64 24}
!12 = !{!"_ZTS12RNNParamSpec", !13, i64 0, !14, i64 4, !14, i64 8, !14, i64 12, !15, i64 16, !15, i64 20, !16, i64 24, !15, i64 28, !17, i64 32}
!13 = !{!"_ZTS7RNNMode", !7, i64 0}
!14 = !{!"int", !7, i64 0}
!15 = !{!"float", !7, i64 0}
!16 = !{!"bool", !7, i64 0}
!17 = !{!"_ZTS14ActivationMode", !7, i64 0}
!18 = !{i8 0, i8 2}
!19 = !{}
!20 = !{!14, !14, i64 0}
!21 = !{!12, !14, i64 12}
!22 = !{!23, !23, i64 0}
!23 = !{!"_ZTS2EE", !7, i64 0}
!24 = !{!12, !14, i64 8}
!25 = !{!15, !15, i64 0}
!26 = !{!27, !27, i64 0}
!27 = !{!"_ZTS10DataFormat", !7, i64 0}
!28 = !{i64 0, i64 4, !29, i64 4, i64 4, !26, i64 8, i64 4, !20, i64 12, i64 80, !31}
!29 = !{!30, !30, i64 0}
!30 = !{!"_ZTS8DataType", !7, i64 0}
!31 = !{!7, !7, i64 0}
!32 = !{i64 0, i64 4, !33, i64 4, i64 4, !20, i64 8, i64 4, !20, i64 12, i64 4, !20, i64 16, i64 4, !25, i64 20, i64 4, !25, i64 24, i64 1, !34, i64 28, i64 4, !25, i64 32, i64 4, !35}
!33 = !{!13, !13, i64 0}
!34 = !{!16, !16, i64 0}
!35 = !{!17, !17, i64 0}
!36 = distinct !{!36, !37}
!37 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.RNNParamSpec = type { i32, i32, i32, i32, float, float, i8, float, i32 }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }

@.str = external hidden unnamed_addr constant [20 x i8], align 1
@stdout = external local_unnamed_addr global ptr, align 8
@.str.1 = external hidden unnamed_addr constant [18 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef i32 @_Z24rnn_transform_filter_cpuPK10TensorDescPPKv12RNNParamSpecPS_PPvPf4Arch(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %3, ptr nocapture noundef readonly %4, ptr noundef %5, i32 noundef %6) local_unnamed_addr #0 {
  %8 = alloca %struct.TensorDesc, align 8
  %9 = getelementptr inbounds i8, ptr %2, i64 24
  %10 = load i8, ptr %9, align 8, !tbaa !5, !range !14, !noundef !15
  %11 = zext nneg i8 %10 to i32
  %12 = getelementptr inbounds i8, ptr %2, i64 12
  %13 = load i32, ptr %12, align 4, !tbaa !16
  %.fr = freeze i32 %13
  %.inv = icmp slt i32 %.fr, 1
  %14 = select i1 %.inv, i32 1, i32 2
  %15 = shl nuw nsw i32 %14, %11
  %16 = getelementptr inbounds i8, ptr %2, i64 8
  %17 = load i32, ptr %16, align 8
  %.fr53 = freeze i32 %17
  %18 = icmp sgt i32 %.fr53, -1
  %invariant.gep = getelementptr inbounds i8, ptr %5, i64 4
  %19 = zext nneg i32 %15 to i64
  %gep = getelementptr inbounds float, ptr %invariant.gep, i64 %19
  br i1 %18, label %.split, label %.split.us.preheader

.split.us.preheader:                              ; preds = %7
  %wide.trip.count = zext nneg i32 %15 to i64
  br label %.split.us

.split.us:                                        ; preds = %.split.us.preheader, %27
  %indvars.iv = phi i64 [ 0, %.split.us.preheader ], [ %indvars.iv.next, %27 ]
  %20 = getelementptr inbounds %struct.TensorDesc, ptr %0, i64 %indvars.iv
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(92) %8, ptr noundef nonnull align 4 dereferenceable(92) %20, i64 92, i1 false), !tbaa.struct !17
  %21 = getelementptr inbounds ptr, ptr %1, i64 %indvars.iv
  %22 = load ptr, ptr %21, align 8, !tbaa !24
  %23 = getelementptr inbounds %struct.TensorDesc, ptr %3, i64 %indvars.iv
  %24 = getelementptr inbounds ptr, ptr %4, i64 %indvars.iv
  %25 = load ptr, ptr %24, align 8, !tbaa !24
  %gep34.us = getelementptr inbounds float, ptr %invariant.gep, i64 %indvars.iv
  %26 = tail call noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %8, ptr noundef %22, ptr noundef nonnull byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %23, ptr noundef %25, ptr noundef nonnull %gep34.us, i32 noundef 19, i32 noundef %6)
  %.not.us = icmp eq i32 %26, 0
  br i1 %.not.us, label %27, label %.split39.us

27:                                               ; preds = %.split.us
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond.not, label %.split37.us, label %.split.us, !llvm.loop !26

.split:                                           ; preds = %7
  %28 = icmp eq ptr %5, null
  %wide.trip.count84 = zext nneg i32 %15 to i64
  br i1 %28, label %.split.split.us, label %.split.split

.split.split.us:                                  ; preds = %.split, %38
  %indvars.iv80 = phi i64 [ %indvars.iv.next81, %38 ], [ 0, %.split ]
  %29 = and i64 %indvars.iv80, 1
  %30 = icmp eq i64 %29, 0
  %or.cond.us = or i1 %.inv, %30
  %. = select i1 %or.cond.us, i32 40, i32 19
  %31 = getelementptr inbounds %struct.TensorDesc, ptr %0, i64 %indvars.iv80
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(92) %8, ptr noundef nonnull align 4 dereferenceable(92) %31, i64 92, i1 false), !tbaa.struct !17
  %32 = getelementptr inbounds ptr, ptr %1, i64 %indvars.iv80
  %33 = load ptr, ptr %32, align 8, !tbaa !24
  %34 = getelementptr inbounds %struct.TensorDesc, ptr %3, i64 %indvars.iv80
  %35 = getelementptr inbounds ptr, ptr %4, i64 %indvars.iv80
  %36 = load ptr, ptr %35, align 8, !tbaa !24
  %gep34.us42 = getelementptr inbounds float, ptr %invariant.gep, i64 %indvars.iv80
  %37 = tail call noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %8, ptr noundef %33, ptr noundef nonnull byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %34, ptr noundef %36, ptr noundef nonnull %gep34.us42, i32 noundef %., i32 noundef %6)
  %.not.us43 = icmp eq i32 %37, 0
  br i1 %.not.us43, label %38, label %.split39.us

38:                                               ; preds = %.split.split.us
  %indvars.iv.next81 = add nuw nsw i64 %indvars.iv80, 1
  %exitcond85.not = icmp eq i64 %indvars.iv.next81, %wide.trip.count84
  br i1 %exitcond85.not, label %.split37.us, label %.split.split.us, !llvm.loop !26

.split.split:                                     ; preds = %.split
  br i1 %.inv, label %.split.split.split.us, label %.split.split.split

.split.split.split.us:                            ; preds = %.split.split, %48
  %indvars.iv74 = phi i64 [ %indvars.iv.next75, %48 ], [ 0, %.split.split ]
  %39 = load float, ptr %gep, align 4, !tbaa !28
  %40 = fcmp une float %39, -3.000000e+00
  %.0.us48 = select i1 %40, i32 40, i32 19
  %41 = getelementptr inbounds %struct.TensorDesc, ptr %0, i64 %indvars.iv74
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(92) %8, ptr noundef nonnull align 4 dereferenceable(92) %41, i64 92, i1 false), !tbaa.struct !17
  %42 = getelementptr inbounds ptr, ptr %1, i64 %indvars.iv74
  %43 = load ptr, ptr %42, align 8, !tbaa !24
  %44 = getelementptr inbounds %struct.TensorDesc, ptr %3, i64 %indvars.iv74
  %45 = getelementptr inbounds ptr, ptr %4, i64 %indvars.iv74
  %46 = load ptr, ptr %45, align 8, !tbaa !24
  %gep34.us49 = getelementptr inbounds float, ptr %invariant.gep, i64 %indvars.iv74
  %47 = tail call noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %8, ptr noundef %43, ptr noundef nonnull byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %44, ptr noundef %46, ptr noundef nonnull %gep34.us49, i32 noundef %.0.us48, i32 noundef %6)
  %.not.us50 = icmp eq i32 %47, 0
  br i1 %.not.us50, label %48, label %.split39.us

48:                                               ; preds = %.split.split.split.us
  %indvars.iv.next75 = add nuw nsw i64 %indvars.iv74, 1
  %exitcond79.not = icmp eq i64 %indvars.iv.next75, %wide.trip.count84
  br i1 %exitcond79.not, label %.split37.us, label %.split.split.split.us, !llvm.loop !26

49:                                               ; preds = %56
  %indvars.iv.next69 = add nuw nsw i64 %indvars.iv68, 1
  %exitcond73.not = icmp eq i64 %indvars.iv.next69, %wide.trip.count84
  br i1 %exitcond73.not, label %.split37.us, label %.split.split.split, !llvm.loop !26

.split37.us:                                      ; preds = %27, %49, %48, %38
  ret i32 0

.split.split.split:                               ; preds = %.split.split, %49
  %indvars.iv68 = phi i64 [ %indvars.iv.next69, %49 ], [ 0, %.split.split ]
  %50 = and i64 %indvars.iv68, 1
  %51 = icmp eq i64 %50, 0
  br i1 %51, label %52, label %55

52:                                               ; preds = %.split.split.split
  %53 = load float, ptr %gep, align 4, !tbaa !28
  %54 = fcmp une float %53, -3.000000e+00
  br i1 %54, label %56, label %55

55:                                               ; preds = %.split.split.split, %52
  br label %56

56:                                               ; preds = %52, %55
  %.0 = phi i32 [ 19, %55 ], [ 40, %52 ]
  %57 = getelementptr inbounds %struct.TensorDesc, ptr %0, i64 %indvars.iv68
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(92) %8, ptr noundef nonnull align 4 dereferenceable(92) %57, i64 92, i1 false), !tbaa.struct !17
  %58 = getelementptr inbounds ptr, ptr %1, i64 %indvars.iv68
  %59 = load ptr, ptr %58, align 8, !tbaa !24
  %60 = getelementptr inbounds %struct.TensorDesc, ptr %3, i64 %indvars.iv68
  %61 = getelementptr inbounds ptr, ptr %4, i64 %indvars.iv68
  %62 = load ptr, ptr %61, align 8, !tbaa !24
  %gep34 = getelementptr inbounds float, ptr %invariant.gep, i64 %indvars.iv68
  %63 = tail call noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %8, ptr noundef %59, ptr noundef nonnull byval(%struct.RNNParamSpec) align 8 %2, ptr noundef %60, ptr noundef %62, ptr noundef nonnull %gep34, i32 noundef %.0, i32 noundef %6)
  %.not = icmp eq i32 %63, 0
  br i1 %.not, label %49, label %.split39.us

.split39.us:                                      ; preds = %.split.us, %56, %.split.split.split.us, %.split.split.us
  %.us-phi = phi i32 [ %37, %.split.split.us ], [ %47, %.split.split.split.us ], [ %63, %56 ], [ %26, %.split.us ]
  %64 = tail call i64 (i64, ...) @syscall(i64 noundef 186) #6
  %65 = trunc i64 %64 to i32
  %66 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str, i32 noundef %65)
  %67 = load ptr, ptr @stdout, align 8, !tbaa !24
  %68 = tail call i32 @fflush(ptr noundef %67)
  %69 = tail call ptr @ee2str(i32 noundef %.us-phi)
  %70 = tail call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str.1, ptr noundef %69)
  %71 = load ptr, ptr @stdout, align 8, !tbaa !24
  %72 = tail call i32 @fflush(ptr noundef %71)
  tail call void @exit(i32 noundef 1) #7
  unreachable
}

; Function Attrs: mustprogress nounwind uwtable
declare hidden noundef i32 @_ZL31rnn_transform_filter_cpu_kernel10TensorDescPKv12RNNParamSpecPS_PvPf10DataFormat4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef byval(%struct.RNNParamSpec) align 8, ptr noundef, ptr noundef, ptr noundef, i32 noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: nounwind
declare i64 @syscall(i64 noundef, ...) local_unnamed_addr #2

; Function Attrs: nofree nounwind
declare noundef i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #3

; Function Attrs: nofree nounwind
declare noundef i32 @fflush(ptr nocapture noundef) local_unnamed_addr #3

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local ptr @ee2str(i32 noundef) local_unnamed_addr #4

; Function Attrs: noreturn nounwind
declare void @exit(i32 noundef) local_unnamed_addr #5

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }
attributes #7 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 24}
!6 = !{!"_ZTS12RNNParamSpec", !7, i64 0, !10, i64 4, !10, i64 8, !10, i64 12, !11, i64 16, !11, i64 20, !12, i64 24, !11, i64 28, !13, i64 32}
!7 = !{!"_ZTS7RNNMode", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"float", !8, i64 0}
!12 = !{!"bool", !8, i64 0}
!13 = !{!"_ZTS14ActivationMode", !8, i64 0}
!14 = !{i8 0, i8 2}
!15 = !{}
!16 = !{!6, !10, i64 12}
!17 = !{i64 0, i64 4, !18, i64 4, i64 4, !20, i64 8, i64 4, !22, i64 12, i64 80, !23}
!18 = !{!19, !19, i64 0}
!19 = !{!"_ZTS8DataType", !8, i64 0}
!20 = !{!21, !21, i64 0}
!21 = !{!"_ZTS10DataFormat", !8, i64 0}
!22 = !{!10, !10, i64 0}
!23 = !{!8, !8, i64 0}
!24 = !{!25, !25, i64 0}
!25 = !{!"any pointer", !8, i64 0}
!26 = distinct !{!26, !27}
!27 = !{!"llvm.loop.mustprogress"}
!28 = !{!11, !11, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopInstSimplifyPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,MemCpyOptPass,PostOrderFunctionAttrsPass,ReassociatePass,SCCPPass,SROAPass,SimplifyCFGPass,TailCallElimPass