; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis6 (GridAxisRecordRepresentation0)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::GridAxisRecordRepresentation0" = type { %"class.DIS::GridAxisRecord.base", i16, %"class.std::vector" }
%"class.DIS::GridAxisRecord.base" = type <{ ptr, i16, i16 }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DIS::OneByteChunk, std::allocator<DIS::OneByteChunk>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::OneByteChunk, std::allocator<DIS::OneByteChunk>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::OneByteChunk, std::allocator<DIS::OneByteChunk>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::OneByteChunk, std::allocator<DIS::OneByteChunk>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS29GridAxisRecordRepresentation0eqERKS0_(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef nonnull align 8 dereferenceable(40) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %7 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  store i8 1, ptr %5, align 1, !tbaa !9
  %8 = load ptr, ptr %4, align 8, !tbaa !5
  %9 = call noundef zeroext i1 @_ZNK3DIS14GridAxisRecordeqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %7, ptr noundef nonnull align 8 dereferenceable(12) %8)
  %10 = zext i1 %9 to i8
  store i8 %10, ptr %5, align 1, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !11
  br label %11

11:                                               ; preds = %28, %2
  %12 = load i64, ptr %6, align 8, !tbaa !11
  %13 = getelementptr inbounds %"class.DIS::GridAxisRecordRepresentation0", ptr %7, i32 0, i32 2
  %14 = call noundef i64 @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %13) #4
  %15 = icmp ult i64 %12, %14
  br i1 %15, label %17, label %16

16:                                               ; preds = %11
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  br label %31

17:                                               ; preds = %11
  %18 = getelementptr inbounds %"class.DIS::GridAxisRecordRepresentation0", ptr %7, i32 0, i32 2
  %19 = load i64, ptr %6, align 8, !tbaa !11
  %20 = call noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %18, i64 noundef %19) #4
  %21 = load ptr, ptr %4, align 8, !tbaa !5
  %22 = getelementptr inbounds %"class.DIS::GridAxisRecordRepresentation0", ptr %21, i32 0, i32 2
  %23 = load i64, ptr %6, align 8, !tbaa !11
  %24 = call noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %22, i64 noundef %23) #4
  %25 = call noundef zeroext i1 @_ZNK3DIS12OneByteChunkeqERKS0_(ptr noundef nonnull align 8 dereferenceable(9) %20, ptr noundef nonnull align 8 dereferenceable(9) %24)
  br i1 %25, label %27, label %26

26:                                               ; preds = %17
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %27

27:                                               ; preds = %26, %17
  br label %28

28:                                               ; preds = %27
  %29 = load i64, ptr %6, align 8, !tbaa !11
  %30 = add i64 %29, 1
  store i64 %30, ptr %6, align 8, !tbaa !11
  br label %11, !llvm.loop !13

31:                                               ; preds = %16
  %32 = load i8, ptr %5, align 1, !tbaa !9, !range !15, !noundef !16
  %33 = trunc i8 %32 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i1 %33
}

declare noundef zeroext i1 @_ZNK3DIS14GridAxisRecordeqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) #3

declare noundef zeroext i1 @_ZNK3DIS12OneByteChunkeqERKS0_(ptr noundef nonnull align 8 dereferenceable(9), ptr noundef nonnull align 8 dereferenceable(9)) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = !{i8 0, i8 2}
!16 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS29GridAxisRecordRepresentation0eqERKS0_(ptr noundef nonnull align 8 dereferenceable(40) %0, ptr noundef nonnull align 8 dereferenceable(40) %1) local_unnamed_addr #1 align 2 {
  %3 = tail call noundef zeroext i1 @_ZNK3DIS14GridAxisRecordeqERKS0_(ptr noundef nonnull align 8 dereferenceable(12) %0, ptr noundef nonnull align 8 dereferenceable(12) %1)
  %4 = getelementptr inbounds i8, ptr %0, i64 16
  %5 = tail call noundef i64 @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %.not = icmp eq i64 %5, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %6 = getelementptr inbounds i8, ptr %1, i64 16
  br label %7

._crit_edge:                                      ; preds = %7, %2
  %.07.lcssa = phi i1 [ %3, %2 ], [ %spec.select, %7 ]
  ret i1 %.07.lcssa

7:                                                ; preds = %.lr.ph, %7
  %.09 = phi i64 [ 0, %.lr.ph ], [ %11, %7 ]
  %.078 = phi i1 [ %3, %.lr.ph ], [ %spec.select, %7 ]
  %8 = tail call noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %4, i64 noundef %.09) #3
  %9 = tail call noundef nonnull align 8 dereferenceable(9) ptr @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %6, i64 noundef %.09) #3
  %10 = tail call noundef zeroext i1 @_ZNK3DIS12OneByteChunkeqERKS0_(ptr noundef nonnull align 8 dereferenceable(9) %8, ptr noundef nonnull align 8 dereferenceable(9) %9)
  %spec.select = select i1 %10, i1 %.078, i1 false
  %11 = add nuw i64 %.09, 1
  %12 = tail call noundef i64 @_ZNKSt6vectorIN3DIS12OneByteChunkESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %4) #3
  %13 = icmp ult i64 %11, %12
  br i1 %13, label %7, label %._crit_edge, !llvm.loop !5
}

declare noundef zeroext i1 @_ZNK3DIS14GridAxisRecordeqERKS0_(ptr noundef nonnull align 8 dereferenceable(12), ptr noundef nonnull align 8 dereferenceable(12)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK3DIS12OneByteChunkeqERKS0_(ptr noundef nonnull align 8 dereferenceable(9), ptr noundef nonnull align 8 dereferenceable(9)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass