; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu/tfslice.ll (Z17isSingleCStepMode10TensorDesc16TfSliceParamSpec)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.TfSliceParamSpec = type { [8 x i32], [8 x i32], [8 x i32], [8 x i8], [8 x i8], [8 x i8], [8 x i8], [8 x i8], i32 }

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_Z17isSingleCStepMode10TensorDesc16TfSliceParamSpec(ptr noundef byval(%struct.TensorDesc) align 8 %0, ptr noundef byval(%struct.TfSliceParamSpec) align 8 %1) #0 {
  %3 = alloca i1, align 1
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  call void @llvm.lifetime.start.p0(i64 4, ptr %4) #2
  %8 = getelementptr inbounds %struct.TensorDesc, ptr %0, i32 0, i32 2
  %9 = load i32, ptr %8, align 8, !tbaa !5
  store i32 %9, ptr %4, align 4, !tbaa !12
  %10 = load i32, ptr %4, align 4, !tbaa !12
  %11 = icmp slt i32 %10, 3
  br i1 %11, label %12, label %13

12:                                               ; preds = %2
  store i1 false, ptr %3, align 1
  store i32 1, ptr %5, align 4
  br label %65

13:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #2
  store i32 0, ptr %6, align 4, !tbaa !12
  br label %14

14:                                               ; preds = %59, %13
  %15 = load i32, ptr %6, align 4, !tbaa !12
  %16 = load i32, ptr %4, align 4, !tbaa !12
  %17 = icmp slt i32 %15, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %14
  store i32 2, ptr %5, align 4
  br label %62

19:                                               ; preds = %14
  call void @llvm.lifetime.start.p0(i64 4, ptr %7) #2
  %20 = load i32, ptr %4, align 4, !tbaa !12
  %21 = sub nsw i32 %20, 1
  %22 = load i32, ptr %6, align 4, !tbaa !12
  %23 = sub nsw i32 %21, %22
  store i32 %23, ptr %7, align 4, !tbaa !12
  %24 = load i32, ptr %6, align 4, !tbaa !12
  %25 = load i32, ptr %4, align 4, !tbaa !12
  %26 = sub nsw i32 %25, 2
  %27 = icmp ne i32 %24, %26
  br i1 %27, label %28, label %55

28:                                               ; preds = %19
  %29 = getelementptr inbounds %struct.TfSliceParamSpec, ptr %1, i32 0, i32 0
  %30 = load i32, ptr %7, align 4, !tbaa !12
  %31 = sext i32 %30 to i64
  %32 = getelementptr inbounds [8 x i32], ptr %29, i64 0, i64 %31
  %33 = load i32, ptr %32, align 4, !tbaa !12
  %34 = icmp ne i32 %33, 0
  br i1 %34, label %54, label %35

35:                                               ; preds = %28
  %36 = getelementptr inbounds %struct.TfSliceParamSpec, ptr %1, i32 0, i32 1
  %37 = load i32, ptr %7, align 4, !tbaa !12
  %38 = sext i32 %37 to i64
  %39 = getelementptr inbounds [8 x i32], ptr %36, i64 0, i64 %38
  %40 = load i32, ptr %39, align 4, !tbaa !12
  %41 = getelementptr inbounds %struct.TensorDesc, ptr %0, i32 0, i32 3
  %42 = load i32, ptr %6, align 4, !tbaa !12
  %43 = sext i32 %42 to i64
  %44 = getelementptr inbounds [20 x i32], ptr %41, i64 0, i64 %43
  %45 = load i32, ptr %44, align 4, !tbaa !12
  %46 = icmp ne i32 %40, %45
  br i1 %46, label %54, label %47

47:                                               ; preds = %35
  %48 = getelementptr inbounds %struct.TfSliceParamSpec, ptr %1, i32 0, i32 2
  %49 = load i32, ptr %7, align 4, !tbaa !12
  %50 = sext i32 %49 to i64
  %51 = getelementptr inbounds [8 x i32], ptr %48, i64 0, i64 %50
  %52 = load i32, ptr %51, align 4, !tbaa !12
  %53 = icmp ne i32 %52, 1
  br i1 %53, label %54, label %55

54:                                               ; preds = %47, %35, %28
  store i1 false, ptr %3, align 1
  store i32 1, ptr %5, align 4
  br label %56

55:                                               ; preds = %47, %19
  store i32 0, ptr %5, align 4
  br label %56

56:                                               ; preds = %55, %54
  call void @llvm.lifetime.end.p0(i64 4, ptr %7) #2
  %57 = load i32, ptr %5, align 4
  switch i32 %57, label %62 [
    i32 0, label %58
  ]

58:                                               ; preds = %56
  br label %59

59:                                               ; preds = %58
  %60 = load i32, ptr %6, align 4, !tbaa !12
  %61 = add nsw i32 %60, 1
  store i32 %61, ptr %6, align 4, !tbaa !12
  br label %14, !llvm.loop !13

62:                                               ; preds = %56, %18
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #2
  %63 = load i32, ptr %5, align 4
  switch i32 %63, label %65 [
    i32 2, label %64
  ]

64:                                               ; preds = %62
  store i1 true, ptr %3, align 1
  store i32 1, ptr %5, align 4
  br label %65

65:                                               ; preds = %64, %62, %12
  call void @llvm.lifetime.end.p0(i64 4, ptr %4) #2
  %66 = load i1, ptr %3, align 1
  ret i1 %66
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 8}
!6 = !{!"_ZTS10TensorDesc", !7, i64 0, !10, i64 4, !11, i64 8, !8, i64 12}
!7 = !{!"_ZTS8DataType", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS10DataFormat", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!11, !11, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.TfSliceParamSpec = type { [8 x i32], [8 x i32], [8 x i32], [8 x i8], [8 x i8], [8 x i8], [8 x i8], [8 x i8], i32 }

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable
define dso_local noundef zeroext i1 @_Z17isSingleCStepMode10TensorDesc16TfSliceParamSpec(ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %0, ptr nocapture noundef readonly byval(%struct.TfSliceParamSpec) align 8 %1) local_unnamed_addr #0 {
  %3 = getelementptr inbounds i8, ptr %0, i64 8
  %4 = load i32, ptr %3, align 8, !tbaa !5
  %5 = icmp slt i32 %4, 3
  br i1 %5, label %.loopexit, label %.preheader

.preheader:                                       ; preds = %2
  %6 = getelementptr inbounds i8, ptr %1, i64 32
  %7 = getelementptr inbounds i8, ptr %1, i64 64
  %8 = add nsw i32 %4, -2
  %9 = getelementptr inbounds i8, ptr %0, i64 12
  %10 = zext nneg i32 %4 to i64
  %11 = zext nneg i32 %8 to i64
  %wide.trip.count = zext nneg i32 %4 to i64
  br label %12

12:                                               ; preds = %.preheader, %.critedge
  %indvars.iv = phi i64 [ 0, %.preheader ], [ %indvars.iv.next, %.critedge ]
  %.not = icmp eq i64 %indvars.iv, %11
  br i1 %.not, label %.critedge, label %13

13:                                               ; preds = %12
  %14 = xor i64 %indvars.iv, -1
  %15 = add nsw i64 %10, %14
  %16 = getelementptr inbounds [8 x i32], ptr %1, i64 0, i64 %15
  %17 = load i32, ptr %16, align 4, !tbaa !12
  %.not19 = icmp eq i32 %17, 0
  br i1 %.not19, label %18, label %.loopexit

18:                                               ; preds = %13
  %19 = getelementptr inbounds [8 x i32], ptr %6, i64 0, i64 %15
  %20 = load i32, ptr %19, align 4, !tbaa !12
  %21 = getelementptr inbounds [20 x i32], ptr %9, i64 0, i64 %indvars.iv
  %22 = load i32, ptr %21, align 4, !tbaa !12
  %.not20 = icmp eq i32 %20, %22
  br i1 %.not20, label %23, label %.loopexit

23:                                               ; preds = %18
  %24 = getelementptr inbounds [8 x i32], ptr %7, i64 0, i64 %15
  %25 = load i32, ptr %24, align 4, !tbaa !12
  %.not21 = icmp eq i32 %25, 1
  br i1 %.not21, label %.critedge, label %.loopexit

.critedge:                                        ; preds = %23, %12
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
  br i1 %exitcond, label %.loopexit.loopexit.split.loop.exit29, label %12, !llvm.loop !13

.loopexit.loopexit.split.loop.exit29:             ; preds = %.critedge
  %.not22.le = icmp uge i64 %indvars.iv.next, %10
  br label %.loopexit

.loopexit:                                        ; preds = %23, %18, %13, %.loopexit.loopexit.split.loop.exit29, %2
  %.3 = phi i1 [ false, %2 ], [ %.not22.le, %.loopexit.loopexit.split.loop.exit29 ], [ false, %13 ], [ false, %18 ], [ false, %23 ]
  ret i1 %.3
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !11, i64 8}
!6 = !{!"_ZTS10TensorDesc", !7, i64 0, !10, i64 4, !11, i64 8, !8, i64 12}
!7 = !{!"_ZTS8DataType", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS10DataFormat", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!11, !11, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: ConstraintEliminationPass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass