; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/ocl (ocl_hardware_manager)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }
%"class.hipsycl::rt::ocl_hardware_manager" = type <{ %"class.hipsycl::rt::backend_hardware_manager", %"class.std::vector.6", %"class.std::vector.11", i32, [4 x i8] }>
%"class.hipsycl::rt::backend_hardware_manager" = type { ptr }
%"class.std::vector.6" = type { %"struct.std::_Vector_base.7" }
%"struct.std::_Vector_base.7" = type { %"struct.std::_Vector_base<hipsycl::rt::ocl_hardware_context, std::allocator<hipsycl::rt::ocl_hardware_context>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::ocl_hardware_context, std::allocator<hipsycl::rt::ocl_hardware_context>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::ocl_hardware_context, std::allocator<hipsycl::rt::ocl_hardware_context>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::ocl_hardware_context, std::allocator<hipsycl::rt::ocl_hardware_context>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.11" = type { %"struct.std::_Vector_base.12" }
%"struct.std::_Vector_base.12" = type { %"struct.std::_Vector_base<cl::Platform, std::allocator<cl::Platform>>::_Vector_impl" }
%"struct.std::_Vector_base<cl::Platform, std::allocator<cl::Platform>>::_Vector_impl" = type { %"struct.std::_Vector_base<cl::Platform, std::allocator<cl::Platform>>::_Vector_impl_data" }
%"struct.std::_Vector_base<cl::Platform, std::allocator<cl::Platform>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7hipsycl2rt18backend_descriptorC2ENS0_17hardware_platformENS0_12api_platformE(ptr noundef nonnull align 4 dereferenceable(12), i32 noundef, i32 noundef) unnamed_addr #0 align 2

declare void @_ZN7hipsycl2rt9device_idC1ENS0_18backend_descriptorEi(ptr noundef nonnull align 4 dereferenceable(16), i64, i32, i32 noundef) unnamed_addr #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: mustprogress uwtable
define dso_local { i64, i64 } @_ZNK7hipsycl2rt20ocl_hardware_manager13get_device_idEm(ptr noundef nonnull align 8 dereferenceable(60) %0, i64 noundef %1) unnamed_addr #3 align 2 {
  %3 = alloca %"class.hipsycl::rt::device_id", align 4
  %4 = alloca ptr, align 8
  %5 = alloca i64, align 8
  %6 = alloca %"struct.hipsycl::rt::backend_descriptor", align 4
  %7 = alloca { i64, i32 }, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i64 %1, ptr %5, align 8, !tbaa !9
  %8 = load ptr, ptr %4, align 8
  %9 = getelementptr inbounds %"class.hipsycl::rt::ocl_hardware_manager", ptr %8, i32 0, i32 3
  %10 = load i32, ptr %9, align 8, !tbaa !11
  call void @_ZN7hipsycl2rt18backend_descriptorC2ENS0_17hardware_platformENS0_12api_platformE(ptr noundef nonnull align 4 dereferenceable(12) %6, i32 noundef %10, i32 noundef 3)
  %11 = load i64, ptr %5, align 8, !tbaa !9
  %12 = trunc i64 %11 to i32
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %7, ptr align 4 %6, i64 12, i1 false)
  %13 = getelementptr inbounds { i64, i32 }, ptr %7, i32 0, i32 0
  %14 = load i64, ptr %13, align 4
  %15 = getelementptr inbounds { i64, i32 }, ptr %7, i32 0, i32 1
  %16 = load i32, ptr %15, align 4
  call void @_ZN7hipsycl2rt9device_idC1ENS0_18backend_descriptorEi(ptr noundef nonnull align 4 dereferenceable(16) %3, i64 %14, i32 %16, i32 noundef %12)
  %17 = load { i64, i64 }, ptr %3, align 4
  ret { i64, i64 } %17
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"long", !7, i64 0}
!11 = !{!12, !22, i64 56}
!12 = !{!"_ZTSN7hipsycl2rt20ocl_hardware_managerE", !13, i64 0, !14, i64 8, !18, i64 32, !22, i64 56}
!13 = !{!"_ZTSN7hipsycl2rt24backend_hardware_managerE"}
!14 = !{!"_ZTSSt6vectorIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!18 = !{!"_ZTSSt6vectorIN2cl8PlatformESaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN2cl8PlatformESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN2cl8PlatformESaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN2cl8PlatformESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSN7hipsycl2rt17hardware_platformE", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local void @_ZN7hipsycl2rt18backend_descriptorC2ENS0_17hardware_platformENS0_12api_platformE(ptr noundef nonnull align 4 dereferenceable(12), i32 noundef, i32 noundef) unnamed_addr #0 align 2

declare void @_ZN7hipsycl2rt9device_idC1ENS0_18backend_descriptorEi(ptr noundef nonnull align 4 dereferenceable(16), i64, i32, i32 noundef) unnamed_addr #1

; Function Attrs: mustprogress uwtable
define dso_local { i64, i64 } @_ZNK7hipsycl2rt20ocl_hardware_manager13get_device_idEm(ptr nocapture noundef nonnull readonly align 8 dereferenceable(60) %0, i64 noundef %1) unnamed_addr #2 align 2 {
  %3 = alloca %"class.hipsycl::rt::device_id", align 8
  %4 = alloca %"struct.hipsycl::rt::backend_descriptor", align 8
  %5 = getelementptr inbounds i8, ptr %0, i64 56
  %6 = load i32, ptr %5, align 8, !tbaa !5
  call void @_ZN7hipsycl2rt18backend_descriptorC2ENS0_17hardware_platformENS0_12api_platformE(ptr noundef nonnull align 4 dereferenceable(12) %4, i32 noundef %6, i32 noundef 3)
  %7 = trunc i64 %1 to i32
  %.sroa.0.0.copyload = load i64, ptr %4, align 8
  %.sroa.2.0..sroa_idx = getelementptr inbounds i8, ptr %4, i64 8
  %.sroa.2.0.copyload = load i32, ptr %.sroa.2.0..sroa_idx, align 8
  call void @_ZN7hipsycl2rt9device_idC1ENS0_18backend_descriptorEi(ptr noundef nonnull align 4 dereferenceable(16) %3, i64 %.sroa.0.0.copyload, i32 %.sroa.2.0.copyload, i32 noundef %7)
  %.fca.0.load = load i64, ptr %3, align 8
  %.fca.0.insert = insertvalue { i64, i64 } poison, i64 %.fca.0.load, 0
  %.fca.1.gep = getelementptr inbounds i8, ptr %3, i64 8
  %.fca.1.load = load i64, ptr %.fca.1.gep, align 8
  %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %.fca.1.load, 1
  ret { i64, i64 } %.fca.1.insert
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !19, i64 56}
!6 = !{!"_ZTSN7hipsycl2rt20ocl_hardware_managerE", !7, i64 0, !8, i64 8, !15, i64 32, !19, i64 56}
!7 = !{!"_ZTSN7hipsycl2rt24backend_hardware_managerE"}
!8 = !{!"_ZTSSt6vectorIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE", !9, i64 0}
!9 = !{!"_ZTSSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE", !10, i64 0}
!10 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE12_Vector_implE", !11, i64 0}
!11 = !{!"_ZTSNSt12_Vector_baseIN7hipsycl2rt20ocl_hardware_contextESaIS2_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!12 = !{!"any pointer", !13, i64 0}
!13 = !{!"omnipotent char", !14, i64 0}
!14 = !{!"Simple C++ TBAA"}
!15 = !{!"_ZTSSt6vectorIN2cl8PlatformESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSSt12_Vector_baseIN2cl8PlatformESaIS1_EE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN2cl8PlatformESaIS1_EE12_Vector_implE", !18, i64 0}
!18 = !{!"_ZTSNSt12_Vector_baseIN2cl8PlatformESaIS1_EE17_Vector_impl_dataE", !12, i64 0, !12, i64 8, !12, i64 16}
!19 = !{!"_ZTSN7hipsycl2rt17hardware_platformE", !13, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass