; LLVM IR from Samson-Mano/EM_Propogation_simulation :: EM_Propogation_simulation/src/ImGui (implot)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.ImPlotRange = type { double, double }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL5ImPowdd(double noundef, double noundef) #1

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #2

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52), double noundef, i1 noundef zeroext, i32 noundef, i1 noundef zeroext, ptr noundef, ptr noundef) #3 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6ImPlot19AddTicksLogarithmicERK11ImPlotRangeiiiR12ImPlotTickerPFidPciPvES6_(ptr noundef nonnull align 8 dereferenceable(16) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef nonnull align 8 dereferenceable(52) %4, ptr noundef %5, ptr noundef %6) #4 {
  %8 = alloca ptr, align 8
  %9 = alloca i32, align 4
  %10 = alloca i32, align 4
  %11 = alloca i32, align 4
  %12 = alloca ptr, align 8
  %13 = alloca ptr, align 8
  %14 = alloca ptr, align 8
  %15 = alloca double, align 8
  %16 = alloca i32, align 4
  %17 = alloca i32, align 4
  %18 = alloca double, align 8
  %19 = alloca double, align 8
  %20 = alloca double, align 8
  %21 = alloca i32, align 4
  %22 = alloca i32, align 4
  %23 = alloca double, align 8
  store ptr %0, ptr %8, align 8, !tbaa !5
  store i32 %1, ptr %9, align 4, !tbaa !9
  store i32 %2, ptr %10, align 4, !tbaa !9
  store i32 %3, ptr %11, align 4, !tbaa !9
  store ptr %4, ptr %12, align 8, !tbaa !5
  store ptr %5, ptr %13, align 8, !tbaa !5
  store ptr %6, ptr %14, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %15) #5
  %24 = load ptr, ptr %8, align 8, !tbaa !5
  %25 = getelementptr inbounds %struct.ImPlotRange, ptr %24, i32 0, i32 1
  %26 = load double, ptr %25, align 8, !tbaa !11
  %27 = call noundef double @_ZL6ImSignd(double noundef %26)
  store double %27, ptr %15, align 8, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 4, ptr %16) #5
  %28 = load i32, ptr %9, align 4, !tbaa !9
  %29 = load i32, ptr %11, align 4, !tbaa !9
  %30 = sub nsw i32 %28, %29
  store i32 %30, ptr %16, align 4, !tbaa !9
  br label %31

31:                                               ; preds = %143, %7
  %32 = load i32, ptr %16, align 4, !tbaa !9
  %33 = load i32, ptr %10, align 4, !tbaa !9
  %34 = load i32, ptr %11, align 4, !tbaa !9
  %35 = add nsw i32 %33, %34
  %36 = icmp slt i32 %32, %35
  br i1 %36, label %38, label %37

37:                                               ; preds = %31
  store i32 2, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %16) #5
  br label %147

38:                                               ; preds = %31
  call void @llvm.lifetime.start.p0(i64 8, ptr %18) #5
  %39 = load double, ptr %15, align 8, !tbaa !14
  %40 = load i32, ptr %16, align 4, !tbaa !9
  %41 = sitofp i32 %40 to double
  %42 = call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %41)
  %43 = fmul double %39, %42
  store double %43, ptr %18, align 8, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 8, ptr %19) #5
  %44 = load double, ptr %15, align 8, !tbaa !14
  %45 = load i32, ptr %16, align 4, !tbaa !9
  %46 = add nsw i32 %45, 1
  %47 = sitofp i32 %46 to double
  %48 = call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %47)
  %49 = fmul double %44, %48
  store double %49, ptr %19, align 8, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 8, ptr %20) #5
  %50 = load double, ptr %19, align 8, !tbaa !14
  %51 = load double, ptr %18, align 8, !tbaa !14
  %52 = fsub double %50, %51
  %53 = fdiv double %52, 9.000000e+00
  store double %53, ptr %20, align 8, !tbaa !14
  %54 = load double, ptr %18, align 8, !tbaa !14
  %55 = load ptr, ptr %8, align 8, !tbaa !5
  %56 = getelementptr inbounds %struct.ImPlotRange, ptr %55, i32 0, i32 0
  %57 = load double, ptr %56, align 8, !tbaa !15
  %58 = fsub double %57, 0x3CB0000000000000
  %59 = fcmp oge double %54, %58
  br i1 %59, label %60, label %73

60:                                               ; preds = %38
  %61 = load double, ptr %18, align 8, !tbaa !14
  %62 = load ptr, ptr %8, align 8, !tbaa !5
  %63 = getelementptr inbounds %struct.ImPlotRange, ptr %62, i32 0, i32 1
  %64 = load double, ptr %63, align 8, !tbaa !11
  %65 = fadd double %64, 0x3CB0000000000000
  %66 = fcmp ole double %61, %65
  br i1 %66, label %67, label %73

67:                                               ; preds = %60
  %68 = load ptr, ptr %12, align 8, !tbaa !5
  %69 = load double, ptr %18, align 8, !tbaa !14
  %70 = load ptr, ptr %13, align 8, !tbaa !5
  %71 = load ptr, ptr %14, align 8, !tbaa !5
  %72 = call noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52) %68, double noundef %69, i1 noundef zeroext true, i32 noundef 0, i1 noundef zeroext true, ptr noundef %70, ptr noundef %71)
  br label %73

73:                                               ; preds = %67, %60, %38
  call void @llvm.lifetime.start.p0(i64 4, ptr %21) #5
  store i32 0, ptr %21, align 4, !tbaa !9
  br label %74

74:                                               ; preds = %139, %73
  %75 = load i32, ptr %21, align 4, !tbaa !9
  %76 = load i32, ptr %11, align 4, !tbaa !9
  %77 = icmp slt i32 %75, %76
  br i1 %77, label %79, label %78

78:                                               ; preds = %74
  store i32 5, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %21) #5
  br label %142

79:                                               ; preds = %74
  %80 = load double, ptr %15, align 8, !tbaa !14
  %81 = load i32, ptr %16, align 4, !tbaa !9
  %82 = load i32, ptr %21, align 4, !tbaa !9
  %83 = add nsw i32 %81, %82
  %84 = sitofp i32 %83 to double
  %85 = call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %84)
  %86 = fmul double %80, %85
  store double %86, ptr %18, align 8, !tbaa !14
  %87 = load double, ptr %15, align 8, !tbaa !14
  %88 = load i32, ptr %16, align 4, !tbaa !9
  %89 = load i32, ptr %21, align 4, !tbaa !9
  %90 = add nsw i32 %88, %89
  %91 = add nsw i32 %90, 1
  %92 = sitofp i32 %91 to double
  %93 = call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %92)
  %94 = fmul double %87, %93
  store double %94, ptr %19, align 8, !tbaa !14
  %95 = load double, ptr %19, align 8, !tbaa !14
  %96 = load double, ptr %18, align 8, !tbaa !14
  %97 = fsub double %95, %96
  %98 = fdiv double %97, 9.000000e+00
  store double %98, ptr %20, align 8, !tbaa !14
  call void @llvm.lifetime.start.p0(i64 4, ptr %22) #5
  store i32 1, ptr %22, align 4, !tbaa !9
  br label %99

99:                                               ; preds = %135, %79
  %100 = load i32, ptr %22, align 4, !tbaa !9
  %101 = load i32, ptr %21, align 4, !tbaa !9
  %102 = load i32, ptr %11, align 4, !tbaa !9
  %103 = sub nsw i32 %102, 1
  %104 = icmp slt i32 %101, %103
  %105 = zext i1 %104 to i32
  %106 = add nsw i32 9, %105
  %107 = icmp slt i32 %100, %106
  br i1 %107, label %109, label %108

108:                                              ; preds = %99
  store i32 8, ptr %17, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %22) #5
  br label %138

109:                                              ; preds = %99
  call void @llvm.lifetime.start.p0(i64 8, ptr %23) #5
  %110 = load double, ptr %18, align 8, !tbaa !14
  %111 = load i32, ptr %22, align 4, !tbaa !9
  %112 = sitofp i32 %111 to double
  %113 = load double, ptr %20, align 8, !tbaa !14
  %114 = call double @llvm.fmuladd.f64(double %112, double %113, double %110)
  store double %114, ptr %23, align 8, !tbaa !14
  %115 = load double, ptr %23, align 8, !tbaa !14
  %116 = load ptr, ptr %8, align 8, !tbaa !5
  %117 = getelementptr inbounds %struct.ImPlotRange, ptr %116, i32 0, i32 0
  %118 = load double, ptr %117, align 8, !tbaa !15
  %119 = fsub double %118, 0x3CB0000000000000
  %120 = fcmp oge double %115, %119
  br i1 %120, label %121, label %134

121:                                              ; preds = %109
  %122 = load double, ptr %23, align 8, !tbaa !14
  %123 = load ptr, ptr %8, align 8, !tbaa !5
  %124 = getelementptr inbounds %struct.ImPlotRange, ptr %123, i32 0, i32 1
  %125 = load double, ptr %124, align 8, !tbaa !11
  %126 = fadd double %125, 0x3CB0000000000000
  %127 = fcmp ole double %122, %126
  br i1 %127, label %128, label %134

128:                                              ; preds = %121
  %129 = load ptr, ptr %12, align 8, !tbaa !5
  %130 = load double, ptr %23, align 8, !tbaa !14
  %131 = load ptr, ptr %13, align 8, !tbaa !5
  %132 = load ptr, ptr %14, align 8, !tbaa !5
  %133 = call noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52) %129, double noundef %130, i1 noundef zeroext false, i32 noundef 0, i1 noundef zeroext false, ptr noundef %131, ptr noundef %132)
  br label %134

134:                                              ; preds = %128, %121, %109
  call void @llvm.lifetime.end.p0(i64 8, ptr %23) #5
  br label %135

135:                                              ; preds = %134
  %136 = load i32, ptr %22, align 4, !tbaa !9
  %137 = add nsw i32 %136, 1
  store i32 %137, ptr %22, align 4, !tbaa !9
  br label %99, !llvm.loop !16

138:                                              ; preds = %108
  br label %139

139:                                              ; preds = %138
  %140 = load i32, ptr %21, align 4, !tbaa !9
  %141 = add nsw i32 %140, 1
  store i32 %141, ptr %21, align 4, !tbaa !9
  br label %74, !llvm.loop !18

142:                                              ; preds = %78
  call void @llvm.lifetime.end.p0(i64 8, ptr %20) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %19) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %18) #5
  br label %143

143:                                              ; preds = %142
  %144 = load i32, ptr %11, align 4, !tbaa !9
  %145 = load i32, ptr %16, align 4, !tbaa !9
  %146 = add nsw i32 %145, %144
  store i32 %146, ptr %16, align 4, !tbaa !9
  br label %31, !llvm.loop !19

147:                                              ; preds = %37
  call void @llvm.lifetime.end.p0(i64 8, ptr %15) #5
  ret void
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL6ImSignd(double noundef) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !13, i64 8}
!12 = !{!"_ZTS11ImPlotRange", !13, i64 0, !13, i64 8}
!13 = !{!"double", !7, i64 0}
!14 = !{!13, !13, i64 0}
!15 = !{!12, !13, i64 0}
!16 = distinct !{!16, !17}
!17 = !{!"llvm.loop.mustprogress"}
!18 = distinct !{!18, !17}
!19 = distinct !{!19, !17}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL5ImPowdd(double noundef, double noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1

; Function Attrs: mustprogress uwtable
declare dso_local noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52), double noundef, i1 noundef zeroext, i32 noundef, i1 noundef zeroext, ptr noundef, ptr noundef) local_unnamed_addr #2 align 2

; Function Attrs: mustprogress uwtable
define dso_local void @_ZN6ImPlot19AddTicksLogarithmicERK11ImPlotRangeiiiR12ImPlotTickerPFidPciPvES6_(ptr nocapture noundef nonnull readonly align 8 dereferenceable(16) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, ptr noundef nonnull align 8 dereferenceable(52) %4, ptr noundef %5, ptr noundef %6) local_unnamed_addr #3 {
  %8 = getelementptr inbounds i8, ptr %0, i64 8
  %9 = load double, ptr %8, align 8, !tbaa !5
  %10 = tail call noundef double @_ZL6ImSignd(double noundef %9)
  %11 = sub nsw i32 %1, %3
  %12 = add nsw i32 %3, %2
  %13 = icmp slt i32 %11, %12
  br i1 %13, label %.lr.ph56, label %._crit_edge57

.lr.ph56:                                         ; preds = %7
  %14 = icmp sgt i32 %3, 0
  %15 = add nsw i32 %3, -1
  br i1 %14, label %.lr.ph56.split.us, label %.lr.ph56.split

.lr.ph56.split.us:                                ; preds = %.lr.ph56, %._crit_edge.us
  %.054.us = phi i32 [ %59, %._crit_edge.us ], [ %11, %.lr.ph56 ]
  %16 = sitofp i32 %.054.us to double
  %17 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %16)
  %18 = fmul double %10, %17
  %19 = add nsw i32 %.054.us, 1
  %20 = sitofp i32 %19 to double
  %21 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %20)
  %22 = load double, ptr %0, align 8, !tbaa !10
  %23 = fadd double %22, 0xBCB0000000000000
  %24 = fcmp ult double %18, %23
  br i1 %24, label %.lr.ph.us.preheader, label %25

25:                                               ; preds = %.lr.ph56.split.us
  %26 = load double, ptr %8, align 8, !tbaa !5
  %27 = fadd double %26, 0x3CB0000000000000
  %28 = fcmp ugt double %18, %27
  br i1 %28, label %.lr.ph.us.preheader, label %29

29:                                               ; preds = %25
  %30 = tail call noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52) %4, double noundef %18, i1 noundef zeroext true, i32 noundef 0, i1 noundef zeroext true, ptr noundef %5, ptr noundef %6)
  br label %.lr.ph.us.preheader

.lr.ph.us.preheader:                              ; preds = %29, %25, %.lr.ph56.split.us
  br label %.lr.ph.us

.lr.ph.us:                                        ; preds = %.lr.ph.us.preheader, %43
  %.04853.us = phi i32 [ %44, %43 ], [ 0, %.lr.ph.us.preheader ]
  %31 = add nsw i32 %.04853.us, %.054.us
  %32 = sitofp i32 %31 to double
  %33 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %32)
  %34 = fmul double %10, %33
  %35 = add nsw i32 %31, 1
  %36 = sitofp i32 %35 to double
  %37 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %36)
  %38 = fmul double %10, %37
  %39 = fsub double %38, %34
  %40 = fdiv double %39, 9.000000e+00
  %41 = icmp slt i32 %.04853.us, %15
  %42 = select i1 %41, i32 10, i32 9
  br label %45

43:                                               ; preds = %57
  %44 = add nuw nsw i32 %.04853.us, 1
  %exitcond59.not = icmp eq i32 %44, %3
  br i1 %exitcond59.not, label %._crit_edge.us, label %.lr.ph.us, !llvm.loop !11

45:                                               ; preds = %57, %.lr.ph.us
  %.04752.us = phi i32 [ 1, %.lr.ph.us ], [ %58, %57 ]
  %46 = uitofp nneg i32 %.04752.us to double
  %47 = tail call double @llvm.fmuladd.f64(double %46, double %40, double %34)
  %48 = load double, ptr %0, align 8, !tbaa !10
  %49 = fadd double %48, 0xBCB0000000000000
  %50 = fcmp ult double %47, %49
  br i1 %50, label %57, label %51

51:                                               ; preds = %45
  %52 = load double, ptr %8, align 8, !tbaa !5
  %53 = fadd double %52, 0x3CB0000000000000
  %54 = fcmp ugt double %47, %53
  br i1 %54, label %57, label %55

55:                                               ; preds = %51
  %56 = tail call noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52) %4, double noundef %47, i1 noundef zeroext false, i32 noundef 0, i1 noundef zeroext false, ptr noundef %5, ptr noundef %6)
  br label %57

57:                                               ; preds = %55, %51, %45
  %58 = add nuw nsw i32 %.04752.us, 1
  %exitcond.not = icmp eq i32 %58, %42
  br i1 %exitcond.not, label %43, label %45, !llvm.loop !13

._crit_edge.us:                                   ; preds = %43
  %59 = add nsw i32 %.054.us, %3
  %60 = icmp slt i32 %.054.us, %2
  br i1 %60, label %.lr.ph56.split.us, label %._crit_edge57, !llvm.loop !14

._crit_edge57:                                    ; preds = %76, %._crit_edge.us, %7
  ret void

.lr.ph56.split:                                   ; preds = %.lr.ph56, %76
  %.054 = phi i32 [ %77, %76 ], [ %11, %.lr.ph56 ]
  %61 = sitofp i32 %.054 to double
  %62 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %61)
  %63 = fmul double %10, %62
  %64 = add nsw i32 %.054, 1
  %65 = sitofp i32 %64 to double
  %66 = tail call noundef double @_ZL5ImPowdd(double noundef 1.000000e+01, double noundef %65)
  %67 = load double, ptr %0, align 8, !tbaa !10
  %68 = fadd double %67, 0xBCB0000000000000
  %69 = fcmp ult double %63, %68
  br i1 %69, label %76, label %70

70:                                               ; preds = %.lr.ph56.split
  %71 = load double, ptr %8, align 8, !tbaa !5
  %72 = fadd double %71, 0x3CB0000000000000
  %73 = fcmp ugt double %63, %72
  br i1 %73, label %76, label %74

74:                                               ; preds = %70
  %75 = tail call noundef nonnull align 8 dereferenceable(36) ptr @_ZN12ImPlotTicker7AddTickEdbibPFidPciPvES1_(ptr noundef nonnull align 8 dereferenceable(52) %4, double noundef %63, i1 noundef zeroext true, i32 noundef 0, i1 noundef zeroext true, ptr noundef %5, ptr noundef %6)
  br label %76

76:                                               ; preds = %74, %70, %.lr.ph56.split
  %77 = add nsw i32 %.054, %3
  %78 = icmp slt i32 %.054, %2
  br i1 %78, label %.lr.ph56.split, label %._crit_edge57, !llvm.loop !14
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare hidden noundef double @_ZL6ImSignd(double noundef) local_unnamed_addr #0

attributes #0 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 8}
!6 = !{!"_ZTS11ImPlotRange", !7, i64 0, !7, i64 8}
!7 = !{!"double", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!6, !7, i64 0}
!11 = distinct !{!11, !12}
!12 = !{!"llvm.loop.mustprogress"}
!13 = distinct !{!13, !12}
!14 = distinct !{!14, !12}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,JumpThreadingPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass