; LLVM IR from upupming/algorithm :: AdvancedLevel_C++/1119. Pre- and Post-order Traversals (30) .ll (Z5getIniiii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@in = external dso_local global %"class.std::vector", align 8
@pre = external dso_local global %"class.std::vector", align 8
@post = external dso_local global %"class.std::vector", align 8
@unique = external dso_local global i8, align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5getIniiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #0 {
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  store i32 %0, ptr %5, align 4, !tbaa !5
  store i32 %1, ptr %6, align 4, !tbaa !5
  store i32 %2, ptr %7, align 4, !tbaa !5
  store i32 %3, ptr %8, align 4, !tbaa !5
  %10 = load i32, ptr %5, align 4, !tbaa !5
  %11 = load i32, ptr %6, align 4, !tbaa !5
  %12 = icmp eq i32 %10, %11
  br i1 %12, label %13, label %17

13:                                               ; preds = %4
  %14 = load i32, ptr %5, align 4, !tbaa !5
  %15 = sext i32 %14 to i64
  %16 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %15) #3
  call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @in, ptr noundef nonnull align 4 dereferenceable(4) %16)
  br label %83

17:                                               ; preds = %4
  %18 = load i32, ptr %5, align 4, !tbaa !5
  %19 = sext i32 %18 to i64
  %20 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %19) #3
  %21 = load i32, ptr %20, align 4, !tbaa !5
  %22 = load i32, ptr %8, align 4, !tbaa !5
  %23 = sext i32 %22 to i64
  %24 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %23) #3
  %25 = load i32, ptr %24, align 4, !tbaa !5
  %26 = icmp eq i32 %21, %25
  br i1 %26, label %27, label %83

27:                                               ; preds = %17
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #3
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = add nsw i32 %28, 1
  store i32 %29, ptr %9, align 4, !tbaa !5
  br label %30

30:                                               ; preds = %47, %27
  %31 = load i32, ptr %9, align 4, !tbaa !5
  %32 = load i32, ptr %6, align 4, !tbaa !5
  %33 = icmp sle i32 %31, %32
  br i1 %33, label %34, label %45

34:                                               ; preds = %30
  %35 = load i32, ptr %9, align 4, !tbaa !5
  %36 = sext i32 %35 to i64
  %37 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %36) #3
  %38 = load i32, ptr %37, align 4, !tbaa !5
  %39 = load i32, ptr %8, align 4, !tbaa !5
  %40 = sub nsw i32 %39, 1
  %41 = sext i32 %40 to i64
  %42 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %41) #3
  %43 = load i32, ptr %42, align 4, !tbaa !5
  %44 = icmp ne i32 %38, %43
  br label %45

45:                                               ; preds = %34, %30
  %46 = phi i1 [ false, %30 ], [ %44, %34 ]
  br i1 %46, label %47, label %50

47:                                               ; preds = %45
  %48 = load i32, ptr %9, align 4, !tbaa !5
  %49 = add nsw i32 %48, 1
  store i32 %49, ptr %9, align 4, !tbaa !5
  br label %30, !llvm.loop !9

50:                                               ; preds = %45
  %51 = load i32, ptr %9, align 4, !tbaa !5
  %52 = load i32, ptr %5, align 4, !tbaa !5
  %53 = sub nsw i32 %51, %52
  %54 = icmp sgt i32 %53, 1
  br i1 %54, label %55, label %68

55:                                               ; preds = %50
  %56 = load i32, ptr %5, align 4, !tbaa !5
  %57 = add nsw i32 %56, 1
  %58 = load i32, ptr %9, align 4, !tbaa !5
  %59 = sub nsw i32 %58, 1
  %60 = load i32, ptr %7, align 4, !tbaa !5
  %61 = load i32, ptr %7, align 4, !tbaa !5
  %62 = load i32, ptr %9, align 4, !tbaa !5
  %63 = load i32, ptr %5, align 4, !tbaa !5
  %64 = sub nsw i32 %62, %63
  %65 = sub nsw i32 %64, 1
  %66 = add nsw i32 %61, %65
  %67 = sub nsw i32 %66, 1
  call void @_Z5getIniiii(i32 noundef %57, i32 noundef %59, i32 noundef %60, i32 noundef %67)
  br label %69

68:                                               ; preds = %50
  store i8 0, ptr @unique, align 1, !tbaa !11
  br label %69

69:                                               ; preds = %68, %55
  %70 = load i32, ptr %8, align 4, !tbaa !5
  %71 = sext i32 %70 to i64
  %72 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %71) #3
  call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @in, ptr noundef nonnull align 4 dereferenceable(4) %72)
  %73 = load i32, ptr %9, align 4, !tbaa !5
  %74 = load i32, ptr %6, align 4, !tbaa !5
  %75 = load i32, ptr %7, align 4, !tbaa !5
  %76 = load i32, ptr %9, align 4, !tbaa !5
  %77 = load i32, ptr %5, align 4, !tbaa !5
  %78 = sub nsw i32 %76, %77
  %79 = sub nsw i32 %78, 1
  %80 = add nsw i32 %75, %79
  %81 = load i32, ptr %8, align 4, !tbaa !5
  %82 = sub nsw i32 %81, 1
  call void @_Z5getIniiii(i32 noundef %73, i32 noundef %74, i32 noundef %80, i32 noundef %82)
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #3
  br label %83

83:                                               ; preds = %69, %17, %13
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@in = external dso_local global %"class.std::vector", align 8
@pre = external dso_local global %"class.std::vector", align 8
@post = external dso_local global %"class.std::vector", align 8
@unique = external dso_local local_unnamed_addr global i8, align 1

; Function Attrs: mustprogress uwtable
define dso_local void @_Z5getIniiii(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 {
  %5 = icmp eq i32 %0, %1
  br i1 %5, label %tailrecurse._crit_edge, label %.lr.ph41.preheader

.lr.ph41.preheader:                               ; preds = %4
  %6 = sext i32 %1 to i64
  %7 = add i32 %1, 1
  %8 = sext i32 %3 to i64
  br label %.lr.ph41

tailrecurse._crit_edge:                           ; preds = %tailrecurse, %4
  %.tr.lcssa = phi i32 [ %0, %4 ], [ %1, %tailrecurse ]
  %9 = sext i32 %.tr.lcssa to i64
  %10 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %9) #2
  tail call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @in, ptr noundef nonnull align 4 dereferenceable(4) %10)
  br label %.loopexit

.lr.ph41:                                         ; preds = %.lr.ph41.preheader, %tailrecurse
  %indvars.iv44 = phi i64 [ %8, %.lr.ph41.preheader ], [ %indvars.iv.next45, %tailrecurse ]
  %.tr3139 = phi i32 [ %2, %.lr.ph41.preheader ], [ %36, %tailrecurse ]
  %.tr38 = phi i32 [ %0, %.lr.ph41.preheader ], [ %.0.lcssa, %tailrecurse ]
  %11 = sext i32 %.tr38 to i64
  %12 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %11) #2
  %13 = load i32, ptr %12, align 4, !tbaa !5
  %14 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %indvars.iv44) #2
  %15 = load i32, ptr %14, align 4, !tbaa !5
  %16 = icmp eq i32 %13, %15
  br i1 %16, label %17, label %.loopexit

17:                                               ; preds = %.lr.ph41
  %18 = add nsw i32 %.tr38, 1
  %.not34.not = icmp slt i32 %.tr38, %1
  br i1 %.not34.not, label %.lr.ph, label %.critedge

.lr.ph:                                           ; preds = %17
  %19 = add nsw i64 %indvars.iv44, -1
  br label %20

20:                                               ; preds = %.lr.ph, %25
  %indvars.iv.in = phi i64 [ %11, %.lr.ph ], [ %indvars.iv, %25 ]
  %indvars.iv = add nsw i64 %indvars.iv.in, 1
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %indvars.iv) #2
  %22 = load i32, ptr %21, align 4, !tbaa !5
  %23 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %19) #2
  %24 = load i32, ptr %23, align 4, !tbaa !5
  %.not29 = icmp eq i32 %22, %24
  br i1 %.not29, label %.critedge.loopexit.split.loop.exit47, label %25

25:                                               ; preds = %20
  %exitcond.not = icmp eq i64 %indvars.iv, %6
  br i1 %exitcond.not, label %.critedge, label %20, !llvm.loop !9

.critedge.loopexit.split.loop.exit47:             ; preds = %20
  %26 = trunc nsw i64 %indvars.iv to i32
  br label %.critedge

.critedge:                                        ; preds = %25, %.critedge.loopexit.split.loop.exit47, %17
  %.0.lcssa = phi i32 [ %18, %17 ], [ %26, %.critedge.loopexit.split.loop.exit47 ], [ %7, %25 ]
  %27 = sub nsw i32 %.0.lcssa, %.tr38
  %28 = icmp sgt i32 %27, 1
  br i1 %28, label %29, label %33

29:                                               ; preds = %.critedge
  %30 = add nsw i32 %.0.lcssa, -1
  %31 = add i32 %.tr3139, -2
  %32 = add i32 %31, %27
  tail call void @_Z5getIniiii(i32 noundef %18, i32 noundef %30, i32 noundef %.tr3139, i32 noundef %32)
  br label %tailrecurse

33:                                               ; preds = %.critedge
  store i8 0, ptr @unique, align 1, !tbaa !11
  br label %tailrecurse

tailrecurse:                                      ; preds = %33, %29
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @post, i64 noundef %indvars.iv44) #2
  tail call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @in, ptr noundef nonnull align 4 dereferenceable(4) %34)
  %35 = add i32 %.tr3139, -1
  %36 = add i32 %35, %27
  %indvars.iv.next45 = add nsw i64 %indvars.iv44, -1
  %37 = icmp eq i32 %.0.lcssa, %1
  br i1 %37, label %tailrecurse._crit_edge, label %.lr.ph41

.loopexit:                                        ; preds = %.lr.ph41, %tailrecurse._crit_edge
  ret void
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = distinct !{!9, !10}
!10 = !{!"llvm.loop.mustprogress"}
!11 = !{!12, !12, i64 0}
!12 = !{!"bool", !7, i64 0}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass