; LLVM IR from daanx/mimalloc-bench :: bench/cache-thrash (cache-thrash)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%class.workerArg = type { i32, i32, i32 }

; Function Attrs: mustprogress uwtable
define dso_local ptr @worker(ptr noundef %0) #0 {
  %2 = alloca ptr, align 8
  %3 = alloca ptr, align 8
  %4 = alloca %class.workerArg, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca ptr, align 8
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca i8, align 1
  store ptr %0, ptr %2, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %3) #5
  %11 = load ptr, ptr %2, align 8, !tbaa !5
  store ptr %11, ptr %3, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 12, ptr %4) #5
  %12 = load ptr, ptr %3, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %4, ptr align 4 %12, i64 12, i1 false), !tbaa.struct !9
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #5
  store i32 0, ptr %5, align 4, !tbaa !10
  br label %13

13:                                               ; preds = %63, %1
  %14 = load i32, ptr %5, align 4, !tbaa !10
  %15 = getelementptr inbounds %class.workerArg, ptr %4, i32 0, i32 1
  %16 = load i32, ptr %15, align 4, !tbaa !12
  %17 = icmp slt i32 %14, %16
  br i1 %17, label %19, label %18

18:                                               ; preds = %13
  store i32 2, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #5
  br label %66

19:                                               ; preds = %13
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #5
  %20 = getelementptr inbounds %class.workerArg, ptr %4, i32 0, i32 0
  %21 = load i32, ptr %20, align 4, !tbaa !14
  %22 = sext i32 %21 to i64
  %23 = call noalias noundef nonnull ptr @_Znam(i64 noundef %22) #6
  store ptr %23, ptr %7, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %8) #5
  store i32 0, ptr %8, align 4, !tbaa !10
  br label %24

24:                                               ; preds = %55, %19
  %25 = load i32, ptr %8, align 4, !tbaa !10
  %26 = getelementptr inbounds %class.workerArg, ptr %4, i32 0, i32 2
  %27 = load i32, ptr %26, align 4, !tbaa !15
  %28 = icmp slt i32 %25, %27
  br i1 %28, label %30, label %29

29:                                               ; preds = %24
  store i32 5, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %8) #5
  br label %58

30:                                               ; preds = %24
  call void @llvm.lifetime.start.p0(i64 4, ptr %9) #5
  store i32 0, ptr %9, align 4, !tbaa !10
  br label %31

31:                                               ; preds = %51, %30
  %32 = load i32, ptr %9, align 4, !tbaa !10
  %33 = getelementptr inbounds %class.workerArg, ptr %4, i32 0, i32 0
  %34 = load i32, ptr %33, align 4, !tbaa !14
  %35 = icmp slt i32 %32, %34
  br i1 %35, label %37, label %36

36:                                               ; preds = %31
  store i32 8, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %9) #5
  br label %54

37:                                               ; preds = %31
  %38 = load i32, ptr %9, align 4, !tbaa !10
  %39 = trunc i32 %38 to i8
  %40 = load ptr, ptr %7, align 8, !tbaa !5
  %41 = load i32, ptr %9, align 4, !tbaa !10
  %42 = sext i32 %41 to i64
  %43 = getelementptr inbounds i8, ptr %40, i64 %42
  store i8 %39, ptr %43, align 1, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 1, ptr %10) #5
  %44 = load ptr, ptr %7, align 8, !tbaa !5
  %45 = load i32, ptr %9, align 4, !tbaa !10
  %46 = sext i32 %45 to i64
  %47 = getelementptr inbounds i8, ptr %44, i64 %46
  %48 = load i8, ptr %47, align 1, !tbaa !16
  store volatile i8 %48, ptr %10, align 1, !tbaa !16
  %49 = load volatile i8, ptr %10, align 1, !tbaa !16
  %50 = add i8 %49, 1
  store volatile i8 %50, ptr %10, align 1, !tbaa !16
  call void @llvm.lifetime.end.p0(i64 1, ptr %10) #5
  br label %51

51:                                               ; preds = %37
  %52 = load i32, ptr %9, align 4, !tbaa !10
  %53 = add nsw i32 %52, 1
  store i32 %53, ptr %9, align 4, !tbaa !10
  br label %31, !llvm.loop !17

54:                                               ; preds = %36
  br label %55

55:                                               ; preds = %54
  %56 = load i32, ptr %8, align 4, !tbaa !10
  %57 = add nsw i32 %56, 1
  store i32 %57, ptr %8, align 4, !tbaa !10
  br label %24, !llvm.loop !19

58:                                               ; preds = %29
  %59 = load ptr, ptr %7, align 8, !tbaa !5
  %60 = icmp eq ptr %59, null
  br i1 %60, label %62, label %61

61:                                               ; preds = %58
  call void @_ZdaPv(ptr noundef %59) #7
  br label %62

62:                                               ; preds = %61, %58
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #5
  br label %63

63:                                               ; preds = %62
  %64 = load i32, ptr %5, align 4, !tbaa !10
  %65 = add nsw i32 %64, 1
  store i32 %65, ptr %5, align 4, !tbaa !10
  br label %13, !llvm.loop !20

66:                                               ; preds = %18
  store i32 1, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 12, ptr %4) #5
  call void @llvm.lifetime.end.p0(i64 8, ptr %3) #5
  ret ptr null
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nobuiltin allocsize(0)
declare noundef nonnull ptr @_Znam(i64 noundef) #3

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nobuiltin nounwind
declare void @_ZdaPv(ptr noundef) #4

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nobuiltin allocsize(0) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { builtin allocsize(0) }
attributes #7 = { builtin nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i64 0, i64 4, !10, i64 4, i64 4, !10, i64 8, i64 4, !10}
!10 = !{!11, !11, i64 0}
!11 = !{!"int", !7, i64 0}
!12 = !{!13, !11, i64 4}
!13 = !{!"_ZTS9workerArg", !11, i64 0, !11, i64 4, !11, i64 8}
!14 = !{!13, !11, i64 0}
!15 = !{!13, !11, i64 8}
!16 = !{!7, !7, i64 0}
!17 = distinct !{!17, !18}
!18 = !{!"llvm.loop.mustprogress"}
!19 = distinct !{!19, !18}
!20 = distinct !{!20, !18}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nounwind memory(argmem: read, inaccessiblemem: readwrite) uwtable
define dso_local noalias noundef ptr @worker(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
  %2 = alloca i8, align 1
  %.sroa.0.0.copyload = load i32, ptr %0, align 4, !tbaa !5
  %3 = freeze i32 %.sroa.0.0.copyload
  %.sroa.5.0..sroa_idx = getelementptr inbounds i8, ptr %0, i64 4
  %.sroa.5.0.copyload = load i32, ptr %.sroa.5.0..sroa_idx, align 4, !tbaa !5
  %.sroa.6.0..sroa_idx = getelementptr inbounds i8, ptr %0, i64 8
  %.sroa.6.0.copyload = load i32, ptr %.sroa.6.0..sroa_idx, align 4, !tbaa !5
  %4 = icmp sgt i32 %.sroa.5.0.copyload, 0
  %5 = icmp sgt i32 %.sroa.6.0.copyload, 0
  %or.cond = select i1 %4, i1 %5, i1 false
  %6 = icmp sgt i32 %3, 0
  %or.cond30 = select i1 %or.cond, i1 %6, i1 false
  br i1 %or.cond30, label %.preheader17.us.us.preheader, label %._crit_edge

.preheader17.us.us.preheader:                     ; preds = %1
  %xtraiter = and i32 %3, 3
  %7 = icmp ult i32 %3, 4
  %unroll_iter = and i32 %3, -4
  %lcmp.mod.not = icmp eq i32 %xtraiter, 0
  br label %.preheader17.us.us

.preheader17.us.us:                               ; preds = %.preheader17.us.us.preheader, %._crit_edge20.split.us.us.us
  %.01621.us.us = phi i32 [ %24, %._crit_edge20.split.us.us.us ], [ 0, %.preheader17.us.us.preheader ]
  br label %.preheader.us.us.us

.preheader.us.us.us:                              ; preds = %._crit_edge.us.us.us, %.preheader17.us.us
  %.01519.us.us.us = phi i32 [ 0, %.preheader17.us.us ], [ %23, %._crit_edge.us.us.us ]
  br i1 %7, label %._crit_edge.us.us.us.unr-lcssa, label %.preheader.us.us.us.new

.preheader.us.us.us.new:                          ; preds = %.preheader.us.us.us, %.preheader.us.us.us.new
  %.018.us.us.us = phi i32 [ %19, %.preheader.us.us.us.new ], [ 0, %.preheader.us.us.us ]
  %niter = phi i32 [ %niter.next.3, %.preheader.us.us.us.new ], [ 0, %.preheader.us.us.us ]
  %8 = trunc i32 %.018.us.us.us to i8
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
  store volatile i8 %8, ptr %2, align 1, !tbaa !9
  %.0..0..0..0..us.us.us = load volatile i8, ptr %2, align 1, !tbaa !9
  %9 = add i8 %.0..0..0..0..us.us.us, 1
  store volatile i8 %9, ptr %2, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
  %10 = trunc i32 %.018.us.us.us to i8
  %11 = or disjoint i8 %10, 1
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
  store volatile i8 %11, ptr %2, align 1, !tbaa !9
  %.0..0..0..0..us.us.us.1 = load volatile i8, ptr %2, align 1, !tbaa !9
  %12 = add i8 %.0..0..0..0..us.us.us.1, 1
  store volatile i8 %12, ptr %2, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
  %13 = trunc i32 %.018.us.us.us to i8
  %14 = or disjoint i8 %13, 2
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
  store volatile i8 %14, ptr %2, align 1, !tbaa !9
  %.0..0..0..0..us.us.us.2 = load volatile i8, ptr %2, align 1, !tbaa !9
  %15 = add i8 %.0..0..0..0..us.us.us.2, 1
  store volatile i8 %15, ptr %2, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
  %16 = trunc i32 %.018.us.us.us to i8
  %17 = or disjoint i8 %16, 3
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
  store volatile i8 %17, ptr %2, align 1, !tbaa !9
  %.0..0..0..0..us.us.us.3 = load volatile i8, ptr %2, align 1, !tbaa !9
  %18 = add i8 %.0..0..0..0..us.us.us.3, 1
  store volatile i8 %18, ptr %2, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
  %19 = add nuw nsw i32 %.018.us.us.us, 4
  %niter.next.3 = add i32 %niter, 4
  %niter.ncmp.3 = icmp eq i32 %niter.next.3, %unroll_iter
  br i1 %niter.ncmp.3, label %._crit_edge.us.us.us.unr-lcssa, label %.preheader.us.us.us.new, !llvm.loop !10

._crit_edge.us.us.us.unr-lcssa:                   ; preds = %.preheader.us.us.us.new, %.preheader.us.us.us
  %.018.us.us.us.unr = phi i32 [ 0, %.preheader.us.us.us ], [ %19, %.preheader.us.us.us.new ]
  br i1 %lcmp.mod.not, label %._crit_edge.us.us.us, label %.epil.preheader

.epil.preheader:                                  ; preds = %._crit_edge.us.us.us.unr-lcssa, %.epil.preheader
  %.018.us.us.us.epil = phi i32 [ %22, %.epil.preheader ], [ %.018.us.us.us.unr, %._crit_edge.us.us.us.unr-lcssa ]
  %epil.iter = phi i32 [ %epil.iter.next, %.epil.preheader ], [ 0, %._crit_edge.us.us.us.unr-lcssa ]
  %20 = trunc i32 %.018.us.us.us.epil to i8
  call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
  store volatile i8 %20, ptr %2, align 1, !tbaa !9
  %.0..0..0..0..us.us.us.epil = load volatile i8, ptr %2, align 1, !tbaa !9
  %21 = add i8 %.0..0..0..0..us.us.us.epil, 1
  store volatile i8 %21, ptr %2, align 1, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
  %22 = add nuw nsw i32 %.018.us.us.us.epil, 1
  %epil.iter.next = add i32 %epil.iter, 1
  %epil.iter.cmp.not = icmp eq i32 %epil.iter.next, %xtraiter
  br i1 %epil.iter.cmp.not, label %._crit_edge.us.us.us, label %.epil.preheader, !llvm.loop !12

._crit_edge.us.us.us:                             ; preds = %.epil.preheader, %._crit_edge.us.us.us.unr-lcssa
  %23 = add nuw nsw i32 %.01519.us.us.us, 1
  %exitcond28.not = icmp eq i32 %23, %.sroa.6.0.copyload
  br i1 %exitcond28.not, label %._crit_edge20.split.us.us.us, label %.preheader.us.us.us, !llvm.loop !14

._crit_edge20.split.us.us.us:                     ; preds = %._crit_edge.us.us.us
  %24 = add nuw nsw i32 %.01621.us.us, 1
  %exitcond29.not = icmp eq i32 %24, %.sroa.5.0.copyload
  br i1 %exitcond29.not, label %._crit_edge, label %.preheader17.us.us, !llvm.loop !15

._crit_edge:                                      ; preds = %._crit_edge20.split.us.us.us, %1
  ret ptr null
}

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress nofree norecurse nounwind memory(argmem: read, inaccessiblemem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!7, !7, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = distinct !{!12, !13}
!13 = !{!"llvm.loop.unroll.disable"}
!14 = distinct !{!14, !11}
!15 = distinct !{!15, !11}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyCFGPass,LoopSimplifyPass,LoopUnrollPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass