; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu/general (depthwise_pointwise_convolution)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ConvolutionParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %union.ActivationSpec, i32, i32, i32, i32 }
%union.ActivationSpec = type { %struct.ClipParamSpec }
%struct.ClipParamSpec = type { float, float }
%struct.ActivationParamSpec = type { i32, [4 x float] }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z39depthwise_pointwise_convolution_general10TensorDescPvS0_S_PKvS_S2_20ConvolutionParamSpecS_S2_S_S2_jS0_S_S0_19ActivationParamSpecS4_(ptr noundef byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef %2, ptr noundef byval(%struct.TensorDesc) align 8 %3, ptr noundef %4, ptr noundef byval(%struct.TensorDesc) align 8 %5, ptr noundef %6, ptr noundef byval(%struct.ConvolutionParamSpec) align 8 %7, ptr noundef byval(%struct.TensorDesc) align 8 %8, ptr noundef %9, ptr noundef byval(%struct.TensorDesc) align 8 %10, ptr noundef %11, i32 noundef %12, ptr noundef %13, ptr noundef byval(%struct.TensorDesc) align 8 %14, ptr noundef %15, ptr noundef byval(%struct.ActivationParamSpec) align 8 %16, ptr noundef byval(%struct.ActivationParamSpec) align 8 %17) #2 {
  %19 = alloca ptr, align 8
  %20 = alloca ptr, align 8
  %21 = alloca ptr, align 8
  %22 = alloca ptr, align 8
  %23 = alloca ptr, align 8
  %24 = alloca ptr, align 8
  %25 = alloca i32, align 4
  %26 = alloca ptr, align 8
  %27 = alloca ptr, align 8
  %28 = alloca %struct.TensorDesc, align 8
  %29 = alloca %struct.TensorDesc, align 8
  %30 = alloca i32, align 4
  store ptr %1, ptr %19, align 8, !tbaa !5
  store ptr %2, ptr %20, align 8, !tbaa !5
  store ptr %4, ptr %21, align 8, !tbaa !5
  store ptr %6, ptr %22, align 8, !tbaa !5
  store ptr %9, ptr %23, align 8, !tbaa !5
  store ptr %11, ptr %24, align 8, !tbaa !5
  store i32 %12, ptr %25, align 4, !tbaa !9
  store ptr %13, ptr %26, align 8, !tbaa !5
  store ptr %15, ptr %27, align 8, !tbaa !5
  %31 = load ptr, ptr %20, align 8, !tbaa !5
  %32 = icmp eq ptr %31, null
  br i1 %32, label %33, label %37

33:                                               ; preds = %18
  %34 = load ptr, ptr %27, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %28, ptr align 8 %14, i64 92, i1 false), !tbaa.struct !11
  %35 = call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8 %28)
  %36 = zext i32 %35 to i64
  call void @_Z10UNI_MEMSETPvim(ptr noundef %34, i32 noundef 0, i64 noundef %36)
  br label %42

37:                                               ; preds = %18
  %38 = load ptr, ptr %27, align 8, !tbaa !5
  %39 = load ptr, ptr %20, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %29, ptr align 8 %14, i64 92, i1 false), !tbaa.struct !11
  %40 = call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8 %29)
  %41 = zext i32 %40 to i64
  call void @_Z10UNI_MEMCPYPvPKvm(ptr noundef %38, ptr noundef %39, i64 noundef %41)
  br label %42

42:                                               ; preds = %37, %33
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #5
  store i32 0, ptr %30, align 4, !tbaa !17
  %43 = getelementptr inbounds %struct.TensorDesc, ptr %0, i32 0, i32 0
  %44 = load i32, ptr %43, align 8, !tbaa !19
  switch i32 %44, label %45 [
  ]

45:                                               ; preds = %42
  store i32 51, ptr %30, align 4, !tbaa !17
  br label %46

46:                                               ; preds = %45
  %47 = load i32, ptr %30, align 4, !tbaa !17
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #5
  ret i32 %47
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z10UNI_MEMSETPvim(ptr noundef, i32 noundef, i64 noundef) #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) #4

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z10UNI_MEMCPYPvPKvm(ptr noundef, ptr noundef, i64 noundef) #4

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{i64 0, i64 4, !12, i64 4, i64 4, !14, i64 8, i64 4, !9, i64 12, i64 80, !16}
!12 = !{!13, !13, i64 0}
!13 = !{!"_ZTS8DataType", !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS10DataFormat", !7, i64 0}
!16 = !{!7, !7, i64 0}
!17 = !{!18, !18, i64 0}
!18 = !{!"_ZTS2EE", !7, i64 0}
!19 = !{!20, !13, i64 0}
!20 = !{!"_ZTS10TensorDesc", !13, i64 0, !15, i64 4, !10, i64 8, !7, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ConvolutionParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %union.ActivationSpec, i32, i32, i32, i32 }
%union.ActivationSpec = type { %struct.ClipParamSpec }
%struct.ClipParamSpec = type { float, float }
%struct.ActivationParamSpec = type { i32, [4 x float] }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z39depthwise_pointwise_convolution_general10TensorDescPvS0_S_PKvS_S2_20ConvolutionParamSpecS_S2_S_S2_jS0_S_S0_19ActivationParamSpecS4_(ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %0, ptr nocapture noundef readnone %1, ptr noundef %2, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %3, ptr nocapture noundef readnone %4, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %5, ptr nocapture noundef readnone %6, ptr nocapture noundef readnone byval(%struct.ConvolutionParamSpec) align 8 %7, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %8, ptr nocapture noundef readnone %9, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %10, ptr nocapture noundef readnone %11, i32 noundef %12, ptr nocapture noundef readnone %13, ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %14, ptr noundef %15, ptr nocapture noundef readnone byval(%struct.ActivationParamSpec) align 8 %16, ptr nocapture noundef readnone byval(%struct.ActivationParamSpec) align 8 %17) local_unnamed_addr #0 {
  %19 = icmp eq ptr %2, null
  %20 = tail call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %14)
  %21 = zext i32 %20 to i64
  br i1 %19, label %22, label %23

22:                                               ; preds = %18
  tail call void @_Z10UNI_MEMSETPvim(ptr noundef %15, i32 noundef 0, i64 noundef %21)
  br label %24

23:                                               ; preds = %18
  tail call void @_Z10UNI_MEMCPYPvPKvm(ptr noundef %15, ptr noundef nonnull %2, i64 noundef %21)
  br label %24

24:                                               ; preds = %23, %22
  ret i32 51
}

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_Z10UNI_MEMSETPvim(ptr noundef, i32 noundef, i64 noundef) local_unnamed_addr #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local void @_Z10UNI_MEMCPYPvPKvm(ptr noundef, ptr noundef, i64 noundef) local_unnamed_addr #2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: DSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass