; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime (multi_queue_executor)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.hipsycl::rt::backend_execution_lane_range" = type { i64, i64 }
%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }
%"class.hipsycl::rt::multi_queue_executor" = type <{ %"class.hipsycl::rt::backend_executor", %"class.std::vector", %"class.std::vector.0", i32, [4 x i8] }>
%"class.hipsycl::rt::backend_executor" = type { ptr }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<hipsycl::rt::multi_queue_executor::per_device_data, std::allocator<hipsycl::rt::multi_queue_executor::per_device_data>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::multi_queue_executor::per_device_data, std::allocator<hipsycl::rt::multi_queue_executor::per_device_data>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::multi_queue_executor::per_device_data, std::allocator<hipsycl::rt::multi_queue_executor::per_device_data>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::multi_queue_executor::per_device_data, std::allocator<hipsycl::rt::multi_queue_executor::per_device_data>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<hipsycl::rt::inorder_queue *, std::allocator<hipsycl::rt::inorder_queue *>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::inorder_queue *, std::allocator<hipsycl::rt::inorder_queue *>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::inorder_queue *, std::allocator<hipsycl::rt::inorder_queue *>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::inorder_queue *, std::allocator<hipsycl::rt::inorder_queue *>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"struct.hipsycl::rt::multi_queue_executor::per_device_data" = type { %"struct.hipsycl::rt::backend_execution_lane_range", %"struct.hipsycl::rt::backend_execution_lane_range", %"class.std::vector.7", %"class.hipsycl::rt::moving_statistics" }
%"class.std::vector.7" = type { %"struct.std::_Vector_base.8" }
%"struct.std::_Vector_base.8" = type { %"struct.std::_Vector_base<std::unique_ptr<hipsycl::rt::inorder_executor>, std::allocator<std::unique_ptr<hipsycl::rt::inorder_executor>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::unique_ptr<hipsycl::rt::inorder_executor>, std::allocator<std::unique_ptr<hipsycl::rt::inorder_executor>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::unique_ptr<hipsycl::rt::inorder_executor>, std::allocator<std::unique_ptr<hipsycl::rt::inorder_executor>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::unique_ptr<hipsycl::rt::inorder_executor>, std::allocator<std::unique_ptr<hipsycl::rt::inorder_executor>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.hipsycl::rt::moving_statistics" = type { i64, i64, i64, %"class.std::vector.12" }
%"class.std::vector.12" = type { %"struct.std::_Vector_base.13" }
%"struct.std::_Vector_base.13" = type { %"struct.std::_Vector_base<hipsycl::rt::moving_statistics::submission, std::allocator<hipsycl::rt::moving_statistics::submission>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::moving_statistics::submission, std::allocator<hipsycl::rt::moving_statistics::submission>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::moving_statistics::submission, std::allocator<hipsycl::rt::moving_statistics::submission>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::moving_statistics::submission, std::allocator<hipsycl::rt::moving_statistics::submission>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@.str.7 = external hidden unnamed_addr constant [61 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [94 x i8], align 1
@__PRETTY_FUNCTION__._ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE = external hidden unnamed_addr constant [113 x i8], align 1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

declare noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16)) #2

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) #3

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(104) ptr @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local { i64, i64 } @_ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE(ptr noundef nonnull align 8 dereferenceable(60) %0, i64 %1, i64 %2) #4 align 2 {
  %4 = alloca %"struct.hipsycl::rt::backend_execution_lane_range", align 8
  %5 = alloca %"class.hipsycl::rt::device_id", align 4
  %6 = alloca ptr, align 8
  %7 = getelementptr inbounds { i64, i64 }, ptr %5, i32 0, i32 0
  store i64 %1, ptr %7, align 4
  %8 = getelementptr inbounds { i64, i64 }, ptr %5, i32 0, i32 1
  store i64 %2, ptr %8, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  %9 = load ptr, ptr %6, align 8
  %10 = call noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16) %5)
  %11 = sext i32 %10 to i64
  %12 = getelementptr inbounds %"class.hipsycl::rt::multi_queue_executor", ptr %9, i32 0, i32 1
  %13 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %12) #5
  %14 = icmp ult i64 %11, %13
  br i1 %14, label %15, label %16

15:                                               ; preds = %3
  br label %18

16:                                               ; preds = %3
  call void @__assert_fail(ptr noundef @.str.7, ptr noundef @.str.8, i32 noundef 184, ptr noundef @__PRETTY_FUNCTION__._ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE) #6
  unreachable

17:                                               ; No predecessors!
  br label %18

18:                                               ; preds = %17, %15
  %19 = getelementptr inbounds %"class.hipsycl::rt::multi_queue_executor", ptr %9, i32 0, i32 1
  %20 = call noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16) %5)
  %21 = sext i32 %20 to i64
  %22 = call noundef nonnull align 8 dereferenceable(104) ptr @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %21) #5
  %23 = getelementptr inbounds %"struct.hipsycl::rt::multi_queue_executor::per_device_data", ptr %22, i32 0, i32 1
  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %4, ptr align 8 %23, i64 16, i1 false), !tbaa.struct !9
  %24 = load { i64, i64 }, ptr %4, align 8
  ret { i64, i64 } %24
}

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }
attributes #6 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i64 0, i64 8, !10, i64 8, i64 8, !10}
!10 = !{!11, !11, i64 0}
!11 = !{!"long", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::device_id" = type { %"struct.hipsycl::rt::backend_descriptor", i32 }
%"struct.hipsycl::rt::backend_descriptor" = type { i32, i32, i32 }

@.str.7 = external hidden unnamed_addr constant [61 x i8], align 1
@.str.8 = external hidden unnamed_addr constant [94 x i8], align 1
@__PRETTY_FUNCTION__._ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE = external hidden unnamed_addr constant [113 x i8], align 1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

declare noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16)) local_unnamed_addr #1

; Function Attrs: noreturn nounwind
declare void @__assert_fail(ptr noundef, ptr noundef, i32 noundef, ptr noundef) local_unnamed_addr #2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(104) ptr @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local { i64, i64 } @_ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE(ptr noundef nonnull align 8 dereferenceable(60) %0, i64 %1, i64 %2) local_unnamed_addr #3 align 2 {
  %4 = alloca %"class.hipsycl::rt::device_id", align 8
  store i64 %1, ptr %4, align 8
  %5 = getelementptr inbounds i8, ptr %4, i64 8
  store i64 %2, ptr %5, align 8
  %6 = call noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16) %4)
  %7 = sext i32 %6 to i64
  %8 = getelementptr inbounds i8, ptr %0, i64 8
  %9 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %8) #4
  %10 = icmp ugt i64 %9, %7
  br i1 %10, label %12, label %11

11:                                               ; preds = %3
  call void @__assert_fail(ptr noundef nonnull @.str.7, ptr noundef nonnull @.str.8, i32 noundef 184, ptr noundef nonnull @__PRETTY_FUNCTION__._ZNK7hipsycl2rt20multi_queue_executor31get_kernel_execution_lane_rangeENS0_9device_idE) #5
  unreachable

12:                                               ; preds = %3
  %13 = call noundef i32 @_ZNK7hipsycl2rt9device_id6get_idEv(ptr noundef nonnull align 4 dereferenceable(16) %4)
  %14 = sext i32 %13 to i64
  %15 = call noundef nonnull align 8 dereferenceable(104) ptr @_ZNKSt6vectorIN7hipsycl2rt20multi_queue_executor15per_device_dataESaIS3_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %8, i64 noundef %14) #4
  %16 = getelementptr inbounds i8, ptr %15, i64 16
  %.sroa.0.0.copyload = load i64, ptr %16, align 8, !tbaa !5
  %.sroa.2.0..sroa_idx = getelementptr inbounds i8, ptr %15, i64 24
  %.sroa.2.0.copyload = load i64, ptr %.sroa.2.0..sroa_idx, align 8, !tbaa !5
  %.fca.0.insert = insertvalue { i64, i64 } poison, i64 %.sroa.0.0.copyload, 0
  %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %.sroa.2.0.copyload, 1
  ret { i64, i64 } %.fca.1.insert
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { noreturn nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }
attributes #5 = { noreturn nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"long", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,SROAPass,SimplifyCFGPass