; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/pcuda (pcuda_thread_state)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.hipsycl::rt::pcuda::thread_local_state" = type { ptr, i32, i32, i32, %"class.std::vector", %"class.std::optional" }
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>, std::allocator<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>>>::_Vector_impl" }
%"struct.std::_Vector_base<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>, std::allocator<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>>>::_Vector_impl" = type { %"struct.std::_Vector_base<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>, std::allocator<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>>>::_Vector_impl_data" }
%"struct.std::_Vector_base<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>, std::allocator<std::vector<std::vector<hipsycl::rt::pcuda::thread_local_state::per_device_data>>>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::optional" = type { %"struct.std::_Optional_base" }
%"struct.std::_Optional_base" = type { %"struct.std::_Optional_payload" }
%"struct.std::_Optional_payload" = type { %"struct.std::_Optional_payload_base.base", [7 x i8] }
%"struct.std::_Optional_payload_base.base" = type <{ %"union.std::_Optional_payload_base<hipsycl::rt::pcuda::thread_local_state::kernel_call_configuration>::_Storage", i8 }>
%"union.std::_Optional_payload_base<hipsycl::rt::pcuda::thread_local_state::kernel_call_configuration>::_Storage" = type { %"struct.hipsycl::rt::pcuda::thread_local_state::kernel_call_configuration" }
%"struct.hipsycl::rt::pcuda::thread_local_state::kernel_call_configuration" = type { %struct.dim3, %struct.dim3, i64, ptr }
%struct.dim3 = type { i32, i32, i32 }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime12get_topologyEv(ptr noundef nonnull align 8 dereferenceable(40)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda15device_topology12all_backendsEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZN7hipsycl2rt5pcuda18thread_local_state11set_backendEi(ptr noundef nonnull align 8 dereferenceable(96) %0, i32 noundef %1) #2 align 2 {
  %3 = alloca i1, align 1
  %4 = alloca ptr, align 8
  %5 = alloca i32, align 4
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %4, align 8, !tbaa !5
  store i32 %1, ptr %5, align 4, !tbaa !9
  %8 = load ptr, ptr %4, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #3
  %9 = getelementptr inbounds %"class.hipsycl::rt::pcuda::thread_local_state", ptr %8, i32 0, i32 0
  %10 = load ptr, ptr %9, align 8, !tbaa !11
  %11 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime12get_topologyEv(ptr noundef nonnull align 8 dereferenceable(40) %10)
  %12 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda15device_topology12all_backendsEv(ptr noundef nonnull align 8 dereferenceable(24) %11)
  store ptr %12, ptr %6, align 8, !tbaa !5
  %13 = load i32, ptr %5, align 4, !tbaa !9
  %14 = sext i32 %13 to i64
  %15 = load ptr, ptr %6, align 8, !tbaa !5
  %16 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %15) #3
  %17 = icmp ult i64 %14, %16
  br i1 %17, label %18, label %21

18:                                               ; preds = %2
  %19 = load i32, ptr %5, align 4, !tbaa !9
  %20 = getelementptr inbounds %"class.hipsycl::rt::pcuda::thread_local_state", ptr %8, i32 0, i32 3
  store i32 %19, ptr %20, align 8, !tbaa !22
  store i1 true, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %22

21:                                               ; preds = %2
  store i1 false, ptr %3, align 1
  store i32 1, ptr %7, align 4
  br label %22

22:                                               ; preds = %21, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #3
  %23 = load i1, ptr %3, align 1
  ret i1 %23
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !6, i64 0}
!12 = !{!"_ZTSN7hipsycl2rt5pcuda18thread_local_stateE", !6, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !13, i64 24, !17, i64 48}
!13 = !{!"_ZTSSt6vectorIS_IS_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS4_EESaIS6_EESaIS8_EE", !14, i64 0}
!14 = !{!"_ZTSSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE", !15, i64 0}
!15 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE12_Vector_implE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!17 = !{!"_ZTSSt8optionalIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationEE", !18, i64 0}
!18 = !{!"_ZTSSt14_Optional_baseIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationELb1ELb1EE", !19, i64 0}
!19 = !{!"_ZTSSt17_Optional_payloadIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationELb1ELb1ELb1EE", !20, i64 0}
!20 = !{!"_ZTSSt22_Optional_payload_baseIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationEE", !7, i64 0, !21, i64 40}
!21 = !{!"bool", !7, i64 0}
!22 = !{!12, !10, i64 16}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime12get_topologyEv(ptr noundef nonnull align 8 dereferenceable(40)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda15device_topology12all_backendsEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef zeroext i1 @_ZN7hipsycl2rt5pcuda18thread_local_state11set_backendEi(ptr nocapture noundef nonnull align 8 dereferenceable(96) %0, i32 noundef %1) local_unnamed_addr #0 align 2 {
  %3 = load ptr, ptr %0, align 8, !tbaa !5
  %4 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda13pcuda_runtime12get_topologyEv(ptr noundef nonnull align 8 dereferenceable(40) %3)
  %5 = tail call noundef nonnull align 8 dereferenceable(24) ptr @_ZNK7hipsycl2rt5pcuda15device_topology12all_backendsEv(ptr noundef nonnull align 8 dereferenceable(24) %4)
  %6 = sext i32 %1 to i64
  %7 = tail call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology7backendESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #1
  %8 = icmp ugt i64 %7, %6
  br i1 %8, label %9, label %11

9:                                                ; preds = %2
  %10 = getelementptr inbounds i8, ptr %0, i64 16
  store i32 %1, ptr %10, align 8, !tbaa !20
  br label %11

11:                                               ; preds = %2, %9
  ret i1 %8
}

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTSN7hipsycl2rt5pcuda18thread_local_stateE", !7, i64 0, !10, i64 8, !10, i64 12, !10, i64 16, !11, i64 24, !15, i64 48}
!7 = !{!"any pointer", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"int", !8, i64 0}
!11 = !{!"_ZTSSt6vectorIS_IS_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS4_EESaIS6_EESaIS8_EE", !12, i64 0}
!12 = !{!"_ZTSSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE", !13, i64 0}
!13 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE12_Vector_implE", !14, i64 0}
!14 = !{!"_ZTSNSt12_Vector_baseISt6vectorIS0_IN7hipsycl2rt5pcuda18thread_local_state15per_device_dataESaIS5_EESaIS7_EESaIS9_EE17_Vector_impl_dataE", !7, i64 0, !7, i64 8, !7, i64 16}
!15 = !{!"_ZTSSt8optionalIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationEE", !16, i64 0}
!16 = !{!"_ZTSSt14_Optional_baseIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationELb1ELb1EE", !17, i64 0}
!17 = !{!"_ZTSSt17_Optional_payloadIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationELb1ELb1ELb1EE", !18, i64 0}
!18 = !{!"_ZTSSt22_Optional_payload_baseIN7hipsycl2rt5pcuda18thread_local_state25kernel_call_configurationEE", !8, i64 0, !19, i64 40}
!19 = !{!"bool", !8, i64 0}
!20 = !{!6, !10, i64 16}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass