; LLVM IR from huawei-noah/bolt :: compute/tensor/src (batch_norm)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.BatchNormParamSpec = type { i32, float, float, float }
%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ArchInfo = type { i32, ptr }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z28batch_norm_infer_output_sizeP6Tensor18BatchNormParamSpecS0_P8ArchInfo(ptr noundef %0, i64 %1, <2 x float> %2, ptr noundef %3, ptr noundef %4) #0 {
  %6 = alloca i32, align 4
  %7 = alloca %struct.BatchNormParamSpec, align 4
  %8 = alloca ptr, align 8
  %9 = alloca ptr, align 8
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  %12 = alloca i32, align 4
  %13 = alloca %struct.TensorDesc, align 8
  %14 = getelementptr inbounds { i64, <2 x float> }, ptr %7, i32 0, i32 0
  store i64 %1, ptr %14, align 4
  %15 = getelementptr inbounds { i64, <2 x float> }, ptr %7, i32 0, i32 1
  store <2 x float> %2, ptr %15, align 4
  store ptr %0, ptr %8, align 8, !tbaa !5
  store ptr %3, ptr %9, align 8, !tbaa !5
  store ptr %4, ptr %10, align 8, !tbaa !5
  %16 = load ptr, ptr %8, align 8, !tbaa !5
  %17 = icmp eq ptr %16, null
  br i1 %17, label %21, label %18

18:                                               ; preds = %5
  %19 = load ptr, ptr %9, align 8, !tbaa !5
  %20 = icmp eq ptr %19, null
  br i1 %20, label %21, label %22

21:                                               ; preds = %18, %5
  store i32 1, ptr %6, align 4
  br label %60

22:                                               ; preds = %18
  call void @llvm.lifetime.start.p0(i64 4, ptr %11) #3
  %23 = load ptr, ptr %10, align 8, !tbaa !5
  %24 = getelementptr inbounds %struct.ArchInfo, ptr %23, i32 0, i32 0
  %25 = load i32, ptr %24, align 8, !tbaa !9
  store i32 %25, ptr %11, align 4, !tbaa !12
  call void @llvm.lifetime.start.p0(i64 4, ptr %12) #3
  store i32 51, ptr %12, align 4, !tbaa !13
  %26 = load i32, ptr %11, align 4, !tbaa !12
  %27 = icmp eq i32 %26, 1
  br i1 %27, label %55, label %28

28:                                               ; preds = %22
  %29 = load i32, ptr %11, align 4, !tbaa !12
  %30 = icmp eq i32 %29, 8
  br i1 %30, label %55, label %31

31:                                               ; preds = %28
  %32 = load i32, ptr %11, align 4, !tbaa !12
  %33 = icmp eq i32 %32, 9
  br i1 %33, label %55, label %34

34:                                               ; preds = %31
  %35 = load i32, ptr %11, align 4, !tbaa !12
  %36 = icmp eq i32 %35, 10
  br i1 %36, label %55, label %37

37:                                               ; preds = %34
  %38 = load i32, ptr %11, align 4, !tbaa !12
  %39 = icmp eq i32 %38, 9
  br i1 %39, label %55, label %40

40:                                               ; preds = %37
  %41 = load i32, ptr %11, align 4, !tbaa !12
  %42 = icmp eq i32 %41, 10
  br i1 %42, label %55, label %43

43:                                               ; preds = %40
  %44 = load i32, ptr %11, align 4, !tbaa !12
  %45 = icmp eq i32 %44, 5
  br i1 %45, label %55, label %46

46:                                               ; preds = %43
  %47 = load i32, ptr %11, align 4, !tbaa !12
  %48 = icmp eq i32 %47, 6
  br i1 %48, label %55, label %49

49:                                               ; preds = %46
  %50 = load i32, ptr %11, align 4, !tbaa !12
  %51 = icmp eq i32 %50, 4
  br i1 %51, label %55, label %52

52:                                               ; preds = %49
  %53 = load i32, ptr %11, align 4, !tbaa !12
  %54 = icmp eq i32 %53, 3
  br i1 %54, label %55, label %58

55:                                               ; preds = %52, %49, %46, %43, %40, %37, %34, %31, %28, %22
  %56 = load ptr, ptr %9, align 8, !tbaa !5
  %57 = load ptr, ptr %8, align 8, !tbaa !5
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind writable sret(%struct.TensorDesc) align 4 %13, ptr noundef nonnull align 8 dereferenceable(32) %57)
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %56, ptr noundef byval(%struct.TensorDesc) align 8 %13)
  store i32 0, ptr %12, align 4, !tbaa !13
  br label %58

58:                                               ; preds = %55, %52
  %59 = load i32, ptr %12, align 4, !tbaa !13
  store i32 %59, ptr %6, align 4
  call void @llvm.lifetime.end.p0(i64 4, ptr %12) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %11) #3
  br label %60

60:                                               ; preds = %58, %21
  %61 = load i32, ptr %6, align 4
  ret i32 %61
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) #2 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !11, i64 0}
!10 = !{!"_ZTS8ArchInfo", !11, i64 0, !6, i64 8}
!11 = !{!"_ZTS4Arch", !7, i64 0}
!12 = !{!11, !11, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS2EE", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }

; Function Attrs: mustprogress uwtable
define dso_local noundef range(i32 0, 52) i32 @_Z28batch_norm_infer_output_sizeP6Tensor18BatchNormParamSpecS0_P8ArchInfo(ptr noundef %0, i64 %1, <2 x float> %2, ptr noundef %3, ptr nocapture noundef readonly %4) local_unnamed_addr #0 {
  %6 = alloca %struct.TensorDesc, align 8
  %7 = icmp eq ptr %0, null
  %8 = icmp eq ptr %3, null
  %or.cond = or i1 %7, %8
  br i1 %or.cond, label %12, label %9

9:                                                ; preds = %5
  %10 = load i32, ptr %4, align 8, !tbaa !5
  switch i32 %10, label %12 [
    i32 10, label %11
    i32 9, label %11
    i32 8, label %11
    i32 6, label %11
    i32 5, label %11
    i32 4, label %11
    i32 3, label %11
    i32 1, label %11
  ]

11:                                               ; preds = %9, %9, %9, %9, %9, %9, %9, %9
  call void @_ZN6Tensor8get_descEv(ptr dead_on_unwind nonnull writable sret(%struct.TensorDesc) align 4 %6, ptr noundef nonnull align 8 dereferenceable(32) %0)
  call void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32) %3, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %6)
  br label %12

12:                                               ; preds = %11, %9, %5
  %.035 = phi i32 [ 1, %5 ], [ 0, %11 ], [ 51, %9 ]
  ret i32 %.035
}

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor6resizeE10TensorDesc(ptr noundef nonnull align 8 dereferenceable(32), ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZN6Tensor8get_descEv(ptr dead_on_unwind noalias writable sret(%struct.TensorDesc) align 4, ptr noundef nonnull align 8 dereferenceable(32)) local_unnamed_addr #1 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !7, i64 0}
!6 = !{!"_ZTS8ArchInfo", !7, i64 0, !10, i64 8}
!7 = !{!"_ZTS4Arch", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"any pointer", !8, i64 0}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass