; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis6 (FastEntityStatePdu)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::ArticulationParameter" = type { ptr, i8, i8, i16, i32, double }
%"class.DIS::FastEntityStatePdu" = type { %"class.DIS::EntityInformationFamilyPdu.base", i16, i16, i16, i8, i8, i8, i8, i16, i8, i8, i8, i8, i8, i8, i16, i8, i8, i8, i8, float, float, float, double, double, double, float, float, float, i32, i8, [15 x i8], float, float, float, float, float, float, [12 x i8], i32, %"class.std::vector" }
%"class.DIS::EntityInformationFamilyPdu.base" = type { %"class.DIS::Pdu.base" }
%"class.DIS::Pdu.base" = type <{ ptr, i8, i8, i8, i8, i32, i16, i16 }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DIS::ArticulationParameter, std::allocator<DIS::ArticulationParameter>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::ArticulationParameter, std::allocator<DIS::ArticulationParameter>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::ArticulationParameter, std::allocator<DIS::ArticulationParameter>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::ArticulationParameter, std::allocator<DIS::ArticulationParameter>>::_Vector_impl_data" = type { ptr, ptr, ptr }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3DIS21ArticulationParameterC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZNK3DIS18FastEntityStatePdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(176) %0) unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca ptr, align 8
  %3 = alloca i32, align 4
  %4 = alloca i64, align 8
  %5 = alloca %"class.DIS::ArticulationParameter", align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  store ptr %0, ptr %2, align 8, !tbaa !5
  %8 = load ptr, ptr %2, align 8
  call void @llvm.lifetime.start.p0(i64 4, ptr %3) #6
  store i32 0, ptr %3, align 4, !tbaa !9
  %9 = call noundef i32 @_ZNK3DIS26EntityInformationFamilyPdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(20) %8)
  store i32 %9, ptr %3, align 4, !tbaa !9
  %10 = load i32, ptr %3, align 4, !tbaa !9
  %11 = add nsw i32 %10, 2
  store i32 %11, ptr %3, align 4, !tbaa !9
  %12 = load i32, ptr %3, align 4, !tbaa !9
  %13 = add nsw i32 %12, 2
  store i32 %13, ptr %3, align 4, !tbaa !9
  %14 = load i32, ptr %3, align 4, !tbaa !9
  %15 = add nsw i32 %14, 2
  store i32 %15, ptr %3, align 4, !tbaa !9
  %16 = load i32, ptr %3, align 4, !tbaa !9
  %17 = add nsw i32 %16, 1
  store i32 %17, ptr %3, align 4, !tbaa !9
  %18 = load i32, ptr %3, align 4, !tbaa !9
  %19 = add nsw i32 %18, 1
  store i32 %19, ptr %3, align 4, !tbaa !9
  %20 = load i32, ptr %3, align 4, !tbaa !9
  %21 = add nsw i32 %20, 1
  store i32 %21, ptr %3, align 4, !tbaa !9
  %22 = load i32, ptr %3, align 4, !tbaa !9
  %23 = add nsw i32 %22, 1
  store i32 %23, ptr %3, align 4, !tbaa !9
  %24 = load i32, ptr %3, align 4, !tbaa !9
  %25 = add nsw i32 %24, 2
  store i32 %25, ptr %3, align 4, !tbaa !9
  %26 = load i32, ptr %3, align 4, !tbaa !9
  %27 = add nsw i32 %26, 1
  store i32 %27, ptr %3, align 4, !tbaa !9
  %28 = load i32, ptr %3, align 4, !tbaa !9
  %29 = add nsw i32 %28, 1
  store i32 %29, ptr %3, align 4, !tbaa !9
  %30 = load i32, ptr %3, align 4, !tbaa !9
  %31 = add nsw i32 %30, 1
  store i32 %31, ptr %3, align 4, !tbaa !9
  %32 = load i32, ptr %3, align 4, !tbaa !9
  %33 = add nsw i32 %32, 1
  store i32 %33, ptr %3, align 4, !tbaa !9
  %34 = load i32, ptr %3, align 4, !tbaa !9
  %35 = add nsw i32 %34, 1
  store i32 %35, ptr %3, align 4, !tbaa !9
  %36 = load i32, ptr %3, align 4, !tbaa !9
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %3, align 4, !tbaa !9
  %38 = load i32, ptr %3, align 4, !tbaa !9
  %39 = add nsw i32 %38, 2
  store i32 %39, ptr %3, align 4, !tbaa !9
  %40 = load i32, ptr %3, align 4, !tbaa !9
  %41 = add nsw i32 %40, 1
  store i32 %41, ptr %3, align 4, !tbaa !9
  %42 = load i32, ptr %3, align 4, !tbaa !9
  %43 = add nsw i32 %42, 1
  store i32 %43, ptr %3, align 4, !tbaa !9
  %44 = load i32, ptr %3, align 4, !tbaa !9
  %45 = add nsw i32 %44, 1
  store i32 %45, ptr %3, align 4, !tbaa !9
  %46 = load i32, ptr %3, align 4, !tbaa !9
  %47 = add nsw i32 %46, 1
  store i32 %47, ptr %3, align 4, !tbaa !9
  %48 = load i32, ptr %3, align 4, !tbaa !9
  %49 = add nsw i32 %48, 4
  store i32 %49, ptr %3, align 4, !tbaa !9
  %50 = load i32, ptr %3, align 4, !tbaa !9
  %51 = add nsw i32 %50, 4
  store i32 %51, ptr %3, align 4, !tbaa !9
  %52 = load i32, ptr %3, align 4, !tbaa !9
  %53 = add nsw i32 %52, 4
  store i32 %53, ptr %3, align 4, !tbaa !9
  %54 = load i32, ptr %3, align 4, !tbaa !9
  %55 = add nsw i32 %54, 8
  store i32 %55, ptr %3, align 4, !tbaa !9
  %56 = load i32, ptr %3, align 4, !tbaa !9
  %57 = add nsw i32 %56, 8
  store i32 %57, ptr %3, align 4, !tbaa !9
  %58 = load i32, ptr %3, align 4, !tbaa !9
  %59 = add nsw i32 %58, 8
  store i32 %59, ptr %3, align 4, !tbaa !9
  %60 = load i32, ptr %3, align 4, !tbaa !9
  %61 = add nsw i32 %60, 4
  store i32 %61, ptr %3, align 4, !tbaa !9
  %62 = load i32, ptr %3, align 4, !tbaa !9
  %63 = add nsw i32 %62, 4
  store i32 %63, ptr %3, align 4, !tbaa !9
  %64 = load i32, ptr %3, align 4, !tbaa !9
  %65 = add nsw i32 %64, 4
  store i32 %65, ptr %3, align 4, !tbaa !9
  %66 = load i32, ptr %3, align 4, !tbaa !9
  %67 = add nsw i32 %66, 4
  store i32 %67, ptr %3, align 4, !tbaa !9
  %68 = load i32, ptr %3, align 4, !tbaa !9
  %69 = add nsw i32 %68, 1
  store i32 %69, ptr %3, align 4, !tbaa !9
  %70 = load i32, ptr %3, align 4, !tbaa !9
  %71 = add nsw i32 %70, 15
  store i32 %71, ptr %3, align 4, !tbaa !9
  %72 = load i32, ptr %3, align 4, !tbaa !9
  %73 = add nsw i32 %72, 4
  store i32 %73, ptr %3, align 4, !tbaa !9
  %74 = load i32, ptr %3, align 4, !tbaa !9
  %75 = add nsw i32 %74, 4
  store i32 %75, ptr %3, align 4, !tbaa !9
  %76 = load i32, ptr %3, align 4, !tbaa !9
  %77 = add nsw i32 %76, 4
  store i32 %77, ptr %3, align 4, !tbaa !9
  %78 = load i32, ptr %3, align 4, !tbaa !9
  %79 = add nsw i32 %78, 4
  store i32 %79, ptr %3, align 4, !tbaa !9
  %80 = load i32, ptr %3, align 4, !tbaa !9
  %81 = add nsw i32 %80, 4
  store i32 %81, ptr %3, align 4, !tbaa !9
  %82 = load i32, ptr %3, align 4, !tbaa !9
  %83 = add nsw i32 %82, 4
  store i32 %83, ptr %3, align 4, !tbaa !9
  %84 = load i32, ptr %3, align 4, !tbaa !9
  %85 = add nsw i32 %84, 12
  store i32 %85, ptr %3, align 4, !tbaa !9
  %86 = load i32, ptr %3, align 4, !tbaa !9
  %87 = add nsw i32 %86, 4
  store i32 %87, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %4) #6
  store i64 0, ptr %4, align 8, !tbaa !11
  br label %88

88:                                               ; preds = %102, %1
  %89 = load i64, ptr %4, align 8, !tbaa !11
  %90 = getelementptr inbounds %"class.DIS::FastEntityStatePdu", ptr %8, i32 0, i32 40
  %91 = call noundef i64 @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %90) #6
  %92 = icmp ult i64 %89, %91
  br i1 %92, label %94, label %93

93:                                               ; preds = %88
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #6
  br label %109

94:                                               ; preds = %88
  call void @llvm.lifetime.start.p0(i64 24, ptr %5) #6
  %95 = getelementptr inbounds %"class.DIS::FastEntityStatePdu", ptr %8, i32 0, i32 40
  %96 = load i64, ptr %4, align 8, !tbaa !11
  %97 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %95, i64 noundef %96) #6
  call void @_ZN3DIS21ArticulationParameterC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %5, ptr noundef nonnull align 8 dereferenceable(24) %97) #6
  %98 = load i32, ptr %3, align 4, !tbaa !9
  %99 = invoke noundef i32 @_ZNK3DIS21ArticulationParameter17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5)
          to label %100 unwind label %105

100:                                              ; preds = %94
  %101 = add nsw i32 %98, %99
  store i32 %101, ptr %3, align 4, !tbaa !9
  call void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #6
  br label %102

102:                                              ; preds = %100
  %103 = load i64, ptr %4, align 8, !tbaa !11
  %104 = add i64 %103, 1
  store i64 %104, ptr %4, align 8, !tbaa !11
  br label %88, !llvm.loop !13

105:                                              ; preds = %94
  %106 = landingpad { ptr, i32 }
          cleanup
  %107 = extractvalue { ptr, i32 } %106, 0
  store ptr %107, ptr %6, align 8
  %108 = extractvalue { ptr, i32 } %106, 1
  store i32 %108, ptr %7, align 4
  call void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr %5) #6
  call void @llvm.lifetime.end.p0(i64 8, ptr %4) #6
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #6
  br label %111

109:                                              ; preds = %93
  %110 = load i32, ptr %3, align 4, !tbaa !9
  call void @llvm.lifetime.end.p0(i64 4, ptr %3) #6
  ret i32 %110

111:                                              ; preds = %105
  %112 = load ptr, ptr %6, align 8
  %113 = load i32, ptr %7, align 4
  %114 = insertvalue { ptr, i32 } poison, ptr %112, 0
  %115 = insertvalue { ptr, i32 } %114, i32 %113, 1
  resume { ptr, i32 } %115
}

declare noundef i32 @_ZNK3DIS26EntityInformationFamilyPdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(20)) unnamed_addr #5

declare noundef i32 @_ZNK3DIS21ArticulationParameter17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #5

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"long long", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::ArticulationParameter" = type { ptr, i8, i8, i16, i32, double }

declare i32 @__gxx_personality_v0(...)

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: inlinehint mustprogress nounwind uwtable
declare dso_local void @_ZN3DIS21ArticulationParameterC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #2 align 2

; Function Attrs: nounwind
declare void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_ZNK3DIS18FastEntityStatePdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(176) %0) unnamed_addr #4 align 2 personality ptr @__gxx_personality_v0 {
  %2 = alloca %"class.DIS::ArticulationParameter", align 8
  %3 = tail call noundef i32 @_ZNK3DIS26EntityInformationFamilyPdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(20) %0)
  %4 = add nsw i32 %3, 132
  %5 = getelementptr inbounds i8, ptr %0, i64 152
  %6 = tail call noundef i64 @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  %.not = icmp eq i64 %6, 0
  br i1 %.not, label %._crit_edge, label %.lr.ph

._crit_edge:                                      ; preds = %9, %1
  %.0.lcssa = phi i32 [ %4, %1 ], [ %10, %9 ]
  ret i32 %.0.lcssa

.lr.ph:                                           ; preds = %1, %9
  %.049 = phi i32 [ %10, %9 ], [ %4, %1 ]
  %.04648 = phi i64 [ %11, %9 ], [ 0, %1 ]
  call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %2) #6
  %7 = call noundef nonnull align 8 dereferenceable(24) ptr @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %5, i64 noundef %.04648) #6
  call void @_ZN3DIS21ArticulationParameterC2ERKS0_(ptr noundef nonnull align 8 dereferenceable(24) %2, ptr noundef nonnull align 8 dereferenceable(24) %7) #6
  %8 = invoke noundef i32 @_ZNK3DIS21ArticulationParameter17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(24) %2)
          to label %9 unwind label %14

9:                                                ; preds = %.lr.ph
  %10 = add nsw i32 %8, %.049
  call void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #6
  %11 = add nuw i64 %.04648, 1
  %12 = call noundef i64 @_ZNKSt6vectorIN3DIS21ArticulationParameterESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %5) #6
  %13 = icmp ult i64 %11, %12
  br i1 %13, label %.lr.ph, label %._crit_edge, !llvm.loop !5

14:                                               ; preds = %.lr.ph
  %15 = landingpad { ptr, i32 }
          cleanup
  call void @_ZN3DIS21ArticulationParameterD1Ev(ptr noundef nonnull align 8 dereferenceable(24) %2) #6
  call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %2) #6
  resume { ptr, i32 } %15
}

declare noundef i32 @_ZNK3DIS26EntityInformationFamilyPdu17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(20)) unnamed_addr #5

declare noundef i32 @_ZNK3DIS21ArticulationParameter17getMarshalledSizeEv(ptr noundef nonnull align 8 dereferenceable(24)) unnamed_addr #5

attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { inlinehint mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #6 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = distinct !{!5, !6}
!6 = !{!"llvm.loop.mustprogress"}


; Effective O3 passes: CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass