; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu (convolution)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ConvolutionParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %union.ActivationSpec, i32, i32, i32, i32 }
%union.ActivationSpec = type { %struct.ClipParamSpec }
%struct.ClipParamSpec = type { float, float }
%struct.ActivationParamSpec = type { i32, [4 x float] }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z15convolution_cpu10TensorDescPvS_PKv20ConvolutionParamSpec27ConvolutionForwardAlgorithmS_S0_S_S2_jS0_S_S0_19ActivationParamSpec4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef byval(%struct.TensorDesc) align 8 %2, ptr noundef %3, ptr noundef byval(%struct.ConvolutionParamSpec) align 8 %4, i32 noundef %5, ptr noundef byval(%struct.TensorDesc) align 8 %6, ptr noundef %7, ptr noundef byval(%struct.TensorDesc) align 8 %8, ptr noundef %9, i32 noundef %10, ptr noundef %11, ptr noundef byval(%struct.TensorDesc) align 8 %12, ptr noundef %13, ptr noundef byval(%struct.ActivationParamSpec) align 8 %14, i32 noundef %15) #0 {
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca i32, align 4
  %20 = alloca ptr, align 8
  %21 = alloca ptr, align 8
  %22 = alloca i32, align 4
  %23 = alloca ptr, align 8
  %24 = alloca ptr, align 8
  %25 = alloca i32, align 4
  %26 = alloca %struct.TensorDesc, align 4
  %27 = alloca %struct.TensorDesc, align 8
  %28 = alloca %struct.TensorDesc, align 8
  %29 = alloca %struct.TensorDesc, align 8
  %30 = alloca i32, align 4
  store ptr %1, ptr %17, align 8, !tbaa !5
  store ptr %3, ptr %18, align 8, !tbaa !5
  store i32 %5, ptr %19, align 4, !tbaa !9
  store ptr %7, ptr %20, align 8, !tbaa !5
  store ptr %9, ptr %21, align 8, !tbaa !5
  store i32 %10, ptr %22, align 4, !tbaa !11
  store ptr %11, ptr %23, align 8, !tbaa !5
  store ptr %13, ptr %24, align 8, !tbaa !5
  store i32 %15, ptr %25, align 4, !tbaa !13
  %31 = getelementptr inbounds %struct.TensorDesc, ptr %0, i32 0, i32 1
  %32 = load i32, ptr %31, align 4, !tbaa !15
  %33 = icmp eq i32 %32, 24
  br i1 %33, label %34, label %44

34:                                               ; preds = %16
  call void @llvm.lifetime.start.p0(i64 92, ptr %26) #5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %26, ptr align 8 %0, i64 92, i1 false), !tbaa.struct !19
  %35 = getelementptr inbounds %struct.TensorDesc, ptr %26, i32 0, i32 1
  store i32 0, ptr %35, align 4, !tbaa !15
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %27, ptr align 8 %0, i64 92, i1 false), !tbaa.struct !19
  %36 = load ptr, ptr %17, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %28, ptr align 4 %26, i64 92, i1 false), !tbaa.struct !19
  %37 = load ptr, ptr %23, align 8, !tbaa !5
  %38 = call noundef i32 @_Z15transformToNCHW10TensorDescPKvS_Pv(ptr noundef byval(%struct.TensorDesc) align 8 %27, ptr noundef %36, ptr noundef byval(%struct.TensorDesc) align 8 %28, ptr noundef %37)
  %39 = load ptr, ptr %23, align 8, !tbaa !5
  store ptr %39, ptr %17, align 8, !tbaa !5
  %40 = load ptr, ptr %23, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %29, ptr align 8 %0, i64 92, i1 false), !tbaa.struct !19
  %41 = call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8 %29)
  %42 = zext i32 %41 to i64
  %43 = getelementptr inbounds i8, ptr %40, i64 %42
  store ptr %43, ptr %23, align 8, !tbaa !5
  call void @llvm.lifetime.end.p0(i64 92, ptr %26) #5
  br label %44

44:                                               ; preds = %34, %16
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #5
  store i32 51, ptr %30, align 4, !tbaa !23
  %45 = load i32, ptr %25, align 4, !tbaa !13
  %46 = icmp eq i32 %45, 1
  br i1 %46, label %47, label %48

47:                                               ; preds = %44
  br label %48

48:                                               ; preds = %47, %44
  %49 = load i32, ptr %30, align 4, !tbaa !23
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #5
  ret i32 %49
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

declare noundef i32 @_Z15transformToNCHW10TensorDescPKvS_Pv(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef) #3

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) #4

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #5 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS27ConvolutionForwardAlgorithm", !7, i64 0}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = !{!14, !14, i64 0}
!14 = !{!"_ZTS4Arch", !7, i64 0}
!15 = !{!16, !18, i64 4}
!16 = !{!"_ZTS10TensorDesc", !17, i64 0, !18, i64 4, !12, i64 8, !7, i64 12}
!17 = !{!"_ZTS8DataType", !7, i64 0}
!18 = !{!"_ZTS10DataFormat", !7, i64 0}
!19 = !{i64 0, i64 4, !20, i64 4, i64 4, !21, i64 8, i64 4, !11, i64 12, i64 80, !22}
!20 = !{!17, !17, i64 0}
!21 = !{!18, !18, i64 0}
!22 = !{!7, !7, i64 0}
!23 = !{!24, !24, i64 0}
!24 = !{!"_ZTS2EE", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ConvolutionParamSpec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %union.ActivationSpec, i32, i32, i32, i32 }
%union.ActivationSpec = type { %struct.ClipParamSpec }
%struct.ClipParamSpec = type { float, float }
%struct.ActivationParamSpec = type { i32, [4 x float] }

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z15convolution_cpu10TensorDescPvS_PKv20ConvolutionParamSpec27ConvolutionForwardAlgorithmS_S0_S_S2_jS0_S_S0_19ActivationParamSpec4Arch(ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %2, ptr nocapture noundef readnone %3, ptr nocapture noundef readnone byval(%struct.ConvolutionParamSpec) align 8 %4, i32 noundef %5, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %6, ptr nocapture noundef readnone %7, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %8, ptr nocapture noundef readnone %9, i32 noundef %10, ptr noundef %11, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %12, ptr nocapture noundef readnone %13, ptr nocapture noundef readnone byval(%struct.ActivationParamSpec) align 8 %14, i32 noundef %15) local_unnamed_addr #0 {
  %17 = alloca %struct.TensorDesc, align 8
  %18 = getelementptr inbounds i8, ptr %0, i64 4
  %19 = load i32, ptr %18, align 4, !tbaa !5
  %20 = icmp eq i32 %19, 24
  br i1 %20, label %21, label %24

21:                                               ; preds = %16
  %.sroa.0.0.copyload = load i32, ptr %0, align 8, !tbaa !12
  %.sroa.5.0..sroa_idx = getelementptr inbounds i8, ptr %0, i64 8
  %.sroa.5.0..sroa_idx4 = getelementptr inbounds i8, ptr %17, i64 8
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(84) %.sroa.5.0..sroa_idx4, ptr noundef nonnull align 8 dereferenceable(84) %.sroa.5.0..sroa_idx, i64 84, i1 false)
  store i32 %.sroa.0.0.copyload, ptr %17, align 8, !tbaa !12
  %.sroa.4.0..sroa_idx2 = getelementptr inbounds i8, ptr %17, i64 4
  store i32 0, ptr %.sroa.4.0..sroa_idx2, align 4, !tbaa !13
  %22 = tail call noundef i32 @_Z15transformToNCHW10TensorDescPKvS_Pv(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %0, ptr noundef %1, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %17, ptr noundef %11)
  %23 = tail call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %0)
  br label %24

24:                                               ; preds = %21, %16
  ret i32 51
}

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

declare noundef i32 @_Z15transformToNCHW10TensorDescPKvS_Pv(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef) local_unnamed_addr #2

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #3

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !10, i64 4}
!6 = !{!"_ZTS10TensorDesc", !7, i64 0, !10, i64 4, !11, i64 8, !8, i64 12}
!7 = !{!"_ZTS8DataType", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!"_ZTS10DataFormat", !8, i64 0}
!11 = !{!"int", !8, i64 0}
!12 = !{!7, !7, i64 0}
!13 = !{!10, !10, i64 0}


; Effective O3 passes: CorrelatedValuePropagationPass,DSEPass,EarlyCSEPass,GlobalOptPass,InferAlignmentPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass