; LLVM IR from huawei-noah/bolt :: compute/tensor/src/cpu (gat)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ActivationParamSpec = type { i32, [4 x float] }
%struct.GATParamSpec = type { i32, %struct.ActivationParamSpec }

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10preprocess10TensorDescS_PvS0_S0_S0_S0_19ActivationParamSpecS0_S_S0_4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef byval(%struct.ActivationParamSpec) align 8, ptr noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, i32 noundef) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) #3

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z7gat_cpu10TensorDescS_S_PvS0_S0_S0_S0_12GATParamSpecS0_S_S0_4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %0, ptr noundef byval(%struct.TensorDesc) align 8 %1, ptr noundef byval(%struct.TensorDesc) align 8 %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, ptr noundef byval(%struct.GATParamSpec) align 8 %8, ptr noundef %9, ptr noundef byval(%struct.TensorDesc) align 8 %10, ptr noundef %11, i32 noundef %12) #0 {
  %14 = alloca ptr, align 8
  %15 = alloca ptr, align 8
  %16 = alloca ptr, align 8
  %17 = alloca ptr, align 8
  %18 = alloca ptr, align 8
  %19 = alloca ptr, align 8
  %20 = alloca ptr, align 8
  %21 = alloca i32, align 4
  %22 = alloca ptr, align 8
  %23 = alloca ptr, align 8
  %24 = alloca %struct.TensorDesc, align 8
  %25 = alloca %struct.TensorDesc, align 8
  %26 = alloca %struct.TensorDesc, align 8
  %27 = alloca %struct.TensorDesc, align 8
  %28 = alloca %struct.ActivationParamSpec, align 8
  %29 = alloca %struct.TensorDesc, align 8
  %30 = alloca i32, align 4
  %31 = alloca i32, align 4
  %32 = alloca i32, align 4
  %33 = alloca i32, align 4
  %34 = alloca i32, align 4
  store ptr %3, ptr %14, align 8, !tbaa !5
  store ptr %4, ptr %15, align 8, !tbaa !5
  store ptr %5, ptr %16, align 8, !tbaa !5
  store ptr %6, ptr %17, align 8, !tbaa !5
  store ptr %7, ptr %18, align 8, !tbaa !5
  store ptr %9, ptr %19, align 8, !tbaa !5
  store ptr %11, ptr %20, align 8, !tbaa !5
  store i32 %12, ptr %21, align 4, !tbaa !9
  call void @llvm.lifetime.start.p0(i64 8, ptr %22) #4
  %35 = load ptr, ptr %19, align 8, !tbaa !5
  store ptr %35, ptr %22, align 8, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 8, ptr %23) #4
  %36 = load ptr, ptr %19, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %24, ptr align 8 %2, i64 92, i1 false), !tbaa.struct !11
  %37 = call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8 %24)
  %38 = zext i32 %37 to i64
  %39 = getelementptr inbounds i8, ptr %36, i64 %38
  store ptr %39, ptr %23, align 8, !tbaa !5
  %40 = load ptr, ptr %23, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %25, ptr align 8 %2, i64 92, i1 false), !tbaa.struct !11
  %41 = call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8 %25)
  %42 = zext i32 %41 to i64
  %43 = getelementptr inbounds i8, ptr %40, i64 %42
  store ptr %43, ptr %19, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %26, ptr align 8 %0, i64 92, i1 false), !tbaa.struct !11
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %27, ptr align 8 %1, i64 92, i1 false), !tbaa.struct !11
  %44 = load ptr, ptr %14, align 8, !tbaa !5
  %45 = load ptr, ptr %15, align 8, !tbaa !5
  %46 = load ptr, ptr %16, align 8, !tbaa !5
  %47 = load ptr, ptr %17, align 8, !tbaa !5
  %48 = load ptr, ptr %18, align 8, !tbaa !5
  %49 = getelementptr inbounds %struct.GATParamSpec, ptr %8, i32 0, i32 1
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %28, ptr align 4 %49, i64 20, i1 false), !tbaa.struct !19
  %50 = load ptr, ptr %19, align 8, !tbaa !5
  call void @llvm.memcpy.p0.p0.i64(ptr align 4 %29, ptr align 8 %2, i64 92, i1 false), !tbaa.struct !11
  %51 = load ptr, ptr %22, align 8, !tbaa !5
  %52 = load i32, ptr %21, align 4, !tbaa !9
  call void @_Z10preprocess10TensorDescS_PvS0_S0_S0_S0_19ActivationParamSpecS0_S_S0_4Arch(ptr noundef byval(%struct.TensorDesc) align 8 %26, ptr noundef byval(%struct.TensorDesc) align 8 %27, ptr noundef %44, ptr noundef %45, ptr noundef %46, ptr noundef %47, ptr noundef %48, ptr noundef byval(%struct.ActivationParamSpec) align 8 %28, ptr noundef %50, ptr noundef byval(%struct.TensorDesc) align 8 %29, ptr noundef %51, i32 noundef %52)
  call void @llvm.lifetime.start.p0(i64 4, ptr %30) #4
  %53 = getelementptr inbounds %struct.GATParamSpec, ptr %8, i32 0, i32 0
  %54 = load i32, ptr %53, align 8, !tbaa !22
  store i32 %54, ptr %30, align 4, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 4, ptr %31) #4
  %55 = getelementptr inbounds %struct.TensorDesc, ptr %0, i32 0, i32 3
  %56 = getelementptr inbounds [20 x i32], ptr %55, i64 0, i64 1
  %57 = load i32, ptr %56, align 4, !tbaa !16
  store i32 %57, ptr %31, align 4, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 4, ptr %32) #4
  %58 = getelementptr inbounds %struct.TensorDesc, ptr %2, i32 0, i32 3
  %59 = getelementptr inbounds [20 x i32], ptr %58, i64 0, i64 1
  %60 = load i32, ptr %59, align 4, !tbaa !16
  store i32 %60, ptr %32, align 4, !tbaa !16
  call void @llvm.lifetime.start.p0(i64 4, ptr %33) #4
  store i32 0, ptr %33, align 4, !tbaa !25
  call void @llvm.lifetime.start.p0(i64 4, ptr %34) #4
  %61 = getelementptr inbounds %struct.TensorDesc, ptr %10, i32 0, i32 0
  %62 = load i32, ptr %61, align 8, !tbaa !27
  store i32 %62, ptr %34, align 4, !tbaa !12
  %63 = load i32, ptr %34, align 4, !tbaa !12
  switch i32 %63, label %64 [
  ]

64:                                               ; preds = %13
  store i32 51, ptr %33, align 4, !tbaa !25
  br label %65

65:                                               ; preds = %64
  %66 = load i32, ptr %33, align 4, !tbaa !25
  call void @llvm.lifetime.end.p0(i64 4, ptr %34) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %33) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %32) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %31) #4
  call void @llvm.lifetime.end.p0(i64 4, ptr %30) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %23) #4
  call void @llvm.lifetime.end.p0(i64 8, ptr %22) #4
  ret i32 %66
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"_ZTS4Arch", !7, i64 0}
!11 = !{i64 0, i64 4, !12, i64 4, i64 4, !14, i64 8, i64 4, !16, i64 12, i64 80, !18}
!12 = !{!13, !13, i64 0}
!13 = !{!"_ZTS8DataType", !7, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"_ZTS10DataFormat", !7, i64 0}
!16 = !{!17, !17, i64 0}
!17 = !{!"int", !7, i64 0}
!18 = !{!7, !7, i64 0}
!19 = !{i64 0, i64 4, !20, i64 4, i64 16, !18}
!20 = !{!21, !21, i64 0}
!21 = !{!"_ZTS14ActivationMode", !7, i64 0}
!22 = !{!23, !17, i64 0}
!23 = !{!"_ZTS12GATParamSpec", !17, i64 0, !24, i64 4}
!24 = !{!"_ZTS19ActivationParamSpec", !21, i64 0, !7, i64 4}
!25 = !{!26, !26, i64 0}
!26 = !{!"_ZTS2EE", !7, i64 0}
!27 = !{!28, !13, i64 0}
!28 = !{!"_ZTS10TensorDesc", !13, i64 0, !15, i64 4, !17, i64 8, !7, i64 12}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.TensorDesc = type { i32, i32, i32, [20 x i32] }
%struct.ActivationParamSpec = type { i32, [4 x float] }
%struct.GATParamSpec = type { i32, %struct.ActivationParamSpec }

; Function Attrs: mustprogress uwtable
declare dso_local void @_Z10preprocess10TensorDescS_PvS0_S0_S0_S0_19ActivationParamSpecS0_S_S0_4Arch(ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef, ptr noundef byval(%struct.ActivationParamSpec) align 8, ptr noundef, ptr noundef byval(%struct.TensorDesc) align 8, ptr noundef, i32 noundef) local_unnamed_addr #0

; Function Attrs: mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1

; Function Attrs: inlinehint mustprogress uwtable
declare dso_local noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef byval(%struct.TensorDesc) align 8) local_unnamed_addr #2

; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @_Z7gat_cpu10TensorDescS_S_PvS0_S0_S0_S0_12GATParamSpecS0_S_S0_4Arch(ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %0, ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %1, ptr nocapture noundef readonly byval(%struct.TensorDesc) align 8 %2, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, ptr nocapture noundef readonly byval(%struct.GATParamSpec) align 8 %8, ptr noundef %9, ptr nocapture noundef readnone byval(%struct.TensorDesc) align 8 %10, ptr nocapture noundef readnone %11, i32 noundef %12) local_unnamed_addr #0 {
  %14 = alloca %struct.ActivationParamSpec, align 8
  %15 = tail call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %2)
  %16 = zext i32 %15 to i64
  %17 = getelementptr inbounds i8, ptr %9, i64 %16
  %18 = tail call noundef i32 @_Z14tensorNumBytes10TensorDesc(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %2)
  %19 = zext i32 %18 to i64
  %20 = getelementptr inbounds i8, ptr %17, i64 %19
  %21 = getelementptr inbounds i8, ptr %8, i64 4
  call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 8 dereferenceable(20) %14, ptr noundef nonnull align 4 dereferenceable(20) %21, i64 20, i1 false), !tbaa.struct !5
  tail call void @_Z10preprocess10TensorDescS_PvS0_S0_S0_S0_19ActivationParamSpecS0_S_S0_4Arch(ptr noundef nonnull byval(%struct.TensorDesc) align 8 %0, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %1, ptr noundef %3, ptr noundef %4, ptr noundef %5, ptr noundef %6, ptr noundef %7, ptr noundef nonnull byval(%struct.ActivationParamSpec) align 8 %14, ptr noundef %20, ptr noundef nonnull byval(%struct.TensorDesc) align 8 %2, ptr noundef %9, i32 noundef %12)
  ret i32 51
}

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { inlinehint mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{i64 0, i64 4, !6, i64 4, i64 16, !10}
!6 = !{!7, !7, i64 0}
!7 = !{!"_ZTS14ActivationMode", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C++ TBAA"}
!10 = !{!8, !8, i64 0}


; Effective O3 passes: DSEPass,EarlyCSEPass,GlobalOptPass,InferFunctionAttrsPass,InstCombinePass,MemCpyOptPass,PostOrderFunctionAttrsPass,SROAPass,SimplifyCFGPass,TailCallElimPass