; LLVM IR from upupming/algorithm :: AdvancedLevel_C++/1043. Is It a Binary Search Tree (25).ll (Z7getpostii)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@isMirror = external dso_local global i8, align 1
@pre = external dso_local global %"class.std::vector", align 8
@post = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_Z7getpostii(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i32 %0, ptr %3, align 4, !tbaa !5
  store i32 %1, ptr %4, align 4, !tbaa !5
  %8 = load i32, ptr %3, align 4, !tbaa !5
  %9 = load i32, ptr %4, align 4, !tbaa !5
  %10 = icmp sgt i32 %8, %9
  br i1 %10, label %11, label %12

11:                                               ; preds = %2
  br label %117

12:                                               ; preds = %2
  call void @llvm.lifetime.start.p0(i64 4, ptr %5) #3
  %13 = load i32, ptr %3, align 4, !tbaa !5
  %14 = add nsw i32 %13, 1
  store i32 %14, ptr %5, align 4, !tbaa !5
  call void @llvm.lifetime.start.p0(i64 4, ptr %6) #3
  %15 = load i32, ptr %4, align 4, !tbaa !5
  store i32 %15, ptr %6, align 4, !tbaa !5
  %16 = load i8, ptr @isMirror, align 1, !tbaa !9, !range !11, !noundef !12
  %17 = trunc i8 %16 to i1
  br i1 %17, label %59, label %18

18:                                               ; preds = %12
  br label %19

19:                                               ; preds = %35, %18
  %20 = load i32, ptr %5, align 4, !tbaa !5
  %21 = load i32, ptr %4, align 4, !tbaa !5
  %22 = icmp sle i32 %20, %21
  br i1 %22, label %23, label %33

23:                                               ; preds = %19
  %24 = load i32, ptr %3, align 4, !tbaa !5
  %25 = sext i32 %24 to i64
  %26 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %25) #3
  %27 = load i32, ptr %26, align 4, !tbaa !5
  %28 = load i32, ptr %5, align 4, !tbaa !5
  %29 = sext i32 %28 to i64
  %30 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %29) #3
  %31 = load i32, ptr %30, align 4, !tbaa !5
  %32 = icmp sgt i32 %27, %31
  br label %33

33:                                               ; preds = %23, %19
  %34 = phi i1 [ false, %19 ], [ %32, %23 ]
  br i1 %34, label %35, label %38

35:                                               ; preds = %33
  %36 = load i32, ptr %5, align 4, !tbaa !5
  %37 = add nsw i32 %36, 1
  store i32 %37, ptr %5, align 4, !tbaa !5
  br label %19, !llvm.loop !13

38:                                               ; preds = %33
  br label %39

39:                                               ; preds = %55, %38
  %40 = load i32, ptr %6, align 4, !tbaa !5
  %41 = load i32, ptr %3, align 4, !tbaa !5
  %42 = icmp sgt i32 %40, %41
  br i1 %42, label %43, label %53

43:                                               ; preds = %39
  %44 = load i32, ptr %3, align 4, !tbaa !5
  %45 = sext i32 %44 to i64
  %46 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %45) #3
  %47 = load i32, ptr %46, align 4, !tbaa !5
  %48 = load i32, ptr %6, align 4, !tbaa !5
  %49 = sext i32 %48 to i64
  %50 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %49) #3
  %51 = load i32, ptr %50, align 4, !tbaa !5
  %52 = icmp sle i32 %47, %51
  br label %53

53:                                               ; preds = %43, %39
  %54 = phi i1 [ false, %39 ], [ %52, %43 ]
  br i1 %54, label %55, label %58

55:                                               ; preds = %53
  %56 = load i32, ptr %6, align 4, !tbaa !5
  %57 = add nsw i32 %56, -1
  store i32 %57, ptr %6, align 4, !tbaa !5
  br label %39, !llvm.loop !15

58:                                               ; preds = %53
  br label %100

59:                                               ; preds = %12
  br label %60

60:                                               ; preds = %76, %59
  %61 = load i32, ptr %5, align 4, !tbaa !5
  %62 = load i32, ptr %4, align 4, !tbaa !5
  %63 = icmp sle i32 %61, %62
  br i1 %63, label %64, label %74

64:                                               ; preds = %60
  %65 = load i32, ptr %3, align 4, !tbaa !5
  %66 = sext i32 %65 to i64
  %67 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %66) #3
  %68 = load i32, ptr %67, align 4, !tbaa !5
  %69 = load i32, ptr %5, align 4, !tbaa !5
  %70 = sext i32 %69 to i64
  %71 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %70) #3
  %72 = load i32, ptr %71, align 4, !tbaa !5
  %73 = icmp sle i32 %68, %72
  br label %74

74:                                               ; preds = %64, %60
  %75 = phi i1 [ false, %60 ], [ %73, %64 ]
  br i1 %75, label %76, label %79

76:                                               ; preds = %74
  %77 = load i32, ptr %5, align 4, !tbaa !5
  %78 = add nsw i32 %77, 1
  store i32 %78, ptr %5, align 4, !tbaa !5
  br label %60, !llvm.loop !16

79:                                               ; preds = %74
  br label %80

80:                                               ; preds = %96, %79
  %81 = load i32, ptr %6, align 4, !tbaa !5
  %82 = load i32, ptr %3, align 4, !tbaa !5
  %83 = icmp sgt i32 %81, %82
  br i1 %83, label %84, label %94

84:                                               ; preds = %80
  %85 = load i32, ptr %3, align 4, !tbaa !5
  %86 = sext i32 %85 to i64
  %87 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %86) #3
  %88 = load i32, ptr %87, align 4, !tbaa !5
  %89 = load i32, ptr %6, align 4, !tbaa !5
  %90 = sext i32 %89 to i64
  %91 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %90) #3
  %92 = load i32, ptr %91, align 4, !tbaa !5
  %93 = icmp sgt i32 %88, %92
  br label %94

94:                                               ; preds = %84, %80
  %95 = phi i1 [ false, %80 ], [ %93, %84 ]
  br i1 %95, label %96, label %99

96:                                               ; preds = %94
  %97 = load i32, ptr %6, align 4, !tbaa !5
  %98 = add nsw i32 %97, -1
  store i32 %98, ptr %6, align 4, !tbaa !5
  br label %80, !llvm.loop !17

99:                                               ; preds = %94
  br label %100

100:                                              ; preds = %99, %58
  %101 = load i32, ptr %5, align 4, !tbaa !5
  %102 = load i32, ptr %6, align 4, !tbaa !5
  %103 = sub nsw i32 %101, %102
  %104 = icmp ne i32 %103, 1
  br i1 %104, label %105, label %106

105:                                              ; preds = %100
  store i32 1, ptr %7, align 4
  br label %115

106:                                              ; preds = %100
  %107 = load i32, ptr %3, align 4, !tbaa !5
  %108 = add nsw i32 %107, 1
  %109 = load i32, ptr %6, align 4, !tbaa !5
  call void @_Z7getpostii(i32 noundef %108, i32 noundef %109)
  %110 = load i32, ptr %5, align 4, !tbaa !5
  %111 = load i32, ptr %4, align 4, !tbaa !5
  call void @_Z7getpostii(i32 noundef %110, i32 noundef %111)
  %112 = load i32, ptr %3, align 4, !tbaa !5
  %113 = sext i32 %112 to i64
  %114 = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %113) #3
  call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @post, ptr noundef nonnull align 4 dereferenceable(4) %114)
  store i32 0, ptr %7, align 4
  br label %115

115:                                              ; preds = %106, %105
  call void @llvm.lifetime.end.p0(i64 4, ptr %6) #3
  call void @llvm.lifetime.end.p0(i64 4, ptr %5) #3
  %116 = load i32, ptr %7, align 4
  switch i32 %116, label %118 [
    i32 0, label %117
    i32 1, label %117
  ]

117:                                              ; preds = %115, %115, %11
  ret void

118:                                              ; preds = %115
  unreachable
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #2 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{i8 0, i8 2}
!12 = !{}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }

@isMirror = external dso_local local_unnamed_addr global i8, align 1
@pre = external dso_local global %"class.std::vector", align 8
@post = external dso_local global %"class.std::vector", align 8

; Function Attrs: mustprogress uwtable
define dso_local void @_Z7getpostii(i32 noundef %0, i32 noundef %1) local_unnamed_addr #0 {
  %3 = icmp sgt i32 %0, %1
  br i1 %3, label %common.ret108, label %4

4:                                                ; preds = %2
  %5 = add nsw i32 %0, 1
  %6 = load i8, ptr @isMirror, align 1, !tbaa !5, !range !9, !noundef !10
  %7 = trunc nuw i8 %6 to i1
  %8 = sext i32 %0 to i64
  %.not4357.not = icmp slt i32 %0, %1
  br i1 %7, label %.preheader, label %.preheader47

.preheader47:                                     ; preds = %4
  br i1 %.not4357.not, label %.lr.ph.preheader, label %.critedge2

.lr.ph.preheader:                                 ; preds = %.preheader47
  %9 = add nsw i64 %8, 1
  %10 = add i32 %1, 1
  br label %.lr.ph

.preheader:                                       ; preds = %4
  br i1 %.not4357.not, label %.lr.ph59.preheader, label %.critedge2

.lr.ph59.preheader:                               ; preds = %.preheader
  %11 = add nsw i64 %8, 1
  %12 = add i32 %1, 1
  br label %.lr.ph59

.lr.ph:                                           ; preds = %.lr.ph.preheader, %18
  %indvars.iv = phi i64 [ %9, %.lr.ph.preheader ], [ %indvars.iv.next, %18 ]
  %13 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %8) #2
  %14 = load i32, ptr %13, align 4, !tbaa !11
  %15 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %indvars.iv) #2
  %16 = load i32, ptr %15, align 4, !tbaa !11
  %17 = icmp sgt i32 %14, %16
  br i1 %17, label %18, label %.critedge.split.loop.exit

18:                                               ; preds = %.lr.ph
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond.not = icmp eq i32 %10, %lftr.wideiv
  br i1 %exitcond.not, label %.critedge, label %.lr.ph, !llvm.loop !13

.critedge.split.loop.exit:                        ; preds = %.lr.ph
  %19 = trunc nsw i64 %indvars.iv to i32
  br label %.critedge

.critedge:                                        ; preds = %18, %.critedge.split.loop.exit
  %.037.lcssa = phi i32 [ %19, %.critedge.split.loop.exit ], [ %10, %18 ]
  br i1 %.not4357.not, label %.lr.ph53.preheader, label %.critedge2

.lr.ph53.preheader:                               ; preds = %.critedge
  %20 = sext i32 %1 to i64
  br label %.lr.ph53

.lr.ph53:                                         ; preds = %.lr.ph53.preheader, %25
  %indvars.iv71 = phi i64 [ %20, %.lr.ph53.preheader ], [ %indvars.iv.next72, %25 ]
  %21 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %8) #2
  %22 = load i32, ptr %21, align 4, !tbaa !11
  %23 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %indvars.iv71) #2
  %24 = load i32, ptr %23, align 4, !tbaa !11
  %.not42 = icmp sgt i32 %22, %24
  br i1 %.not42, label %.critedge2.loopexit84.split.loop.exit, label %25

25:                                               ; preds = %.lr.ph53
  %indvars.iv.next72 = add nsw i64 %indvars.iv71, -1
  %26 = icmp sgt i64 %indvars.iv.next72, %8
  br i1 %26, label %.lr.ph53, label %.critedge2, !llvm.loop !15

.lr.ph59:                                         ; preds = %.lr.ph59.preheader, %31
  %indvars.iv74 = phi i64 [ %11, %.lr.ph59.preheader ], [ %indvars.iv.next75, %31 ]
  %27 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %8) #2
  %28 = load i32, ptr %27, align 4, !tbaa !11
  %29 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %indvars.iv74) #2
  %30 = load i32, ptr %29, align 4, !tbaa !11
  %.not44 = icmp sgt i32 %28, %30
  br i1 %.not44, label %.critedge4.split.loop.exit, label %31

31:                                               ; preds = %.lr.ph59
  %indvars.iv.next75 = add nsw i64 %indvars.iv74, 1
  %lftr.wideiv77 = trunc i64 %indvars.iv.next75 to i32
  %exitcond78.not = icmp eq i32 %12, %lftr.wideiv77
  br i1 %exitcond78.not, label %.critedge4, label %.lr.ph59, !llvm.loop !16

.critedge4.split.loop.exit:                       ; preds = %.lr.ph59
  %32 = trunc nsw i64 %indvars.iv74 to i32
  br label %.critedge4

.critedge4:                                       ; preds = %31, %.critedge4.split.loop.exit
  %.138.lcssa = phi i32 [ %32, %.critedge4.split.loop.exit ], [ %12, %31 ]
  br i1 %.not4357.not, label %.lr.ph64.preheader, label %.critedge2

.lr.ph64.preheader:                               ; preds = %.critedge4
  %33 = sext i32 %1 to i64
  br label %.lr.ph64

.lr.ph64:                                         ; preds = %.lr.ph64.preheader, %39
  %indvars.iv79 = phi i64 [ %33, %.lr.ph64.preheader ], [ %indvars.iv.next80, %39 ]
  %34 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %8) #2
  %35 = load i32, ptr %34, align 4, !tbaa !11
  %36 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %indvars.iv79) #2
  %37 = load i32, ptr %36, align 4, !tbaa !11
  %38 = icmp sgt i32 %35, %37
  br i1 %38, label %39, label %.critedge2.loopexit.split.loop.exit

39:                                               ; preds = %.lr.ph64
  %indvars.iv.next80 = add nsw i64 %indvars.iv79, -1
  %40 = icmp sgt i64 %indvars.iv.next80, %8
  br i1 %40, label %.lr.ph64, label %.critedge2, !llvm.loop !17

.critedge2.loopexit.split.loop.exit:              ; preds = %.lr.ph64
  %41 = trunc nsw i64 %indvars.iv79 to i32
  br label %.critedge2

.critedge2.loopexit84.split.loop.exit:            ; preds = %.lr.ph53
  %42 = trunc nsw i64 %indvars.iv71 to i32
  br label %.critedge2

.critedge2:                                       ; preds = %25, %39, %.critedge2.loopexit84.split.loop.exit, %.critedge2.loopexit.split.loop.exit, %.preheader, %.preheader47, %.critedge, %.critedge4
  %.239 = phi i32 [ %.138.lcssa, %.critedge4 ], [ %.037.lcssa, %.critedge ], [ %5, %.preheader47 ], [ %5, %.preheader ], [ %.138.lcssa, %.critedge2.loopexit.split.loop.exit ], [ %.037.lcssa, %.critedge2.loopexit84.split.loop.exit ], [ %.138.lcssa, %39 ], [ %.037.lcssa, %25 ]
  %.2 = phi i32 [ %1, %.critedge4 ], [ %1, %.critedge ], [ %1, %.preheader47 ], [ %1, %.preheader ], [ %41, %.critedge2.loopexit.split.loop.exit ], [ %42, %.critedge2.loopexit84.split.loop.exit ], [ %0, %39 ], [ %0, %25 ]
  %43 = sub nsw i32 %.239, %.2
  %.not45 = icmp eq i32 %43, 1
  br i1 %.not45, label %44, label %common.ret108

common.ret108:                                    ; preds = %.critedge2, %2, %44
  ret void

44:                                               ; preds = %.critedge2
  tail call void @_Z7getpostii(i32 noundef %5, i32 noundef %.2)
  tail call void @_Z7getpostii(i32 noundef %.239, i32 noundef %1)
  %45 = sext i32 %0 to i64
  %46 = tail call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) @pre, i64 noundef %45) #2
  tail call void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24) @post, ptr noundef nonnull align 4 dereferenceable(4) %46)
  br label %common.ret108
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #1 align 2

; Function Attrs: mustprogress uwtable
declare dso_local void @_ZNSt6vectorIiSaIiEE9push_backERKi(ptr noundef nonnull align 8 dereferenceable(24), ptr noundef nonnull align 4 dereferenceable(4)) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"bool", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{i8 0, i8 2}
!10 = !{}
!11 = !{!12, !12, i64 0}
!12 = !{!"int", !7, i64 0}
!13 = distinct !{!13, !14}
!14 = !{!"llvm.loop.mustprogress"}
!15 = distinct !{!15, !14}
!16 = distinct !{!16, !14}
!17 = distinct !{!17, !14}


; Effective O3 passes: EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,IndVarSimplifyPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,SROAPass,SimplifyCFGPass,TailCallElimPass