; LLVM IR from AdaptiveCpp/AdaptiveCpp :: src/runtime/pcuda (pcuda_device_topology)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"struct.hipsycl::rt::pcuda::device_topology::platform" = type { i32, %"class.std::vector.41" }
%"class.std::vector.41" = type { %"struct.std::_Vector_base.42" }
%"struct.std::_Vector_base.42" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl" = type { %"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl_data" }
%"struct.std::_Vector_base<hipsycl::rt::pcuda::device_topology::device, std::allocator<hipsycl::rt::pcuda::device_topology::device>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef) #1 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology10get_deviceEiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) #1 align 2 {
  %5 = alloca ptr, align 8
  %6 = alloca ptr, align 8
  %7 = alloca i32, align 4
  %8 = alloca i32, align 4
  %9 = alloca i32, align 4
  %10 = alloca ptr, align 8
  %11 = alloca i32, align 4
  store ptr %0, ptr %6, align 8, !tbaa !5
  store i32 %1, ptr %7, align 4, !tbaa !9
  store i32 %2, ptr %8, align 4, !tbaa !9
  store i32 %3, ptr %9, align 4, !tbaa !9
  %12 = load ptr, ptr %6, align 8
  call void @llvm.lifetime.start.p0(i64 8, ptr %10) #2
  %13 = load i32, ptr %7, align 4, !tbaa !9
  %14 = load i32, ptr %8, align 4, !tbaa !9
  %15 = call noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24) %12, i32 noundef %13, i32 noundef %14)
  store ptr %15, ptr %10, align 8, !tbaa !5
  %16 = load ptr, ptr %10, align 8, !tbaa !5
  %17 = icmp ne ptr %16, null
  br i1 %17, label %19, label %18

18:                                               ; preds = %4
  store ptr null, ptr %5, align 8
  store i32 1, ptr %11, align 4
  br label %36

19:                                               ; preds = %4
  %20 = load i32, ptr %9, align 4, !tbaa !9
  %21 = icmp slt i32 %20, 0
  br i1 %21, label %29, label %22

22:                                               ; preds = %19
  %23 = load i32, ptr %9, align 4, !tbaa !9
  %24 = sext i32 %23 to i64
  %25 = load ptr, ptr %10, align 8, !tbaa !5
  %26 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::platform", ptr %25, i32 0, i32 1
  %27 = call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %26) #2
  %28 = icmp uge i64 %24, %27
  br i1 %28, label %29, label %30

29:                                               ; preds = %22, %19
  store ptr null, ptr %5, align 8
  store i32 1, ptr %11, align 4
  br label %36

30:                                               ; preds = %22
  %31 = load ptr, ptr %10, align 8, !tbaa !5
  %32 = getelementptr inbounds %"struct.hipsycl::rt::pcuda::device_topology::platform", ptr %31, i32 0, i32 1
  %33 = load i32, ptr %9, align 4, !tbaa !9
  %34 = sext i32 %33 to i64
  %35 = call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %32, i64 noundef %34) #2
  store ptr %35, ptr %5, align 8
  store i32 1, ptr %11, align 4
  br label %36

36:                                               ; preds = %30, %29, %18
  call void @llvm.lifetime.end.p0(i64 8, ptr %10) #2
  %37 = load ptr, ptr %5, align 8
  ret ptr %37
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #1 align 2

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"int", !7, i64 0}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24), i32 noundef, i32 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
define dso_local noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology10get_deviceEiii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 align 2 {
  %5 = tail call noundef ptr @_ZNK7hipsycl2rt5pcuda15device_topology12get_platformEii(ptr noundef nonnull align 8 dereferenceable(24) %0, i32 noundef %1, i32 noundef %2)
  %.not = icmp eq ptr %5, null
  %6 = icmp slt i32 %3, 0
  %or.cond = or i1 %6, %.not
  br i1 %or.cond, label %13, label %7

7:                                                ; preds = %4
  %8 = zext nneg i32 %3 to i64
  %9 = getelementptr inbounds i8, ptr %5, i64 8
  %10 = tail call noundef i64 @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %9) #1
  %.not12 = icmp ugt i64 %10, %8
  br i1 %.not12, label %11, label %13

11:                                               ; preds = %7
  %12 = tail call noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %9, i64 noundef %8) #1
  br label %13

13:                                               ; preds = %7, %4, %11
  %.0 = phi ptr [ %12, %11 ], [ null, %4 ], [ null, %7 ]
  ret ptr %.0
}

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(32) ptr @_ZNKSt6vectorIN7hipsycl2rt5pcuda15device_topology6deviceESaIS4_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}


; Effective O3 passes: EarlyCSEPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass