; LLVM IR from AF-GRILL/DISPluginForUnreal :: Source/ThirdParty/include/dis6 (EventReportReliablePdu)

; Unoptimized IR (clang -disable-llvm-passes):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%"class.DIS::EventReportReliablePdu" = type { %"class.DIS::SimulationManagementWithReliabilityFamilyPdu", i16, i32, i32, i32, %"class.std::vector", %"class.std::vector.0" }
%"class.DIS::SimulationManagementWithReliabilityFamilyPdu" = type { %"class.DIS::Pdu.base", [4 x i8], %"class.DIS::EntityID", %"class.DIS::EntityID" }
%"class.DIS::Pdu.base" = type <{ ptr, i8, i8, i8, i8, i32, i16, i16 }>
%"class.DIS::EntityID" = type <{ ptr, i16, i16, i16, [2 x i8] }>
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<DIS::FixedDatum, std::allocator<DIS::FixedDatum>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::FixedDatum, std::allocator<DIS::FixedDatum>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::FixedDatum, std::allocator<DIS::FixedDatum>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::FixedDatum, std::allocator<DIS::FixedDatum>>::_Vector_impl_data" = type { ptr, ptr, ptr }
%"class.std::vector.0" = type { %"struct.std::_Vector_base.1" }
%"struct.std::_Vector_base.1" = type { %"struct.std::_Vector_base<DIS::VariableDatum, std::allocator<DIS::VariableDatum>>::_Vector_impl" }
%"struct.std::_Vector_base<DIS::VariableDatum, std::allocator<DIS::VariableDatum>>::_Vector_impl" = type { %"struct.std::_Vector_base<DIS::VariableDatum, std::allocator<DIS::VariableDatum>>::_Vector_impl_data" }
%"struct.std::_Vector_base<DIS::VariableDatum, std::allocator<DIS::VariableDatum>>::_Vector_impl_data" = type { ptr, ptr, ptr }

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS22EventReportReliablePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) #2 align 2 {
  %3 = alloca ptr, align 8
  %4 = alloca ptr, align 8
  %5 = alloca i8, align 1
  %6 = alloca i64, align 8
  %7 = alloca i64, align 8
  store ptr %0, ptr %3, align 8, !tbaa !5
  store ptr %1, ptr %4, align 8, !tbaa !5
  %8 = load ptr, ptr %3, align 8
  call void @llvm.lifetime.start.p0(i64 1, ptr %5) #4
  store i8 1, ptr %5, align 1, !tbaa !9
  %9 = load ptr, ptr %4, align 8, !tbaa !5
  %10 = call noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %8, ptr noundef nonnull align 8 dereferenceable(56) %9)
  %11 = zext i1 %10 to i8
  store i8 %11, ptr %5, align 1, !tbaa !9
  %12 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 1
  %13 = load i16, ptr %12, align 8, !tbaa !11
  %14 = zext i16 %13 to i32
  %15 = load ptr, ptr %4, align 8, !tbaa !5
  %16 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %15, i32 0, i32 1
  %17 = load i16, ptr %16, align 8, !tbaa !11
  %18 = zext i16 %17 to i32
  %19 = icmp eq i32 %14, %18
  br i1 %19, label %21, label %20

20:                                               ; preds = %2
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %21

21:                                               ; preds = %20, %2
  %22 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 2
  %23 = load i32, ptr %22, align 4, !tbaa !26
  %24 = load ptr, ptr %4, align 8, !tbaa !5
  %25 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %24, i32 0, i32 2
  %26 = load i32, ptr %25, align 4, !tbaa !26
  %27 = icmp eq i32 %23, %26
  br i1 %27, label %29, label %28

28:                                               ; preds = %21
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %29

29:                                               ; preds = %28, %21
  call void @llvm.lifetime.start.p0(i64 8, ptr %6) #4
  store i64 0, ptr %6, align 8, !tbaa !27
  br label %30

30:                                               ; preds = %47, %29
  %31 = load i64, ptr %6, align 8, !tbaa !27
  %32 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 5
  %33 = call noundef i64 @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %32) #4
  %34 = icmp ult i64 %31, %33
  br i1 %34, label %36, label %35

35:                                               ; preds = %30
  call void @llvm.lifetime.end.p0(i64 8, ptr %6) #4
  br label %50

36:                                               ; preds = %30
  %37 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 5
  %38 = load i64, ptr %6, align 8, !tbaa !27
  %39 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %37, i64 noundef %38) #4
  %40 = load ptr, ptr %4, align 8, !tbaa !5
  %41 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %40, i32 0, i32 5
  %42 = load i64, ptr %6, align 8, !tbaa !27
  %43 = call noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %41, i64 noundef %42) #4
  %44 = call noundef zeroext i1 @_ZNK3DIS10FixedDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(16) %39, ptr noundef nonnull align 8 dereferenceable(16) %43)
  br i1 %44, label %46, label %45

45:                                               ; preds = %36
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %46

46:                                               ; preds = %45, %36
  br label %47

47:                                               ; preds = %46
  %48 = load i64, ptr %6, align 8, !tbaa !27
  %49 = add i64 %48, 1
  store i64 %49, ptr %6, align 8, !tbaa !27
  br label %30, !llvm.loop !29

50:                                               ; preds = %35
  call void @llvm.lifetime.start.p0(i64 8, ptr %7) #4
  store i64 0, ptr %7, align 8, !tbaa !27
  br label %51

51:                                               ; preds = %68, %50
  %52 = load i64, ptr %7, align 8, !tbaa !27
  %53 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 6
  %54 = call noundef i64 @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %53) #4
  %55 = icmp ult i64 %52, %54
  br i1 %55, label %57, label %56

56:                                               ; preds = %51
  call void @llvm.lifetime.end.p0(i64 8, ptr %7) #4
  br label %71

57:                                               ; preds = %51
  %58 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %8, i32 0, i32 6
  %59 = load i64, ptr %7, align 8, !tbaa !27
  %60 = call noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %58, i64 noundef %59) #4
  %61 = load ptr, ptr %4, align 8, !tbaa !5
  %62 = getelementptr inbounds %"class.DIS::EventReportReliablePdu", ptr %61, i32 0, i32 6
  %63 = load i64, ptr %7, align 8, !tbaa !27
  %64 = call noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %62, i64 noundef %63) #4
  %65 = call noundef zeroext i1 @_ZNK3DIS13VariableDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(44) %60, ptr noundef nonnull align 8 dereferenceable(44) %64)
  br i1 %65, label %67, label %66

66:                                               ; preds = %57
  store i8 0, ptr %5, align 1, !tbaa !9
  br label %67

67:                                               ; preds = %66, %57
  br label %68

68:                                               ; preds = %67
  %69 = load i64, ptr %7, align 8, !tbaa !27
  %70 = add i64 %69, 1
  store i64 %70, ptr %7, align 8, !tbaa !27
  br label %51, !llvm.loop !31

71:                                               ; preds = %56
  %72 = load i8, ptr %5, align 1, !tbaa !9, !range !32, !noundef !33
  %73 = trunc i8 %72 to i1
  call void @llvm.lifetime.end.p0(i64 1, ptr %5) #4
  ret i1 %73
}

declare noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef nonnull align 8 dereferenceable(56)) #3

declare noundef zeroext i1 @_ZNK3DIS10FixedDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) #3

declare noundef zeroext i1 @_ZNK3DIS13VariableDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(44), ptr noundef nonnull align 8 dereferenceable(44)) #3

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #4 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
!8 = !{!"Simple C++ TBAA"}
!9 = !{!10, !10, i64 0}
!10 = !{!"bool", !7, i64 0}
!11 = !{!12, !16, i64 56}
!12 = !{!"_ZTSN3DIS22EventReportReliablePduE", !13, i64 0, !16, i64 56, !15, i64 60, !15, i64 64, !15, i64 68, !18, i64 72, !22, i64 96}
!13 = !{!"_ZTSN3DIS44SimulationManagementWithReliabilityFamilyPduE", !14, i64 0, !17, i64 24, !17, i64 40}
!14 = !{!"_ZTSN3DIS3PduE", !7, i64 8, !7, i64 9, !7, i64 10, !7, i64 11, !15, i64 12, !16, i64 16, !16, i64 18}
!15 = !{!"int", !7, i64 0}
!16 = !{!"short", !7, i64 0}
!17 = !{!"_ZTSN3DIS8EntityIDE", !16, i64 8, !16, i64 10, !16, i64 12}
!18 = !{!"_ZTSSt6vectorIN3DIS10FixedDatumESaIS1_EE", !19, i64 0}
!19 = !{!"_ZTSSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSNSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE12_Vector_implE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!22 = !{!"_ZTSSt6vectorIN3DIS13VariableDatumESaIS1_EE", !23, i64 0}
!23 = !{!"_ZTSSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE", !24, i64 0}
!24 = !{!"_ZTSNSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE12_Vector_implE", !25, i64 0}
!25 = !{!"_ZTSNSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE17_Vector_impl_dataE", !6, i64 0, !6, i64 8, !6, i64 16}
!26 = !{!12, !15, i64 60}
!27 = !{!28, !28, i64 0}
!28 = !{!"long", !7, i64 0}
!29 = distinct !{!29, !30}
!30 = !{!"llvm.loop.mustprogress"}
!31 = distinct !{!31, !30}
!32 = !{i8 0, i8 2}
!33 = !{}


; Optimized IR (opt -passes='default<O3>'):
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef i64 @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24)) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress nounwind uwtable
declare dso_local noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24), i64 noundef) local_unnamed_addr #0 align 2

; Function Attrs: mustprogress uwtable
define dso_local noundef zeroext i1 @_ZNK3DIS22EventReportReliablePdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(120) %0, ptr noundef nonnull align 8 dereferenceable(120) %1) local_unnamed_addr #1 align 2 {
  %3 = tail call noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56) %0, ptr noundef nonnull align 8 dereferenceable(56) %1)
  %4 = getelementptr inbounds i8, ptr %0, i64 56
  %5 = load i16, ptr %4, align 8, !tbaa !5
  %6 = getelementptr inbounds i8, ptr %1, i64 56
  %7 = load i16, ptr %6, align 8, !tbaa !5
  %8 = icmp eq i16 %5, %7
  %narrow = and i1 %3, %8
  %9 = getelementptr inbounds i8, ptr %0, i64 60
  %10 = load i32, ptr %9, align 4, !tbaa !23
  %11 = getelementptr inbounds i8, ptr %1, i64 60
  %12 = load i32, ptr %11, align 4, !tbaa !23
  %13 = icmp eq i32 %10, %12
  %narrow18 = select i1 %13, i1 %narrow, i1 false
  %14 = getelementptr inbounds i8, ptr %0, i64 72
  %15 = tail call noundef i64 @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  %.not = icmp eq i64 %15, 0
  br i1 %.not, label %.preheader, label %.lr.ph

.lr.ph:                                           ; preds = %2
  %16 = getelementptr inbounds i8, ptr %1, i64 72
  br label %20

.preheader:                                       ; preds = %20, %2
  %.2.lcssa = phi i1 [ %narrow18, %2 ], [ %spec.select16, %20 ]
  %17 = getelementptr inbounds i8, ptr %0, i64 96
  %18 = tail call noundef i64 @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  %.not25 = icmp eq i64 %18, 0
  br i1 %.not25, label %._crit_edge, label %.lr.ph23

.lr.ph23:                                         ; preds = %.preheader
  %19 = getelementptr inbounds i8, ptr %1, i64 96
  br label %27

20:                                               ; preds = %.lr.ph, %20
  %.01420 = phi i64 [ 0, %.lr.ph ], [ %24, %20 ]
  %.219 = phi i1 [ %narrow18, %.lr.ph ], [ %spec.select16, %20 ]
  %21 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %14, i64 noundef %.01420) #3
  %22 = tail call noundef nonnull align 8 dereferenceable(16) ptr @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %16, i64 noundef %.01420) #3
  %23 = tail call noundef zeroext i1 @_ZNK3DIS10FixedDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(16) %21, ptr noundef nonnull align 8 dereferenceable(16) %22)
  %spec.select16 = select i1 %23, i1 %.219, i1 false
  %24 = add nuw i64 %.01420, 1
  %25 = tail call noundef i64 @_ZNKSt6vectorIN3DIS10FixedDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %14) #3
  %26 = icmp ult i64 %24, %25
  br i1 %26, label %20, label %.preheader, !llvm.loop !24

._crit_edge:                                      ; preds = %27, %.preheader
  %.4.lcssa = phi i1 [ %.2.lcssa, %.preheader ], [ %spec.select17, %27 ]
  ret i1 %.4.lcssa

27:                                               ; preds = %.lr.ph23, %27
  %.022 = phi i64 [ 0, %.lr.ph23 ], [ %31, %27 ]
  %.421 = phi i1 [ %.2.lcssa, %.lr.ph23 ], [ %spec.select17, %27 ]
  %28 = tail call noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %17, i64 noundef %.022) #3
  %29 = tail call noundef nonnull align 8 dereferenceable(44) ptr @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EEixEm(ptr noundef nonnull align 8 dereferenceable(24) %19, i64 noundef %.022) #3
  %30 = tail call noundef zeroext i1 @_ZNK3DIS13VariableDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(44) %28, ptr noundef nonnull align 8 dereferenceable(44) %29)
  %spec.select17 = select i1 %30, i1 %.421, i1 false
  %31 = add nuw i64 %.022, 1
  %32 = tail call noundef i64 @_ZNKSt6vectorIN3DIS13VariableDatumESaIS1_EE4sizeEv(ptr noundef nonnull align 8 dereferenceable(24) %17) #3
  %33 = icmp ult i64 %31, %32
  br i1 %33, label %27, label %._crit_edge, !llvm.loop !26
}

declare noundef zeroext i1 @_ZNK3DIS44SimulationManagementWithReliabilityFamilyPdueqERKS0_(ptr noundef nonnull align 8 dereferenceable(56), ptr noundef nonnull align 8 dereferenceable(56)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK3DIS10FixedDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(16), ptr noundef nonnull align 8 dereferenceable(16)) local_unnamed_addr #2

declare noundef zeroext i1 @_ZNK3DIS13VariableDatumeqERKS0_(ptr noundef nonnull align 8 dereferenceable(44), ptr noundef nonnull align 8 dereferenceable(44)) local_unnamed_addr #2

attributes #0 = { mustprogress nounwind uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 19.1.0 (git@github.com:llvm/llvm-project.git a4bf6cd7cfb1a1421ba92bca9d017b49936c55e4)"}
!5 = !{!6, !12, i64 56}
!6 = !{!"_ZTSN3DIS22EventReportReliablePduE", !7, i64 0, !12, i64 56, !11, i64 60, !11, i64 64, !11, i64 68, !14, i64 72, !19, i64 96}
!7 = !{!"_ZTSN3DIS44SimulationManagementWithReliabilityFamilyPduE", !8, i64 0, !13, i64 24, !13, i64 40}
!8 = !{!"_ZTSN3DIS3PduE", !9, i64 8, !9, i64 9, !9, i64 10, !9, i64 11, !11, i64 12, !12, i64 16, !12, i64 18}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C++ TBAA"}
!11 = !{!"int", !9, i64 0}
!12 = !{!"short", !9, i64 0}
!13 = !{!"_ZTSN3DIS8EntityIDE", !12, i64 8, !12, i64 10, !12, i64 12}
!14 = !{!"_ZTSSt6vectorIN3DIS10FixedDatumESaIS1_EE", !15, i64 0}
!15 = !{!"_ZTSSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE", !16, i64 0}
!16 = !{!"_ZTSNSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE12_Vector_implE", !17, i64 0}
!17 = !{!"_ZTSNSt12_Vector_baseIN3DIS10FixedDatumESaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!18 = !{!"any pointer", !9, i64 0}
!19 = !{!"_ZTSSt6vectorIN3DIS13VariableDatumESaIS1_EE", !20, i64 0}
!20 = !{!"_ZTSSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE", !21, i64 0}
!21 = !{!"_ZTSNSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE12_Vector_implE", !22, i64 0}
!22 = !{!"_ZTSNSt12_Vector_baseIN3DIS13VariableDatumESaIS1_EE17_Vector_impl_dataE", !18, i64 0, !18, i64 8, !18, i64 16}
!23 = !{!6, !11, i64 60}
!24 = distinct !{!24, !25}
!25 = !{!"llvm.loop.mustprogress"}
!26 = distinct !{!26, !25}


; Effective O3 passes: AggressiveInstCombinePass,CorrelatedValuePropagationPass,EarlyCSEPass,GVNPass,GlobalOptPass,IPSCCPPass,InferFunctionAttrsPass,InstCombinePass,InstSimplifyPass,JumpThreadingPass,LCSSAPass,LICMPass,LoopRotatePass,LoopSimplifyPass,LoopUnrollPass,ReassociatePass,SROAPass,SimplifyCFGPass,TailCallElimPass