Task: Four bit adder







Python: 

from myhdl import *



@block
def NOTgate( a,  q ):   
   
   @always_comb   
   def NOTgateLogic():
      q.next = not a

   return NOTgateLogic   


@block
def ANDgate( a, b,  q ):
   
   @always_comb 
   def ANDgateLogic():
      q.next = a and b

   return ANDgateLogic


@block
def ORgate( a, b,  q ):
      
   @always_comb  
   def ORgateLogic():
      q.next = a or b

   return ORgateLogic




@block
def XORgate( a, b,  q ):
      
   
   nota, notb, annotb, bnnota = [Signal(bool(0)) for i in range(4)]
   
   inv0 = NOTgate( a,  nota )
   inv1 = NOTgate( b,  notb )
   and2a = ANDgate( a, notb,  annotb )
   and2b = ANDgate( b, nota,  bnnota )
   or2a = ORgate( annotb, bnnota,  q )

   return inv0, inv1, and2a, and2b, or2a


@block
def HalfAdder( in_a, in_b,  summ, carry ):
    
   and2a =  ANDgate(in_a, in_b,  carry)
   xor2a =  XORgate(in_a, in_b,  summ)

   return and2a, xor2a


@block
def FullAdder( fa_c0, fa_a, fa_b,  fa_s, fa_c1 ):
   

   ha1_s, ha1_c1, ha2_c1 = [Signal(bool(0)) for i in range(3)]

   HalfAdder01 = HalfAdder( fa_c0, fa_a,  ha1_s, ha1_c1 )
   HalfAdder02 = HalfAdder( ha1_s, fa_b,  fa_s,  ha2_c1 )
   or2a = ORgate(ha1_c1, ha2_c1,  fa_c1)

   return HalfAdder01, HalfAdder02, or2a


@block
def Adder4b( ina, inb,  cOut, sum4):
    

   cl = [Signal(bool()) for i in range(0,4)]  
   sl = [Signal(bool()) for i in range(4)]  

   HalfAdder0 = HalfAdder(        ina(0), inb(0),  sl[0], cl[1] )
   FullAdder1 = FullAdder( cl[1], ina(1), inb(1),  sl[1], cl[2] ) 
   FullAdder2 = FullAdder( cl[2], ina(2), inb(2),  sl[2], cl[3] ) 
   FullAdder3 = FullAdder( cl[3], ina(3), inb(3),  sl[3], cOut ) 

   sc = ConcatSignal(*reversed(sl))  

   @always_comb
   def list2intbv():
      sum4.next = sc  

   return HalfAdder0, FullAdder1, FullAdder2, FullAdder3, list2intbv



t_co, t_s, t_a, t_b, dbug =  [Signal(bool(0)) for i in range(5)]
ina4, inb4, sum4 =  [Signal(intbv(0)[4:])  for i in range(3)]

from random import randrange 

@block
def Test_Adder4b():
   
   dut = Adder4b( ina4, inb4,  t_co, sum4 )

   @instance
   def check():
      print( "\n      b   a   |  c1    s   \n     -------------------" )
      for i in range(15):
         ina4.next, inb4.next = randrange(2**4), randrange(2**4)
         yield delay(5)
         print( "     %2d  %2d   |  %2d   %2d     " \
                % (ina4,inb4, t_co,sum4) )
         assert t_co * 16 + sum4 == ina4 + inb4  
      print()

   return dut, check




def main():
   simInst = Test_Adder4b()
   simInst.name = "mySimInst"
   simInst.config_sim(trace=True)  
   simInst.run_sim(duration=None)

   inst = Adder4b( ina4, inb4,  t_co, sum4 )  
   inst.convert(hdl='VHDL')  
   inst.convert(hdl='Verilog')  

    
if __name__ == '__main__':
   main()



COBOL:        program-id. test-add.
       environment division.
       configuration section.
       special-names.
           class bin is "0" "1".
       data division.
       working-storage section.
       1 parms.
        2 a-in pic 9999.
        2 b-in pic 9999.
        2 r-out pic 9999.
        2 c-out pic 9.
       procedure division.
           display "Enter 'A' value (4-bits binary): "
               with no advancing
           accept a-in
           if a-in (1:) not bin
               display "A is not binary"
               stop run
           end-if
           display "Enter 'B' value (4-bits binary): "
               with no advancing
           accept b-in
           if b-in (1:) not bin
               display "B is not binary"
               stop run
           end-if
           call "add-4b" using parms
           display "Carry " c-out " result " r-out
           stop run
           .
       end program test-add.

       program-id. add-4b.
       data division.
       working-storage section.
       1 wk binary.
        2 i pic 9(4).
        2 occurs 5.
         3 a-reg pic 9.
         3 b-reg pic 9.
         3 c-reg pic 9.
         3 r-reg pic 9.
        2 a pic 9.
        2 b pic 9.
        2 c pic 9.
        2 a-not pic 9.
        2 b-not pic 9.
        2 c-not pic 9.
        2 ha-1s pic 9.
        2 ha-1c pic 9.
        2 ha-1s-not pic 9.
        2 ha-1c-not pic 9.
        2 ha-2s pic 9.
        2 ha-2c pic 9.
        2 fa-s pic 9.
        2 fa-c pic 9.
       linkage section.
       1 parms.
        2 a-in pic 9999.
        2 b-in pic 9999.
        2 r-out pic 9999.
        2 c-out pic 9.
       procedure division using parms.
           initialize wk
           perform varying i from 1 by 1
           until i > 4
               move a-in (5 - i:1) to a-reg (i)
               move b-in (5 - i:1) to b-reg (i)
           end-perform
           perform simulate-adder varying i from 1 by 1
               until i > 4
           move c-reg (5) to c-out
           perform varying i from 1 by 1
           until i > 4
               move r-reg (i) to r-out (5 - i:1)
           end-perform
           exit program
           .

       simulate-adder section.
           move a-reg (i) to a
           move b-reg (i) to b
           move c-reg (i) to c
           add a -1 giving a-not
           add b -1 giving b-not
           add c -1 giving c-not

           compute ha-1s = function max (
               function min ( a b-not )
               function min ( b a-not ) )
           compute ha-1c = function min ( a b )
           add ha-1s -1 giving ha-1s-not
           add ha-1c -1 giving ha-1c-not

           compute ha-2s = function max (
               function min ( c ha-1s-not )
               function min ( ha-1s c-not ) )
           compute ha-2c = function min ( c ha-1c )

           compute fa-s = ha-2s
           compute fa-c = function max ( ha-1c ha-2c )

           move fa-s to r-reg (i)
           move fa-c to c-reg (i + 1)
           .
       end program add-4b.