Task: Four bit adder




Go: package main

import "fmt"

func xor(a, b byte) byte {
    return a&(^b) | b&(^a)
}

func ha(a, b byte) (s, c byte) {
    return xor(a, b), a & b
}

func fa(a, b, c0 byte) (s, c1 byte) {
    sa, ca := ha(a, c0)
    s, cb := ha(sa, b)
    c1 = ca | cb
    return
}

func add4(a3, a2, a1, a0, b3, b2, b1, b0 byte) (v, s3, s2, s1, s0 byte) {
    s0, c0 := fa(a0, b0, 0)
    s1, c1 := fa(a1, b1, c0)
    s2, c2 := fa(a2, b2, c1)
    s3, v = fa(a3, b3, c2)
    return
}

func main() {
    
    fmt.Println(add4(1, 0, 1, 0, 1, 0, 0, 1))
}




Python: 

from myhdl import *



@block
def NOTgate( a,  q ):   
   
   @always_comb   
   def NOTgateLogic():
      q.next = not a

   return NOTgateLogic   


@block
def ANDgate( a, b,  q ):
   
   @always_comb 
   def ANDgateLogic():
      q.next = a and b

   return ANDgateLogic


@block
def ORgate( a, b,  q ):
      
   @always_comb  
   def ORgateLogic():
      q.next = a or b

   return ORgateLogic




@block
def XORgate( a, b,  q ):
      
   
   nota, notb, annotb, bnnota = [Signal(bool(0)) for i in range(4)]
   
   inv0 = NOTgate( a,  nota )
   inv1 = NOTgate( b,  notb )
   and2a = ANDgate( a, notb,  annotb )
   and2b = ANDgate( b, nota,  bnnota )
   or2a = ORgate( annotb, bnnota,  q )

   return inv0, inv1, and2a, and2b, or2a


@block
def HalfAdder( in_a, in_b,  summ, carry ):
    
   and2a =  ANDgate(in_a, in_b,  carry)
   xor2a =  XORgate(in_a, in_b,  summ)

   return and2a, xor2a


@block
def FullAdder( fa_c0, fa_a, fa_b,  fa_s, fa_c1 ):
   

   ha1_s, ha1_c1, ha2_c1 = [Signal(bool(0)) for i in range(3)]

   HalfAdder01 = HalfAdder( fa_c0, fa_a,  ha1_s, ha1_c1 )
   HalfAdder02 = HalfAdder( ha1_s, fa_b,  fa_s,  ha2_c1 )
   or2a = ORgate(ha1_c1, ha2_c1,  fa_c1)

   return HalfAdder01, HalfAdder02, or2a


@block
def Adder4b( ina, inb,  cOut, sum4):
    

   cl = [Signal(bool()) for i in range(0,4)]  
   sl = [Signal(bool()) for i in range(4)]  

   HalfAdder0 = HalfAdder(        ina(0), inb(0),  sl[0], cl[1] )
   FullAdder1 = FullAdder( cl[1], ina(1), inb(1),  sl[1], cl[2] ) 
   FullAdder2 = FullAdder( cl[2], ina(2), inb(2),  sl[2], cl[3] ) 
   FullAdder3 = FullAdder( cl[3], ina(3), inb(3),  sl[3], cOut ) 

   sc = ConcatSignal(*reversed(sl))  

   @always_comb
   def list2intbv():
      sum4.next = sc  

   return HalfAdder0, FullAdder1, FullAdder2, FullAdder3, list2intbv



t_co, t_s, t_a, t_b, dbug =  [Signal(bool(0)) for i in range(5)]
ina4, inb4, sum4 =  [Signal(intbv(0)[4:])  for i in range(3)]

from random import randrange 

@block
def Test_Adder4b():
   
   dut = Adder4b( ina4, inb4,  t_co, sum4 )

   @instance
   def check():
      print( "\n      b   a   |  c1    s   \n     -------------------" )
      for i in range(15):
         ina4.next, inb4.next = randrange(2**4), randrange(2**4)
         yield delay(5)
         print( "     %2d  %2d   |  %2d   %2d     " \
                % (ina4,inb4, t_co,sum4) )
         assert t_co * 16 + sum4 == ina4 + inb4  
      print()

   return dut, check




def main():
   simInst = Test_Adder4b()
   simInst.name = "mySimInst"
   simInst.config_sim(trace=True)  
   simInst.run_sim(duration=None)

   inst = Adder4b( ina4, inb4,  t_co, sum4 )  
   inst.convert(hdl='VHDL')  
   inst.convert(hdl='Verilog')  

    
if __name__ == '__main__':
   main()