Emerging non-volatile memory enabled by carbon nano-materials [electronic resource]

Flash is the mainstream non-volatile memory (NVM) offering fast read access times, and the rapidly increasing demand for mobile and portable electronic devices has driven fast market growth in the NAND Flash industry. However, the Flash memory beyond the 1z nm technology node is expected to face serious reliability and feasibility issues ultimately due to the problem of few storage electrons (10-15 electrons for a 10 nm device). On the other hand, significant progress on emerging NVMs with sub-10 nm scalability, such as resistive RAM (RRAM), phase change memory (PCM), and spin-transfer-torque magnetic RAM (STT-MRAM), has made it possible to complement Flash with on-chip storage that may even satisfy the needs of requirements across a broad range of the memory hierarchy (e.g., L2/L3 cache). This is very important, as the energy efficiency of computing systems has been increasingly limited by the data movement between the memory and data storage devices and the computational units. In this thesis work, two fundamental challenges in emerging NVM technologies are addressed with a view to realizing their promise as a next-generation memory technology: (1) development of cost-effective and 3D-stackable memory arrays and (2) designing an energy-efficient NVM cell. First, in order to mitigate the sneak path problem in the cross-point structure without requiring an enlarged device area footprint, we constructed a novel 1TnR (one-transistor-n-resistors) array architecture using one-dimensional (1D) selection device. Experimental demonstrations were made with two emerging NVM candidates of RRAM and PCM, by employing the high-performance carbon nanotube (CNT) field-effect transistor (CNFET) as the 1D selector. Second, in order to improve energy-efficiency of PCM, we placed a 3 Å thick single-layer graphene (SLG) layer at the interface between the phase-change material (GST) and the columnar bottom electrode (W) heater. We found that using a SLG as an interfacial thermal barrier results in a significant decrease in the RESET programming current of PCM, as compared with the conventional PCM of the same effective contact size. The reduced RESET current of the graphene-inserted PCM device is attributed to the fact that the SLG layer adds large amounts of thermal resistances at the GST/W interface, which in turn effectively confines the generated heat inside the active programming volume of the GST. In the last part of the thesis, we presented our studies on crystallization properties of the PCM device. The crystallization process in PCM has not been clearly identified so far due to its strong dependence on materials and device geometry and its random nature. We particularly focused on the recrystallization of a PCM cell due to thermal disturbances from its neighboring cells that are being programmed, as it remains a serious issue that may cause retention failure of the cells in a high-density PCM array. We demonstrated using a doped SbTe phase-change alloy and an on-chip micro-thermal stage (MTS) heater that the problem of thermal cross-talk in PCM can be significantly relieved by choosing a proper programming scheme and tuning the effective activation energy barrier by adjusting the amount of resistance drift between the thermal disturbances.

Keywords: Electrical Engineering.
Advisor: Wong Hon-Sum Philip
Nishi Yoshio
Saraswat Krishna advisor. Thesis advisor