Device / circuit fabrication using diblock copolymer lithography [electronic resource]

Device scaling in semiconductor industry has been driven by the stringent performance demand. Smaller devices are enabled by continuously miniaturizing the feature size of device components. However it is approaching a hard stop due to the physical limit of optical lithography resolution so that extensive researches on next generation lithography technology have been carried out in view of the deficiency of optical lithography alone. The feasibility of each next generation lithography candidate substantially revolved on its throughput capability and its cost of operation and ownership. Electron beam lithography (EBL) and nanoimprint lithography are limited mainly by the throughput, while extreme ultraviolet (EUV) lithography is limited by infrastructure and operation costs. Amongst the next generation lithography candidates, block copolymer lithography has the cost-effective advantages of retaining the current optical lithography toolsets and adopting similar double patterning scheme as is in use for 193 nm immersion lithography today. Block copolymers are unique soft materials that can self-assemble into periodic arrays consisting of nanometer-sized features. Self-assembly process is analogous to lithographic patterning, but with the driving force of generating patterns being internal repulsion between unlike blocks instead of external agitation such as light source. This is the major benefit of deploying block copolymer lithography as it does not demand for aggressive wavelength reduction nor costly apparatus needs which all convert to the capital expense in the leading semiconductor companies. In addition, block copolymers are highly scalable to the limit on the order of molecular sizes providing synthesis method for such block copolymers exist. This dissertation builds on these meritorious promises to explore the use of block copolymer lithography to fabricate top-gated field effect transistors and circuits. The focus of this dissertation is on merging "bottom-up" block copolymer lithography with "top-down" optical lithography for conventional CMOS process. As a proof of concept, this work demonstrates the realization of the first top-gated transistors and circuits featuring 20 nm self-assembled contact holes. Based on previous art, self-assembled features can be generated in desirable locations by way of topographic confinements fulfilled by optical lithography. If the confinement templates are on the order of dimensions comparable to the natural self-assembly length scale and pitch, the self-assembled pattern stops adhering to its natural array and shapes, resulting in nanometer-sized holes with shapes and arrays potentially useful for random logic and memory applications. Consider block copolymer lithography can be applied in the mass production environment, many technical measures and characterizations should be made available. Among them, a full set of design rules for designing the confinement templates should be derived both simulation-wise and experiment-wise so that final self-assembled features and arrays can be predicted and realized.

Keywords: Materials Science and Engineering
Advisor: Brongersma Mark L. primary advisor. Thesis advisor
Wong Hon-Sum Philip
Cui Yi