Nanostructured SiGe and Ge for future electronic devices [electronic resource]

As the packing density of silicon (Si) integrated circuits (IC) increases, scaling requirements are becoming severe. Two approaches are considered to be effective to continue dimensional scaling. One is to alter the active device layer so that it is a semiconductor other than silicon. Silicon-germanium (SiGe) and germanium (Ge) are suitable candidates because of their greater carrier mobilities than Si and their process compatibility with Si substrates. Another approach is to change the device structure or circuit configuration so that there is less power consumption and better performance for higher device packing densities in ICs. Nanoscale structures such as ultra-thin semiconductor-on-insulators or nanowires can be incorporated in future transistors. This dissertation will focus initially on synthesis of highly compressively strained SiGe-on-insulator (SGOI) substrate fabrication. The strain relaxation mechanisms in highly compressively-strained (0.67 % ~ 2.33 % biaxial strain), thin SGOI structures with Ge atomic fraction ranging from 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were fabricated by selective oxidization of Si from compressively strained SiGe films epitaxially grown on single crystalline Si-on-insulator (SOI) layers. After high temperature oxidation annealing, ~ 30 % of the observed strain relaxation can be attributed to formation of intrinsic SFs and the remaining strain relaxation to stress-driven buckling of the SiGe layers. Second part of the dissertation discusses about the directed synthesis of germanium oxide (GeOx) nanowires (NWs) by locally-catalyzed thermal oxidation of aligned arrays of gold (Au) catalyst-tipped germanium NWs. During oxygen anneals con- ducted above the Au-Ge binary eutectic temperature (T > 361 °C), one-dimensional oxidation of as-grown Ge NWs occurs by diffusion of Ge through the Au-Ge cat- alyst droplet, in the presence of an oxygen containing ambient. Elongated GeOx wires grow from the liquid catalyst tip, consuming the adjoining Ge NW as they grow. The oxide NW diameter is dictated by the catalyst diameter, and their alignment generally parallels that of the growth direction of the initial Ge NWs. Growth rate comparisons reveal a substantial oxidation rate enhancement in the presence of the Au catalyst. Statistical analysis of GeOx nanowire growth by ex situ transmission electron microscopy and scanning electron microscopy suggests a transition from an initial, diameter-dependent kinetic regime, to diameter-independent wire growth. This behavior suggests the existence of an incubation time for GeOx NW nucleation at the start of vapor-liquid-solid oxidation. The dissertation will also discuss the path to obtain higher-k dielectrics on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate capacitance density dielectrics on high-mobility Ge channels, one solution is to interpose a large energy band gap (Eg) insulator with moderate k as an interface layer between a higher-k dielectric and the channel, since higher-k dielectrics tend to have small Eg. Al2O3 layers (k ~ 8) can have stable interfaces with Ge and a large band gap. On the other hand, TiO2 can achieve a much higher k value (~ 60) when in the rutile crystalline phase, but its conduction band offset with Ge is less than 1 eV. TiO2/Al2O3 bilayers deposited on Ge(100) by ALD can achieve low interface trap density with small leakage current after post-metal forming gas anneal. From measurements performed on MOS capacitors, the maximum capacitance at a given frequency increases after the 450 °C forming gas anneal, indicating that the dielectric constant of TiO2 increased to ~ 50 after annealing. Consistent with these results, TEM data indicate that the ALD- grown TiO2 phase had transformed from amorphous phase to the predominant rutile phase after annealing. In order to measure the channel transfer characteristics for this TiO2 (7.5 nm)/Al2O3 (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (Lg = 2 ~ 30 [mu]m) were fabricated. The devices show a subthreshold swing of 110 mV/dec and an on-state current of 73 mA/mm. Measured peak hole mobility reaches 370 cm2/Vs, which suggests the feasibility and potential of TiO2/Al2O3/Ge gate stacks for high performance MOSFETs.

Keywords: Materials Science and Engineering
Advisor: McIntyre Paul Cameron primary advisor. Thesis advisor
Nishi Yoshio
Nix William D. advisor. Thesis advisor