Design and fabrication of electrostatically actuated nanoelectromechanical relays and their integration with CMOS [electronic resource]

Over the past few decades, CMOS transistor scaling has resulted in a dramatic increase in computing power. However, continuing the voltage scaling is becoming increasingly difficult because of the increase in subthreshold leakage. This increase is inevitable with threshold voltage scaling, since the subthreshold slope is theoretically limited to be larger than 60 mV/dec at room temperature. Nanoelectromechanical (NEM) relays are promising devices to overcome this voltage scaling issue because of their sharp on/off transition characteristics and zero off-state leakage. However, these devices have long switching times due to their long mechanical delays. By combining NEM relays with CMOS, it is possible to capitalize on the benefits of each technology. In the first part of this work, a novel CMOS--NEM static random access memory (SRAM) cell design is proposed, in which three-terminal (3T) NEM relays replace the pull-down NMOS transistors of a conventional six-transistor (6T) CMOS SRAM cell. This SRAM cell utilizes the sharp on/off transition characteristics and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. To simulate this novel design, various NEM relay parameters are modeled and calculated to build a Verilog-A model of a 3T NEM relay. Compared to a 65 nm CMOS 6T SRAM cell, when 10 nm-gap NEM relays (pull-in voltage = 0.8 V, pull-out voltage = 0.2 V, on-resistance = 1 k[omega]) are integrated, hold and read static noise margin (SNM) improve by approximately two-fold and three-fold, respectively. In addition, static power dissipation decreases by approximately 85 %. The write delay decreases by approximately 60 %, while read delay decreases by approximately 10 %. The advantages in SNM and static power dissipation are expected to increase with scaling. Despite these advantages, this circuit has not yet been experimentally demonstrated; therefore, in the second part of this work, as an initial step towards the demonstration, the fabrication of NEM relays and their integration with CMOS, is experimentally demonstrated. NEM relays without CMOS are first fabricated and electrically characterized in two different versions: 1) optically patterned devices with larger dimensions, which have a polysilicon structural layer and a metal (platinum or titanium nitride) coating layer, with actuation voltages in the range of 10--80 V and 2) e-beam patterned devices with scaled-down dimensions, which have a single metal (platinum) layer, with actuation voltages in the range of 3--6 V. The scaled down devices are suitable for CMOS--NEM integration, since they have low actuation voltages and a CMOS-compatible fabrication process. With these devices, simple CMOS--NEM integrated circuits — an NMOS transistor driving a NEM relay and a CMOS inverter driving a NEM relay — are fabricated and electrically tested, for the first time, demonstrating the feasibility of CMOS--NEM integration.

Keywords: Electrical Engineering
Advisor: Wong Hon-Sum Philip
Howe Roger Thomas advisor. Thesis advisor
Mitra Subhasish advisor. Thesis advisor