Resistive switching random access memory - device scaling in 3D architecture and integration with complementary metal oxide semiconductor

The rapid development and proliferation of mobile devices, such as smartphones, has enabled quick and easy Internet access, providing various sensor data from those devices. Amid a plethora of data, there has been an increase in demand for higher density storage class memory (SCM), which has been met through feature size scaling. However, it is expected that mainstream memory technology - NAND Flash - going beyond the 1z nm technology node will face its ultimate scaling limit. Resistive random access memories (RRAM) based on metal oxide is widely considered one of the most prominent next-generation non-volatile memory (NVM) technologies. Its key attributes, including better endurance, retention, speed, low programming voltages, and 3D integration capacity, make it a promising candidate for future SCM. In the first part of this dissertation, I demonstrate ultimate vertical scaling for RRAM in the 3D architecture (3D-RRAM) by employing the atomically thin nature of graphene edge (~3 Å thick). In this architecture, RRAM cell is formulated at the intersection between the pillar electrode and graphene edge electrode. Our 3D-RRAM with graphene edge electrode shows drastic vertical scaling of an individual stack height, allowing our device to stack up to 200 layers, whereas NAND Flash products can only go several tens of layers. Graphene has an outstanding electrical property due to its superior sheet resistance per thickness, and our study by SPICE simulation suggests that our 3D-RRAM can achieve > 100 Gb array size. Our fabricated 2-layer of 3D-RRAM exhibits excellent electrical characteristics, such as high resistance values and good endurance. Moreover, the role of top electrode (TE) and bottom electrode (BE) is exchangeable with each other in our device depending on the initial device programming voltage polarity (the forming process), making it possible to monitor the movement of oxygen ions using Raman image analysis. Due to the low switching voltage in the reverse switching mode, we are able to achieve very low switching power consumption as compared to recently reported RRAMs. This work contributes to research and development of energy efficient, high density non-volatile memory, which is needed to meet the growing demands of storing and processing of data in future computing systems. The last chapter of this dissertation introduces the integration of RRAM on a CMOS logic platform. In this study, we show it is possible to build fully functional RRAMs starting from Si CMOS wafers from a commercial foundry and successfully integrate RRAM as a back end of line (BEOL) on the Si CMOS wafer. In this chapter, I present the architecture of a compact, one-transistor-two-RRAM (1T2R) array, with associated read/write scheme. This chapter describes the process flow of RRAM integration and reports on the evaluation of RRAMs in an array with a memory array test scheme. The development of CMOS-compatible RRAM is also covered in the final chapter.

Keywords: Electrical Engineering.
Advisor: Wong Hon-Sum Philip
Nishi Yoshio
Wong S.