Energy proportional memory systems [electronic resource]

The horizon of computer systems is changing. Moore's law is power constrained, making energy efficiency the primary goal of computer systems. In particular, memory energy has emerged as the key efficiency bottleneck, owing to extensive research in low power CPU architectures. On the other hand, the popularity of modern day internet services has lead to a vast expansion of datacenters, magnifying the importance of efficient computer system design. With datacenter energy provisioning and running costs running into millions of dollars, energy is an even more important criterion in datacenters. To increase computer system energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3x the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices i.e. LPDDR2, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5x lower memory power, better proportionality, and negligible performance penalties for datacenter workloads. Noting that LPDDR2 has performance impact for high bandwidth applications, we explore low-power, high-speed interfaces that can be applied to a broad variety of applications. We re-think DRAM power modes by modeling and characterizing inter-arrival times for memory requests to determine the properties an ideal power mode should have. This analysis indicates that even the most responsive of today's power modes are rarely used. As a result, up to 88% of memory is spent idling in an active mode. This analysis indicates that power modes must have much shorter exit latencies than they have today. Wake-up latencies less than 100ns are ideal. To address these challenges, we present MemBlaze, an architecture with DRAMs and links that are capable of fast powerup, which provides more opportunities to powerdown memories. By eliminating DRAM chip timing circuitry, a key contributor to powerup latency, and by shifting timing responsibility to the controller, MemBlaze permits data transfers immediately after wake-up and reduces energy per transfer by 50% with no performance impact. Alternatively, in scenarios where DRAM timing circuitry must remain, we explore mechanisms to accommodate DRAMs that powerup with less than perfect interface timing. We present MemCorrect which detects timing errors while MemDrowsy lowers transfer rates and widens sampling margins to accommodate timing uncertainty in situations where the interface circuitry must recalibrate after exit from powerdown state. Combined, MemCorrect and MemDrowsy still reduce energy per transfer by 50% but incur modest (e.g., 10%) performance penalties. Finally, we demonstrate that we need to re-evaluate our design choices for last level caches whose static power is beginning to compete with the dynamic energy of new and efficient memory systems like LPDDR2. We propose a novel metric called "Average Memory Access Energy" that quantifies energy costs of the memory hierarchy and helps us make efficient design choices. We demonstrate how the low energy memory hierarchy helps us in lowering system operating costs.

Keywords: Electrical Engineering.
Advisor: Horowitz Mark (Mark Alan) primary advisor. Thesis advisor
Kozyrakis Christoforos
Lee Benjamin C. advisor. Thesis advisor