Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters

Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration – from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.

Advisor: Alon, Elad