Scalability and reliability of phase change memory [electronic resource]

Various memory devices are being widely used for a wide range of applications. There has not been any universal memory device so far because each memory device has a unique set of features. Large performance gaps in various dimensions of features between memory devices and a new set of features required by new electronic systems such as portable electronics open up new opportunities for new memory devices to emerge as mainstream memory devices. Besides, the imminent scaling limit for existing mainstream memory devices also motivates development and research of new memory devices which can meet the increasing demand for large memory capacity. Phase change memory (PCM) is one of the most promising emerging memory devices. It has the potential to combine DRAM-like features such as bit alteration, fast read and write, and good endurance and Flash-like features such as non-volatility and a simple structure. PCM is expected to be a highly scalable technology extending beyond scaling limit of existing memory devices. Prototypical PCM chips have been developed and are being tested for targeted memory applications. However, understanding of fundament physics behind PCM operation is still lacking because the key material in PCM devices, the chalcogenide, is relatively new for use in solid state devices. Evaluation and development of PCM technology as successful mainstream memory devices require more study on PCM devices. This thesis focuses on issues relevant to scalability and reliability of PCM which are two of the most important qualities that new emerging memory devices should demonstrate. We first study basic scaling rule based on thermoelectric analysis on the maximum temperature in a PCM cell and show that both isotropic and non-isotropic scaling result in constant programming voltage. The minimum programming voltage is determined by material properties such as electrical resistivity and thermal conductivity regardless of the device size. These results highlight first-order principles governing scaling rules. In the first-order scaling rule analysis, we assume that material properties are constant regardless of its physical size. However, when materials are scaled down to the nanometer regime, material properties can change because the relative contribution from the surface property to the overall system property increases compared to that from the bulk property. We study scaling effect on material property and device characteristics using a novel device structure -- a PCM cell with a pseudo electrode. With the pseudo electrode PCM cell, we can accurately relate the observed properties to the amorphous region size. We show that threshold switching voltage scales linearly with thickness of the amorphous region and threshold switching field drifts in time after programming. We also show that the drift coefficient for resistance drift stays the same for scaled devices. These property scaling results provide not only estimates for scaled device characteristics but also clues for modeling and understanding mechanisms for threshold switching and drift. To make scaled memory cells in an array form, not only memory device elements but also selection devices need to be scaled. PCM requires relatively large programming current, which makes it challenging to scale down selection devices. We integrate Ge nanowire diodes as selection devices in search for new candidates for high density PCM. Ge nanowire diode provides on/off ratio of ~100 and small contact area of 40 nm in diameter which results in programming current below 200 [mu]A. The processing temperature for Ge nanowire diode is below 400°C, which makes Ge nanowire diode a potential enabler for 3D integration. As memory devices are scaled down, more serious reliability issues arise. We study the reliability of PCM using a novel structure -- micro-thermal stage (MTS). The high-resistance-state (RESET) resistance and threshold switching voltage are important device characteristics for reliable operation of PCM devices. We study the drift behavior of RESET resistance and threshold switching voltage and its temperature dependence using the MTS. Results show that the drift coefficient increases proportionally to annealing temperature until it saturates. The analytical drift model for time-varying annealing temperature that we derive from existing phenomenological drift models agrees well with the measurement results. The analytical drift model can be used to estimate the impact of thermal disturbance (program disturbance) on RESET resistance and threshold switching voltage. Thermal disturbance is a unique disturbance mechanism in PCM which is caused by thermal diffusion from a cell being programmed. The MTS can effectively emulate the short heat pulse, enabling detailed study on thermal disturbance impact on cell characteristics. We show that random thermal disturbance can result in at least 25 and 100 % variations in RESET resistance and threshold switching voltage. The existing model on how to add up the impact of thermal disturbance on crystallization is experimentally verified using the MTS. Based on measurement and modeling results, we propose a new programming scheme to improve stability of PCM with a short-time annealing pulse.

Keywords: Electrical Engineering
Advisor: Wong Hon-Sum Philip
Cui Yi
Nishi Yoshio