Application of graphene in integrated circuit interconnect technology [electronic resource]

Back-End-Of-Line (BEOL) process refers to the second part of the Integrated Circuit (IC) fabrication process during which different levels of interconnect wires are fabricated to connect devices (transistors, resistors, capacitors, etc.) together into circuits. As the dimension of semiconductor devices scales down progressively, conventional interconnect technology using metals such as copper is facing great challenges to meet performance requirement and is becoming a bottleneck for further improving IC performance. At narrow linewidth < 50nm, copper wire conductivity decreases due to increased surface and grain boundary scattering. The interconnect conductivity degradation problem is further exacerbated by the lack of scalability of copper diffusion barrier layer conventionally fabricated using resistive materials such as tantalum nitride (TaN). One way to alleviate this problem and extend the scaling path for copper interconnect is to develop a new diffusion barrier layer that is thinner and more conductive. This dissertation proposed and studied the possibility of using graphene as an ultra-thin highly conductive copper diffusion barrier. Performance of graphene-based diffusion barrier is evaluated by studying the Time-Dependent-Dielectric-Breakdown (TDDB) lifetime of dielectric underneath the barrier layer in a MOS capacitor structure. Result shows that high quality multi-layer graphene indeed has the promise of being used as an effective copper diffusion barrier. Besides the conductivity degradation, copper interconnect is also facing reliability concerns at narrow linewidth due to electromigration. As the cross-section area of interconnects scales down, maximum current density increases. Joule heating will also increase due to wire resistance increase. Both of these factors will greatly compromise reliability performance of copper wires. In the near future, the degradation of copper conductivity and reliability will be so significant that the need for an alternative interconnect material that is more conductive and reliable at nano-scale becomes imperative. In recent years, graphene has been considered as one of the most promising candidates for future interconnect technology. Theory shows that graphene nanoribbons (GNR) can offer performance improvements compared to copper at deeply scaled technology node ( < 10 nm). In this dissertation, we mainly focused on experimental study of the speed and reliability performance of graphene interconnects. To demonstrate and assess the speed performance of graphene interconnect in a realistic IC operating environment, we developed a process flow to integrate graphene wires with CMOS test platform that operates at above 1GHz. Using this test platform, we were able to demonstrate for the first time graphene interconnects that operates at 1.3 GHz. We also experimentally compared the performance of on-chip graphene and multi-wall carbon nanotubes interconnects. Unlike copper, the strong hexagonal lattice structure of graphene formed by covalent carbon-carbon bonds gives it immunity to electromigration, the phenomenon that limits the life span of metallic interconnects. However, there are other mechanisms that put constraints on graphene interconnect reliability performance. In this dissertation, we studied the failure mechanisms of graphene interconnects, characterized graphene time-dependent reliability performance under thermal and current stress, and experimentally extracted the activation energy of graphene interconnect failure for the first time. We showed that graphene interconnect lifetime is mainly limited by graphene oxidation, and therefore optimized passivation is necessary to improve graphene reliability. We studied the impact of different dielectric passivations and showed that when passivated, graphene interconnect can have lifetime 3~4 times better than CoWP passivated copper interconnect of similar physical dimensions. This dissertation is organized as follows: chapter one and two will give an overview of the state-of-art CMOS interconnect technology, the scaling challenges it is facing, and the motivation of using graphene in BEOL technology. Chapter three will investigate the possibility of using graphene as copper diffusion barrier. Chapter four and five will focus on performance studies of graphene interconnect, both the feasibility of using graphene as high-speed interconnect integrated with CMOS and reliability performances. In summary, this thesis presented the first experimental demonstration of graphene interconnect integrated with CMOS operating above GHz frequency range. We also provided a thorough study of graphene interconnect time-dependent reliability for the first time, and investigated the interconnect failure mechanism as well as the impact of passivation on interconnect reliability performance. This dissertation also proposed a new idea of using graphene as copper wire diffusion barrier. Preliminary experimental result shows promise but more study is still needed to further establish the possibility of this new application of graphene in interconnect technology.

Keywords: Physics
Advisor: Goldhaber-Gordon David
Wong Hon-Sum Philip
Cui Yi