VictorJuiz/thesis huggingface dataset:
De novo synthesis and biological evaluation of modified saxitoxins for sodium ion channel study [electronic resource]

Access to novel forms of (+)-saxitoxin (STX), a potent and selective inhibitor of voltage-gated sodium ion channels (NaV), has been made possible through de novo synthesis. Saxitoxin is believed to lodge in the outer mouth of the sodium channel pore, thereby stoppering ion flux. Saxitoxin and derivatives thereof represent high-precision pharmacological tools that can be used to gain insight into the structure and integrated cellular function of sodium channel proteins. The preparation and biological evaluation of N21-carbamoyl-modified saxitoxins are described herein. The synthesis plan for assembling these molecules features a robust sequence that enables the preparation of gram quantities of a key nine-membered ring guanidine intermediate. Transformation of this advanced intermediate into a strained 5,6,5-fused tricycle through four-electron olefin oxidation affords an amine-reactive oxazolidinone from which all N21-modified saxitoxins are available. The potencies of STX and all analogous structures have been determined using heterologous gene expression and voltage clamp electrophysiology. These studies show that various N21 substituents are readily accommodated in the STX binding site of the protein with little loss of ligand-receptor binding affinity. This discovery has allowed for the design of photoaffinity and fluorescently labeled saxitoxins, which will serve to further our understanding of the architecture of the STX binding site, and represent a novel set of molecular probes that make possible real-time, live cell investigations of NaV function. Studies utilizing analogues of the pore blocker, saxitoxin, were complimented by an investigation of the aconine alkaloid, aconitine, a known Site II modifier of NaV function. A semi-synthetic pathway used to access derivatives of aconitine is detailed, along with an electrophysiological analysis of the ability of these derivatives to modify the conductive properties of the sodium channel.

Keywords: Chemistry
Advisor: Du Bois Justin primary advisor. Thesis advisor
Waymouth Robert M. advisor. Thesis advisor
Wender Paul A. advisor. Thesis advisor
Depot-specific gene expression programs of adipocytes [electronic resource] : physiological and developmental implications

Adipose tissue is found in diverse depots throughout the human body. The diversity of physiological specialization of these fat depots is reflected in the diverse depot-specific alterations seen in lipodystrophies and links between specific patterns of fat distribution and susceptibility to diseases, including Type II Diabetes and coronary artery disease. Previous studies, although focused on only 2 major fat depots (omental and abdominal subcutaneous), have identified numerous differences in metabolic, endocrine and developmental programs. We carried out a more extensive and higher resolution investigation of the anatomic specialization of white adipose tissue, based on 59 samples collected from 7 anatomically diverse fat depots, from 56 individuals. Using DNA microarrays we measured relative abundance of ~25,000 distinct mRNAs in each adipose tissue sample and in adipocytes and stromal-vascular cells isolated from each sample, and compared their gene expression patterns with ~120 samples representing diverse non-adipose tissues. Adipocytes from different regions of the body displayed distinct gene expression profiles. Characteristic patterns of expression of HOX genes distinguished adipocyte samples by site of origin; these patterns were recapitulated when adipocyte precursors from each site were cultured and differentiated ex vivo, suggesting that these genes may have a role in programming and/or maintaining depot-specific differentiation of adipocytes. Expression in adipocytes of 300 genes with major roles in energy metabolism showed both depot-dependent and inter-individual variation. Some of the patterns suggested important differences among anatomic depots in metabolic roles. For example, a set of genes involved in lipid uptake and storage and hormone-regulated lipolysis were generally most highly expressed in breast, pericolonic and omental adipocytes whereas genes involved in glycogen metabolism and de novo fatty acid synthesis were generally most highly expressed in breast and abdominal subcutaneous adipocytes, suggesting that these depots play a role as glucose buffers. Dozens of genes known or predicted to encode secreted molecular signals were highly expressed in adipocytes compared to either adipose stromal-vascular cells or other organs; many of these were differentially expressed among adipocyte depots. Some of these genes appear to be good candidates for encoding novel adipokines. In summary, we found extensive variation among adipose depots, as well as inter-individual variation, in global gene expression. Differences in genes linked to development, metabolism and cell-cell communication suggest new hypotheses relevant to depot-specific and general aspects of adipocyte biology.

Keywords: Biochemistry.
Advisor: Brown Patrick O'Reilly
Chu Gilbert advisor. Thesis advisor
Kingsley David M. (David Mark) advisor. Thesis advisor
Krasnow Mark
The descriptive mode [electronic resource] : Flaubert, Verga, Huysmans, D'Annunzio

Looking at novels by Flaubert, Verga, Huysmans, and D'Annunzio, this project charts the increasing role of subjectivity in novelistic descriptions from mid- to late- nineteenth century France and Italy. This extended analysis of literary techniques that express subjectivity reveals that description was increasingly seen as a field of experimentation in which the parameters of an individual's access to the observable world could be adjusted to the concerns of a particular novel. Earlier approaches to description in the nineteenth century had used the proliferation of individual details as a way of ensuring fidelity to the observable world. An unobtrusive describing voice was considered a mark of the objectivity of a description. Adaptations of this concept to new types of projects -- projects in which the distinctive perspective of figures within the world of the novel are key to the novel's plot -- produced different results, however, in the second half of the century: the issue became not only whether or not one could describe sufficiently and in as objective a way as possible, but how a description could adapt to accommodate observational subjectivity while maintaining the referential basis of the descriptive mode. In some cases the use of techniques that imply the presence of a filtering subjectivity leads to what seems like a greater impersonality, as the observing descriptor is redistributed and reabsorbed into the reality of the novel's characters. In contrast, in others the overabundance of subjectivity techniques and the influence they have on sentence and paragraph structure overwhelms the composition and the novel moves into relativism and even idiolect. This dissertation traces a progression from the former tendency to the latter over the course of the second half of the nineteenth century in France and Italy, thus showing a continuity between 'realist' tropes of observation integrated in description and the 'decadent' style that appropriated those tropes in the interest of individual expression.

Keywords: French & Italian
Advisor: Gumbrecht Hans Ulrich primary advisor. Thesis advisor
Moretti Franco
Wittman Laura advisor. Thesis advisor
Design and fabrication of imperfection-immune carbon nanotube digital VLSI circuits [electronic resource]

Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single walled Carbon Nanotubes (CNTs), show great promise as extensions to silicon CMOS. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale integration. This work presents design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques. Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits implementing arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows. A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 10^3-10^5, and overcomes the limitations of existing metallic-CNT removal techniques. The above techniques are demonstrated for complex logic structures using wafer-scale growth of (99.5%, estimated from Scanning Electron Micrographs) aligned CNTs on single-crystal quartz and wafer-scale CNT transfer from quartz to silicon. Such an integrated approach enables the first experimental demonstration of VLSI-compatible CNFET combinational circuits (e.g., computational elements such as half-adder sum-generators) and storage circuits (e.g., sequential elements such as D-latches) that are immune to inherent CNT imperfections. These experimentally-demonstrated circuits form essential building blocks for large-scale digital computing systems.

Keywords: Electrical Engineering
Advisor: Mitra Subhasish primary advisor. Thesis advisor
Kozyrakis Christoforos
Wong Hon-Sum Philip
The design and implementation of hardware systems for information flow tracking [electronic resource]

Computer security is a critical problem impacting every segment of social life. Recent research has shown that Dynamic Information Flow Tracking (DIFT) is a promising technique for detecting a wide range of security attacks. With hardware support, DIFT can provide comprehensive protection to unmodified application binaries against input validation attacks such as SQL injection, with minimal performance overhead. This dissertation presents Raksha, the first flexible hardware platform for DIFT that protects both unmodified applications, and the operating system from both low-level memory corruption exploits such as buffer overflows, and high-level semantic vulnerabilities such as SQL injections and cross-site scripting. Raksha uses tagged memory to support multiple, programmable security policies that can protect the system against concurrent attacks. It also describes the full-system prototype of Raksha constructed using a synthesizable SPARC V8 core and an FPGA board. This prototype provides comprehensive security protection with no false-positives and minimal performance, and area overheads. Traditional DIFT architectures require significant changes to the processors and caches, and are not portable across different processor designs. This dissertation addresses this practicality issue of hardware DIFT and proposes an off-core coprocessor approach that greatly reduces the design and validation costs associated with hardware DIFT systems. Observing that DIFT operations and regular computation need only synchronize on system calls to maintain security guarantees, the coprocessor decouples all DIFT functionality from the main core. Using a full-system prototype based on a synthesizable SPARC core, it shows that the coprocessor approach to DIFT provides the same security guarantees as Raksha, with low performance and hardware overheads. It also provides a practical and fast hardware solution to the problem of inconsistency between data and metadata in multiprocessor systems, when DIFT functionality is decoupled from the main core. This dissertation also explores the use of tagged memory architectures for solving se- curity problems other than DIFT. Recent work has shown that application policies can be expressed in terms of information flow restrictions and enforced in an OS kernel, providing a strong assurance of security. This thesis shows that enforcement of these policies can be pushed largely into the processor itself, by using tagged memory support, which can pro- vide stronger security guarantees by enforcing application security even if the OS kernel is compromised. It presents the Loki architecture that uses tagged memory to directly enforce application security policies in hardware. Using a full-system prototype, it shows that such an architecture can help reduce the amount of code that must be trusted by the operating system kernel.

Keywords: Electrical Engineering
Advisor: Kozyrakis Christoforos
Mitra Subhasish advisor. Thesis advisor
Olukotun Oyekunle Ayinde advisor. Thesis advisor
Design and implementation of plasmonic cavities in thin metallic films [electronic resource]

Metals contain a sea of free electrons that are easily driven into collective oscillation by electromagnetic waves. As a result, small metal objects can serve as antennas that strongly scatter light. At the same time, extended metal surfaces have been shown to guide surface plasmons (photons bound to surface charge oscillations) that can confine light to deep sub-wavelength dimensions. Patterned metallic films can combine both the scattering and guiding properties of metals to capture and concentrate light from free space into a photodetector or to control the emission of light from emitting media. We first consider the wide range of functions that can be achieved in directing light emission with the help of smooth metallic films. We then describe how light interacts with patterned metallic films and present a detailed study of the effect of a single metallic groove on the scattering and surface plasmon guiding processes. This has lead to our discovery of new, exciting opportunities for dense optical functionality with non-periodically patterned metallic films. We show that a micronscale structure consisting of just two grooves in a metal film can lead to directional light coupling and wavelength splitting with a contrast ratio of 3:1. Our understanding is then generalized giving rise to a fast, simplified optimization of large non-periodic structures for a desired function. Lastly we consider the efficiency and bandwidth limits of coupling light through sub-wavelength slits for photodetection. We outline a path to efficient, spectrally selective detection which may find application in compact, polarization sensitive, multi-wavelength plasmonic detectors.

Keywords: Applied Physics
Advisor: Brongersma Mark L. primary advisor. Thesis advisor
Miller D. A. B. primary advisor. Thesis advisor
Fan Shanhui
Design and optimization of processors for energy efficiency [electronic resource] : a joint architecture-circuit approach

The design of a digital system for energy efficiency often requires the analysis of trade-offs in both the circuit design and the architecture. To assist with this analysis, we present a novel optimization framework for performing joint design space exploration of architectural and circuit design spaces. In this approach, we use statistical inference/regression techniques to create a models of large micro-architectural design spaces from a small number of simulation samples. We then characterize the design trade-offs of each of the underlying circuits and integrate these with the higher level architectural models to define the joint circuit-architecture design space. By using posynomial forms for all our models, we are then able to formulate the optimization problem as a geometric program, enabling the use of convex optimization tools to efficiently search the joint design space. We apply this framework to study energy-performance trade-offs in general purpose microprocessor design. We consider six different high-level architectures, from a simple single-issue in-order processor to a quad-issue out-of-order processor. Optimizing across this space for different performance targets, we identify the order in which high-level architectural features should be considered as one seeks more performance; starting with a low-power single-issue in-order design, to increase performance efficiently one should first increase the issue-width to two, then add out-of-order execution, and finally increase the issue-width further to end with the quad-issue out-of-order processor if maximum performance is required. Extending our study to include the voltage scaling, we find that the results change dramatically. Our results show that architectural and circuit design techniques have a very rapidly changing marginal cost profile, with many options having either very low or very high marginal costs. Since the marginal cost of obtaining additional performance through voltage changes more slowly, we find that when we optimize the system jointly with voltage, the set of efficient architecture/circuit design features become confined to a small sweet spot for a large part of the design space. Thus, when optimized with voltage as a parameter, two high-level architectures--the dual-issue in-order processor and the dual-issue out-of-order processor--are efficient over almost the complete range of performance targets.

Keywords: Electrical Engineering
Advisor: Horowitz Mark (Mark Alan) primary advisor. Thesis advisor
Kozyrakis Christoforos
Boyd Stephen P. advisor. Thesis advisor
Design and process for three-dimensional heterogeneous integration [electronic resource]

Since the invention of the integrated circuit (IC) in the late 1950s, the semiconductor industry has experienced dramatic growth driven by both technology and manufacturing improvements. Over the past 40 years, the industry's growth trend has been predicted by Moore's law, and driven by the constant electrical field scaling design methodology. While the intrinsic performance of each device improves over generations, the corresponding interconnects do not. To alleviate this interconnect issue, a three-dimensional (3D) integration concept of transforming longer side to side interconnects into shorter vertical vias by using multiple active layers has attracted much attention. The focus of this thesis is on providing the foundation for 3D heterogeneous integration by investigating methods of growing single crystal materials on the silicon platform and the subsequent low-temperature process flow, through experimental demonstration, theoretical modeling and device structure simplification. First, thin film single crystal GaAs and GaSb were grown on dielectric layers on bulk silicon substrates by the rapid melt growth (RMG) method, using both rapid thermal annealing (RTA) and laser annealing. The relationship between stoichiometry and the crystal structure is discussed according to the theoretical phase diagram and the experimental results. A modified RMG structure is also proposed and demonstrated to solve the potential issue involved in integrating the RMG method into a three-dimensional integrated circuits (3D-IC) process with thick isolation layers. In order to estimate the outcome of the crystallization and to provide further understanding of the physics behind this RMG process, compact models are derived based on classical crystallization theory. Mathematical models including the geometry, the thermal environment and the outcome of the crystallization are built. The initial cooling rate is identified as the key factor for the RMG process. With the ability of integrating multiple materials on silicon substrates, the subsequent process flows using low-temperature-fabrication or simplified device structures are proposed and evaluated to achieve high density 3D integration. A "bonding substrate/monolithic contact" approach is proposed to relieve the thermal constraint from getting the starting single crystal layer without sacrificing the interconnect performance. A low-temperature process using germanium as the channel material is also discussed. Finally, gated thin film resistor structures are designed and compared to the conventional MOSFET structure with a focus on their relative performance and process complexity trade-off for future 3D-IC implementation.

Keywords: Electrical Engineering
Advisor: Plummer James L.
Griffin Peter B. advisor. Thesis advisor
Nishi Yoshio
The design and validation of an automatically-scored constructed-response item type for measuring graphical representation skill [electronic resource]

Graphical representation--the construct that consists of shifting between graphical and non-graphical (e.g., textual, tabular) representations of a problem situation--has a prominent place in state and national standards, and is a skill required for information producers and consumers alike. But because of the cost of hand-scoring items that would require students to produce graphs, current measurement of this important skill is often limited to multiple-choice items that test only students' ability to consume graphs. Because of this misalignment, teachers and students may focus instruction and learning on graph consumption and neglect the important skill of graph production. This work aims to align measurement with educator expectations by introducing an automated scoring system for "graphical-response" items--items that present the student with a problem situation and ask them to sketch a graph that represents that situation. In this dissertation, an interpretive argument (Kane, 1992, 2006) justifying the use of automatically-scored graphical response items to measure graphical representation skill is articulated and then tested through an empirical study. This validation study supports the use of automatically-scored graphical-response items in low-stakes formative assessments, and suggests that with more comprehensive empirical evidence these items could be viable in higher-stakes assessments as well. The dissertation concludes by examining limitations of the study and by detailing potential formative and summative applications.

Keywords: Education.
Advisor: Haertel Edward primary advisor. Thesis advisor
Blikstein Paulo
Osborne Jonathan advisor. Thesis advisor