Chemical mechanical polishing: asperity-based computational modeling at the feature and die scales

Semiconductor manufacturing is the process used to create electronic computer chips. Advancing semiconductor process technology enables the design of new computer chips with lower power requirements and faster speeds. For our society, this enables expanded availability of communications, higher levels of defense, more intelligent modes of transportation, and higher capacity consumer electronics./nChemical mechanical polishing (CMP) is a crucial step in semiconductor manufacturing, as it enables the manufacture of ever-smaller integrated circuits that would not be possible without it. One significant CMP application is the shallow trench isolation (STI) process, where CMP is used to planarize oxide; this oxide subsequently forms dielectric isolation between transistors. While critical and ubiquitous in semiconductor manufacturing, CMP presents many open engineering problems, including the need to reduce chip defects and maintain high efficiency. For STI in particular, the relevant efficiency metric is the planarization efficiency, which evaluates the normalized difference in material removal rate within desired and undesired areas. Many components synergize to make an efficient CMP process, including the polishing pad, the polish material (wafer), the conditioning disk, and the abrasive slurry./nThis thesis focuses on the polishing pad’s role in polishing. As recent advances in additive manufacturing enable a much larger space of possible pad designs, this thesis provides a framework for modeling the efficiency of a pad design, which may guide optimal pad design selection. At present, polishing pad selection requires significant trial and error, which involves testing multiple pad designs (at a high cost) until the CMP tool user identifies a suitable pad design. The CMP tool user repeats this trial and error process for each new chip design since each has its polish requirements. A computational prediction tool that replaces this trial and error process would be beneficial for reducing the development time./nHowever, computational modeling of this process is a highly complex task, as the process contains billions of polygons that would be impossible to represent computationally. I present a framework for simulating the polish between a given chip layout and pad design. In particular, this work enables the simulation of polishes using segmented pads, consisting of a higher elastic modulus contacting material embedded in a lower elastic modulus material. The simulation of a multimaterial CMP pad in such detail is novel. The computational method uses a contact wear model and well-established tribology and contact mechanics techniques. In CMP, the pad’s surface texturing plays a dominant role, as only a few asperities that protrude furthest from the pad are contacting the polish material. This thesis shows the use of microscopy techniques to scan an entire, used CMP pad surface. The computational method then uses that experimental scan as input to contact simulations./nBefore simulating die polishing, we must understand how features with a given size, shape, and height behave when polished by a given pad. This thesis first presents a feature scale model, which predicts a pad’s planarization efficiency when polishing features with known size, shape, and height. This feature scale model operates by simulating the solid contact between the pad and features across the range of relative positions and rotations and subsequently averaging the behavior across those positions and rotations. This information feeds into the die-scale model, which predicts the polish behavior for arrangements of various features./nAs a result of this modeling work, we can look forward to application-specific CMP pad development. Until now, the design of a CMP pad relied heavily upon trial and error at high experimental cost; this model now informs that design process for the first time.

Advisor: Taylor, Hayden K