Reducing Reliance on Buffering and Virtual Channels in Networks-on-Chip

Networks-on-Chip (NoCs) address many shortcomings of traditional interconnects. However, they consume a considerable portion of a chip's total power -- particularly when the utilization is low.As transistor size continues to shrink, we expect NoCs to contribute even more, especially static power. Existing techniques to reduce static power consumption of NoC routers leverage the fact that utilization of NoC resources is low in typical applications. These solutions can be classified into power gating and simplified microarchitectures. Power gating is an efficient technique to reduce the static power of underutilized resources in different types of circuits. For NoC, routers are promising candidates for power gating since they present high idle time. On the other hand, simplified microarchitectures try to reduce router structures as much as they can to save both power and area. However, none of these methods can present a final remedy for a NoC's cost (i.e., power, area and energy). The main root of this cost comes from maintaining correctness. Maintaining correctness is of paramount importance in the design of a computer system. Within a multiprocessor interconnection network, a cornerstone of correctness is guaranteed by having deadlock-free communication at both the protocol and network levels. Designing for deadlock freedom is expensive. Prior solutions eithersacrifice performance or power efficiency to proactively avoid deadlocks or impose high hardware complexity to reactively resolve deadlocks as they occur. As an example, modern network-on-chip designs typically use multiple virtual networks to maintain protocol-level deadlock freedom, at the expense of high power and area overheads. Other techniques involve complex detection and recovery mechanisms which incur additional packet latency. Considering that the probability of deadlocks occurring is low, the additional resources needed to avoid/resolve deadlocks should also be low. In this thesis, we propose three classes of solutions to reduce a NoC's cost: (1) applying power-gating to the NoC routers, (2) simplifying the NoC architecture, and (3) designing efficient deadlock avoidance techniques in NoCs. To reduce static power, our power-gating solutions are based on the fact that most of the packet traversals are straight (e.g., west to east traversal), thus other packets could traverse power-gated routers through a bypass or detour mechanisms while imposing negligible latency overhead. To save both power and area, our simplified NoC architecture reduces underutilized buffer space by leveraging an observation that for most switch traversals, only a single packet is present. Although our power-gating and simplified NoC solutions can save power, they still rely on multiple virtual networks (VNs) to guarantee correctness, leaving considerable power and area savings on the table; to handle both network- and protocol-level deadlocks without using any VNs, we introduce an entirely new class of deadlock-freedomtechnique for interconnection networks called subactive deadlock freedom. Subactive solutions neither avoid nor react to deadlocks but rather let them happen and eventually clean them up. Therefore, this new class of solutions reduces power and area at NX fewer VCs, where N is the number of message types needed by the protocol at no performance cost.

Advisor: Enright Jerger, Natalie NEJ