Synthesis, properties and electronics of graphene nanoribbons [electronic resource]
Keywords: Physics

Graphene, a two-dimensional single atomic layer of graphite, has emerged as a material with interesting physical and chemical properties and high potential for various applications such as sensors, transparent electrodes and electronics. Due to high carrier mobility (up to ~15,000cm2/Vs), graphene has gained much interest as a possible candidate to extend beyond silicon complementary metal-oxide-semiconductor (CMOS) technology for future nano-electronics. Bulk graphene is a semi-metal with zero bandgap, not suitable for high on/off ratio transistors. However, narrow (~ a few nanometer) graphene nanoribbons (GNRs) have been theoretically predicted to be semiconductors that afford high performance room temperature field-effect transistors (FETs). This thesis focuses on the synthesis, physical and chemical properties and electronic devices of GNRs down to a few nanometers wide. We address several critical issues towards large scale graphene electronics and propose a roadmap to achieve this goal. In the first part of this thesis, I will show a chemical route to produce GNRs with width below 10 nanometers, as well as single ribbons with varying widths along their lengths or containing lattice defined graphene junctions. The GNRs were solution phase derived, stably suspended in solvents with noncovalent polymer functionalization, and exhibited ultra-smooth edges with possibly well defined zigzag or armchair edge structures. Electrical transport experiments showed that the bandgaps of these GNRs are inversely proportional to the widths, which confirms that quantum confinement is responsible for the bandgap opening. Unlike single-walled carbon nanotubes (SWNTs), all of the GNRs narrower than ~5nm are semiconductors that afford graphene FETs with on/off ratios of higher than ~105 at room temperature. We then study the chemically derived narrow semiconducting GNR-FETs on 10nm SiO2 systematically. We find that the on state current density can be as high as ~2000[mu]A/[mu]m, carrier mobility is ~200cm2/Vs and scattering mean free path is ~10 nm. Scattering mechanisms by edges, acoustic phonon, and defects are discussed. The semiconducting GNR-FETs are comparable to small diameter (d~1:2 nm) semiconducting SWNT-FETs in on-state current density and on/off ratio. In the second part of this thesis, I will talk about complementary electronics of GNRs. As made GNR device are usually p-doped by adsorbates, but for device applications, it would be useful to access the n-doped material. Individual graphene nanoribbons could be covalently functionalized by nitrogen species through high-power electrical joule heating in NH3, leading to n-type electronic doping consistent with theory. The formation of the carbon-nitrogen bond should occur mostly at the edges of graphene where chemical reactivity is high. We fabricate the first n-type graphene FET that operates at room temperature. Spectroscopic study of graphene oxide (GO) annealed in NH3 provides direct evidence of nitrogen incorporation and sheds light on the possible configurations of nitrogen in carbon networks. In the third part of this thesis, I study the interface between graphene and high dielectric constant (high-k) metal oxides, which are widely used in current silicon technology as gate dielectrics of transistors. We use atomic layer deposition (ALD) to deposit the metal oxides. We find that ALD of metal oxides gives no direct deposition on defect-free pristine graphene. On the edges and defect sites, however, dangling bonds or functional groups can react with ALD precursors to afford active oxide growth. This leads to an interesting and simple way to decorate and visualize defects in graphene. By noncovalent functionalization of graphene with carboxylate-terminated perylene molecules, one can coat graphene with densely packed polar groups for uniform ALD of high-k dielectrics. Uniform high-k coverage is achieved on large pieces of graphene sheets with a size of greater than 5 [mu]m. This method opens the possibility of integrating ultrathin high-k dielectrics in future graphene electronics. Finally, I will describe a scalable lithographic approach to make GNRs narrower than 10nm for future logic applications. We devise a gas phase chemical approach to etch and shrink graphene from the edges without damaging its basal plane. The reaction involves high temperature oxidation of graphene in a slight reducing environment to afford controlled etch rate ([less than or equal to] ~1nm/min). We then fabricate ~20-30nm wide GNR arrays by electron beam lithography, and use the gas phase etching chemistry to narrow the ribbons down to < 10nm. Parallel arrays of ultra-narrow GNRs are obtained. For the first time, high on/off ratio up to ~104 has been achieved at room temperature for field effect transistors built with sub-5nm wide GNR semiconductors derived from lithographic patterning and narrowing. Controlled chemical etching could play important roles in tailoring the dimensions of graphene for large scale device integration.