Fabrication and characterization of vertical silicon nanowire arrays [electronic resource] : a promising building block for thermoelectric devices
Keywords: Mechanical Engineering.

Thermoelectric devices, which convert temperature gradients into electricity, have the potential to harness waste heat to improve overall energy efficiency. However, current thermoelectric devices are not cost-effective for most applications due to their low efficiencies and high material costs. To improve the overall conversion efficiency, thermoelectric materials should possess material properties that closely resemble a "phonon glass" and an "electron crystal". The desired low thermal and high electrical conductivities allow the thermoelectric device to maintain a high temperature gradient while effectively transporting current. Unfortunately, thermal transport and electrical transport are a closely coupled phenomena and it is difficult to independently engineer each specific conduction mechanism in conventional materials. One strategy to realize this is to generate nanostructured silicon (e.g. silicon nanowires (SiNWs)), which have been shown to reduce thermal conductivity ([kappa]) through enhanced phonon scattering while theoretically preserving the electronic properties; therefore, improving the overall device efficiency. The ability to suppress phonon propagation in nanostructured silicon, which has a bulk phonon mean free path ~ 300 nm at 300 K, has raised substantial interest as an ultra-low [kappa] material capable of reducing the thermal conductivity up to three orders of magnitude lower than that of bulk silicon. While the formation of porous silicon and SiNWs has individually been demonstrated as promising methods to reduce [kappa], there is a lack of research investigating the thermal conductivity in SiNWs containing porosity. We fabricated SiNW arrays using top-down etching methods (deep reactive ion etching and metal-assisted chemical etching) and by tuning the diameter with different patterning methods and tuning the internal porosity with different SiNW etching conditions. The effects of both the porosity and the SiNW dimensions at the array scale are investigated by measuring [kappa] of vertical SiNW arrays using a nanosecond time-domain thermoreflectance technique. In addition to thermoelectric devices, vertical SiNW arrays, due to their anisotropic electronic and optical properties, large surface to volume ratios, resistance to Li-ion pulverization, ability to orthogonalize light absorption and carrier transport directions, and trap light, make vertical SiNW arrays important building blocks for various applications. These may include sensors, solar cells, and Li-ion batteries. Many of these applications benefit from vertical SiNW arrays fabricated on non-silicon based substrates which endow the final devices with the properties of flexibility, transparency, and light-weight while removing any performance limitation of the silicon fabrication substrate. We then developed two vertical transfer printing methods (V-TPMs) that are used to detach SiNW arrays from their original fabrication substrates and subsequently attach them to any desired substrate while retaining their vertical alignment over a large area. The transfer of vertically aligned arrays of uniform length SiNWs is desirable to remove the electrical, thermal, optical, and structural impact from the fabrication substrate and also to enable the integration of vertical SiNWs directly into flexible and conductive substrates. Moreover, realization of a thermoelectric device requires the formation of electrical contacts on both sides of the SiNW arrays. We formed metallic contacts on both ends of the SiNW arrays with a mechanical supporting and electrical insulating polymer in between. Electrical characterization of the SiNW devices exhibited good current-voltage (I-V) characteristics independent of substrates materials and bending conditions. We believe the V-TPMs developed in this work have great potential for manufacturing practical thermoelectric devices as well as high performing, scalable SiNW array devices on flexible and conducting substrates.