Quadrature clock generation methods based on parametric capacitance modulation [electronic resource]
Keywords: Electrical Engineering.

The thriving market of high-speed data communication devices demands low-cost and low-power transceivers. Quadrature clock signals are indispensable elements of such communication systems. Conventional quadrature generation methods such as polyphase filters, ring oscillators, frequency dividers, and coupled LC oscillators, either fail to fulfill the stringent phase-noise and phase-accuracy requirements, consume undesirable amounts of power or die area, or do not easily scale to higher frequencies. This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while also reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power- and area-constrained SOCs. Although the general concept of parametric energy transfer at RF frequencies has been utilized before in discrete implementations, we demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. Modulation of a three-terminal capacitor leads to an area-efficient parametric pumping architecture that does not require extensive filtering using passive LC tanks. In this work, two methods of quadrature generation are proposed and experimentally verified. In the first method, a driven, parametrically-pumped-resonator (PPR) based architecture enables generation of quadrature signals from a two-phase signal. It also offers phase-interpolation capability about quadrature, making it suitable for generating a phase-tunable sampling clock in wireline receivers. Two implementations based on this concept are described. The first is a receiver designed in 28nm CMOS for the CEI 28G standard, and which exhibits a BER< 10-12 up to 27Gbps with a 7-inch backplane. The quadrature generation method supports tuning over a 11.55-14.6GHz frequency range while consuming only 3.1mW at 13.5GHz and providing quadrature outputs with an accuracy of 1.5°. The second design is implemented in a 65nm CMOS process, and dissipates 0.96mW while providing quadrature signals with an accuracy of 2 degrees over an input frequency range of 5.3-to-6.75GHz, and supporting a phase interpolation range of 23 to 170 degrees at 6GHz. The measured performance of the prototypes shows that this method is a viable, low-power alternative to traditional methods used in clock and data recovery to generate the sampling clocks. Such methods include delay-locked-loops (DLLs), quadrature ring oscillators followed by phase interpolators and injection-locked oscillators. In the second part, we describe the design of a parametrically pumped quadrature voltage controlled oscillator (PQVCO) that is able to relax considerably the trade-off between phase accuracy and phase noise. The quadrature VCO is based on mutual parametric pumping between two LC resonators. Two designs have been implemented as proof-of-concept for this topology. The first design occupies only 0.11mm2 in 65nm technology, consumes 16.8mW, and achieves a phase noise of -116.7dBc/Hz at a 1MHz offset from a 6.57GHz carrier, while providing CMOS quadrature outputs. The measured phase error is less than 0.3° across the entire tuning range. Relative to state-of-the-art quadrature VCOs, it compares favorably in terms of phase accuracy and phase noise, while being very compact, making it attractive for applications in wireless synthesizers. The second PQVCO provides digital outputs with measured quadrature phase accuracy better than one degree. The phase noise is -113dBc/Hz at a 10MHz offset from a 10.5GHz carrier. Also fabricated in 65nm CMOS, it dissipates 18mW and occupies an area of only 0.074mm2. The oscillator is continuously tunable from 9.75GHz to 10.5GHz, making it suitable for applications in optical front-end transceivers for the 10-Gigabit Ethernet (10.3Gb/s) and OC-192 SONET/SDH (9.95Gb/s) standards, or half-rate CDR in the 20Gb/s range.