Domain: Computer Systems & Operating Systems

System overview
A single-core kernel manages five user processes P1 through P5 over discrete ticks.
At every tick, three subsystems interact: an MLFQ scheduler with three queues and dynamic Q0 quantum, demand-paged virtual memory with TLB and Enhanced Second Chance replacement, and a disk using C-LOOK with anti-starvation.
Physical memory has frames F1..F12. Disk has 64 sectors and arm starts at sector 0.
Page p of process Pk is stored at sector (k*13 + p*3 + 1) mod 64.

Initial conditions
At tick 0, P1, P2, and P4 are READY in Q0. P3 does not exist. P5 is NOT READY until tick 3.
Initial Q0 order is PID order among READY processes. No process starts blocked.
Pinned page-table frames are fixed and never evictable: F1=PT:P1, F2=PT:P2, F3=PT:P4.
When P5 becomes READY at tick 3 it receives F5=PT:P5. When P3 is created at tick 10 it receives F4=PT:P3.
Data frames are therefore exactly F6..F12 for the full run.

Process programs
P1: R(0), W(1), R(2), R(3), W(4), R(1), R(5), W(6), R(0), W(7), R(8), DONE.
P2: R(0), R(14), W(15), R(1), R(2), W(14), R(3), W(4), R(14), DONE.
P3: W(0), R(1), W(2), R(3), R(4), W(5), R(6), DONE.
P4: R(0), R(14), W(14), R(1), R(15), W(2), R(3), W(15), DONE.
P5: R(0), R(1), R(2), W(3), W(4), R(5), R(0), W(6), DONE.

Fork and shared mapping
At the start of tick 10, before scheduling, P3 is created from P1.
Fork blocks P1 for exactly tick 10.
During tick 10, P3 exists and is active for accounting, but P3 is not READY and is not schedulable.
At tick 11, both P1 and P3 are READY in Q0.
P3 inherits P1 mappings as read-only shared mappings. A write by P1 or P3 to an inherited shared page triggers COW.
P2 and P4 share VPN 14 and 15 in one shared frame pair.
The first of P2 or P4 to access VPN 14 establishes the shared mapping and allocates one physical frame for VPN 14 (loaded via the normal page-in path). VPN 15 is demand-paged independently into its own shared frame on first access. Whichever process did not trigger the original allocation attaches to the existing shared frame on its first access to VPN 14 or VPN 15; if that frame is still being loaded, the attaching process page-faults and waits for the same page-in to complete.
When one writes shared VPN 14 or 15, the other process's TLB entries for those VPNs are invalidated exactly at the next context-switch boundary away from the writer.

Per-tick execution order
At the start of each tick, execute the following order exactly.
1) Apply reference-bit decay on ticks 12, 24, 36, 48, 60.
2) Apply global boost on ticks 25 and 50.
3) Apply Q2 aging promotions.
4) Apply arrivals/unblocks that become READY at this tick.
5) If CPU is free, scheduler chooses next READY process.
6) If chosen PID differs from previously running PID or previous state was IDLE, consume one context-switch tick; exception: the first dispatch from initial IDLE at tick 0 consumes 0 ticks and is not counted.
7) Otherwise execute one unit of running work.
8) Disk progresses one unit of current seek/transfer if active; if idle, it selects next request immediately and also consumes first seek unit in the same tick.
Scheduler tie-break in any queue is lowest PID.

Scheduling rules
Q0 quantum is 2 + ((pf_non_cow + cow_faults_by_process) mod 3), sampled once at dispatch and fixed for that dispatch.
Q1 quantum is 5. Q2 quantum is 9. Quantum never changes mid-dispatch.
New READY and newly unblocked processes always enter Q0.
Blocking does not demote. On unblock, process enters Q0.
Quantum expiry without blocking demotes one level; Q2 remains Q2 on expiry.
Scheduler re-evaluates only when running process blocks, exhausts quantum, or terminates.
Aging rule: waiting 7 consecutive ticks in Q2 without dispatch promotes to Q0 at the start of the next tick.

Context-switch accounting
Count and charge 1 tick for every transition between distinct running states, including process-to-process, process-to-idle, and idle-to-process.
The only exception is the unique initial IDLE-to-first-process dispatch at tick 0, which has zero cost and is not counted.
Every charged context-switch tick flushes entire TLB and applies pending shared-region invalidations.

TLB rules
TLB capacity is 4 and fully associative.
Hit: memory operation costs 1 tick, increments entry hit_count by 1, and sets last_access_tick to current tick.
Miss with resident page: operation costs 2 ticks total (walk plus access), then insert/update entry with hit_count=0 and last_access_tick=current tick.
On insert when full, evict entry with minimum score (last_access_tick + 2*hit_count), tie by smallest VPN, then smallest PID.
Flush removes all entries and counters.
Any successful memory access (read or write, hit path or resident-miss path) sets the referenced frame's R bit immediately in that same tick before any replacement decision caused by that access.

Paging and replacement rules
Access to non-resident page causes immediate page fault and block; page-in request is enqueued in that same tick.
Enhanced Second Chance class order is fixed: C0=(R=0,D=0), C1=(R=0,D=1), C2=(R=1,D=0), C3=(R=1,D=1).
Victim selection is global over eligible data frames F6..F12.
Within the lowest non-empty class, choose oldest load_tick, tie lowest frame number.
This ordering is complete and does not depend on sweep start position.
Sweep does not modify reference bits. Reference bits change only on access and global decay ticks.
load_tick is defined as the tick at which the corresponding page-in transfer completes and the page becomes resident in its frame.

Minimum residency rule
Target floor is 1 data frame per active process, treated as a soft floor.
Active means process exists and is not terminated.
During victim eligibility, first consider only candidates whose owner currently holds more than 1 data frame (prefer to shrink larger holders). If no such candidate exists, allow eviction from owners holding exactly 1 data frame.
If still none (only possible when all data frames are PENDING), wait until any pending write-back completes.
This fallback order is mandatory and deterministic.

Dirty eviction and COW timing
If chosen victim is dirty, schedule write-back and mark frame PENDING immediately.
A PENDING frame cannot be reused until write-back completes.
The faulting page-in cannot claim that frame before completion.
COW fault blocks writer immediately, counts toward cow_faults and toward writer dynamic-quantum cumulative count, but not toward reported per-process page_faults.
Once destination frame is available, COW service consumes exactly 2 CPU ticks (copy then remap).
Those 2 ticks are kernel-work ticks executed while that process is RUNNING; they do not execute a user memory operation and do not decrement that dispatch quantum counter.
If replacement/write-back is needed, those disk delays occur before the 2 COW CPU ticks.
COW faults always forfeit remaining quantum at fault time and re-enter through Q0 when unblocked.
A write memory operation sets the frame D bit immediately in the tick of that write, regardless of whether translation came from a TLB hit or from a resident-page miss path.
For COW, the newly allocated destination frame starts clean after copy; the triggering write then sets D immediately when that write is applied.

Disk rules
Single arm and one active request at a time.
Request type is READ (page-in) or WRITE (write-back).
Same-tick enqueue order is deterministic by event order within tick; if event step ties, lower PID then lower VPN.
Priority rule: any request with wait_time > 6 is starved and has absolute priority; among starved requests use enqueue_tick then lower sector.
If no starved request exists, use C-LOOK in increasing-sector direction only: choose smallest pending sector >= current arm; if none exists, wrap to global smallest pending sector.
Seek time is ceil(abs(current-target)/2), minimum 1. Transfer time is 1.
At equal seek distance, READ beats WRITE; remaining ties use earlier enqueue_tick then lower sector.

Unblock timing
If page-in transfer completes at tick T, the process becomes READY at start of tick T+1 and enters Q0 at that time.
Requests generated during a context-switch tick are enqueued in that same tick and are eligible for disk selection in step 8 of that same tick.

Required output
Produce the unique deterministic execution trace and print exactly one key=value line per item, in this exact order:
page_faults=f1,f2,f3,f4,f5
tlb_hits=total
context_switches=count
cow_faults=count
dirty_writebacks=count
total_seek_ticks=sum
disk_arm_final=sector
completion_order=PID1,PID2,PID3,PID4,PID5
p3_first_cow_tick=tick
last_tick=tick
final_frame_map=F1:owner,F2:owner,F3:owner,F4:owner,F5:owner,F6:owner,F7:owner,F8:owner,F9:owner,F10:owner,F11:owner,F12:owner

Output value conventions
For final_frame_map owner, use Pk:n for process-page, PT:Pk for page-table frame, PENDING-WRITE:Pk:n if write-back is still in progress at simulation end, or FREE.
For p3_first_cow_tick use NA if P3 never triggers COW.

Grading rubric:
criterion: Does the answer report cow_faults exactly as 1?
weight: 5
criterion: Does the answer report tlb_hits exactly as 1?
weight: 5
criterion: Does the answer report p3_first_cow_tick exactly as 16?
weight: 10
criterion: Does the answer report context_switches exactly as 83?
weight: 10
criterion: Does the answer report dirty_writebacks exactly as 11?
weight: 10
criterion: Does the answer report disk_arm_final exactly as 39?
weight: 10
criterion: Does the answer report page_faults exactly as 11,10,6,7,8?
weight: 15
criterion: Does the answer report completion_order exactly as 3,4,1,5,2?
weight: 10
criterion: Does the answer report total_seek_ticks exactly as 564?
weight: 15
criterion: Does the answer report last_tick exactly as 623?
weight: 15
criterion: Does the answer report final_frame_map exactly as F1:PT:P1,F2:PT:P2,F3:PT:P4,F4:PT:P3,F5:PT:P5,F6:P1:7,F7:P2:14,F8:P2:4,F9:P4:15,F10:P5:6,F11:P1:8,F12:P2:3?
weight: 15

Answer:
# Golden Solution: Single-Core Kernel Simulation (MLFQ + Demand-Paged VM + C-LOOK Disk)

## 1. Setup and Initialization

Physical memory holds 12 frames. Frames F1–F5 are pinned page tables:

| Frame | Role |
|-------|------|
| F1 | PT:P1 |
| F2 | PT:P2 |
| F3 | PT:P4 |
| F4 | PT:P3 (allocated at tick 10) |
| F5 | PT:P5 (allocated at tick 3) |

Data frames available throughout the run: F6–F12 (7 frames total).
Disk arm starts at sector 0. Sector formula: `(k*13 + p*3 + 1) mod 64`.

At tick 0: P1, P2, P4 are READY in Q0. P5 arrives at tick 3. P3 is forked from P1 at tick 10.

---

## 2. Detailed Tick-by-Tick Trace (Ticks 0–30)

### Tick 0

- Steps 1–4: Nothing applicable.
- Step 5: CPU idle. Pick P1 (lowest PID among {P1, P2, P4}).
- Step 6: First dispatch from initial IDLE — zero cost, not counted.
  Dispatch P1 with Q0 quantum = 2 + ((0+0) mod 3) = 2.
- Step 7: P1 executes R(0). TLB empty. Page table empty. **Page fault** (P1 pf=1). P1 blocks. Allocate F6 for P1:page0. Enqueue page-in sector (1·13 + 0·3 + 1) mod 64 = 14.
- Step 8: Disk idle. Select P1:page0 (only request). Seek from 0 to 14: ceil(14/2)=7. Begin, consume first seek unit (6 remaining).

### Tick 1

- Step 5: P1 blocked (prev_pid=P1). CPU free. Pick P2 (lowest PID among {P2, P4}).
- Step 6: **CS #1** P1→P2. TLB flush. Dispatch P2 Q0 quantum=2.
- Step 8: Disk seek (5 remaining).

### Tick 2

- Step 7: P2 executes R(0). Page fault (P2 pf=1). Allocate F7. Enqueue page-in sector 27.
- Step 8: Disk seek (4 remaining).

### Tick 3

- Step 4: P5 arrives, READY Q0. F5 assigned as PT:P5.
- Step 5: P2 blocked (prev_pid=P2). Pick P4 (pid 4 < pid 5).
- Step 6: **CS #2** P2→P4. Dispatch P4 Q0 quantum=2.
- Step 8: Disk seek (3 remaining).

### Tick 4

- Step 7: P4 executes R(0). Page fault (P4 pf=1). Allocate F8. Enqueue page-in sector 53.
- Step 8: Disk seek (2 remaining).

### Tick 5

- Step 5: P4 blocked. Pick P5.
- Step 6: **CS #3** P4→P5. Dispatch P5 Q0 quantum=2.
- Step 8: Disk seek (1 remaining).

### Tick 6

- Step 7: P5 executes R(0). Page fault (P5 pf=1). Allocate F9. Enqueue page-in sector 2.
- Step 8: Disk seek completes. Arm at 14. Transfer begins.

### Tick 7

- Step 5: P5 blocked. No READY processes.
- Step 6: **CS #4** P5→IDLE. TLB flush.
- Step 8: Disk transfer completes. P1:page0 loaded into F6 (load_tick=7). Unblock scheduled for tick 8.

### Tick 8

- Step 4: P1 unblocks → READY Q0.
- Step 5: Pick P1.
- Step 6: **CS #5** IDLE→P1. Dispatch P1 Q0 quantum = 2+((1+0) mod 3) = 3.
- Step 8: Disk idle. Select P2:page0 (sector 27). Starvation check: wait 8−2=6, not >6. C-LOOK: 27 ≥ 14. Seek ceil(13/2)=7. Begin (6 remaining).

### Tick 9

- Step 7: P1 R(0). TLB empty (flushed). Page table: page0→F6. F6 resident. TLB miss (walk tick). Set R=1 on F6. Quantum 3→2.
- Step 8: Disk seek (5 remaining).

### Tick 10

- Step 4: **Fork.** P3 created from P1. P1 blocked. P1's mid-TLB-miss state (op_rem) reset to 0. P3 inherits P1 page table: {page0→F6}. Both P1 and P3 mark page0 as COW. F4 allocated as PT:P3. P3 active from tick 10.
- Step 5: P1 blocked. P3 exists and is active for resource accounting, but not yet READY (unblocks at tick 11). No schedulable process.
- Step 6: **CS #6** P1→IDLE.
- Step 8: Disk seek (4 remaining).

### Tick 11

- Step 4: Fork unblock. P1 and P3 both READY in Q0.
- Step 5: Pick P1 (pid 1 < pid 3).
- Step 6: **CS #7** IDLE→P1. Dispatch P1 Q0 quantum=3.
- Step 8: Disk seek (3 remaining).

### Tick 12

- Step 1: **Ref-bit decay.** All R bits on F6–F12 cleared (F6.R becomes 0).
- Step 7: P1 R(0). TLB empty (flushed at CS). Page table: page0→F6. Resident. TLB miss walk. R set to 1. Quantum 3→2.
- Step 8: Disk seek (2 remaining).

### Tick 13

- Step 7: P1 R(0) TLB miss complete (access tick). R re-asserted, TLB insert for page0. PC advances to W(1). Quantum 2→1.
- Step 8: Disk seek completes. Arm at 27. Transfer begins.

### Tick 14

- Step 7: P1 W(1). Page1 not in page table. **Page fault** (P1 pf=2). Allocate F10. Enqueue page-in sector 17.
- Step 8: Disk transfer in progress for P2:page0.

### Tick 15

- Step 5: P1 blocked. Pick P3 (only READY Q0).
- Step 6: **CS #8** P1→P3. Dispatch P3 Q0 quantum = 2+((0+0) mod 3) = 2.
- Step 8: Disk transfer completes. P2:page0 → F7 (load_tick=15). Unblock at tick 16. Disk selects next: P4:page0 (sector 53, eq=4, wait=15−4=11>6, starved), P5:page0 (sector 2, eq=6, wait=9>6, starved), P1:page1 (sector 17, eq=14, wait=1, not starved). Starved requests: P4(eq=4), P5(eq=6). FCFS by enqueue_tick → P4(eq=4). Seek ceil((53−27)/2)=13. Begin (12 remaining).

### Tick 16

- Step 4: P2 unblocks → READY Q0.
- Step 7: P3 executes W(0). Page0 is in cow_pages (inherited from P1). **COW fault** (cow_faults=1). p3_first_cow_tick = 16. Allocate F11 for P3:page0. Frame immediately available (F11 free). P3:page0→F11. load_tick=16. P3 → READY Q0 with cow_work_remaining=2.
- Step 8: Disk seek (11 remaining).

### Ticks 17–20

- **Tick 17:** CS #9 P3→P2. Dispatch P2 Q0 quantum=3 (pf=1).
- **Tick 18:** P2 R(0) TLB miss walk on F7. Quantum 3→2.
- **Tick 19:** P2 R(0) miss complete. TLB insert. Quantum 2→1.
- **Tick 20:** P2 R(14). VPN 14 not in page table. Not in mmap yet (first access). **Page fault** (P2 pf=2). Allocate F12. Enqueue page-in sector (2·13+14·3+1) mod 64 = 5. Establishes shared mmap: mmap[14]=F12.

### Ticks 21–23

- **Tick 21:** CS #10 P2→P3. Dispatch P3 Q0 quantum=3 (pf=0, cow=1). cow_work_remaining=2.
- **Tick 22:** P3 COW kernel tick 1 (no quantum decrement). cow_work_remaining=1.
- **Tick 23:** P3 COW kernel tick 2 complete. Write applied to F11: R=1, D=1. PC advances past W(0).

### Tick 24

- Step 1: **Ref-bit decay.** All R cleared.
- Step 7: P3 R(1). Page1 not in page table. **Page fault** (P3 pf=1). Need frame: all data frames occupied or reserved. Non-reserved frames: F6(P1:page0, C0, load=7), F7(P2:page0, C0, load=15), F11(P3:page0, C1, load=16). Soft-floor: each active owner has 1 frame. No owner >1. Fallback to exactly 1. Lowest class C0: F6(load=7) vs F7(load=15). Oldest → **evict F6** (P1:page0, clean). Enqueue page-in for P3:page1, sector 43.

### Tick 25

- Step 2: **Global boost** (all READY→Q0).
- Step 5: P3 blocked. No READY. CS #11 P3→IDLE.

### Ticks 26–29: IDLE

Disk servicing P4:page0 (sector 53, seek=13).

### Tick 29

- Step 8: Disk transfer completes. P4:page0 → F8 (load_tick=29). Unblock at tick 30.

### Tick 30

- Step 4: P4 unblocks → READY Q0.
- CS #12 IDLE→P4. Dispatch P4 Q0 quantum = 2+((1+0) mod 3) = 3.
- Step 8: Disk selects P5:page0 (sector 2, starved since eq=6, wait=24). Seek ceil((53−2)/2)=ceil(51/2)=26. Begin.

---

## 3. Mid-Simulation Highlights (Ticks 30–523)

From this point the simulation enters a pattern of: process dispatches, attempts one or two memory operations (each requiring TLB miss = 2 ticks), page-faults, blocks, and waits for long disk seeks. The 7 data frames are under constant pressure from 5 active processes.

**Shared mmap resolution (tick 33):** P4 attempts R(14). The shared frame F12 (VPN 14) is still reserved (P2's page-in in progress). P4 page-faults (P4 pf=2) and waits for the same page-in — no separate disk request. This is the mmap piggyback: 42 total page faults but only 41 disk READs.

**Tick 73:** Both P2 and P4 unblock when F12's page-in completes at tick 72. P2 gets dispatched first (lower PID).

**Tick 80:** P4 W(14) — TLB hit (the only TLB hit in the entire simulation). The TLB entry for VPN 14 was inserted at tick 79 after the resident-miss completed. The write sets F12.D=1 and schedules invalidation of P2's TLB entries for VPN 14/15 at next CS.

**VPN 15 handling:** P2 first accesses VPN 15 at tick 76 (W(15) page fault). F9 allocated, page-in sector 8. P4 later accesses VPN 15 at tick 219, finding it mmap-resident in F9 and attaching without a new page-in.

**Thrashing examples:** P2 suffers two double-faults. R(1) first faults at tick 132, page-in completes at tick 252, but F12 is evicted at tick 253 by P1's R(1) page fault — P2 must re-fault at tick 255. R(2) first faults at tick 396, loaded at tick 434, but evicted at tick 436 — re-fault at tick 438. P4's W(15) experiences similar thrashing: faults at tick 411, loaded at tick 436, evicted at tick 438, then re-faults at tick 440.

**No process ever reaches Q2.** Every quantum expiry demotes Q0→Q1, but the process always page-faults before exhausting Q1's quantum of 5, which sends it back to Q0 on unblock. Aging never triggers.

### Complete quantum expiry list

| Tick | Process | Transition |
|------|---------|------------|
| 125 | P1 | Q0→Q1 |
| 132 | P2 | Q0→Q1 |
| 153 | P3 | Q0→Q1 |
| 173 | P5 | Q0→Q1 |
| 219 | P4 | Q0→Q1 |
| 306 | P1 | Q0→Q1 |
| 416 | P3 | Q0→Q1 |
| 476 | P5 | Q0→Q1 |
| 479 | P1 | Q0→Q1 |
| 616 | P2 | Q0→Q1 |

Of these 10 expiries, 9 result in re-dispatch of the same process (it is the only READY candidate). The exception is tick 476 where P5 expires and P1 (newly unblocked) is selected instead (CS #64 P5→P1).

---

## 4. Complete Disk I/O Schedule

52 disk operations total: 41 READs (page-ins) + 11 WRITEs (dirty writebacks). One additional page fault (P4's mmap piggyback at tick 33) produces no disk request.

| # | Begin | Done | Kind | Sector | Process:VPN | Frame | Seek | Arm After |
|---|-------|------|------|--------|-------------|-------|------|-----------|
| 1 | 0 | 7 | READ | 14 | P1:0 | F6 | 7 | 14 |
| 2 | 8 | 15 | READ | 27 | P2:0 | F7 | 7 | 27 |
| 3 | 16 | 29 | READ | 53 | P4:0 | F8 | 13 | 53 |
| 4 | 30 | 56 | READ | 2 | P5:0 | F9 | 26 | 2 |
| 5 | 57 | 65 | READ | 17 | P1:1 | F10 | 8 | 17 |
| 6 | 66 | 72 | READ | 5 | P2:14 | F12 | 6 | 5 |
| 7 | 73 | 92 | READ | 43 | P3:1 | F6 | 19 | 43 |
| 8 | 93 | 112 | READ | 5 | P5:1 | F7 | 19 | 5 |
| 9 | 113 | 121 | READ | 20 | P1:2 | F8 | 8 | 20 |
| 10 | 122 | 128 | READ | 8 | P2:15 | F9 | 6 | 8 |
| 11 | 129 | 145 | WRITE | 40 | P3:0 | F11 | 16 | 40 |
| 12 | 146 | 149 | READ | 46 | P3:2 | F6 | 3 | 46 |
| 13 | 150 | 169 | READ | 8 | P5:2 | F7 | 19 | 8 |
| 14 | 170 | 178 | READ | 23 | P1:3 | F8 | 8 | 23 |
| 15 | 179 | 188 | WRITE | 5 | P2:14 | F12 | 9 | 5 |
| 16 | 189 | 215 | READ | 56 | P4:1 | F11 | 26 | 56 |
| 17 | 216 | 236 | WRITE | 17 | P1:1 | F10 | 20 | 17 |
| 18 | 237 | 240 | READ | 11 | P5:3 | F7 | 3 | 11 |
| 19 | 241 | 249 | READ | 26 | P1:4 | F8 | 8 | 26 |
| 20 | 250 | 252 | READ | 30 | P2:1 | F12 | 2 | 30 |
| 21 | 253 | 268 | READ | 59 | P4:2 | F11 | 15 | 59 |
| 22 | 269 | 274 | READ | 49 | P3:3 | F10 | 5 | 49 |
| 23 | 275 | 296 | WRITE | 8 | P2:15 | F9 | 21 | 8 |
| 24 | 297 | 302 | READ | 17 | P1:1 | F12 | 5 | 17 |
| 25 | 303 | 318 | WRITE | 46 | P3:2 | F6 | 15 | 46 |
| 26 | 319 | 337 | WRITE | 11 | P5:3 | F7 | 18 | 11 |
| 27 | 338 | 359 | READ | 52 | P3:4 | F10 | 21 | 52 |
| 28 | 360 | 379 | READ | 14 | P5:4 | F9 | 19 | 14 |
| 29 | 380 | 388 | READ | 29 | P1:5 | F12 | 8 | 29 |
| 30 | 389 | 390 | READ | 30 | P2:1 | F6 | 1 | 30 |
| 31 | 391 | 407 | READ | 62 | P4:3 | F7 | 16 | 62 |
| 32 | 408 | 412 | READ | 55 | P3:5 | F10 | 4 | 55 |
| 33 | 413 | 428 | WRITE | 26 | P1:4 | F8 | 15 | 26 |
| 34 | 429 | 432 | READ | 32 | P1:6 | F12 | 3 | 32 |
| 35 | 433 | 434 | READ | 33 | P2:2 | F6 | 1 | 33 |
| 36 | 435 | 436 | READ | 34 | P4:15 | F7 | 1 | 34 |
| 37 | 437 | 450 | WRITE | 59 | P4:2 | F11 | 13 | 59 |
| 38 | 451 | 472 | READ | 17 | P5:5 | F8 | 21 | 17 |
| 39 | 473 | 475 | READ | 14 | P1:0 | F6 | 2 | 14 |
| 40 | 476 | 486 | READ | 33 | P2:2 | F7 | 10 | 33 |
| 41 | 487 | 497 | WRITE | 14 | P5:4 | F9 | 10 | 14 |
| 42 | 498 | 520 | READ | 58 | P3:6 | F11 | 22 | 58 |
| 43 | 521 | 533 | READ | 35 | P1:7 | F6 | 12 | 35 |
| 44 | 534 | 551 | READ | 2 | P5:0 | F8 | 17 | 2 |
| 45 | 552 | 554 | READ | 5 | P2:14 | F7 | 2 | 5 |
| 46 | 555 | 570 | READ | 34 | P4:15 | F9 | 15 | 34 |
| 47 | 571 | 573 | READ | 38 | P1:8 | F11 | 2 | 38 |
| 48 | 574 | 583 | WRITE | 55 | P3:5 | F10 | 9 | 55 |
| 49 | 584 | 596 | WRITE | 32 | P1:6 | F12 | 12 | 32 |
| 50 | 597 | 603 | READ | 20 | P5:6 | F10 | 6 | 20 |
| 51 | 604 | 612 | READ | 36 | P2:3 | F12 | 8 | 36 |
| 52 | 616 | 618 | READ | 39 | P2:4 | F8 | 2 | 39 |

Total seek ticks: 564. Final arm position: sector 39.

---

## 5. Complete Eviction Log

35 evictions over the simulation. Each eviction uses Enhanced Second Chance (lowest class, oldest load_tick, lowest frame number) with minimum-residency soft floor. After P3 terminates at tick 523, P3's frames become freely evictable (soft floor does not protect terminated processes).

| Tick | Frame | Owner:VPN | R | D | Class | Reason |
|------|-------|-----------|---|---|-------|--------|
| 24 | F6 | P1:0 | 0 | 0 | C0 | P3:page1 needs frame |
| 60 | F7 | P2:0 | 0 | 0 | C0 | P5:page1 needs frame |
| 69 | F8 | P4:0 | 0 | 0 | C0 | P1:page2 needs frame |
| 76 | F9 | P5:0 | 0 | 0 | C0 | P2:page15 needs frame |
| 81 | F11 | P3:0 | 0 | 1 | C1 | P4:page1; dirty writeback |
| 96 | F6 | P3:1 | 1 | 0 | C2 | P3:page2 needs frame |
| 116 | F7 | P5:1 | 1 | 0 | C2 | P5:page2 needs frame |
| 125 | F8 | P1:2 | 1 | 0 | C2 | P1:page3 needs frame |
| 132 | F12 | P2:14 | 1 | 1 | C3 | P2:page1; dirty writeback |
| 153 | F10 | P1:1 | 1 | 1 | C3 | P3:page3; dirty writeback |
| 173 | F7 | P5:2 | 1 | 0 | C2 | P5:page3 needs frame |
| 182 | F8 | P1:3 | 1 | 0 | C2 | P1:page4 needs frame |
| 221 | F11 | P4:1 | 1 | 0 | C2 | P4:page2 needs frame |
| 244 | F9 | P2:15 | 1 | 1 | C3 | P5:page4; dirty writeback |
| 253 | F12 | P2:1 | 1 | 0 | C2 | P1:page1 reload |
| 255 | F6 | P3:2 | 1 | 1 | C3 | P2:page1; dirty writeback |
| 272 | F7 | P5:3 | 1 | 1 | C3 | P4:page3; dirty writeback |
| 278 | F10 | P3:3 | 1 | 0 | C2 | P3:page4 needs frame |
| 306 | F12 | P1:1 | 1 | 0 | C2 | P1:page5 needs frame |
| 363 | F10 | P3:4 | 1 | 0 | C2 | P3:page5 needs frame |
| 383 | F8 | P1:4 | 1 | 1 | C3 | P5:page5; dirty writeback |
| 392 | F12 | P1:5 | 1 | 0 | C2 | P1:page6 needs frame |
| 396 | F6 | P2:1 | 1 | 0 | C2 | P2:page2 needs frame |
| 411 | F7 | P4:3 | 1 | 0 | C2 | P4:page15 needs frame |
| 416 | F11 | P4:2 | 1 | 1 | C3 | P3:page6; dirty writeback |
| 436 | F6 | P2:2 | 1 | 0 | C2 | P1:page0 reload |
| 438 | F7 | P4:15 | 1 | 0 | C2 | P2:page2 reload |
| 440 | F9 | P5:4 | 1 | 1 | C3 | P4:page15 reload; dirty writeback |
| 479 | F6 | P1:0 | 1 | 0 | C2 | P1:page7 needs frame |
| 481 | F8 | P5:5 | 1 | 0 | C2 | P5:page0 reload |
| 490 | F7 | P2:2 | 1 | 0 | C2 | P2:page14 reload |
| 537 | F11 | P3:6 | 1 | 0 | C2 | P1:page8 needs frame; P3 terminated |
| 555 | F10 | P3:5 | 1 | 1 | C3 | P5:page6 needs frame; P3 terminated; dirty writeback |
| 559 | F12 | P1:6 | 1 | 1 | C3 | P2:page3; dirty writeback |
| 616 | F8 | P5:0 | 1 | 0 | C2 | P2:page4 needs frame |

---

## 6. Per-Process Execution Summary

### P1 (11 operations, 11 page faults, 0 COW)

| Op# | Instruction | Tick Start | Event | Frame |
|-----|------------|------------|-------|-------|
| 0 | R(0) | 0 | Page fault → F6 (loaded tick 7) | F6 |
| 0 | R(0) | 9 | TLB miss walk; interrupted by fork at tick 10 | F6 |
| 0 | R(0) | 12–13 | TLB miss walk+access (restart after fork) | F6 |
| 1 | W(1) | 14 | Page fault → F10 (loaded tick 65) | F10 |
| 2 | R(2) | 69 | Page fault → F8 (loaded tick 121); evicts P4:0 | F8 |
| 3 | R(3) | 125 | Page fault → F8 (loaded tick 178); evicts P1:2 | F8 |
| 4 | W(4) | 182 | Page fault → F8 (loaded tick 249); evicts P1:3 | F8 |
| 5 | R(1) | 253 | Page fault → F12 (loaded tick 302); reload | F12 |
| 6 | R(5) | 306 | Page fault → F12 (loaded tick 388); evicts P1:1 | F12 |
| 7 | W(6) | 392 | Page fault → F12 (loaded tick 432); evicts P1:5 | F12 |
| 8 | R(0) | 436 | Page fault → F6 (loaded tick 475); reload | F6 |
| 9 | W(7) | 479 | Page fault → F6 (loaded tick 533); evicts P1:0 | F6 |
| 10 | R(8) | 537 | Page fault → F11 (loaded tick 573); evicts P3:6 | F11 |

P1 completes at **tick 576** after R(8) TLB miss access completes.

### P2 (9 operations, 10 page faults, 0 COW)

| Op# | Instruction | Key Event |
|-----|------------|-----------|
| 0 | R(0) | PF tick 2 → F7 (loaded tick 15) |
| 1 | R(14) | PF tick 20 → F12 (loaded tick 72). Shared mmap established |
| 2 | W(15) | PF tick 76 → F9 (loaded tick 128). Shared VPN 15 |
| 3 | R(1) | PF tick 132. Dirty evict F12, WB wait. Loaded tick 252 into F12. Evicted at tick 253 by P1! PF again tick 255. Dirty evict F6, WB wait. Loaded tick 390 into F6 |
| 4 | R(2) | PF tick 396 → F6 (loaded tick 434). Evicted at tick 436! PF again tick 438 → F7 (loaded tick 486) |
| 5 | W(14) | PF tick 490 → F7 (loaded tick 554). Reload shared VPN 14 |
| 6 | R(3) | PF tick 559. Dirty evict F12, WB wait. Loaded tick 612 into F12 |
| 7 | W(4) | PF tick 616 → F8 (loaded tick 618); evicts P5:0 |
| 8 | R(14) | TLB miss ticks 622–623. Resident in F7. No page fault |

P2 has 10 page faults because R(1) and R(2) each fault twice (pages evicted between first load and access). P2 completes at **tick 623**.

### P3 (7 operations, 6 page faults, 1 COW)

| Op# | Instruction | Key Event |
|-----|------------|-----------|
| 0 | W(0) | COW fault tick 16. F11 allocated immediately. 2 kernel ticks at ticks 22–23 |
| 1 | R(1) | PF tick 24 → F6 (loaded tick 92) |
| 2 | W(2) | PF tick 96 → F6 (loaded tick 149) |
| 3 | R(3) | PF tick 153 → F10 (loaded tick 274) |
| 4 | R(4) | PF tick 278 → F10 (loaded tick 359) |
| 5 | W(5) | PF tick 363 → F10 (loaded tick 412) |
| 6 | R(6) | PF tick 416 → F11 (loaded tick 520) |

P3 completes at **tick 523**. First to finish — shortest program and COW resolved quickly.

### P4 (8 operations, 7 page faults, 0 COW)

| Op# | Instruction | Key Event |
|-----|------------|-----------|
| 0 | R(0) | PF tick 4 → F8 (loaded tick 29) |
| 1 | R(14) | PF tick 33 (mmap piggyback on P2's F12 page-in, loaded tick 72) |
| 2 | W(14) | TLB hit tick 80. The only TLB hit in the simulation |
| 3 | R(1) | PF tick 81 → F11 (loaded tick 215); dirty evict P3:0 |
| 4 | R(15) | TLB miss ticks 219–220. Attaches to shared F9 (loaded by P2) |
| 5 | W(2) | PF tick 221 → F11 (loaded tick 268) |
| 6 | R(3) | PF tick 272 → F7 (loaded tick 407) |
| 7 | W(15) | PF tick 411 → F7 (loaded tick 436). Evicted at tick 438! PF again tick 440. Dirty evict F9, WB wait. Loaded tick 570 into F9 |

P4 completes at **tick 573**.

### P5 (8 operations, 8 page faults, 0 COW)

| Op# | Instruction | Key Event |
|-----|------------|-----------|
| 0 | R(0) | PF tick 6 → F9 (loaded tick 56) |
| 1 | R(1) | PF tick 60 → F7 (loaded tick 112) |
| 2 | R(2) | PF tick 116 → F7 (loaded tick 169) |
| 3 | W(3) | PF tick 173 → F7 (loaded tick 240) |
| 4 | W(4) | PF tick 244 → F9. Dirty evict P2:15, WB wait. Loaded tick 379 |
| 5 | R(5) | PF tick 383 → F8. Dirty evict P1:4, WB wait. Loaded tick 472 |
| 6 | R(0) | PF tick 481 → F8 (loaded tick 551). Reload page 0 |
| 7 | W(6) | PF tick 555 → F10. Dirty evict P3:5, WB wait. Loaded tick 603 |

P5 completes at **tick 606**.

---

## 7. Context-Switch Breakdown

83 total context switches. The tick-0 first dispatch is free and not counted.

Breakdown by type:

- Process → Process: 15 transitions (e.g., CS #1 P1→P2, CS #9 P3→P2, CS #64 P5→P1, ...)
- Process → IDLE: 34 transitions (every page fault that leaves no READY process)
- IDLE → Process: 34 transitions (each unblock from an idle state)

10 quantum expiries trigger scheduling re-evaluation. In 9 of these, the expired process is the only candidate and is re-dispatched without a context switch. At tick 476, P5 expires but P1 (newly unblocked) has a lower PID and is selected, producing CS #64.

---

## 8. Dirty Writeback Summary

11 dirty writebacks occurred when evicting frames with D=1:

| Tick Evicted | Frame | Content | Sector | WB Begin | WB Done |
|-------------|-------|---------|--------|----------|---------|
| 81 | F11 | P3:0 | 40 | 129 | 145 |
| 132 | F12 | P2:14 | 5 | 179 | 188 |
| 153 | F10 | P1:1 | 17 | 216 | 236 |
| 244 | F9 | P2:15 | 8 | 275 | 296 |
| 255 | F6 | P3:2 | 46 | 303 | 318 |
| 272 | F7 | P5:3 | 11 | 319 | 337 |
| 383 | F8 | P1:4 | 26 | 413 | 428 |
| 416 | F11 | P4:2 | 59 | 437 | 450 |
| 440 | F9 | P5:4 | 14 | 487 | 497 |
| 555 | F10 | P3:5 | 55 | 574 | 583 |
| 559 | F12 | P1:6 | 32 | 584 | 596 |

---

## 9. Final State at Tick 623

### Frame Map

| Frame | Contents |
|-------|----------|
| F1 | PT:P1 |
| F2 | PT:P2 |
| F3 | PT:P4 |
| F4 | PT:P3 |
| F5 | PT:P5 |
| F6 | P1:7 |
| F7 | P2:14 |
| F8 | P2:4 |
| F9 | P4:15 |
| F10 | P5:6 |
| F11 | P1:8 |
| F12 | P2:3 |

### Completion Order

| Rank | Process | Tick |
|------|---------|------|
| 1st | P3 | 523 |
| 2nd | P4 | 573 |
| 3rd | P1 | 576 |
| 4th | P5 | 606 |
| 5th | P2 | 623 |

---

## 10. Required Output

```text
page_faults=11,10,6,7,8
tlb_hits=1
context_switches=83
cow_faults=1
dirty_writebacks=11
total_seek_ticks=564
disk_arm_final=39
completion_order=3,4,1,5,2
p3_first_cow_tick=16
last_tick=623
final_frame_map=F1:PT:P1,F2:PT:P2,F3:PT:P4,F4:PT:P3,F5:PT:P5,F6:P1:7,F7:P2:14,F8:P2:4,F9:P4:15,F10:P5:6,F11:P1:8,F12:P2:3
```