Domain: Computer Systems & Operating Systems

# PROMPT

Simulate Tomasulo's Algorithm for out-of-order execution with the following configuration:

EXECUTION LATENCIES (by instruction type):
- ADD/SUB: 2 cycles
- MUL: 4 cycles
- DIV: 8 cycles
- LOAD: 3 cycles (includes memory access)

RESERVATION STATIONS:
- 3 Add/Sub stations: Add1, Add2, Add3
- 2 Mul/Div stations: Mul1, Mul2
- 2 Load stations: Load1, Load2

There are no structural hazards on functional units. Every reservation station that is ready to execute can begin execution immediately regardless of how many other stations of the same type are already executing.

REGISTER FILE: F0, F2, F4, F6, F8, F10 (all initially ready with value 0). Integer base registers R1 and R2 are always ready and are not tracked by the algorithm.

RULES:
1. Issue: One instruction issues per cycle in program order, provided a reservation station of the correct type is available. If no station is available, the instruction stalls and no later instruction can issue.
2. Execute: Begins the cycle AFTER all source operands are available. An operand broadcast on cycle T is considered available starting cycle T+1.
3. Write: Results broadcast on the CDB exactly one cycle after execution completes. If execution ends in cycle E, the write occurs in cycle E+1.
4. CDB Conflict: If multiple instructions are ready to write in the same cycle, the instruction in the station with the lowest name (alphabetical, then numeric) wins. Full priority order: Add1 < Add2 < Add3 < Load1 < Load2 < Mul1 < Mul2.
5. Stations freed: A reservation station is freed in the same cycle its instruction writes (broadcasts on CDB).
6. An instruction cannot begin execution in the same cycle it is issued.

INSTRUCTION SEQUENCE (I1-I8):
I1: LOAD  F2, 0(R1)
I2: LOAD  F4, 0(R2)
I3: MUL   F6, F2, F4
I4: ADD   F8, F2, F4
I5: DIV   F10, F6, F2
I6: SUB   F2, F8, F6
I7: ADD   F4, F2, F10
I8: MUL   F2, F4, F6

Track each instruction through Issue (I), Execute Start (X), Execute End (E), Write (W) cycles.

Compute these EXACT values:

1) In which cycle does I3 (MUL) begin execution?
2) In which cycle does I5 (DIV) write its result?
3) What is the SUM of write cycles for all 8 instructions?
4) In which cycle does I6 (SUB) begin execution?
5) What is the PRODUCT of issue cycles for I3, I5, and I7?
6) How many cycles have at least one instruction executing (between execute start and execute end, inclusive)?
7) In which cycle does I8 write its result?
8) What is the total number of cycles from I1 issue to I8 write (inclusive)?
9) What is the SUM of (Write cycle - Issue cycle) for instructions I1 through I4?
10) In cycle 10, how many reservation stations are occupied?

State each answer with its question number explicitly.


Grading rubric:
criterion: The response states that I3 (MUL) begins execution in exactly cycle 7.
weight: 10
criterion: The response states that I5 (DIV) writes its result in exactly cycle 20.
weight: 10
criterion: The response states that the sum of write cycles for all 8 instructions is exactly 116.
weight: 10
criterion: The response states that I6 (SUB) begins execution in exactly cycle 12.
weight: 10
criterion: The response states that the product of issue cycles for I3, I5, and I7 is exactly 105.
weight: 10
criterion: The response states that exactly 22 cycles have at least one instruction executing.
weight: 10
criterion: The response states that I8 (MUL) writes its result in exactly cycle 28.
weight: 10
criterion: The response states that the total number of cycles from I1 issue to I8 write (inclusive) is exactly 28.
weight: 10
criterion: The response states that the sum of (Write cycle - Issue cycle) for I1 through I4 is exactly 21.
weight: 10
criterion: The response states that exactly 4 reservation stations are occupied in cycle 10.
weight: 10

Answer:
# GOLDEN ANSWER

## Step-by-step Trace

**I1: LOAD F2, 0(R1)** - Issues cycle 1 to Load1. R1 always ready, no data dependency. Cannot execute same cycle as issue (Rule 6), so execution starts cycle 2. Execution latency = 3 cycles: executes cycles 2-4. Writes cycle 5. F2 available from cycle 5 (usable for execution starting cycle 6).

**I2: LOAD F4, 0(R2)** - Issues cycle 2 to Load2. R2 always ready. Execution starts cycle 3 (cycle after issue). Executes cycles 3-5. Writes cycle 6. F4 available from cycle 6 (usable cycle 7).

**I3: MUL F6, F2, F4** - Issues cycle 3 to Mul1. Needs F2 (available cycle 5, usable cycle 6) and F4 (available cycle 6, usable cycle 7). Both operands usable cycle 7. Execution starts cycle 7. Latency = 4: executes cycles 7-10. Writes cycle 11. F6 available from cycle 11 (usable cycle 12).

**I4: ADD F8, F2, F4** - Issues cycle 4 to Add1. Needs F2 (usable cycle 6) and F4 (usable cycle 7). Both usable cycle 7. Execution starts cycle 7. Latency = 2: executes cycles 7-8. Writes cycle 9. (No CDB conflict - only I4 ready to write cycle 9.) F8 available from cycle 9 (usable cycle 10).

**I5: DIV F10, F6, F2** - Issues cycle 5 to Mul2. Needs F6 (usable cycle 12) and F2 (usable cycle 6). Both usable cycle 12. Execution starts cycle 12. Latency = 8: executes cycles 12-19. Writes cycle 20. F10 available from cycle 20 (usable cycle 21).

**I6: SUB F2, F8, F6** - Issues cycle 6 to Add2. Needs F8 (usable cycle 10) and F6 (usable cycle 12). Both usable cycle 12. Execution starts cycle 12. Latency = 2: executes cycles 12-13. Writes cycle 14. (No CDB conflict cycle 14.) F2 (new value) available cycle 14 (usable cycle 15).

**I7: ADD F4, F2, F10** - Issues cycle 7 to Add3. Needs F2 from I6 (usable cycle 15) and F10 from I5 (usable cycle 21). Both usable cycle 21. Execution starts cycle 21. Latency = 2: executes cycles 21-22. Writes cycle 23. F4 available cycle 23 (usable cycle 24).

**I8: MUL F2, F4, F6** - Needs a Mul station. At cycle 8: Mul1 has I3 (executing), Mul2 has I5 (waiting). Both occupied. Stalls cycles 8, 9, 10. Cycle 11: I3 writes and frees Mul1. I8 issues cycle 11 to Mul1. Needs F4 from I7 (usable cycle 24) and F6 (from I3, available cycle 11, usable cycle 12). Both usable cycle 24. Execution starts cycle 24. Latency = 4: executes cycles 24-27. Writes cycle 28.

## Summary Table

| Inst | Station | I  | X  | E  | W  |
|------|---------|----|----|----|----|
| I1   | Load1   | 1  | 2  | 4  | 5  |
| I2   | Load2   | 2  | 3  | 5  | 6  |
| I3   | Mul1    | 3  | 7  | 10 | 11 |
| I4   | Add1    | 4  | 7  | 8  | 9  |
| I5   | Mul2    | 5  | 12 | 19 | 20 |
| I6   | Add2    | 6  | 12 | 13 | 14 |
| I7   | Add3    | 7  | 21 | 22 | 23 |
| I8   | Mul1    | 11 | 24 | 27 | 28 |

## Answers

**1)** I3 begins execution in cycle **7**.

**2)** I5 writes its result in cycle **20**.

**3)** Sum of write cycles: 5 + 6 + 11 + 9 + 20 + 14 + 23 + 28 = **116**.

**4)** I6 begins execution in cycle **12**.

**5)** Product of issue cycles for I3, I5, I7: 3 x 5 x 7 = **105**.

**6)** Execution ranges (X to E inclusive): I1: 2-4, I2: 3-5, I3: 7-10, I4: 7-8, I5: 12-19, I6: 12-13, I7: 21-22, I8: 24-27. Union of cycles: {2,3,4,5, 7,8,9,10, 12,13,14,15,16,17,18,19, 21,22, 24,25,26,27} = **22** cycles.

**7)** I8 writes its result in cycle **28**.

**8)** I1 issues cycle 1, I8 writes cycle 28. Total inclusive: 28 - 1 + 1 = **28**.

**9)** (W-I) values: I1: 5-1=4, I2: 6-2=4, I3: 11-3=8, I4: 9-4=5. Sum = 4+4+8+5 = **21**.

**10)** Cycle 10 station occupancy: Mul1 has I3 (executing, writes cycle 11), Mul2 has I5 (waiting, issued cycle 5), Add2 has I6 (waiting, issued cycle 6), Add3 has I7 (waiting, issued cycle 7). Load1 freed cycle 5, Load2 freed cycle 6, Add1 freed cycle 9. I8 not yet issued. Total = **4** stations occupied.