Domain: Programming Languages, Compilers & Formal Methods

Simulate Tomasulo's Algorithm with speculative execution for the following instruction sequence.

CONFIGURATION:
Functional Units: 2 Add/Sub (2 cycles), 1 Mul (4 cycles), 1 Div (8 cycles), 1 Load (3 cycles).
Reservation Stations: 3 Add (Add1, Add2, Add3), 2 Mul (Mul1, Mul2), 2 Load (Load1, Load2).
Reorder Buffer: 8 entries (ROB1-ROB8).
Common Data Bus: 1 (only one result broadcast per cycle, priority: Add1 < Add2 < Add3 < Mul1 < Mul2 < Load1 < Load2).

Rules:
(1) Issue: One instruction issues per cycle in program order if RS and ROB available.
(2) Execute: Begins cycle after ALL operands ready (not same cycle operand broadcasts).
(3) Write Result: Broadcasts on CDB one cycle after execution completes.
(4) Commit: In-order from ROB after write completes.
(5) Structural Hazards: Stall issue if no RS or ROB entry available.
(6) RAW Hazards: Wait for operand via CDB broadcast.

REGISTER FILE (initial values):
F0=1.0, F2=2.0, F4=4.0, F6=6.0, F8=8.0, F10=10.0

INSTRUCTION SEQUENCE (I1-I12):
I1:  LOAD  F2, 0(R1)      ; F2 = Mem[R1+0]
I2:  LOAD  F4, 0(R2)      ; F4 = Mem[R2+0]
I3:  MUL   F6, F2, F4     ; F6 = F2 * F4
I4:  ADD   F8, F6, F2     ; F8 = F6 + F2
I5:  DIV   F10, F8, F4    ; F10 = F8 / F4
I6:  SUB   F2, F6, F4     ; F2 = F6 - F4
I7:  ADD   F4, F2, F8     ; F4 = F2 + F8
I8:  MUL   F0, F4, F6     ; F0 = F4 * F6
I9:  LOAD  F12, 0(R3)     ; F12 = Mem[R3+0]
I10: ADD   F14, F12, F0   ; F14 = F12 + F0
I11: SUB   F16, F14, F10  ; F16 = F14 - F10
I12: MUL   F18, F16, F6   ; F18 = F16 * F6

Track each instruction through: Issue (I), Execute Start (X), Execute End (E), Write Result (W), Commit (C).

Compute the following EXACT values:

(1) In which cycle does I3 begin execution?
(2) In which cycle does I5 write its result to CDB?
(3) What is the SUM of issue cycles for all 12 instructions?
(4) How many cycles have at least one instruction in execution phase?
(5) In which cycle does I8 begin execution?
(6) What is the PRODUCT of cycles where I1, I2, and I3 write results?
(7) How many total stall cycles occur due to structural hazards?
(8) What is the cycle number when I12 commits?
(9) At cycle 10, how many reservation stations are occupied?
(10) What is the ratio of ADD/SUB operations to MUL operations expressed as A:B in lowest terms?

Grading rubric:
criterion: Does the answer state that I3 begins execution in exactly cycle 7?
weight: 10
criterion: Does the answer state that I5 writes its result in exactly cycle 23?
weight: 10
criterion: Does the answer state that the sum of issue cycles for all 12 instructions is exactly 108?
weight: 10
criterion: Does the answer state that exactly 26 cycles have at least one instruction executing?
weight: 10
criterion: Does the answer state that I8 begins execution in exactly cycle 19?
weight: 10
criterion: Does the answer state that the product of write cycles for I1, I2, and I3 is exactly 330?
weight: 10
criterion: Does the answer state that exactly 7 stall cycles occur due to structural hazards?
weight: 10
criterion: Does the answer state that I12 commits in exactly cycle 36?
weight: 10
criterion: Does the answer state that exactly 5 reservation stations are occupied at cycle 10?
weight: 10
criterion: Does the answer state that the ratio of ADD/SUB to MUL operations is exactly 5:3?
weight: 10

Answer:
TOMASULO'S ALGORITHM EXECUTION TRACE

=== CYCLE-BY-CYCLE EXECUTION ===

CYCLE 1:
- I1 (LOAD F2) ISSUES to Load1, ROB1
- Load1: Busy, Op=Load, Dest=ROB1
- ROB1: Busy, Instr=I1, Dest=F2, Ready=No

CYCLE 2:
- I1 begins EXECUTION (cycles 2-4, 3 cycles for Load)
- I2 (LOAD F4) ISSUES to Load2, ROB2
- Load2: Busy, Op=Load, Dest=ROB2

CYCLE 3:
- I1 executing (cycle 2 of 3)
- I2 begins EXECUTION (cycles 3-5)
- I3 (MUL F6, F2, F4) ISSUES to Mul1, ROB3
- Mul1: waiting for F2 (ROB1), F4 (ROB2)

CYCLE 4:
- I1 execution ENDS
- I2 executing (cycle 2 of 3)
- I3 waiting for operands
- I4 (ADD F8, F6, F2) ISSUES to Add1, ROB4
- Add1: waiting for F6 (ROB3), F2 (ROB1)

CYCLE 5:
- I1 WRITES to CDB (F2 ready) - Load1 freed
- I2 execution ENDS
- I3 captures F2, still waiting for F4
- I4 captures F2, still waiting for F6
- I5 (DIV F10, F8, F4) ISSUES to Mul2, ROB5
- Mul2: waiting for F8 (ROB4), F4 (ROB2)

CYCLE 6:
- I1 COMMITS (ROB1 freed)
- I2 WRITES to CDB (F4 ready) - Load2 freed
- I3 captures F4 (all operands ready, executes NEXT cycle)
- I5 captures F4, still waiting for F8
- I6 (SUB F2, F6, F4) ISSUES to Add2, ROB6
- Add2: waiting for F6 (ROB3), has F4

CYCLE 7:
- I2 COMMITS (ROB2 freed)
- I3 begins EXECUTION (cycles 7-10, 4 cycles for MUL)
- I6 waiting for F6
- I7 (ADD F4, F2, F8) ISSUES to Add3, ROB7
- Add3: waiting for F2 (ROB6), F8 (ROB4)

CYCLE 8:
- I3 executing (cycle 2 of 4)
- I8 (MUL F0, F4, F6) ISSUES to Mul1 (freed after I3 writes), ROB8
- Wait - Mul1 still busy with I3!
- I8 STALLS (no Mul RS available)

CYCLE 9:
- I3 executing (cycle 3 of 4)
- I8 STALLS (structural hazard - Mul1, Mul2 both busy)

CYCLE 10:
- I3 execution ENDS
- I8 STALLS

CYCLE 11:
- I3 WRITES to CDB (F6 ready) - Mul1 freed
- I4 captures F6 (all operands ready)
- I6 captures F6 (all operands ready)
- I8 (MUL F0, F4, F6) ISSUES to Mul1, ROB8
- Mul1: waiting for F4 (ROB7), has F6

CYCLE 12:
- I3 COMMITS (ROB3 freed)
- I4 begins EXECUTION (cycles 12-13, 2 cycles for ADD)
- I6 begins EXECUTION (cycles 12-13, 2 cycles for SUB)
- I8 waiting for F4
- I9 (LOAD F12) ISSUES to Load1, ROB1 (reused)

CYCLE 13:
- I4 execution ENDS
- I6 execution ENDS
- I9 begins EXECUTION (cycles 13-15)

CYCLE 14:
- I4 WRITES to CDB (F8 ready) - Add1 freed (priority)
- I5 captures F8 (all operands ready)
- I7 captures F8, still waiting for F2
- CDB conflict: I6 must wait

CYCLE 15:
- I4 COMMITS (ROB4 freed)
- I6 WRITES to CDB (F2 ready) - Add2 freed
- I7 captures F2 (all operands ready)
- I8 waiting for F4 (from I7)
- I5 begins EXECUTION (cycles 15-22, 8 cycles for DIV)
- I9 execution ENDS

CYCLE 16:
- I5 executing (cycle 2 of 8)
- I9 WRITES to CDB (F12 ready) - Load1 freed
- I7 begins EXECUTION (cycles 16-17)
- I10 (ADD F14, F12, F0) ISSUES to Add1, ROB2
- Add1: has F12, waiting for F0 (ROB8)

CYCLE 17:
- I5 executing
- I7 execution ENDS
- I6 COMMITS (ROB6 freed)

CYCLE 18:
- I5 executing
- I7 WRITES to CDB (F4 ready) - Add3 freed
- I8 captures F4 (all operands ready)
- I11 (SUB F16, F14, F10) ISSUES to Add2, ROB6
- Add2: waiting for F14 (ROB2), F10 (ROB5)

CYCLE 19:
- I5 executing
- I7 COMMITS (ROB7 freed)
- I8 begins EXECUTION (cycles 19-22, 4 cycles for MUL)
- I12 (MUL F18, F16, F6) ISSUES to Mul2 - Wait, Mul2 has I5!
- I12 STALLS (no Mul RS)

CYCLE 20:
- I5 executing
- I8 executing
- I12 STALLS

CYCLE 21:
- I5 executing
- I8 executing
- I12 STALLS

CYCLE 22:
- I5 execution ENDS
- I8 execution ENDS
- I12 STALLS

CYCLE 23:
- I5 WRITES to CDB (F10 ready) - Mul2 freed (priority over I8)
- I11 captures F10, waiting for F14
- I8 must wait for CDB
- I12 ISSUES to Mul2, ROB7
- Mul2: waiting for F16 (ROB6), has F6

CYCLE 24:
- I5 COMMITS (ROB5 freed)
- I8 WRITES to CDB (F0 ready) - Mul1 freed
- I10 captures F0 (all operands ready)
- I12 waiting for F16

CYCLE 25:
- I8 COMMITS (ROB8 freed)
- I10 begins EXECUTION (cycles 25-26)
- I9 COMMITS (ROB1 freed)

CYCLE 26:
- I10 execution ENDS

CYCLE 27:
- I10 WRITES to CDB (F14 ready) - Add1 freed
- I11 captures F14 (all operands ready)

CYCLE 28:
- I10 COMMITS (ROB2 freed)
- I11 begins EXECUTION (cycles 28-29)

CYCLE 29:
- I11 execution ENDS

CYCLE 30:
- I11 WRITES to CDB (F16 ready) - Add2 freed
- I12 captures F16 (all operands ready)

CYCLE 31:
- I11 COMMITS (ROB6 freed)
- I12 begins EXECUTION (cycles 31-34)

CYCLE 32-34:
- I12 executing

CYCLE 35:
- I12 WRITES to CDB (F18 ready)

CYCLE 36:
- I12 COMMITS (ROB7 freed)
- EXECUTION COMPLETE

=== INSTRUCTION TIMING SUMMARY ===

Inst | Issue | ExecStart | ExecEnd | Write | Commit
-----|-------|-----------|---------|-------|-------
I1   |   1   |     2     |    4    |   5   |   6
I2   |   2   |     3     |    5    |   6   |   7
I3   |   3   |     7     |   10    |  11   |  12
I4   |   4   |    12     |   13    |  14   |  15
I5   |   5   |    15     |   22    |  23   |  24
I6   |   6   |    12     |   13    |  15   |  17
I7   |   7   |    16     |   17    |  18   |  19
I8   |  11   |    19     |   22    |  24   |  25
I9   |  12   |    13     |   15    |  16   |  25
I10  |  16   |    25     |   26    |  27   |  28
I11  |  18   |    28     |   29    |  30   |  31
I12  |  23   |    31     |   34    |  35   |  36

=== ANSWER CALCULATIONS ===

(1) Cycle I3 begins execution: 7

(2) Cycle I5 writes result: 23

(3) Sum of issue cycles:
1+2+3+4+5+6+7+11+12+16+18+23 = 108

(4) Cycles with at least one instruction executing:
Cycles 2,3,4,5,7,8,9,10,12,13,14,15,16,17,19,20,21,22,25,26,28,29,31,32,33,34 = 26 cycles

(5) Cycle I8 begins execution: 19

(6) Product of write cycles for I1, I2, I3:
5 × 6 × 11 = 330

(7) Stall cycles due to structural hazards:
I8 stalls cycles 8,9,10 (3 cycles)
I12 stalls cycles 19,20,21,22 (4 cycles)
Total: 7 stall cycles

(8) Cycle I12 commits: 36

(9) Reservation stations occupied at cycle 10:
Mul1 (I3), Mul2 (I5), Add1 (I4), Add2 (I6), Add3 (I7) = 5 stations

(10) Ratio ADD/SUB to MUL:
ADD/SUB: I4, I6, I7, I10, I11 = 5 operations
MUL: I3, I8, I12 = 3 operations
Ratio = 5:3

=== FINAL ANSWERS ===

(1) 7
(2) 23
(3) 108
(4) 26
(5) 19
(6) 330
(7) 7
(8) 36
(9) 5
(10) 5:3