GE 645

The GE 645 mainframe computer was a development of the GE 635 for use in the Multics project. This was the first computer that implemented a configurable hardware protected memory system. It was designed to satisfy the requirements of Project MAC to develop a platform that would host their proposed next generation time-sharing operating system (Multics) and to meet the requirements of a theorized computer utility. The system was the first truly symmetric multiprocessing machine to use virtual memory, it was also among the first machines to implement what is now know as a translation lookaside buffer. The foundational patent for which was granted to John Couleur and Edward Glaser. 

General Electric initially publicly announced the GE 645 at the Fall Joint Computer Conference in November 1965. At a subsequent press conference in December of that year it was announced that they would be working towards "broad commercial availability" of the system. However they would subsequently withdraw it from active marketing at the end of 1966. In total at least 6 sites ran GE 645 systems in the period from 1967 to 1975.

System configuration
The basic system configuration consisted of a combination of 4 basic modules these were:
 Processor
 System Controller
 Generalized I/O Controller (GIOC)
 Extended Memory Unit (EMU)

Compared to the rest of the 600 series the 645 did not use the standard IOC's (input/output controllers) for I/O. Nor did it use the DATANET-30 front end processor for communications. Instead both sets of functionality was combined into one unit called a GIOC (Generalized I/O Controller) which provided dedicated channels for both Peripheral (Disc/Tape) and Terminal I/O. The GIOC acted as an Active Device and was directly connected to memory via dedicated links to each System Controller that was present in a specific configuration.

The Extended Memory Unit, though termed a drum, was in reality a large fixed-head hard disk with one head per track, this was a OEM product from Librascope. The EMU consisted of 4,096 tracks providing 4MW (megawords) of storage (equivalent to 16MB). Each track had a dedicated read/write head, these were organised into groups of 16 "track sets" which are used to read/write a sector. A sector is the default unit of data allocation in the EMU and is made up of 80 words, of which 64 words are data and the remaining 16 were used as a guard band. The average transfer rate between the EMU and memory was 470,000 words per second, all transfers were 72-bits (two words) wide, with it taking 6.7μs to transfer 4 words. The unit had a rotational speed of 1,725 rpm, which ensured an average latency of 17.4 milliseconds.

Architecture

Processor Modes 
The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 218 words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 224 words and with instruction execution occurring in either Master or Slave modes.

Slave Mode 
By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts (bit 28 of instruction word) is forbidden. Format of instruction addresses is via the Appending Process.

Master Mode 
In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.

Absolute Mode 
All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 218 (18-bit) absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

Appending Mode 
By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a base address, or the offset is linked to the base address.

Functional Units 
The 645 processor was divided into four major functional units these were:

 Appending Unit: 
 Controls data I/O from memory
 Controls memory selection and interleave
 Carries out Memory appending
 Control fault recognition
 Does power on/off sequencing
 Associative Memory Unit:
 Consists of Associative Memory made up of 16 x 60-bit Registers 
 Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table)
 Performs the fuction of what would now be classed as a TLB.
 Control Unit:
 Performs all control fuctions
 Performs Address modification
 Controls the processor mode (master, slave, absolute)
 Interrupt recognition/handling
 Opcode decoding
 Operations Unit:
 Performs fractional and integer divisions and multiplications.
 Performs automatic alignment of floating-point numbers for addition and subtraction.
 Performs inverted divisions on floating-point numbers.
 Performs automatic normalization of floating-point resultants.
 Performs shifts.
 Performs indicator register loading and storing.
 Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of virtual memory. The APU was also used to implement a single-level store which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1). 

       GE-645 Instruction Format

     0 0 0             1 1       2 2 2 3    3
     0 2 3             7 8       6 7 9 0    5
    +---+---------------+---------+---+------+
    |BR |   ADDRESS     | OPCODE  |UIB| TAG  |
    +---+---------------+---------+---+------+

       Field Name   Size      Purpose
       ----------   -------   -------
       BR            3 bits   base register; 0-7
       ADDRESS      15 bits   word address; 0-32767 (32KW)
       OPCODE        9 bits   instruction opcode
       U             1 bit    unused
       I             1 bit    interrupt inhibit flag
       B             1 bit    0=no base register (GE-635 format)
                              1=base register (GE-645 format)
       TAG           6 bits   index/indirect type

History
CTSS had originated in the MIT Computation Center using a IBM 709 and was first demonstrated in November 1961, it was subsequently upgraded to a 7090 in 1962, and finally to a 7094 in 1963. This required modification to these standard systems via the addition of a number of RPQ's which among others added two banks of memory and bank-switching between user and supervisor mode, i.e. programs running in the A-core memory bank had access to instructions that programs running in the B-core bank did not.

Project MAC formally began with signing of contract with ARPA on the 1st of July 1963. By October 1963 they had received a dedicated 7094 to run CTSS under, this was termed the "Red Machine" due to it having red side panels. This would provide a time-sharing environment for Project MAC, and would subsequently be heavily used for the development of Multics. During this period exploratory work was carried out into what a replacement for CTSS would look like and what type of hardware it would require to run on. A committee was formed consisting of Fernando J. Corbató, Ted Glaser, Jack Dennis and Robert Graham with responsibility to visit computer manufacturers to gauge level of interest in the industry to tender for the hardware platform. They proceeded to visit among others Burroughs, CDC, DEC, General Electric, IBM and Sperry Univac. Of these GE and IBM showed the strongest interest.

While the GE 645 hardware was being designed and debugged in Phoenix, a system was put in place where a GE 635 could be used to run a simulator known as the 6.36, so that development and checkout of Multics could occur in parallel. This process involved creating a tape on the CTSS system which would be inputted to GECOS on the 635 system in MIT so that it would run under the 6.36 simulator; the resulting output would be carried back via tape to CTSS for debugging/analysis. This simulated environment was replaced by the first 645 hardware in 1967. The GECOS operating system was fully replaced by Multics in 1969 with the Multics supervisor separated by protection rings with "gates" allowing access from user mode.

A later generation in the form of the 645F (F for follow-on) wasn't completed by the time the division was sold to Honeywell, and became known as the Honeywell 6180. The original access control mechanism of the GE/Honeywell 645 were found inadequate for high speed trapping of access instructions and the re-implementation in the 6180 solved those problems. The bulk of these computers running time-sharing on Multics were installed at the NSA and similar governmental sites. Their usage was limited by the extreme security measures and had limited impact on subsequent systems, other than the protection ring.

The hardware protection introduced on this computer and modified on the 6180 was later implemented in the Intel 286 computer processor as a four-layer protection ring, but four rings was found to be too cumbersome to program and too slow to operate. Protection ring architecture is now used only to protect kernel mode from user mode code just as it was in the original use of the 645.

See also
 GE-600 series
 Honeywell 6000 series
 Multics
 Mainframe computer
 Time-sharing
 IBM System/360 Model 67

Further reading

References

External links
GE-645 Circuit Board
645 System: Artist's Conception
Multics Phase One (includes photo of GE-645)
Installing the GE-645 in Paris (includes photo of part of a GE-645)

600
Transistorized computers
36-bit computers
Computer-related introductions in 1967
Time-sharing