用VHDL语言编写的程序
library ieee; use ieeestd_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dac_ds is port(reset :in std_logic; clk :in std_logic; din :in std_logic_vector(7 downto 0);--Signed integer dout :out std_logic; ); end dac_ds; architecture arch_dac_ds of dac_ds is signal error :std_logic_vector(9 downto 0);--Error accumulator is 2 bits larger constant zeros:std_logic_vector(7 downto 0):=(others=>'0'); begin process(reset,clk,din) variable val :std_logic_vector(9 downto 0); begin if reset='1'then error'0'); dout