50Mhz,时钟周期20ns,延迟一拍即可。module clk(start,clk_in,clk_out); //clk_in为输入时钟,Start为开始信号
input start,clk_in;
output clk_out;
reg clk_out;
reg clk_out_r;
always @(posedge clk_in)
begin
if(!start)
begin
clk_out <= 0;
clk_out_r <= 0;
end
else
begin
clk_out_r <= ~clk_out_r;
clk_out <= clk_out_r;
end
end
endmodule