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资料介绍
比较完整的CPLD芯片资料
Features.。。
High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generaTIon MulTIple Array MatriX (MAX®) architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test AcTIon Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compaTIble with IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the po