Exhibit 10.1
Second Amendment
To
Patent Purchase Agreement
     This Second Amendment (“Amendment”) is entered into as of March 18, 2009,
(“Effective Date”) by and between Aprolase Development Co., LLC, a Delaware
limited liability company, with an address at 2711 Centerville Road, Suite 400,
Wilmington, DE 19808 (“Purchaser”) and Irvine Sensors Corporation, a Delaware
corporation, with an office at 3001 Redhill Ave., Bldg. 4, Suite 108, Costa
Mesa, CA 92672 (“Seller”). The parties hereby agree as follows:
1. Background
1.1 Seller and Purchaser entered into a Patent Purchase Agreement effective as
of December 11, 2008 (the “Agreement”).
1.2. Seller and Purchaser desire to amend the Agreement pursuant the terms and
conditions of this Amendment.
2. Terms Used in This Amendment
Capitalized terms used in this Amendment shall have the same meanings set forth
in the Agreement, unless stated otherwise herein.
3. Amendments to Agreement
3.1 Section 3.4 is deleted in its entirety and replaced with the following:
“3.4 Payment.
(a) Purchase Price. At Closing, Purchaser will pay to Seller the amount of Eight
Million Five Hundred Thousand U.S. Dollars (US $8,500,000), which payment shall
be made as set forth below. Purchaser may record the Executed Assignments with
the applicable patent offices only on or after Closing:
(i) Two Million Eight Hundred Thousand U.S. Dollars (US $2,800,000) to the
following:
Citibank, N.A.
1155 6th Avenue
New York, NY 10036
ABA Number: ***
For Credit to: ***
Account Number: ***
(ii) One Million Forty Thousand U.S. Dollars (US $1,040,000) to the following:
 

*   Confidential treatment requested pursuant to Rule 24b-2 under the Securities
Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions
have been omitted from this exhibit and filed separately with the Securities and
Exchange Commission.

 

--------------------------------------------------------------------------------

 

U.S. Bank, NA
ABA: ***
FBO: U.S. Bank Trust NA
Acct: ***
FFC: ***
(iii) Four Million Sixty Hundred Sixty Thousand U.S. Dollars ($4,660,000) to the
following:
Bank name: U.S. Bank
Bank Address: 4100 Newport Place, Newport Beach, CA 92660
Account Name: ***
Checking account number: ***
ABA routing number: ***
Swift Number: ***
Bank contact person: ***
Bank phone number: 949 863-2462
Bank Fax: 949 863-2336”
(b) Post-Closing Payment. To the extent Seller has fully satisfied the
conditions to all of the “Post-Closing Payment” (as defined below) within the
thirty (30) day period immediately following Closing (the “Post-Closing Payment
Period”), Seller will provide Purchase with one written notice (the
“Post-Closing Notice”) setting forth such satisfaction, accompanied by any
documentation to be delivered to Purchaser pursuant to this subparagraph 3.4(b).
The Post-Closing Notice must be received by Purchaser within the thirty (30) day
period immediately following Closing. If Purchaser is satisfied that the
Post-Closing Notice will fulfill the Post- Closing Payment conditions set forth
below, Purchase will pay to Seller by wire transfer the Post-Closing Payment
within ten (10) days of receipt of Post-Closing Notice. The amount of the
Post-Closing Payment to be paid to Seller under this Agreement will be One
Million U.S. Dollars ($1,000,000). If Seller has not, prior to the end of the
Post-Closing Payment Period, fully satisfied all of the conditions to payment of
the Post-Closing Payment as further set forth in paragraphs 3.4(b)(i) through
(ii), Seller will have no right to receive, and Purchaser will have no
obligations to pay any portion of the Post-Closing Payment. For purposes of the
limitation of liability of each party as set forth in paragraph 8.1, the
“purchase price” will equal the total of the amount set forth in paragraph
3.4(a) together with the amount of Post-Closing Payments (if any) paid to
Seller. The “Post-Closing Payment” and the corresponding conditions to
Purchaser’s obligation to make such Post-Closing Payments are as following:
(i) Seller confirms that it has not received any correspondence from *** or from
*** pursuant to the termination letter dated ***, such that the License
Agreement between *** and Irvine Sensors Corporation *** is terminated.
 

*   Confidential treatment requested pursuant to Rule 24b-2 under the Securities
Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions
have been omitted from this exhibit and filed separately with the Securities and
Exchange Commission.

Page 2

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(ii) Seller shall use best efforts to obtain from *** proper agreements from ***
and ***, and ***, in a form acceptable to Purchaser, either terminating the
sublicense agreements or amending each sublicenses so that it is non-exclusive,
nonsublicensable and nontransferable. The obligations set forth in this
subsection (ii) shall continue until such time as the sublicense agreements are
terminated or amended as set forth therein. Purchaser payment of the
Post-Closing Payment shall not relieve Seller of these obligations.
3.2 The references to “paragraph 3.4” in paragraphs 3.2 and 3.3 will be deleted
and replaced with references to “paragraph 3.4(a)”.
3.3 The following is added as new Section 5.1(d):
“(d) Seller covenants that pursuant to the License Agreement entered into on ***
between *** and Seller, that Seller shall not agree to nor shall provide any
approval, written or otherwise which would authorize or allow *** to grant any
sublicenses under paragraph 7 of the License Agreement. Seller further covenants
that Seller shall not agree to nor shall provide any approval, written or
otherwise which would authorize or allow *** to assign the License Agreement or
any of the rights, benefits or obligations thereunder under Paragraph 16 of the
License Agreement.”
3.4 Exhibits A, B, and C are deleted in their entirety and replaced with the
attached Exhibits A, B, and C.
3.5 Exhibit G is deleted in its entirety and replaced with the attached
Exhibit G.
4. No Other Changes
This Amendment amends and supersedes the Agreement and all prior amendments with
respect to the subject matter of this Amendment, and supersedes all prior and
contemporaneous negotiations and other writings with respect to such matters. In
the event that a conflict arises between this Amendment and the Agreement or a
prior amendment, this Amendment shall control. Except for the changes made
herein, the terms and conditions of the Agreement and its Exhibits shall remain
unchanged and in full force and effect.
5. Governing Law
This Amendment will be interpreted, construed, and enforced in all respects in
accordance with the laws of the State of Delaware, without reference to its
choice of law principles to the contrary.
6. Counterparts; Electronic Signature
 

*   Confidential treatment requested pursuant to Rule 24b-2 under the Securities
Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions
have been omitted from this exhibit and filed separately with the Securities and
Exchange Commission.

Page 3

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This Amendment may be executed in counterparts, each of which will be deemed an
original, and all of which together constitute one and the same instrument. Each
party will execute and promptly deliver to the other parties a copy of this
Amendment bearing the original signature. Prior to such delivery, in order to
expedite the process of entering into this Amendment, the parties acknowledge
that a Transmitted Copy of this version will be deemed an original document.
“Transmitted Copy” means a copy bearing a signature of a party that is
reproduced or transmitted via email of a .pdf file, photocopy, facsimile, or
other process of complete and accurate reproduction and transmission.
In witness whereof, intending to be legally bound, the parties have executed
this Amendment as of the Effective Date.

                      SELLER:   PURCHASER:    
 
                    IRVINE SENSORS CORPORATION   APROLASE DEVELOPMENT CO., LLC  
 
 
                   
By:
  /s/ John J. Stuart, Jr.
 
      By:   /s/ Melissa Coleman
 
   
 
  Name: John J. Stuart, Jr.           Name: Melissa Coleman    
 
  Title:   Sr. VP & Chief Financial Officer           Title:   Authorized Person
   

Page 4

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Exhibit A, revised
PATENTS TO BE ASSIGNED

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
5,235,672
(07/651,477)
  US   8/10/1993
(2/6/1991)   Hardware for electronic neural network

Carson, John C.
 
           
6,389,404
(09/223,476)
  US   5/14/2002
(12/30/1998)   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
6,650,704
(09/427,384)
  US   11/18/2003
(10/25/1999)   Method of producing a high quality, high resolution image from a
sequence of low quality, low resolution images that are undersampled and subject
to jitter

Carlson, Randolph S.; Arnold, Jack L.; Feldmus, Valentine G.
 
           
6,829,237
(09/973,857)
  US   12/7/2004 (10/9/2001)   High speed multi-stage switching network formed
from stacked switching layers Carson, John C.; Ozguz, Volkan H.
 
           
7,082,591
(10/346,363)
  US   7/25/2006
(1/17/2003)   Method for effectively embedding various integrated circuits
within field programmable gate arrays

Carlson, Randolph S.
 
           
6,856,167
(10/347,038)
  US   2/15/2005
(1/17/2003)   Field programmable gate array with a variably wide word width
memory

Ozguz, Volkan H.; Carlson, Randolph S.; Gann, Keith D.; Leon, John P.
 
           
7,265,579
(11/037,490)
  US   9/4/2007
(1/18/2005)   Field programmable gate array incorporating dedicated memory
stacks

Carlson, Randolph Stuart; Ozguz, Volkan; Gann, Keith D.; Leon, John P.
 
           
5,508,836
(08/305,066)
  US   4/16/1996 (9/13/1994)   Infrared wireless communication between
electronic system components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
5,635,705
(08/526,415)
  US   6/3/1997
(9/11/1995)   Sensing and selecting observed events for signal processing

Saunders, Christ H.
 
           
6,195,268
(09/031,435)
  US   2/27/2001
(2/26/1998)   Stacking layers containing enclosed IC chips

Eide, Floyd K.
 
           
5,045,685
(07/534,969)
  US   9/3/1991
(6/6/1990)   Analog to digital conversion on multiple channel IC chips

Wall, Llewellyn E.
 
           
5,104,820
(07/720,025)
  US   4/14/1992
(6/24/1991)   Method of fabricating electronic circuitry unit containing stacked
IC layers having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
5,279,991
(07/996,794)
  US   1/18/1994
(12/24/1992)   Method for fabricating stacks of IC chips by segmenting a larger
stack

Minahan, Joseph A.; Pepe, Angel A.
 
           
5,432,318
(08/178,923)
  US   7/11/1995
(1/7/1994)   Apparatus for segmenting stacked IC chips

Minahan, Joseph A.
 
           
5,304,790
(07/956,914)
  US   4/19/1994
(10/5/1992)   Apparatus and system for controllably varying image resolution to
reduce data output

Arnold, Jack
 
           
5,347,428
(07/985,837)
  US   9/13/1994
(12/3/1992)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
5,406,701
(08/120,675)
  US   4/18/1995
(9/13/1993)   Fabrication of dense parallel solder bump connections

Pepe, Angel A.; Reinker, David M.; Minahan, Joseph A.
 
           
5,424,920
(08/232,739)
  US   6/13/1995
(4/25/1994)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
5,432,729
(08/255,465)
  US   7/11/1995
(6/8/1994)   Electronic module comprising a stack of IC chips each interacting
with an IC chip secured to the stack

Carson, John C.; Some, Raphael R.
 
           
5,581,498
(08/326,645)
  US   12/3/1996
(10/20/1994)   Stack of IC chips in lieu of single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
5,688,721
(08/62,2671)
  US   11/18/1997
(3/26/1996)   3D stack of IC chips having leads reached by vias through
passivation covering access plane

Johnson, Tony K.
 
           
5,953,588
(08/777,747)
  US   9/14/1999
(12/21/1996)   Stackable layers containing encapsulated IC chips

Camien, Andrew N; Yamaguchi, James S.
 
           
6,072,234
(09/316,740)
  US   6/6/2000
(5/21/1999)   Stack of equal layer neo-chips containing encapsulated IC chips of
different sizes

Camien, Andrew N.; Yamaguchi, James S.
 
           
5,955,668
(09/166,458)
  US   9/21/1999
(10/5/1998)   Multi-element micro gyro

Hsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.
 
           
6,089,089
(09/301,847)
  US   7/18/2000
(4/29/1999)   Multi-element micro gyro

Hsu, Ying W.
 
           
6,578,420
(09/604,782)
  US   6/17/2003
(6/26/2000)   Multi-axis micro gyro structure

Hsu, Ying Wen
 
           
6,014,316
(09/095,416)
  US   1/11/2000
(6/10/1998)   IC stack utilizing BGA contacts

Eide, Floyd K.
 
           
6,028,352
(09/095,415)
  US   2/22/2000
(6/10/1998)   IC stack utilizing secondary lead frames

Eide, Floyd K.
 
           
6,117,704
(09/282,704)
  US   9/12/2000
(3/31/1999)   Stackable layers containing encapsulated chips

Yamaguchi, James S.; Ozguz, Volkan H.; Camien, Andrew N.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
6,476,392
(09/853,819)
  US   11/5/2002
(5/11/2001)   Method and apparatus for temperature compensation of an uncooled
focal plane array

Kaufman, Charles S.; Carson, Randolph S.; Hornback, William B.
 
           
6,891,160
(10/281,393)
  US   5/10/2005
(10/25/2002)   Method and apparatus for temperature compensation of an uncooled
focal plane array

Kaufman, Charles S.; Carson, Randolph S.; Hornback, William B.
 
           
7,235,785
(11/048,634)
  US   6/26/2007
(1/31/2005)   Imaging device with multiple fields of view incorporating
memory-based temperature compensation of an uncooled focal plane array

Hornback, Bert; Harwood, Doug; Boyd, W. Eric; Carlson, Randy
 
           
6,596,997
(09/921,525)
  US   7/22/2003
(8/3/2001)   Retro-reflector warm stop for uncooled thermal imaging cameras and
method of using the same

Kaufman, Charles S.
 
           
6,706,971
(10/142,557)
  US   3/16/2004
(5/10/2002)   Stackable microcircuit layer formed from a plastic encapsulated
microcircuit

Albert, Douglas M.; Gann, Keith D.
 
           
7,174,627
(10/338,974)
  US   2/13/2007
(1/9/2003)   Method of fabricating known good dies from packaged integrated
circuits

Gann, Keith D.
 
           
6,560,109
(09/949,024)
  US   5/6/2003
(9/7/2001)   Stack of multilayer modules with heat-focusing metal layer

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
6,717,061
(09/949,512)
  US   4/6/2004
(9/7/2001)   Stacking of multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
6,734,370
(09/948,950)
  US   5/11/2004
(9/7/2001)   Multilayer modules with flexible substrates

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
7,127,807
(10/431,914)
  US   10/31/2006
(5/7/2003)   Process of manufacturing multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
6,797,537
(09/938,686)
  US   9/28/2004
(10/30/2001)   Method of making stackable layers containing encapsulated
integrated circuit chips with one or more overlaying interconnect layers

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
6,784,547
(10/302,680)
  US   8/31/2004
(11/21/2002)   Stackable layers containing encapsulated integrated circuit chips
with one or more overlying interconnect layers

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
7,239,012
(10/951,990)
  US   7/3/2007
(9/28/2004)   Three-dimensional module comprised of layers containing IC chips
with overlying interconnect layers

Pepe, Angel; Yamaguchi, James
 
           
6,806,559
(10/128,728)
  US   10/19/2004
(4/22/2002)   Method and apparatus for connecting vertically stacked integrated
circuit chips

Gann, Keith D.; Albert, Douglas M.
 
           
6,912,862
(10/615,641)
  US   7/5/2005
(7/8/2003)   Cryopump piston position tracking

Sapir, Itzhak
 
           
6,967,411
(10/360,244)
  US   11/22/2005
(2/7/2003)   Stackable layers containing ball grid array packages

Eide, Floyd K.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
7,242,082
(11/229,351)
  US   6/10/2007
(9/15/2005)   Stackable layer containing ball grid array package

Eide, Floyd
 
           
6,993,835
(10/726,888)
  US   2/7/2006 (12/4/2003)   Method for electrical interconnection of angularly
disposed conductive patterns

Albert, Douglas Marice
 
           
6,998,328
(10/701,783)
  US   2/14/2006
(11/5/2003)   Method for creating neo-wafers from singulated integrated circuit
die and a device made according to the method

Stern, Jonathan Michael
 
           
7,417,323
(10/703,177)
  US   (11/6/2003)   Neo-wafer device and method

Sambo S. He
 
           
7,198,965
(11/354,370)
  US   4/3/2007
(2/14/2006)   Method for making a neo-layer comprising embedded discrete
components

He, Sambo
 
           
7,180,579
(10/806,037)
  US   2/20/2007
(3/22/2004)   Three-dimensional imaging processing module incorporating stacked
layers containing microelectronic circuits

Ludwig, David E.; Kennedy, John V.; Kleinhans, William; Liu, Tina; Krutzik,
Christian
 
           
7,436,494
(11/706,724)
  US   10/14/2008
(2/15/2007)   Three-dimensional LADAR module with alignment reference insert
circuitry

Ludwig, David E.; Kennedy, John V.; Kleinhans, William; Liu, Tina; Krutzik,
Christian
 
           
7,335,576
(11/197,828)
  US   2/26/2008
(8/5/2005)   Method for precision integrated circuit die singulation using
differential etch rates

David, Ludwig; Yamaguchi, James; Clark, Stuart; Boyd, W. Eric
 
           
7,380,459
(11/654,292)
  US   6/3/2008
(1/16/2007)   Absolute pressure sensor

Sapir, Itzhak
 
           
10/968,572
  US   10/19/2004   Vertically stacked pre-packaged integrated circuit chips

Keith Gann; Douglas N. Albert

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
7,440,449
(10/960,712)
  US   10/6/2004   High speed switching module comprised of stacked layers
incorporating T-connect structures

John C. Carson; Volkan H. Orguz
 
           
11/977,447
  US   10/24/2007   Wire bond method for angularly disposed conductive pads and
a device made from the method

Randy Wayne Bindrup
 
           
11/897,938
  US   08/31/2007   Field programmable gate array utilizing dedicated memory
stacks in a vertical layer format

Ozguz, Volkan; Carlson, Randolph Stuart; Gann, Keith D.; Leon, John P.; Boyd, W
Eric
 
           
11/825,643
  US   7/7/2007   Ball grid array package format layers and structure

Keith Gann; W Eric Boyd
 
           
11/807,671
  US   5/30/2007   Large Format Thermoelectic Infrared Detector and a Method of
Fabrication

Ying Hsu
 
           
11/731,154
  US   3/31/2007   Ball Grid Array Stack

Frank Mantz
 
           
11/524,090
  US   9/20/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
11/511,117
  US   8/26/2006   MEMS cooling device

Itzhak Sapir
 
           
11/499,403
  US   8/4/2006   High density interconnect assembly comprising stacked
electronic module

John V. Kennedy
 
           
11/441,908
  US   5/26/2006   Stackable tier structure comprising prefabricated high
density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
11/429,468
  US   5/5/2006   Global positioning using planetary constants

Sapir Itzhak

 

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                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
11/415,891
  US   5/1/2006   Low power electronic circuit incorporating real time clock

Gary Gottlieb
 
           
11/350,974
  US   2/8/2006   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd; Daniel Michaels
 
           
11/301,645
  US   12/12/2005   Cornerbond assembly comprising three-dimensional electronic
modules

Albert Douglas
 
           
11/259,683
  US   10/25/2005   Stacked microelectronic layer and module with three-axis
channel T-connects

Keith D. Gann; W. Eric Boyd
 
           
11/248,659
  US   10/11/2005   Anti-tamper module

Volkan H. Ozguz; John Leon
 
           
10/178,390
  US   6/24/2002   Video event capture, storage and processing method and
apparatus

Randolph S. Carlson
 
           
60/993,689
  US       Chip scale vacuum pump

Itzhak Sapir
 
           
11/150,712
  US   6/10/2005   Stackable semiconductor chip layer comprising prefabricated
trench interconnect vias

W. Eric Boyd; Angel Pepe; James Yamaguchi; Volkan Ozguz; Andrew Camien; Douglas
Albert
 
           
11/062,507
  US   2/22/2005   BGA-scale stacks comprised of layers containing integrated
circuit die and a method for making the same

Gann Keith; William E. Boyd
 
           
12/008,253
  US   1/8/2008   Microcombustion power system

Ying Hsu
 
           
61/007,497
  US   12/12/2007   Forced vibration piezo generator

Itzhak Sapir

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
SE0570479
(SE92905662.0)
  SE   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
NL0570479
(NL92905662.0)
  NL   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
JP2005-507894
  JP   1/16/2006   Stackable layers containing ball grid array packages

Inventorship not available
 
           
JP2006-286556
  JP   10/20/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
JP2000-591490
  JP   12/30/1999   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
JP3308265
(JP12-554175)
  JP   6/10/1999   IC stack utilizing flexible circuits with BGA contacts

Eide, Floyd K.
 
           
JP3511008
(JP12-553982)
  JP   6/10/1999   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
JP3544974
(JP06-0502691)
  JP   5/5/1993   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
GB0570479
(GB92905662.0)
  GB   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
GB1097467
(GB9992850.2)
  GB   11/2/2006
(6/10/1993)   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
GB1596433
(GB04394026.1)
  GB   1/2/2008 (5/12/2004)   A method for creating neo-wafers from singulated
integrated circuit die and a device made according to the method Stern, Jonathan
Michael

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
GB0596075
(GB93911250.4)
  GB   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
GB0683968
(GB94903352.6)
  GB   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
GB0695494
(GB94915397.7)
  GB   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
GB0713609
(GB94925876.8)
  GB   5/7/2003
(8/12/1994)   Stack of IC chips as substitute for single IC chip Ludwig, David
E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
GB067087
(GB94909418.9)
  GB   (12/16/1993)   Fabricating stacks of IC chips by segmenting a larger
stack

MINIHAN JOSEPH A; PEPE ANGEL A
 
           
FR1097467
(FR99928570.2)
  FR   11/2/2006
(6/10/1993)   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
FR1596433
(FR04394026.1)
  FR   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
FR0596075
(FR93911250.4)
  FR   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
FR0683968
(FR94903352.6)
  FR   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
FR0695494
(FR94915397.7)
  FR   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
FR0713609
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  FR   5/7/2003
(8/12/1994)   Stack of IC chips as substitute for single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
EP02705988.0
  EP   1/25/2002   A stackable microcircuit layer formed from a plastic
encapsulated microcircuit and method of making the same

Albert, Douglas M.; Gann, Keith D.
 
           
EP06255467.0
  EP   10/24/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
EP99967712.3
  EP   12/30/1999   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
EP99928570.2
  EP   6/10/1993   IC stack utilizing flexible circuits with BGA contacts

Eide, Floyd K.
 
           
EP02805694.3
  EP   7/16/2002   Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
EP02789292.6
  EP   10/25/2002   Stackable layers containing encapsulated integrated circuit
chips with one or more overlying interconnect layers and a method of making the
same

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
EP02798173.7
  EP   9/9/2002   Stacking of multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
EP95935157.8
  EP   9/27/1995   Infrared wireless communication between electronic system
components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale
 
           
EP03721978.9
  EP   4/22/2003   Method and apparatus for connecting vertically stacked
integrated circuit chips

Gann, Keith D.; Albert, Douglas M.
 
           
DE69232116
(DE69232116)
  DE   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
DE69330630
(DE69330630)
  DE   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
DE69426695
(DE6942669.5)
  DE   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
DE602004011025
(DE602004011025)
  DE   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
PCT/US06/039915
  WO   8/26/2006   MEMS cooling device

Itzhak Sapir
 
           
4,814,629
(07/107352)
  US   3/21/1989
(10/13/1987)   Pixel displacement by series-parallel analog switching

Arnold, Jack L.
 
           
11/825,643
  US   7/7/2007   Ball grid array package format layers and structure

Keith Gann
 
           
EP06738029.5
  EP   3/10/2006   Method for making a neo-layer comprising embedded discrete
components

Sambo S. He

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
JP2000-519921
  JP   11/10/1998   Method for thinning semiconductor wafers with circuits and
wafers made by the same

Inventorship not available
 
           
JP2004-72804
  JP   3/15/2004   Stackable layer, mini stack, and laminated electronic module

Volkan Ozguz
 
           
EP06735419.1
  EP   2/14/2006   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd
 
           
5,635,010
  US   4/14/1995   Dry adhesive joining of layers of electronic devices

Angel A. Pepe
 
           
6,731,121
  US   10/16/2000   Highly configurable capacitive transducer interface circuit

Christ Ying Hsu
 
           
6,513,380
  US   6/19/2001   Mems sensor with single central anchor and motion-limiting
connection geometry

John William Reeds III
 
           
6,715,352
  US   6/26/2001   Method of designing a flexure system for tuning the modal
response of a decoupled micromachined gyroscope and a gyroscoped designed
according to the method

Michael J. Tracy
 
           
6,370,937
  US   3/19/2001   Method of canceling quadrature error in an angular rate
sensor

Ying Wen Hsu

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
JP2664754
  JP   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go
 
           
JP2001-533437
  JP   10/16/2000   Highly configurable capacitive transducer interface circuit

Christ Ying Hsu
 
           
EP02744453.8
  EP   6/18/2002   Mems sensor with single central anchor and motion-limiting
connection geometry

John William Reeds III
 
           
EP02746710.9
  EP   6/18/2002   Method of designing a flexure system for tuning the modal
response of a decoupled micromachined gyroscope and a gyroscoped designed
according to the method

Michael J. Tracy
 
           
JP2002-562134
  JP   1/25/2002   A stackable microcircuit layer formed from a plastic
encapsulated microcircuit and method of making the same
 
           
12/287,691
  US   10/10/2008   Three dimensional LADAR module with alignment reference
insert circuitry comprising high density interconnect structure

John Kennedy; David Ludwig; Christian Krutzik
 
           
EP03818224.2
  EP   8/8/2003   Stackable layers containing ball grid array packages

Eide, Floyd K.

 

--------------------------------------------------------------------------------

 

Exhibit B, revised
ASSIGNMENT OF PATENT RIGHTS
     For good and valuable consideration, the receipt of which is hereby
acknowledged, Irvine Sensors Corporation, a Delaware corporation, with an office
at 3001 Redhill Ave., Bldg. 4, Suite 108, Costa Mesa, CA 92672 (“Assignor”),
does hereby sell, assign, transfer, and convey unto Aprolase Development Co.,
LLC, a Delaware limited liability company, having an address at 2711 Centerville
Road, Suite 400, Wilmington, DE 19808 (“Assignee”), or its designees, all right,
title, and interest that exist today and may exist in the future in and to any
and all of the following (collectively, the “Patent Rights”):
     (a) the provisional patent applications, patent applications and patents
listed in the table below (the “Patents”);

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
5,235,672
(07/651,477)
  US   8/10/1993
(2/6/1991)   Hardware for electronic neural network

Carson, John C.
 
           
6,389,404
(09/223,476)
  US   5/14/2002
(12/30/1998)   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
6,650,704
(09/427,384)
  US   11/18/2003
(10/25/1999)   Method of producing a high quality, high resolution image from a
sequence of low quality, low resolution images that are undersampled and subject
to jitter

Carlson, Randolph S.; Arnold, Jack L.; Feldmus, Valentine G.
 
           
6,829,237
(09/973,857)
  US   12/7/2004 (10/9/2001)   High speed multi-stage switching network formed
from stacked switching layers Carson, John C.; Ozguz, Volkan H.
 
           
7,082,591
(10/346,363)
  US   7/25/2006
(1/17/2003)   Method for effectively embedding various integrated circuits
within field programmable gate arrays

Carlson, Randolph S.
 
           
6,856,167
(10/347,038)
  US   2/15/2005
(1/17/2003)   Field programmable gate array with a variably wide word width
memory

Ozguz, Volkan H.; Carlson, Randolph S.; Gann, Keith D.; Leon, John P.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
7,265,579
(11/037,490)
  US   9/4/2007
(1/18/2005)   Field programmable gate array incorporating dedicated memory
stacks

Carlson, Randolph Stuart; Ozguz, Volkan; Gann, Keith D.; Leon, John P.
 
           
5,508,836
(08/305,066)
  US   4/16/1996 (9/13/1994)   Infrared wireless communication between
electronic system components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale
 
           
5,635,705
(08/526,415)
  US   6/3/1997
(9/11/1995)   Sensing and selecting observed events for signal processing

Saunders, Christ H.
 
           
6,195,268
(09/031,435)
  US   2/27/2001
(2/26/1998)   Stacking layers containing enclosed IC chips

Eide, Floyd K.
 
           
5,045,685
(07/534,969)
  US   9/3/1991
(6/6/1990)   Analog to digital conversion on multiple channel IC chips

Wall, Llewellyn E.
 
           
5,104,820
(07/720,025)
  US   4/14/1992
(6/24/1991)   Method of fabricating electronic circuitry unit containing stacked
IC layers having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
5,279,991
(07/996,794)
  US   1/18/1994
(12/24/1992)   Method for fabricating stacks of IC chips by segmenting a larger
stack

Minahan, Joseph A.; Pepe, Angel A.
 
           
5,432,318
(08/178,923)
  US   7/11/1995
(1/7/1994)   Apparatus for segmenting stacked IC chips

Minahan, Joseph A.
 
           
5,304,790
(07/956,914)
  US   4/19/1994
(10/5/1992)   Apparatus and system for controllably varying image resolution to
reduce data output

Arnold, Jack
 
           
5,347,428
(07/985,837)
  US   9/13/1994
(12/3/1992)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
5,406,701
(08/120,675)
  US   4/18/1995
(9/13/1993)   Fabrication of dense parallel solder bump connections

Pepe, Angel A.; Reinker, David M.; Minahan, Joseph A.
 
           
5,424,920
(08/232,739)
  US   6/13/1995
(4/25/1994)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
5,432,729
(08/255,465)
  US   7/11/1995
(6/8/1994)   Electronic module comprising a stack of IC chips each interacting
with an IC chip secured to the stack

Carson, John C.; Some, Raphael R.
 
           
5,581,498
(08/326,645)
  US   12/3/1996
(10/20/1994)   Stack of IC chips in lieu of single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
5,688,721
(08/62,2671)
  US   11/18/1997
(3/26/1996)   3D stack of IC chips having leads reached by vias through
passivation covering access plane

Johnson, Tony K.
 
           
5,953,588
(08/777,747)
  US   9/14/1999
(12/21/1996)   Stackable layers containing encapsulated IC chips

Camien, Andrew N; Yamaguchi, James S.
 
           
6,072,234
(09/316,740)
  US   6/6/2000
(5/21/1999)   Stack of equal layer neo-chips containing encapsulated IC chips of
different sizes

Camien, Andrew N.; Yamaguchi, James S.
 
           
5,955,668
(09/166,458)
  US   9/21/1999
(10/5/1998)   Multi-element micro gyro

Hsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.
 
           
6,089,089
(09/301,847)
  US   7/18/2000
(4/29/1999)   Multi-element micro gyro

Hsu, Ying W.
 
           
6,578,420
(09/604,782)
  US   6/17/2003
(6/26/2000)   Multi-axis micro gyro structure

Hsu, Ying Wen
 
           
6,014,316
(09/095,416)
  US   1/11/2000
(6/10/1998)   IC stack utilizing BGA contacts

Eide, Floyd K.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
6,028,352
(09/095,415)
  US   2/22/2000
(6/10/1998)   IC stack utilizing secondary lead frames

Eide, Floyd K.
 
           
6,117,704
(09/282,704)
  US   9/12/2000
(3/31/1999)   Stackable layers containing encapsulated chips

Yamaguchi, James S.; Ozguz, Volkan H.; Camien, Andrew N.
 
           
6,476,392
(09/853,819)
  US   11/5/2002
(5/11/2001)   Method and apparatus for temperature compensation of an uncooled
focal plane array

Kaufman, Charles S.; Carson, Randolph S.; Hornback, William B.
 
           
6,891,160
(10/281,393)
  US   5/10/2005
(10/25/2002)   Method and apparatus for temperature compensation of an uncooled
focal plane array

Kaufman, Charles S.; Carson, Randolph S.; Hornback, William B.
 
           
7,235,785
(11/048,634)
  US   6/26/2007
(1/31/2005)   Imaging device with multiple fields of view incorporating
memory-based temperature compensation of an uncooled focal plane array

Hornback, Bert; Harwood, Doug; Boyd, W. Eric; Carlson, Randy
 
           
6,596,997
(09/921,525)
  US   7/22/2003
(8/3/2001)   Retro-reflector warm stop for uncooled thermal imaging cameras and
method of using the same

Kaufman, Charles S.
 
           
6,706,971
(10/142,557)
  US   3/16/2004
(5/10/2002)   Stackable microcircuit layer formed from a plastic encapsulated
microcircuit

Albert, Douglas M.; Gann, Keith D.
 
           
7,174,627
(10/338,974)
  US   2/13/2007
(1/9/2003)   Method of fabricating known good dies from packaged integrated
circuits

Gann, Keith D.
 
           
6,560,109
(09/949,024)
  US   5/6/2003
(9/7/2001)   Stack of multilayer modules with heat-focusing metal layer

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
6,717,061
(09/949,512)
  US   4/6/2004
(9/7/2001)   Stacking of multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
6,734,370
(09/948,950)
  US   5/11/2004
(9/7/2001)   Multilayer modules with flexible substrates

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
7,127,807
(10/431,914)
  US   10/31/2006
(5/7/2003)   Process of manufacturing multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
6,797,537
(09/938,686)
  US   9/28/2004
(10/30/2001)   Method of making stackable layers containing encapsulated
integrated circuit chips with one or more overlaying interconnect layers

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
6,784,547
(10/302,680)
  US   8/31/2004
(11/21/2002)   Stackable layers containing encapsulated integrated circuit chips
with one or more overlying interconnect layers

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
7,239,012
(10/951,990)
  US   7/3/2007
(9/28/2004)   Three-dimensional module comprised of layers containing IC chips
with overlying interconnect layers

Pepe, Angel; Yamaguchi, James
 
           
6,806,559
(10/128,728)
  US   10/19/2004
(4/22/2002)   Method and apparatus for connecting vertically stacked integrated
circuit chips

Gann, Keith D.; Albert, Douglas M.
 
           
6,912,862
(10/615,641)
  US   7/5/2005
(7/8/2003)   Cryopump piston position tracking

Sapir, Itzhak
 
           
6,967,411
(10/360,244)
  US   11/22/2005
(2/7/2003)   Stackable layers containing ball grid array packages

Eide, Floyd K.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
7,242,082
(11/229,351)
  US   6/10/2007
(9/15/2005)   Stackable layer containing ball grid array package

Eide, Floyd
 
           
6,993,835
(10/726,888)
  US   2/7/2006 (12/4/2003)   Method for electrical interconnection of angularly
disposed conductive patterns

Albert, Douglas Marice
 
           
6,998,328
(10/701,783)
  US   2/14/2006
(11/5/2003)   Method for creating neo-wafers from singulated integrated circuit
die and a device made according to the method

Stern, Jonathan Michael
 
           
7,417,323
(10/703,177)
  US   (11/6/2003)   Neo-wafer device and method

Sambo S. He
 
           
7,198,965
(11/354,370)
  US   4/3/2007
(2/14/2006)   Method for making a neo-layer comprising embedded discrete
components

He, Sambo
 
           
7,180,579
(10/806,037)
  US   2/20/2007
(3/22/2004)   Three-dimensional imaging processing module incorporating stacked
layers containing microelectronic circuits

Ludwig, David E.; Kennedy, John V.; Kleinhans, William; Liu, Tina; Krutzik,
Christian
 
           
7,436,494
(11/706,724)
  US   10/14/2008
(2/15/2007)   Three-dimensional LADAR module with alignment reference insert
circuitry

Ludwig, David E.; Kennedy, John V.; Kleinhans, William; Liu, Tina; Krutzik,
Christian
 
           
7,335,576
(11/197,828)
  US   2/26/2008
(8/5/2005)   Method for precision integrated circuit die singulation using
differential etch rates

David, Ludwig; Yamaguchi, James; Clark, Stuart; Boyd, W. Eric
 
           
7,380,459
(11/654,292)
  US   6/3/2008
(1/16/2007)   Absolute pressure sensor

Sapir, Itzhak
 
           
10/968,572
  US   10/19/2004   Vertically stacked pre-packaged integrated circuit chips

Keith Gann; Douglas N. Albert

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
7,440,449
(10/960,712)
  US   10/6/2004   High speed switching module comprised of stacked layers
incorporating T-connect structures

John C. Carson; Volkan H. Orguz
 
           
11/977,447
  US   10/24/2007   Wire bond method for angularly disposed conductive pads and
a device made from the method

Randy Wayne Bindrup
 
           
11/897,938
  US   08/31/2007   Field programmable gate array utilizing dedicated memory
stacks in a vertical layer format

Ozguz, Volkan; Carlson, Randolph Stuart; Gann, Keith D.; Leon, John P.; Boyd, W
Eric
 
           
11/825,643
  US   7/7/2007   Ball grid array package format layers and structure

Keith Gann; W Eric Boyd
 
           
11/807,671
  US   5/30/2007   Large Format Thermoelectic Infrared Detector and a Method of
Fabrication

Ying Hsu
 
           
11/731,154
  US   3/31/2007   Ball Grid Array Stack

Frank Mantz
 
           
11/524,090
  US   9/20/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
11/511,117
  US   8/26/2006   MEMS cooling device

Itzhak Sapir
 
           
11/499,403
  US   8/4/2006   High density interconnect assembly comprising stacked
electronic module

John V. Kennedy
 
           
11/441,908
  US   5/26/2006   Stackable tier structure comprising prefabricated high
density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
11/429,468
  US   5/5/2006   Global positioning using
planetary constants

Sapir Itzhak

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
11/415,891
  US   5/1/2006   Low power electronic circuit incorporating real time clock

Gary Gottlieb
 
           
11/350,974
  US   2/8/2006   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd; Daniel Michaels
 
           
11/301,645
  US   12/12/2005   Cornerbond assembly comprising three-dimensional electronic
modules

Albert Douglas
 
           
11/259,683
  US   10/25/2005   Stacked microelectronic layer and module with three-axis
channel T-connects

Keith D. Gann; W. Eric Boyd
 
           
11/248,659
  US   10/11/2005   Anti-tamper module

Volkan H. Ozguz; John Leon
 
           
10/178,390
  US   6/24/2002   Video event capture, storage and processing method and
apparatus

Randolph S. Carlson
 
           
60/993,689
  US       Chip scale vacuum pump

Itzhak Sapir
 
           
11/150,712
  US   6/10/2005   Stackable semiconductor chip layer comprising prefabricated
trench interconnect vias

W. Eric Boyd; Angel Pepe; James Yamaguchi; Volkan Ozguz; Andrew Camien; Douglas
Albert
 
           
11/062,507
  US   2/22/2005   BGA-scale stacks comprised of layers containing integrated
circuit die and a method for making the same

Gann Keith; William E. Boyd
 
           
12/008,253
  US   1/8/2008   Microcombustion power system

Ying Hsu
 
           
61/007,497
  US   12/12/2007   Forced vibration piezo generator

Itzhak Sapir
 
           
SE0570479 (SE92905662.0)
  SE   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
NL0570479 (NL92905662.0)
  NL   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
JP2005-507894
  JP   1/16/2006   Stackable layers containing ball grid array packages

Inventorship not available
 
           
JP2006-286556
  JP   10/20/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
JP2000-591490
  JP   12/30/1999   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
JP3308265
(JP12-554175)
  JP   6/10/1999   IC stack utilizing flexible circuits with BGA contacts

Eide, Floyd K.
 
           
JP3511008
(JP12-553982)
  JP   6/10/1999   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
JP3544974
(JP06-0502691)
  JP   5/5/1993   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
GB0570479 (GB92905662.0)
  GB   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
GB1097467 (GB9992850.2)
  GB   11/2/2006
(6/10/1993)   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
GB1596433 (GB04394026.1)
  GB   1/2/2008 (5/12/2004)   A method for creating neo-wafers from singulated
integrated circuit die and a device made according to the method Stern, Jonathan
Michael
 
           
GB0596075 (GB93911250.4)
  GB   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
GB0683968 (GB94903352.6)
  GB   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
GB0695494 (GB94915397.7)
  GB   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
GB0713609 (GB94925876.8)
  GB   5/7/2003
(8/12/1994)   Stack of IC chips as substitute for single IC chip Ludwig, David
E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
GB067087
(GB94909418.9)
  GB   (12/16/1993)   Fabricating stacks of IC chips by segmenting a larger
stack

MINIHAN JOSEPH A; PEPE ANGEL A
 
           
FR1097467 (FR99928570.2)
  FR   11/2/2006
(6/10/1993)   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
FR1596433 (FR04394026.1)
  FR   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
FR0596075 (FR93911250.4)
  FR   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
FR0683968 (FR94903352.6)
  FR   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
FR0695494 (FR94915397.7)
  FR   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
FR0713609 (FR94925876.8)
  FR   5/7/2003
(8/12/1994)   Stack of IC chips as substitute for single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
EP02705988.0
  EP   1/25/2002   A stackable microcircuit layer formed from a plastic
encapsulated microcircuit and method of making the same

Albert, Douglas M.; Gann, Keith D.
 
           
EP06255467.0
  EP   10/24/2006   Stackable tier structure comprising high density feedthrough

Volkan Ozguz; Jonathan Stern
 
           
EP99967712.3
  EP   12/30/1999   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
EP99928570.2
  EP   6/10/1993   IC stack utilizing flexible circuits with BGA contacts

Eide, Floyd K.
 
           
EP02805694.3
  EP   7/16/2002   Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
EP02789292.6
  EP   10/25/2002   Stackable layers containing encapsulated integrated circuit
chips with one or more overlying interconnect layers and a method of making the
same

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
EP02798173.7
  EP   9/9/2002   Stacking of multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
EP95935157.8
  EP   9/27/1995   Infrared wireless communication between electronic system
components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale
 
           
EP03721978.9
  EP   4/22/2003   Method and apparatus for connecting vertically stacked
integrated circuit chips

Gann, Keith D.; Albert, Douglas M.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
DE69232116
(DE69232116)
  DE   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
DE69330630
(DE69330630)
  DE   8/22/2001
(5/5/1993)   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
DE69426695 (DE6942669.5)
  DE   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
DE602004011025
(DE602004011025)
  DE   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
PCT/US06/039915
  WO   8/26/2006   MEMS cooling device

Itzhak Sapir
 
           
4,814,629
(07/107352)
  US   3/21/1989
(10/13/1987)   Pixel displacement by series- parallel analog switching

Arnold, Jack L.
 
           
11/825,643
  US   7/7/2007   Ball grid array package format layers and structure
Keith Gann
 
           
EP06738029.5
  EP   3/10/2006   Method for making a neo-layer comprising embedded discrete
components
Sambo S. He
 
           
JP2000-519921
  JP   11/10/1998   Method for thinning semiconductor wafers with circuits and
wafers made by the same Inventorship not available
 
           
JP2004-72804
  JP   3/15/2004   Stackable layer, mini stack, and laminated electronic module
Volkan Ozguz
 
           
EP06735419.1
  EP   2/14/2006   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd
 
           
5,635,010
  US   4/14/1995   Dry adhesive joining of layers of electronic devices
Angel A. Pepe
 
           
6,731,121
  US   10/16/2000   Highly configurable capacitive transducer interface circuit
Christ Ying Hsu

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Patent or Application No.  
Country   Filing Date   Named Inventor
6,513,380
  US   6/19/2001   Mems sensor with single central anchor and motion-limiting
connection geometry
John William Reeds III
 
           
6,715,352
  US   6/26/2001   Method of designing a flexure system for tuning the modal
response of a decoupled micromachined gyroscope and a gyroscoped designed
according to the method
Michael J. Tracy
 
           
6,370,937
  US   3/19/2001   Method of canceling quadrature error in an angular rate
sensor

Ying Wen Hsu
 
           
JP2664754
  JP   1/4/1998   High density electronic package comprising stacked sub-modules
Tiong C. Go
 
           
JP2001-533437
  JP   10/16/2000   Highly configurable capacitive transducer interface circuit

Christ Ying Hsu
 
           
EP02744453.8
  EP   6/18/2002   Mems sensor with single central anchor and motion-limiting
connection geometry
John William Reeds III
 
           
EP02746710.9
  EP   6/18/2002   Method of designing a flexure system for tuning the modal
response of a decoupled micromachined gyroscope and a gyroscoped designed
according to the method
Michael J. Tracy
 
           
JP2002-562134
  JP   1/25/2002   A stackable microcircuit layer formed from a plastic
encapsulated microcircuit and method of making the same
 
           
12/287,691
  US   10/10/2008   Three dimensional LADAR module with alignment reference
insert circuitry comprising high density interconnect structure
John Kennedy; David Ludwig; Christian Krutzik
 
           
EP03818224.2
  EP   8/8/2003   Stackable layers containing ball grid array packages

Eide, Floyd K.

     (b) all patents and patent applications (i) to which any of the Patents
directly or indirectly claims priority, (ii) for which any of the Patents
directly or indirectly forms a basis for priority, and/or (iii) that were
co-owned applications that incorporate by reference, or are incorporated by
reference into, the Patents;

 

--------------------------------------------------------------------------------

 

     (c) all reissues, reexaminations, extensions, continuations, continuations
in part, continuing prosecution applications, requests for continuing
examinations, divisions, registrations of any item in any of the foregoing
categories (a) and (b);
     (d) all foreign patents, patent applications, and counterparts relating to
any item in any of the foregoing categories (a) through (c), including, without
limitation, certificates of invention, utility models, industrial design
protection, design patent protection, and other governmental grants or
issuances;
     (e) all items in any of the foregoing in categories (b) through (d),
whether or not expressly listed as Patents below and whether or not claims in
any of the foregoing have been rejected, withdrawn, cancelled, or the like;
     (f) inventions, invention disclosures, and discoveries described in any of
the Patents and/or any item in the foregoing categories (b) through (e) that
(i) are included in any claim in the Patents and/or any item in the foregoing
categories (b) through (e), (ii) are subject matter capable of being reduced to
a patent claim in a reissue or reexamination proceedings brought on any of the
Patents and/or any item in the foregoing categories (b) through (e), and/or
(iii) could have been included as a claim in any of the Patents and/or any item
in the foregoing categories (b) through (e);
     (g) all rights to apply in any or all countries of the world for patents,
certificates of invention, utility models, industrial design protections, design
patent protections, or other governmental grants or issuances of any type
related to any item in any of the foregoing categories (a) through (f),
including, without limitation, under the Paris Convention for the Protection of
Industrial Property, the International Patent Cooperation Treaty, or any other
convention, treaty, agreement, or understanding;
     (h) all causes of action (whether known or unknown or whether currently
pending, filed, or otherwise) and other enforcement rights under, or on account
of, any of the Patents and/or any item in any of the foregoing categories
(b) through (g), including, without limitation, all causes of action and other
enforcement rights for
          (1) damages,
          (2) injunctive relief, and
          (3) any other remedies of any kind
for past, current, and future infringement; and
     (i) all rights to collect royalties and other payments under or on account
of any of the Patents and/or any item in any of the foregoing categories
(b) through (h).
     Assignor represents, warrants and covenants that:
(1) Assignor has the full power and authority, and has obtained all third party
consents, approvals and/or other authorizations required to enter into this
Agreement and to carry out its obligations hereunder, including the assignment
of the Patent Rights to Assignee; and

 

--------------------------------------------------------------------------------

 

(2) Assignor owns, and by this document assigns to Assignee, all right, title,
and interest to the Patent Rights, including, without limitation, all right,
title, and interest to sue for infringement of the Patent Rights. Assignor has
obtained and properly recorded previously executed assignments for the Patent
Rights as necessary to fully perfect its rights and title therein in accordance
with governing law and regulations in each respective jurisdiction. The Patent
Rights are free and clear of all liens, claims, mortgages, security interests or
other encumbrances, and restrictions. There are no actions, suits,
investigations, claims or proceedings threatened, pending or in progress
relating in any way to the Patent Rights. There are no existing contracts,
agreements, options, commitments, proposals, bids, offers, or rights with, to,
or in any person to acquire any of the Patent Rights.
     Assignor hereby authorizes the respective patent office or governmental
agency in each jurisdiction to issue any and all patents, certificates of
invention, utility models or other governmental grants or issuances that may be
granted upon any of the Patent Rights in the name of Assignee, as the assignee
to the entire interest therein.
Assignor will, at the reasonable request of Assignee and without demanding any
further consideration therefore, do all things necessary, proper, or advisable,
including without limitation, the execution, acknowledgment, and recordation of
specific assignments, oaths, declarations, and other documents on a
country-by-country basis, to assist Assignee in obtaining, perfecting,
sustaining, and/or enforcing the Patent Rights. The terms and conditions of this
Assignment of Patent Rights will inure to the benefit of Assignee, its
successors, assigns, and other legal representatives and will be binding upon
Assignor, its successors, assigns, and other legal representatives.
     IN WITNESS WHEREOF this Assignment of Patent Rights is executed at Costa
Mesa, California on March 16, 2009.

          ASSIGNOR:

Irvine Sensors Corporation
      By:   /s/ John J. Stuart, Jr.         Name:   John J. Stuart, Jr.       
Title:   Sr. VP & Chief Financial Officer       (Signature MUST be attested)   
   

ATTESTATION OF SIGNATURE PURSUANT TO 28 U.S.C. § 1746
The undersigned witnessed the signature of John J. Stuart, Jr. to the above
Assignment of Patent Rights on behalf of Irvine Sensors Corporation and makes
the following statements:
1. I am over the age of 18 and competent to testify as to the facts in this
Attestation block if called upon to do so.

 

--------------------------------------------------------------------------------

 

2. John J. Stuart, Jr is personally known to me (or proved to me on the basis of
satisfactory evidence) and appeared before me on 16 March, 2009 to execute the
above Assignment of Patent Rights on behalf of Irvine Sensors Corporation.
3. John J. Stuart, Jr subscribed to the above Assignment of Patent Rights on
behalf of Irvine Sensors Corporation.
I declare under penalty of perjury under the laws of the United States of
America that the statements made in the three (3) numbered paragraphs
immediately above are true and correct.

          EXECUTED on 16 March, 2009 (date)
      /s/ John C. Carson       Print name: John C. Carson           

 

--------------------------------------------------------------------------------

 

Exhibit C, revised
ASSIGNMENT OF RIGHTS IN CERTAIN ASSETS
     For good and valuable consideration, the receipt of which is hereby
acknowledged, Irvine Sensors Corporation, a Delaware corporation, with an office
at 3001 Redhill Ave., Bldg. 4, Suite 108, Costa Mesa, CA 92672 (“Assignor”),
does hereby sell, assign, transfer, and convey unto Aprolase Development Co.,
LLC, a Delaware limited liability company, having an address at 2711 Centerville
Road, Suite 400, Wilmington, DE 19808 (“Assignee”), or its designees, the right,
title, and interest in and to any and all of the following provisional patent
applications, patent applications, patents, and other governmental grants or
issuances of any kind (the “Certain Assets”):

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
PCT/US00/029448
  WO   10/25/2000   SYSTEM AND METHODS FOR PRODUCING HIGH RESOLUTION IMAGES FROM
A VIDEO SEQUENCE OF LOWER RESOLUTION IMAGES

CARLSON RANDOLPH S; ARNOLD JACK L; FELDMUS VALENTIN G
 
           
PCT/US92/005348
  WO   6/24/1992   Fabricating electronic circuitry unit containing stacked IC
layers having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
PCT/US03/004462
  WO   5/5/1993   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
PCT/US99/013171
  WO   6/10/1999   IC stack utilizing flexible circuits with BGA contacts

Eide, Floyd K.
 
           
PCT/US06/008920
  WO   3/10/2006   Method for making a neo-layer
comprising embedded discrete
components

He, Sambo
 
           
PCT/US01/031583
  WO   10/9/2001   High speed switching module comprised of stacked layers
incorporating T-connect structures

John C. Carson; Volkan H. Orguz
 
           
PCT/US02/002276
  WO   1/25/2002   A stackable microcircuit layer formed from a plastic
encapsulated microcircuit and method of making the same

Albert, Douglas M.; Gann, Keith D.
 
           
PCT/US02/006848
  WO   3/4/2002   Retro-reflector warm stop for uncooled thermal imaging cameras
and method of using the same

Kaufman, Charles S.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
PCT/US02/022617
  WO   7/16/2002   Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
PCT/US02/028628
  WO   9/9/2002   Stacking of multilayer modules

Yamaguchi, James Satsuo; Pepe, Angel Antonio; Ozguz, Volkan H.; Camien, Andrew
Nelson
 
           
PCT/US02/034339
  WO   10/25/2002   Stackable layers containing encapsulated integrated circuit
chips with one or more overlying interconnect layers and a method of making the
same

Pepe, Angel Antonio; Yamaguchi, James Satsuo
 
           
PCT/US02/19779
  WO   6/24/2002   Video event capture, storage and processing method and
apparatus

Randolph S. Carlson
 
           
PCT/US03/009190
  WO   9/27/1993   Fabrication of dense parallel solder bump connections

Pepe, Angel A.; Reinker, David M.; Minahan, Joseph A.
 
           
PCT/US03/013569
  WO   4/22/2003   Method and apparatus for connecting vertically stacked
integrated circuit chips

Gann, Keith D.; Albert, Douglas M.
 
           
PCT/US03/024706
  WO   08/08/2003   Stackable layers containing ball grid array packages

Eide, Floyd K.
 
           
PCT/US83/01142
  WO   7/25/1983   Multiplexer circuitry for high density analog signals
 
           
PCT/US88/003084
  WO   9/8/1988   Bonding of aligned conductive bumps on adjacent surfaces

Go, Tiong C.
 
           
PCT/US92/000780
  WO   1/29/1992   Hardware for electronic neural network

Carson, John C.
 
           
PCT/US92/003705
  WO   6/28/1990   Fabricating electronic circuitry unit containing stacked IC
layers having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
PCT/US93/009470
  WO   10/5/1993   Apparatus and system for controllably varying image
resolution to reduce data output

Arnold, Jack
 
           
PCT/US93/011601
  WO   12/1/1993   Module comprising IC memory stack dedicated to and
structurally combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
PCT/US93/012268
  WO   12/16/1993   Fabricating stacks of IC chips by segmenting a larger stack

MINIHAN JOSEPH A; PEPE ANGEL A
 
           
PCT/US94/004322
  WO   4/19/1994   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
PCT/US94/009186
  WO   8/12/1994   Stack of IC chips as substitute for single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.
 
           
PCT/US95/002851
  WO   3/7/1995   3D stack of IC chips having leads reached by vias through
passivation covering access plane

Johnson, Tony K.
 
           
PCT/US95/012378
  WO   9/27/1995   Infrared wireless communication between electronic system
components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale
 
           
PCT/US96/000746
  WO   1/22/1996   Stackable modules and multimodular assemblies

Carson, John C.; DeCaro, Robert E.; Hsu, Ying; Miyake, Michael K.
 
           
PCT/US96/014610
  WO   9/11/1996   SENSING AND SELECTING OBSERVED EVENTS
FOR SIGNAL PROCESSING

SAUNDERS CHRIST H
 
           
PCT/US98/021798
  WO   10/14/1998   Multi-element micro gyro

Hsu, Ying Wen
 
           
PCT/US98/023929
  WO   11/10/1998   Method for thinning semiconductor wafers with circuits and
wafers made by the same

Albert, Douglas; Ogzuz Volkhan H

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
PCT/US99/001734
  WO   3/23/1990   Analog to digital conversion incorporated in Z-technology
module

Wall, Llewellyn E.
 
           
PCT/US99/004211
  WO   2/25/1999   STACKING LAYERS CONTAINING ENCLOSED
IC CHIPS

EIDE FLOYD
 
           
PCT/US99/031124
  WO   12/30/1999   Neural processing module with input architectures that make
maximal use of a weighted synapse array

Carson, John C.; Saunders, Christ H.
 
           
07/329,003
  US   3/27/1989   Analog to digital conversion on multiple channel IC chips

Wall, Llewellyn E.
 
           
07/377,241
  US   7/7/1989   Inventorship not available
 
           
07/884,719
  US   5/15/1992   Method for fabricating stacks of IC chips by segmenting a
larger stack

Minahan, Joseph A.; Pepe, Angel A.
 
           
07/884660
  US   5/15/1992   Non-conductive end layer for integrated stack of IC chips

Miyake, Michael K.
 
           
07/955461
  US   10/2/1992   Fabrication of dense parallel solder bump connections

Joseph Minahan
 
           
08/052,475
  US   4/23/1993   Electronic module comprising a stack of IC chips each
interacting with an IC chip secured to the stack face Carson, John C.; Some,
Raphael R.
 
           
08/106,909
  US   8/13/1993   Inventorship not available
 
           
08/213,149
  US   3/15/1994   3D stack of IC chips having leads reached by vias through
passivation covering access plane

Johnson, Tony K.
 
           
08/870,812
  US   6/6/1997   Multi-element micro gyro

Hsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.
 
           
08/943,305
  US   10/14/1997   Multi-element micro gyro

Hsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
09/190,378
  US   11/10/1998   Method for thinning semiconductor wafers with circuits and
wafers made by the same

Albert, Douglas
 
           
09/770,864
  US   1/26/2001   Method of making a stackable microcircuit layer from a
plastic encapsulated microcircuit

Douglas M. Albert; Keith D. Gann
 
           
10/197,006
  US   7/16/2002   Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
10/663,371
  US       Stacked microelectronic module with vertical interconnect vias Ogzuz,
Volkhan H;
 
           
10/805,849
  US   3/22/2004   Three-dimensional imaging device incorporating stacked layers
containing microelectronic circuits

David E. Ludwig; John V. Kennedy; Christian Krutzik
 
           
11/003,429
  US   12/6/2004   Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
60/036,759
  US   1/28/1997   Multi-element micro gyro

Hsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.
 
           
60/049,025
  US   6/9/1997   Stacking layers containing enclosed IC chips

Eide, Floyd K.
 
           
60/049,026
  US   6/9/1997   Stacking layers containing enclosed IC chips Eide, Floyd K.
 
           
60/049,582
  US   6/13/1997   IC stack utilizing BGA contacts

Eide, Floyd K.
 
           
60/065,088
  US        
 
           
60/238,797
  US   10/6/2000   High speed data switch with traverse-mated stacks containing
superconducting electronics

John Carson
 
           
60/274,120
  US        
 
           
60/305,353
  US       Biomonitor device

Ogzuz, Volkhan H
 
           
60/346,494
  US   1/9/2002   Low cost miniature computer and methods for making same Gann,
Keith

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
60/348,852
  US   1/17/2002   Field programmable gate array structure incorporating high
density support circuitry and method for making same

Ozguz, Volkan H.;
 
           
60/354,442
  US   2/7/2002   BGA layer and assembly and method for making same

Eide, Floyd K.
 
           
60/355,955
  US   2/12/2002   Stacked BGA assembly Eide, Floyd K.
 
           
60/394,167
  US   7/8/2002   Cryopump piston position tracking using an encoder

Sapir, Itzhak
 
           
60/410,895
  US       Wearable biomonitor with flexible thinned integrated circuit

Ogzuz, Volkhan H; Khashayar, Abbas
 
           
60/424,022
  US       NEO-wafers and NEO-chips, device and method

Sambo S. He
 
           
60/424,025
  US   11/6/2002   Creating wafers from singulated die

Stern, Jonathan Michael
 
           
60/462,677
  US   3/28/2003   High-speed transmitter and receiver incorporating
three-dimensional readout electronic module

David E. Ludwig;
 
           
60/546,598
  US   2/20/2004   BGA-scale stacks comprised of thin small outline packages and
method for making the same

Gann Keith; William E. Boyd
 
           
60/617,356
  US   10/8/2004   Anti-tamper module

Volkan H. Ozguz; John Leon
 
           
60/652,777
  US   2/14/2005   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd; Daniel Michaels
 
           
60/678,618
  US   5/5/2005   GPS incorporating low power real time clock circuitry

Itzhak Sapir
 
           
60/684,372
  US   5/26/2005   Stackable layers of encapsulated integrated circuit chips
interconnected with prefabricated via structures

Volkan Ozguz; Jonathan Stern

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
60/710,717
  US   8/24/2005   Surface trenched stackable layers

Keith Gann; Douglas N. Albert
 
           
60/711,375
  US   8/26/2005   High density interconnect scheme for stacked electronic
modules

John V. Kennedy
 
           
60/711,376
  US   8/26/2005   MEMS cooling device

Itzhak Sapir
 
           
60/758,922
  US   1/17/2006   Absolute pressure sensor

Sapir, Itzhak
 
           
60/628,742
  US   11/18/2004   Interface optimization of high density interconnects

Stewart Clark
 
           
60/617,426
  US   10/8/2004   Interface optimization of high density interconnects

Stewart Clark
 
           
RE33331
(07/336,017)
  US   9/11/1990
(4/10/1989)   Multiplexer circuitry for high density analog signals

Inventorship not available
 
           
4,490,626
(06/403,004)
  US   12/25/1984
(7/29/1982)   Multiplexer circuitry for high density analog signals

Carlson, Randolph S.
 
           
4,912,545
(07/097,797)
  US   3/27/1990
(9/16/1987)   Bonding of aligned conductive bumps on adjacent surfaces

Go, Tiong C.
 
           
4,983,533
(07/114,415)
  US   1/8/1991
(10/28/1987)   High-density electronic modules — process and product

Go, Tiong C.
 
           
4,290,844
(06/015070)
  US   9/22/1981
(2/26/1979)   Focal plane photo-detector mosaic array fabrication

Rotolante, Ralph A.; Koehler, Toivo
 
           
4,304,624
(05/855242)
  US   12/8/1981
(11/28/1977)   Method of fabricating a multi-layer structure for detector array
module

Carson, John C.; Dahlgren, Paul F.
 
           
4,352,715
(06/206993)
  US   10/5/1982
(11/17/1980)   Detector array module fabrication

Carson, John C.; Dahlgren, Paul F.
 
           
4,354,107
(06/206994)
  US   10/12/1982
(11/14/1980)   Detector array module-structure and fabrication

Carson, John C.; Dahlgren, Paul F.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
4,403,238
(06/213933)
  US   9/6/1983
(12/8/1980)   Detector array focal plane configuration

Clark, Stewart A.
 
           
4,449,044
(06/262296)
  US   5/15/1984
(5/11/1981)   Focal plane photo-detector mosaic array apparatus

Rotolante, Ralph A.; Koehler, Toivo
 
           
4,525,921
(06/517221)
  US   7/2/1985
(7/25/1983)   High-density electronic processing package-structure and
fabrication

Carson, John C.; Clark, Stewart A.
 
           
4,551,629
(06/572802)
  US   11/5/1985
(1/23/1984)   Detector array module-structure and fabrication

Carson, John C.; Clark, Stewart A.
 
           
4,555,623
(06/558099)
  US   11/26/1985
(12/5/1983)   Pre-amplifier in focal plane detector array

Bridgewater, Walter F.; De Caro, Robert E.; Larson, Roger; Wall, Llewellyn E.
 
           
4,596,948
(06/661727)
  US   6/24/1986
(10/17/1984)   Constant current source for integrated circuits

Wall, Llewellyn E.
 
           
4,617,160
(06/674096)
  US   10/14/1986
(11/23/1984)   Method for fabricating modules comprising uniformly stacked,
aligned circuit-carrying layers

Belanger, Robert J.; Bisignano, Alan G.
 
           
4,646,128
(06/720902)
  US   2/24/1987
(4/8/1985)   High-density electronic processing package—structure and
fabrication

Carson, John C.; Clark, Stewart A.
 
           
4,672,737
(06/761889)
  US   6/16/1987
(8/2/1985)   Detector array module fabrication process

Carson, John C.; Clark, Stewart A.
 
           
4,675,532
(06/795988)
  US   6/23/1987
(11/6/1985)   Combined staring and scanning photodetector sensing system having
both temporal and spatial filter in

Carson, John C.
 
           
4,704,319
(06/842159)
  US   11/3/1987
(3/21/1986)   Apparatus and method for fabricating modules comprising stacked
circuit-carrying layers

Belanger, Robert J.; Bisignano, Alan G.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
4,706,166
(06/856835)
  US   11/10/1987
(4/25/1986)   High-density electronic modules—process and product

Go, Tiong C.
 
           
4,764,846
(07/000562)
  US   8/16/1988
(1/5/1987)   High density electronic package comprising stacked sub-modules

Go, Tiong C.
 
           
4,779,005
(07/048551)
  US   10/18/1988
(5/11/1987)   Multiple detector viewing of pixels using parallel time delay and
integration circuitry

Arnold, Jack L.
 
           
4,791,286
(07/042686)
  US   12/13/1988
(4/27/1987)   Pre-amplifier in focal plane detector array

Wall, Llewellyn E.
 
           
4,806,761
(07/023644)
  US   2/21/1989
(3/9/1987)   Thermal imager incorporating electronics module having focal plane
sensor mosaic

Carson, John C.; Clark, Stewart A.
 
           
4,912,545
(07/097797)
  US   3/27/1990
(9/16/1987)   Bonding of aligned conductive bumps on adjacent surfaces

Go, Tiong C.
 
           
5,701,233
(08/376,799)
  US   12/23/1997
(1/23/1995)   Stackable modules and multimodular assemblies

Carson, John C.; DeCaro, Robert E.; Hsu, Ying; Miyake, Michael K.
 
           
5,745,631
(08/592,691)
  US   4/28/1998
(1/26/1996)   Self-aligning optical beam system

Reinker, David M.
 
           
NL0511218 (NL90917886.5)
  NL   3/12/1997
(6/28/1990)   Fabricating electronic circuitry unit containing stacked IC layers
having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
JP06-0515293
  JP   12/16/1993   Inventorship not available
 
           
JP97-0513369
  JP   9/27/1995   Infrared wireless communication between electronic system
components

DeCaro, Robert; Saunders, Christ H.; Maeding, Dale
 
           
JP02-0506137
  JP   3/23/1990   Inventorship not available
 
           
JP04-0505734
  JP   1/29/1992   Hardware for electronic neural network

Carson, John C.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
JP58-502699
  JP   7/25/1983   Inventorship not available
 
           
PCT/US98/021798
  WO   10/14/1998   Multi-element micro gyro Hsu, Ying Wen
 
           
FR0511218 (FR90917886.5)
  FR   3/12/1997
(6/28/1990)   Fabricating electronic circuitry unit containing stacked IC layers
having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
EP0116072 (EP83902618.4)
  EP   10/11/1989
(7/25/1983)   Multiplexer circuitry for high density analog signals
 
           
EP01979633.3
  EP   10/9/2001   High speed multi-stage stacked layer switch

John C. Carson; Volkan H. Orguz
 
           
EP02797722.2
  EP   3/4/2002   Retro-reflector warm stop for uncooled thermal imaging cameras
and method of using the same

Kaufman, Charles S.
 
           
EP0511218 (EP90917886.5)
  EP   3/12/1997
(6/28/1990)   Fabricating electronic circuitry unit containing stacked IC layers
having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
EP0570479 (EP92905662.0)
  EP   10/10/2001
(1/29/1992)   Hardware for electronic neural network

Carson, John C.
 
           
EP067087 (EP94909418.9)
  EP   (12/16/1993)   Fabricating stacks of IC chips by segmenting a larger
stack MINIHAN

JOSEPH A; PEPE ANGEL A
 
           
EP0683968 (EP94903352.6)
  EP   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
EP0695494 (EP94915397.7)
  EP   2/24/2001
(4/19/1994)   Electronic module comprising a stack of IC chips

Carson, John C.; Some, Raphael R.
 
           
EP0713609 (EP94925876.8)
  EP   5/7/2003
(8/12/1994)   Stack of IC chips as substitute for single IC chip

Ludwig, David E.; Saunders, Christ H.; Some, Raphael R.; Stuart, John J.

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
EP90906503.9
  EP   3/23/1990   Analog to digital conversion in Z-technology module

Wall, Llewellyn E.
 
           
EP92916059.6
  EP   6/24/1992   Fabricating electronic circuitry unit containing stacked IC
layers having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
EP93922760.9
  EP   9/27/1993   Fabrication of dense parallel solder bump connections

Pepe, Angel A.; Reinker, David M.; Minahan, Joseph A.
 
           
EP96902733.3
  EP   1/22/1996   Stackable modules and multimodular assemblies

Carson, John C.; DeCaro, Robert E.; Hsu, Ying; Miyake, Michael K.
 
           
EP98957755.6
  EP   11/10/1998   Method for thinning semiconductor wafers with circuits and
wafers made by the same

Albert, Douglas; Ogzuz Volkhan H
 
           
EP98964683.1
  EP   10/14/1998   Multi-element micro gyro

Hsu, Ying Wen
 
           
DE0683968 (DE94903352.6)
  DE   10/24/2002
(12/1/1993)   Module comprising IC memory stack dedicated to and structurally
combined with an IC microprocessor chip

Carson, John C.; Indin, Ronald J.; Shanken, Stuart N.
 
           
DE69030195 (DE69030195.2)
  DE   3/12/1997
(6/28/1990)   Fabricating electronic circuitry unit containing stacked IC layers
having lead rerouting

Go, Tiong C.(deceased,); Minahan, Joseph A.; Shanken, Stuart N.
 
           
FR0116072 (FR83902618.4)
  FR   7/25/1983   Multiplexer circuitry for high density analog signals

Inventorship not available
 
           
DE0116072 (DE83902618.4)
  DE   7/25/1983   Multiplexer circuitry for high density analog signals

Inventorship not available
 
           
GB0116072 (GB83902618.4)
  GB   7/25/1983   Multiplexer circuitry for high density analog signals

Inventorship not available

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
NL0116072 (NL83902618.4)
  NL   7/25/1983   Multiplexer circuitry for high density analog signals

Inventorship not available
 
           
SE0116072 (SE83902618.4)
  SE   7/25/1983   Multiplexer circuitry for high
density analog signals

Inventorship not available
 
           
EP0596075 (EP93911250.4)
  EP   8/22/2001 (5/5/1993)   Non-conductive end layer for integrated stack of
IC chips Miyake,

Michael K.
 
           
EP1097467 (EP99928570.2)
  EP   11/2/2006
(6/10/1993)   IC stack utilizing secondary leadframes

Eide, Floyd K.
 
           
10/339,023
  US   1/9/2003   Method for making stacked integrated circuits (ICs) using
prepackaged

parts Keith D. Gann
 
           
11/644,438
  US   12/22/2006   Method for making stacked integrated circuits (ICs) using
prepackaged parts

Keith D. Gann
 
           
09/949,203
  US   9/7/2001   Method of manufacturing multilayer modules

James Satsuo Yamaguchi; Angel Antonio Pepe; Volkan H. Ozguz; Andrew Nelson
Camien
 
           
EP1596433 (EP04394026.1)
  EP   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
TR1596433 (TR04394026.1)
  TR   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
IT1596433 (IT04394026.1)
  IT   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
IE1596433 (IE04394026.1)
  IE   1/2/2008
(5/12/2004)   A method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Stern, Jonathan Michael
 
           
EP05111589.7
  EP   12/1/2005   BGA-scale stacks comprised of layers containing integrated
circuit die and a method for making the same

Gann Keith; William E. Boyd
 
           
11/302,480
  US   12/12/2005   Neo-wafer device comprised of multiple singulated integrated
circuit die

Stern Jonathan
 
           
JP2098125
(JP63-501172)
  JP   10/20/1987   High-density electronic modules, process and product

Go, Tiong C.
 
           
DE6933329
  DE   12/16/1993   Method for fabricating stacks of IC chips by segmenting a
larger stack

Joseph A. Minahan
 
           
IT0676087
  IT   12/16/1993   Method for fabricating stacks of IC chips by segmenting a
larger stack

Joseph A. Minahan
 
           
NL0676087
  NL   12/16/1993   Method for fabricating stacks of IC chips by segmenting a
larger stack

Joseph A. Minahan
 
           
PCT/US99/023460
  WO   10/6/1999   Multi-element micro gyro

Ying W. Hsu

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
EP99951869.9
  EP   10/6/1999   Multi-element micro gyro

Ying W. Hsu
 
           
60/049,580
  US   6/13/1997   IC stack utilizing secondary leadframes

Floyd K. Eide
 
           
PCT/US99/013173
  WO   06/10/1999   IC stack utilizing secondary leadframes

Floyd K. Eide
 
           
DE69933873
  DE   6/10/1999   IC stack utilizing secondary leadframes

Floyd K. Eide
 
           
PCT/US02/006803
  WO   3/4/2002   Method and apparatus for temperature compensation of an
uncooled focal plane array

Randolph S. Carson
 
           
EP02721271.1
  EP   3/4/2002   Method and apparatus for temperature compensation of an
uncooled focal plane array

Randolph S. Carson
 
           
CY1596433
  CY   5/12/2004   Method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Jonathan Stern
 
           
EE1596433
  EE   5/12/2004   Method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Jonathan Stern
 
           
GR1596433
  GR   5/12/2004   Method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Jonathan Stern

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
HU1596433
  HU   5/12/2004   Method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Jonathan Stern
 
           
LU1596433
  LU   5/12/2004   Method for creating neo-wafers from singulated integrated
circuit die and a device made according to the method

Jonathan Stern
 
           
11/302,480
  US   12/12/2005   Neo-wafer device comprised of multiple singulated integrated
circuit die

Jonathan Stern
 
           
60/785,135
  US   3/24/2006   Method for image jitter reduction in a multiplayer LADAR
device

John Kennedy
 
           
60/300,449
  US   6/25/2001   Video event capture, storage and processing method and
apparatus

Randolph S. Carlson
 
           
PCT/US06/005754
  WO   2/14/2006   Stacked ball grid array package module utilizing one or more
interposer layers

William E. Boyd
 
           
PCT/US96/005065
  WO   4/11/1996   Dry adhesive joining of layers of electronic devices

Angel A. Pepe
 
           
PCT/US88/000060
  WO   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go
 
           
PCT/US00/041207
  WO   10/16/2006   Highly configurable capacitive transducer interface circuit

Christ Ying Hsu

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
PCT/US02/019452
  WO   6/18/2002   Mems sensor with single central anchor and motion-limiting
connection geometry

John William Reeds III
 
           
PCT/US02/020290
  WO   6/26/2002   Method of designing a flexure system for turning the modal
response of a decoupled micromachined gyroscope and a gyroscope designed
according to the method

Michael J. Tracy
 
           
PCT/US01/08720
  WO   3/19/2001   Method of canceling quadrature error in an angular rate
sensor

Ying Wen Hsu
 
           
06/187,787
  US   9/16/1980   Detector array module-structure and fabrication

John C. Carson
 
           
06/282,459
  US   7/13/1981   Detector array module-structure and fabrication

John C. Carson
 
           
60/159,832
  US   10/15/1999   Universal capacitive interface circuit

Christ Ying Hsu
 
           
06/721,040
  US   4/8/1985   Thermal imager incorporating electronics module having focal
plane sensor mosaic

John C. Carson
 
           
60/190,271
  US   3/17/2000   Method for canceling quadrature error in angular rate sensor

Ying Wen Hsu
 
           
EP0340241
  EP   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go

 

--------------------------------------------------------------------------------

 

                          Title of Patent and First Named Patent or Application
No.   Country   Filing Date   Inventor
DE3854814
  DE   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go
 
           
FR0340241
  FR   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go
 
           
GB0340241
  GB   1/4/1998   High density electronic package comprising stacked sub-modules

Tiong C. Go
 
           
EP00982671.0
  EP   10/16/2000   Highly configurable capacitive transducer interface circuit

Christ Ying Hsu
 
           
PCT/US87/002746
  WO   10/20/1987   High-density electronic modules, process and product

Tiong C. Go
 
           
EP0385979
  EP   10/20/1987   High-density electronic modules, process and product

Tiong C. Go
 
           
DE0385979
  DE   10/20/1987   High-density electronic modules, process and product

Tiong C. Go
 
           
FR0385979
  FR   10/20/1987   High-density electronic modules, process and product

Tiong C. Go
 
           
60/809,466
  US   5/30/2006   Large format thermoelectric infrared detector and a method of
fabrication

Ying Hsu
 
           
GB0385979
  GB   10/20/1987   High-density electronic modules, process and product

Tiong C. Go

 

--------------------------------------------------------------------------------

 

     Assignor assigns to Assignee all rights to the inventions, invention
disclosures, and discoveries in the assets listed above, together, with the
rights, if any, to revive prosecution of claims under such assets and to sue or
otherwise enforce any claims under such assets for past, present or future
infringement.
     Assignor hereby authorizes the respective patent office or governmental
agency in each jurisdiction to make available to Assignee all records regarding
the Certain Assets.
The terms and conditions of this Assignment of Rights in Certain Assets will
inure to the benefit of Assignee, its successors, assigns, and other legal
representatives and will be binding upon Assignor, its successors, assigns, and
other legal representatives.
     DATED this 16th day of March 2009.

          ASSIGNOR:

Irvine Sensors Corporation
      By:   /s/ John J. Stuart, Jr.         Name:   John J. Stuart, Jr.       
Title:   Sr. VP & Chief Financial Officer     

 

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Exhibit G revised
EXISTING LICENSES
License Agreement, dated *** between Irvine Sensors Corporation and ***.

  •   Exclusive license as to certain technology and know-how, but non-exclusive
as to the Improvements (defined as any patents issued or any applications filed
during the term of the Agreement.)     •   *** has the right to grant
sublicenses to third parties for the sole purpose of manufacturing certain
specified products.     •   License is non-assignable except that it may be
assigned, sublicensed or otherwise transferred to any division or other
Affiliate (defined as any entity that directly or indirectly controls (owning
directly or indirectly more than 50% of the voting stock or equity of the
entity), or is controlled by or is under common control with the party
concerned) with the consent of the other party, provided that the assigning
party remains liable for any and all obligations.

License Agreement, dated *** between Irvine Sensors Corporation and ***.

  •   Non-exclusive license, with the right to sublicense, subject to written
approval of Irvine Sensors, which approval may be withheld in the sole
discretion of Irvine Sensors.     •   License is assignable with prior written
consent of the other party.

Royalty Agreement, dated February 4, 2003 between Irvine Sensors Corporation and
Floyd Eide.
The Agreement provides for certain royalty payments to Floyd Eide for sales and
licenses of certain products relating to U.S. patent number 6,028,352.
Agreement, dated May 24, 2002 between Irvine Sensors Corporation and ***, as
amended by Amendment to Agreement, *** and the Second Amendment to Agreement,
***.

  •   Exclusive license under specified patents and related know-how solely to
make, use, sell and otherwise dispose of certain products in a specified Field
of Use (defined as applications within the *** industry, the fields of ***, and
any other applications agreed upon by the parties.     •   Sublicensable to
third parties.     •   License is assignable by licensee with prior written
consent of Irvine Sensors and ***, except that licensee may assign in connection
with the sale or other transfer of all of licensee’s assets.     •   *** has
granted sublicenses to ***. The sublicense to *** has been terminated.

License Agreement, dated March 7, 1997 between Irvine Sensors Corporation and
Novalog, Inc.

  •   An exclusive license under the patents, trade secrets and know-how found
in the Licensed Technology (defined as all patents and technical information of
Irvine Sensors) within the field of wireless infrared data communication for use
for any purpose. The license excludes the right to make, have made or sell
certain products that are to be delivered to and used by the U.S. Government
(except for those products that are substantially similar to those shipped to
commercial customers).     •   Sublicensable under trade secrets, know-how and
copyrights found in the Licensed Technology, but each party has an obligation to
offer third parties a license under its patents. The license must include
“reasonable terms and conditions” and be at least as permissive as the license
granted in this Agreement.     •   Non-transferable and non-assignable, unless
prior written consent of the other party.

 

*   Confidential treatment requested pursuant to Rule 24b-2 under the Securities
Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions
have been omitted from this exhibit and filed separately with the Securities and
Exchange Commission.

 

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Cross License Agreement dated ***, and amended on *** between Irvine Sensors
Corporation and ***.

  •   Non-exclusive license to the Licensed Patents to make, have made, use,
lease, sell and otherwise transfer Licensed Products (***) and to practice the
method or process involved in the manufacture or use thereof.     •  
Sublicensable to Subsidiaries and the right of such sublicensed Subsidiaries to
sublicense other Subsidiaries. If a Subsidiary ceases to be a Subsidiary and
holds any patents or patent application under the License, such licenses will
continue for the life of such patents or patent application; however, any
sublicense granted to a Subsidiary shall terminate on the date such Subsidiary
ceases to be Subsidiary. Subsidiaries are defined as (i) an entity with more
than 50% of outstanding shares or securities; or (ii) an entity which does not
have outstanding shares or securities, as may be the case in a partnership,
joint venture or unincorporated association, but has more than 50% of the
ownership interest representing the right to make the decisions for the entity,
now or hereafter, owned or controlled, directly or indirectly, by a party
hereto.     •   Sublicensable to Spinoff Entity which is defined as an entity,
other than a Subsidiary with (i) more than 20% ownership; (ii) more than 20%
ownership not owned or controlled by third party; and (iii) formed for special
purpose. All three conditions must exist for an entity to be considered a
Spinoff Entity.

*** License and Joint Development Agreement dated ***, and modified on ***
between Irvine Sensors Corporation and ***.

  •   Non-exclusive, non-transferable, non-assignable, worldwide, perpetual,
royalty bearing cross license to make, have made, use, have used, develop and
maintain ***, and the right to lease, sell import or otherwise transfer ***. The
cross license includes patents that read on the *** and those patents entitled
to an effective filing date prior to April 1, 1997.     •   Sublicensable to its
Subsidiaries (as defined under Cross License Agreement) within the scope of the
license, such sublicenses to its Subsidiaries terminates on the date the
sublicensed Subsidiary is no longer a Subsidiary.     •   Third party license —
if one party licensed their solely owned patent(s) to a third party, the other
party is required to negotiate a license to its solely owned and cross licensed
patent(s) to that third party. Seller represents and warrants that no such
transaction has yet occurred or been requested by either party.     •   This
agreement expired on December 31, 1999.

 

*   Confidential treatment requested pursuant to Rule 24b-2 under the Securities
Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions
have been omitted from this exhibit and filed separately with the Securities and
Exchange Commission.

 

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PATENT PURCHASE AGREEMENT
      This PATENT PURCHASE AGREEMENT (this “Agreement”) is entered into, as of
the Effective Date (defined below), by and between Irvine Sensors Corporation, a
Delaware corporation, with an office at 3001 Redhill Ave., Bldg. 4, Suite 108,
Costa Mesa, CA 92672 (“Seller”) and Aprolase Development Co., LLC, a Delaware
limited liability company, with an address at 2711 Centerville Road, Suite 400,
Wilmington, DE 19808 (“Purchaser”). The parties hereby agree as follows:
1. Background
1.1 Seller owns certain provisional patent applications, patent applications,
patents, and/or related foreign patents and applications.
1.2 Seller wishes to sell to Purchaser all right, title, and interest in such
patents and applications and the causes of action to sue for infringement
thereof and other enforcement rights.
1.3 Purchaser wishes to purchase from Seller all right, title, and interest in
the Assigned Patent Rights (defined below), free and clear of any restrictions,
liens, claims, and encumbrances.
2. Definitions
“Abandoned Assets” means those specific provisional patent applications, patent
applications, patents and other governmental grants or issuances listed on
Exhibit C (as such list may be updated based on Purchaser’s review pursuant to
paragraph 3.1).
“Assigned Patent Rights” means the Patents and the additional rights set forth
in paragraph 4.2.
“Assignment Agreements” means the agreements assigning ownership of the Assigned
Patent Rights and the Abandoned Assets from the inventors and/or prior owners to
Seller.
“Common Interest Agreement” means an agreement, in the form set forth on
Exhibit E, setting forth the terms under which Seller and Purchaser will protect
certain information relating to the Patents under the common interest privilege.
“Docket” means Seller’s or its agents’ list or other means of tracking
information relating to the prosecution or maintenance of the Patents throughout
the world, including, without limitation, the names, addresses, email addresses,
and phone numbers of prosecution counsel and agents, and information relating to
deadlines, payments, and filings, which list or other means of tracking
information is current as of the Effective Date.
“Effective Date” means the date set forth as the Effective Date on the signature
page of this Agreement.
“Executed Assignments” means both the executed and notarized Assignment of
Patent Rights in Exhibit B, the executed Assignment of Rights in Certain Assets
in Exhibit C, each as signed by a duly authorized representative of Seller, and
the additional documents Seller may be required to execute and deliver under
paragraph 5.3.
“Live Assets” means the provisional patent applications, patent applications,
and patents listed on Exhibits A and/or B (as such lists may be updated based on
Purchaser’s review pursuant to paragraph 3.1).
“Patents” means, excluding the Abandoned Assets, all (a) Live Assets;
(b) patents or patent applications (i) to which any of the Live Assets directly
or indirectly claims priority, (ii) for which any of the Live Assets directly or
indirectly forms a basis for priority, and/or (iii) that were co-owned
applications that incorporate by reference, or are incorporated by reference
into, the Live Assets; (c) reissues, reexaminations, extensions, continuations,
continuations in part, continuing prosecution applications, requests for

 

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continuing examinations, divisions, and registrations of any item in any of the
foregoing categories (a) and (b); (d) foreign patents, patent applications and
counterparts relating to any item in any of the foregoing categories (a) through
(c), including, without limitation, certificates of invention, utility models,
industrial design protection, design patent protection, and other governmental
grants or issuances; and (e) any items in any of the foregoing categories
(b) through (d) whether or not expressly listed as Live Assets and whether or
not claims in any of the foregoing have been rejected, withdrawn, cancelled, or
the like.
“Primary Warranties” means, collectively, the representations and warranties of
Seller set forth in paragraphs 6.1, 6.2, 6.3, 6.4, and 6.5 hereof.
“Prosecution History Files” means all files, documents and tangible things, as
those terms have been interpreted pursuant to rules and laws governing the
production of documents and things, constituting, comprising or relating to the
investigation, evaluation, preparation, prosecution, maintenance, defense,
filing, issuance, registration, assertion or enforcement of the Patents.
“Transmitted Copy” has the meaning set forth in paragraph 8.12.
3. Transmittal, Review, Closing Conditions and Payment
3.1 Transmittal. Within twenty (20) calendar days following the later of the
Effective Date or the date Purchaser receives a Transmitted Copy of this
Agreement executed by Seller, Seller will send to Purchaser, or its legal
counsel, the items identified on Exhibit D (the “Initial Deliverables”);
provided, however, the Common Interest Agreement will not be required to be
executed on behalf of the Seller if there are no pending patent applications
included in the Patents. Seller acknowledges and agrees that Purchaser may
request, and Seller will promptly deliver to Purchaser or its legal counsel, as
reasonably directed by Purchaser, additional documents in Purchaser’s care,
custody or control, or to which Seller otherwise has access, based on
Purchaser’s review of the Initial Deliverables (such additional documents and
the Initial Deliverables are, collectively, the “Deliverables”), and that as a
result of Purchaser’s review, the lists of Live Assets on Exhibits A and B and
the list of Abandoned Assets on Exhibit C, may be revised by Purchaser, with
mutual agreement of Seller (evidenced by one or more Executed Assignments), both
before and after the Closing to conform these lists to the definition of Patents
(and these revisions may therefore require the inclusion of additional
provisional patent applications, patent applications, and patents on Exhibit A
and B or Exhibit C). To the extent any of the Live Assets are removed for any
reason, the payment in paragraph 3.4 may be reduced by mutual agreement of the
parties. If originals of the Deliverables are not available and delivered to
Purchaser prior to Closing, Seller will cause (i) such originals of the
Deliverables to be sent to Purchaser or Purchaser’s representative promptly if
and after such originals are located and (ii) Seller will deliver to Purchaser a
declaration, executed under penalty of perjury, detailing Seller’s efforts to
locate such unavailable original documents and details regarding how delivered
copies were obtained.
3.2 Closing. The closing of the sale of the Assigned Patent Rights and the
assignment of the Abandoned Assets hereunder will occur when all conditions set
forth in paragraph 3.3 have been satisfied or waived and the payment set forth
in paragraph 3.4(a) is made (the “Closing”). Purchaser and Seller will use
reasonable efforts to carry out the Closing within thirty (30) calendar days
following the later of the Effective Date or the date on which the last of the
Deliverables was received by Purchaser.
3.3 Closing Conditions. The following are conditions precedent to Purchaser’s
obligation to make the payment in paragraph 3.4(a).
(a) Signature by Seller. Seller timely executed this Agreement and delivered a
Transmitted Copy of this Agreement to Purchaser’s representatives by not later
than December 18, 2008 at 5:00 p.m., Pacific time and promptly delivered two
(2) executed originals of this Agreement to Purchaser’s representatives.
(b) Transmittal of Documents. Seller delivered to Purchaser all the
Deliverables.

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(c) Compliance With Agreement. Seller performed and complied in all respects
with all of the obligations under this Agreement that are to be performed or
complied with by it on or prior to the Closing.
(d) Representations and Warranties True. Except for the representations and
warranties in paragraph 6.3, which must be true and correct as of Closing,
Purchaser is satisfied that, as of the Effective Date and as of the Closing, the
representations and warranties of Seller contained in Section 6 are true and
correct.
(e) Patents Not Abandoned. Purchaser is satisfied that, as of the Effective Date
and as of the Closing, none of the assets that are included in the Patents have
expired, lapsed, been abandoned, or deemed withdrawn.
(f) Delivery of Executed Assignments. Seller caused the Executed Assignments to
be delivered to Purchaser’s representatives.
(g) Existing Licenses. Purchaser is satisfied that, as of the Closing, the
representations and warranties of Seller in paragraph 6.3 are true and correct,
and that each of the licenses listed on Exhibit G has been terminated, or
amended such that each of them is non-exclusive, non-sublicensable and
nontransferable.
(h) Royalty Agreement. Seller (i) entered into an agreement with Floyd Eide, in
a form acceptable to Purchaser, confirming that Mr. Eide and his heirs and
assigns, including, without limitation, The Eide Family Trust Dated August 9,
1990, do not have any rights or claims to the Purchase Price or to any other
amounts from Purchaser or any third party as a result of the Royalty Agreement
between Seller and Floyd Eide, dated effective as of February 4, 2003, and
(ii) delivered to Purchaser an executed copy of that agreement.
(i) Existing License Agreements. For each license listed on Exhibit G that is
exclusive, sublicenseable, and/or transferable, Seller (i) entered into an
agreement with the relevant licensee, in a form acceptable to Purchaser, to
either terminate each such license or amend each such license so that it is
non-exclusive, nonsublicensable and nontransferable, and (ii) delivered to
Purchaser an executed copy of each such agreement.
(k) Delivery of License Agreements. Seller has provided to Purchaser or its
legal counsel true and correct copies of the sublicenses granted to *** and ***
under the Agreement, dated ***, between Seller and ***, as amended by Amendment
to Agreement, dated ***, and Second Amendment to Agreement, dated ***, and
Purchaser is satisfied that such sublicensees have no further right to
sublicense and Purchaser is satisfied, in its sole and absolute discretion, that
such sublicenses do not decrease the value of the Assigned Patent Rights.
3.4 Payment.
[Deleted in its entirety and replaced with language of Amendment dated March 18,
2009 by and between Purchaser and Seller]
3.5 Termination and Survival. In the event all conditions to Closing set forth
in paragraph 3.3 are not met within ninety (90) days following the Effective
Date, either party will have the right to terminate this Agreement by written
notice to the other party; provided, however, that Seller shall only have the
right to terminate this Agreement if Seller has complied, in all material
respects, with all of its obligations under this Agreement prior to such
termination. Upon termination, Purchaser will return all documents delivered to
Purchaser under this Section 3 to Seller. The provisions of Section 8 will
survive any termination.
 

***   Confidential treatment requested pursuant to Rule 24b-2 under the
Securities Exchange Act of 1934. In accordance with Rule 24b-2, these
confidential portions have been omitted from this exhibit and filed separately
with the Securities and Exchange Commission.

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4. Transfer of Patents and Additional Rights
4.1 Assignment of Patents. Upon the Closing, Seller hereby sells, assigns,
transfers, and conveys to Purchaser all right, title, and interest in and to the
Assigned Patent Rights. Seller understands and acknowledges that, if any of the
Patents are assigned to Seller’s affiliates or subsidiaries, Seller may be
required prior to the Closing to perform certain actions to establish that
Seller is the assignee and to record such assignments. On or before Closing,
Seller will execute and deliver to Purchaser the Assignment of Patent Rights in
the form set forth in Exhibit B (as may be updated based on Purchaser’s review
pursuant to paragraph 3.1).
4.2 Assignment of Additional Rights. Upon the Closing, Seller hereby also sells,
assigns, transfers, and conveys to Purchaser all right, title and interest in
and to all
(a) inventions, invention disclosures, and discoveries described in any of the
Patents or Abandoned Assets that (i) are included in any claim in the Patents or
Abandoned Assets, (ii) are subject matter capable of being reduced to a patent
claim in a reissue or reexamination proceedings brought on any of the Patents or
Abandoned Assets, and/or (iii) could have been included as a claim in any of the
Patents or Abandoned Assets;
(b) rights to apply in any or all countries of the world for patents,
certificates of invention, utility models, industrial design protections, design
patent protections, or other governmental grants or issuances of any type
related to any of the Patents and the inventions, invention disclosures, and
discoveries therein;
(c) causes of action (whether known or unknown or whether currently pending,
filed, or otherwise) and other enforcement rights under, or on account of, any
of the Patents and/or the rights described in subparagraph 4.2(b), including,
without limitation, all causes of action and other enforcement rights for
(i) damages, (ii) injunctive relief, and (iii) any other remedies of any kind
for past, current and future infringement; and
(d) rights to collect royalties or other payments under or on account of any of
the Patents and/or any of the foregoing.
4.3 Assignment of Rights in Certain Assets. Upon the Closing, Seller hereby
sells, assigns, transfers, and conveys to Purchaser all of Seller’s right,
title, and interest in and to the Abandoned Assets. On or before Closing, Seller
will execute and deliver to Purchaser the Assignment of Certain Rights in the
form set forth in Exhibit C (as may be updated based on Purchaser’s review
pursuant to paragraph 3.1).
4.4 License Back to Seller under Patents. Upon the Closing, Purchaser will grant
a license to the Patents to Seller pursuant to a separate agreement between the
parties (“Seller License”).
5. Additional Obligations
5.1 Further Cooperation.
(a) At the reasonable request of Purchaser, Seller will execute and deliver such
other instruments and do and perform such other acts and things as may be
necessary or desirable for effecting completely the consummation of the
transactions contemplated hereby, including, without limitation, execution,
acknowledgment, and recordation of other such papers, and using commercially
reasonable efforts to obtain the same from the respective inventors, as
necessary or desirable for fully perfecting and conveying unto Purchaser the
benefit of the transactions contemplated hereby.
(b) To the extent any attorney-client privilege or the attorney work-product
doctrine applies to any portion of the Prosecution History Files and that is
retained after Closing under Seller or Seller’s representatives normal document
retention policy, Seller will ensure that, if any such

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portion of the Prosecution History File remains under Seller’s possession or
control after Closing, it is not disclosed to any third party unless
(a) disclosure is ordered by a court of competent jurisdiction, after all
appropriate appeals to prevent disclosure have been exhausted, and (b) Seller
gave Purchaser prompt notice upon learning that any third party sought or
intended to seek a court order requiring the disclosure of any such portion of
the Prosecution History File. In addition, Seller will continue to prosecute,
maintain, and defend the Patents at its sole expense until the Closing.
(c) Seller will also, at the reasonable request of Purchaser after Closing,
assist Purchaser in providing, and obtaining, from the respective inventors,
prompt production of pertinent facts and documents, otherwise giving of
testimony, execution of petitions, oaths, powers of attorney, specifications,
declarations or other papers and other assistance reasonably necessary for
filing patent applications, enforcement or other actions and proceedings with
respect to the claims under the Patents. Purchaser shall compensate Seller for
any reasonable, documented disbursements and time incurred after Closing in
connection with providing assistance under this subparagraph 5.1(c) in
connection with any enforcement or other infringement action regarding the
Patents, under a standard billable hour rate of Seller; provided that Seller
shall have furnished Purchaser an advance, written estimate of the fees and
costs for such assistance and Purchaser shall have agreed in writing to pay such
fees and costs.
5.2 Payment of Fees. Seller will pay any maintenance fees, annuities, and the
like due or payable on the Patents until the Closing. For the avoidance of
doubt, Seller shall pay any maintenance fees for which the fee is payable (e.g.,
the fee payment window opens) on or prior to the Closing even if the surcharge
date or final deadline for payment of such fee would be after the Closing.
Seller hereby gives Purchaser power-of-attorney to (a) execute documents in the
name of Seller in order to effectuate the recordation of the transfers of any
portion of the Patents in an governmental filing office in the world and
(b) instruct legal counsel to take steps to pay maintenance fees and annuities
that Seller declines to pay and to make filings on behalf of Seller prior to
Closing and otherwise preserve the assets through Closing.
5.3 Foreign Assignments. To the extent the Patents include non-United States
patents and patent applications, Seller will deliver to Purchaser’s
representatives executed documents in a form as may be required in the non-U.S
jurisdiction in order to perfect the assignment to Purchaser of the non-U.S.
patents and patent applications.
5.4 Pre-existing Royalty Agreement. Purchaser shall not be liable for any
obligations under the pre-existing Royalty Agreement between Irvine Sensors
Corporation and Floyd Eide with the effective date of February 4, 2003.
6. Representations and Warranties of Seller
Seller hereby represents and warrants to Purchaser as follows that, as of the
Effective Date and as of the Closing:
6.1 Authority. Seller is a company duly formed, validly existing, and in good
standing under the laws of the jurisdiction of its formation. Seller has the
full power and authority and has obtained all third party consents, approvals,
and/or other authorizations required to enter into this Agreement and to carry
out its obligations hereunder, including, without limitation, the assignment of
the Assigned Patent Rights to Purchaser.
6.2 Title and Contest. Seller owns all right, title, and interest to the
Assigned Patent Rights, including, without limitation, all right, title, and
interest to sue for infringement of the Patents. Seller has obtained and
properly recorded previously executed assignments for the Patents as necessary
to fully perfect its rights and title therein in accordance with governing law
and regulations in each respective jurisdiction. As of Closing, the Assigned
Patent Rights are free and clear of all liens, claims, mortgages, security

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interests or other encumbrances, and restrictions. There are no actions, suits,
investigations, claims, or proceedings threatened, pending, or in progress
relating in any way to the Assigned Patent Rights. There are no existing
contracts, agreements, options, commitments, proposals, bids, offers, or rights
with, to, or in any person to acquire any of the Assigned Patent Rights.
6.3 Existing Licenses and Obligations. There is no obligation imposed by a
standards-setting organization to license any of the Patents on particular terms
or conditions. Except for the Seller License and the non-exclusive licenses
listed on Exhibit G, no licenses under the Patents have been granted or retained
by Seller, any prior owners, or inventors. After Closing, except for the Seller
License, none of Seller, any prior owner, or any inventor will retain any rights
or interest in the Assigned Patent Rights. None of the licenses or rights in the
Patents listed on Exhibit G is an exclusive grant or right and, except as
expressly noted on Exhibit G, each such license is nontransferable and
nonsublicensable. Except as set forth on Exhibit G, none of the licenses listed
on Exhibit G have been assigned or sublicensed and no further licenses have been
granted by any sublicensees.
6.4 Restrictions on Rights. Purchaser will not be subject to any covenant not to
sue or similar restrictions on its enforcement or enjoyment of the Assigned
Patent Rights or the Abandoned Assets as a result of any prior transaction
related to the Assigned Patent Rights or the Abandoned Assets.
6.5 Validity and Enforceability. None of the Patents or the Abandoned Assets
(other than Abandoned Assets for which abandonment resulted solely from unpaid
fees and/or annuities) have ever been found invalid, unpatentable, or
unenforceable for any reason in any administrative, arbitration, judicial or
other proceeding, and Seller does not know of and has not received any notice or
information of any kind from any source suggesting that the Patents may be
invalid, unpatentable, or unenforceable. If any of the Patents are terminally
disclaimed to another patent or patent application, all patents and patent
applications subject to such terminal disclaimer are included in this
transaction. To the extent “small entity” fees were paid to the United States
Patent and Trademark Office for any Patent, such reduced fees were then
appropriate because the payor qualified to pay “small entity” fees at the time
of such payment and specifically had not licensed rights in the any Patent to an
entity that was not a “small entity.”
6.6 Conduct. None of Seller, any prior owner or their respective agents or
representatives have engaged in any conduct, or omitted to perform any necessary
act, the result of which would invalidate any of the Patents or hinder their
enforcement, including, without limitation, misrepresenting the Patents to a
standard-setting organization.
6.7 Enforcement. Seller has not put a third party on notice of actual or
potential infringement of any of the Patents or the Abandoned Assets. Seller has
not invited any third party to enter into a license under any of the Patents or
the Abandoned Assets. Seller has not initiated any enforcement action with
respect to any of the Patents or the Abandoned Assets.
6.8 Patent Office Proceedings. None of the Patents or the Abandoned Assets have
been or are currently involved in any reexamination, reissue, interference
proceeding, or any similar proceeding, and no such proceedings are pending or
threatened.
6.9 Fees. All maintenance fees, annuities, and the like due or payable on the
Patents have been timely paid. For the avoidance of doubt, such timely payment
includes payment of any maintenance fees for which the fee is payable (e.g., the
fee payment window opens) even if the surcharge date or final deadline for
payment of such fee would be in the future.
6.10 Abandoned Assets. According to each applicable patent office, each of the
Abandoned Assets has expired, lapsed, or been abandoned or deemed withdrawn.

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7. Representations and Warranties of Purchaser
Purchaser hereby represents and warrants to Seller as follows that, as of the
Effective Date and as of the Closing:
7.1 Purchaser is a limited liability company duly formed, validly existing, and
in good standing under the laws of the jurisdiction of its formation.
7.2 Purchaser has all requisite power and authority to (i) enter into, execute,
and deliver this Agreement and (ii) perform fully its obligations hereunder.
8. Miscellaneous
8.1 Limitation of Liability. EXCEPT IN THE EVENT OF BREACH OF ANY OF THE PRIMARY
WARRANTIES BY SELLER OR SELLER’S INTENTIONAL MISREPRESENTATION, SELLER’S TOTAL
LIABILITY UNDER THIS AGREEMENT WILL NOT EXCEED THE PURCHASE PRICE SET FORTH IN
PARAGRAPH 3.4 OF THIS AGREEMENT. PURCHASER’S TOTAL LIABILITY UNDER THIS
AGREEMENT WILL NOT EXCEED THE PURCHASE PRICE SET FORTH IN PARAGRAPH 3.4 OF THIS
AGREEMENT. THE PARTIES ACKNOWLEDGE THAT THE LIMITATIONS ON POTENTIAL LIABILITIES
SET FORTH IN THIS PARAGRAPH 8.1 WERE AN ESSENTIAL ELEMENT IN SETTING
CONSIDERATION UNDER THIS AGREEMENT.
8.2 Limitation on Consequential Damages. EXCEPT IN THE EVENT OF SELLER’S
INTENTIONAL MISREPRESENTATION, NEITHER PARTY WILL HAVE ANY OBLIGATION OR
LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT (INCLUDING NEGLIGENCE)) OR
OTHERWISE, AND NOTWITHSTANDING ANY FAULT, NEGLIGENCE (WHETHER ACTIVE, PASSIVE OR
IMPUTED), REPRESENTATION, STRICT LIABILITY OR PRODUCT LIABILITY, FOR COVER OR
FOR ANY INCIDENTAL, INDIRECT OR CONSEQUENTIAL, MULTIPLIED, PUNITIVE, SPECIAL, OR
EXEMPLARY DAMAGES OR LOSS OF REVENUE, PROFIT, SAVINGS OR BUSINESS ARISING FROM
OR OTHERWISE RELATED TO THIS AGREEMENT, EVEN IF A PARTY OR ITS REPRESENTATIVES
HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE PARTIES ACKNOWLEDGE
THAT THESE EXCLUSIONS OF POTENTIAL DAMAGES WERE AN ESSENTIAL ELEMENT IN SETTING
CONSIDERATION UNDER THIS AGREEMENT.
8.3 Compliance With Laws. Notwithstanding anything contained in this Agreement
to the contrary, the obligations of the parties with respect to the consummation
of the transactions contemplated by this Agreement shall be subject to all laws,
present and future, of any government having jurisdiction over the parties and
this transaction, and to orders, regulations, directions or requests of any such
government.
8.4 Confidentiality of Terms. The parties hereto will keep the terms and
existence of this Agreement and the identities of the parties hereto and their
affiliates confidential and will not now or hereafter divulge any of this
information to any third party except (a) with the prior written consent of the
other party; (b) as otherwise may be required by law or legal process; (c)
during the course of litigation, so long as the disclosure of such terms and
conditions is restricted in the same manner as is the confidential information
of other litigating parties; (d) in confidence to its legal counsel,
accountants, banks, and financing sources and their advisors solely in
connection with complying with or administering its obligations with respect to
this Agreement; (e) by Purchaser, to potential purchasers or licensees of the
Assigned Patent Rights or the Abandoned Assets; (f) in order to perfect
Purchaser’s interest in the Assigned Patent Rights or the Abandoned Assets with
any governmental patent office (including, without limitation, recording the
Executed Assignments in any governmental patent office); (g) to enforce
Purchaser’s right, title, and interest in and to the Assigned Patent Rights or
the Abandoned Assets; or (h) as set forth in paragraph 8.13 below; provided
that, in (b) and (c) above, (i) to the extent permitted by law, the disclosing
party will use all legitimate and legal means available to minimize the
disclosure to third parties, including, without limitation, seeking a
confidential treatment request or protective order whenever appropriate or
available; and (ii) the disclosing party will provide the other party with at
least ten (10) days’ prior written notice of such disclosure. Without limiting
the foregoing, Seller will cause its agents involved in this transaction to

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abide by the terms of this paragraph, including, without limitation, ensuring
that such agents do not disclose or otherwise publicize the existence of this
transaction with actual or potential clients in marketing materials, or industry
conferences.
8.5 Governing Law; Venue/Jurisdiction. This Agreement will be interpreted,
construed, and enforced in all respects in accordance with the laws of the State
of Delaware, without reference to its choice of law principles to the contrary.
Seller will not commence or prosecute any action, suit, proceeding or claim
arising under or by reason of this Agreement other than in the state or federal
courts located in Delaware. Seller irrevocably consents to the jurisdiction and
venue of the courts identified in the preceding sentence in connection with any
action, suit, proceeding, or claim arising under or by reason of this Agreement.
8.6 Notices. All notices given hereunder will be given in writing (in English or
with an English translation), will refer to Purchaser and to this Agreement and
will be delivered to the address set forth below by (i) personal delivery or
(ii) delivery postage prepaid by an internationally-recognized express courier
service:

     
If to Purchaser
  If to Seller
Aprolase Development Co., LLC
2711 Centerville Road, Suite 400Wilmington,
DE 19808
  Irvine Sensors Corporation
3001 Redhill Ave.
Bldg. 4, Suite 108
Costa Mesa, CA 92672
 
   
Attn: Managing Director
  Attn: Eric Boyd

Notices are deemed given on (a) the date of receipt if delivered personally or
by express courier or (b) if delivery is refused, the date of refusal. Notice
given in any other manner will be deemed to have been given only if and when
received at the address of the person to be notified. Either party may from time
to time change its address for notices under this Agreement by giving the other
party written notice of such change in accordance with this paragraph.
8.7 Relationship of Parties. The parties hereto are independent contractors.
Nothing in this Agreement will be construed to create a partnership, joint
venture, franchise, fiduciary, employment or agency relationship between the
parties. Neither party has any express or implied authority to assume or create
any obligations on behalf of the other or to bind the other to any contract,
agreement or undertaking with any third party.
8.8 Equitable Relief. Seller acknowledges and agrees that damages alone would be
insufficient to compensate Purchaser for a breach by Seller of this Agreement
and that irreparable harm would result from a breach of this Agreement. Seller
hereby consents to the entering of an order for injunctive relief to prevent a
breach or further breach, and the entering of an order for specific performance
to compel performance of any obligations under this Agreement.
8.9 Severability. If any provision of this Agreement is found to be invalid or
unenforceable, then the remainder of this Agreement will have full force and
effect, and the invalid provision will be modified, or partially enforced, to
the maximum extent permitted to effectuate the original objective.
8.10 Waiver. Failure by either party to enforce any term of this Agreement will
not be deemed a waiver of future enforcement of that or any other term in this
Agreement or any other agreement that may be in place between the parties.
8.11 Miscellaneous. This Agreement, including its exhibits, constitutes the
entire agreement between the parties with respect to the subject matter hereof
and merges and supersedes all prior and contemporaneous agreements,
understandings, negotiations, and discussions. Neither of the parties will be
bound by any conditions, definitions, warranties, understandings, or
representations with respect to the subject matter hereof other than as
expressly provided herein. The section headings contained in this Agreement are
for reference purposes only and will not affect in any way the meaning or
interpretation of

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this Agreement. This Agreement is not intended to confer any right or benefit on
any third party (including, but not limited to, any employee or beneficiary of
any party), and no action may be commenced or prosecuted against a party by any
third party claiming as a third-party beneficiary of this Agreement or any of
the transactions contemplated by this Agreement. No oral explanation or oral
information by either party hereto will alter the meaning or interpretation of
this Agreement. No amendments or modifications will be effective unless in a
writing signed by authorized representatives of both parties. The terms and
conditions of this Agreement will prevail notwithstanding any different,
conflicting or additional terms and conditions that may appear on any letter,
email or other communication or other writing not expressly incorporated into
this Agreement. The following exhibits are attached hereto and incorporated
herein: Exhibit A (entitled “Patents to be Assigned”); Exhibit B (entitled
“Assignment of Patent Rights”); Exhibit C (entitled “Assignment of Rights in
Certain Assets”); Exhibit D (entitled “List of Initial Deliverables”); Exhibit E
(entitled “Common Interest Agreement”); Exhibit F (entitled “Form of Press
Release”); and Exhibit G (entitled “Existing Licenses”).
8.12 Counterparts; Electronic Signature; Delivery Mechanics. This Agreement may
be executed in counterparts, each of which will be deemed an original, and all
of which together constitute one and the same instrument. Each party will
execute and promptly deliver to the other parties a copy of this Agreement
bearing the original signature. Prior to such delivery, in order to expedite the
process of entering into this Agreement, the parties acknowledge that a
Transmitted Copy of this Agreement will be deemed an original document.
“Transmitted Copy” means a copy bearing a signature of a party that is
reproduced or transmitted via email of a .pdf file, photocopy, facsimile, or
other process of complete and accurate reproduction and transmission.
8.13 Publicity and SEC Reporting. Seller may make one public announcement
contemporaneously with signing and with the Closing, which announcements will be
substantially of the form set forth in Exhibit F. Seller shall submit any such
proposed announcement to Purchaser at least five (5) business days prior to its
making such an announcement for Purchaser’s review and approval, which approval
shall not be unreasonably withheld by Purchaser so long as such proposed
announcement substantially conforms to Exhibit F. After the Effective Date,
Seller shall have the right to file the statement set forth on Exhibit F with
Seller’s 8K filing with the Securities Exchange Commission (“SEC”). Seller and
Purchaser agree that Seller shall not file this Agreement with the SEC unless
the SEC informs Seller in writing that Seller is required by law to file this
Agreement with the SEC. If Seller receives such notice from the SEC, then Seller
will include only those portions of this Agreement that are required to be filed
with the SEC pursuant to applicable laws and regulations.
      In witness whereof, intending to be legally bound, the parties have
executed this Patent Purchase Agreement as of the Effective Date.

                      SELLER:       PURCHASER:    
 
                    IRVINE SENSORS CORPORATION       APROLASE DEVELOPMENT CO.,
LLC    
 
                   
By:
  /s/ John C. Carson       By:   /s/ Melissa Coleman    
 
                   
 
  Name: John C. Carson           Name: Melissa Coleman    
 
  Title:   President and CEO           Title:   Authorized Person    

Effective Date: December 11, 2008

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Exhibit A
[Deleted in its entirety and replaced with language of Amendment dated March 18,
2009 by and between Purchaser and Seller]

 

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Exhibit B
[Deleted in its entirety and replaced with language of Amendment dated March 18,
2009 by and between Purchaser and Seller]

 

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Exhibit C
[Deleted in its entirety and replaced with language of Amendment dated March 18,
2009 by and between Purchaser and Seller]

 

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Exhibit D
LIST OF INITIAL DELIVERABLES
Seller will cause the following to be delivered to Purchaser, or Purchaser’s
representative, within the time provided in paragraph 3.1 of the attached Patent
Purchase Agreement:

     (a) U.S. Patents. For each item of the Patents that is an issued United
States patent, and for each Abandoned Asset that forms the basis for priority
for such issued U.S. patent (whether a patent or similar protection has been
issued or granted),
(i) the original
(A) ribbon copy issued by the United States Patent and Trademark Office,
(B) Assignment Agreement(s),
(C) conception and reduction to practice materials, and
(ii) a copy of
(A) the Docket, and
(B) each relevant license and security agreement.
     (b) Non-U.S. For each Live Asset for which a non-United States patent or
similar protection has been issued or granted,
(i) the original ribbon copy or certificate issued by the applicable government,
if available
(ii) copy of each pending foreign application
(iii) the Docket,
(iv) the original Assignment Agreement(s),
(v) a copy of applicant name change, if necessary, and
(vi) a copy of each relevant license and security agreement.
     (c) Patent Applications. For each item of the Patents that is a patent
application,
(i) a copy of the patent application, as filed,
(ii) if unpublished, a copy of the filing receipt and the non-publication
request, if available,
(iii) the original Assignment Agreement(s),
(iv) the Docket,
(v) all available conception and reduction to practice materials,
(vi) evidence of foreign filing license (or denial thereof),
(vii) a copy of each relevant license and security agreement, and
(viii) the Prosecution History Files.
     (d) Common Interest Agreement. Seller will deliver any Initial Deliverables
to be delivered by Seller under paragraph (c) above to Purchaser’s legal
counsel, together with two (2) executed originals of the Common Interest
Agreement.
     (e) Thorough Search/Declaration. If originals of the Initial Deliverables
are not available and delivered to Purchaser prior to Closing, Seller will cause
(i) such originals of the Initial Deliverables to be sent to Purchaser or
Purchaser’s representative promptly if and after such originals are located and
(ii) an appropriate executive officer of Seller to deliver to Purchaser an
declaration, executed by such officer under penalty of perjury, detailing
Seller’s efforts to locate such unavailable original documents and details
regarding how delivered copies were obtained.
Capitalized terms used in this Exhibit D are defined in the Patent Purchase
Agreement to which this Exhibit D is attached.

 

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Exhibit E
COMMON INTEREST AGREEMENT
     THIS COMMON INTEREST AGREEMENT (“Agreement”) is entered into between the
undersigned legal counsel (“Counsel”), for themselves and on behalf of the
parties they represent (as indicated below).
1. Background.
1.1 Aprolase Development Co., LLC, a Delaware limited liability company
(“Purchaser”) and Irvine Sensors Corporation, a Delaware Corporation (“Seller”)
(Purchaser and Seller are sometimes hereafter referred to herein as a “party” or
the “parties”), have entered into an agreement under which Purchaser will
acquire all substantial rights of Seller in certain patent applications filed or
to be filed throughout the world (the “Patent Matters”).
1.2 The parties have a common interest in the Patent Matters and have agreed to
treat their communications and those of their Counsel relating to the Patent
Matters as protected by the common interest privilege. Furtherance of the Patent
Matters requires the exchange of proprietary documents and information, the
joint development of legal strategies and the exchange of attorney work product
developed by the parties and their respective Counsel.
2. Common Interest.
2.1 The parties have a common, joint and mutual legal interest in cooperating
with each other, to the extent permitted by law, to share information protected
by the attorney-client privilege and by the work product doctrine with respect
to the Patent Matters. Any counsel or consultant retained by a party or their
Counsel to assist in the Patent Matters shall be bound by, and entitled to the
benefits of, this Agreement.
2.2 In order to further their common interest, the parties and their Counsel
shall exchange privileged and work product information, orally and in writing,
including, without limitation, factual analyses, mental impressions, legal
memoranda, source materials, draft legal documents, prosecution history files
and other information (hereinafter “Common Interest Materials”). The sole
purpose for the exchange of the Common Interest Materials is to support the
parties’ common interest with respect to the prosecution and enforcement of the
Patent Matters. Any Common Interest Materials exchanged shall continue to be
protected under all applicable privileges and no such exchange shall constitute
a waiver of any applicable privilege or protection.
3. Nondisclosure.
3.1 The parties and their Counsel shall use the Common Interest Materials solely
in connection with the Patent Matters and shall take appropriate steps to
protect the privileged and confidential nature of the Common Interest Materials.
Neither client nor their respective Counsel shall produce privileged documents
or information unless or until directed to do so by a final order of a court of
competent jurisdiction, or upon the prior written consent of the other party. No
privilege or objection shall be waived by a party hereunder without the prior
written consent of the other party. The obligations under this paragraph will
not apply either to Purchaser after closing of the acquisition of the Patent
Matters or to Seller with respect to any dispute with Purchaser related to such
potential acquisition.
3.2 Except as herein provided, in the event that either party or their Counsel
is requested or required in the context of a litigation, governmental, judicial
or regulatory investigation or other similar proceedings (by oral questions,
interrogatories, requests for information or documents, subpoenas, civil
investigative demands or similar process) to disclose any Common Interest
Materials, the party or their Counsel shall immediately inform the other party
and their Counsel and shall assert all applicable privileges, including, without
limitation, the common interest doctrine, the joint prosecution privilege.
4. Relationship; Additions; Termination.
4.1 This Agreement does not create any agency or similar relationship among the
parties. Through the Closing (as defined in the Patent Purchase Agreement
executed by Purchaser and Seller), neither party nor their respective Counsel
has the authority to waive any applicable privilege or doctrine on behalf of any
other party.
4.2 Nothing in this Agreement affects the separate and independent
representation of each party by its respective Counsel or creates an attorney
client relationship between the Counsel for a party and the other party to this
Agreement.
4.3 This Agreement shall continue until terminated upon the written request of
either party. Upon termination, each party and their respective Counsel shall
return any Common Interest Materials furnished by the other party.
Notwithstanding termination, this Agreement shall continue to protect all Common
Interest Materials disclosed prior to termination. Sections 3 and 5 shall
survive termination of this Agreement.
5. General Terms.

5.1 This Agreement is governed by the laws of the State of Delaware, without
regard to its choice of law principles to the contrary. In the event any
provision of this Agreement is held by any court of competent jurisdiction to be
illegal, void or unenforceable, the remaining terms shall remain in effect.
Failure of either party to enforce any provision of this Agreement shall not be
deemed a waiver of future enforcement of that or any other provision.
5.2 The parties agree that a breach of this Agreement would result in
irreparable injury, that money damages would not be a sufficient remedy and that
the disclosing party shall be entitled to equitable relief, including injunctive
relief, as a non-exclusive remedy for any such breach.
5.3 Notices given under this Agreement shall be given in writing and delivered
by messenger or overnight delivery service to a party and their respective
Counsel at their last known address, and shall be deemed to have been given on
the day received.
5.4 This Agreement is effective and binding upon each party as of the date it is
signed by or on behalf of a party and may be amended only by a writing signed by
or on behalf of each party. This Agreement may be executed in counterparts. Any
signature reproduced or transmitted via email of a  .pdf file, photocopy,
facsimile or other process of complete and accurate reproduction and
transmission shall be considered an original for purposes of this Agreement.

This Agreement is being executed by each of the undersigned Counsel with the
fully informed authority and consent of the respective party it represents.

                      Counsel for Aprolase Development Co., LLC   Counsel for
Irvine Sensors Corporation  
 
                   
By:
          By:        
 
 
     
 
   
Date:
          Date:      
 
 
 
         
 
   

 

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Exhibit F
FORM OF PRESS RELEASE
At Closing:
[City, State], [Date]/PRNewswire-FirstCall/ — Irvine Sensors Corporation
announced today that it has completed the sale of selected patents and patent
applications to [Purchaser] for net proceeds of approximately $_______________.
The patents and patent applications sold relate to Irvine Sensors Corporation’s
_______________. Irvine Sensors Corporation retains a worldwide, non-exclusive
license under the patents for the __________________.]

 

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Exhibit G
[Deleted in its entirety and replaced with language of Amendment dated March 18,
2009 by and between Purchaser and Seller]