Repository: fujiapple852/trippy (language: rust)

Issue:
Add sequence custom column
Add sequence number as a custom column


Discussion / hints:

Fix patch:
diff --git a/src/backend/trace.rs b/src/backend/trace.rs
index 8e91a61ed..3915f75b4 100644
--- a/src/backend/trace.rs
+++ b/src/backend/trace.rs
@@ -151,6 +151,8 @@ pub struct Hop {
     last_src_port: u16,
     /// The destination port for last probe for this hop.
     last_dest_port: u16,
+    /// The sequence number for the last probe for this hop.
+    last_sequence: u16,
     /// The history of round trip times across the last N rounds.
     samples: Vec<Duration>,
     /// The ICMP extensions for this hop.
@@ -252,14 +254,21 @@ impl Hop {
         self.jinta
     }
 
+    /// The source port for last probe for this hop.
     pub fn last_src_port(&self) -> u16 {
         self.last_src_port
     }
 
+    /// The destination port for last probe for this hop.
     pub fn last_dest_port(&self) -> u16 {
         self.last_dest_port
     }
 
+    /// The sequence number for the last probe for this hop.
+    pub fn last_sequence(&self) -> u16 {
+        self.last_sequence
+    }
+
     /// The last N samples.
     pub fn samples(&self) -> &[Duration] {
         &self.samples
@@ -287,6 +296,7 @@ impl Default for Hop {
             jinta: 0f64,
             last_src_port: 0_u16,
             last_dest_port: 0_u16,
+            last_sequence: 0_u16,
             mean: 0f64,
             m2: 0f64,
             samples: Vec::default(),
@@ -411,6 +421,7 @@ impl TraceData {
                 hop.extensions = complete.extensions.clone();
                 hop.last_src_port = complete.src_port.0;
                 hop.last_dest_port = complete.dest_port.0;
+                hop.last_sequence = complete.sequence.0;
             }
             ProbeState::Awaited(awaited) => {
                 self.update_lowest_ttl(awaited.ttl);
@@ -424,6 +435,7 @@ impl TraceData {
                 }
                 self.hops[index].last_src_port = awaited.src_port.0;
                 self.hops[index].last_dest_port = awaited.dest_port.0;
+                self.hops[index].last_sequence = awaited.sequence.0;
             }
             ProbeState::NotSent | ProbeState::Skipped => {}
         }
diff --git a/src/config/columns.rs b/src/config/columns.rs
index 4c24e12c1..e53455f90 100644
--- a/src/config/columns.rs
+++ b/src/config/columns.rs
@@ -83,6 +83,8 @@ pub enum TuiColumn {
     LastSrcPort,
     /// The destination port for last probe for this hop.
     LastDestPort,
+    /// The sequence number for the last probe for this hop.
+    LastSeq,
 }
 
 impl TryFrom<char> for TuiColumn {
@@ -107,6 +109,7 @@ impl TryFrom<char> for TuiColumn {
             'i' => Ok(Self::Jinta),
             'S' => Ok(Self::LastSrcPort),
             'P' => Ok(Self::LastDestPort),
+            'Q' => Ok(Self::LastSeq),
             c => Err(anyhow!(format!("unknown column code: {c}"))),
         }
     }
@@ -132,6 +135,7 @@ impl Display for TuiColumn {
             Self::Jinta => write!(f, "i"),
             Self::LastSrcPort => write!(f, "S"),
             Self::LastDestPort => write!(f, "P"),
+            Self::LastSeq => write!(f, "Q"),
         }
     }
 }
diff --git a/src/frontend/columns.rs b/src/frontend/columns.rs
index 56b44bf4f..0fd7e2a01 100644
--- a/src/frontend/columns.rs
+++ b/src/frontend/columns.rs
@@ -91,6 +91,8 @@ pub enum Column {
     LastSrcPort,
     /// The destination port for last probe for this hop.
     LastDestPort,
+    /// The sequence number for the last probe for this hop.
+    LastSeq,
 }
 
 impl From<Column> for char {
@@ -113,6 +115,7 @@ impl From<Column> for char {
             Column::Jinta => 'i',
             Column::LastSrcPort => 'S',
             Column::LastDestPort => 'P',
+            Column::LastSeq => 'Q',
         }
     }
 }
@@ -137,6 +140,7 @@ impl From<TuiColumn> for Column {
             TuiColumn::Jinta => Self::Jinta,
             TuiColumn::LastSrcPort => Self::LastSrcPort,
             TuiColumn::LastDestPort => Self::LastDestPort,
+            TuiColumn::LastSeq => Self::LastSeq,
         }
     }
 }
@@ -161,6 +165,7 @@ impl Display for Column {
             Self::Jinta => write!(f, "Jint"),
             Self::LastSrcPort => write!(f, "Sprt"),
             Self::LastDestPort => write!(f, "Dprt"),
+            Self::LastSeq => write!(f, "Seq"),
         }
     }
 }
@@ -187,6 +192,7 @@ impl Column {
             Self::Jinta => ColumnWidth::Fixed(8),
             Self::LastSrcPort => ColumnWidth::Fixed(7),
             Self::LastDestPort => ColumnWidth::Fixed(7),
+            Self::LastSeq => ColumnWidth::Fixed(7),
         }
     }
 }
diff --git a/src/frontend/render/table.rs b/src/frontend/render/table.rs
index af394dba3..9b34b06e4 100644
--- a/src/frontend/render/table.rs
+++ b/src/frontend/render/table.rs
@@ -163,6 +163,7 @@ fn new_cell(
         Column::Jinta => render_float_cell(Some(hop.jinta()), 1),
         Column::LastSrcPort => render_port_cell(hop.last_src_port()),
         Column::LastDestPort => render_port_cell(hop.last_dest_port()),
+        Column::LastSeq => render_usize_cell(usize::from(hop.last_sequence())),
     }
 }
 


Test patch: