Repository: talonmyburgh/casper_dspdevel (language: python)

Issue:
Talon block wrapping
Include addition of simple bram VACC block


Discussion / hints:

Fix patch:
diff --git a/.gitignore b/.gitignore
index 3cb15149..db1fd30b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -17,3 +17,4 @@ vivado*.str
 *proj.runs*
 *.cache/
 *proj*.sim/
+casper_wb_fft/ngvla_test_proj/*
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ce316fcc..2e59f146 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,11 +1,12 @@
 image: ghdl/vunit:mcode-master
 variables:
-  GIT_CLONE_PATH: $CI_BUILDS_DIR/$CI_CONCURRENT_ID/casper_dspdevel
+  GIT_CLONE_PATH: $CI_BUILDS_DIR/$CI_CONCURRENT_ID/sim/casper_dspdevel
   GIT_SUBMODULE_STRATEGY: recursive
   
 stages:          # List of stages for jobs, and their order of execution
   - VunitSim
   - QuestaSim
+  - VivadoSynthesis
 casper_accumulators_test:   # This job runs in the test stage.
   stage: VunitSim    # It only starts when the job in the build stage completes successfully.
   tags: 
@@ -706,3 +707,48 @@ Questa_casper_wbpfb:   # This job runs in the test stage.
       - $GIT_CLONE_PATH/reports/*.xml
     reports:
       junit: $GIT_CLONE_PATH/reports/*.xml
+VivadoSynthesisWBFFT:
+  variables:
+    GIT_CLONE_PATH: $CI_BUILDS_DIR/$CI_CONCURRENT_ID/vivado/casper_dspdevel
+    GIT_SUBMODULE_STRATEGY: recursive
+  stage: VivadoSynthesis
+  image : vivado:2022.2
+  needs: []
+  tags:
+    - Vivado
+  script :
+    - echo Starting Vivado Synthesis WBFFT
+    # Fix any packages out of date, and install the missing libtinfo5
+    - apt update
+    - apt upgrade -y
+    - apt install -y libtinfo5 sudo
+    - useradd -m ci
+    - cd /tmp
+    - git clone https://github.com/Xilinx/XilinxTclStore.git
+    - chown -R ci $GIT_CLONE_PATH
+    - |     
+      sudo -H -i -u ci /usr/bin/bash -e -x << EOS
+      cd $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj
+      export LM_LICENSE_FILE=2100@cv-flexserverB.ad.nrao.edu:1717@cv-flexserverB.ad.nrao.edu
+      export XILINX_TCLAPP_REPO=/tmp/XilinxTclStore
+      export XILINX_LOCAL_USER_DATA=NO
+      rm -f *.jou
+      rm -f *.log
+      rm -f synth_output/post_synth.dcp
+      source /export/data_1/Xilinx/Vivado/2022.2/settings64.sh
+      LD_PRELOAD=/lib/x86_64-linux-gnu/libudev.so.1 vivado -mode batch -source ngVLA_wbfft_test.tcl
+      EOS
+  after_script:
+    # Set files back to root
+    - chown -R root.root $GIT_CLONE_PATH
+  when: manual
+  artifacts:
+    when: always
+    paths:
+      - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/*.jou
+      - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/*.log
+      - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/hs_err*
+      - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/report.xml
+      - $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/synth_output/post_synth.dcp
+    reports:
+      junit: $GIT_CLONE_PATH/casper_wb_fft/ngvla_test_proj/report.xml
diff --git a/casper_accumulators/addr_bram_vacc.vhd b/casper_accumulators/addr_bram_vacc.vhd
index 078e7fc9..f898044e 100644
--- a/casper_accumulators/addr_bram_vacc.vhd
+++ b/casper_accumulators/addr_bram_vacc.vhd
@@ -29,7 +29,6 @@ architecture rtl of addr_bram_vacc is
     SIGNAL s_delay_new_acc : std_logic :='0';
     SIGNAL s_delay_din : std_logic_vector(din'RANGE);
     SIGNAL s_pulse_ext_out : std_logic;
-    SIGNAL s_dout  : std_logic_vector(g_bit_w - 1 DOWNTO 0);
     SIGNAL s_a : std_logic_vector(g_bit_w - 1 DOWNTO 0);
     SIGNAL s_b : std_logic_vector(g_bit_w - 1 DOWNTO 0);
     SIGNAL s_delay_bram_in : std_logic_vector(g_bit_w - 1 DOWNTO 0);
@@ -41,7 +40,7 @@ begin
 --------------------------------------------------------------
 -- delay new_acc signal
 --------------------------------------------------------------
-delay_new_acc : process(clk, ce) 
+delay_new_acc : process(clk) 
 BEGIN
     IF rising_edge(clk) AND ce = '1' THEN
         s_delay_new_acc <= new_acc;
@@ -143,7 +142,7 @@ port map (
 --------------------------------------------------------------
 -- delay s_delay_bram_out signal
 --------------------------------------------------------------
-delay_bram_out : process(clk, ce) 
+delay_bram_out : process(clk) 
 BEGIN
     IF rising_edge(clk) AND ce = '1' THEN
         dout <= s_delay_bram_out;
@@ -153,7 +152,7 @@ END PROCESS;
 --------------------------------------------------------------
 -- delay s_pulse_ext_out signal
 --------------------------------------------------------------
-delay_s_pulse_ext_out : process(clk, ce) 
+delay_s_pulse_ext_out : process(clk) 
 BEGIN
     IF rising_edge(clk) AND ce = '1' THEN
         we <= s_pulse_ext_out;
diff --git a/casper_accumulators/run.py b/casper_accumulators/run.py
index 0a771504..c61263d0 100644
--- a/casper_accumulators/run.py
+++ b/casper_accumulators/run.py
@@ -1,6 +1,5 @@
 from vunit import VUnit
 from os.path import dirname, join
-from itertools import product
 import numpy as np
 
 # Create VUnit instance by parsing command line arguments
@@ -84,9 +83,14 @@
 # Accumulator Library
 casper_accumulator_lib = vu.add_library("casper_accumulator_lib")
 casper_accumulator_lib.add_source_files(join(script_dir, "./addr_bram_vacc.vhd"))
+casper_accumulator_lib.add_source_files(join(script_dir, "./simple_bram_vacc.vhd"))
 casper_accumulator_lib.add_source_files(join(script_dir, "./tb_addr_bram_vacc.vhd"))
+casper_accumulator_lib.add_source_files(join(script_dir, "./tb_simple_bram_vacc.vhd"))
 casper_accumulator_lib.add_source_files(join(script_dir, "./tb_tb_vu_addr_bram_vacc.vhd"))
+casper_accumulator_lib.add_source_files(join(script_dir, "./tb_tb_vu_simple_bram_vacc.vhd"))
+
 TB_ADDR_BRAM_VACC = casper_accumulator_lib.test_bench("tb_tb_vu_addr_bram_vacc")
+TB_SIMPLE_BRAM_VACC = casper_accumulator_lib.test_bench("tb_tb_vu_simple_bram_vacc")
 
 # Generics
 bit_w = [8,18]
@@ -98,6 +102,7 @@
 for b_w in bit_w:
     vector_len = ramp.size
     config_name = "TB_ADDR_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,rampstr[0:8])
+    config_name_simple = "TB_SIMPLE_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,rampstr[0:8])
     TB_ADDR_BRAM_VACC.add_config(
         name=config_name,
         generics=dict(
@@ -106,8 +111,17 @@
             g_vector_length=vector_len
         )
     )
+    TB_SIMPLE_BRAM_VACC.add_config(
+        name=config_name_simple,
+        generics=dict(
+            g_bit_w=b_w,
+            g_values=rampstr,
+            g_vector_length=vector_len
+        )
+    )
     vector_len = randnums.size
     config_name = "TB_ADDR_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,randstr[0:8])
+    config_name_simple = "TB_SIMPLE_BRAM_VACC: bit_w=%d, vec_len=%d, strvalue=%s..." % (b_w,vector_len,randstr[0:8])
     TB_ADDR_BRAM_VACC.add_config(
         name=config_name,
         generics=dict(
@@ -116,6 +130,14 @@
             g_vector_length=vector_len
         )
     )
+    TB_SIMPLE_BRAM_VACC.add_config(
+        name=config_name_simple,
+        generics=dict(
+            g_bit_w=b_w,
+            g_values=randstr,
+            g_vector_length=vector_len
+        )
+    )
 
 vu.set_compile_option("ghdl.a_flags", ["-Wno-hide", "-frelaxed","-fsynopsys","-fexplicit"])
 vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","-fsynopsys","-fexplicit","--syn-binding"])
diff --git a/casper_accumulators/simple_bram_vacc.vhd b/casper_accumulators/simple_bram_vacc.vhd
new file mode 100644
index 00000000..1c6d8b4c
--- /dev/null
+++ b/casper_accumulators/simple_bram_vacc.vhd
@@ -0,0 +1,104 @@
+-- A VHDL implementation of the CASPER simple_bram_vacc.
+-- @author: Talon Myburgh
+-- @company: Mydon Solutions
+
+LIBRARY IEEE, common_pkg_lib, 
+casper_misc_lib, common_components_lib, casper_adder_lib,
+casper_delay_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_pkg_lib.common_pkg.ALL;
+
+entity simple_bram_vacc is
+    generic(
+        g_vector_length : NATURAL := 16;
+        g_output_type   : STRING  := "SIGNED";
+        g_bit_w         : NATURAL := 32
+    );
+    port (
+        clk         : IN std_logic;
+        ce          : IN std_logic;
+        new_acc     : IN std_logic;
+        din         : IN std_logic_vector;
+        valid       : OUT std_logic := '0';
+        dout        : OUT std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0')
+    );
+END simple_bram_vacc;
+
+architecture rtl of simple_bram_vacc is
+    SIGNAL s_pulse_ext_out : std_logic;
+    SIGNAL s_a : std_logic_vector(g_bit_w - 1 DOWNTO 0);
+    SIGNAL s_delay_bram_in : std_logic_vector(g_bit_w - 1 DOWNTO 0);
+    SIGNAL s_delay_bram_out : std_logic_vector(g_bit_w - 1 DOWNTO 0);
+    SIGNAL s_mux_out : std_logic_vector(g_bit_w - 1 DOWNTO 0);
+
+begin
+
+--------------------------------------------------------------
+-- pulse extend new_acc signal
+--------------------------------------------------------------
+pulse_ext : entity casper_misc_lib.pulse_ext
+generic map(
+    g_extension => g_vector_length
+)
+port map(
+    clk => clk,
+    ce  => ce,
+    i_pulse => new_acc,
+    o_pulse => s_pulse_ext_out
+);
+
+--------------------------------------------------------------
+-- mux block
+--------------------------------------------------------------
+s_mux_out <=  s_delay_bram_out when s_pulse_ext_out = '0' else
+        (others=>'0') when  s_pulse_ext_out = '1' else
+        (others=>'X');
+
+--------------------------------------------------------------
+-- resize din signal
+--------------------------------------------------------------
+s_a <= RESIZE_SVEC(din, g_bit_w);
+
+--------------------------------------------------------------
+-- adder block
+--------------------------------------------------------------
+add_a_b : entity casper_adder_lib.common_add_sub
+generic map(
+    g_direction => "ADD",
+    g_representation => g_output_type,
+    g_pipeline_input => 0,
+    g_pipeline_output => 2,
+    g_in_dat_w => g_bit_w,
+    g_out_dat_w => g_bit_w
+)
+port map(
+    clk => clk,
+    clken => ce,
+    in_a => s_a,
+    in_b => s_mux_out,
+    result => s_delay_bram_in
+);
+
+--------------------------------------------------------------
+-- delay bram
+--------------------------------------------------------------
+delay_bram_blk : entity casper_delay_lib.delay_bram
+generic map (
+    g_delay => g_vector_length - 2,
+    g_ram_primitive => "block",
+    g_ram_latency => 2
+)
+port map (
+    clk => clk,
+    ce => ce,
+    din => s_delay_bram_in,
+    dout => s_delay_bram_out
+);
+
+--------------------------------------------------------------
+-- set up output signals
+--------------------------------------------------------------
+dout <= s_delay_bram_out;
+valid <= s_pulse_ext_out;
+
+END rtl;
\ No newline at end of file
diff --git a/casper_accumulators/tb_simple_bram_vacc.vhd b/casper_accumulators/tb_simple_bram_vacc.vhd
new file mode 100644
index 00000000..6328b7f1
--- /dev/null
+++ b/casper_accumulators/tb_simple_bram_vacc.vhd
@@ -0,0 +1,127 @@
+-- A VHDL testbench for simple_bram_vacc.vhd.
+-- @author: Talon Myburgh
+-- @company: Mydon Solutions
+
+LIBRARY IEEE, std, common_pkg_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_pkg_lib.common_pkg.ALL;
+USE STD.TEXTIO.ALL;
+
+entity tb_simple_bram_vacc is
+    generic (
+        g_vector_length : NATURAL := 8;
+        g_bit_w_out     : NATURAL := 8;
+        g_bit_w         : NATURAL := 8;
+        g_values        : t_integer_arr := (-1, 4, 10, -2, 3, 0, -15, 0)
+    );
+    port (
+        o_clk   : out std_logic;
+        o_tb_end : out std_logic;
+        o_test_msg : out STRING(1 to 80);
+        o_test_pass : out BOOLEAN := True 
+    );
+end entity tb_simple_bram_vacc;
+
+architecture rtl of tb_simple_bram_vacc is
+
+    CONSTANT clk_period : TIME    := 10 ns;
+
+    SIGNAL clk : STD_LOGIC := '0';
+    SIGNAL ce : STD_LOGIC;
+    SIGNAL tb_end  : STD_LOGIC := '0';
+    SIGNAL new_acc : STD_LOGIC := '0';
+    SIGNAL din : std_logic_vector(g_bit_w - 1 DOWNTO 0) := (others=>'0');
+    SIGNAL valid : STD_LOGIC;
+    SIGNAL dout : std_logic_vector(g_bit_w_out - 1 DOWNTO 0);
+
+begin
+    clk  <= NOT clk OR tb_end AFTER clk_period / 2;
+
+	o_clk <= clk;
+	o_tb_end <= tb_end;
+
+    ---------------------------------------------------------------------
+    -- Stimulus process
+    ---------------------------------------------------------------------
+    p_stimuli_verify : PROCESS
+        VARIABLE v_test_msg : STRING(1 to o_test_msg'length) := (OTHERS => '.');
+        VARIABLE v_test_vector : STD_LOGIC_VECTOR(g_bit_w -1 DOWNTO 0);
+        VARIABLE v_test_pass : BOOLEAN := True;
+    BEGIN
+        WAIT UNTIL rising_edge(clk);
+        ce <= '1';
+        new_acc <= '1';
+        WAIT FOR clk_period*(g_vector_length+2);
+        FOR I in 0 to g_vector_length - 1 LOOP
+            WAIT FOR clk_period;
+            v_test_vector := TO_SVEC(g_values(g_values'LOW + I), g_bit_w);
+            v_test_pass := v_test_pass or (dout = v_test_vector);
+            IF NOT v_test_pass THEN
+                v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.');
+                o_test_msg <= v_test_msg;
+                report "Error: " & v_test_msg severity error;
+            END IF;
+        END LOOP;
+        WAIT FOR clk_period*(g_vector_length)*5;
+        FOR I in 0 to g_vector_length - 1 LOOP
+            WAIT FOR clk_period;
+            v_test_vector := TO_SVEC(g_values(g_values'LOW + I)*7, g_bit_w);
+            v_test_pass := v_test_pass or (dout = v_test_vector);
+            IF NOT v_test_pass THEN
+                v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.');
+                o_test_msg <= v_test_msg;
+                report "Error: " & v_test_msg severity error;
+            END IF;
+        END LOOP;
+        new_acc <= '0';
+        WAIT FOR clk_period*(g_vector_length - 1);
+        -- reload the vector
+        new_acc <= '1';
+        WAIT FOR clk_period*(g_vector_length+1);
+        WAIT UNTIL rising_edge(clk);
+        v_test_vector := TO_SVEC(g_values(g_values'LOW), g_bit_w);
+        v_test_pass := v_test_pass or (dout = v_test_vector);
+        IF NOT v_test_pass THEN
+            v_test_msg := pad("wrong RTL result for dout, expected: " & to_hstring(v_test_vector) & " but got: " & to_hstring(dout), o_test_msg'length, '.');
+            o_test_msg <= v_test_msg;
+            report "Error: " & v_test_msg severity error;
+        END IF;
+        o_test_msg <= v_test_msg;
+        o_test_pass <= v_test_pass;
+        tb_end <= '1';
+    WAIT;
+    
+    END PROCESS;
+
+    -- Process to unroll values into din
+    p_unroll_nat_array : PROCESS(clk)
+        VARIABLE I : INTEGER := 0;
+    BEGIN
+        IF rising_edge(clk) and ce = '1' THEN
+            din <= TO_SVEC(g_values(g_values'LOW + I), g_bit_w);
+            IF I = g_vector_length -1 THEN
+                I := 0;
+            ELSE
+                I := I + 1;
+            END IF;
+        END IF;
+    END PROCESS;
+    ---------------------------------------------------------------------
+    -- simple BRAM vacc module
+    ---------------------------------------------------------------------
+    simple_bram_vacc : ENTITY work.simple_bram_vacc
+    generic map(
+            g_vector_length => g_vector_length,
+            g_bit_w         => g_bit_w_out
+        )
+        port map(
+            clk => clk,
+            ce => ce,
+            new_acc => new_acc,
+            din => din,
+            valid => valid,
+            dout => dout
+        );
+
+end architecture;
\ No newline at end of file
diff --git a/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd b/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd
new file mode 100644
index 00000000..433a16c2
--- /dev/null
+++ b/casper_accumulators/tb_tb_vu_simple_bram_vacc.vhd
@@ -0,0 +1,67 @@
+-- @author: Talon Myburgh
+-- @company: Mydon Solutions
+
+library ieee, common_pkg_lib, vunit_lib;
+use IEEE.std_logic_1164.all;
+use common_pkg_lib.common_pkg.all;
+context vunit_lib.vunit_context;
+
+entity tb_tb_vu_simple_bram_vacc is
+    GENERIC(
+        g_vector_length : NATURAL := 8;
+        g_bit_w         : NATURAL := 8;
+        g_values        : STRING; -- CSV list of naturals
+        runner_cfg      : STRING
+    );
+end tb_tb_vu_simple_bram_vacc;
+
+architecture tb of tb_tb_vu_simple_bram_vacc is
+
+    SIGNAL rst      	: STD_LOGIC := '0';
+	SIGNAL clk      	: STD_LOGIC;
+	SIGNAL tb_end   	: STD_LOGIC;
+	SIGNAL test_msg     : STRING(1 to 80);
+	SIGNAL test_pass	: BOOLEAN;
+
+	IMPURE FUNCTION decode(encoded_natural_vector : string) return t_integer_arr is
+		VARIABLE parts : lines_t := split(encoded_natural_vector, ",");
+		VARIABLE return_value : t_integer_arr(parts'range);
+	BEGIN
+		for i in parts'range loop
+			return_value(i) := natural'value(parts(i).all);
+		end loop;
+		return return_value;
+	END;
+
+	CONSTANT c_values : t_integer_arr := decode(g_values);
+BEGIN
+	tb_ut : ENTITY work.tb_simple_bram_vacc
+        GENERIC MAP(
+            g_vector_length => g_vector_length,
+            g_bit_w_out => 32,
+            g_bit_w => g_bit_w,
+            g_values => c_values
+        )
+		PORT MAP(
+			o_clk => clk,
+			o_tb_end => tb_end,
+			o_test_msg => test_msg,
+			o_test_pass => test_pass
+		);
+
+	p_vunit : PROCESS
+	BEGIN
+		test_runner_setup(runner, runner_cfg);
+		wait until tb_end = '1';
+		test_runner_cleanup(runner);
+		wait;
+	END PROCESS;
+
+	p_verify : PROCESS(clk)
+	BEGIN
+		IF rising_edge(clk) THEN
+			check(test_pass, "Test Failed: " & test_msg);
+		END IF;
+
+	END PROCESS;
+END tb;
\ No newline at end of file
diff --git a/casper_adder/run.py b/casper_adder/run.py
index b00d5e2c..ec9a08d3 100644
--- a/casper_adder/run.py
+++ b/casper_adder/run.py
@@ -1,92 +1,149 @@
-import os
-import random
-from itertools import product
-from vunit import VUnit
-
-def generate_tests(obj, direc, add_sub, inp_pipeline, out_pipeline, in_dat_w):
-    """
-    Generate test by varying the generics of casper_adder:
-        direc : string {SUB,ADD,BOTH}
-        add_sub : int {0,1}
-        pipeline_in : int {0,1}
-        pipeline_out : int {5}
-        in_dat_w : int {1,5}
-        out_dat_w : int {in_dat_w,in_dat_w+1}
-    """
-    testnum = 1;
-    for d, a_s, i_pipe, o_pipe, i_d_w in product(direc,add_sub,inp_pipeline,out_pipeline,in_dat_w):
-        ab_value_ranges = [(0,0,0,0)] # default, exhaustive
-        if i_d_w > 14:
-            min_val = -(2**(i_d_w-1))
-            max_val = (-min_val)-1
-
-            ab_value_ranges = [
-                (min_val,min_val+128,-16,15),
-                (-128,+128,-16,15),
-                (max_val,max_val-128,-16,15)
-                ]
-        elif i_d_w > 10:
-            ab_value_ranges = [(0,0,-16,15)] # default, exhaustive
-
-        for a_v_min, a_v_max, b_v_min, b_v_max in ab_value_ranges:
-            non_exhaustive_value_range = any([lim != 0 for lim in [a_v_min, a_v_max, b_v_min, b_v_max]])
-            value_range_string = ", a_val = [%d,%d] , b_val = [%d,%d]" % (
-                a_v_min if a_v_min != 0 else -(2**(i_d_w-1)),
-                a_v_max if a_v_max != 0 else (2**(i_d_w-1))-1,
-                b_v_min if b_v_min != 0 else -(2**(i_d_w-1)),
-                b_v_max if b_v_max != 0 else (2**(i_d_w-1))-1 
-            )
-            config_name1 = "TestA%d"%(testnum)
-            #testnum = testnum + 1
-            #config_name1 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w)
-            #if non_exhaustive_value_range:
-            #    config_name1 += value_range_string
-            obj.add_config(
-                name = config_name1,
-                generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w,
-                                g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max)
-            )
-            #config_name2 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w+1)
-            #if non_exhaustive_value_range:
-            #    config_name2 += value_range_string
-            config_name2 = "TestB%d"%(testnum)
-            testnum = testnum + 1
-            obj.add_config(
-                name = config_name2,
-                generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w+1,
-                                g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max)
-            )
-
-vu = VUnit.from_argv()
-vu.add_vhdl_builtins()
-script_dir = os.path.dirname(__file__)
-
-lib1 = vu.add_library("casper_adder_lib",allow_duplicate=True)
-lib1.add_source_files(os.path.join(script_dir, "*.vhd"))
-TB_GENERATED = lib1.test_bench("tb_tb_vu_common_add_sub")
-
-direc_values = ['BOTH']
-add_sub_values = [0,1]
-inp_pipeline_values = random.sample([0,1], 1)
-out_pipeline_values = [0] + random.sample(range(1,5), 1)
-in_dat_w_values = [18] + random.sample(range(4, 8), 1) + random.sample(range(9, 17), 1) 
-
-generate_tests(TB_GENERATED,
-    direc_values,
-    add_sub_values,
-    inp_pipeline_values,
-    out_pipeline_values,
-    in_dat_w_values
-)
-
-lib2 = vu.add_library("common_components_lib",allow_duplicate=True)
-lib2.add_source_files(os.path.join(script_dir, "../common_components/*.vhd"))
-
-lib3 = vu.add_library("common_pkg_lib",allow_duplicate = True)
-lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_float_types_c.vhd"))
-lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_pkg_c.vhd"))
-lib3.add_source_files(os.path.join(script_dir, "../common_pkg/float_pkg_c.vhd"))
-lib3.add_source_files(os.path.join(script_dir, "../common_pkg/*.vhd"))
-
-vu.set_compile_option("ghdl.a_flags", ["-Wno-hide"])
-vu.main()
+import os
+import random
+from itertools import product
+from vunit import VUnit
+
+def generate_tests(obj, direc, add_sub, inp_pipeline, out_pipeline, in_dat_w):
+    """
+    Generate test by varying the generics of casper_adder:
+        direc : string {SUB,ADD,BOTH}
+        add_sub : int {0,1}
+        pipeline_in : int {0,1}
+        pipeline_out : int {5}
+        in_dat_w : int {1,5}
+        out_dat_w : int {in_dat_w,in_dat_w+1}
+    """
+    testnum = 1;
+    for d, a_s, i_pipe, o_pipe, i_d_w in product(direc,add_sub,inp_pipeline,out_pipeline,in_dat_w):
+        ab_value_ranges = [(0,0,0,0)] # default, exhaustive
+        if i_d_w > 14:
+            min_val = -(2**(i_d_w-1))
+            max_val = (-min_val)-1
+
+            ab_value_ranges = [
+                (min_val,min_val+128,-16,15),
+                (-128,+128,-16,15),
+                (max_val,max_val-128,-16,15)
+                ]
+        elif i_d_w > 10:
+            ab_value_ranges = [(0,0,-16,15)] # default, exhaustive
+
+        for a_v_min, a_v_max, b_v_min, b_v_max in ab_value_ranges:
+            non_exhaustive_value_range = any([lim != 0 for lim in [a_v_min, a_v_max, b_v_min, b_v_max]])
+            value_range_string = ", a_val = [%d,%d] , b_val = [%d,%d]" % (
+                a_v_min if a_v_min != 0 else -(2**(i_d_w-1)),
+                a_v_max if a_v_max != 0 else (2**(i_d_w-1))-1,
+                b_v_min if b_v_min != 0 else -(2**(i_d_w-1)),
+                b_v_max if b_v_max != 0 else (2**(i_d_w-1))-1 
+            )
+            config_name1 = "TestA%d"%(testnum)
+            #testnum = testnum + 1
+            #config_name1 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w)
+            #if non_exhaustive_value_range:
+            #    config_name1 += value_range_string
+            obj.add_config(
+                name = config_name1,
+                generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w,
+                                g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max)
+            )
+            #config_name2 = "direc = %s, add_sub = %s, i_pipe = %i, o_pipe = %i, in_dat_w = %i, out_dat_w = %i" % (d, a_s, i_pipe, o_pipe, i_d_w, i_d_w+1)
+            #if non_exhaustive_value_range:
+            #    config_name2 += value_range_string
+            config_name2 = "TestB%d"%(testnum)
+            testnum = testnum + 1
+            obj.add_config(
+                name = config_name2,
+                generics=dict(g_direction=d,g_sel_add=a_s,g_pipeline_in=i_pipe, g_pipeline_out=o_pipe, g_in_dat_w=i_d_w,g_out_dat_w=i_d_w+1,
+                                g_a_val_min=a_v_min, g_a_val_max=a_v_max, g_b_val_min=b_v_min, g_b_val_max=b_v_max)
+            )
+
+vu = VUnit.from_argv()
+vu.add_vhdl_builtins()
+script_dir = os.path.dirname(__file__)
+
+lib1 = vu.add_library("casper_adder_lib",allow_duplicate=True)
+lib1.add_source_files(os.path.join(script_dir, "*.vhd"))
+TB_GENERATED = lib1.test_bench("tb_tb_vu_common_add_sub")
+
+direc_values = ['BOTH']
+add_sub_values = [0,1]
+inp_pipeline_values = random.sample([0,1], 1)
+out_pipeline_values = [0] + random.sample(range(1,5), 1)
+in_dat_w_values = [18] + random.sample(range(4, 8), 1) + random.sample(range(9, 17), 1) 
+
+generate_tests(TB_GENERATED,
+    direc_values,
+    add_sub_values,
+    inp_pipeline_values,
+    out_pipeline_values,
+    in_dat_w_values
+)
+
+lib2 = vu.add_library("common_components_lib",allow_duplicate=True)
+lib2.add_source_files(os.path.join(script_dir, "../common_components/*.vhd"))
+
+# XPM Library compile
+lib_xpm = vu.add_library("xpm")
+lib_xpm.add_source_files(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_VCOMP.vhd"))
+xpm_source_file_base = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_base.vhd"))
+xpm_source_file_sdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sdpram.vhd"))
+xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_tdpram.vhd"))
+xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_sprom.vhd"))
+xpm_source_file_tdpram = lib_xpm.add_source_file(os.path.join(script_dir, "../xilinx/xpm_vhdl/src/xpm/xpm_memory/hdl/xpm_memory_dprom.vhd"))
+xpm_source_file_sdpram.add_dependency_on(xpm_source_file_base)
+xpm_source_file_tdpram.add_dependency_on(xpm_source_file_base)
+
+# Altera_mf library
+lib_altera_mf = vu.add_library("altera_mf")
+lib_altera_mf.add_source_file(os.path.join(script_dir, "../intel/altera_mf/altera_mf_components.vhd"))
+altera_mf_source_file = lib_altera_mf.add_source_file(os.path.join(script_dir, "../intel/altera_mf/altera_mf.vhd"))
+
+# STRATIXIV RAM Library
+ip_stratixiv_ram_lib = vu.add_library("ip_stratixiv_ram_lib")
+ip_stratix_file_cr_cw = ip_stratixiv_ram_lib.add_source_file(os.path.join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd"))
+ip_stratix_file_crw_crw = ip_stratixiv_ram_lib.add_source_file(os.path.join(script_dir, "../ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd"))
+ip_stratix_file_cr_cw.add_dependency_on(altera_mf_source_file)
+ip_stratix_file_crw_crw.add_dependency_on(altera_mf_source_file)
+
+ip_xpm_ram_lib = vu.add_library("ip_xpm_ram_lib")
+ip_xpm_file_cr_cw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd"))
+ip_xpm_file_cr_cw.add_dependency_on(xpm_source_file_sdpram)
+ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd"))
+ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram)
+ip_xpm_file_crw_crw = ip_xpm_ram_lib.add_source_files(os.path.join(script_dir, "../ip_xpm/ram/ip_xpm_rom_r_r.vhd"))
+ip_xpm_file_crw_crw.add_dependency_on(xpm_source_file_tdpram)
+
+# TECHNOLOGY Library
+technology_lib = vu.add_library("technology_lib")
+technology_lib.add_source_files(os.path.join(script_dir, "../technology/technology_select_pkg.vhd"))
+
+casper_ram_lib = vu.add_library("casper_ram_lib")
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_pkg.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_component_pkg.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_ram_crw_crw.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_ram_cr_cw.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_rom_r.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/tech_memory_rom_r_r.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_crw_crw.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_rw_rw.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_rom_r_r.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_ram_r_w.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_r_w.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_rw_rw.vhd"))
+casper_ram_lib.add_source_file(os.path.join(script_dir, "../casper_ram/common_paged_ram_crw_crw.vhd"))
+
+lib3 = vu.add_library("common_pkg_lib",allow_duplicate = True)
+lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_float_types_c.vhd"))
+lib3.add_source_files(os.path.join(script_dir, "../common_pkg/fixed_pkg_c.vhd"))
+lib3.add_source_files(os.path.join(script_dir, "../common_pkg/float_pkg_c.vhd"))
+lib3.add_source_files(os.path.join(script_dir, "../common_pkg/*.vhd"))
+
+
+
+
+vu.set_compile_option("ghdl.a_flags", ["-frelaxed","-fsynopsys","-fexplicit","-Wno-hide"])
+#vu.set_sim_option("ghdl.elab_e", True)
+vu.set_sim_option("ghdl.elab_flags", ["-frelaxed","-fsynopsys","-fexplicit","--syn-binding"])
+vu.set_sim_option("ghdl.sim_flags",["--max-stack-alloc=4096"])
+
+vu.main()
diff --git a/casper_filter/fil_ppf_ctrl.vhd b/casper_filter/fil_ppf_ctrl.vhd
index d2b380b4..e377e18c 100644
--- a/casper_filter/fil_ppf_ctrl.vhd
+++ b/casper_filter/fil_ppf_ctrl.vhd
@@ -84,7 +84,17 @@ architecture rtl of fil_ppf_ctrl is
     out_val_ena  : std_logic;                                  -- Output enable 
   end record;
   
-  signal r, rin : reg_type; 
+  constant c_reg_type_rst : reg_type := (
+    in_dat_arr => (others=>(others=>'0')),
+    init_dly_cnt => 0,
+    val_dly => (others=>'0'),
+    rd_addr => (others=>'0'),
+    wr_addr => (others=>'0'),
+    wr_en => '0',
+    taps_out_vec => (others=>'0'),
+    out_val_ena => '0'); 
+  
+  signal r, rin : reg_type := c_reg_type_rst; 
   
 begin
   
diff --git a/casper_wb_fft/fft_reorder_sepa_pipe.vhd b/casper_wb_fft/fft_reorder_sepa_pipe.vhd
index 6968dce0..97af6890 100755
--- a/casper_wb_fft/fft_reorder_sepa_pipe.vhd
+++ b/casper_wb_fft/fft_reorder_sepa_pipe.vhd
@@ -123,36 +123,49 @@ architecture rtl of fft_reorder_sepa_pipe is
     signal buf_rd_val, buf_rd_val_d1                : std_logic;
 
     -- separate ports
-    signal sep_in_dat                            : std_logic_vector(c_dat_w - 1 downto 0);
-    signal sep_in_val, sep_in_sync, sep_out_sync : std_logic;
-
-    signal sep_out_dat_i : std_logic_vector(c_dat_w - 1 downto 0);
-    signal sep_out_val_i : std_logic;
-
-    signal not_first_spectrum : std_logic := '0';
-    signal count_out_en       : std_logic;
-
-    signal next_page : std_logic;
-
-    signal cnt_ena : std_logic;
-
-    signal rd_en       : std_logic;
-    signal rd_adr_up   : std_logic_vector(c_adr_points_w downto 0);
-    signal rd_adr_down : std_logic_vector(c_adr_points_w downto 0); -- use intermediate rd_adr_down that has 1 bit extra to avoid truncation warning with TO_UVEC()
-    signal rd_adr      : std_logic_vector(c_adr_tot_w - 1 downto 0);
-
-    type state_type is (s_idle, s_run_separate, s_run_normal);
-
-    type reg_type is record
-        rd_en      : std_logic;         -- The read enable signal to read out the data from the dp memory
-        switch     : std_logic;         -- Toggel register used for separate functionalilty
-        count_up   : natural;           -- An upwards counter for read addressing
-        count_down : natural;           -- A downwards counter for read addressing
-        count_chan : natural;           -- Counter that holds the number of channels for reading. 
-        state      : state_type;        -- The state machine. 
-    end record;
-
-    signal r, rin : reg_type;
+    signal sep_in_dat, sep_out_dat      : std_logic_vector(c_dat_w - 1 downto 0);
+    signal sep_in_val, sep_out_val      : std_logic;
+
+    signal sep_out_dat_i      : std_logic_vector(c_dat_w - 1 downto 0);
+    signal sep_out_val_i      : std_logic;
+    
+    signal not_first_spectrum     : std_logic := '0';
+    signal count_out_en           : std_logic;
+           
+	signal next_page : std_logic;
+
+	signal cnt_ena : std_logic;
+
+	signal rd_en       : std_logic;
+	signal rd_adr_up   : std_logic_vector(c_adr_points_w downto 0);
+	signal rd_adr_down : std_logic_vector(c_adr_points_w downto 0); -- use intermediate rd_adr_down that has 1 bit extra to avoid truncation warning with TO_UVEC()
+	signal rd_adr      : std_logic_vector(c_adr_tot_w - 1 downto 0);
+	signal rd_dat      : std_logic_vector(c_dat_w - 1 downto 0);
+	signal rd_val      : std_logic;
+
+	signal out_dat_i : std_logic_vector(c_dat_w - 1 downto 0);
+	signal out_val_i : std_logic;
+
+	type state_type is (s_idle, s_run_separate, s_run_normal);
+
+	type reg_type is record
+		rd_en      : std_logic;         -- The read enable signal to read out the data from the dp memory
+		switch     : std_logic;         -- Toggel register used for separate functionalilty
+		count_up   : natural;           -- An upwards counter for read addressing
+		count_down : natural;           -- A downwards counter for read addressing
+		count_chan : natural;           -- Counter that holds the number of channels for reading. 
+		state      : state_type;        -- The state machine. 
+	end record;
+	
+	constant c_reg_type : reg_type := (
+	       rd_en => '0',
+	       switch => '0',
+	       count_up => 0,
+	       count_down => 0,
+	       count_chan => 0,
+	       state => s_idle);
+
+	signal r, rin : reg_type := c_reg_type;
 
 begin
     u_adr_chan_cnt : entity casper_counter_lib.common_counter
diff --git a/casper_wb_fft/fft_sepa.vhd b/casper_wb_fft/fft_sepa.vhd
index a8c982e4..2f9e25ac 100755
--- a/casper_wb_fft/fft_sepa.vhd
+++ b/casper_wb_fft/fft_sepa.vhd
@@ -95,8 +95,23 @@ architecture rtl of fft_sepa is
         out_dat     : std_logic_vector(c_c_data_w - 1 downto 0); -- Registered output value
         out_val     : std_logic;        -- Registered data valid signal  
     end record;
+    
+    constant c_reg_type : reg_type := (
+        switch      => '0',        -- Register used to toggle between A & B definitionn
+        val_dly     => (others=>'0'), -- Register that delays the incoming valid signal
+        xn_m_reg    => (others=>'0'), -- Register to hold the X(N-m) value for one cycle
+        xm_reg      => (others=>'0'), -- Register to hold the X(m) value for one cycle
+        add_1_reg_a => (others=>'0'), -- Input register A for the adder
+        add_1_reg_b => (others=>'0'), -- Input register B for the adder
+        add_2_reg_a => (others=>'0'), -- Input register A for the subtractor
+        add_2_reg_b => (others=>'0'), -- Input register B for the subtractor
+        adder_1_dir => '0',        -- Direction for the adder block
+        adder_2_dir => '0',        -- Direction for the adder block
+        out_dat     => (others=>'0'), -- Registered output value
+        out_val     => '0'        -- Registered data valid signal 
+    );
 
-    signal r, rin     : reg_type;
+    signal r, rin     : reg_type := c_reg_type;
     signal sub_result : std_logic_vector(c_data_w downto 0); -- Result of the subtractor   
     signal add_result : std_logic_vector(c_data_w downto 0); -- Result of the adder
     
diff --git a/casper_wbpfb/dp_block_gen_valid_arr.vhd b/casper_wbpfb/dp_block_gen_valid_arr.vhd
index 7d7071a5..685c61f0 100644
--- a/casper_wbpfb/dp_block_gen_valid_arr.vhd
+++ b/casper_wbpfb/dp_block_gen_valid_arr.vhd
@@ -160,7 +160,7 @@ ENTITY dp_block_gen_valid_arr IS
     snk_in      : IN  t_fft_sosi_out;  -- = snk_in_arr(0)
     snk_in_arr  : IN  t_fft_sosi_arr_out(g_nof_streams-1 DOWNTO 0);
     -- Streaming source
-    src_out_arr : OUT t_fft_sosi_arr_out(g_nof_streams-1 DOWNTO 0);
+    src_out_arr : OUT t_fft_sosi_arr_out(g_nof_streams-1 DOWNTO 0) := (others => c_fft_sosi_rst_out);
     -- Control
     enable      : IN  STD_LOGIC := '1'  -- can connect via MM or could also connect to a src_in.xon
   );
@@ -183,8 +183,6 @@ ARCHITECTURE rtl OF dp_block_gen_valid_arr IS
     RETURN TRUE;
   END parameter_asserts;
   
-  CONSTANT c_parameters_ok : BOOLEAN := parameter_asserts(g_check_input_sync, g_nof_pages_bsn);
-  
   TYPE t_state IS (s_sop, s_data, s_eop);
 
   TYPE t_reg IS RECORD  -- local registers
@@ -204,8 +202,8 @@ ARCHITECTURE rtl OF dp_block_gen_valid_arr IS
   SIGNAL nxt_src_out_arr : t_fft_sosi_arr_out(g_nof_streams-1 DOWNTO 0);
     
   -- Define the local registers in t_reg record
-  SIGNAL r         : t_reg;
-  SIGNAL nxt_r     : t_reg;
+  SIGNAL r         : t_reg := c_reg_rst;
+  SIGNAL nxt_r     : t_reg := c_reg_rst;
   
 BEGIN
   
diff --git a/casper_wbpfb/wbpfb_unit_dev.vhd b/casper_wbpfb/wbpfb_unit_dev.vhd
index bbdf1b96..9fcbf616 100644
--- a/casper_wbpfb/wbpfb_unit_dev.vhd
+++ b/casper_wbpfb/wbpfb_unit_dev.vhd
@@ -337,26 +337,26 @@ use work.wbpfb_gnrcs_intrfcs_pkg.all;
 
 entity wbpfb_unit_dev is
     generic(
-        g_big_endian_wb_in   : boolean := true;
-        g_wpfb               : t_wpfb  := c_wpfb;
-        g_dont_flip_channels : boolean := false; -- True preserves channel interleaving for pipelined FFT
-        g_use_prefilter      : boolean := TRUE;
-        g_coefs_file_prefix  : string  := c_coefs_file; -- File prefix for the coefficients files.
-        g_alt_output         : boolean := FALSE; -- Governs the ordering of the output samples. False = ArBrArBr;AiBiAiBi, True = AiArAiAr;BiBrBiBr
-        g_fil_ram_primitive  : string  := "block";
-        g_use_variant        : string  := "4DSP"; --! = "4DSP" or "3DSP" for 3 or 4 mult cmult.
-        g_use_dsp            : string  := "yes"; --! = "yes" or "no"
-        g_ovflw_behav        : string  := "WRAP"; --! = "WRAP" or "SATURATE" will default to WRAP if invalid option used
-        g_round              : t_rounding_mode  := ROUND; --! = ROUND, ROUNDINF or TRUNCATE - defaults to ROUND if not specified
-        g_fft_ram_primitive  : string  := "block"; --! = "auto", "distributed", "block" or "ultra" for RAM architecture
-        g_twid_file_stem     : string  := c_twid_file_stem --! file stem for the twiddle coefficients                  
+        g_big_endian_wb_in   : boolean         := true;
+        g_wpfb               : t_wpfb          := c_wpfb;
+        g_dont_flip_channels : boolean         := false; -- True preserves channel interleaving for pipelined FFT
+        g_use_prefilter      : boolean         := TRUE;
+        g_coefs_file_prefix  : string          := c_coefs_file; -- File prefix for the coefficients files.
+        g_alt_output         : boolean         := FALSE; -- Governs the ordering of the output samples. False = ArBrArBr;AiBiAiBi, True = AiArAiAr;BiBrBiBr
+        g_fil_ram_primitive  : string          := "block";
+        g_use_variant        : string          := "4DSP"; --! = "4DSP" or "3DSP" for 3 or 4 mult cmult.
+        g_use_dsp            : string          := "yes"; --! = "yes" or "no"
+        g_ovflw_behav        : string          := "WRAP"; --! = "WRAP" or "SATURATE" will default to WRAP if invalid option used
+        g_round              : t_rounding_mode := ROUND; --! = ROUND, ROUNDINF or TRUNCATE - defaults to ROUND if not specified
+        g_fft_ram_primitive  : string          := "block"; --! = "auto", "distributed", "block" or "ultra" for RAM architecture
+        g_twid_file_stem     : string          := c_twid_file_stem --! file stem for the twiddle coefficients                  
     );
     port(
-        rst          : in  std_logic                                                                := '0';
-        clk          : in  std_logic                                                                := '0';
-        ce           : in  std_logic                                                                := '1';
-        shiftreg     : in  std_logic_vector(ceil_log2(g_wpfb.nof_points) - 1 DOWNTO 0)              := (others => '1'); --! Shift register
-        in_sosi_arr  : in  t_fil_sosi_arr_in(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => c_fil_sosi_rst_in);
+        rst          : in  std_logic                                                   := '0';
+        clk          : in  std_logic                                                   := '0';
+        ce           : in  std_logic                                                   := '1';
+        shiftreg     : in  std_logic_vector(ceil_log2(g_wpfb.nof_points) - 1 DOWNTO 0) := (others => '1'); --! Shift register
+        in_sosi_arr  : in  t_fil_sosi_arr_in(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
         fil_sosi_arr : out t_fil_sosi_arr_out(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
         ovflw        : out std_logic_vector(ceil_log2(g_wpfb.nof_points) - 1 DOWNTO 0); --! Ovflw register
         out_sosi_arr : out t_fft_sosi_arr_out(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0)
@@ -367,6 +367,8 @@ architecture str of wbpfb_unit_dev is
 
     constant c_nof_channels : natural := 2 ** g_wpfb.nof_chan;
 
+    constant c_nof_stages : natural := ceil_log2(g_wpfb.nof_points);
+
     constant c_nof_data_per_block  : natural := c_nof_channels * g_wpfb.nof_points;
     constant c_nof_valid_per_block : natural := c_nof_data_per_block / g_wpfb.wb_factor;
 
@@ -397,23 +399,26 @@ architecture str of wbpfb_unit_dev is
                                g_wpfb.stat_data_w,
                                g_wpfb.stat_data_sz,
                                g_wpfb.pipe_reo_in_place);
--- Parameters for the (wideband) poly phase filter. 
-
+    -- Parameters for the (wideband) poly phase filter. 
 
+    type t_ovflw_array is ARRAY (INTEGER RANGE <>) OF std_logic_vector(c_nof_stages - 1 DOWNTO 0);
+    type t_ovflw_array_trans is ARRAY (INTEGER RANGE <>) OF std_logic_vector(g_wpfb.nof_wb_streams - 1 DOWNTO 0);
 
+    signal ovflw_array : t_ovflw_array(g_wpfb.nof_wb_streams - 1 DOWNTO 0);
+    signal trans_ovflw_array : t_ovflw_array_trans(c_nof_stages - 1 DOWNTO 0);
 
     signal fil_in_arr  : t_fil_slv_arr_in(c_nof_complex * g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
-    signal fil_in_val  : std_logic;
+    signal fil_in_val  : std_logic                                                                                := '0';
     signal fil_out_arr : t_fil_slv_arr_out(c_nof_complex * g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => (others => '0'));
-    signal fil_out_val : std_logic;
+    signal fil_out_val : std_logic                                                                                := '0';
 
     signal fft_in_re_arr : t_slv_44_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
     signal fft_in_im_arr : t_slv_44_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
-    signal fft_in_val    : std_logic;
+    signal fft_in_val    : std_logic := '0';
 
-    signal fft_out_re_arr      : t_slv_64_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);--(g_wpfb.fft_out_dat_w-1 downto 0);
-    signal fft_out_im_arr      : t_slv_64_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);--(g_wpfb.fft_out_dat_w-1 downto 0);
-    signal fft_out_val_arr     : std_logic_vector(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
+    signal fft_out_re_arr  : t_slv_64_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0); --(g_wpfb.fft_out_dat_w-1 downto 0);
+    signal fft_out_im_arr  : t_slv_64_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0); --(g_wpfb.fft_out_dat_w-1 downto 0);
+    signal fft_out_val_arr : std_logic_vector(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => '0');
 
     signal fft_out_sosi     : t_fft_sosi_out;
     signal fft_out_sosi_arr : t_fft_sosi_arr_out(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0) := (others => c_fft_sosi_rst_out);
@@ -424,7 +429,7 @@ architecture str of wbpfb_unit_dev is
         in_sosi_arr : t_fil_sosi_arr_in(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0);
     end record;
 
-    signal r, rin : reg_type;
+    signal r, rin : reg_type := (others => (others => c_fil_sosi_rst_in));
 
 begin
 
@@ -469,10 +474,10 @@ begin
     -- Wire fil_out_arr --> fft_in_re_arr, fft_in_im_arr
     wire_fft_in_streams : for S in 0 to g_wpfb.nof_wb_streams - 1 generate
         wire_fft_in_wideband : for P in 0 to g_wpfb.wb_factor - 1 generate
-            assert g_wpfb.fft_in_dat_w=g_wpfb.fil_out_dat_w report "wbpfb: Taking highest bits from filter because FFT is different size than Filter output, no rounding is implemented." severity warning;
-            assert g_wpfb.fft_in_dat_w<=g_wpfb.fil_out_dat_w report "wbpfb: FFT input must be smaller or equal to FILter output" severity failure;
-            fft_in_re_arr(S * g_wpfb.wb_factor + P) <= RESIZE_SVEC(fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex)(g_wpfb.fil_out_dat_w-1 downto g_wpfb.fil_out_dat_w-g_wpfb.fft_in_dat_w),44);
-            fft_in_im_arr(S * g_wpfb.wb_factor + P) <= RESIZE_SVEC(fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex + 1)(g_wpfb.fil_out_dat_w-1 downto g_wpfb.fil_out_dat_w-g_wpfb.fft_in_dat_w),44);
+            assert g_wpfb.fft_in_dat_w = g_wpfb.fil_out_dat_w report "wbpfb: Taking highest bits from filter because FFT is different size than Filter output, no rounding is implemented." severity warning;
+            assert g_wpfb.fft_in_dat_w <= g_wpfb.fil_out_dat_w report "wbpfb: FFT input must be smaller or equal to FILter output" severity failure;
+            fft_in_re_arr(S * g_wpfb.wb_factor + P) <= RESIZE_SVEC(fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex)(g_wpfb.fil_out_dat_w - 1 downto g_wpfb.fil_out_dat_w - g_wpfb.fft_in_dat_w), 44);
+            fft_in_im_arr(S * g_wpfb.wb_factor + P) <= RESIZE_SVEC(fil_out_arr(P * g_wpfb.nof_wb_streams * c_nof_complex + S * c_nof_complex + 1)(g_wpfb.fil_out_dat_w - 1 downto g_wpfb.fil_out_dat_w - g_wpfb.fft_in_dat_w), 44);
         end generate;
     end generate;
 
@@ -538,7 +543,7 @@ begin
                     in_val     => fft_in_val,
                     out_re_arr => fft_out_re_arr((S + 1) * g_wpfb.wb_factor - 1 downto S * g_wpfb.wb_factor),
                     out_im_arr => fft_out_im_arr((S + 1) * g_wpfb.wb_factor - 1 downto S * g_wpfb.wb_factor),
-                    ovflw      => ovflw,
+                    ovflw      => ovflw_array(S)(c_nof_stages - 1 DOWNTO 0),
                     out_val    => fft_out_val_arr(S)
                 );
         end generate;
@@ -549,9 +554,9 @@ begin
     ---------------------------------------------------------------
     gen_pipeline_fft : if g_wpfb.wb_factor = 1 generate
         gen_fft_r2_pipe_streams : for S in 0 to g_wpfb.nof_wb_streams - 1 generate
-        signal temp_re : std_logic_vector(c_fft.out_dat_w-1 downto 0);
-        signal temp_im : std_logic_vector(c_fft.out_dat_w-1 downto 0);
-        
+            signal temp_re : std_logic_vector(c_fft.out_dat_w - 1 downto 0);
+            signal temp_im : std_logic_vector(c_fft.out_dat_w - 1 downto 0);
+
         begin
             u_fft_r2_pipe : entity wb_fft_lib.fft_r2_pipe
                 generic map(
@@ -570,20 +575,30 @@ begin
                     clk      => clk,
                     rst      => rst,
                     shiftreg => shiftreg,
-                    in_re    => fft_in_re_arr(S)(c_fft.in_dat_w-1 downto 0),
-                    in_im    => fft_in_im_arr(S)(c_fft.in_dat_w-1 downto 0),
+                    in_re    => fft_in_re_arr(S)(c_fft.in_dat_w - 1 downto 0),
+                    in_im    => fft_in_im_arr(S)(c_fft.in_dat_w - 1 downto 0),
                     in_val   => fft_in_val,
                     out_re   => temp_re,
                     out_im   => temp_im,
-                    ovflw    => ovflw,
+                    ovflw    => ovflw_array(S)(c_nof_stages - 1 DOWNTO 0),
                     out_val  => fft_out_val_arr(S)
                 );
-            fft_out_re_arr(S) <= RESIZE_SVEC(temp_re,64);
-            fft_out_im_arr(S) <= RESIZE_SVEC(temp_im,64);
+            fft_out_re_arr(S) <= RESIZE_SVEC(temp_re, 64);
+            fft_out_im_arr(S) <= RESIZE_SVEC(temp_im, 64);
         end generate;
 
     end generate;
 
+    ---------------------------------------------------------------
+    -- COLLAPSE OVERFLOW ARRAY
+    ---------------------------------------------------------------
+    gen_collapse_per_stage_ovflw_array : FOR I IN c_nof_stages - 1 DOWNTO 0 GENERATE
+        gen_transpose_ovflw_array : FOR J IN g_wpfb.nof_wb_streams - 1 DOWNTO 0 GENERATE
+            trans_ovflw_array(I)(J) <= ovflw_array(J)(I);
+        END GENERATE;
+        ovflw(I) <= sel_a_b(TO_UINT(trans_ovflw_array(I)) = 0, '0', '1');
+    end generate;
+
     ---------------------------------------------------------------
     -- FFT CONTROL UNIT
     ---------------------------------------------------------------
@@ -596,8 +611,8 @@ begin
     fft_out_sosi.valid <= fft_out_val_arr(0);
 
     wire_fft_out_sosi_arr : for I in 0 to g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 generate
-        fft_out_sosi_arr(I).re    <= fft_out_re_arr(I)(c_fft.out_dat_w-1 downto 0);
-        fft_out_sosi_arr(I).im    <= fft_out_im_arr(I)(c_fft.out_dat_w-1 downto 0);
+        fft_out_sosi_arr(I).re    <= fft_out_re_arr(I)(c_fft.out_dat_w - 1 downto 0);
+        fft_out_sosi_arr(I).im    <= fft_out_im_arr(I)(c_fft.out_dat_w - 1 downto 0);
         fft_out_sosi_arr(I).valid <= fft_out_val_arr(I);
     end generate;
 
@@ -626,4 +641,3 @@ begin
     out_sosi_arr <= pfb_out_sosi_arr;
 
 end str;
-
diff --git a/common_components/common_delay.vhd b/common_components/common_delay.vhd
index bae8c82b..1f6b1383 100644
--- a/common_components/common_delay.vhd
+++ b/common_components/common_delay.vhd
@@ -28,6 +28,8 @@ use IEEE.STD_LOGIC_1164.all;
 use IEEE.numeric_std.all;
 library common_pkg_lib;
 use common_pkg_lib.common_pkg.all;
+library casper_ram_lib;
+use casper_ram_lib.common_ram_pkg.all;
 entity common_delay is
 	generic(
 		g_dat_w : NATURAL := 8;         --! need g_dat_w to be able to use (others=>'') assignments for two dimensional unconstraint vector arrays
@@ -48,7 +50,7 @@ architecture rtl of common_delay is
 	type t_dly_arr is array (0 to g_depth) of STD_LOGIC_VECTOR(g_dat_w - 1 downto 0);
 
 	
-    type t_mem_arr is array (0 to g_depth-2) of STD_LOGIC_VECTOR(g_dat_w - 1 downto 0);
+    type t_mem_arr is array (0 to (((2**ceil_log2(g_depth))-1))) of STD_LOGIC_VECTOR(g_dat_w - 1 downto 0);
     --signal shift_reg : t_dly_arr := (others => (others => '0'));
 begin
 
@@ -74,32 +76,88 @@ begin
 		end process;
 	end generate;
 	gen_regMEM : if g_depth >= 128 generate -- Use a Memory implementation
-	--signal mem_addr_rd : unsigned(ceil_log2(g_depth-1)-1 downto 0) := to_unsigned(g_depth-2,ceil_log2(g_depth-1));
-	signal mem_addr_wr : unsigned(ceil_log2(g_depth-1)-1 downto 0) := to_unsigned(0,ceil_log2(g_depth-1));
-	signal memory : t_mem_arr := (others => (others => '0'));
-    attribute ram_style: string;
-    attribute ram_style of memory: signal is "block";
-	signal out_datmem  : STD_LOGIC_VECTOR(g_dat_w - 1 downto 0) := (others => '0'); --! Output value
+	signal mem_addr_wr 		: unsigned(ceil_log2(g_depth-1)-1 downto 0) := to_unsigned(g_depth-5,ceil_log2(g_depth));
+	signal mem_addr_rd 		: unsigned(ceil_log2(g_depth-1)-1 downto 0) := to_unsigned(0,ceil_log2(g_depth));
+	signal out_datmem  		: STD_LOGIC_VECTOR(g_dat_w - 1 downto 0) := (others => '0'); --! Output value
+	signal out_dat_p 		: STD_LOGIC_VECTOR(g_dat_w - 1 downto 0) := (others => '0'); --! Output value
+	signal in_dat_d1		: STD_LOGIC_VECTOR(g_dat_w - 1 downto 0) := (others => '0'); --! Output value
+	signal in_dat_d2		: STD_LOGIC_VECTOR(g_dat_w - 1 downto 0) := (others => '0'); --! Output value
+	attribute DONT_TOUCH : string;
+	attribute KEEP : string;
+	attribute KEEP of out_dat_p : signal is "TRUE";  -- try to prevent this signal from being absorbed into the block
+	attribute DONT_TOUCH of out_dat_p : signal is "TRUE"; -- try to prevent this signal from being absorbed into the block
+
+
+
     begin
-        out_dat <= out_datmem;
-        --assert out_datmem = shift_reg(g_depth) report "non matching data" severity failure;
-		p_clk : process(clk)
+        --out_dat <= out_datmem;
+		--shift_reg(0) <= in_dat;
+		--out_shift    <= shift_reg(g_depth);
+        --assert out_datmem = shift_reg(g_depth-2) report "non matching data" severity failure;
+		--p_clk : process(clk)
+		--begin
+		--	if rising_edge(clk) then
+		--		if in_val = '1' then
+		--		    out_datmem <= memory(to_integer(mem_addr_rd));
+		--			memory(to_integer(mem_addr_wr)) <= in_dat;
+		--			--shift_reg(1 to g_depth) <= shift_reg(0 to g_depth - 1);
+		--		end if;
+		--	end if;
+		--end process;
+		RamInst : entity casper_ram_lib.tech_memory_ram_cr_cw
+			generic map(
+				g_adr_w         => ceil_log2(g_depth-1),
+				g_dat_w         => g_dat_w,
+				g_nof_words     => 2**ceil_log2(g_depth),
+				g_rd_latency    => 1
+				--g_init_file     => g_init_file,
+				--g_ram_primitive => g_ram_primitive
+			)
+			port map(
+				data      => in_dat_d2,
+				rdaddress => std_logic_vector(mem_addr_rd),
+				rdclock   => clk,
+				rdclocken => in_val,
+				wraddress => std_logic_vector(mem_addr_wr),
+				wrclock   => clk,
+				wrclocken => in_val,
+				wren      => in_val,
+				q         => out_datmem
+			);
+		
+		--RamInst : entity casper_ram_lib.common_ram_r_w
+		--	generic map(
+		--		g_ram            => c_mem_settings,
+		--		--g_init_file      => g_init_file,
+		--		g_true_dual_port => false
+		--		--g_ram_primitive  => g_ram_primitive
+		--	)
+		--	port map(
+		--		clk    => clk,
+		--		clken  => in_val,
+		--		wr_en  => in_val,
+		--		wr_adr => std_logic_vector(mem_addr_wr),
+		--		wr_dat => in_dat,
+		--		rd_en  => in_val,
+		--		rd_adr => std_logic_vector(mem_addr_rd),
+		--		rd_dat => out_datmem,
+		--		rd_val => open
+		--	);
+		
+		reg_data : process (clk)
 		begin
 			if rising_edge(clk) then
-			    
-				if in_val = '1' then
-				    out_datmem <= memory(to_integer(mem_addr_wr));
-					memory(to_integer(mem_addr_wr)) <= in_dat;
-					--mem_addr_rd <= mem_addr_wr;
-					if mem_addr_wr=(g_depth-2) then
-					   mem_addr_wr <= to_unsigned(0,mem_addr_wr'length);
-					else
-					   mem_addr_wr <= mem_addr_wr + 1;
-					end if;
-
-					--shift_reg(1 to g_depth) <= shift_reg(0 to g_depth - 1);
+				if in_val='1' then
+					in_dat_d1 <= in_dat;
+					in_dat_d2 <= in_dat_d1;
+					out_dat_p <= out_datmem;
+					out_dat <= out_dat_p;
+					mem_addr_wr <= mem_addr_wr + 1;
+					mem_addr_rd <= mem_addr_rd + 1;
 				end if;
 			end if;
 		end process;
+
+					
 	end generate;
 end rtl;
diff --git a/docs/source/accumulators.rst b/docs/source/accumulators.rst
index 178dfcb8..f8ad84d8 100644
--- a/docs/source/accumulators.rst
+++ b/docs/source/accumulators.rst
@@ -50,6 +50,43 @@ Parameters
 | Output bin pt  | Natural | 0        | Output binary point for dout type.                             |
 +----------------+---------+----------+----------------------------------------------------------------+
 
+================
+Simple Bram Vacc
+================
+This simple vector accumulator is based on a shift register. It outputs its previous accumulated vector after a new_acc pulse is received.
+
+-----
+Ports
+-----
++----------------+--------------------------+---------------------------+----------------------------------------------------------------+
+| Signal         | Type                     | Size                      | Description                                                    |
++================+==========================+===========================+================================================================+
+| new_acc        | std_logic                | 1                         | This port accepts the pulse signal indicating the start of a   |
+|                |                          |                           | vector for accumulation.                                       |
++----------------+--------------------------+---------------------------+----------------------------------------------------------------+
+| din            | std_logic_vector         | any                       | The input into which the vector is supplied one element at a   |
+|                |                          |                           | time.                                                          |  
++----------------+--------------------------+---------------------------+----------------------------------------------------------------+
+| dout           | std_logic_vector         | any                       | The accumulated vector indices out.                            |  
++----------------+--------------------------+---------------------------+----------------------------------------------------------------+
+| valid          | std_logic                | 1                         | Signal indicates valid dout.                                   |  
++----------------+--------------------------+---------------------------+----------------------------------------------------------------+
+
+----------
+Parameters
+----------
++----------------+---------+----------+----------------------------------------------------------------+
+| Generic        | Type    | Value    | Description                                                    |
++================+=========+==========+================================================================+
+| Vector length  | Natural | 10       | The length of the vector to accumulate.                        |
++----------------+---------+----------+----------------------------------------------------------------+
+| Output sign    | String  | "SIGNED" | Value options of "SIGNED" and "UNSIGNED" for dout type.        |
++----------------+---------+----------+----------------------------------------------------------------+
+| Output bitwidth| Natural | 18       | Output bitwidth for dout type.                                 |
++----------------+---------+----------+----------------------------------------------------------------+
+| Output bin pt  | Natural | 0        | Output binary point for dout type.                             |
++----------------+---------+----------+----------------------------------------------------------------+
+
 ================
 DSP48e BRAM VACC
 ================
diff --git a/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr b/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr
index 60add3b4..d3a257fc 100644
--- a/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr
+++ b/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr
@@ -1,532 +1,539 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2020.1 (64-bit)              -->
-<!--                                                         -->
-<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
-
-<Project Version="7" Minor="49" Path="C:/Users/mybur/Repos/CASPER/dspdevel_designs/casper_dspdevel/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr">
-  <DefaultLaunch Dir="$PRUNDIR"/>
-  <Configuration>
-    <Option Name="Id" Val="8f3443920199435eaca42eb69f4c3ed1"/>
-    <Option Name="Part" Val="xc7z020clg400-1"/>
-    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
-    <Option Name="CompiledLibDirXSim" Val=""/>
-    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
-    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
-    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
-    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
-    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
-    <Option Name="SimulatorInstallDirModelSim" Val=""/>
-    <Option Name="SimulatorInstallDirQuesta" Val=""/>
-    <Option Name="SimulatorInstallDirIES" Val=""/>
-    <Option Name="SimulatorInstallDirXcelium" Val=""/>
-    <Option Name="SimulatorInstallDirVCS" Val=""/>
-    <Option Name="SimulatorInstallDirRiviera" Val=""/>
-    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
-    <Option Name="TargetLanguage" Val="VHDL"/>
-    <Option Name="BoardPart" Val=""/>
-    <Option Name="ActiveSimSet" Val="sim_1"/>
-    <Option Name="DefaultLib" Val="xil_defaultlib"/>
-    <Option Name="ProjectType" Val="Default"/>
-    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
-    <Option Name="IPCachePermission" Val="read"/>
-    <Option Name="IPCachePermission" Val="write"/>
-    <Option Name="EnableCoreContainer" Val="FALSE"/>
-    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
-    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
-    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
-    <Option Name="UseIPStaticLibs" Val="0"/>
-    <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="WTXSimLaunchSim" Val="132"/>
-    <Option Name="WTModelSimLaunchSim" Val="0"/>
-    <Option Name="WTQuestaLaunchSim" Val="0"/>
-    <Option Name="WTIesLaunchSim" Val="0"/>
-    <Option Name="WTVcsLaunchSim" Val="0"/>
-    <Option Name="WTRivieraLaunchSim" Val="0"/>
-    <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="0"/>
-    <Option Name="WTModelSimExportSim" Val="0"/>
-    <Option Name="WTQuestaExportSim" Val="0"/>
-    <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="0"/>
-    <Option Name="WTRivieraExportSim" Val="0"/>
-    <Option Name="WTActivehdlExportSim" Val="0"/>
-    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
-    <Option Name="XSimRadix" Val="hex"/>
-    <Option Name="XSimTimeUnit" Val="ns"/>
-    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
-    <Option Name="XSimTraceLimit" Val="65536"/>
-    <Option Name="SimTypes" Val="rtl"/>
-    <Option Name="SimTypes" Val="bfm"/>
-    <Option Name="SimTypes" Val="tlm"/>
-    <Option Name="SimTypes" Val="tlm_dpi"/>
-    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
-    <Option Name="DcpsUptoDate" Val="TRUE"/>
-  </Configuration>
-  <FileSets Version="1" Minor="31">
-    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
-      <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../../common_components/common_bit_delay.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_components_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/fixed_float_types_c.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/fixed_pkg_c.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/common_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../technology/technology_select_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="technology_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_components/common_pipeline.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_components_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_components/common_pipeline_sl.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_components_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_multiplier/tech_mult_component.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_multiplier/tech_agilex_versal_cmult.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_multiplier/tech_complex_mult.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_multiplier/common_complex_mult.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_counter/common_counter.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_counter_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_components/common_delay.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_components_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_ram_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/tech_memory_component_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/tech_memory_ram_crw_crw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/tech_memory_ram_cr_cw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_ram_crw_crw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_crw_crw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_rw_rw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_r_w.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_requantize/common_round.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_requantize_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_requantize/common_resize.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_requantize_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_requantize/common_requantize.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_requantize_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/tech_memory_rom_r_r.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/tech_memory_rom_r.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_ram/common_rom_r_r.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/common_str_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/mult/ip_cmult_rtl_3dsp.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/mult/ip_cmult_rtl_4dsp.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_multiplier_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_rom_r.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="ip_xpm_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_rom_r_r.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="ip_xpm_ram_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoBF.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoBFStage.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoOrder.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoSDFPkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../twiddlesPkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoWeights.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoWMul.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../casper_requantize/r_shift_requantize.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="casper_requantize_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoSDFStage.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../rTwoSDF.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/float_pkg_c.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="rTwoSDF"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
-      <Filter Type="Constrs"/>
-      <Config>
-        <Option Name="ConstrsType" Val="XDC"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
-      <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../../common_pkg/common_lfsr_sequences_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../../common_pkg/tb_common_pkg.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="common_pkg_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../tb_rTwoSDF.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../tb_tb_rTwoSDF.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PPRDIR/../tb_rTwoOrder.vhd">
-        <FileInfo>
-          <Attr Name="Library" Val="r2sdf_fft_lib"/>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <Config>
-        <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="tb_tb_rTwoSDF"/>
-        <Option Name="TopLib" Val="r2sdf_fft_lib"/>
-        <Option Name="TransportPathDelay" Val="0"/>
-        <Option Name="TransportIntDelay" Val="0"/>
-        <Option Name="SelectedSimModel" Val="rtl"/>
-        <Option Name="PamDesignTestbench" Val=""/>
-        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
-        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
-        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
-        <Option Name="SrcSet" Val="sources_1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
-      <Filter Type="Utils"/>
-      <Config>
-        <Option Name="TopAutoSet" Val="TRUE"/>
-      </Config>
-    </FileSet>
-  </FileSets>
-  <Simulators>
-    <Simulator Name="XSim">
-      <Option Name="Description" Val="Vivado Simulator"/>
-      <Option Name="CompiledLib" Val="0"/>
-    </Simulator>
-    <Simulator Name="ModelSim">
-      <Option Name="Description" Val="ModelSim Simulator"/>
-    </Simulator>
-    <Simulator Name="Questa">
-      <Option Name="Description" Val="Questa Advanced Simulator"/>
-    </Simulator>
-    <Simulator Name="Riviera">
-      <Option Name="Description" Val="Riviera-PRO Simulator"/>
-    </Simulator>
-    <Simulator Name="ActiveHDL">
-      <Option Name="Description" Val="Active-HDL Simulator"/>
-    </Simulator>
-  </Simulators>
-  <Runs Version="1" Minor="11">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
-        <Step Id="init_design"/>
-        <Step Id="opt_design"/>
-        <Step Id="power_opt_design"/>
-        <Step Id="place_design"/>
-        <Step Id="post_place_power_opt_design"/>
-        <Step Id="phys_opt_design"/>
-        <Step Id="route_design"/>
-        <Step Id="post_route_phys_opt_design"/>
-        <Step Id="write_bitstream"/>
-      </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-  </Runs>
-  <Board/>
-  <DashboardSummary Version="1" Minor="0">
-    <Dashboards>
-      <Dashboard Name="default_dashboard">
-        <Gadgets>
-          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
-          </Gadget>
-          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
-          </Gadget>
-          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
-          </Gadget>
-          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
-          </Gadget>
-          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
-            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
-            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
-          </Gadget>
-          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
-            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
-          </Gadget>
-        </Gadgets>
-      </Dashboard>
-      <CurrentDashboard>default_dashboard</CurrentDashboard>
-    </Dashboards>
-  </DashboardSummary>
-</Project>
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.1 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="49" Path="/export/home/creon/mschiller_ngvla_project/casper_dspdevel/r2sdf_fft/r2SDF_FFT_proj/r2SDF_FFT_proj.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="8f3443920199435eaca42eb69f4c3ed1"/>
+    <Option Name="Part" Val="xc7z020clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="UseIPStaticLibs" Val="0"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="92"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../common_components/common_bit_delay.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_components_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/fixed_float_types_c.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/fixed_pkg_c.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/common_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../technology/technology_select_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="technology_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_components/common_pipeline.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_components_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_components/common_pipeline_sl.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_components_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_multiplier/tech_mult_component.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_multiplier/tech_agilex_versal_cmult.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_multiplier/tech_complex_mult.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_multiplier/common_complex_mult.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_counter/common_counter.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_counter_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_ram_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/tech_memory_component_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/tech_memory_ram_cr_cw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_components/common_delay.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_components_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/tech_memory_ram_crw_crw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_ram_crw_crw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_crw_crw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_rw_rw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_paged_ram_r_w.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_requantize/common_round.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_requantize_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_requantize/common_resize.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_requantize_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_requantize/common_requantize.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_requantize_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/tech_memory_rom_r_r.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/tech_memory_rom_r.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_ram/common_rom_r_r.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/common_str_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/mult/ip_cmult_rtl_3dsp.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/mult/ip_cmult_rtl_4dsp.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_multiplier_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_rom_r.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="ip_xpm_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../ip_xpm/ram/ip_xpm_rom_r_r.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="ip_xpm_ram_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoBF.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoBFStage.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoOrder.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoSDFPkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../twiddlesPkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoWeights.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoWMul.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../casper_requantize/r_shift_requantize.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="casper_requantize_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoSDFStage.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rTwoSDF.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/float_pkg_c.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="rTwoSDF"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../common_pkg/common_lfsr_sequences_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../common_pkg/tb_common_pkg.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="common_pkg_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../tb_rTwoSDF.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../tb_tb_rTwoSDF.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../tb_rTwoOrder.vhd">
+        <FileInfo>
+          <Attr Name="Library" Val="r2sdf_fft_lib"/>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tb_tb_rTwoSDF"/>
+        <Option Name="TopLib" Val="r2sdf_fft_lib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="11">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
\ No newline at end of file
diff --git a/wrappers/simulink/ACCUMULATORS.slx b/wrappers/simulink/ACCUMULATORS.slx
index 99dfa302..2716157a 100644
Binary files a/wrappers/simulink/ACCUMULATORS.slx and b/wrappers/simulink/ACCUMULATORS.slx differ
diff --git a/wrappers/simulink/bus_expand_arbitrary_config.m b/wrappers/simulink/bus_expand_arbitrary_config.m
index 536e546e..4fd33402 100644
--- a/wrappers/simulink/bus_expand_arbitrary_config.m
+++ b/wrappers/simulink/bus_expand_arbitrary_config.m
@@ -18,7 +18,7 @@ function bus_expand_arbitrary_config(this_block)
   types = strrep(types, '"', '');
   types = str2double(regexp(types,'\d+','match'));
 
-  if length(division_bit_widths) != radix_points || length(division_bit_widths) != length(types)
+  if length(division_bit_widths) ~= length(radix_points) || length(division_bit_widths) ~= length(types)
     this_block.setError(sprintf('Inconsistent number of values given.'));
   end
 
@@ -42,15 +42,15 @@ function bus_expand_arbitrary_config(this_block)
     end
     
     for o_data_i = 1:length(division_bit_widths)
-      port_name = sprintf('o_data_%d',o_data_i)
+      port_name = sprintf('o_data_%d',o_data_i);
       o_data_port = this_block.port(port_name);
       o_data_port.setWidth(division_bit_widths(o_data_i));
       if types(o_data_i) == 0 % UFix
         str_o_dat_type = sprintf('UFix_%d_%d', division_bit_widths(o_data_i), radix_points(o_data_i));
         o_data_port.setType(str_o_dat_type);
       elseif types(o_data_i) == 1 % Fix
-        str_o_dat_type = sprintf('Fix_%d_%d', division_bit_widths(o_data_i), radix_points(o_data_i));
-        o_data_port.setType(str_o_dat_type);
+        str_o_dat_type = sprintf('Fix_%d_%d', division_bit_widths(o_data_i), radix_points(o_data_i))
+        o_data_port.setType(str_o_dat_type)
       elseif types(o_data_i) == 2 % bool
         if (o_data_port.width ~= 1)
           this_block.setError(sprintf('Output port "%s" must have width 1 to be bool.', port_name));
diff --git a/wrappers/simulink/bus_expand_blk.slx b/wrappers/simulink/bus_expand_blk.slx
index 8cc52ba9..79cc3236 100644
Binary files a/wrappers/simulink/bus_expand_blk.slx and b/wrappers/simulink/bus_expand_blk.slx differ
diff --git a/wrappers/simulink/casper_wb_fft_config.m b/wrappers/simulink/casper_wb_fft_config.m
index 05a747e6..c22f11ab 100644
--- a/wrappers/simulink/casper_wb_fft_config.m
+++ b/wrappers/simulink/casper_wb_fft_config.m
@@ -100,15 +100,15 @@ function casper_wb_fft_config(this_block)
 %inport declarations
 this_block.addSimulinkInport('rst');
 in_rst_port = this_block.port('rst');
-in_rst_port.setType('Ufix_1_0');
+in_rst_port.setType('Bool');
 in_rst_port.useHDLVector(false);
 this_block.addSimulinkInport('in_sync');
 in_sync_port = this_block.port('in_sync');
-in_sync_port.setType('Ufix_1_0');
+in_sync_port.setType('Bool');
 in_sync_port.useHDLVector(false);
 this_block.addSimulinkInport('in_valid');
 in_valid_port = this_block.port('in_valid');
-in_valid_port.setType('Ufix_1_0');
+in_valid_port.setType('Bool');
 in_valid_port.useHDLVector(false);
 this_block.addSimulinkInport('in_shiftreg');
 in_shiftreg_port = this_block.port('in_shiftreg');
@@ -123,12 +123,12 @@ function casper_wb_fft_config(this_block)
 
   this_block.addSimulinkInport('in_sop');
   in_sop_port = this_block.port('in_sop');
-  in_sop_port.setType('Ufix_1_0');
+  in_sop_port.setType('Bool');
   in_sop_port.useHDLVector(false);
   
   this_block.addSimulinkInport('in_eop');
   in_eop_port = this_block.port('in_eop');
-  in_eop_port.setType('Ufix_1_0');
+  in_eop_port.setType('Bool');
   in_eop_port.useHDLVector(false);
   
   this_block.addSimulinkInport('in_empty');
@@ -159,12 +159,12 @@ function casper_wb_fft_config(this_block)
   
   this_block.addSimulinkOutport('out_sync');
   out_sync_port = this_block.port('out_sync');
-  out_sync_port.setType('Ufix_1_0');
+  out_sync_port.setType('Bool');
   out_sync_port.useHDLVector(false);
   
   this_block.addSimulinkOutport('out_valid');
   out_valid_port = this_block.port('out_valid');
-  out_valid_port.setType('Ufix_1_0');
+  out_valid_port.setType('Bool');
   out_valid_port.useHDLVector(false);
   
   this_block.addSimulinkOutport('out_ovflw');
@@ -178,12 +178,12 @@ function casper_wb_fft_config(this_block)
     
     this_block.addSimulinkOutport('out_sop');
     out_sop_port = this_block.port('out_sop');
-    out_sop_port.setType('Ufix_1_0');
+    out_sop_port.setType('Bool');
     out_sop_port.useHDLVector(false);
     
     this_block.addSimulinkOutport('out_eop');
     out_eop_port = this_block.port('out_eop');
-    out_eop_port.setType('Ufix_1_0');
+    out_eop_port.setType('Bool');
     out_eop_port.useHDLVector(false);
     
     this_block.addSimulinkOutport('out_empty');
diff --git a/wrappers/simulink/simple_bram_vacc_blk.slx b/wrappers/simulink/simple_bram_vacc_blk.slx
new file mode 100644
index 00000000..6ec8afdb
Binary files /dev/null and b/wrappers/simulink/simple_bram_vacc_blk.slx differ
diff --git a/wrappers/simulink/simple_bram_vacc_config.m b/wrappers/simulink/simple_bram_vacc_config.m
new file mode 100644
index 00000000..203575b3
--- /dev/null
+++ b/wrappers/simulink/simple_bram_vacc_config.m
@@ -0,0 +1,122 @@
+
+function simple_bram_vacc_config(this_block)
+
+  this_block.setTopLevelLanguage('VHDL');
+
+  this_block.setEntityName('simple_bram_vacc');
+  filepath = fileparts(which('simple_bram_vacc_config'));
+
+  function boolval =  checkbox2bool(bxval)
+    if strcmp(bxval, 'on')
+     boolval= true;
+    elseif strcmp(bxval, 'off')
+     boolval= false;
+    end 
+  end
+  function strboolval = bool2sign(bval)
+    if bval
+        strboolval = '"SIGNED"';
+    elseif ~bval
+        strboolval = '"UNSIGNED"';
+    end
+  end
+
+  simple_bram_vacc_blk = this_block.blockName;
+  simple_bram_vacc_blk_parent = get_param(simple_bram_vacc_blk,'Parent');
+  
+  % Extract block parameters
+  vector_length = get_param(simple_bram_vacc_blk_parent,'vector_length');
+  is_signed = checkbox2bool(get_param(simple_bram_vacc_blk_parent,'output_sign'));
+  output_bit_w = get_param(simple_bram_vacc_blk_parent,'output_bit_w');
+  output_bin_pt = get_param(simple_bram_vacc_blk_parent,'output_bin_pt');
+
+  this_block.addSimulinkInport('new_acc');
+  new_acc_port = this_block.port('new_acc');
+
+  this_block.addSimulinkInport('din');
+
+  this_block.addSimulinkOutport('dout');
+  dout_port = this_block.port('dout');
+  if is_signed
+    dout_port.setType(sprintf('Fix_%s_%s',output_bit_w,output_bin_pt))
+  else
+    dout_port.setType(sprintf('Ufix_%s_%s',output_bit_w,output_bin_pt))
+  end
+
+  this_block.addSimulinkOutport('valid');
+  valid_port = this_block.port('valid');
+  valid_port.setType('Ufix_1_0');
+  valid_port.useHDLVector(false);
+
+  % -----------------------------
+  if (this_block.inputTypesKnown)
+    % do input type checking, dynamic output type and generic setup in this code block.
+    if (new_acc_port.width ~= 1)
+      this_block.setError('Input data type for port "new_acc" must have width=1.');
+    end
+    new_acc_port.setType('Ufix_1_0');
+    new_acc_port.useHDLVector(false);
+  end  % if(inputTypesKnown)
+  % -----------------------------
+
+  % -----------------------------
+   if (this_block.inputRatesKnown)
+     setup_as_single_rate(this_block,'clk','ce')
+   end  % if(inputRatesKnown)
+  % -----------------------------
+
+  uniqueInputRates = unique(this_block.getInputRates);
+
+  is_signed_str = bool2sign(is_signed);
+  this_block.addGeneric('g_vector_length','NATURAL',vector_length);
+  this_block.addGeneric('g_output_type','STRING',is_signed_str);
+  this_block.addGeneric('g_bit_w','NATURAL',output_bit_w);
+  
+  this_block.addFileToLibrary([filepath '/../../casper_accumulators/simple_bram_vacc.vhd'],'xil_defaultlib');
+  this_block.addFileToLibrary([filepath '/../../common_pkg/common_pkg.vhd'],'common_pkg_lib');
+  this_block.addFileToLibrary([filepath '/../../common_components/common_delay.vhd'],'common_components_lib');
+  this_block.addFileToLibrary([filepath '/../../misc/edge_detect.vhd'],'casper_misc_lib');
+  this_block.addFileToLibrary([filepath '/../../misc/pulse_ext.vhd'],'casper_misc_lib');
+  this_block.addFileToLibrary([filepath '/../../common_components/common_pipeline.vhd'],'common_components_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_adder/common_add_sub.vhd'],'casper_adder_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/common_ram_pkg.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../technology/technology_select_pkg.vhd'],'technology_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/tech_memory_component_pkg.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/tech_memory_ram_crw_crw.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/tech_memory_ram_cr_cw.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/common_ram_crw_crw.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/common_ram_rw_rw.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_ram/common_ram_r_w.vhd'],'casper_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../casper_delay/delay_bram.vhd'],'casper_delay_lib');
+  this_block.addFileToLibrary([filepath '/../../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd'],'ip_xpm_ram_lib');
+  this_block.addFileToLibrary([filepath '/../../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd'],'ip_xpm_ram_lib');
+return;
+end
+
+
+% ------------------------------------------------------------
+
+function setup_as_single_rate(block,clkname,cename) 
+  inputRates = block.inputRates; 
+  uniqueInputRates = unique(inputRates); 
+  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
+    block.addError('The inputs to this block cannot all be constant.'); 
+    return; 
+  end 
+  if (uniqueInputRates(end) == Inf) 
+     hasConstantInput = true; 
+     uniqueInputRates = uniqueInputRates(1:end-1); 
+  end 
+  if (length(uniqueInputRates) ~= 1) 
+    block.addError('The inputs to this block must run at a single rate.'); 
+    return; 
+  end 
+  theInputRate = uniqueInputRates(1); 
+  for i = 1:block.numSimulinkOutports 
+     block.outport(i).setRate(theInputRate); 
+  end 
+  block.addClkCEPair(clkname,cename,theInputRate); 
+  return; 
+end
+% ------------------------------------------------------------
+
diff --git a/wrappers/simulink/top_wbpfb_code_gen.m b/wrappers/simulink/top_wbpfb_code_gen.m
index 36c95e16..f0953e70 100644
--- a/wrappers/simulink/top_wbpfb_code_gen.m
+++ b/wrappers/simulink/top_wbpfb_code_gen.m
@@ -172,8 +172,8 @@
                                  "g_coef_dat_w, g_use_reorder, g_use_fft_shift, g_use_separate, g_fft_in_dat_w, g_fft_out_dat_w, g_fft_out_gain_w, g_stage_dat_w,"
                                  "g_twiddle_dat_w, g_max_addr_w, g_guard_w, g_guard_enable, g_pipe_reo_in_place, 56, 2, 800000, c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);"
     "signal in_fil_sosi_arr  : t_fil_sosi_arr_in(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
-    "signal out_fil_sosi_arr : t_fil_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
-    "signal out_fft_sosi_arr : t_fft_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
+    "signal out_fil_sosi_arr : t_fil_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0) := (others => c_fil_sosi_rst_out);"
+    "signal out_fft_sosi_arr : t_fft_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0) := (others => c_fft_sosi_rst_out);"
     "begin"
     " wbpfb_unit : entity wpfb_lib.wbpfb_unit_dev"
     " generic map ("
@@ -210,26 +210,42 @@
     "in_fil_sosi_arr(j).channel <= in_channel;"
     "in_fil_sosi_arr(j).err <= in_err;"
     "end generate;"
-    "otheroutprtmap: for k in 0 to g_wb_factor-1 generate"
-    "out_sync <= out_fft_sosi_arr(k).sync;"
-    "out_bsn <= out_fft_sosi_arr(k).bsn;"
-    "out_valid <= out_fft_sosi_arr(k).valid ;"
-    "out_sop <= out_fft_sosi_arr(k).sop;"
-    "out_eop <= out_fft_sosi_arr(k).eop;"
-    "out_empty <= out_fft_sosi_arr(k).empty;"
-    "out_channel <= out_fft_sosi_arr(k).channel;"
-    "out_err <= out_fft_sosi_arr(k).err;"
-    "end generate;"
-    "otherfilprtmap: for k in 0 to g_wb_factor-1 generate"
-    "fil_sync <= out_fil_sosi_arr(k).sync;"
-    "fil_bsn <= out_fil_sosi_arr(k).bsn;"
-    "fil_valid <= out_fil_sosi_arr(k).valid ;"
-    "fil_sop <= out_fil_sosi_arr(k).sop;"
-    "fil_eop <= out_fil_sosi_arr(k).eop;"
-    "fil_empty <= out_fil_sosi_arr(k).empty;"
-    "fil_channel <= out_fil_sosi_arr(k).channel;"
-    "fil_err <= out_fil_sosi_arr(k).err;"
-    "end generate;"
+    "out_sync <= out_fft_sosi_arr(0).sync;"
+    "out_bsn <= out_fft_sosi_arr(0).bsn;"
+    "out_valid <= out_fft_sosi_arr(0).valid ;"
+    "out_sop <= out_fft_sosi_arr(0).sop;"
+    "out_eop <= out_fft_sosi_arr(0).eop;"
+    "out_empty <= out_fft_sosi_arr(0).empty;"
+    "out_channel <= out_fft_sosi_arr(0).channel;"
+    "out_err <= out_fft_sosi_arr(0).err;"
+%     "otheroutprtmap: for k in 0 to g_wb_factor-1 generate"
+%     "out_sync <= out_fft_sosi_arr(k).sync;"
+%     "out_bsn <= out_fft_sosi_arr(k).bsn;"
+%     "out_valid <= out_fft_sosi_arr(k).valid ;"
+%     "out_sop <= out_fft_sosi_arr(k).sop;"
+%     "out_eop <= out_fft_sosi_arr(k).eop;"
+%     "out_empty <= out_fft_sosi_arr(k).empty;"
+%     "out_channel <= out_fft_sosi_arr(k).channel;"
+%     "out_err <= out_fft_sosi_arr(k).err;"
+%     "end generate;"
+    "fil_sync <= out_fil_sosi_arr(0).sync;"
+    "fil_bsn <= out_fil_sosi_arr(0).bsn;"
+    "fil_valid <= out_fil_sosi_arr(0).valid ;"
+    "fil_sop <= out_fil_sosi_arr(0).sop;"
+    "fil_eop <= out_fil_sosi_arr(0).eop;"
+    "fil_empty <= out_fil_sosi_arr(0).empty;"
+    "fil_channel <= out_fil_sosi_arr(0).channel;"
+    "fil_err <= out_fil_sosi_arr(0).err;"
+%     "otherfilprtmap: for k in 0 to g_wb_factor-1 generate"
+%     "fil_sync <= out_fil_sosi_arr(k).sync;"
+%     "fil_bsn <= out_fil_sosi_arr(k).bsn;"
+%     "fil_valid <= out_fil_sosi_arr(k).valid ;"
+%     "fil_sop <= out_fil_sosi_arr(k).sop;"
+%     "fil_eop <= out_fil_sosi_arr(k).eop;"
+%     "fil_empty <= out_fil_sosi_arr(k).empty;"
+%     "fil_channel <= out_fil_sosi_arr(k).channel;"
+%     "fil_err <= out_fil_sosi_arr(k).err;"
+%     "end generate;"
 	];
     
     lnsafterarchopen_w_o_xtradat = [");"
@@ -240,8 +256,8 @@
                              "g_coef_dat_w, g_use_reorder, g_use_fft_shift, g_use_separate, g_fft_in_dat_w, g_fft_out_dat_w, g_fft_out_gain_w, g_stage_dat_w,"
                              "g_twiddle_dat_w, g_max_addr_w,g_guard_w, g_guard_enable, g_pipe_reo_in_place, 56, 2, 800000, c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);"
     "signal in_fil_sosi_arr  : t_fil_sosi_arr_in(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
-    "signal out_fil_sosi_arr : t_fil_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
-    "signal out_fft_sosi_arr : t_fft_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0);"
+    "signal out_fil_sosi_arr : t_fil_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0) := (others => c_fil_sosi_rst_out);"
+    "signal out_fft_sosi_arr : t_fft_sosi_arr_out(g_wb_factor*g_nof_wb_streams - 1 downto 0) := (others => c_fft_sosi_rst_out);"
     "begin"
     " wbpfb_unit : entity wpfb_lib.wbpfb_unit_dev"
     " generic map ("
@@ -272,14 +288,18 @@
     "in_fil_sosi_arr(j).sync <= in_sync;"
     "in_fil_sosi_arr(j).valid <= in_valid;"
     "end generate;"
-    "otheroutprtmap: for k in 0 to g_wb_factor-1 generate"
-    "out_sync <= out_fft_sosi_arr(k).sync;"
-    "out_valid <= out_fft_sosi_arr(k).valid;"
-    "end generate;"
-    "otherfilprtmap: for k in 0 to g_wb_factor-1 generate"
-    "fil_sync <= out_fil_sosi_arr(k).sync;"
-    "fil_valid <= out_fil_sosi_arr(k).valid;"
-    "end generate;"
+    "out_sync <= out_fft_sosi_arr(0).sync;"
+    "out_valid <= out_fft_sosi_arr(0).valid;"
+%     "otheroutprtmap: for k in 0 to g_wb_factor-1 generate"
+%     "out_sync <= out_fft_sosi_arr(k).sync;"
+%     "out_valid <= out_fft_sosi_arr(k).valid;"
+%     "end generate;"
+    "fil_sync <= out_fil_sosi_arr(0).sync;"
+    "fil_valid <= out_fil_sosi_arr(0).valid;"
+%     "otherfilprtmap: for k in 0 to g_wb_factor-1 generate"
+%     "fil_sync <= out_fil_sosi_arr(k).sync;"
+%     "fil_valid <= out_fil_sosi_arr(k).valid;"
+%     "end generate;"
 	];
     %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     %create an array of lines from architecture opening till where 
@@ -362,10 +382,8 @@
             i=i+1;
             if (j ~= wbfctr-1 | k ~= nof_wb_streams-1)
                 chararr(i,1)=sprintf(outrechar,k,j);
-                fprintf("Not finished, wb: %d, str: %d",j,k);
             else
                 chararr(i,1)=sprintf(strip(outrechar,';'),k,j);
-                fprintf("Finished, wb: %d, str: %d",j,k);
             end
             i=i+1;
         end
@@ -381,9 +399,9 @@
     omap_re_c = "out_re_str%d_wb%d <= out_fft_sosi_arr(%d).re;";
     omap_im_c = "out_im_str%d_wb%d <= out_fft_sosi_arr(%d).im;";
     l = 1;
+    arr_index = 0;
     for n=0:1:nof_wb_streams-1
         for m=0:1:wbfctr-1
-            arr_index = (n+1)*m;
             achararr(l,1)=sprintf(imap_re_c,arr_index,n,m);
             l=l+1;
             achararr(l,1)=sprintf(imap_im_c,arr_index,n,m);
@@ -396,6 +414,7 @@
             l=l+1;
             achararr(l,1)=sprintf(omap_im_c,n,m,arr_index);
             l=l+1;
+            arr_index = arr_index + 1;
         end
     end
 end
diff --git a/wrappers/simulink/wbpfb_unit_top_config.m b/wrappers/simulink/wbpfb_unit_top_config.m
index 7f7cd961..fcaa4d9e 100644
--- a/wrappers/simulink/wbpfb_unit_top_config.m
+++ b/wrappers/simulink/wbpfb_unit_top_config.m
@@ -115,15 +115,15 @@ function wbpfb_unit_top_config(this_block)
 %inport declarations
 this_block.addSimulinkInport('rst');
 in_rst_port = this_block.port('rst');
-in_rst_port.setType('Ufix_1_0');
+in_rst_port.setType('Bool');
 in_rst_port.useHDLVector(false);
 this_block.addSimulinkInport('in_sync');
 in_sync_port = this_block.port('in_sync');
-in_sync_port.setType('Ufix_1_0');
+in_sync_port.setType('Bool');
 in_sync_port.useHDLVector(false);
 this_block.addSimulinkInport('in_valid');
 in_valid_port = this_block.port('in_valid');
-in_valid_port.setType('Ufix_1_0');
+in_valid_port.setType('Bool');
 in_valid_port.useHDLVector(false);
 this_block.addSimulinkInport('shiftreg');
 in_shiftreg_port = this_block.port('shiftreg');
@@ -138,12 +138,12 @@ function wbpfb_unit_top_config(this_block)
 
   this_block.addSimulinkInport('in_sop');
   in_sop_port = this_block.port('in_sop');
-  in_sop_port.setType('Ufix_1_0');
+  in_sop_port.setType('Bool');
   in_sop_port.useHDLVector(false);
   
   this_block.addSimulinkInport('in_eop');
   in_eop_port = this_block.port('in_eop');
-  in_eop_port.setType('Ufix_1_0');
+  in_eop_port.setType('Bool');
   in_eop_port.useHDLVector(false);
   
   this_block.addSimulinkInport('in_empty');
@@ -177,19 +177,19 @@ function wbpfb_unit_top_config(this_block)
 % outport declarations
 this_block.addSimulinkOutport('fil_sync');
 fil_sync_port = this_block.port('fil_sync');
-fil_sync_port.setType('Ufix_1_0');
+fil_sync_port.setType('Bool');
 fil_sync_port.useHDLVector(false);
 this_block.addSimulinkOutport('out_sync');
 out_sync_port = this_block.port('out_sync');
-out_sync_port.setType('Ufix_1_0');
+out_sync_port.setType('Bool');
 out_sync_port.useHDLVector(false);
 this_block.addSimulinkOutport('fil_valid');
 fil_valid_port = this_block.port('fil_valid');
-fil_valid_port.setType('Ufix_1_0');
+fil_valid_port.setType('Bool');
 fil_valid_port.useHDLVector(false);
 this_block.addSimulinkOutport('out_valid');
 out_valid_port = this_block.port('out_valid');
-out_valid_port.setType('Ufix_1_0');
+out_valid_port.setType('Bool');
 out_valid_port.useHDLVector(false);
 this_block.addSimulinkOutport('ovflw');
 out_ovflw_port = this_block.port('ovflw');


Test patch:
diff --git a/casper_wb_fft/ngvla_test_proj/ngVLA_wbfft_test.tcl b/casper_wb_fft/ngvla_test_proj/ngVLA_wbfft_test.tcl
new file mode 100644
index 00000000..f1d0fc10
--- /dev/null
+++ b/casper_wb_fft/ngvla_test_proj/ngVLA_wbfft_test.tcl
@@ -0,0 +1,125 @@
+package require ::tclapp::xilinx::junit
+namespace import ::tclapp::xilinx::junit::*
+# See: https://github.com/Xilinx/XilinxTclStore/blob/master/tclapp/xilinx/junit/README.md
+
+set origin_dir "."
+set outputDir ./synth_output
+set_report ./report.xml
+
+file mkdir $outputDir
+
+
+
+read_vhdl "$origin_dir/wb_wrapper.vhd"
+read_vhdl "$origin_dir/top.vhd"
+# read_xdc "$origin_dir/wb_wrapper_ooc.xdc"
+read_xdc "$origin_dir/test.xdc"
+read_vhdl -library common_components_lib "$origin_dir/../../common_components/common_bit_delay.vhd"
+read_vhdl -library common_components_lib "$origin_dir/../../common_components/common_delay.vhd"
+read_vhdl -library common_components_lib "$origin_dir/../../common_components/common_pipeline.vhd"
+read_vhdl -library common_components_lib "$origin_dir/../../common_components/common_pipeline_sl.vhd"
+read_vhdl -library common_components_lib "$origin_dir/../../common_components/common_components_pkg.vhd"
+
+read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/fixed_float_types_c.vhd"
+read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/fixed_pkg_c.vhd"
+read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/common_pkg.vhd"
+read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/common_str_pkg.vhd"
+read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/common_lfsr_sequences_pkg.vhd"
+#read_vhdl -library common_pkg_lib "$origin_dir/../../common_pkg/float_pkg_c.vhd"
+
+read_vhdl -library technology_lib "$origin_dir/../../technology/technology_select_pkg_versal.vhd"
+
+read_vhdl -library casper_multiplier_lib "$origin_dir/../../casper_multiplier/tech_mult_component.vhd"
+read_vhdl -library casper_multiplier_lib "$origin_dir/../../casper_multiplier/tech_agilex_versal_cmult.vhd"
+read_vhdl -library casper_multiplier_lib "$origin_dir/../../casper_multiplier/tech_complex_mult.vhd"
+read_vhdl -library casper_multiplier_lib "$origin_dir/../../casper_multiplier/common_complex_mult.vhd"
+
+read_vhdl -library casper_counter_lib "$origin_dir/../../casper_counter/common_counter.vhd"
+
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_ram_pkg.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/tech_memory_component_pkg.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/tech_memory_ram_cr_cw.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/tech_memory_ram_crw_crw.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_ram_crw_crw.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_paged_ram_crw_crw.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_paged_ram_rw_rw.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_paged_ram_r_w.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/tech_memory_rom_r_r.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/tech_memory_rom_r.vhd"
+read_vhdl -library casper_ram_lib "$origin_dir/../../casper_ram/common_rom_r_r.vhd"
+
+read_vhdl -library casper_requantize_lib "$origin_dir/../../casper_requantize/common_round.vhd"
+read_vhdl -library casper_requantize_lib "$origin_dir/../../casper_requantize/common_resize.vhd"
+read_vhdl -library casper_requantize_lib "$origin_dir/../../casper_requantize/common_requantize.vhd"
+read_vhdl -library casper_requantize_lib "$origin_dir/../../casper_requantize/r_shift_requantize.vhd"
+
+read_vhdl -library casper_multiplexer_lib "$origin_dir/../../casper_multiplexer/common_zip.vhd"
+
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/twiddlesPkg.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoSDFPkg.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoBF.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoBFStage.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoWeights.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoSDFStage.vhd"
+read_vhdl -library r2sdf_fft_lib "$origin_dir/../../r2sdf_fft/rTwoWMul.vhd"
+
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_pkg.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_gnrcs_intrfcs_pkg.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_r2_bf_par.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_r2_par.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_sepa.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_reorder_sepa_pipe.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_r2_pipe.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_sepa_wide.vhd"
+read_vhdl -library wb_fft_lib "$origin_dir/../../casper_wb_fft/fft_r2_wide.vhd"
+
+read_vhdl -library ip_xpm_mult_lib "$origin_dir/../../ip_xpm/mult/ip_cmult_rtl_3dsp.vhd"
+read_vhdl -library ip_xpm_mult_lib "$origin_dir/../../ip_xpm/mult/ip_cmult_rtl_4dsp.vhd"
+read_vhdl -library ip_xpm_ram_lib "$origin_dir/../../ip_xpm/ram/ip_xpm_ram_cr_cw.vhd"
+read_vhdl -library ip_xpm_ram_lib "$origin_dir/../../ip_xpm/ram/ip_xpm_ram_crw_crw.vhd"
+read_vhdl -library ip_xpm_ram_lib "$origin_dir/../../ip_xpm/ram/ip_xpm_rom_r.vhd"
+read_vhdl -library ip_xpm_ram_lib "$origin_dir/../../ip_xpm/ram/ip_xpm_rom_r_r.vhd"
+
+update_compile_order
+
+run_step {synth_design -top top -part xczu48dr-ffvg1517-1-i}
+
+write_checkpoint -force $outputDir/post_synth
+# validation
+validate_timing "Post synth_design"
+validate_logic "Post synth_design"
+
+
+# opt_design
+#run_step {opt_design}
+#write_checkpoint opt_design.dcp
+# validation
+#validate_timing "Post opt_design"
+#validate_logic "Post opt_design"
+
+# place_design
+#run_step {place_design}
+#write_checkpoint place_design.dcp
+# validation
+#validate_timing "Post place_design"
+#validate_logic "Post place_design"
+
+# phys_opt_design
+#run_step {phys_opt_design}
+#write_checkpoint phys_opt_design.dcp
+# validation
+#validate_timing "Post phys_opt_design"
+#validate_logic "Post phys_opt_design"
+
+# route_design
+#run_step {route_design}
+#write_checkpoint route_design.dcp
+# validation
+#validate_timing "Post route_design"
+#validate_routing "Post route_design"
+
+
+validate_messages "Final"
+validate_drcs "Final"
+
+write_results
diff --git a/casper_wb_fft/ngvla_test_proj/test.xdc b/casper_wb_fft/ngvla_test_proj/test.xdc
new file mode 100644
index 00000000..b4c6f76a
--- /dev/null
+++ b/casper_wb_fft/ngvla_test_proj/test.xdc
@@ -0,0 +1,1 @@
+create_clock -period 1.818 -name i_clk -waveform {0.000 0.909} [get_ports i_clk]
diff --git a/casper_wb_fft/ngvla_test_proj/top.vhd b/casper_wb_fft/ngvla_test_proj/top.vhd
new file mode 100644
index 00000000..c9b40f56
--- /dev/null
+++ b/casper_wb_fft/ngvla_test_proj/top.vhd
@@ -0,0 +1,93 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/31/2023 12:31:29 PM
+-- Design Name: 
+-- Module Name: top - top_arch
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+library ieee, r2sdf_fft_lib,wb_fft_lib,common_pkg_lib;
+use ieee.std_logic_1164.all; 
+use ieee.numeric_std.all; 
+use common_pkg_lib.common_pkg.all;
+use wb_fft_lib.fft_gnrcs_intrfcs_pkg.all;
+use r2sdf_fft_lib.rTwoSDFPkg.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+        
+    port(
+        i_clk           : in  std_logic;     --! Clock
+        i_rst           : in  std_logic := '0'; --! Reset
+        i_shiftreg      : in  std_logic_vector(17  DOWNTO 0); --! Shift register
+        i_re_arr        : in  t_slv_44_arr(31 downto 0); --! Input real data (wb_factor wide)
+        i_im_arr        : in  t_slv_44_arr(31 downto 0); --! Input imag data (wb_factor wide)
+        i_val           : in  std_logic := '1'; --! In data valid
+        o_re_arr        : out t_slv_64_arr(31 downto 0); --! Output real data (wb_factor wide)
+        o_im_arr        : out t_slv_64_arr(31 downto 0); --! Output imag data (wb_factor wide)
+        o_ovflw         : out std_logic_vector(17 DOWNTO 0); --! Overflow register
+        o_val           : out std_logic      --! Out data valid
+    );
+end top;
+
+architecture top_arch of top is
+
+component wb_wrapper is
+    generic(
+        g_wb_factor     : integer := 32
+    );   
+    port(
+        i_clk           : in  std_logic;     --! Clock
+        i_rst           : in  std_logic := '0'; --! Reset
+        i_shiftreg      : in  std_logic_vector(17  DOWNTO 0); --! Shift register
+        i_re_arr        : in  t_slv_44_arr(g_wb_factor-1 downto 0); --! Input real data (wb_factor wide)
+        i_im_arr        : in  t_slv_44_arr(g_wb_factor-1 downto 0); --! Input imag data (wb_factor wide)
+        i_val           : in  std_logic := '1'; --! In data valid
+        o_re_arr        : out t_slv_64_arr(g_wb_factor-1 downto 0); --! Output real data (wb_factor wide)
+        o_im_arr        : out t_slv_64_arr(g_wb_factor-1 downto 0); --! Output imag data (wb_factor wide)
+        o_ovflw         : out std_logic_vector(17 DOWNTO 0) := (others => '0'); --! Overflow register
+        o_val           : out std_logic      --! Out data valid
+    );
+end component wb_wrapper;
+constant c_wb_factor : integer := 4;
+begin
+
+
+wb_wrapper_inst : wb_wrapper
+  generic map(
+    g_wb_factor => c_wb_factor)
+  port map(
+    i_clk                 => i_clk,
+    i_rst                 => i_rst,
+    i_shiftreg            => i_shiftreg,
+    i_re_arr           => i_re_arr(c_wb_factor-1 downto 0),
+    i_im_arr           => i_im_arr(c_wb_factor-1 downto 0),
+    i_val              => i_val,
+    o_re_arr          => o_re_arr(c_wb_factor-1 downto 0),
+    o_im_arr          => o_im_arr(c_wb_factor-1 downto 0),
+    o_ovflw               => o_ovflw,
+    o_val             => o_val
+  );
+
+
+end top_arch;
diff --git a/casper_wb_fft/ngvla_test_proj/wb_wrapper.vhd b/casper_wb_fft/ngvla_test_proj/wb_wrapper.vhd
new file mode 100644
index 00000000..fb9f4064
--- /dev/null
+++ b/casper_wb_fft/ngvla_test_proj/wb_wrapper.vhd
@@ -0,0 +1,126 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/31/2023 12:31:29 PM
+-- Design Name: 
+-- Module Name: top - top_arch
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+library ieee, r2sdf_fft_lib,wb_fft_lib,common_pkg_lib;
+use ieee.std_logic_1164.all; 
+use ieee.numeric_std.all; 
+use common_pkg_lib.common_pkg.all;
+use wb_fft_lib.fft_gnrcs_intrfcs_pkg.all;
+use r2sdf_fft_lib.rTwoSDFPkg.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity wb_wrapper is
+    generic(
+        g_wb_factor     : integer := 32
+    );   
+    port(
+        i_clk           : in  std_logic;     --! Clock
+        i_rst           : in  std_logic := '0'; --! Reset
+        i_shiftreg      : in  std_logic_vector(17  DOWNTO 0); --! Shift register
+        i_re_arr        : in  t_slv_44_arr(g_wb_factor-1 downto 0); --! Input real data (wb_factor wide)
+        i_im_arr        : in  t_slv_44_arr(g_wb_factor-1 downto 0); --! Input imag data (wb_factor wide)
+        i_val           : in  std_logic := '1'; --! In data valid
+        o_re_arr        : out t_slv_64_arr(g_wb_factor-1 downto 0); --! Output real data (wb_factor wide)
+        o_im_arr        : out t_slv_64_arr(g_wb_factor-1 downto 0); --! Output imag data (wb_factor wide)
+        o_ovflw         : out std_logic_vector(17 DOWNTO 0) := (others => '0'); --! Overflow register
+        o_val           : out std_logic      --! Out data valid
+    );
+end wb_wrapper;
+
+architecture wb_wrapper_arch of wb_wrapper is
+        
+constant c_fft_test : t_fft :=  (
+                                  use_reorder         => false, 
+                                  use_fft_shift       => false, 
+                                  use_separate        => false,  -- we'll actually use seperate on ngVLA but let's start with complex 
+                                  nof_chan            => 0, 
+                                  wb_factor           => g_wb_factor, 
+                                  nof_points          => 131072, 
+                                  in_dat_w            => 18, 
+                                  out_dat_w           => 18, 
+                                  out_gain_w          => 0, 
+                                  stage_dat_w         => 18, 
+                                  twiddle_dat_w       => 18, 
+                                  max_addr_w          => c_max_addr_w,
+                                  guard_w             => 0,
+                                  guard_enable        => true,
+                                  stat_data_w         => 56,
+                                  stat_data_sz        => 2,
+                                  pipe_reo_in_place   => false
+                                );
+
+signal shiftreg      : std_logic_vector(ceil_log2(c_fft_test.nof_points) - 1 DOWNTO 0); --! Shift register
+signal re_arr        : t_slv_44_arr(g_wb_factor-1 downto 0); --! Input real data (wb_factor wide)
+signal im_arr        : t_slv_44_arr(g_wb_factor-1 downto 0); --! Input imag data (wb_factor wide)
+signal vald          : std_logic := '1'; --! In data valid
+
+										  
+begin
+
+
+reg_inputs : process(i_clk)
+begin
+	if rising_edge(i_clk) then
+		re_arr		<= i_re_arr;
+		im_arr		<= i_im_arr;
+		shiftreg 	<= i_shiftreg(shiftreg'length-1 downto 0);
+		vald		<= i_val;
+	end if;
+end process;
+
+
+fft_r2_wide_inst : entity wb_fft_lib.fft_r2_wide
+  generic map(
+    g_fft               => c_fft_test,
+    g_pft_pipeline      => c_fft_pipeline, -- r2sdf_fft_lib.rTwoSDFPkg
+    g_fft_pipeline      => c_fft_pipeline, -- r2sdf_fft_lib.rTwoSDFPkg
+    g_alt_output        => true,
+    g_use_variant       => "4DSP",
+    g_use_dsp           => "yes",
+    g_ovflw_behav       => "SATURATE",
+    g_round             => ROUND,
+    g_use_mult_round    => ROUND,
+    g_ram_primitive     => "auto",
+    g_twid_file_stem    => "UNUSED"
+  )
+  port map(
+    clken               => '1', -- let's not use clock enables...
+    clk                 => i_clk,
+    rst                 => i_rst,
+    shiftreg            => shiftreg,
+    in_re_arr           => re_arr,
+    in_im_arr           => im_arr,
+    in_val              => vald,
+    out_re_arr          => o_re_arr,
+    out_im_arr          => o_im_arr,
+    ovflw               => o_ovflw(ceil_log2(c_fft_test.nof_points)-1 downto 0),
+    out_val             => o_val
+  );
+
+
+end wb_wrapper_arch;
diff --git a/casper_wb_fft/ngvla_test_proj/wb_wrapper_ooc.xdc b/casper_wb_fft/ngvla_test_proj/wb_wrapper_ooc.xdc
new file mode 100644
index 00000000..04a16303
--- /dev/null
+++ b/casper_wb_fft/ngvla_test_proj/wb_wrapper_ooc.xdc
@@ -0,0 +1,8 @@
+# (c) Copyright 2014 Xilinx, Inc. All rights reserved.
+
+# Add in a clock definition for each input clock to the out-of-context module.
+# The module will be synthesized as top so reference the clock origin using get_ports.
+# You will need to define a clock on each input clock port, no top level clock information
+# is provided to the module when set as out-of-context.
+# Here is an example:
+create_clock -name clk_500 -period 2 [get_ports i_clk]