Repository: ucb-bar/hammer (language: python)

Issue:
Is it possible to skip using asap 7 calibre deck to perform synthesis?
Hi,

I want to ask a few questions about using hammer with the chipyard.
1. Is it possible to skip using asap 7 calibre deck to perform synthesis? 
`make buildfile` needs the deck file. 
*I use `.edu` instead of `.edu.tw` email to request the Calibre deck and still no response yet.
2. Is it possible to use primetime to calculate the netlist power?
3. When I simply type `make buildfile` under `vlsi/`. It will say that it cannot compile the memory.
![Imgur](https://i.imgur.com/J8mhBnr.png)

For now, I just want to synthesize the design and calculate its netlist simulation performance.


Thank you.
Best regards,
Waxpple
asap-7 dual port SRAM
Hi:

I am using asap-7 behavior model provided  inside hammer. I was wondering whether both ports of SRAM2RW* instance will be used to write **and** read,  because I want to substitute asap7-sram with other SRAMs of another technology. If one of them be only used to write and another used to read.  Then 2prf (2 port register file) is suitable for reg-to-sram substitution. am I right ? or must I use DPSRAM whichever technology I choose ? 
or let's say，will configuration `“rw, rw”` / `"mrw, rw"` show up in top.mem.conf ? 
for now, I just see `"write, read",  "mwrite, read"` cases


best,
Leon


Discussion / hints:
1. Yes, you can synthesize without the Calibre decks. You will need to comment this out: https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/defaults.yml#L4 so that Hammer doesn't try to extract/check the tarball. I don't know what's going on with the ASU folks. The developer Vinay's email is vinay.vashishtha@asu.edu but I believe he left ASU already and I don't know who has taken over the.
2. We do not have a PrimeTime Hammer plugin, but if you have scripts yourself you can of course take the outputs from Hammer into your flow. We would also appreciate any contributions for a PrimeTime plugin!
3. This is actually an output from MacroCompiler, and it seems like you have a memory that requires mask granularity of 17 and an error (it probably should just be a warning) is thrown for each available SRAM that doesn't match that mask width. Does it fail entirely, or do you still get a .mems.v file at the end?
Hi,

1. I commented out line 4 
(https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/defaults.yml#L4)
and It will still enter the deck file extraction. 
(a) Shouldn't line 6 and 9 use `technology.asap7.pdk_install_dir` and `technology.asap7.stdcell_install_dir` directly? (https://github.com/ucb-bar/hammer/blob/d200c62ec2d35b7d999f10487e89527f95180d79/src/hammer-vlsi/technology/asap7/defaults.yml#L5-L9)
(b) After commented `asap7/defaults.yml #L4`, the program still enter this condition https://github.com/ucb-bar/hammer/blob/d200c62ec2d35b7d999f10487e89527f95180d79/src/hammer-tech/hammer_tech.py#L741-L742 and call `extract_tallballs`. I commented `L742` for ad hoc and it works now.
(c) Yes, I also post an issue on Vinay's asap repository too. 
2. Yes! I love to contribute something. After I figure the flow all out, I will try to implement the primetime plugin.
3. Yes, the `vlsi/generated-src/{Design_name}/{Design_name}.harness.mems.v` exists.
4. Is there any way to perform netlist-sim with vcs and output log file in `output/` like I do in rtl-sim `make run-asm-tests`. Because if I perform netlist-sim, vcs only shows `simulation completed` without telling it is correct or not.

Thanks!




1. Ooops, I realized that you should have actually removed these lines: https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/asap7.tech.json#L19-L25. This is what the lines 741-742 actually check to extract. This way you don't need to modify defaults.yml at all.
2. Thank you so much! If you want to interface directly with me for any questions about writing the plugin, you can email me at harrisonliew@berkeley.edu
3. Ok, what about `vlsi/generated-src/{Design_name}/{Design_name}.top.mems.v` file? This is what would be needed in order to run synthesis. If this exists, then MacroCompiler was able to compile some memories.
4. Assuming you are running this with Chipyard, yes, you can run netlist (RTL-level) sim with Hammer and VCS. You will need to use the sim-rtl-debug target here: https://github.com/ucb-bar/chipyard/blob/eb48397009c7708d2c43b02ac1da2193ab1df25e/vlsi/sim.mk#L53 with the appropriate benchmark set in the `BINARY` variable. Then, you will get the debug output (all instructions + a VPD/FSDB file) in the `sim-rundir`.
Hi,

3. Not sure if my thought is correct, the memory compiler should generate `.v` for simulation of the memory behavior, `.gds and .lef` for APR and its timing library like `.lib`. 
What should this folder `vlsi/generated-src/{Design_name}/sram_generator-rundir` do, is it normal to be empty?
Under `vlsi/generated-src/{Design_name}/tech-asap7-cache` there is SRAM with `.lib`, `.gds`, and `.lib` files.

With chipyard, the macro compiler is using `Barstools` right? [Barstools](https://chipyard.readthedocs.io/en/latest/Tools/Barstools.html).
As you mentioned, maybe it is just a warning.

Thanks.
Yes, the macro compiler is using Barstools.

So, in the asap7 case, its sram compiler puts one of the collateral (`.lib`) in the `tech-asap7-cache` directory https://github.com/ucb-bar/hammer/blob/d200c62ec2d35b7d999f10487e89527f95180d79/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py#L40, then generates a JSON file ([`sram_generator-output.json`](https://github.com/ucb-bar/chipyard/blob/eb48397009c7708d2c43b02ac1da2193ab1df25e/vlsi/Makefile#L99)) that points to all of these files https://github.com/ucb-bar/hammer/blob/d200c62ec2d35b7d999f10487e89527f95180d79/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py#L43. As long as you have this resulting JSON file and the memories inside match the ones in `vlsi/generated-src/{Design_name}/{Design_name}.top.mems.v`, you are good to go. Not all tech plugins utilize the `sram_generator-rundir`. 
Hi,

1. I have synthesized LargeBoomConfig, and even I push Genus very hard to optimize the design, the timing is still not met in the default sdc.
 
```tcl
...
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort extreme
...
syn_opt
syn_opt -inc
...
```
 *Note: This still ends up with better timing even it is not met. Maybe in the flow, it can add an option on effort strategy.

I think It will also fail on post-synthesis simulation too. But I run `rtl-sim-debug`, It will only generate a waveform file. and in the terminal, there is a `Fatal` keyword.
![Imgur](https://i.imgur.com/C1CUZuT.png)
How to generate a result such as this in rtl-sim?
![Imgur](https://i.imgur.com/b7C4paZ.png)
2. Where do I change the default sdc config?
3. I think vcs should use -fpg flag to take advantage of multi-thread simulation. The idea is from (https://www.francisz.cn/2020/07/09/vcs-parallel/)
Hi, Waxpple:

 Could you please tell me what your linux server version and VCS version is? I have some problem in `make sim-rtl`  issued here. #643 

Best,
Leon
> Hi, Waxpple:
> 
> Could you please tell me what your linux server version and VCS version is? I have some problem in `make sim-rtl` issued here. #643
> 
> Best, Leon

Hi,

Yes, here is my environment set up.

OS: Redhat Enterprise Linux 7.9
VCS: 2021.09 version

I think the EDA tool is not very compatible with the Debian-based Linux system.


> > Hi, Waxpple:
> > Could you please tell me what your linux server version and VCS version is? I have some problem in `make sim-rtl` issued here. #643
> > Best, Leon
> 
> Hi,
> 
> Yes, here is my environment set up.
> 
> OS: Redhat Enterprise Linux 7.9 VCS: 2021.09 version
> 
> I think the EDA tool is not very compatible with the Debian-based Linux system.

Thanks a lot. 

Yes, There are some many problems need to fix.  I will try it  on another RHEL6.10 linux server.  
> I have synthesized LargeBoomConfig, and even I push Genus very hard to optimize the design, the timing is still not met in the default sdc.

Perhaps a dumb question, but did you adjust the clock constraints (`vlsi.inputs.clocks`)? The default clock period is set for the example tiny config. Due to the size of a LargeBoomConfig, it would almost certainly not pass timing at the same frequency. Indeed, you can add these optimization commands as a synthesis hook in your flow (see the `example-vlsi` file for a template).

For your simulation, are you running timing-annotated simulation or only post-synthesis functional simulation? If it's timing-annotated, it would make sense that it doesn't pass. If not, then I might look at that line in the `.top.v` file to see where the `$fatal` directive is being called to debug. If this is a functional issue with BOOM, please raise an issue in the BOOM and/or Chipyard repositories, where appropriate instead of in Hammer.

> I think vcs should use -fpg flag to take advantage of multi-thread simulation. 

This would be a welcome contribution in hammer-synopsys-plugins! This should use the `vlsi.core.max_threads` key to set the number of cores.

> I think the EDA tool is not very compatible with the Debian-based Linux system.

VCS 2021.09 should be compatible with RHEL7 (we use that here), but not RHEL6 (due to outdated GNU C libraries).
Update on the ASAP7 Calibre decks. I sent an email to the ASAP7 project leader asking for help, and he replied that the Calibre deck is pulled off from the site for now.
Did he give any reason why? This is quite important for people wanting to use the PDK...

Anyways, I think I might actually implement the `-fgp` flags myself since it might potentially help me out. I'll have you review the PR when I'm done.
I'd love for you to review the VCS parallelism PR: ucb-bar/hammer-synopsys-plugins#23 (I can't add you as a reviewer directly).
> Did he give any reason why? This is quite important for people wanting to use the PDK...
> 

Yes, there are some issues/concerns with files being distributed on GitHub.

> I'd love for you to review the VCS parallelism PR: https://github.com/ucb-bar/hammer-synopsys-plugins/pull/23 (I can't add you as a reviewer directly).

Sure!


I can run simulation under `chipyard/sims/vcs` with same `CONFIG` and `BINARY`. But I cannot run the `make sim-rtl` under `chipyard/vlsi/`. Which means it is not a functional error? Or I should post an issue on `chipyard`?

If I turn the dramsim off, the result is still the same.

```bash
/home/ethan/Downloads/chipyard/vlsi/build/chipyard.TestHarness.SmallBoomConfig-ChipTop/sim-rtl-rundir/simv +permissive +dramsim +dramsim_ini_dir=/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +permissive-off /home/ethan/Downloads/chipyard/riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09_Full64; Runtime version S-2021.09_Full64;  Apr  2 03:41 2022
[UART] UART0 is here (stdin/stdout).
== Loading device model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' == 
== Loading system model file '/home/ethan/Downloads/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
Fatal: "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", 191091: TestDriver.testHarness.chiptop.system.tile_prci_domain.tile_reset_domain.boom_tile.frontend.icache: at time 2913500000 fs
$finish called from file "/home/ethan/Downloads/chipyard/vlsi/generated-src/chipyard.TestHarness.SmallBoomConfig/chipyard.TestHarness.SmallBoomConfig.top.v", line 191091.
$finish at simulation time             29135000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2913500000 fs
CPU Time:      1.340 seconds;       Data structure size:  14.0Mb
Sat Apr  2 03:41:41 2022
```

The top Verilog file

```verilog
 `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 <= 3'h1 | ~s1_valid) & ~reset) begin
          $fatal; // @[icache.scala 206:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_9 <= 3'h1 | ~s1_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at icache.scala:206 assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n"); // @[icache.scala 206:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS

```

> Yes, there are some issues/concerns with files being distributed on GitHub.

Weird. The whole point of requesting the decks was that it was not distributed on Github along with the rest of the PDK.

> I can run simulation under chipyard/sims/vcs with same CONFIG and BINARY. But I cannot run the make sim-rtl under chipyard/vlsi/. Which means it is not a functional error? Or I should post an issue on chipyard?

Not quite. There is a difference between running RTL simulation in `sims/vcs` vs. in `vlsi`. In the latter case, you have replaced the SeqMems with the behavioral model of the ASAP7 SRAMs that are mapped to your design. 

I haven't seen this particular issue before, and it looks like it has something to do with your ICache, not the simulated DRAM (hence why turning off DRAMSim didn't make a difference). Are you able to pull up the waveforms of both simulations to compare those wires (`_T_9` and `s1_valid`, perhaps) to see if there's a difference that might be caused by the SRAM models in any way?
Hi,

Yes, the behavior of two wires `_T_9 and s1_valid ` are not the same!
`_T_9 =  _T_5+ _T_7`
and the assertion failed on `rtl-sim`

### The `RTL-SIM` under `vlsi`
![Imgur](https://i.imgur.com/a7pULbk.png)
![Imgur](https://i.imgur.com/hrjezlM.png)

### The `sims/vcs` result
![Imgur](https://i.imgur.com/4NKTjYE.png)

Maybe I should create an issue on Chipyard.
Hm, looks like you need to trace `_T_5` back further before you create any issue in Chipyard so that you know what the cause is. If you have trouble, perhaps you can also attach the Verilog file here for me to see if it may be the SRAM models or not.
OK! I will add the trace and the file.
The trace of `_T_5=s1_tag_hit_0 + s1_tag_hit_1` and `s1_tag_hit_0= s1_vb_1 & tag_array_RW0_rdata_0 == s1_tag;`

#### `vcs/sims`
![Imgur](https://i.imgur.com/hVI7xjL.png)

#### `vlsi/`
![Imgur](https://i.imgur.com/wil2o3c.png)
The verilog file under `vlsi` and `sims/vcs`
https://github.com/Waxpple/generated_src_SBC

I think the two `top.v` Verilog files are identical, however, the two tag_array files are not identical.
Yeah, actually I do need to see the `mems.v` file (which contains the `module tag_array_0_ext`). Edit: I see you uploaded it.
Can you show the waveform for the ports to `tag_array_0_ext` for at least a few cycles before the read, as well as the value in the memory at the commanded address (inside the `ram` reg for `split_tag_array_0_ext` in the `sims/vcs` simulation and the `memory` reg inside `SRAM1RW60x24` in the `vlsi` simulation, respectively)? I want to see why the array read data is different (`0x1ec2` vs. `0x0010`).

I'm trying to compare the behavior of the 2 RAM models (`split_tag_array_0_ext` vs. `SRAM1RW60x24`) and I don't see anything immediately obvious. One difference is that [the latter multiplexes between read/write mode](https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v#L4055-L4146) whereas the former always reads. However, this intuitively shouldn't be a problem.
It seems just very different from the waveform...
I double check with the binary file, it is the same.
#### `sims/vcs` `tag_array_0_ext`
![Imgur](https://i.imgur.com/ZuAkyne.png)
![Imgur](https://i.imgur.com/GT0xcgm.png)
The `f_1ec2` always the same from the beginning, changed untiled 9423500000fs.
![Imgur](https://i.imgur.com/JxbHhwS.png)

#### `vlsi` `SRAM1RW60x24`
![Imgur](https://i.imgur.com/Mj3tc0I.png)
![Imgur](https://i.imgur.com/HK2lT8e.png)

Is this what you would like to see?
Ok, so comparing the last pictures from both sims, what's actually different is that `_T_7` goes to `2'h1` in the `vlsi` sim. `_T_7 = s1_tag_hit_2 + s1_tag_hit_3`, which means that for some reason, you're getting a tag hit in more than 1 set, which raises the assertion error.

So, can you dig a little deeper and compare the output tags from all 4 sets `tag_array_RW0_data_<3:0>` against the `s1_tag`? Please check these values before the first write to all 4 tag array sets at addresses `6'h00` and `6'h01` and also at the same time as the last picture here. I want to see whether by chance, the [random array initialization](https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v#L4123-L4129) is causing a line in the tag array to be `20'h00010	` before the first write.
Hi,

Yes, It gets 2 tag hits.
I trace the `wmode` and the `wmask` on `tag_array_0_ext`. 
If wmode is `1'h1` for writing op and `1'h0` for reading op. It writes the same value twice on address `6'h1` with different mask value.
First write @6'h01
![Imgur](https://i.imgur.com/LbMAqb0.png)

![Imgur](https://i.imgur.com/wzRwRuc.png)

![Imgur](https://i.imgur.com/sqV7MKz.png)
Second write @6'h01
![Imgur](https://i.imgur.com/NsPRu0g.png)
And the last
![Imgur](https://i.imgur.com/xkrhJfL.png)

### sims vcs
Yes, the value of `_T_9` is never greater than 2.
![Imgur](https://i.imgur.com/zW2II3r.png)
Huh. Ok so from what I see in order of screenshot:

1. Write to 3rd tag set (mask = 4'b0100) @ address 6'h01 of data 20'h00010
2. Write to 1st tag set (mask = 4'b0001) @ address 6'h02 of data 20'h00010
3. Write to 1st tag set (mask = 4'b0001) @ address 6'h00 of data 20'h00010
4. Write to 1st tag set (mask = 4'b0001) @ address 6'h01 of data 20'h00010
5. When read address goes to 6'h01, read data is 80'hffff_f000_10ff_fff0_0010. There are two 20'h00010 in there -> double hit -> error.

So, this seems to me that the SRAM behavioral models are correct. The issue seems to be why the write data is always fixed at 80'h0001_0000_1000_0100_0010 for the entire duration of the simulation. Does this not happen in the `sims/vcs` simulation?
Yes, It happens. It will stick to 80'h0001_0000_1000_0100_0010 for a while.
In the `vlsi` sim, it failed on the first section when reading 2 hits.

### `sims/vcs`
![Imgur](https://i.imgur.com/ObHVMts.png)

Maybe I will try to run other types of tests to see if this test is the problem.
I see, but it looks like only 3 writes are occurring while the write data is 80'h0001_0000_1000_0100_0010 in this sim, compared to 4 writes in the failing one (the 4th write is the problematic one). It would help to figure out why this is different before you run other types of tests.

Based on these waveforms, I think we can rule out the ASAP7 SRAM models as the problem, do you agree?
No, I did not show the first write in the sims/vcs. However, those four writes is like following:
Write to 3rd tag set (mask = 4'b0100) @ address 6'h01 of data 20'h00010
Write to 1st tag set (mask = 4'b0001) @ address 6'h00 of data 20'h00010
Write to 1st tag set (mask = 4'b0001) @ address 6'h02 of data 20'h00010
Write to 1st tag set (mask = 4'b0001) @ address **6'h03** of data 20'h00010

> Based on these waveforms, I think we can rule out the ASAP7 SRAM models as the problem, do you agree?

I think the SRAM model works fine, it does the R/W on what we saw.

Edit: Verilog looks fine too.

### Edit: The first write
![Imgur](https://i.imgur.com/Elfb81g.png)

### The fourth write
![Imgur](https://i.imgur.com/lwROtlV.png)

Edit: The problem should be why it will try to write the same data on the same address with a different mask value.

But am I the only one who runs into this assertion failure? 

Edit: I ran dhrystone and it failed too.
Can you email me the waveform of this run? This is odd, we wouldn't expect a microarchitectural bug to manifest only here.
> Can you email me the waveform of this run? This is odd, we wouldn't expect a microarchitectural bug to manifest only here.

Okay. I sent the email. Thanks
I'm seeing one of the SRAMs in the tags performing a 2-cycle read. Specifically, the cycle before the icache launches the second refill request to `0x10040`, it reads the tag SRAM, which doesn't respond with correct data until 2 cycles later.

![image](https://user-images.githubusercontent.com/14086183/162533380-c6ec2baf-a0da-4075-99ff-b3e14793618d.png)



Fix patch:
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py b/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py
index 139121c55..f066647e8 100644
--- a/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py
+++ b/src/hammer-vlsi/technology/asap7/sram_compiler/__init__.py
@@ -1,5 +1,5 @@
 
-import os, tempfile, subprocess
+import os, tempfile, subprocess, math
 
 from hammer_vlsi import MMMCCorner, MMMCCornerType, HammerTool, HammerToolStep, HammerSRAMGeneratorTool, SRAMParameters
 from hammer_vlsi.units import VoltageValue, TemperatureValue
@@ -37,15 +37,131 @@ def generate_sram(self, params: SRAMParameters, corner: MMMCCorner) -> ExtraLibr
                 fc=fam_code,
                 d=params.depth,
                 w=params.width)
-        lib_path ="{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str)
-        if not os.path.exists(lib_path):
-            os.symlink("{b}/lib/{n}_lib/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str), "{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str))
+
+        # Generate Verilog file from template
+        verilog_path ="{t}/{n}.v".format(t=tech_cache_dir,n=sram_name)
+        with open(verilog_path, 'w') as f:
+            if params.family == "1RW":
+                f.write("""
+`timescale 1ns/100fs
+
+module {NAME} (A,CE,WEB,OEB,CSB,I,O);
+
+input 				CE;
+input 				WEB;
+input 				OEB;
+input 				CSB;
+
+input 	[{NUMADDR}-1:0] 		A;
+input 	[{WORDLENGTH}-1:0] 	I;
+output 	[{WORDLENGTH}-1:0] 	O;
+
+reg     [{WORDLENGTH}-1:0]	memory[{NUMWORDS}-1:0];
+reg  	[{WORDLENGTH}-1:0]	data_out;
+wire 	[{WORDLENGTH}-1:0] 	O;
+
+wire 				RE;
+wire 				WE;
+and u1 (RE, ~CSB, ~OEB);
+and u2 (WE, ~CSB, ~WEB);
+
+// Initialization for simulation
+integer i;
+initial begin
+    for (i = 0; i < {NUMWORDS}; i = i + 1) begin
+        memory[i] = {{{RAND_WIDTH}{{$urandom()}}}};
+    end
+    data_out = {{{RAND_WIDTH}{{$urandom()}}}};
+end
+
+always @ (posedge CE) begin
+	if (RE)
+		data_out <= memory[A];
+	if (WE)
+		memory[A] <= I;
+end
+
+assign O = data_out;
+
+endmodule
+""".format(NUMADDR=math.ceil(math.log2(params.depth)), NUMWORDS=params.depth, WORDLENGTH=params.width, NAME=sram_name, RAND_WIDTH=math.ceil(params.width/32)))
+            else:
+                f.write("""
+`timescale 1ns/100fs
+
+module {NAME} (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
+
+input 				CE1;
+input 				CE2;
+input 				WEB1;
+input 				WEB2;
+input 				OEB1;
+input 				OEB2;
+input 				CSB1;
+input 				CSB2;
+
+input 	[{NUMADDR}-1:0] 		A1;
+input 	[{NUMADDR}-1:0] 		A2;
+input 	[{WORDLENGTH}-1:0] 	I1;
+input 	[{WORDLENGTH}-1:0] 	I2;
+output 	[{WORDLENGTH}-1:0] 	O1;
+output 	[{WORDLENGTH}-1:0] 	O2;
+
+reg     [{WORDLENGTH}-1:0]	memory[{NUMWORDS}-1:0];
+reg  	[{WORDLENGTH}-1:0]	data_out1;
+reg  	[{WORDLENGTH}-1:0]	data_out2;
+wire 	[{WORDLENGTH}-1:0] 	O1;
+wire  	[{WORDLENGTH}-1:0]	O2;
+
+wire 				RE1;
+wire 				RE2;
+wire 				WE1;
+wire 				WE2;
+and u1 (RE1, ~CSB1, ~OEB1);
+and u2 (RE2, ~CSB2, ~OEB2);
+and u3 (WE1, ~CSB1, ~WEB1);
+and u4 (WE2, ~CSB2, ~WEB2);
+
+// Initialization for simulation
+integer i;
+initial begin
+    for (i = 0; i < {NUMWORDS}; i = i + 1) begin
+        memory[i] = {{{RAND_WIDTH}{{$urandom()}}}};
+    end
+    data_out1 = {{{RAND_WIDTH}{{$urandom()}}}};
+    data_out2 = {{{RAND_WIDTH}{{$urandom()}}}};
+end
+
+always @ (posedge CE1) begin
+	if (RE1)
+		data_out1 <= memory[A1];
+	if (WE1)
+		memory[A1] <= I1;
+end
+
+always @ (posedge CE2) begin
+	if (RE2)
+		data_out2 <= memory[A2];
+	if (WE2)
+		memory[A2] <= I2;
+end
+
+assign O1 = data_out1;
+assign O2 = data_out2;
+
+endmodule
+""".format(NUMADDR=math.ceil(math.log2(params.depth)), NUMWORDS=params.depth, WORDLENGTH=params.width, NAME=sram_name, RAND_WIDTH=math.ceil(params.width/32)))
+
+        #lib_path ="{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str)
+        #if not os.path.exists(lib_path):
+        #    os.symlink("{b}/lib/{n}_lib/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str), "{t}/{n}_{c}.lib".format(t=tech_cache_dir,n=sram_name,c=corner_str))
         lib = ExtraLibrary(prefix=None, library=Library(
                 name=sram_name,
-                nldm_liberty_file=lib_path,
+                nldm_liberty_file="{b}/lib/{n}_lib/{n}_{c}.lib".format(b=base_dir,n=sram_name,c=corner_str),
                 lef_file="{b}/lef/{n}_x4.lef".format(b=base_dir,n=sram_name),
                 gds_file="{b}/gds/{n}_x4.gds".format(b=base_dir,n=sram_name),
-                verilog_sim="{b}/behavioral/sram_behav_models.v".format(b=base_dir),
+                #verilog_sim="{b}/behavioral/sram_behav_models.v".format(b=base_dir),
+                verilog_sim=verilog_path,
                 corner = {'nmos': speed_name, 'pmos': speed_name, 'temperature': str(corner.temp.value_in_units("C")) +" C"},
                 supplies = {'VDD': str(corner.voltage.value_in_units("V")) + " V", 'GND': "0 V" },
                 provides = [{'lib_type': "sram", 'vt': params.vt}]))  # type: ExtraLibrary
diff --git a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v b/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v
deleted file mode 100644
index 4c7762831..000000000
--- a/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v
+++ /dev/null
@@ -1,7448 +0,0 @@
-/*********************************************************************
-*  Filename      : SRAM1RW1024x16.v                                  *
-*  SRAM name     : SRAM1RW1024x16                                    *
-*  Word width    : 16     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 16
-
-
-module SRAM1RW1024x16 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x16_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x16_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x16_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x16_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x16_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x16_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x16_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x16_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x16_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x16_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x16_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x16_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x16_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x16_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x16_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x16_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-
-
-endmodule
-
-
-module SRAM1RW1024x16_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x17.v                                  *
-*  SRAM name     : SRAM1RW1024x17                                    *
-*  Word width    : 17     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 17
-
-
-module SRAM1RW1024x17 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x17_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x17_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x17_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x17_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x17_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x17_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x17_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x17_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x17_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x17_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x17_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x17_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x17_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x17_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x17_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x17_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x17_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-
-
-endmodule
-
-
-module SRAM1RW1024x17_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x32.v                                  *
-*  SRAM name     : SRAM1RW1024x32                                    *
-*  Word width    : 32     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 32
-
-
-module SRAM1RW1024x32 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x32_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x32_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x32_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x32_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x32_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x32_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x32_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x32_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x32_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x32_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x32_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x32_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x32_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x32_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x32_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x32_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x32_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW1024x32_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW1024x32_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW1024x32_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW1024x32_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW1024x32_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW1024x32_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW1024x32_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW1024x32_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW1024x32_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW1024x32_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW1024x32_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW1024x32_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW1024x32_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW1024x32_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW1024x32_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-
-
-endmodule
-
-
-module SRAM1RW1024x32_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x37.v                                  *
-*  SRAM name     : SRAM1RW1024x37                                  *
-*  Word width    : 37     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 37
-
-
-module SRAM1RW1024x37 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x37_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x37_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x37_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x37_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x37_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x37_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x37_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x37_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x37_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x37_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x37_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x37_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x37_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x37_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x37_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x37_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x37_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW1024x37_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW1024x37_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW1024x37_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW1024x37_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW1024x37_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW1024x37_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW1024x37_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW1024x37_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW1024x37_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW1024x37_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW1024x37_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW1024x37_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW1024x37_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW1024x37_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW1024x37_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW1024x37_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW1024x37_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW1024x37_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW1024x37_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW1024x37_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-
-
-endmodule
-
-
-module SRAM1RW1024x37_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x38.v                                  *
-*  SRAM name     : SRAM1RW1024x38                                  *
-*  Word width    : 38     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 38
-
-
-module SRAM1RW1024x38 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x38_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x38_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x38_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x38_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x38_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x38_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x38_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x38_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x38_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x38_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x38_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x38_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x38_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x38_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x38_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x38_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x38_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW1024x38_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW1024x38_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW1024x38_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW1024x38_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW1024x38_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW1024x38_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW1024x38_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW1024x38_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW1024x38_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW1024x38_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW1024x38_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW1024x38_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW1024x38_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW1024x38_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW1024x38_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW1024x38_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW1024x38_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW1024x38_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW1024x38_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW1024x38_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW1024x38_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-
-
-endmodule
-
-
-module SRAM1RW1024x38_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x44.v                                  *
-*  SRAM name     : SRAM1RW1024x44                                  *
-*  Word width    : 44     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 44
-
-
-module SRAM1RW1024x44 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x44_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x44_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x44_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x44_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x44_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x44_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x44_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x44_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x44_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x44_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x44_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x44_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x44_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x44_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x44_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x44_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x44_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW1024x44_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW1024x44_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW1024x44_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW1024x44_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW1024x44_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW1024x44_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW1024x44_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW1024x44_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW1024x44_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW1024x44_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW1024x44_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW1024x44_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW1024x44_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW1024x44_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW1024x44_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW1024x44_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW1024x44_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW1024x44_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW1024x44_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW1024x44_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW1024x44_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW1024x44_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW1024x44_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW1024x44_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW1024x44_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW1024x44_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW1024x44_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-
-
-endmodule
-
-
-module SRAM1RW1024x44_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x64.v                                  *
-*  SRAM name     : SRAM1RW1024x64                                  *
-*  Word width    : 64     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 64
-
-
-module SRAM1RW1024x64 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x64_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x64_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x64_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x64_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x64_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x64_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x64_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x64_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW1024x64_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW1024x64_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW1024x64_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW1024x64_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW1024x64_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW1024x64_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW1024x64_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW1024x64_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW1024x64_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW1024x64_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW1024x64_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW1024x64_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW1024x64_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW1024x64_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW1024x64_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW1024x64_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW1024x64_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW1024x64_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW1024x64_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW1024x64_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW1024x64_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW1024x64_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW1024x64_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW1024x64_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW1024x64_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW1024x64_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW1024x64_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW1024x64_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW1024x64_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW1024x64_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW1024x64_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW1024x64_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW1024x64_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW1024x64_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW1024x64_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW1024x64_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW1024x64_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW1024x64_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW1024x64_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW1024x64_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW1024x64_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW1024x64_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-SRAM1RW1024x64_1bit sram_IO50 ( CE, WEB,  A, OEB, CSB, I[50], O[50]);
-SRAM1RW1024x64_1bit sram_IO51 ( CE, WEB,  A, OEB, CSB, I[51], O[51]);
-SRAM1RW1024x64_1bit sram_IO52 ( CE, WEB,  A, OEB, CSB, I[52], O[52]);
-SRAM1RW1024x64_1bit sram_IO53 ( CE, WEB,  A, OEB, CSB, I[53], O[53]);
-SRAM1RW1024x64_1bit sram_IO54 ( CE, WEB,  A, OEB, CSB, I[54], O[54]);
-SRAM1RW1024x64_1bit sram_IO55 ( CE, WEB,  A, OEB, CSB, I[55], O[55]);
-SRAM1RW1024x64_1bit sram_IO56 ( CE, WEB,  A, OEB, CSB, I[56], O[56]);
-SRAM1RW1024x64_1bit sram_IO57 ( CE, WEB,  A, OEB, CSB, I[57], O[57]);
-SRAM1RW1024x64_1bit sram_IO58 ( CE, WEB,  A, OEB, CSB, I[58], O[58]);
-SRAM1RW1024x64_1bit sram_IO59 ( CE, WEB,  A, OEB, CSB, I[59], O[59]);
-SRAM1RW1024x64_1bit sram_IO60 ( CE, WEB,  A, OEB, CSB, I[60], O[60]);
-SRAM1RW1024x64_1bit sram_IO61 ( CE, WEB,  A, OEB, CSB, I[61], O[61]);
-SRAM1RW1024x64_1bit sram_IO62 ( CE, WEB,  A, OEB, CSB, I[62], O[62]);
-SRAM1RW1024x64_1bit sram_IO63 ( CE, WEB,  A, OEB, CSB, I[63], O[63]);
-
-
-endmodule
-
-
-module SRAM1RW1024x64_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW1024x8.v                                  *
-*  SRAM name     : SRAM1RW1024x8                                    *
-*  Word width    : 8     bits                                        *
-*  Word number   : 1024                                              *
-*  Adress width  : 10    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 10
-`define numWords 1024
-`define wordLength 8
-
-
-module SRAM1RW1024x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW1024x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW1024x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW1024x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW1024x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW1024x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW1024x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW1024x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW1024x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW1024x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW2048x8.v                                  *
-*  SRAM name     : SRAM1RW2048x8                                    *
-*  Word width    : 8     bits                                        *
-*  Word number   : 2048                                             *
-*  Adress width  : 11    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 11
-`define numWords 2048
-`define wordLength 8
-
-
-module SRAM1RW2048x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW2048x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW2048x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW2048x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW2048x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW2048x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW2048x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW2048x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW2048x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW2048x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x12.v                                  *
-*  SRAM name     : SRAM1RW128x12                                    *
-*  Word width    : 12    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 12
-
-
-module SRAM1RW128x12 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x12_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x12_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x12_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x12_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x12_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x12_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x12_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x12_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x12_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x12_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x12_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x12_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-
-
-endmodule
-
-
-module SRAM1RW128x12_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x14.v                                  *
-*  SRAM name     : SRAM1RW128x14                                    *
-*  Word width    : 14    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 14
-
-
-module SRAM1RW128x14 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x14_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x14_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x14_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x14_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x14_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x14_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x14_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x14_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x14_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x14_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x14_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x14_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x14_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x14_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-
-
-endmodule
-
-
-module SRAM1RW128x14_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x22.v                                  *
-*  SRAM name     : SRAM1RW128x22                                    *
-*  Word width    : 22    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 22
-
-
-module SRAM1RW128x22 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x22_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x22_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x22_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x22_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x22_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x22_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x22_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x22_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x22_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x22_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x22_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x22_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x22_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x22_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW128x22_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW128x22_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW128x22_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW128x22_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW128x22_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW128x22_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW128x22_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW128x22_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-
-
-endmodule
-
-
-module SRAM1RW128x22_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x40.v                                  *
-*  SRAM name     : SRAM1RW128x40                                    *
-*  Word width    : 40    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 40
-
-
-module SRAM1RW128x40 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x40_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x40_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x40_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x40_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x40_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x40_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x40_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x40_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x40_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x40_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x40_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x40_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x40_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x40_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW128x40_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW128x40_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW128x40_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW128x40_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW128x40_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW128x40_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW128x40_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW128x40_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW128x40_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW128x40_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW128x40_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW128x40_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW128x40_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW128x40_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW128x40_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW128x40_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW128x40_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW128x40_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW128x40_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW128x40_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW128x40_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW128x40_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW128x40_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW128x40_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW128x40_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW128x40_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-
-
-endmodule
-
-
-module SRAM1RW128x40_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x46.v                                  *
-*  SRAM name     : SRAM1RW128x46                                    *
-*  Word width    : 46    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 46
-
-
-module SRAM1RW128x46 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x46_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x46_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x46_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x46_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x46_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x46_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x46_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x46_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x46_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x46_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x46_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x46_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x46_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x46_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW128x46_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW128x46_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW128x46_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW128x46_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW128x46_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW128x46_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW128x46_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW128x46_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW128x46_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW128x46_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW128x46_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW128x46_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW128x46_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW128x46_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW128x46_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW128x46_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW128x46_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW128x46_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW128x46_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW128x46_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW128x46_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW128x46_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW128x46_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW128x46_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW128x46_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW128x46_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW128x46_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW128x46_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW128x46_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW128x46_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW128x46_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW128x46_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-
-
-endmodule
-
-
-module SRAM1RW128x46_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x48.v                                  *
-*  SRAM name     : SRAM1RW128x48                                    *
-*  Word width    : 48    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 48
-
-
-module SRAM1RW128x48 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x48_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x48_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x48_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x48_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x48_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x48_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x48_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x48_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x48_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x48_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x48_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x48_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x48_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x48_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW128x48_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW128x48_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW128x48_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW128x48_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW128x48_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW128x48_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW128x48_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW128x48_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW128x48_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW128x48_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW128x48_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW128x48_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW128x48_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW128x48_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW128x48_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW128x48_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW128x48_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW128x48_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW128x48_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW128x48_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW128x48_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW128x48_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW128x48_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW128x48_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW128x48_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW128x48_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW128x48_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW128x48_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW128x48_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW128x48_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW128x48_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW128x48_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW128x48_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW128x48_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-
-
-endmodule
-
-
-module SRAM1RW128x48_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x64.v                                  *
-*  SRAM name     : SRAM1RW128x64                                    *
-*  Word width    : 64    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 64
-
-
-module SRAM1RW128x64 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x64_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x64_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x64_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x64_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x64_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x64_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x64_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x64_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW128x64_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW128x64_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW128x64_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW128x64_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW128x64_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW128x64_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW128x64_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW128x64_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW128x64_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW128x64_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW128x64_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW128x64_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW128x64_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW128x64_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW128x64_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW128x64_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW128x64_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW128x64_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW128x64_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW128x64_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW128x64_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW128x64_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW128x64_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW128x64_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW128x64_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW128x64_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW128x64_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW128x64_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW128x64_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW128x64_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW128x64_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW128x64_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW128x64_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW128x64_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW128x64_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW128x64_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW128x64_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW128x64_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW128x64_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW128x64_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW128x64_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW128x64_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-SRAM1RW128x64_1bit sram_IO50 ( CE, WEB,  A, OEB, CSB, I[50], O[50]);
-SRAM1RW128x64_1bit sram_IO51 ( CE, WEB,  A, OEB, CSB, I[51], O[51]);
-SRAM1RW128x64_1bit sram_IO52 ( CE, WEB,  A, OEB, CSB, I[52], O[52]);
-SRAM1RW128x64_1bit sram_IO53 ( CE, WEB,  A, OEB, CSB, I[53], O[53]);
-SRAM1RW128x64_1bit sram_IO54 ( CE, WEB,  A, OEB, CSB, I[54], O[54]);
-SRAM1RW128x64_1bit sram_IO55 ( CE, WEB,  A, OEB, CSB, I[55], O[55]);
-SRAM1RW128x64_1bit sram_IO56 ( CE, WEB,  A, OEB, CSB, I[56], O[56]);
-SRAM1RW128x64_1bit sram_IO57 ( CE, WEB,  A, OEB, CSB, I[57], O[57]);
-SRAM1RW128x64_1bit sram_IO58 ( CE, WEB,  A, OEB, CSB, I[58], O[58]);
-SRAM1RW128x64_1bit sram_IO59 ( CE, WEB,  A, OEB, CSB, I[59], O[59]);
-SRAM1RW128x64_1bit sram_IO60 ( CE, WEB,  A, OEB, CSB, I[60], O[60]);
-SRAM1RW128x64_1bit sram_IO61 ( CE, WEB,  A, OEB, CSB, I[61], O[61]);
-SRAM1RW128x64_1bit sram_IO62 ( CE, WEB,  A, OEB, CSB, I[62], O[62]);
-SRAM1RW128x64_1bit sram_IO63 ( CE, WEB,  A, OEB, CSB, I[63], O[63]);
-
-
-endmodule
-
-
-module SRAM1RW128x64_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW128x8.v                                   *
-*  SRAM name     : SRAM1RW128x8                                     *
-*  Word width    : 8     bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 8
-
-
-module SRAM1RW128x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW128x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW128x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW128x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW128x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW128x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW128x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW128x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW128x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW128x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x128.v                                 *
-*  SRAM name     : SRAM1RW256x128                                   *
-*  Word width    : 128   bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 128
-
-
-module SRAM1RW256x128 (A,CE,WEB,OEB,CSB,BYTEMASK,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-input [`wordLength/8-1:0]	BYTEMASK;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x128_1bit sram_IO0 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x128_1bit sram_IO1 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x128_1bit sram_IO2 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x128_1bit sram_IO3 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x128_1bit sram_IO4 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x128_1bit sram_IO5 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x128_1bit sram_IO6 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x128_1bit sram_IO7 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[7], O[7]);
-SRAM1RW256x128_1bit sram_IO8 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[8], O[8]);
-SRAM1RW256x128_1bit sram_IO9 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[9], O[9]);
-SRAM1RW256x128_1bit sram_IO10 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[10], O[10]);
-SRAM1RW256x128_1bit sram_IO11 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[11], O[11]);
-SRAM1RW256x128_1bit sram_IO12 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[12], O[12]);
-SRAM1RW256x128_1bit sram_IO13 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[13], O[13]);
-SRAM1RW256x128_1bit sram_IO14 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[14], O[14]);
-SRAM1RW256x128_1bit sram_IO15 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[15], O[15]);
-SRAM1RW256x128_1bit sram_IO16 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[16], O[16]);
-SRAM1RW256x128_1bit sram_IO17 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[17], O[17]);
-SRAM1RW256x128_1bit sram_IO18 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[18], O[18]);
-SRAM1RW256x128_1bit sram_IO19 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[19], O[19]);
-SRAM1RW256x128_1bit sram_IO20 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[20], O[20]);
-SRAM1RW256x128_1bit sram_IO21 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[21], O[21]);
-SRAM1RW256x128_1bit sram_IO22 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[22], O[22]);
-SRAM1RW256x128_1bit sram_IO23 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[23], O[23]);
-SRAM1RW256x128_1bit sram_IO24 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[24], O[24]);
-SRAM1RW256x128_1bit sram_IO25 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[25], O[25]);
-SRAM1RW256x128_1bit sram_IO26 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[26], O[26]);
-SRAM1RW256x128_1bit sram_IO27 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[27], O[27]);
-SRAM1RW256x128_1bit sram_IO28 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[28], O[28]);
-SRAM1RW256x128_1bit sram_IO29 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[29], O[29]);
-SRAM1RW256x128_1bit sram_IO30 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[30], O[30]);
-SRAM1RW256x128_1bit sram_IO31 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[31], O[31]);
-SRAM1RW256x128_1bit sram_IO32 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[32], O[32]);
-SRAM1RW256x128_1bit sram_IO33 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[33], O[33]);
-SRAM1RW256x128_1bit sram_IO34 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[34], O[34]);
-SRAM1RW256x128_1bit sram_IO35 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[35], O[35]);
-SRAM1RW256x128_1bit sram_IO36 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[36], O[36]);
-SRAM1RW256x128_1bit sram_IO37 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[37], O[37]);
-SRAM1RW256x128_1bit sram_IO38 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[38], O[38]);
-SRAM1RW256x128_1bit sram_IO39 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[39], O[39]);
-SRAM1RW256x128_1bit sram_IO40 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[40], O[40]);
-SRAM1RW256x128_1bit sram_IO41 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[41], O[41]);
-SRAM1RW256x128_1bit sram_IO42 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[42], O[42]);
-SRAM1RW256x128_1bit sram_IO43 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[43], O[43]);
-SRAM1RW256x128_1bit sram_IO44 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[44], O[44]);
-SRAM1RW256x128_1bit sram_IO45 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[45], O[45]);
-SRAM1RW256x128_1bit sram_IO46 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[46], O[46]);
-SRAM1RW256x128_1bit sram_IO47 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[47], O[47]);
-SRAM1RW256x128_1bit sram_IO48 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[48], O[48]);
-SRAM1RW256x128_1bit sram_IO49 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[49], O[49]);
-SRAM1RW256x128_1bit sram_IO50 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[50], O[50]);
-SRAM1RW256x128_1bit sram_IO51 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[51], O[51]);
-SRAM1RW256x128_1bit sram_IO52 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[52], O[52]);
-SRAM1RW256x128_1bit sram_IO53 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[53], O[53]);
-SRAM1RW256x128_1bit sram_IO54 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[54], O[54]);
-SRAM1RW256x128_1bit sram_IO55 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[55], O[55]);
-SRAM1RW256x128_1bit sram_IO56 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[56], O[56]);
-SRAM1RW256x128_1bit sram_IO57 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[57], O[57]);
-SRAM1RW256x128_1bit sram_IO58 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[58], O[58]);
-SRAM1RW256x128_1bit sram_IO59 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[59], O[59]);
-SRAM1RW256x128_1bit sram_IO60 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[60], O[60]);
-SRAM1RW256x128_1bit sram_IO61 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[61], O[61]);
-SRAM1RW256x128_1bit sram_IO62 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[62], O[62]);
-SRAM1RW256x128_1bit sram_IO63 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[63], O[63]);
-SRAM1RW256x128_1bit sram_IO64 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[64], O[64]);
-SRAM1RW256x128_1bit sram_IO65 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[65], O[65]);
-SRAM1RW256x128_1bit sram_IO66 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[66], O[66]);
-SRAM1RW256x128_1bit sram_IO67 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[67], O[67]);
-SRAM1RW256x128_1bit sram_IO68 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[68], O[68]);
-SRAM1RW256x128_1bit sram_IO69 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[69], O[69]);
-SRAM1RW256x128_1bit sram_IO70 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[70], O[70]);
-SRAM1RW256x128_1bit sram_IO71 ( CE, WEB | ~BYTEMASK[8],  A, OEB, CSB, I[71], O[71]);
-SRAM1RW256x128_1bit sram_IO72 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[72], O[72]);
-SRAM1RW256x128_1bit sram_IO73 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[73], O[73]);
-SRAM1RW256x128_1bit sram_IO74 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[74], O[74]);
-SRAM1RW256x128_1bit sram_IO75 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[75], O[75]);
-SRAM1RW256x128_1bit sram_IO76 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[76], O[76]);
-SRAM1RW256x128_1bit sram_IO77 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[77], O[77]);
-SRAM1RW256x128_1bit sram_IO78 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[78], O[78]);
-SRAM1RW256x128_1bit sram_IO79 ( CE, WEB | ~BYTEMASK[9],  A, OEB, CSB, I[79], O[79]);
-SRAM1RW256x128_1bit sram_IO80 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[80], O[80]);
-SRAM1RW256x128_1bit sram_IO81 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[81], O[81]);
-SRAM1RW256x128_1bit sram_IO82 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[82], O[82]);
-SRAM1RW256x128_1bit sram_IO83 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[83], O[83]);
-SRAM1RW256x128_1bit sram_IO84 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[84], O[84]);
-SRAM1RW256x128_1bit sram_IO85 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[85], O[85]);
-SRAM1RW256x128_1bit sram_IO86 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[86], O[86]);
-SRAM1RW256x128_1bit sram_IO87 ( CE, WEB | ~BYTEMASK[10],  A, OEB, CSB, I[87], O[87]);
-SRAM1RW256x128_1bit sram_IO88 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[88], O[88]);
-SRAM1RW256x128_1bit sram_IO89 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[89], O[89]);
-SRAM1RW256x128_1bit sram_IO90 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[90], O[90]);
-SRAM1RW256x128_1bit sram_IO91 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[91], O[91]);
-SRAM1RW256x128_1bit sram_IO92 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[92], O[92]);
-SRAM1RW256x128_1bit sram_IO93 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[93], O[93]);
-SRAM1RW256x128_1bit sram_IO94 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[94], O[94]);
-SRAM1RW256x128_1bit sram_IO95 ( CE, WEB | ~BYTEMASK[11],  A, OEB, CSB, I[95], O[95]);
-SRAM1RW256x128_1bit sram_IO96 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[96], O[96]);
-SRAM1RW256x128_1bit sram_IO97 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[97], O[97]);
-SRAM1RW256x128_1bit sram_IO98 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[98], O[98]);
-SRAM1RW256x128_1bit sram_IO99 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[99], O[99]);
-SRAM1RW256x128_1bit sram_IO100 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[100], O[100]);
-SRAM1RW256x128_1bit sram_IO101 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[101], O[101]);
-SRAM1RW256x128_1bit sram_IO102 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[102], O[102]);
-SRAM1RW256x128_1bit sram_IO103 ( CE, WEB | ~BYTEMASK[12],  A, OEB, CSB, I[103], O[103]);
-SRAM1RW256x128_1bit sram_IO104 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[104], O[104]);
-SRAM1RW256x128_1bit sram_IO105 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[105], O[105]);
-SRAM1RW256x128_1bit sram_IO106 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[106], O[106]);
-SRAM1RW256x128_1bit sram_IO107 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[107], O[107]);
-SRAM1RW256x128_1bit sram_IO108 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[108], O[108]);
-SRAM1RW256x128_1bit sram_IO109 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[109], O[109]);
-SRAM1RW256x128_1bit sram_IO110 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[110], O[110]);
-SRAM1RW256x128_1bit sram_IO111 ( CE, WEB | ~BYTEMASK[13],  A, OEB, CSB, I[111], O[111]);
-SRAM1RW256x128_1bit sram_IO112 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[112], O[112]);
-SRAM1RW256x128_1bit sram_IO113 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[113], O[113]);
-SRAM1RW256x128_1bit sram_IO114 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[114], O[114]);
-SRAM1RW256x128_1bit sram_IO115 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[115], O[115]);
-SRAM1RW256x128_1bit sram_IO116 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[116], O[116]);
-SRAM1RW256x128_1bit sram_IO117 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[117], O[117]);
-SRAM1RW256x128_1bit sram_IO118 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[118], O[118]);
-SRAM1RW256x128_1bit sram_IO119 ( CE, WEB | ~BYTEMASK[14],  A, OEB, CSB, I[119], O[119]);
-SRAM1RW256x128_1bit sram_IO120 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[120], O[120]);
-SRAM1RW256x128_1bit sram_IO121 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[121], O[121]);
-SRAM1RW256x128_1bit sram_IO122 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[122], O[122]);
-SRAM1RW256x128_1bit sram_IO123 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[123], O[123]);
-SRAM1RW256x128_1bit sram_IO124 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[124], O[124]);
-SRAM1RW256x128_1bit sram_IO125 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[125], O[125]);
-SRAM1RW256x128_1bit sram_IO126 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[126], O[126]);
-SRAM1RW256x128_1bit sram_IO127 ( CE, WEB | ~BYTEMASK[15],  A, OEB, CSB, I[127], O[127]);
-
-
-endmodule
-
-
-module SRAM1RW256x128_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x32.v                                  *
-*  SRAM name     : SRAM1RW256x32                                    *
-*  Word width    : 32    bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 32
-
-
-module SRAM1RW256x32 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x32_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x32_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x32_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x32_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x32_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x32_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x32_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x32_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW256x32_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW256x32_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW256x32_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW256x32_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW256x32_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW256x32_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW256x32_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW256x32_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW256x32_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW256x32_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW256x32_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW256x32_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW256x32_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW256x32_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW256x32_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW256x32_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW256x32_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW256x32_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW256x32_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW256x32_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW256x32_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW256x32_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW256x32_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW256x32_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-
-
-endmodule
-
-
-module SRAM1RW256x32_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x46.v                                  *
-*  SRAM name     : SRAM1RW256x46                                    *
-*  Word width    : 46    bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 46
-
-
-module SRAM1RW256x46 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x46_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x46_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x46_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x46_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x46_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x46_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x46_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x46_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW256x46_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW256x46_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW256x46_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW256x46_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW256x46_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW256x46_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW256x46_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW256x46_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW256x46_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW256x46_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW256x46_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW256x46_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW256x46_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW256x46_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW256x46_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW256x46_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW256x46_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW256x46_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW256x46_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW256x46_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW256x46_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW256x46_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW256x46_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW256x46_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW256x46_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW256x46_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW256x46_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW256x46_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW256x46_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW256x46_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW256x46_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW256x46_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW256x46_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW256x46_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW256x46_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW256x46_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW256x46_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW256x46_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-
-
-endmodule
-
-
-module SRAM1RW256x46_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x48.v                                  *
-*  SRAM name     : SRAM1RW256x48                                    *
-*  Word width    : 48    bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 48
-
-
-module SRAM1RW256x48 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x48_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x48_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x48_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x48_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x48_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x48_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x48_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x48_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW256x48_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW256x48_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW256x48_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW256x48_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW256x48_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW256x48_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW256x48_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW256x48_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW256x48_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW256x48_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW256x48_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW256x48_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW256x48_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW256x48_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW256x48_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW256x48_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW256x48_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW256x48_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW256x48_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW256x48_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW256x48_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW256x48_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW256x48_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW256x48_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW256x48_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW256x48_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW256x48_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW256x48_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW256x48_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW256x48_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW256x48_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW256x48_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW256x48_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW256x48_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW256x48_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW256x48_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW256x48_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW256x48_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW256x48_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW256x48_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-
-
-endmodule
-
-
-module SRAM1RW256x48_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x64.v                                 *
-*  SRAM name     : SRAM1RW256x64                                   *
-*  Word width    : 64   bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 64
-
-
-module SRAM1RW256x64 (A,CE,WEB,OEB,CSB,BYTEMASK,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-input [`wordLength/8-1:0]	BYTEMASK;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x64_1bit sram_IO0 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x64_1bit sram_IO1 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x64_1bit sram_IO2 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x64_1bit sram_IO3 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x64_1bit sram_IO4 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x64_1bit sram_IO5 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x64_1bit sram_IO6 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x64_1bit sram_IO7 ( CE, WEB | ~BYTEMASK[0],  A, OEB, CSB, I[7], O[7]);
-SRAM1RW256x64_1bit sram_IO8 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[8], O[8]);
-SRAM1RW256x64_1bit sram_IO9 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[9], O[9]);
-SRAM1RW256x64_1bit sram_IO10 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[10], O[10]);
-SRAM1RW256x64_1bit sram_IO11 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[11], O[11]);
-SRAM1RW256x64_1bit sram_IO12 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[12], O[12]);
-SRAM1RW256x64_1bit sram_IO13 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[13], O[13]);
-SRAM1RW256x64_1bit sram_IO14 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[14], O[14]);
-SRAM1RW256x64_1bit sram_IO15 ( CE, WEB | ~BYTEMASK[1],  A, OEB, CSB, I[15], O[15]);
-SRAM1RW256x64_1bit sram_IO16 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[16], O[16]);
-SRAM1RW256x64_1bit sram_IO17 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[17], O[17]);
-SRAM1RW256x64_1bit sram_IO18 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[18], O[18]);
-SRAM1RW256x64_1bit sram_IO19 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[19], O[19]);
-SRAM1RW256x64_1bit sram_IO20 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[20], O[20]);
-SRAM1RW256x64_1bit sram_IO21 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[21], O[21]);
-SRAM1RW256x64_1bit sram_IO22 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[22], O[22]);
-SRAM1RW256x64_1bit sram_IO23 ( CE, WEB | ~BYTEMASK[2],  A, OEB, CSB, I[23], O[23]);
-SRAM1RW256x64_1bit sram_IO24 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[24], O[24]);
-SRAM1RW256x64_1bit sram_IO25 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[25], O[25]);
-SRAM1RW256x64_1bit sram_IO26 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[26], O[26]);
-SRAM1RW256x64_1bit sram_IO27 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[27], O[27]);
-SRAM1RW256x64_1bit sram_IO28 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[28], O[28]);
-SRAM1RW256x64_1bit sram_IO29 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[29], O[29]);
-SRAM1RW256x64_1bit sram_IO30 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[30], O[30]);
-SRAM1RW256x64_1bit sram_IO31 ( CE, WEB | ~BYTEMASK[3],  A, OEB, CSB, I[31], O[31]);
-SRAM1RW256x64_1bit sram_IO32 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[32], O[32]);
-SRAM1RW256x64_1bit sram_IO33 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[33], O[33]);
-SRAM1RW256x64_1bit sram_IO34 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[34], O[34]);
-SRAM1RW256x64_1bit sram_IO35 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[35], O[35]);
-SRAM1RW256x64_1bit sram_IO36 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[36], O[36]);
-SRAM1RW256x64_1bit sram_IO37 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[37], O[37]);
-SRAM1RW256x64_1bit sram_IO38 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[38], O[38]);
-SRAM1RW256x64_1bit sram_IO39 ( CE, WEB | ~BYTEMASK[4],  A, OEB, CSB, I[39], O[39]);
-SRAM1RW256x64_1bit sram_IO40 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[40], O[40]);
-SRAM1RW256x64_1bit sram_IO41 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[41], O[41]);
-SRAM1RW256x64_1bit sram_IO42 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[42], O[42]);
-SRAM1RW256x64_1bit sram_IO43 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[43], O[43]);
-SRAM1RW256x64_1bit sram_IO44 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[44], O[44]);
-SRAM1RW256x64_1bit sram_IO45 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[45], O[45]);
-SRAM1RW256x64_1bit sram_IO46 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[46], O[46]);
-SRAM1RW256x64_1bit sram_IO47 ( CE, WEB | ~BYTEMASK[5],  A, OEB, CSB, I[47], O[47]);
-SRAM1RW256x64_1bit sram_IO48 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[48], O[48]);
-SRAM1RW256x64_1bit sram_IO49 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[49], O[49]);
-SRAM1RW256x64_1bit sram_IO50 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[50], O[50]);
-SRAM1RW256x64_1bit sram_IO51 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[51], O[51]);
-SRAM1RW256x64_1bit sram_IO52 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[52], O[52]);
-SRAM1RW256x64_1bit sram_IO53 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[53], O[53]);
-SRAM1RW256x64_1bit sram_IO54 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[54], O[54]);
-SRAM1RW256x64_1bit sram_IO55 ( CE, WEB | ~BYTEMASK[6],  A, OEB, CSB, I[55], O[55]);
-SRAM1RW256x64_1bit sram_IO56 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[56], O[56]);
-SRAM1RW256x64_1bit sram_IO57 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[57], O[57]);
-SRAM1RW256x64_1bit sram_IO58 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[58], O[58]);
-SRAM1RW256x64_1bit sram_IO59 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[59], O[59]);
-SRAM1RW256x64_1bit sram_IO60 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[60], O[60]);
-SRAM1RW256x64_1bit sram_IO61 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[61], O[61]);
-SRAM1RW256x64_1bit sram_IO62 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[62], O[62]);
-SRAM1RW256x64_1bit sram_IO63 ( CE, WEB | ~BYTEMASK[7],  A, OEB, CSB, I[63], O[63]);
-
-
-endmodule
-
-
-module SRAM1RW256x64_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW256x8.v                                   *
-*  SRAM name     : SRAM1RW256x8                                     *
-*  Word width    : 8     bits                                        *
-*  Word number   : 256                                               *
-*  Adress width  : 8     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 8
-`define numWords 256
-`define wordLength 8
-
-
-module SRAM1RW256x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW256x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW256x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW256x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW256x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW256x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW256x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW256x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW256x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW256x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW32x50.v                                   *
-*  SRAM name     : SRAM1RW32x50                                     *
-*  Word width    : 50    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 50
-
-
-module SRAM1RW32x50 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW32x50_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW32x50_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW32x50_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW32x50_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW32x50_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW32x50_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW32x50_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW32x50_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW32x50_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW32x50_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW32x50_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW32x50_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW32x50_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW32x50_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW32x50_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW32x50_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW32x50_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW32x50_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW32x50_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW32x50_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW32x50_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW32x50_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW32x50_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW32x50_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW32x50_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW32x50_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW32x50_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW32x50_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW32x50_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW32x50_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW32x50_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW32x50_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW32x50_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW32x50_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW32x50_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW32x50_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW32x50_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW32x50_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW32x50_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW32x50_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW32x50_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW32x50_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW32x50_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW32x50_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW32x50_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW32x50_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW32x50_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW32x50_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW32x50_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW32x50_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-
-
-endmodule
-
-
-module SRAM1RW32x50_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW4096x16.v                                  *
-*  SRAM name     : SRAM1RW4096x16                                    *
-*  Word width    : 16     bits                                        *
-*  Word number   : 4096                                              *
-*  Adress width  : 12    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 12
-`define numWords 4096
-`define wordLength 16
-
-
-module SRAM1RW4096x16 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW4096x16_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW4096x16_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW4096x16_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW4096x16_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW4096x16_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW4096x16_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW4096x16_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW4096x16_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW4096x16_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW4096x16_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW4096x16_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW4096x16_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW4096x16_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW4096x16_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW4096x16_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW4096x16_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-
-
-endmodule
-
-
-module SRAM1RW4096x16_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW4096x8.v                                  *
-*  SRAM name     : SRAM1RW4096x8                                    *
-*  Word width    : 8     bits                                        *
-*  Word number   : 4096                                             *
-*  Adress width  : 12    bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 12
-`define numWords 4096
-`define wordLength 8
-
-
-module SRAM1RW4096x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW4096x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW4096x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW4096x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW4096x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW4096x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW4096x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW4096x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW4096x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW4096x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW512x128.v                                 *
-*  SRAM name     : SRAM1RW512x128                                   *
-*  Word width    : 128   bits                                        *
-*  Word number   : 512                                               *
-*  Adress width  : 9     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 9
-`define numWords 512
-`define wordLength 128
-
-
-module SRAM1RW512x128 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW512x128_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW512x128_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW512x128_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW512x128_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW512x128_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW512x128_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW512x128_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW512x128_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW512x128_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW512x128_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW512x128_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW512x128_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW512x128_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW512x128_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW512x128_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW512x128_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW512x128_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW512x128_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW512x128_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW512x128_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW512x128_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW512x128_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW512x128_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW512x128_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW512x128_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW512x128_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW512x128_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW512x128_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW512x128_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW512x128_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW512x128_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW512x128_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW512x128_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW512x128_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW512x128_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW512x128_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW512x128_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW512x128_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW512x128_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW512x128_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW512x128_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW512x128_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW512x128_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW512x128_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW512x128_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW512x128_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW512x128_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW512x128_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW512x128_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW512x128_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-SRAM1RW512x128_1bit sram_IO50 ( CE, WEB,  A, OEB, CSB, I[50], O[50]);
-SRAM1RW512x128_1bit sram_IO51 ( CE, WEB,  A, OEB, CSB, I[51], O[51]);
-SRAM1RW512x128_1bit sram_IO52 ( CE, WEB,  A, OEB, CSB, I[52], O[52]);
-SRAM1RW512x128_1bit sram_IO53 ( CE, WEB,  A, OEB, CSB, I[53], O[53]);
-SRAM1RW512x128_1bit sram_IO54 ( CE, WEB,  A, OEB, CSB, I[54], O[54]);
-SRAM1RW512x128_1bit sram_IO55 ( CE, WEB,  A, OEB, CSB, I[55], O[55]);
-SRAM1RW512x128_1bit sram_IO56 ( CE, WEB,  A, OEB, CSB, I[56], O[56]);
-SRAM1RW512x128_1bit sram_IO57 ( CE, WEB,  A, OEB, CSB, I[57], O[57]);
-SRAM1RW512x128_1bit sram_IO58 ( CE, WEB,  A, OEB, CSB, I[58], O[58]);
-SRAM1RW512x128_1bit sram_IO59 ( CE, WEB,  A, OEB, CSB, I[59], O[59]);
-SRAM1RW512x128_1bit sram_IO60 ( CE, WEB,  A, OEB, CSB, I[60], O[60]);
-SRAM1RW512x128_1bit sram_IO61 ( CE, WEB,  A, OEB, CSB, I[61], O[61]);
-SRAM1RW512x128_1bit sram_IO62 ( CE, WEB,  A, OEB, CSB, I[62], O[62]);
-SRAM1RW512x128_1bit sram_IO63 ( CE, WEB,  A, OEB, CSB, I[63], O[63]);
-SRAM1RW512x128_1bit sram_IO64 ( CE, WEB,  A, OEB, CSB, I[64], O[64]);
-SRAM1RW512x128_1bit sram_IO65 ( CE, WEB,  A, OEB, CSB, I[65], O[65]);
-SRAM1RW512x128_1bit sram_IO66 ( CE, WEB,  A, OEB, CSB, I[66], O[66]);
-SRAM1RW512x128_1bit sram_IO67 ( CE, WEB,  A, OEB, CSB, I[67], O[67]);
-SRAM1RW512x128_1bit sram_IO68 ( CE, WEB,  A, OEB, CSB, I[68], O[68]);
-SRAM1RW512x128_1bit sram_IO69 ( CE, WEB,  A, OEB, CSB, I[69], O[69]);
-SRAM1RW512x128_1bit sram_IO70 ( CE, WEB,  A, OEB, CSB, I[70], O[70]);
-SRAM1RW512x128_1bit sram_IO71 ( CE, WEB,  A, OEB, CSB, I[71], O[71]);
-SRAM1RW512x128_1bit sram_IO72 ( CE, WEB,  A, OEB, CSB, I[72], O[72]);
-SRAM1RW512x128_1bit sram_IO73 ( CE, WEB,  A, OEB, CSB, I[73], O[73]);
-SRAM1RW512x128_1bit sram_IO74 ( CE, WEB,  A, OEB, CSB, I[74], O[74]);
-SRAM1RW512x128_1bit sram_IO75 ( CE, WEB,  A, OEB, CSB, I[75], O[75]);
-SRAM1RW512x128_1bit sram_IO76 ( CE, WEB,  A, OEB, CSB, I[76], O[76]);
-SRAM1RW512x128_1bit sram_IO77 ( CE, WEB,  A, OEB, CSB, I[77], O[77]);
-SRAM1RW512x128_1bit sram_IO78 ( CE, WEB,  A, OEB, CSB, I[78], O[78]);
-SRAM1RW512x128_1bit sram_IO79 ( CE, WEB,  A, OEB, CSB, I[79], O[79]);
-SRAM1RW512x128_1bit sram_IO80 ( CE, WEB,  A, OEB, CSB, I[80], O[80]);
-SRAM1RW512x128_1bit sram_IO81 ( CE, WEB,  A, OEB, CSB, I[81], O[81]);
-SRAM1RW512x128_1bit sram_IO82 ( CE, WEB,  A, OEB, CSB, I[82], O[82]);
-SRAM1RW512x128_1bit sram_IO83 ( CE, WEB,  A, OEB, CSB, I[83], O[83]);
-SRAM1RW512x128_1bit sram_IO84 ( CE, WEB,  A, OEB, CSB, I[84], O[84]);
-SRAM1RW512x128_1bit sram_IO85 ( CE, WEB,  A, OEB, CSB, I[85], O[85]);
-SRAM1RW512x128_1bit sram_IO86 ( CE, WEB,  A, OEB, CSB, I[86], O[86]);
-SRAM1RW512x128_1bit sram_IO87 ( CE, WEB,  A, OEB, CSB, I[87], O[87]);
-SRAM1RW512x128_1bit sram_IO88 ( CE, WEB,  A, OEB, CSB, I[88], O[88]);
-SRAM1RW512x128_1bit sram_IO89 ( CE, WEB,  A, OEB, CSB, I[89], O[89]);
-SRAM1RW512x128_1bit sram_IO90 ( CE, WEB,  A, OEB, CSB, I[90], O[90]);
-SRAM1RW512x128_1bit sram_IO91 ( CE, WEB,  A, OEB, CSB, I[91], O[91]);
-SRAM1RW512x128_1bit sram_IO92 ( CE, WEB,  A, OEB, CSB, I[92], O[92]);
-SRAM1RW512x128_1bit sram_IO93 ( CE, WEB,  A, OEB, CSB, I[93], O[93]);
-SRAM1RW512x128_1bit sram_IO94 ( CE, WEB,  A, OEB, CSB, I[94], O[94]);
-SRAM1RW512x128_1bit sram_IO95 ( CE, WEB,  A, OEB, CSB, I[95], O[95]);
-SRAM1RW512x128_1bit sram_IO96 ( CE, WEB,  A, OEB, CSB, I[96], O[96]);
-SRAM1RW512x128_1bit sram_IO97 ( CE, WEB,  A, OEB, CSB, I[97], O[97]);
-SRAM1RW512x128_1bit sram_IO98 ( CE, WEB,  A, OEB, CSB, I[98], O[98]);
-SRAM1RW512x128_1bit sram_IO99 ( CE, WEB,  A, OEB, CSB, I[99], O[99]);
-SRAM1RW512x128_1bit sram_IO100 ( CE, WEB,  A, OEB, CSB, I[100], O[100]);
-SRAM1RW512x128_1bit sram_IO101 ( CE, WEB,  A, OEB, CSB, I[101], O[101]);
-SRAM1RW512x128_1bit sram_IO102 ( CE, WEB,  A, OEB, CSB, I[102], O[102]);
-SRAM1RW512x128_1bit sram_IO103 ( CE, WEB,  A, OEB, CSB, I[103], O[103]);
-SRAM1RW512x128_1bit sram_IO104 ( CE, WEB,  A, OEB, CSB, I[104], O[104]);
-SRAM1RW512x128_1bit sram_IO105 ( CE, WEB,  A, OEB, CSB, I[105], O[105]);
-SRAM1RW512x128_1bit sram_IO106 ( CE, WEB,  A, OEB, CSB, I[106], O[106]);
-SRAM1RW512x128_1bit sram_IO107 ( CE, WEB,  A, OEB, CSB, I[107], O[107]);
-SRAM1RW512x128_1bit sram_IO108 ( CE, WEB,  A, OEB, CSB, I[108], O[108]);
-SRAM1RW512x128_1bit sram_IO109 ( CE, WEB,  A, OEB, CSB, I[109], O[109]);
-SRAM1RW512x128_1bit sram_IO110 ( CE, WEB,  A, OEB, CSB, I[110], O[110]);
-SRAM1RW512x128_1bit sram_IO111 ( CE, WEB,  A, OEB, CSB, I[111], O[111]);
-SRAM1RW512x128_1bit sram_IO112 ( CE, WEB,  A, OEB, CSB, I[112], O[112]);
-SRAM1RW512x128_1bit sram_IO113 ( CE, WEB,  A, OEB, CSB, I[113], O[113]);
-SRAM1RW512x128_1bit sram_IO114 ( CE, WEB,  A, OEB, CSB, I[114], O[114]);
-SRAM1RW512x128_1bit sram_IO115 ( CE, WEB,  A, OEB, CSB, I[115], O[115]);
-SRAM1RW512x128_1bit sram_IO116 ( CE, WEB,  A, OEB, CSB, I[116], O[116]);
-SRAM1RW512x128_1bit sram_IO117 ( CE, WEB,  A, OEB, CSB, I[117], O[117]);
-SRAM1RW512x128_1bit sram_IO118 ( CE, WEB,  A, OEB, CSB, I[118], O[118]);
-SRAM1RW512x128_1bit sram_IO119 ( CE, WEB,  A, OEB, CSB, I[119], O[119]);
-SRAM1RW512x128_1bit sram_IO120 ( CE, WEB,  A, OEB, CSB, I[120], O[120]);
-SRAM1RW512x128_1bit sram_IO121 ( CE, WEB,  A, OEB, CSB, I[121], O[121]);
-SRAM1RW512x128_1bit sram_IO122 ( CE, WEB,  A, OEB, CSB, I[122], O[122]);
-SRAM1RW512x128_1bit sram_IO123 ( CE, WEB,  A, OEB, CSB, I[123], O[123]);
-SRAM1RW512x128_1bit sram_IO124 ( CE, WEB,  A, OEB, CSB, I[124], O[124]);
-SRAM1RW512x128_1bit sram_IO125 ( CE, WEB,  A, OEB, CSB, I[125], O[125]);
-SRAM1RW512x128_1bit sram_IO126 ( CE, WEB,  A, OEB, CSB, I[126], O[126]);
-SRAM1RW512x128_1bit sram_IO127 ( CE, WEB,  A, OEB, CSB, I[127], O[127]);
-
-
-endmodule
-
-
-module SRAM1RW512x128_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW512x32.v                                  *
-*  SRAM name     : SRAM1RW512x32                                    *
-*  Word width    : 32    bits                                        *
-*  Word number   : 512                                               *
-*  Adress width  : 9     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 9
-`define numWords 512
-`define wordLength 32
-
-
-module SRAM1RW512x32 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW512x32_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW512x32_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW512x32_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW512x32_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW512x32_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW512x32_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW512x32_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW512x32_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW512x32_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW512x32_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW512x32_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW512x32_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW512x32_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW512x32_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW512x32_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW512x32_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW512x32_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW512x32_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW512x32_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW512x32_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW512x32_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW512x32_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW512x32_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW512x32_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW512x32_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW512x32_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW512x32_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW512x32_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW512x32_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW512x32_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW512x32_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW512x32_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-
-
-endmodule
-
-
-module SRAM1RW512x32_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW512x64.v                                 *
-*  SRAM name     : SRAM1RW512x64                                   *
-*  Word width    : 64   bits                                        *
-*  Word number   : 512                                               *
-*  Adress width  : 9     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 9
-`define numWords 512
-`define wordLength 64
-
-
-module SRAM1RW512x64 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW512x64_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW512x64_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW512x64_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW512x64_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW512x64_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW512x64_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW512x64_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW512x64_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW512x64_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW512x64_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW512x64_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW512x64_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW512x64_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW512x64_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW512x64_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW512x64_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW512x64_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW512x64_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW512x64_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW512x64_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW512x64_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW512x64_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW512x64_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW512x64_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW512x64_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW512x64_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW512x64_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW512x64_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW512x64_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW512x64_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW512x64_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW512x64_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW512x64_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW512x64_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW512x64_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW512x64_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW512x64_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW512x64_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW512x64_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW512x64_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW512x64_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW512x64_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW512x64_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW512x64_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW512x64_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW512x64_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW512x64_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW512x64_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW512x64_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW512x64_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-SRAM1RW512x64_1bit sram_IO50 ( CE, WEB,  A, OEB, CSB, I[50], O[50]);
-SRAM1RW512x64_1bit sram_IO51 ( CE, WEB,  A, OEB, CSB, I[51], O[51]);
-SRAM1RW512x64_1bit sram_IO52 ( CE, WEB,  A, OEB, CSB, I[52], O[52]);
-SRAM1RW512x64_1bit sram_IO53 ( CE, WEB,  A, OEB, CSB, I[53], O[53]);
-SRAM1RW512x64_1bit sram_IO54 ( CE, WEB,  A, OEB, CSB, I[54], O[54]);
-SRAM1RW512x64_1bit sram_IO55 ( CE, WEB,  A, OEB, CSB, I[55], O[55]);
-SRAM1RW512x64_1bit sram_IO56 ( CE, WEB,  A, OEB, CSB, I[56], O[56]);
-SRAM1RW512x64_1bit sram_IO57 ( CE, WEB,  A, OEB, CSB, I[57], O[57]);
-SRAM1RW512x64_1bit sram_IO58 ( CE, WEB,  A, OEB, CSB, I[58], O[58]);
-SRAM1RW512x64_1bit sram_IO59 ( CE, WEB,  A, OEB, CSB, I[59], O[59]);
-SRAM1RW512x64_1bit sram_IO60 ( CE, WEB,  A, OEB, CSB, I[60], O[60]);
-SRAM1RW512x64_1bit sram_IO61 ( CE, WEB,  A, OEB, CSB, I[61], O[61]);
-SRAM1RW512x64_1bit sram_IO62 ( CE, WEB,  A, OEB, CSB, I[62], O[62]);
-SRAM1RW512x64_1bit sram_IO63 ( CE, WEB,  A, OEB, CSB, I[63], O[63]);
-
-
-endmodule
-
-
-module SRAM1RW512x64_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW512x8.v                                   *
-*  SRAM name     : SRAM1RW512x8                                     *
-*  Word width    : 8     bits                                        *
-*  Word number   : 512                                               *
-*  Adress width  : 9     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 9
-`define numWords 512
-`define wordLength 8
-
-
-module SRAM1RW512x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW512x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW512x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW512x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW512x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW512x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW512x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW512x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW512x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW512x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x128.v                                  *
-*  SRAM name     : SRAM1RW64x128                                    *
-*  Word width    : 128   bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 128
-
-
-module SRAM1RW64x128 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x128_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x128_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x128_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x128_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x128_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x128_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x128_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x128_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x128_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x128_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x128_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x128_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x128_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x128_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x128_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x128_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x128_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x128_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x128_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x128_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW64x128_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW64x128_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW64x128_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW64x128_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW64x128_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW64x128_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW64x128_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW64x128_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW64x128_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW64x128_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW64x128_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW64x128_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW64x128_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW64x128_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-SRAM1RW64x128_1bit sram_IO34 ( CE, WEB,  A, OEB, CSB, I[34], O[34]);
-SRAM1RW64x128_1bit sram_IO35 ( CE, WEB,  A, OEB, CSB, I[35], O[35]);
-SRAM1RW64x128_1bit sram_IO36 ( CE, WEB,  A, OEB, CSB, I[36], O[36]);
-SRAM1RW64x128_1bit sram_IO37 ( CE, WEB,  A, OEB, CSB, I[37], O[37]);
-SRAM1RW64x128_1bit sram_IO38 ( CE, WEB,  A, OEB, CSB, I[38], O[38]);
-SRAM1RW64x128_1bit sram_IO39 ( CE, WEB,  A, OEB, CSB, I[39], O[39]);
-SRAM1RW64x128_1bit sram_IO40 ( CE, WEB,  A, OEB, CSB, I[40], O[40]);
-SRAM1RW64x128_1bit sram_IO41 ( CE, WEB,  A, OEB, CSB, I[41], O[41]);
-SRAM1RW64x128_1bit sram_IO42 ( CE, WEB,  A, OEB, CSB, I[42], O[42]);
-SRAM1RW64x128_1bit sram_IO43 ( CE, WEB,  A, OEB, CSB, I[43], O[43]);
-SRAM1RW64x128_1bit sram_IO44 ( CE, WEB,  A, OEB, CSB, I[44], O[44]);
-SRAM1RW64x128_1bit sram_IO45 ( CE, WEB,  A, OEB, CSB, I[45], O[45]);
-SRAM1RW64x128_1bit sram_IO46 ( CE, WEB,  A, OEB, CSB, I[46], O[46]);
-SRAM1RW64x128_1bit sram_IO47 ( CE, WEB,  A, OEB, CSB, I[47], O[47]);
-SRAM1RW64x128_1bit sram_IO48 ( CE, WEB,  A, OEB, CSB, I[48], O[48]);
-SRAM1RW64x128_1bit sram_IO49 ( CE, WEB,  A, OEB, CSB, I[49], O[49]);
-SRAM1RW64x128_1bit sram_IO50 ( CE, WEB,  A, OEB, CSB, I[50], O[50]);
-SRAM1RW64x128_1bit sram_IO51 ( CE, WEB,  A, OEB, CSB, I[51], O[51]);
-SRAM1RW64x128_1bit sram_IO52 ( CE, WEB,  A, OEB, CSB, I[52], O[52]);
-SRAM1RW64x128_1bit sram_IO53 ( CE, WEB,  A, OEB, CSB, I[53], O[53]);
-SRAM1RW64x128_1bit sram_IO54 ( CE, WEB,  A, OEB, CSB, I[54], O[54]);
-SRAM1RW64x128_1bit sram_IO55 ( CE, WEB,  A, OEB, CSB, I[55], O[55]);
-SRAM1RW64x128_1bit sram_IO56 ( CE, WEB,  A, OEB, CSB, I[56], O[56]);
-SRAM1RW64x128_1bit sram_IO57 ( CE, WEB,  A, OEB, CSB, I[57], O[57]);
-SRAM1RW64x128_1bit sram_IO58 ( CE, WEB,  A, OEB, CSB, I[58], O[58]);
-SRAM1RW64x128_1bit sram_IO59 ( CE, WEB,  A, OEB, CSB, I[59], O[59]);
-SRAM1RW64x128_1bit sram_IO60 ( CE, WEB,  A, OEB, CSB, I[60], O[60]);
-SRAM1RW64x128_1bit sram_IO61 ( CE, WEB,  A, OEB, CSB, I[61], O[61]);
-SRAM1RW64x128_1bit sram_IO62 ( CE, WEB,  A, OEB, CSB, I[62], O[62]);
-SRAM1RW64x128_1bit sram_IO63 ( CE, WEB,  A, OEB, CSB, I[63], O[63]);
-SRAM1RW64x128_1bit sram_IO64 ( CE, WEB,  A, OEB, CSB, I[64], O[64]);
-SRAM1RW64x128_1bit sram_IO65 ( CE, WEB,  A, OEB, CSB, I[65], O[65]);
-SRAM1RW64x128_1bit sram_IO66 ( CE, WEB,  A, OEB, CSB, I[66], O[66]);
-SRAM1RW64x128_1bit sram_IO67 ( CE, WEB,  A, OEB, CSB, I[67], O[67]);
-SRAM1RW64x128_1bit sram_IO68 ( CE, WEB,  A, OEB, CSB, I[68], O[68]);
-SRAM1RW64x128_1bit sram_IO69 ( CE, WEB,  A, OEB, CSB, I[69], O[69]);
-SRAM1RW64x128_1bit sram_IO70 ( CE, WEB,  A, OEB, CSB, I[70], O[70]);
-SRAM1RW64x128_1bit sram_IO71 ( CE, WEB,  A, OEB, CSB, I[71], O[71]);
-SRAM1RW64x128_1bit sram_IO72 ( CE, WEB,  A, OEB, CSB, I[72], O[72]);
-SRAM1RW64x128_1bit sram_IO73 ( CE, WEB,  A, OEB, CSB, I[73], O[73]);
-SRAM1RW64x128_1bit sram_IO74 ( CE, WEB,  A, OEB, CSB, I[74], O[74]);
-SRAM1RW64x128_1bit sram_IO75 ( CE, WEB,  A, OEB, CSB, I[75], O[75]);
-SRAM1RW64x128_1bit sram_IO76 ( CE, WEB,  A, OEB, CSB, I[76], O[76]);
-SRAM1RW64x128_1bit sram_IO77 ( CE, WEB,  A, OEB, CSB, I[77], O[77]);
-SRAM1RW64x128_1bit sram_IO78 ( CE, WEB,  A, OEB, CSB, I[78], O[78]);
-SRAM1RW64x128_1bit sram_IO79 ( CE, WEB,  A, OEB, CSB, I[79], O[79]);
-SRAM1RW64x128_1bit sram_IO80 ( CE, WEB,  A, OEB, CSB, I[80], O[80]);
-SRAM1RW64x128_1bit sram_IO81 ( CE, WEB,  A, OEB, CSB, I[81], O[81]);
-SRAM1RW64x128_1bit sram_IO82 ( CE, WEB,  A, OEB, CSB, I[82], O[82]);
-SRAM1RW64x128_1bit sram_IO83 ( CE, WEB,  A, OEB, CSB, I[83], O[83]);
-SRAM1RW64x128_1bit sram_IO84 ( CE, WEB,  A, OEB, CSB, I[84], O[84]);
-SRAM1RW64x128_1bit sram_IO85 ( CE, WEB,  A, OEB, CSB, I[85], O[85]);
-SRAM1RW64x128_1bit sram_IO86 ( CE, WEB,  A, OEB, CSB, I[86], O[86]);
-SRAM1RW64x128_1bit sram_IO87 ( CE, WEB,  A, OEB, CSB, I[87], O[87]);
-SRAM1RW64x128_1bit sram_IO88 ( CE, WEB,  A, OEB, CSB, I[88], O[88]);
-SRAM1RW64x128_1bit sram_IO89 ( CE, WEB,  A, OEB, CSB, I[89], O[89]);
-SRAM1RW64x128_1bit sram_IO90 ( CE, WEB,  A, OEB, CSB, I[90], O[90]);
-SRAM1RW64x128_1bit sram_IO91 ( CE, WEB,  A, OEB, CSB, I[91], O[91]);
-SRAM1RW64x128_1bit sram_IO92 ( CE, WEB,  A, OEB, CSB, I[92], O[92]);
-SRAM1RW64x128_1bit sram_IO93 ( CE, WEB,  A, OEB, CSB, I[93], O[93]);
-SRAM1RW64x128_1bit sram_IO94 ( CE, WEB,  A, OEB, CSB, I[94], O[94]);
-SRAM1RW64x128_1bit sram_IO95 ( CE, WEB,  A, OEB, CSB, I[95], O[95]);
-SRAM1RW64x128_1bit sram_IO96 ( CE, WEB,  A, OEB, CSB, I[96], O[96]);
-SRAM1RW64x128_1bit sram_IO97 ( CE, WEB,  A, OEB, CSB, I[97], O[97]);
-SRAM1RW64x128_1bit sram_IO98 ( CE, WEB,  A, OEB, CSB, I[98], O[98]);
-SRAM1RW64x128_1bit sram_IO99 ( CE, WEB,  A, OEB, CSB, I[99], O[99]);
-SRAM1RW64x128_1bit sram_IO100 ( CE, WEB,  A, OEB, CSB, I[100], O[100]);
-SRAM1RW64x128_1bit sram_IO101 ( CE, WEB,  A, OEB, CSB, I[101], O[101]);
-SRAM1RW64x128_1bit sram_IO102 ( CE, WEB,  A, OEB, CSB, I[102], O[102]);
-SRAM1RW64x128_1bit sram_IO103 ( CE, WEB,  A, OEB, CSB, I[103], O[103]);
-SRAM1RW64x128_1bit sram_IO104 ( CE, WEB,  A, OEB, CSB, I[104], O[104]);
-SRAM1RW64x128_1bit sram_IO105 ( CE, WEB,  A, OEB, CSB, I[105], O[105]);
-SRAM1RW64x128_1bit sram_IO106 ( CE, WEB,  A, OEB, CSB, I[106], O[106]);
-SRAM1RW64x128_1bit sram_IO107 ( CE, WEB,  A, OEB, CSB, I[107], O[107]);
-SRAM1RW64x128_1bit sram_IO108 ( CE, WEB,  A, OEB, CSB, I[108], O[108]);
-SRAM1RW64x128_1bit sram_IO109 ( CE, WEB,  A, OEB, CSB, I[109], O[109]);
-SRAM1RW64x128_1bit sram_IO110 ( CE, WEB,  A, OEB, CSB, I[110], O[110]);
-SRAM1RW64x128_1bit sram_IO111 ( CE, WEB,  A, OEB, CSB, I[111], O[111]);
-SRAM1RW64x128_1bit sram_IO112 ( CE, WEB,  A, OEB, CSB, I[112], O[112]);
-SRAM1RW64x128_1bit sram_IO113 ( CE, WEB,  A, OEB, CSB, I[113], O[113]);
-SRAM1RW64x128_1bit sram_IO114 ( CE, WEB,  A, OEB, CSB, I[114], O[114]);
-SRAM1RW64x128_1bit sram_IO115 ( CE, WEB,  A, OEB, CSB, I[115], O[115]);
-SRAM1RW64x128_1bit sram_IO116 ( CE, WEB,  A, OEB, CSB, I[116], O[116]);
-SRAM1RW64x128_1bit sram_IO117 ( CE, WEB,  A, OEB, CSB, I[117], O[117]);
-SRAM1RW64x128_1bit sram_IO118 ( CE, WEB,  A, OEB, CSB, I[118], O[118]);
-SRAM1RW64x128_1bit sram_IO119 ( CE, WEB,  A, OEB, CSB, I[119], O[119]);
-SRAM1RW64x128_1bit sram_IO120 ( CE, WEB,  A, OEB, CSB, I[120], O[120]);
-SRAM1RW64x128_1bit sram_IO121 ( CE, WEB,  A, OEB, CSB, I[121], O[121]);
-SRAM1RW64x128_1bit sram_IO122 ( CE, WEB,  A, OEB, CSB, I[122], O[122]);
-SRAM1RW64x128_1bit sram_IO123 ( CE, WEB,  A, OEB, CSB, I[123], O[123]);
-SRAM1RW64x128_1bit sram_IO124 ( CE, WEB,  A, OEB, CSB, I[124], O[124]);
-SRAM1RW64x128_1bit sram_IO125 ( CE, WEB,  A, OEB, CSB, I[125], O[125]);
-SRAM1RW64x128_1bit sram_IO126 ( CE, WEB,  A, OEB, CSB, I[126], O[126]);
-SRAM1RW64x128_1bit sram_IO127 ( CE, WEB,  A, OEB, CSB, I[127], O[127]);
-
-
-endmodule
-
-
-module SRAM1RW64x128_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x20.v                                   *
-*  SRAM name     : SRAM1RW64x20                                     *
-*  Word width    : 20    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 20
-
-
-module SRAM1RW64x20 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x20_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x20_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x20_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x20_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x20_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x20_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x20_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x20_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x20_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x20_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x20_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x20_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x20_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x20_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x20_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x20_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x20_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x20_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x20_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x20_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-
-
-endmodule
-
-
-module SRAM1RW64x20_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x21.v                                   *
-*  SRAM name     : SRAM1RW64x21                                     *
-*  Word width    : 21    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 21
-
-
-module SRAM1RW64x21 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x21_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x21_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x21_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x21_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x21_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x21_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x21_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x21_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x21_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x21_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x21_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x21_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x21_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x21_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x21_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x21_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x21_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x21_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x21_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x21_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW64x21_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-
-
-endmodule
-
-
-module SRAM1RW64x21_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x22.v                                   *
-*  SRAM name     : SRAM1RW64x22                                     *
-*  Word width    : 22    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 22
-
-
-module SRAM1RW64x22 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x22_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x22_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x22_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x22_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x22_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x22_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x22_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x22_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x22_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x22_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x22_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x22_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x22_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x22_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x22_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x22_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x22_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x22_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x22_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x22_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW64x22_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW64x22_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-
-
-endmodule
-
-
-module SRAM1RW64x22_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x32.v                                   *
-*  SRAM name     : SRAM1RW64x32                                     *
-*  Word width    : 32    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 32
-
-
-module SRAM1RW64x32 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x32_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x32_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x32_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x32_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x32_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x32_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x32_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x32_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x32_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x32_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x32_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x32_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x32_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x32_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x32_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x32_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x32_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x32_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x32_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x32_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW64x32_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW64x32_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW64x32_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW64x32_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW64x32_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW64x32_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW64x32_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW64x32_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW64x32_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW64x32_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW64x32_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW64x32_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-
-
-endmodule
-
-
-module SRAM1RW64x32_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x34.v                                   *
-*  SRAM name     : SRAM1RW64x34                                     *
-*  Word width    : 34    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 34
-
-
-module SRAM1RW64x34 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x34_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x34_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x34_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x34_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x34_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x34_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x34_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x34_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-SRAM1RW64x34_1bit sram_IO8 ( CE, WEB,  A, OEB, CSB, I[8], O[8]);
-SRAM1RW64x34_1bit sram_IO9 ( CE, WEB,  A, OEB, CSB, I[9], O[9]);
-SRAM1RW64x34_1bit sram_IO10 ( CE, WEB,  A, OEB, CSB, I[10], O[10]);
-SRAM1RW64x34_1bit sram_IO11 ( CE, WEB,  A, OEB, CSB, I[11], O[11]);
-SRAM1RW64x34_1bit sram_IO12 ( CE, WEB,  A, OEB, CSB, I[12], O[12]);
-SRAM1RW64x34_1bit sram_IO13 ( CE, WEB,  A, OEB, CSB, I[13], O[13]);
-SRAM1RW64x34_1bit sram_IO14 ( CE, WEB,  A, OEB, CSB, I[14], O[14]);
-SRAM1RW64x34_1bit sram_IO15 ( CE, WEB,  A, OEB, CSB, I[15], O[15]);
-SRAM1RW64x34_1bit sram_IO16 ( CE, WEB,  A, OEB, CSB, I[16], O[16]);
-SRAM1RW64x34_1bit sram_IO17 ( CE, WEB,  A, OEB, CSB, I[17], O[17]);
-SRAM1RW64x34_1bit sram_IO18 ( CE, WEB,  A, OEB, CSB, I[18], O[18]);
-SRAM1RW64x34_1bit sram_IO19 ( CE, WEB,  A, OEB, CSB, I[19], O[19]);
-SRAM1RW64x34_1bit sram_IO20 ( CE, WEB,  A, OEB, CSB, I[20], O[20]);
-SRAM1RW64x34_1bit sram_IO21 ( CE, WEB,  A, OEB, CSB, I[21], O[21]);
-SRAM1RW64x34_1bit sram_IO22 ( CE, WEB,  A, OEB, CSB, I[22], O[22]);
-SRAM1RW64x34_1bit sram_IO23 ( CE, WEB,  A, OEB, CSB, I[23], O[23]);
-SRAM1RW64x34_1bit sram_IO24 ( CE, WEB,  A, OEB, CSB, I[24], O[24]);
-SRAM1RW64x34_1bit sram_IO25 ( CE, WEB,  A, OEB, CSB, I[25], O[25]);
-SRAM1RW64x34_1bit sram_IO26 ( CE, WEB,  A, OEB, CSB, I[26], O[26]);
-SRAM1RW64x34_1bit sram_IO27 ( CE, WEB,  A, OEB, CSB, I[27], O[27]);
-SRAM1RW64x34_1bit sram_IO28 ( CE, WEB,  A, OEB, CSB, I[28], O[28]);
-SRAM1RW64x34_1bit sram_IO29 ( CE, WEB,  A, OEB, CSB, I[29], O[29]);
-SRAM1RW64x34_1bit sram_IO30 ( CE, WEB,  A, OEB, CSB, I[30], O[30]);
-SRAM1RW64x34_1bit sram_IO31 ( CE, WEB,  A, OEB, CSB, I[31], O[31]);
-SRAM1RW64x34_1bit sram_IO32 ( CE, WEB,  A, OEB, CSB, I[32], O[32]);
-SRAM1RW64x34_1bit sram_IO33 ( CE, WEB,  A, OEB, CSB, I[33], O[33]);
-
-
-endmodule
-
-
-module SRAM1RW64x34_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM1RW64x8.v                                    *
-*  SRAM name     : SRAM1RW64x8                                      *
-*  Word width    : 8     bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 8
-
-
-module SRAM1RW64x8 (A,CE,WEB,OEB,CSB,I,O);
-
-input 				CE;
-input 				WEB;
-input 				OEB;
-input 				CSB;
-
-input 	[`numAddr-1:0] 		A;
-input 	[`wordLength-1:0] 	I;
-output 	[`wordLength-1:0] 	O;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out;*/
-wire 	[`wordLength-1:0] 	O;
-
-wire 				RE;
-wire 				WE;
-
-SRAM1RW64x8_1bit sram_IO0 ( CE, WEB,  A, OEB, CSB, I[0], O[0]);
-SRAM1RW64x8_1bit sram_IO1 ( CE, WEB,  A, OEB, CSB, I[1], O[1]);
-SRAM1RW64x8_1bit sram_IO2 ( CE, WEB,  A, OEB, CSB, I[2], O[2]);
-SRAM1RW64x8_1bit sram_IO3 ( CE, WEB,  A, OEB, CSB, I[3], O[3]);
-SRAM1RW64x8_1bit sram_IO4 ( CE, WEB,  A, OEB, CSB, I[4], O[4]);
-SRAM1RW64x8_1bit sram_IO5 ( CE, WEB,  A, OEB, CSB, I[5], O[5]);
-SRAM1RW64x8_1bit sram_IO6 ( CE, WEB,  A, OEB, CSB, I[6], O[6]);
-SRAM1RW64x8_1bit sram_IO7 ( CE, WEB,  A, OEB, CSB, I[7], O[7]);
-
-
-endmodule
-
-
-module SRAM1RW64x8_1bit (CE_i, WEB_i,  A_i, OEB_i, CSB_i, I_i, O_i);
-
-input CSB_i;
-input OEB_i;
-input CE_i;
-input WEB_i;
-
-input 	[`numAddr-1:0] 	A_i;
-input 	[0:0] I_i;
-
-output 	[0:0] O_i;
-
-reg 	[0:0]O_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out;
-
-
-// Write Mode
-wire RE;
-wire WE;
-and u1 (RE, ~CSB_i,  WEB_i);
-and u2 (WE, ~CSB_i, ~WEB_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out = $urandom_range(1);
-end
-
-always @ (posedge CE_i) 
-	if (RE)
-		data_out = memory[A_i];
-always @ (posedge CE_i) 
-	if (WE)
-		memory[A_i] = I_i;
-		
-
-always @ (posedge CE_i)
-	if (!OEB_i) 
-		O_i = data_out;
-	else
-		O_i =  1'bz;
-
-
-endmodule
-
-
-/*********************************************************************
-*  Filename      : SRAM2RW128x16.v                                      *
-*  SRAM name     : SRAM2RW128x16                                        *
-*  Word width    : 16    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 16
-
-
-
-module SRAM2RW128x16 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW128x16_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW128x16_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW128x16_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW128x16_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW128x16_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW128x16_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW128x16_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW128x16_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW128x16_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW128x16_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW128x16_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW128x16_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW128x16_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW128x16_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW128x16_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW128x16_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-
-
-endmodule
-
-
-module SRAM2RW128x16_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW128x32.v                                      *
-*  SRAM name     : SRAM2RW128x32                                        *
-*  Word width    : 32    bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 32
-
-
-
-module SRAM2RW128x32 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW128x32_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW128x32_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW128x32_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW128x32_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW128x32_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW128x32_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW128x32_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW128x32_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW128x32_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW128x32_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW128x32_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW128x32_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW128x32_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW128x32_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW128x32_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW128x32_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW128x32_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW128x32_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW128x32_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW128x32_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW128x32_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW128x32_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW128x32_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW128x32_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW128x32_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW128x32_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW128x32_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW128x32_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW128x32_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW128x32_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW128x32_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW128x32_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-
-
-endmodule
-
-
-module SRAM2RW128x32_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW128x4.v                                       *
-*  SRAM name     : SRAM2RW128x4                                         *
-*  Word width    : 4     bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 4
-
-
-
-module SRAM2RW128x4 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW128x4_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW128x4_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW128x4_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW128x4_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-
-
-endmodule
-
-
-module SRAM2RW128x4_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW128x8.v                                       *
-*  SRAM name     : SRAM2RW128x8                                         *
-*  Word width    : 8     bits                                        *
-*  Word number   : 128                                               *
-*  Adress width  : 7     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 7
-`define numWords 128
-`define wordLength 8
-
-
-
-module SRAM2RW128x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW128x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW128x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW128x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW128x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW128x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW128x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW128x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW128x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-
-
-endmodule
-
-
-module SRAM2RW128x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW16x16.v                                       *
-*  SRAM name     : SRAM2RW16x16                                         *
-*  Word width    : 16    bits                                        *
-*  Word number   : 16                                                *
-*  Adress width  : 4     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 4
-`define numWords 16
-`define wordLength 16
-
-
-
-module SRAM2RW16x16 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW16x16_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW16x16_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW16x16_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW16x16_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW16x16_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW16x16_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW16x16_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW16x16_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW16x16_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW16x16_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW16x16_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW16x16_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW16x16_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW16x16_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW16x16_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW16x16_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-
-
-endmodule
-
-
-module SRAM2RW16x16_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW16x32.v                                       *
-*  SRAM name     : SRAM2RW16x32                                         *
-*  Word width    : 32    bits                                        *
-*  Word number   : 16                                                *
-*  Adress width  : 4     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 4
-`define numWords 16
-`define wordLength 32
-
-
-
-module SRAM2RW16x32 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW16x32_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW16x32_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW16x32_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW16x32_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW16x32_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW16x32_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW16x32_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW16x32_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW16x32_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW16x32_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW16x32_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW16x32_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW16x32_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW16x32_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW16x32_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW16x32_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW16x32_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW16x32_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW16x32_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW16x32_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW16x32_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW16x32_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW16x32_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW16x32_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW16x32_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW16x32_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW16x32_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW16x32_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW16x32_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW16x32_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW16x32_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW16x32_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-
-
-endmodule
-
-
-module SRAM2RW16x32_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW16x4.v                                        *
-*  SRAM name     : SRAM2RW16x4                                          *
-*  Word width    : 4     bits                                        *
-*  Word number   : 16                                                *
-*  Adress width  : 4     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 4
-`define numWords 16
-`define wordLength 4
-
-
-
-module SRAM2RW16x4 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW16x4_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW16x4_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW16x4_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW16x4_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-
-
-endmodule
-
-
-module SRAM2RW16x4_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW16x8.v                                        *
-*  SRAM name     : SRAM2RW16x8                                          *
-*  Word width    : 8     bits                                        *
-*  Word number   : 16                                                *
-*  Adress width  : 4     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 4
-`define numWords 16
-`define wordLength 8
-
-
-
-module SRAM2RW16x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW16x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW16x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW16x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW16x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW16x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW16x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW16x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW16x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-
-
-endmodule
-
-
-module SRAM2RW16x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x16.v                                       *
-*  SRAM name     : SRAM2RW32x16                                         *
-*  Word width    : 16    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 16
-
-
-
-module SRAM2RW32x16 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x16_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x16_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x16_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x16_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x16_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x16_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x16_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x16_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW32x16_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW32x16_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW32x16_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW32x16_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW32x16_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW32x16_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW32x16_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW32x16_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-
-
-endmodule
-
-
-module SRAM2RW32x16_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x22.v                                       *
-*  SRAM name     : SRAM2RW32x22                                         *
-*  Word width    : 22    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 22
-
-
-
-module SRAM2RW32x22 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x22_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x22_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x22_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x22_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x22_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x22_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x22_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x22_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW32x22_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW32x22_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW32x22_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW32x22_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW32x22_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW32x22_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW32x22_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW32x22_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW32x22_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW32x22_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW32x22_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW32x22_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW32x22_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW32x22_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-
-
-endmodule
-
-
-module SRAM2RW32x22_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x32.v                                       *
-*  SRAM name     : SRAM2RW32x32                                         *
-*  Word width    : 32    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 32
-
-
-
-module SRAM2RW32x32 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x32_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x32_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x32_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x32_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x32_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x32_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x32_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x32_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW32x32_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW32x32_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW32x32_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW32x32_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW32x32_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW32x32_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW32x32_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW32x32_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW32x32_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW32x32_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW32x32_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW32x32_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW32x32_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW32x32_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW32x32_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW32x32_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW32x32_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW32x32_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW32x32_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW32x32_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW32x32_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW32x32_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW32x32_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW32x32_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-
-
-endmodule
-
-
-module SRAM2RW32x32_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x33.v                                       *
-*  SRAM name     : SRAM2RW32x33                                         *
-*  Word width    : 33    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 33
-
-
-
-module SRAM2RW32x33 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x33_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x33_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x33_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x33_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x33_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x33_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x33_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x33_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW32x33_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW32x33_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW32x33_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW32x33_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW32x33_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW32x33_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW32x33_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW32x33_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW32x33_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW32x33_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW32x33_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW32x33_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW32x33_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW32x33_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW32x33_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW32x33_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW32x33_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW32x33_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW32x33_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW32x33_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW32x33_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW32x33_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW32x33_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW32x33_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-SRAM2RW32x33_1bit sram_IO32 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[32], I2[32], O1[32], O2[32]);
-
-
-endmodule
-
-
-module SRAM2RW32x33_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x39.v                                       *
-*  SRAM name     : SRAM2RW32x39                                         *
-*  Word width    : 39    bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 39
-
-
-
-module SRAM2RW32x39 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x39_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x39_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x39_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x39_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x39_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x39_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x39_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x39_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW32x39_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW32x39_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW32x39_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW32x39_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW32x39_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW32x39_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW32x39_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW32x39_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW32x39_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW32x39_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW32x39_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW32x39_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW32x39_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW32x39_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW32x39_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW32x39_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW32x39_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW32x39_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW32x39_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW32x39_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW32x39_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW32x39_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW32x39_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW32x39_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-SRAM2RW32x39_1bit sram_IO32 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[32], I2[32], O1[32], O2[32]);
-SRAM2RW32x39_1bit sram_IO33 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[33], I2[33], O1[33], O2[33]);
-SRAM2RW32x39_1bit sram_IO34 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[34], I2[34], O1[34], O2[34]);
-SRAM2RW32x39_1bit sram_IO35 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[35], I2[35], O1[35], O2[35]);
-SRAM2RW32x39_1bit sram_IO36 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[36], I2[36], O1[36], O2[36]);
-SRAM2RW32x39_1bit sram_IO37 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[37], I2[37], O1[37], O2[37]);
-SRAM2RW32x39_1bit sram_IO38 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[38], I2[38], O1[38], O2[38]);
-
-
-endmodule
-
-
-module SRAM2RW32x39_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x4.v                                        *
-*  SRAM name     : SRAM2RW32x4                                          *
-*  Word width    : 4     bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 4
-
-
-
-module SRAM2RW32x4 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x4_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x4_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x4_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x4_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-
-
-endmodule
-
-
-module SRAM2RW32x4_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW32x8.v                                        *
-*  SRAM name     : SRAM2RW32x8                                          *
-*  Word width    : 8     bits                                        *
-*  Word number   : 32                                                *
-*  Adress width  : 5     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 5
-`define numWords 32
-`define wordLength 8
-
-
-
-module SRAM2RW32x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW32x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW32x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW32x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW32x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW32x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW32x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW32x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW32x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-
-
-endmodule
-
-
-module SRAM2RW32x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW64x16.v                                       *
-*  SRAM name     : SRAM2RW64x16                                         *
-*  Word width    : 16    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 16
-
-
-
-module SRAM2RW64x16 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW64x16_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW64x16_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW64x16_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW64x16_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW64x16_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW64x16_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW64x16_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW64x16_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW64x16_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW64x16_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW64x16_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW64x16_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW64x16_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW64x16_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW64x16_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW64x16_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-
-
-endmodule
-
-
-module SRAM2RW64x16_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW64x24.v                                       *
-*  SRAM name     : SRAM2RW64x24                                         *
-*  Word width    : 24    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 24
-
-
-
-module SRAM2RW64x24 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW64x24_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW64x24_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW64x24_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW64x24_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW64x24_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW64x24_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW64x24_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW64x24_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW64x24_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW64x24_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW64x24_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW64x24_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW64x24_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW64x24_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW64x24_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW64x24_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW64x24_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW64x24_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW64x24_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW64x24_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW64x24_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW64x24_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW64x24_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW64x24_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-
-
-endmodule
-
-
-module SRAM2RW64x24_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW64x32.v                                       *
-*  SRAM name     : SRAM2RW64x32                                         *
-*  Word width    : 32    bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 32
-
-
-
-module SRAM2RW64x32 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW64x32_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW64x32_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW64x32_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW64x32_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW64x32_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW64x32_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW64x32_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW64x32_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-SRAM2RW64x32_1bit sram_IO8 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[8], I2[8], O1[8], O2[8]);
-SRAM2RW64x32_1bit sram_IO9 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[9], I2[9], O1[9], O2[9]);
-SRAM2RW64x32_1bit sram_IO10 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[10], I2[10], O1[10], O2[10]);
-SRAM2RW64x32_1bit sram_IO11 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[11], I2[11], O1[11], O2[11]);
-SRAM2RW64x32_1bit sram_IO12 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[12], I2[12], O1[12], O2[12]);
-SRAM2RW64x32_1bit sram_IO13 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[13], I2[13], O1[13], O2[13]);
-SRAM2RW64x32_1bit sram_IO14 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[14], I2[14], O1[14], O2[14]);
-SRAM2RW64x32_1bit sram_IO15 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[15], I2[15], O1[15], O2[15]);
-SRAM2RW64x32_1bit sram_IO16 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[16], I2[16], O1[16], O2[16]);
-SRAM2RW64x32_1bit sram_IO17 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[17], I2[17], O1[17], O2[17]);
-SRAM2RW64x32_1bit sram_IO18 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[18], I2[18], O1[18], O2[18]);
-SRAM2RW64x32_1bit sram_IO19 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[19], I2[19], O1[19], O2[19]);
-SRAM2RW64x32_1bit sram_IO20 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[20], I2[20], O1[20], O2[20]);
-SRAM2RW64x32_1bit sram_IO21 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[21], I2[21], O1[21], O2[21]);
-SRAM2RW64x32_1bit sram_IO22 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[22], I2[22], O1[22], O2[22]);
-SRAM2RW64x32_1bit sram_IO23 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[23], I2[23], O1[23], O2[23]);
-SRAM2RW64x32_1bit sram_IO24 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[24], I2[24], O1[24], O2[24]);
-SRAM2RW64x32_1bit sram_IO25 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[25], I2[25], O1[25], O2[25]);
-SRAM2RW64x32_1bit sram_IO26 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[26], I2[26], O1[26], O2[26]);
-SRAM2RW64x32_1bit sram_IO27 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[27], I2[27], O1[27], O2[27]);
-SRAM2RW64x32_1bit sram_IO28 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[28], I2[28], O1[28], O2[28]);
-SRAM2RW64x32_1bit sram_IO29 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[29], I2[29], O1[29], O2[29]);
-SRAM2RW64x32_1bit sram_IO30 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[30], I2[30], O1[30], O2[30]);
-SRAM2RW64x32_1bit sram_IO31 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[31], I2[31], O1[31], O2[31]);
-
-
-endmodule
-
-
-module SRAM2RW64x32_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW64x4.v                                        *
-*  SRAM name     : SRAM2RW64x4                                          *
-*  Word width    : 4     bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 4
-
-
-
-module SRAM2RW64x4 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW64x4_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW64x4_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW64x4_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW64x4_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-
-
-endmodule
-
-
-module SRAM2RW64x4_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule
-/*********************************************************************
-*  Filename      : SRAM2RW64x8.v                                        *
-*  SRAM name     : SRAM2RW64x8                                          *
-*  Word width    : 8     bits                                        *
-*  Word number   : 64                                                *
-*  Adress width  : 6     bits                                        *
-**********************************************************************/
-
-`timescale 1ns/100fs
-
-`define numAddr 6
-`define numWords 64
-`define wordLength 8
-
-
-
-module SRAM2RW64x8 (A1,A2,CE1,CE2,WEB1,WEB2,OEB1,OEB2,CSB1,CSB2,I1,I2,O1,O2);
-
-input 				CE1;
-input 				CE2;
-input 				WEB1;
-input 				WEB2;
-input 				OEB1;
-input 				OEB2;
-input 				CSB1;
-input 				CSB2;
-
-input 	[`numAddr-1:0] 		A1;
-input 	[`numAddr-1:0] 		A2;
-input 	[`wordLength-1:0] 	I1;
-input 	[`wordLength-1:0] 	I2;
-output 	[`wordLength-1:0] 	O1;
-output 	[`wordLength-1:0] 	O2;
-
-/*reg   [`wordLength-1:0]   	memory[`numWords-1:0];*/
-/*reg  	[`wordLength-1:0]	data_out1;*/
-/*reg  	[`wordLength-1:0]	data_out2;*/
-wire 	[`wordLength-1:0] 	O1;
-wire  	[`wordLength-1:0]	O2;
-	
-wire 				RE1;
-wire 				RE2;	
-wire 				WE1;	
-wire 				WE2;
-
-SRAM2RW64x8_1bit sram_IO0 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[0], I2[0], O1[0], O2[0]);
-SRAM2RW64x8_1bit sram_IO1 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[1], I2[1], O1[1], O2[1]);
-SRAM2RW64x8_1bit sram_IO2 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[2], I2[2], O1[2], O2[2]);
-SRAM2RW64x8_1bit sram_IO3 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[3], I2[3], O1[3], O2[3]);
-SRAM2RW64x8_1bit sram_IO4 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[4], I2[4], O1[4], O2[4]);
-SRAM2RW64x8_1bit sram_IO5 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[5], I2[5], O1[5], O2[5]);
-SRAM2RW64x8_1bit sram_IO6 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[6], I2[6], O1[6], O2[6]);
-SRAM2RW64x8_1bit sram_IO7 ( CE1, CE2, WEB1, WEB2,  A1, A2, OEB1, OEB2, CSB1, CSB2, I1[7], I2[7], O1[7], O2[7]);
-
-
-endmodule
-
-
-module SRAM2RW64x8_1bit (CE1_i, CE2_i, WEB1_i, WEB2_i,  A1_i, A2_i, OEB1_i, OEB2_i, CSB1_i, CSB2_i, I1_i, I2_i, O1_i, O2_i);
-
-input 	CSB1_i, CSB2_i;
-input 	OEB1_i, OEB2_i;
-input 	CE1_i, CE2_i;
-input 	WEB1_i, WEB2_i;
-
-input 	[`numAddr-1:0] 	A1_i, A2_i;
-input 	[0:0] I1_i, I2_i;
-
-output 	[0:0] O1_i, O2_i;
-
-reg 	[0:0] O1_i, O2_i;
-reg    	[0:0]  	memory[`numWords-1:0];
-reg  	[0:0]	data_out1, data_out2;
-
-
-wire RE1;
-wire WE1;
-wire RE2;
-wire WE2;
-and u1 (RE1, ~CSB1_i,  WEB1_i);
-and u2 (WE1, ~CSB1_i, ~WEB1_i);
-and u3 (RE2, ~CSB2_i,  WEB2_i);
-and u4 (WE2, ~CSB2_i, ~WEB2_i);
-
-// Initialization for simulation
-integer i;
-initial begin
-    O1_i = $urandom_range(1);
-    O2_i = $urandom_range(1);
-    for (i = 0; i < `numWords; i = i + 1) begin
-        memory[i] = $urandom_range(1);
-    end
-    data_out1 = $urandom_range(1);
-    data_out2 = $urandom_range(1);
-end
-
-//Primary ports
-
-always @ (posedge CE1_i) 
-	if (RE1)
-		data_out1 = memory[A1_i];
-always @ (posedge CE1_i) 
-	if (WE1)
-		memory[A1_i] = I1_i;
-		
-
-always @ (data_out1 or OEB1_i)
-	if (!OEB1_i) 
-		O1_i = data_out1;
-	else
-		O1_i =  1'bz;
-
-//Dual ports	
-always @ (posedge CE2_i)
-  	if (RE2)
-		data_out2 = memory[A2_i];
-always @ (posedge CE2_i)
-	if (WE2)
-		memory[A2_i] = I2_i;
-		
-always @ (data_out2 or OEB2_i)
-	if (!OEB2_i) 
-		O2_i = data_out2;
-	else
-		O2_i = 1'bz;
-
-endmodule


Test patch:
diff --git a/src/hammer-vlsi/test.py b/src/hammer-vlsi/test.py
index 8c8cc889f..377a73f8e 100644
--- a/src/hammer-vlsi/test.py
+++ b/src/hammer-vlsi/test.py
@@ -1688,12 +1688,10 @@ def test_get_results(self) -> None:
           # Should have an sram for each corner(2) and parameter(2) for a total of 4
           self.assertEqual(len(output_libs),4)
           libs = list(map(lambda ex: ex.library, output_libs)) # type: List[Library]
-          lib_names = list(map(lambda lib: lib.nldm_liberty_file, libs)) # type: ignore # These are actually List[str]
-          self.assertEqual(set(lib_names), set([
-            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM2RW32x32_PVT_0P63V_100C.lib"),
-            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM2RW32x32_PVT_0P77V_0C.lib"),
-            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM1RW64x128_PVT_0P63V_100C.lib"),
-            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM1RW64x128_PVT_0P77V_0C.lib")]))
+          verilog_names = list(map(lambda lib: lib.verilog_sim, libs)) # type: ignore # These are actually List[str]
+          self.assertEqual(set(verilog_names), set([
+            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM2RW32x32.v"),
+            os.path.join(c.temp_dir, "tech-nop-cache", "SRAM1RW64x128.v")]))
 
 class HammerPCBDeliverableToolTestContext:
     def __init__(self, test: unittest.TestCase) -> None: